feat: PS配置AD9653,PL对AD9653数据进行解包
AD9653采集数据异常,需要进一步调试
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# sjl_2z7100_ad9528_2ad9361 - u4
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## Timing Assertions Section
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## Physical Constraints Section
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# Clocks
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set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 } [get_ports refclk_1_p ] ;# F2_REFCLK1_P
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set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS } [get_ports refclk_2_p ] ;# F2_REFCLK2_P
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set_property -dict {PACKAGE_PIN AD10 } [get_ports gtclk_109_p ] ;# F2_GTCLK0_P
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set_property -dict {PACKAGE_PIN AA8 } [get_ports gtclk_110_p ] ;# F2_GTCLK1_P
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# AD9528 Interface
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# set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_csn ] ;# AD9528_SPI_CSB
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# set_property -dict {PACKAGE_PIN AJ25 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_clk ] ;# AD9528_SPI_SCLK
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# set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_mosi ] ;# AD9528_SPI_SDI
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# set_property -dict {PACKAGE_PIN AK22 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_miso ] ;# AD9528_SPI_SDO
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# set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33} [get_ports ad9528_status[0] ] ;# AD9528_STATUS0
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# set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33} [get_ports ad9528_status[1] ] ;# AD9528_STATUS1
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# set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS33} [get_ports ad9528_reset_b ] ;# AD9528_RESETB
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# set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS33} [get_ports ad9528_sysref_req ] ;# AD9528_SYSREF_REQ
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# AD9653
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set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports ad9653_spi_csn ] ;# AD9653_CSB
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set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports ad9653_spi_clk ] ;# AD9653_SCLK
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set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS18} [get_ports ad9653_spi_sdio ] ;# AD9653_SDIO
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set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports ad9653_pdwn ] ;# AD9653_PDWN
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set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVDS } [get_ports ad9653_dco_p ] ;# AD9653_DCO_P
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set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVDS } [get_ports ad9653_fco_p ] ;# AD9653_FCO_P
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set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVDS } [get_ports ad9653_c_d0_p ] ;# AD9653_D0_C_P
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set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVDS } [get_ports ad9653_d_d0_p ] ;# AD9653_D0_D_P
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set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVDS } [get_ports ad9653_d_d1_p ] ;# AD9653_D1_D_P
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set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVDS } [get_ports ad9653_c_d1_p ] ;# AD9653_D1_C_P
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set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVDS } [get_ports ad9653_b_d0_p ] ;# AD9653_D0_B_P
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set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVDS } [get_ports ad9653_b_d1_p ] ;# AD9653_D1_B_P
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set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVDS } [get_ports ad9653_a_d1_p ] ;# AD9653_D1_A_P
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set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVDS } [get_ports ad9653_a_d0_p ] ;# AD9653_D0_A_P
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# Inter-FPGA Ports
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set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[0] ] ;# LVDS_IO_GRP0_00P
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set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[1] ] ;# LVDS_IO_GRP0_01P
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set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[2] ] ;# LVDS_IO_GRP0_02P
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set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[3] ] ;# LVDS_IO_GRP0_03P
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set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[4] ] ;# LVDS_IO_GRP0_04P
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set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[5] ] ;# LVDS_IO_GRP0_05P
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set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[6] ] ;# LVDS_IO_GRP0_06P
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set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[7] ] ;# LVDS_IO_GRP0_07P
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set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[8] ] ;# LVDS_IO_GRP0_08P
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set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[9] ] ;# LVDS_IO_GRP0_09P
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set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[10] ] ;# LVDS_IO_GRP0_10P
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set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[11] ] ;# LVDS_IO_GRP0_11P
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set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[12] ] ;# LVDS_IO_GRP0_12P
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set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[13] ] ;# LVDS_IO_GRP0_13P
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set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[14] ] ;# LVDS_IO_GRP0_14P
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set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[15] ] ;# LVDS_IO_GRP0_15P
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set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[16] ] ;# LVDS_IO_GRP0_16P
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set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[17] ] ;# LVDS_IO_GRP0_17P
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set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[18] ] ;# LVDS_IO_GRP0_18P
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set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[19] ] ;# LVDS_IO_GRP0_19P
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set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[20] ] ;# LVDS_IO_GRP0_20P
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set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[21] ] ;# LVDS_IO_GRP0_21P
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set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[22] ] ;# LVDS_IO_GRP0_22P
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set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[0] ] ;# LVDS_IO_GRP1_00P
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set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[1] ] ;# LVDS_IO_GRP1_01P
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set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[2] ] ;# LVDS_IO_GRP1_02P
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set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[3] ] ;# LVDS_IO_GRP1_03P
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set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[4] ] ;# LVDS_IO_GRP1_04P
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set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[5] ] ;# LVDS_IO_GRP1_05P
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set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[6] ] ;# LVDS_IO_GRP1_06P
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set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[7] ] ;# LVDS_IO_GRP1_07P
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set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[8] ] ;# LVDS_IO_GRP1_08P
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set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[9] ] ;# LVDS_IO_GRP1_09P
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set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[10] ] ;# LVDS_IO_GRP1_10P
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set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[11] ] ;# LVDS_IO_GRP1_11P
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set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[12] ] ;# LVDS_IO_GRP1_12P
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set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[13] ] ;# LVDS_IO_GRP1_13P
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set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[14] ] ;# LVDS_IO_GRP1_14P
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set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[15] ] ;# LVDS_IO_GRP1_15P
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set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[16] ] ;# LVDS_IO_GRP1_16P
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set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[17] ] ;# LVDS_IO_GRP1_17P
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set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[18] ] ;# LVDS_IO_GRP1_18P
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set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[19] ] ;# LVDS_IO_GRP1_19P
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set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[20] ] ;# LVDS_IO_GRP1_20P
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set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[21] ] ;# LVDS_IO_GRP1_21P
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set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[22] ] ;# LVDS_IO_GRP1_22P
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set_property -dict {PACKAGE_PIN AH10 } [get_ports if_gtx_rxp[0] ] ;# GTX_F1T_F2R_00P
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set_property -dict {PACKAGE_PIN AJ8 } [get_ports if_gtx_rxp[1] ] ;# GTX_F1T_F2R_01P
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set_property -dict {PACKAGE_PIN AG8 } [get_ports if_gtx_rxp[2] ] ;# GTX_F1T_F2R_02P
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set_property -dict {PACKAGE_PIN AE8 } [get_ports if_gtx_rxp[3] ] ;# GTX_F1T_F2R_03P
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set_property -dict {PACKAGE_PIN AH6 } [get_ports if_gtx_rxp[4] ] ;# GTX_F1T_F2R_04P
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set_property -dict {PACKAGE_PIN AG4 } [get_ports if_gtx_rxp[5] ] ;# GTX_F1T_F2R_05P
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set_property -dict {PACKAGE_PIN AF6 } [get_ports if_gtx_rxp[6] ] ;# GTX_F1T_F2R_06P
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set_property -dict {PACKAGE_PIN AD6 } [get_ports if_gtx_rxp[7] ] ;# GTX_F1T_F2R_07P
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# set_property -dict {PACKAGE_PIN AK10 } [get_ports if_gtx_txp[0] ] ;# GTX_F1R_F2T_00P
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# set_property -dict {PACKAGE_PIN AK6 } [get_ports if_gtx_txp[1] ] ;# GTX_F1R_F2T_01P
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# set_property -dict {PACKAGE_PIN AJ4 } [get_ports if_gtx_txp[2] ] ;# GTX_F1R_F2T_02P
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# set_property -dict {PACKAGE_PIN AK2 } [get_ports if_gtx_txp[3] ] ;# GTX_F1R_F2T_03P
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# set_property -dict {PACKAGE_PIN AH2 } [get_ports if_gtx_txp[4] ] ;# GTX_F1R_F2T_04P
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# set_property -dict {PACKAGE_PIN AF2 } [get_ports if_gtx_txp[5] ] ;# GTX_F1R_F2T_05P
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# set_property -dict {PACKAGE_PIN AE4 } [get_ports if_gtx_txp[6] ] ;# GTX_F1R_F2T_06P
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# set_property -dict {PACKAGE_PIN AD2 } [get_ports if_gtx_txp[7] ] ;# GTX_F1R_F2T_07P
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# PS PJTAG
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set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS33} [get_ports pjtag_tdi ] ;# PS2_TDI
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set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS33} [get_ports pjtag_tms ] ;# PS2_TMS
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set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS33} [get_ports pjtag_tck ] ;# PS2_TCK
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set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS33} [get_ports pjtag_tdo ] ;# PS2_TDO
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# 3.3V Debug IO
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set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports uart_rxd ] ;# PL2_UART_RXD
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set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports uart_txd ] ;# PL2_UART_TXD
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set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# PL2_DEBUG_IO_1
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set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# PL2_DEBUG_IO_2
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set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# PL2_DEBUG_IO_3
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set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# PL2_DEBUG_IO_4
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set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# PL2_DEBUG_IO_5
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