feat: PS配置AD9653,PL对AD9653数据进行解包
AD9653采集数据异常,需要进一步调试
This commit is contained in:
@@ -0,0 +1,243 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2024/10/09 21:26:30
|
||||
// Design Name:
|
||||
// Module Name: ad9653_rx_map_lvds_dual
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ad9653_map_default_ddr
|
||||
(
|
||||
input ad9653_clk_in ,
|
||||
input clk_in_rst ,
|
||||
|
||||
input rx_data_clk ,
|
||||
input rx_data_clk_rst ,
|
||||
|
||||
input rx_fifo_rst ,
|
||||
|
||||
/* input rx_frame_p ,
|
||||
input rx_frame_n ,
|
||||
input rx_data_p ,
|
||||
input rx_data_n , */
|
||||
|
||||
input AD9653_D0_A_P,
|
||||
input AD9653_D0_A_N,
|
||||
input AD9653_D1_A_P,
|
||||
input AD9653_D1_A_N,
|
||||
|
||||
input fco,
|
||||
input fco_pos,
|
||||
input fco_neg,
|
||||
|
||||
// input FCO_P,
|
||||
// input FCO_N,
|
||||
|
||||
|
||||
/* output [11:0] rx_ch1_i ,
|
||||
output [11:0] rx_ch1_q ,
|
||||
output [11:0] rx_ch2_i , */
|
||||
output [15:0] rx_data_9653_out
|
||||
);
|
||||
|
||||
wire rx_frame;
|
||||
wire rx_frame_p;
|
||||
wire rx_frame_n;
|
||||
|
||||
wire rx_data_p;
|
||||
wire rx_data_n;
|
||||
|
||||
assign rx_frame = fco;
|
||||
|
||||
// IBUFDS #(
|
||||
// .DIFF_TERM ("TRUE" ) // Differential Termination
|
||||
// ) u_rx_FCO_ibufds
|
||||
// (
|
||||
// .I (FCO_P ), // Diff_p buffer input (connect directly to top-level port)
|
||||
// .IB (FCO_N ), // Diff_n buffer input (connect directly to top-level port)
|
||||
// .O (rx_frame ) // Buffer output
|
||||
// );
|
||||
|
||||
// assign rx_frame_p = FCO_P;
|
||||
// assign rx_frame_n = FCO_N;
|
||||
|
||||
IBUFDS #(
|
||||
.DIFF_TERM ("TRUE" ) // Differential Termination
|
||||
) u_rx_D0_A_ibufds
|
||||
(
|
||||
.I (AD9653_D0_A_P ), // Diff_p buffer input (connect directly to top-level port)
|
||||
.IB (AD9653_D0_A_N ), // Diff_n buffer input (connect directly to top-level port)
|
||||
.O (rx_data_p ) // Buffer output
|
||||
);
|
||||
|
||||
IBUFDS #(
|
||||
.DIFF_TERM ("TRUE" ) // Differential Termination
|
||||
) u_rx_D1_A_ibufds
|
||||
(
|
||||
.I (AD9653_D1_A_P ), // Diff_p buffer input (connect directly to top-level port)
|
||||
.IB (AD9653_D1_A_N ), // Diff_n buffer input (connect directly to top-level port)
|
||||
.O (rx_data_n ) // Buffer output
|
||||
);
|
||||
// rx frame from port
|
||||
|
||||
wire rx_frame_pos;
|
||||
wire rx_frame_neg;
|
||||
|
||||
assign rx_frame_pos = fco_pos;
|
||||
assign rx_frame_neg = fco_neg;
|
||||
|
||||
/* IBUFDS #(
|
||||
.DIFF_TERM ("TRUE" ) // Differential Termination
|
||||
) u_rx_frame_ibufds
|
||||
(
|
||||
.I (rx_frame_p ), // Diff_p buffer input (connect directly to top-level port)
|
||||
.IB (rx_frame_n ), // Diff_n buffer input (connect directly to top-level port)
|
||||
.O (rx_frame ) // Buffer output
|
||||
); */
|
||||
|
||||
// IDDR #(
|
||||
// .DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
|
||||
// .INIT_Q1 (1'b0 ), // Initial value of Q1: 1'b0 or 1'b1
|
||||
// .INIT_Q2 (1'b0 ), // Initial value of Q2: 1'b0 or 1'b1
|
||||
// .SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
|
||||
// ) i_rx_frame_iddr (
|
||||
// .CE (1'b1 ), // 1-bit clock enable input
|
||||
// .R (1'b0 ), // 1-bit reset
|
||||
// .S (1'b0 ), // 1-bit set
|
||||
// .C (ad9653_clk_in ), // 1-bit clock input
|
||||
// .D (rx_frame ), // 1-bit DDR data input
|
||||
// .Q1 (rx_frame_pos ), // 1-bit output for positive edge of clock
|
||||
// .Q2 (rx_frame_neg ) // 1-bit output for negative edge of clock
|
||||
// );
|
||||
|
||||
reg [2:0] rx_frame_pos_cnt;
|
||||
always @(posedge ad9653_clk_in) begin
|
||||
if (clk_in_rst) begin
|
||||
rx_frame_pos_cnt <= 'b0;
|
||||
end
|
||||
else if(~rx_frame_pos&rx_frame===1) begin
|
||||
rx_frame_pos_cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
rx_frame_pos_cnt <= rx_frame_pos_cnt +1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
reg rx_fifo_wr_en = 'b0;
|
||||
reg rx_fifo_rd_en = 'b0;
|
||||
reg [15:0] rx_data_9653 = 'b0;
|
||||
|
||||
always @(posedge ad9653_clk_in) begin
|
||||
if (clk_in_rst) begin
|
||||
rx_data_9653 <= 16'b0;
|
||||
rx_fifo_wr_en <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (rx_frame_pos_cnt)
|
||||
3'd7: begin
|
||||
rx_data_9653[14] <= rx_data_p;
|
||||
rx_data_9653[15] <= rx_data_n;
|
||||
rx_fifo_wr_en <= 'b0;
|
||||
end
|
||||
3'd0: begin
|
||||
rx_data_9653[12] <= rx_data_p;
|
||||
rx_data_9653[13] <= rx_data_n;
|
||||
rx_fifo_wr_en <= 'b0;
|
||||
end
|
||||
3'd1:begin
|
||||
rx_data_9653[10] <= rx_data_p;
|
||||
rx_data_9653[11] <= rx_data_n;
|
||||
rx_fifo_wr_en <= 'b0;
|
||||
end
|
||||
3'd2:begin
|
||||
rx_data_9653[8] <= rx_data_p;
|
||||
rx_data_9653[9] <= rx_data_n;
|
||||
rx_fifo_wr_en <= 'b0;
|
||||
end
|
||||
3'd3:begin
|
||||
rx_data_9653[6] <= rx_data_p;
|
||||
rx_data_9653[7] <= rx_data_n;
|
||||
rx_fifo_wr_en <= 'b0;
|
||||
end
|
||||
3'd4:begin
|
||||
rx_data_9653[4] <= rx_data_p;
|
||||
rx_data_9653[5] <= rx_data_n;
|
||||
rx_fifo_wr_en <= 'b0;
|
||||
end
|
||||
3'd5:begin
|
||||
rx_data_9653[2] <= rx_data_p;
|
||||
rx_data_9653[3] <= rx_data_n;
|
||||
rx_fifo_wr_en <= 'b0;
|
||||
end
|
||||
3'd6:begin
|
||||
rx_data_9653[0] <= rx_data_p;
|
||||
rx_data_9653[1] <= rx_data_n;
|
||||
rx_fifo_wr_en <= 'b1;
|
||||
end
|
||||
|
||||
default: begin
|
||||
rx_data_9653[15:0] <= rx_data_9653[15:0];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
//---------------------------/////////////////////////
|
||||
reg [15:0] rx_data_9653_out_reg='b0;
|
||||
always @(posedge ad9653_clk_in) begin
|
||||
if (clk_in_rst) begin
|
||||
rx_data_9653_out_reg <= 'b0;
|
||||
|
||||
end
|
||||
else if(rx_frame_pos_cnt==3'd7)begin
|
||||
rx_data_9653_out_reg[15:0] <= rx_data_9653[15:0];
|
||||
end
|
||||
else begin
|
||||
rx_data_9653_out_reg[15:0] <= rx_data_9653_out_reg[15:0];
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
|
||||
wire [15:0] rx_fifo_data_9653_out;
|
||||
assign rx_fifo_data_9653_out[15:0] = rx_data_9653_out_reg[15:0];
|
||||
|
||||
wire rx_fifo_empty;
|
||||
always @(posedge rx_data_clk) begin
|
||||
if (rx_data_clk_rst) begin
|
||||
rx_fifo_rd_en <= 'b0;
|
||||
end
|
||||
else begin
|
||||
rx_fifo_rd_en <= ~rx_fifo_empty;
|
||||
end
|
||||
end
|
||||
|
||||
ad9653_fifo u_rx_fifo_9653
|
||||
(
|
||||
.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
|
||||
.wr_clk (ad9653_clk_in ), // input wire wr_clk
|
||||
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||
.din (rx_fifo_data_9653_out[15:0] ), // input wire [11 : 0] din
|
||||
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (rx_data_9653_out[15:0] ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty ( rx_fifo_empty ) // output wire empty
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,404 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 09/09/2024 07:16:39 PM
|
||||
// Design Name:
|
||||
// Module Name: system_top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module system_top
|
||||
(
|
||||
/***************************************************************************
|
||||
* Contents
|
||||
* 01. Clocks
|
||||
* 02. AD9528 Interface
|
||||
* 03. AD9361-1 Interface
|
||||
* 04. AD9361-2 Interface
|
||||
* 05. Inter-FPGA Ports
|
||||
* 06. Inter-board Ports
|
||||
* 07. 3.3V Debug IO
|
||||
* 08. DDR and Fixed-io (Do NOT Modify)
|
||||
**************************************************************************/
|
||||
|
||||
// *************************************************************************
|
||||
// ******************************** Clocks *********************************
|
||||
// *************************************************************************
|
||||
// ad9528 clock
|
||||
input refclk_1_p , // 200MHz
|
||||
input refclk_1_n ,
|
||||
input refclk_2_p , // 200MHz
|
||||
input refclk_2_n ,
|
||||
input gtclk_109_p , // 200MHz
|
||||
input gtclk_109_n ,
|
||||
input gtclk_110_p , // 200MHz
|
||||
input gtclk_110_n ,
|
||||
// *************************************************************************
|
||||
// *************************** AD9653 Interface ****************************
|
||||
// *************************************************************************
|
||||
// spi interface
|
||||
output ad9653_spi_clk ,
|
||||
output ad9653_spi_csn ,
|
||||
inout ad9653_spi_sdio ,
|
||||
output ad9653_pdwn ,
|
||||
// data interface
|
||||
input ad9653_dco_p ,
|
||||
input ad9653_dco_n ,
|
||||
input ad9653_fco_p ,
|
||||
input ad9653_fco_n ,
|
||||
input ad9653_a_d0_p ,
|
||||
input ad9653_a_d0_n ,
|
||||
input ad9653_a_d1_p ,
|
||||
input ad9653_a_d1_n ,
|
||||
input ad9653_b_d0_p ,
|
||||
input ad9653_b_d0_n ,
|
||||
input ad9653_b_d1_p ,
|
||||
input ad9653_b_d1_n ,
|
||||
input ad9653_c_d0_p ,
|
||||
input ad9653_c_d0_n ,
|
||||
input ad9653_c_d1_p ,
|
||||
input ad9653_c_d1_n ,
|
||||
input ad9653_d_d0_p ,
|
||||
input ad9653_d_d0_n ,
|
||||
input ad9653_d_d1_p ,
|
||||
input ad9653_d_d1_n ,
|
||||
// *************************************************************************
|
||||
// *************************** Inter-FPGA Ports ****************************
|
||||
// *************************************************************************
|
||||
// low speed
|
||||
inout [22:0] if_lvds_io_1_p ,
|
||||
inout [22:0] if_lvds_io_1_n ,
|
||||
inout [22:0] if_lvds_io_2_p ,
|
||||
inout [22:0] if_lvds_io_2_n ,
|
||||
// high speed
|
||||
input [ 7:0] if_gtx_rxp ,
|
||||
input [ 7:0] if_gtx_rxn ,
|
||||
// output [ 7:0] if_gtx_txp ,
|
||||
// output [ 7:0] if_gtx_txn ,
|
||||
// *************************************************************************
|
||||
// ****************************** PS PJTAG *******************************
|
||||
// *************************************************************************
|
||||
input pjtag_tdi ,
|
||||
input pjtag_tms ,
|
||||
input pjtag_tck ,
|
||||
output pjtag_tdo ,
|
||||
// *************************************************************************
|
||||
// ***************************** 3.3V Debug IO *****************************
|
||||
// *************************************************************************
|
||||
// uart
|
||||
input uart_rxd ,
|
||||
output uart_txd ,
|
||||
// gpio
|
||||
inout debug_io_1 ,
|
||||
inout debug_io_2 ,
|
||||
inout debug_io_3 ,
|
||||
inout debug_io_4 ,
|
||||
inout debug_io_5 ,
|
||||
// *************************************************************************
|
||||
// ******************* DDR and Fixed-io (Do NOT Modify) ********************
|
||||
// *************************************************************************
|
||||
// ddr
|
||||
inout [14:0] ddr_addr ,
|
||||
inout [ 2:0] ddr_ba ,
|
||||
inout ddr_cas_n ,
|
||||
inout ddr_ck_n ,
|
||||
inout ddr_ck_p ,
|
||||
inout ddr_cke ,
|
||||
inout ddr_cs_n ,
|
||||
inout [ 3:0] ddr_dm ,
|
||||
inout [31:0] ddr_dq ,
|
||||
inout [ 3:0] ddr_dqs_n ,
|
||||
inout [ 3:0] ddr_dqs_p ,
|
||||
inout ddr_odt ,
|
||||
inout ddr_ras_n ,
|
||||
inout ddr_reset_n ,
|
||||
inout ddr_we_n ,
|
||||
// fixed-io
|
||||
inout fixed_io_ddr_vrn ,
|
||||
inout fixed_io_ddr_vrp ,
|
||||
inout [53:0] fixed_io_mio ,
|
||||
inout fixed_io_ps_clk ,
|
||||
inout fixed_io_ps_porb ,
|
||||
inout fixed_io_ps_srstb ,
|
||||
// system monitor
|
||||
input sysmon_vp ,
|
||||
input sysmon_vn
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////// System Clock Generation ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
wire sys_clk ; // 125 MHz
|
||||
wire sys_clk_2x; // 250 MHz
|
||||
wire sys_clk_4x; // 500 MHz
|
||||
wire sys_rstn ;
|
||||
|
||||
sys_clk_gen u_sys_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (sys_clk ), // output clk_out1
|
||||
.clk_out2 (sys_clk_2x ), // output clk_out2
|
||||
.clk_out3 (sys_clk_4x ), // output clk_out3
|
||||
// Status and control signals
|
||||
.locked (sys_rstn ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1_p (ad9653_dco_p ), // input clk_in1_p
|
||||
.clk_in1_n (ad9653_dco_n ) // input clk_in1_n
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////// Block Design Interface ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// gpio
|
||||
wire [47:0] gpio_i;
|
||||
wire [47:0] gpio_o;
|
||||
wire [47:0] gpio_t;
|
||||
|
||||
assign gpio_i[47:1] = gpio_o[47:1];
|
||||
|
||||
// ad9653
|
||||
assign ad9653_pdwn = gpio_o[0]; // ad9653 active-high power down
|
||||
|
||||
// spi interface
|
||||
wire spi_sclk ;
|
||||
wire [ 3:0] spi_cs ;
|
||||
wire spi_sdi ;
|
||||
wire spi_sdo ;
|
||||
wire spi_sdo_t ;
|
||||
wire spi_three_wire;
|
||||
wire spi_active ;
|
||||
|
||||
// ad9653 - three-wire spi
|
||||
assign ad9653_spi_clk = spi_sclk;
|
||||
assign ad9653_spi_csn = spi_cs[3];
|
||||
assign ad9653_spi_sdio = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
assign spi_sdi = ad9653_spi_sdio;
|
||||
|
||||
// ps clock
|
||||
wire ps_clk_50m;
|
||||
wire ps_clk_100m;
|
||||
wire ps_clk_rstn;
|
||||
|
||||
system_bd_wrapper system_bd
|
||||
(
|
||||
// ddr
|
||||
.ddr_addr (ddr_addr ), // inout [14:0]ddr_addr
|
||||
.ddr_ba (ddr_ba ), // inout [2:0]ddr_ba
|
||||
.ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n
|
||||
.ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n
|
||||
.ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p
|
||||
.ddr_cke (ddr_cke ), // inout ddr_cke
|
||||
.ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n
|
||||
.ddr_dm (ddr_dm ), // inout [3:0]ddr_dm
|
||||
.ddr_dq (ddr_dq ), // inout [31:0]ddr_dq
|
||||
.ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n
|
||||
.ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p
|
||||
.ddr_odt (ddr_odt ), // inout ddr_odt
|
||||
.ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n
|
||||
.ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n
|
||||
.ddr_we_n (ddr_we_n ), // inout ddr_we_n
|
||||
|
||||
// fixed-io
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp
|
||||
.fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb
|
||||
|
||||
// system monitor
|
||||
.vp_vn_v_p (sysmon_vp ), // input vp_vn_v_p
|
||||
.vp_vn_v_n (sysmon_vn ), // input vp_vn_v_n
|
||||
|
||||
// pjtag
|
||||
.pjtag_tck (pjtag_tck ), // input pjtag_tck
|
||||
.pjtag_tdi (pjtag_tdi ), // input pjtag_tdi
|
||||
.pjtag_tdo (pjtag_tdo ), // output pjtag_tdo
|
||||
.pjtag_tms (pjtag_tms ), // input pjtag_tms
|
||||
|
||||
// gpio, for control signals
|
||||
.gpio_i (gpio_i ), // input [47:0]gpio_i
|
||||
.gpio_o (gpio_o ), // output [47:0]gpio_o
|
||||
.gpio_t (gpio_t ), // output [47:0]gpio_t
|
||||
|
||||
// spi interface
|
||||
.spi_sclk (spi_sclk ), // output spi_sclk
|
||||
.spi_cs (spi_cs ), // output [3:0]spi_cs
|
||||
.spi_sdi (spi_sdi ), // input [0:0]spi_sdi
|
||||
.spi_sdo (spi_sdo ), // output spi_sdo
|
||||
.spi_sdo_t (spi_sdo_t ), // output spi_sdo_t
|
||||
.spi_three_wire (spi_three_wire ), // output spi_three_wire
|
||||
.spi_active (spi_active ), // output spi_active
|
||||
|
||||
// ps clock
|
||||
.ps_clk_50m (ps_clk_50m ), // output ps_clk_50m
|
||||
.ps_clk_100m (ps_clk_100m ) // output ps_clk_100m
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Rx Signals //////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
wire ad9653_fco;
|
||||
wire ad9653_fco_pos;
|
||||
wire ad9653_fco_neg;
|
||||
wire [15:0] rx_ch1;
|
||||
wire [15:0] rx_ch2;
|
||||
wire [15:0] rx_ch3;
|
||||
wire [15:0] rx_ch4;
|
||||
|
||||
IBUFDS #(
|
||||
.DIFF_TERM ("TRUE" ) // Differential Termination
|
||||
) u_ad9653_fco_ibufds
|
||||
(
|
||||
.I (ad9653_fco_p ), // Diff_p buffer input (connect directly to top-level port)
|
||||
.IB (ad9653_fco_n ), // Diff_n buffer input (connect directly to top-level port)
|
||||
.O (ad9653_fco ) // Buffer output
|
||||
);
|
||||
|
||||
IDDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
|
||||
.INIT_Q1 (1'b0 ), // Initial value of Q1: 1'b0 or 1'b1
|
||||
.INIT_Q2 (1'b0 ), // Initial value of Q2: 1'b0 or 1'b1
|
||||
.SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
|
||||
) i_rx_frame_iddr (
|
||||
.CE (1'b1 ), // 1-bit clock enable input
|
||||
.R (1'b0 ), // 1-bit reset
|
||||
.S (1'b0 ), // 1-bit set
|
||||
.C (sys_clk_4x ), // 1-bit clock input
|
||||
.D (ad9653_fco ), // 1-bit DDR data input
|
||||
.Q1 (ad9653_fco_pos ), // 1-bit output for positive edge of clock
|
||||
.Q2 (ad9653_fco_neg ) // 1-bit output for negative edge of clock
|
||||
);
|
||||
|
||||
ad9653_map_default_ddr u_ad9653_rx_ch1_map
|
||||
(
|
||||
.ad9653_clk_in (sys_clk_4x ),
|
||||
.clk_in_rst (~sys_rstn ),
|
||||
|
||||
.rx_data_clk (sys_clk ),
|
||||
.rx_data_clk_rst (~sys_rstn ),
|
||||
|
||||
.rx_fifo_rst (1'b0 ),
|
||||
|
||||
.AD9653_D0_A_P (ad9653_a_d0_p ),
|
||||
.AD9653_D0_A_N (ad9653_a_d0_n ),
|
||||
.AD9653_D1_A_P (ad9653_a_d1_p ),
|
||||
.AD9653_D1_A_N (ad9653_a_d1_n ),
|
||||
|
||||
.fco (ad9653_fco ),
|
||||
.fco_pos (ad9653_fco_pos ),
|
||||
.fco_neg (ad9653_fco_neg ),
|
||||
|
||||
.rx_data_9653_out (rx_ch1 )
|
||||
);
|
||||
|
||||
ad9653_map_default_ddr u_ad9653_rx_ch2_map
|
||||
(
|
||||
.ad9653_clk_in (sys_clk_4x ),
|
||||
.clk_in_rst (~sys_rstn ),
|
||||
|
||||
.rx_data_clk (sys_clk ),
|
||||
.rx_data_clk_rst (~sys_rstn ),
|
||||
|
||||
.rx_fifo_rst (1'b0 ),
|
||||
|
||||
.AD9653_D0_A_P (ad9653_b_d0_p ),
|
||||
.AD9653_D0_A_N (ad9653_b_d0_n ),
|
||||
.AD9653_D1_A_P (ad9653_b_d1_p ),
|
||||
.AD9653_D1_A_N (ad9653_b_d1_n ),
|
||||
|
||||
.fco (ad9653_fco ),
|
||||
.fco_pos (ad9653_fco_pos ),
|
||||
.fco_neg (ad9653_fco_neg ),
|
||||
|
||||
.rx_data_9653_out (rx_ch2 )
|
||||
);
|
||||
|
||||
ad9653_map_default_ddr u_ad9653_rx_ch3_map
|
||||
(
|
||||
.ad9653_clk_in (sys_clk_4x ),
|
||||
.clk_in_rst (~sys_rstn ),
|
||||
|
||||
.rx_data_clk (sys_clk ),
|
||||
.rx_data_clk_rst (~sys_rstn ),
|
||||
|
||||
.rx_fifo_rst (1'b0 ),
|
||||
|
||||
.AD9653_D0_A_P (ad9653_c_d0_p ),
|
||||
.AD9653_D0_A_N (ad9653_c_d0_n ),
|
||||
.AD9653_D1_A_P (ad9653_c_d1_p ),
|
||||
.AD9653_D1_A_N (ad9653_c_d1_n ),
|
||||
|
||||
.fco (ad9653_fco ),
|
||||
.fco_pos (ad9653_fco_pos ),
|
||||
.fco_neg (ad9653_fco_neg ),
|
||||
|
||||
.rx_data_9653_out (rx_ch3 )
|
||||
);
|
||||
|
||||
ad9653_map_default_ddr u_ad9653_rx_ch4_map
|
||||
(
|
||||
.ad9653_clk_in (sys_clk_4x ),
|
||||
.clk_in_rst (~sys_rstn ),
|
||||
|
||||
.rx_data_clk (sys_clk ),
|
||||
.rx_data_clk_rst (~sys_rstn ),
|
||||
|
||||
.rx_fifo_rst (1'b0 ),
|
||||
|
||||
.AD9653_D0_A_P (ad9653_d_d0_p ),
|
||||
.AD9653_D0_A_N (ad9653_d_d0_n ),
|
||||
.AD9653_D1_A_P (ad9653_d_d1_p ),
|
||||
.AD9653_D1_A_N (ad9653_d_d1_n ),
|
||||
|
||||
.fco (ad9653_fco ),
|
||||
.fco_pos (ad9653_fco_pos ),
|
||||
.fco_neg (ad9653_fco_neg ),
|
||||
|
||||
.rx_data_9653_out (rx_ch4 )
|
||||
);
|
||||
// <--------------------------------------------------------------------------->
|
||||
// <----------------------- insert receiver logic below ----------------------->
|
||||
// <--------------------------------------------------------------------------->
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////// ILAs and VIOs /////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
ila_rx u_ila_rx
|
||||
(
|
||||
.clk (sys_clk), // input wire clk
|
||||
.probe0 (rx_ch1 ), // input wire [15:0] probe0
|
||||
.probe1 (rx_ch2 ), // input wire [15:0] probe1
|
||||
.probe2 (rx_ch3 ), // input wire [15:0] probe2
|
||||
.probe3 (rx_ch4 ) // input wire [15:0] probe3
|
||||
);
|
||||
|
||||
// ila_ad9653 u_ila_ad9653
|
||||
// (
|
||||
// .clk (sys_clk_4x ), // input wire clk
|
||||
// .probe0 (u_ad9653_rx_ch1_map.rx_data_p ), // input wire [0:0] probe0
|
||||
// .probe1 (u_ad9653_rx_ch1_map.rx_data_n ), // input wire [0:0] probe1
|
||||
// .probe2 (ad9653_fco_pos ), // input wire [0:0] probe2
|
||||
// .probe3 (ad9653_fco_neg ), // input wire [0:0] probe3
|
||||
// .probe4 (u_ad9653_rx_ch1_map.rx_frame_pos_cnt ), // input wire [2:0] probe4
|
||||
// .probe5 (u_ad9653_rx_ch1_map.rx_fifo_wr_en ), // input wire [0:0] probe5
|
||||
// .probe6 (u_ad9653_rx_ch1_map.rx_fifo_data_9653_out ) // input wire [0:0] probe6
|
||||
// );
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user