/*****************************************************************************/
/**
 * Description: hwconfig.h
 *

 * Date: 2024-02-20 13:19
 * Last Edit Time: [2024-02-20 13:19]
 *
 * Revisions: Rev 0.0
 * History:
 * [2023-05-07]: Initial edition.
 *
 * Copyright(c) 2024 Beijing Institute of Technology.
 *
 ******************************************************************************/

/***************************** Include Files *********************************/
// Standard
#include <stdint.h>
#include <stdbool.h>
// Xilinx
#include "xgpiops.h"
#include "drivers/axi_core/spi_engine/spi_engine.h"
// App
#include "common.h"
#include "error.h"
#include "delay.h"
#include "system_monitor.h"
#include "hwconfig.h"
#include "config/app_config.h"
#include "dev_profile/dev_profile.h"
#ifdef RFSOC
#include "xrfdc.h"
#endif

/************************** Function Prototypes ******************************/
/*********************** Driver Instance Definitions **************************/
static struct hmc7044_dev *hmc7044_inst;
ad9528Device_t *ad9528_inst;
static struct lmk04828_dev *lmk04828_inst;
static struct lmx2594_dev *lmx2594_adc_inst;
static struct lmx2594_dev *lmx2594_dac_inst;
static struct ad9361_reg_dev *ad9361_1_reg_inst;
static struct ad9361_reg_dev *ad9361_2_reg_inst;
static struct ad9361_rf_phy *ad9361_phy;
static struct ad9653_dev *ad9653_inst;
static struct ad9694_dev *ad9694_inst;

XGpioPs Gpio;
#ifdef RFSOC
XRFdc	RFdc;
#endif

/*****************************************************************************/
/**
 * @brief   Hardware_Init
 *
 * @param   none.
 *
 * @return  None.
 *
 ******************************************************************************/
int32_t Hardware_Init(void)
{
	int32_t Status;

	// gpio initialization
	XGpioPs_Config *ConfigPtr;
	ConfigPtr = XGpioPs_LookupConfig(AD9361_GPIO_DEVICE_ID);
	Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
	if (Status != SUCCESS)
	{
		return FAILURE;
	}

#ifdef RFSOC
	/**********************************************************/
	/************* RF Data Converter Configuration ************/
	/**********************************************************/
	// rf data converter initialization
	XRFdc_Config *RFdc_ConfigPtr;
	RFdc_ConfigPtr = XRFdc_LookupConfig(RFDC_DEVICE_ID);
	Status = XRFdc_CfgInitialize(&RFdc, RFdc_ConfigPtr);
	if (Status != XST_SUCCESS)
	{
		return XST_FAILURE;
	}
	mdelay(100);
#endif

#ifdef HMC7044
	/**********************************************************/
	/****************** HMC7044 Configuration *****************/
	/**********************************************************/
	Status = hmc7044_init(&hmc7044_inst, &hmc7044_default_init_param);
	if (Status != SUCCESS)
	{
		DBG_ERROR("HDWR: hmc7044_init() error: %" PRId32 "\n", Status);
		return FAILURE;
	}
#endif

#ifdef AD9528
	/**********************************************************/
	/****************** AD9528 Configuration ******************/
	/**********************************************************/
	Status = AD9528_init(&ad9528_inst, &ad9528_default_init_param);
	if (Status != SUCCESS) {
		DBG_ERROR("HDWR: AD9528_init() error: %" PRId32 "\n", Status);
		return FAILURE;
	}

	Status = AD9528_config(ad9528_inst);
	if (Status != SUCCESS) {
		return FAILURE;
		DBG_ERROR("HDWR: AD9528_config() error: %" PRId32 "\n", Status);
	}
#endif

#ifdef LMK04828
	/**********************************************************/
	/***************** LMK04828 Configuration *****************/
	/**********************************************************/
	Status = lmk04828_init(&lmk04828_inst, &lmk04828_default_init_param);
	for(int i = 0; i < lmk04828_default_config_len; i++)
	{
		Status = lmk04828_write(lmk04828_inst,
				lmk04828_default_config[i].addr, lmk04828_default_config[i].value);
		if (lmk04828_default_config[i].addr == 0x0000)
		{
			mdelay(500);
		}
	}

	uint8_t Lmk04828Read;

	// check pll1 lock status
	Status = lmk04828_read(lmk04828_inst, 0x0182, &Lmk04828Read);
	if ((Lmk04828Read & 0x02) == 0x02) {
		DBG_INFO("HDWR: [LMK04828] PLL1 Locked.\r\n");
	}
	else {
		DBG_ERROR("HDWR: [LMK04828] PLL1 NOT lock. It takes a while "
				"for PLL1 to lock. Lock status is shown on LED.\r\n");
	}

	// check pll2 lock status
	Status = lmk04828_read(lmk04828_inst, 0x0183, &Lmk04828Read);
	if ((Lmk04828Read & 0x02) == 0x02) {
		DBG_INFO("HDWR: [LMK04828] PLL2 Locked.\r\n");
	}
	else {
		DBG_INFO("HDWR: [LMK04828] PLL2 NOT lock!\r\n");
	}
#endif

#ifdef LMX2594_ADC
	/**********************************************************/
	/************* LMX2594 for ADC Configuration **************/
	/**********************************************************/
	Status = lmx2594_init(&lmx2594_adc_inst, &lmx2594_adc_init_param);
	for(int i = 0; i < lmx2594_default_config_len; i++)
	{
		Status = lmx2594_write(lmx2594_adc_inst,
				lmx2594_default_config[i].addr, lmx2594_default_config[i].value);
		if (lmx2594_default_config[i].addr == 0)
		{
			mdelay(500);
		}
	}

	uint16_t Lmx2594AdcRead;

	// check vco lock status
	Status = lmx2594_read(lmx2594_adc_inst, 110, &Lmx2594AdcRead);
	if (((Lmx2594AdcRead >> 9) & 0x0003) == 0x0002) {
		DBG_INFO("HDWR: [ADC LMX2594] Config Done.\r\n");
	}
	else {
		DBG_INFO("HDWR: [ADC LMX2594] not lock!\r\n");
	}

	// set mux out to lock status
	Status = lmx2594_write(lmx2594_adc_inst, 0x00, 0x259C);
	DBG_INFO("HDWR: [ADC LMX2594] SPI readback disabled, "
			"lock status is shown on LED.\r\n");
#endif

#ifdef LMX2594_DAC
	/**********************************************************/
	/************* LMX2594 for DAC Configuration **************/
	/**********************************************************/
	Status = lmx2594_init(&lmx2594_dac_inst, &lmx2594_dac_init_param);
	for(int i = 0; i < lmx2594_default_config_len; i++)
	{
		Status = lmx2594_write(lmx2594_dac_inst,
				lmx2594_default_config[i].addr, lmx2594_default_config[i].value);
		if (lmx2594_default_config[i].addr == 0)
		{
			mdelay(500);
		}
	}

	uint16_t Lmx2594DacRead;

	// check vco lock status
	Status = lmx2594_read(lmx2594_dac_inst, 110, &Lmx2594DacRead);
	if (((Lmx2594DacRead >> 9) & 0x0003) == 0x0002) {
		DBG_INFO("HDWR: [DAC LMX2594] Config Done.\r\n");
	}
	else {
		DBG_INFO("HDWR: [DAC LMX2594] not lock!\r\n");
	}

	// set mux out to lock status
	Status = lmx2594_write(lmx2594_dac_inst, 0x00, 0x259C);
	DBG_INFO("HDWR: [DAC LMX2594] SPI readback disabled, "
			"lock status is shown on LED.\r\n");
#endif

#if defined(AD9361_API) || defined(AD9361_REG)
	/**********************************************************/
	/***************** AD9361-1 Configuration *****************/
	/**********************************************************/
	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_TXNRX, AD9361_GPIO_OUTPUT);
	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_ENABLE, AD9361_GPIO_OUTPUT);
	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_EN_AGC, AD9361_GPIO_OUTPUT);
	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_RESET_B, AD9361_GPIO_OUTPUT);

#ifdef AD9361_REG
	ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param);
	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 0);
	ad9361_1_reg_config(ad9361_1_reg_inst);
	XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 1);
#endif
#ifdef AD9361_API
	Status = ad9361_init(&ad9361_phy, &ad9361_default_init_param);
	if (Status != XST_SUCCESS){
		DBG_ERROR("HDWR: ad9361_init() error: %" PRId32 "\n", Status);
		return XST_FAILURE;
	}
	ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
	ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
#endif
	/**********************************************************/
	/***************** AD9361-2 Configuration *****************/
	/**********************************************************/
	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_TXNRX, AD9361_GPIO_OUTPUT);
	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_ENABLE, AD9361_GPIO_OUTPUT);
	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_EN_AGC, AD9361_GPIO_OUTPUT);
	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_RESET_B, AD9361_GPIO_OUTPUT);

	ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param);
	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 0);
	ad9361_2_reg_config(ad9361_2_reg_inst);
	XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 1);

	//	uint8_t rd_back;
	//	Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back);
	//	Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back);

//	/**********************************************************/
//	/******* AD9361 Baseband Multichip Synchronization ********/
//	/**********************************************************/
//	XGpioPs_SetDirectionPin(&Gpio, AD9361_SYNC, AD9361_GPIO_OUTPUT);
//	XGpioPs_SetDirectionPin(&Gpio, AD9361_RX_FIFO_RST, AD9361_GPIO_OUTPUT);
//
//	// SYNC BBPLL and DIGITAL SAMPLING CLOCKS
//	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable
//	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D);
//	ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable
//	ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80);
//	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
//	mdelay(20);
//	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin
//	mdelay(500);
//	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
//	mdelay(2000);
//	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable
//	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B);
//	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin
//	mdelay(500);
//	XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
//	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits
//	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08);
//
//	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
//	mdelay(20);
//	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 1);
//	mdelay(20);
//	XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
//
//	/**********************************************************/
//	/********* AD9361 Multichip Rx Phase Calibration **********/
//	/**********************************************************/
//	XGpioPs_SetDirectionPin(&Gpio, AD9361_TX_SWITCH, AD9361_GPIO_OUTPUT);
//	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_START, AD9361_GPIO_OUTPUT);
//	XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_DONE, AD9361_GPIO_INPUT);
//	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_START, AD9361_GPIO_OUTPUT);
//	XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_DONE, AD9361_GPIO_INPUT);
//
//	// switch to lower frequency
//	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126);
//	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 1);
//	mdelay(20);
//
//	// switch rx channel
//	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30);
//	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30);
//
//	// enable dual ad9361 tx channels
//	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels
//
//	// switch ad9361 tx channel
//	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
//	mdelay(20);
//
//	// begin to calibrate the 1st ad9361
//	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
//	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 1);
//	mdelay(1);
//	XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
//
//	// read calibration status
//	int32_t time_out_cnt = 0;
//	do
//	{
//		mdelay(1); // Wait 1ms
//		time_out_cnt++;
//	} while (((XGpioPs_ReadPin(&Gpio, AD9361_1_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
//
//	if (time_out_cnt == AD9361_TIMEOUT_TH)
//	{
//		return FAILURE;
//	}
//
//	// begin to calibrate the 2nd ad9361
//	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 1);
//	mdelay(1);
//	XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 0);
//
//	// read calibration status
//	time_out_cnt = 0;
//	do
//	{
//		mdelay(1); // Wait 1ms
//		time_out_cnt++;
//	} while (((XGpioPs_ReadPin(&Gpio, AD9361_2_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
//
//	if (time_out_cnt == AD9361_TIMEOUT_TH)
//	{
//		return FAILURE;
//	}
//
//	// enable single ad9361 tx channels
//	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels
//
//	// switch ad9361 tx & rx channel
//	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03);
//	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03);
//
//	// switch to higher frequency
//	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125);
//	XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 0);
//
	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0109, 0x14); // Rx Gain
	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x010C, 0x14); // Rx Gain
	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0109, 0x14); // Rx Gain
	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x010C, 0x14); // Rx Gain
#endif

#ifdef AD9653
	Status = ad9653_init(&ad9653_inst, &ad9653_default_init_param);
	for(int i = 0; i < ad9653_default_config_len; i++){
		Status = ad9653_write(ad9653_inst, ad9653_default_config[i].addr,
				ad9653_default_config[i].value);
		if (ad9653_default_config[i].addr == 0x0000){
			mdelay(500);
		}
	}
#endif

#ifdef AD9694
	/**********************************************************/
	/****************** AD9694 Configuration ******************/
	/**********************************************************/
	Status = ad9694_init(&ad9694_inst, &ad9694_default_init_param);
	for(int i = 0; i < ad9694_default_config_len; i++){
		Status = ad9694_write(ad9694_inst, ad9694_default_config[i].addr, ad9694_default_config[i].value);
		if (ad9694_default_config[i].addr == 0x0000){
			mdelay(500);
		}
	}

//	uint8_t reg0008;
//	uint8_t reg056F;
//	uint8_t reg0571;
//
//	ad9694_read(ad9694_inst,0x008,&reg0008);
//	ad9694_read(ad9694_inst,0x56F,&reg056F);
//	ad9694_read(ad9694_inst,0x571,&reg0571);
#endif

#ifdef RFSOC
    /*
     * DAC Mapping:
     *   Number       Tile                  Block
     *   1 (VOUT_00)  228 (XRFDC_TILE_ID0)  DAC 0/DUC 0 (XRFDC_BLK_ID0)
     *   2 (VOUT_02)  228 (XRFDC_TILE_ID0)  DAC 1/DUC 2 (XRFDC_BLK_ID2)
     *   3 (VOUT_10)  229 (XRFDC_TILE_ID1)  DAC 1/DUC 0 (XRFDC_BLK_ID0)
     *   4 (VOUT_12)  229 (XRFDC_TILE_ID1)  DAC 1/DUC 2 (XRFDC_BLK_ID2)
     *   5 (VOUT_20)  230 (XRFDC_TILE_ID2)  DAC 0/DUC 0 (XRFDC_BLK_ID0)
     *   6 (VOUT_22)  230 (XRFDC_TILE_ID2)  DAC 1/DUC 2 (XRFDC_BLK_ID2)
     *   7 (VOUT_30)  231 (XRFDC_TILE_ID3)  DAC 0/DUC 0 (XRFDC_BLK_ID0)
     *   8 (VOUT_32)  231 (XRFDC_TILE_ID3)  DAC 1/DUC 2 (XRFDC_BLK_ID2)
     *
     */

    // get & set mixer settings
    XRFdc_Mixer_Settings Mixer_Settings_DAC;

    // 3th channel
    Status = XRFdc_GetMixerSettings(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
    		XRFDC_BLK_ID0, &Mixer_Settings_DAC);
    if (Status != XST_SUCCESS) {
        return XST_FAILURE;
    }

	Mixer_Settings_DAC.Freq = 1500;

	Status = XRFdc_SetMixerSettings(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
			XRFDC_BLK_ID0, &Mixer_Settings_DAC);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	mdelay(100);

	Status = XRFdc_UpdateEvent(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
			XRFDC_BLK_ID0, XRFDC_EVENT_MIXER);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	 /*
	 * ADC Mapping:
	 *   Number       Tile                  Block
	 *   1 (VIN0_01)  224 (XRFDC_TILE_ID0)  ADC 0 (XRFDC_BLK_ID0)
	 *   2 (VIN0_12)  224 (XRFDC_TILE_ID0)  ADC 1 (XRFDC_BLK_ID1)
	 *   3 (VIN1_01)  225 (XRFDC_TILE_ID1)  ADC 0 (XRFDC_BLK_ID0)
	 *   4 (VIN1_23)  225 (XRFDC_TILE_ID1)  ADC 1 (XRFDC_BLK_ID1)
	 *   5 (VIN2_01)  226 (XRFDC_TILE_ID2)  ADC 0 (XRFDC_BLK_ID0)
	 *   6 (VIN2_23)  227 (XRFDC_TILE_ID2)  ADC 1 (XRFDC_BLK_ID1)
	 *   7 (VIN3_01)  224 (XRFDC_TILE_ID0)  ADC 0 (XRFDC_BLK_ID0)
	 *   8 (VIN3_23)  227 (XRFDC_TILE_ID3)  ADC 1 (XRFDC_BLK_ID1)
	 *
	 */

	// get & set mixer settings
	XRFdc_Mixer_Settings Mixer_Settings_ADC;

	// 3rd channel
	Status = XRFdc_GetMixerSettings(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
			XRFDC_BLK_ID0, &Mixer_Settings_ADC);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	Mixer_Settings_ADC.Freq = 1500;
	Mixer_Settings_ADC.EventSource = XRFDC_EVNT_SRC_TILE;

	Status = XRFdc_SetMixerSettings(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
			XRFDC_BLK_ID0, &Mixer_Settings_ADC);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	mdelay(100);

	Status = XRFdc_UpdateEvent(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
			XRFDC_BLK_ID0, XRFDC_EVENT_MIXER);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

#endif

	DBG_INFO("HDWR: Configuration Done.\n");

	return SUCCESS;
}

/*****************************************************************************/
/**
 * @brief   Hardware_SwitchFreq
 *
 * @param   devSysMonitor_UpdateHardwareStatus(newHwState);
 * @param   freq
 *
 * @return  None.
 *
 ******************************************************************************/
int32_t Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq)
{
	int32_t status = 0;
	uint8_t value = 0;
	int32_t time_out_cnt = 0;

	switch (freq)
	{
	case TX_FREQ_125:
	{
		//************************************************************
		// Setup Tx Frequency-Dependent Syntheisizer Registers
		//************************************************************
		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
		status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp)
		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3

		//************************************************************
		// Write Tx Frequency Words
		//************************************************************
		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
		status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting

		//************************************************************
		// Tx Quadrature Calibration Settings
		//************************************************************
		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used

		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal

		break;
	}
	case TX_FREQ_126:
	{
		//************************************************************
		// Setup Tx Frequency-Dependent Syntheisizer Registers
		//************************************************************
		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3

		//************************************************************
		// Write Tx Frequency Words
		//************************************************************
		status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0]
		status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8]
		status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16]
		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
		status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
		status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting

		//************************************************************
		// Tx Quadrature Calibration Settings
		//************************************************************
		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
		status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
		status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used

		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal

		break;
	}
	case TX_FREQ_4125:
	{
		//************************************************************
		// Setup Tx Frequency-Dependent Syntheisizer Registers
		//************************************************************
		status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
		status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
		status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
		status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
		status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
		status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
		status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
		status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
		status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
		status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter  R1 and C3
		status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3

		//************************************************************
		// Write Rx Frequency Words
		//************************************************************
		status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
		status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
		status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
		status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
		status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
		status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting

		//************************************************************
		// Tx Quadrature Calibration Settings
		//************************************************************
		status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
		status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
		status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
		status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
		status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
		status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
		status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
		status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index
		status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
		status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used

		status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
		status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal

		break;
	}

		// Wait for cal to complete (Done when 0x016[4]==0)
		time_out_cnt = 0;
		do
		{
			status |= ad9361_reg_read(dev, 0x0016, &value);
			mdelay(1); // Wait 1ms
			time_out_cnt++;
		} while ((value & 0x10) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
	}

	return status;
}

// @ Get AD9361 - 1 temperature (Celsius Degree)
/**
 * Read corresponding register to get AD9361 - 1 current temperature.
 */
int8_t Hardware_GetAD9361Temp_1(void)
{
	int8_t scaleTemp;
	double temp;

	ad9361_reg_write(ad9361_1_reg_inst, 0x000B, -64);
	ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x01); // disable aux adc
	ad9361_reg_read(ad9361_1_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
	ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x00); // enable aux adc

	temp = ((double)scaleTemp + 64)/1.16;
	return ((temp > INT8_MAX) ? INT8_MAX : (int8_t)temp);
}

// @ Get AD9361 - 2 temperature (Celsius Degree)
/**
 * Read corresponding register to get AD9361 - 2 current temperature.
 */
int8_t Hardware_GetAD9361Temp_2(void)
{
	int8_t scaleTemp;
	double temp;

	ad9361_reg_write(ad9361_2_reg_inst, 0x000B, -64);
	ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x01); // disable aux adc
	ad9361_reg_read(ad9361_2_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
	ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x00); // enable aux adc
	temp = ((double)scaleTemp + 64)/1.16;
	return ((temp > INT8_MAX) ? INT8_MAX : (int8_t)temp);
}

// @ Determine AD9361 lock state
/**
 * Read corresponding register to determine AD9361(both) lock state.
 */
uint8_t Hardware_GetAD9361LockStatus(void)
{
	uint8_t ret = 0;
	uint8_t regVal;

	// bbpll
	ad9361_reg_read(ad9361_1_reg_inst, 0x005E, &regVal); // [D7] is lock indicator
	ret |= ((regVal & 0x80) == 0x80) ? CLK_AD0_BBPLL_LOCK : 0;
	ad9361_reg_read(ad9361_2_reg_inst, 0x005E, &regVal); // [D7] is lock indicator
	ret |= ((regVal & 0x80) == 0x80) ? CLK_AD1_BBPLL_LOCK : 0;

	// rfpll
	ad9361_reg_read(ad9361_1_reg_inst, 0x0287, &regVal); // [D1] is lock indicator
	ret |= ((regVal & 0x02) == 0x02) ? CLK_AD0_RFPLL_LOCK : 0;
	ad9361_reg_read(ad9361_2_reg_inst, 0x0287, &regVal); // [D1] is lock indicator
	ret |= ((regVal & 0x02) == 0x02) ? CLK_AD1_RFPLL_LOCK : 0;

	return ret;
}

// @ Determine HMC7044 lock state
/**
 * Read corresponding register to determine clock lock state.
 */
uint8_t Hardware_GetHMC7044LockStatus(void)
{
	uint8_t ret = 0;
	uint8_t regVal;

	// pll1
	hmc7044_read(hmc7044_inst, 0x007C, &regVal); // [D5] is lock indicator
	ret |= ((regVal & 0xE0) != 0x00) ? CLK_SP_PLL0_LOCK : 0;

	// pll2
	hmc7044_read(hmc7044_inst, 0x007D, &regVal); // [D0] is lock indicator
	ret |= ((regVal & 0x01) == 0x01) ? CLK_SP_PLL1_LOCK : 0;

	return ret;
}