741 lines
29 KiB
C
741 lines
29 KiB
C
/*****************************************************************************/
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/**
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* Description: hwconfig.h
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*
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* Date: 2024-02-20 13:19
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* Last Edit Time: [2024-02-20 13:19]
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*
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* Revisions: Rev 0.0
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* History:
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* [2023-05-07]: Initial edition.
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*
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* Copyright(c) 2024 Beijing Institute of Technology.
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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// Standard
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#include <stdint.h>
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#include <stdbool.h>
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// Xilinx
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#include "xgpiops.h"
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#include "drivers/axi_core/spi_engine/spi_engine.h"
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// App
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#include "common.h"
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#include "error.h"
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#include "delay.h"
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#include "system_monitor.h"
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#include "hwconfig.h"
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#include "config/app_config.h"
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#include "dev_profile/dev_profile.h"
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#ifdef RFSOC
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#include "xrfdc.h"
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#endif
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/************************** Function Prototypes ******************************/
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/*********************** Driver Instance Definitions **************************/
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static struct hmc7044_dev *hmc7044_inst;
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ad9528Device_t *ad9528_inst;
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static struct lmk04828_dev *lmk04828_inst;
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static struct lmx2594_dev *lmx2594_adc_inst;
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static struct lmx2594_dev *lmx2594_dac_inst;
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static struct ad9361_reg_dev *ad9361_1_reg_inst;
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static struct ad9361_reg_dev *ad9361_2_reg_inst;
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static struct ad9361_rf_phy *ad9361_phy;
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static struct ad9653_dev *ad9653_inst;
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static struct ad9694_dev *ad9694_inst;
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XGpioPs Gpio;
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#ifdef RFSOC
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XRFdc RFdc;
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#endif
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/*****************************************************************************/
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/**
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* @brief Hardware_Init
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*
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* @param none.
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*
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* @return None.
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*
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******************************************************************************/
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int32_t Hardware_Init(void)
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{
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int32_t Status;
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// gpio initialization
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XGpioPs_Config *ConfigPtr;
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ConfigPtr = XGpioPs_LookupConfig(AD9361_GPIO_DEVICE_ID);
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Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
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if (Status != SUCCESS)
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{
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return FAILURE;
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}
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#ifdef RFSOC
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/**********************************************************/
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/************* RF Data Converter Configuration ************/
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/**********************************************************/
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// rf data converter initialization
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XRFdc_Config *RFdc_ConfigPtr;
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RFdc_ConfigPtr = XRFdc_LookupConfig(RFDC_DEVICE_ID);
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Status = XRFdc_CfgInitialize(&RFdc, RFdc_ConfigPtr);
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if (Status != XST_SUCCESS)
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{
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return XST_FAILURE;
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}
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mdelay(100);
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#endif
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#ifdef HMC7044
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/**********************************************************/
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/****************** HMC7044 Configuration *****************/
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/**********************************************************/
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Status = hmc7044_init(&hmc7044_inst, &hmc7044_default_init_param);
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if (Status != SUCCESS)
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{
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DBG_ERROR("HDWR: hmc7044_init() error: %" PRId32 "\n", Status);
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return FAILURE;
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}
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#endif
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#ifdef AD9528
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/**********************************************************/
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/****************** AD9528 Configuration ******************/
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/**********************************************************/
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Status = AD9528_init(&ad9528_inst, &ad9528_default_init_param);
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if (Status != SUCCESS) {
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DBG_ERROR("HDWR: AD9528_init() error: %" PRId32 "\n", Status);
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return FAILURE;
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}
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Status = AD9528_config(ad9528_inst);
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if (Status != SUCCESS) {
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return FAILURE;
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DBG_ERROR("HDWR: AD9528_config() error: %" PRId32 "\n", Status);
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}
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#endif
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#ifdef LMK04828
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/**********************************************************/
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/***************** LMK04828 Configuration *****************/
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/**********************************************************/
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Status = lmk04828_init(&lmk04828_inst, &lmk04828_default_init_param);
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for(int i = 0; i < lmk04828_default_config_len; i++)
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{
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Status = lmk04828_write(lmk04828_inst,
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lmk04828_default_config[i].addr, lmk04828_default_config[i].value);
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if (lmk04828_default_config[i].addr == 0x0000)
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{
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mdelay(500);
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}
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}
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uint8_t Lmk04828Read;
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// check pll1 lock status
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Status = lmk04828_read(lmk04828_inst, 0x0182, &Lmk04828Read);
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if ((Lmk04828Read & 0x02) == 0x02) {
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DBG_INFO("HDWR: [LMK04828] PLL1 Locked.\r\n");
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}
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else {
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DBG_ERROR("HDWR: [LMK04828] PLL1 NOT lock. It takes a while "
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"for PLL1 to lock. Lock status is shown on LED.\r\n");
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}
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// check pll2 lock status
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Status = lmk04828_read(lmk04828_inst, 0x0183, &Lmk04828Read);
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if ((Lmk04828Read & 0x02) == 0x02) {
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DBG_INFO("HDWR: [LMK04828] PLL2 Locked.\r\n");
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}
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else {
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DBG_INFO("HDWR: [LMK04828] PLL2 NOT lock!\r\n");
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}
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#endif
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#ifdef LMX2594_ADC
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/**********************************************************/
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/************* LMX2594 for ADC Configuration **************/
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/**********************************************************/
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Status = lmx2594_init(&lmx2594_adc_inst, &lmx2594_adc_init_param);
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for(int i = 0; i < lmx2594_default_config_len; i++)
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{
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Status = lmx2594_write(lmx2594_adc_inst,
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lmx2594_default_config[i].addr, lmx2594_default_config[i].value);
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if (lmx2594_default_config[i].addr == 0)
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{
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mdelay(500);
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}
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}
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uint16_t Lmx2594AdcRead;
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// check vco lock status
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Status = lmx2594_read(lmx2594_adc_inst, 110, &Lmx2594AdcRead);
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if (((Lmx2594AdcRead >> 9) & 0x0003) == 0x0002) {
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DBG_INFO("HDWR: [ADC LMX2594] Config Done.\r\n");
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}
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else {
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DBG_INFO("HDWR: [ADC LMX2594] not lock!\r\n");
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}
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// set mux out to lock status
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Status = lmx2594_write(lmx2594_adc_inst, 0x00, 0x259C);
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DBG_INFO("HDWR: [ADC LMX2594] SPI readback disabled, "
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"lock status is shown on LED.\r\n");
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#endif
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#ifdef LMX2594_DAC
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/**********************************************************/
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/************* LMX2594 for DAC Configuration **************/
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/**********************************************************/
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Status = lmx2594_init(&lmx2594_dac_inst, &lmx2594_dac_init_param);
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for(int i = 0; i < lmx2594_default_config_len; i++)
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{
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Status = lmx2594_write(lmx2594_dac_inst,
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lmx2594_default_config[i].addr, lmx2594_default_config[i].value);
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if (lmx2594_default_config[i].addr == 0)
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{
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mdelay(500);
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}
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}
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uint16_t Lmx2594DacRead;
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// check vco lock status
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Status = lmx2594_read(lmx2594_dac_inst, 110, &Lmx2594DacRead);
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if (((Lmx2594DacRead >> 9) & 0x0003) == 0x0002) {
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DBG_INFO("HDWR: [DAC LMX2594] Config Done.\r\n");
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}
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else {
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DBG_INFO("HDWR: [DAC LMX2594] not lock!\r\n");
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}
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// set mux out to lock status
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Status = lmx2594_write(lmx2594_dac_inst, 0x00, 0x259C);
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DBG_INFO("HDWR: [DAC LMX2594] SPI readback disabled, "
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"lock status is shown on LED.\r\n");
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#endif
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#if defined(AD9361_API) || defined(AD9361_REG)
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/**********************************************************/
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/***************** AD9361-1 Configuration *****************/
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/**********************************************************/
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XGpioPs_SetDirectionPin(&Gpio, AD9361_1_TXNRX, AD9361_GPIO_OUTPUT);
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XGpioPs_SetDirectionPin(&Gpio, AD9361_1_ENABLE, AD9361_GPIO_OUTPUT);
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XGpioPs_SetDirectionPin(&Gpio, AD9361_1_EN_AGC, AD9361_GPIO_OUTPUT);
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XGpioPs_SetDirectionPin(&Gpio, AD9361_1_RESET_B, AD9361_GPIO_OUTPUT);
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#ifdef AD9361_REG
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ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param);
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XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 0);
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ad9361_1_reg_config(ad9361_1_reg_inst);
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XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 1);
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#endif
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#ifdef AD9361_API
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Status = ad9361_init(&ad9361_phy, &ad9361_default_init_param);
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if (Status != XST_SUCCESS){
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DBG_ERROR("HDWR: ad9361_init() error: %" PRId32 "\n", Status);
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return XST_FAILURE;
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}
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ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
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ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
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#endif
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/**********************************************************/
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/***************** AD9361-2 Configuration *****************/
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/**********************************************************/
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XGpioPs_SetDirectionPin(&Gpio, AD9361_2_TXNRX, AD9361_GPIO_OUTPUT);
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XGpioPs_SetDirectionPin(&Gpio, AD9361_2_ENABLE, AD9361_GPIO_OUTPUT);
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XGpioPs_SetDirectionPin(&Gpio, AD9361_2_EN_AGC, AD9361_GPIO_OUTPUT);
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XGpioPs_SetDirectionPin(&Gpio, AD9361_2_RESET_B, AD9361_GPIO_OUTPUT);
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ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param);
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XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 0);
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ad9361_2_reg_config(ad9361_2_reg_inst);
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XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 1);
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// uint8_t rd_back;
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// Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back);
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// Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back);
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// /**********************************************************/
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// /******* AD9361 Baseband Multichip Synchronization ********/
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// /**********************************************************/
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// XGpioPs_SetDirectionPin(&Gpio, AD9361_SYNC, AD9361_GPIO_OUTPUT);
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// XGpioPs_SetDirectionPin(&Gpio, AD9361_RX_FIFO_RST, AD9361_GPIO_OUTPUT);
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//
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// // SYNC BBPLL and DIGITAL SAMPLING CLOCKS
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// ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable
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// ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D);
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// ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable
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// ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80);
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// XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
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// mdelay(20);
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// XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin
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// mdelay(500);
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// XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
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// mdelay(2000);
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// ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable
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// ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B);
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// XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin
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// mdelay(500);
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// XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
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// ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits
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// ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08);
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//
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// XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
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// mdelay(20);
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// XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 1);
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// mdelay(20);
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// XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
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//
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// /**********************************************************/
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// /********* AD9361 Multichip Rx Phase Calibration **********/
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// /**********************************************************/
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// XGpioPs_SetDirectionPin(&Gpio, AD9361_TX_SWITCH, AD9361_GPIO_OUTPUT);
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// XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_START, AD9361_GPIO_OUTPUT);
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// XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_DONE, AD9361_GPIO_INPUT);
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// XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_START, AD9361_GPIO_OUTPUT);
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// XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_DONE, AD9361_GPIO_INPUT);
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//
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// // switch to lower frequency
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// Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126);
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// XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 1);
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// mdelay(20);
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//
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// // switch rx channel
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// Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30);
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// Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30);
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//
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// // enable dual ad9361 tx channels
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// Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels
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//
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// // switch ad9361 tx channel
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// Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
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// mdelay(20);
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//
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// // begin to calibrate the 1st ad9361
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// XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
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// XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 1);
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// mdelay(1);
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// XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
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//
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// // read calibration status
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// int32_t time_out_cnt = 0;
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// do
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// {
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// mdelay(1); // Wait 1ms
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// time_out_cnt++;
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// } while (((XGpioPs_ReadPin(&Gpio, AD9361_1_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
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//
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// if (time_out_cnt == AD9361_TIMEOUT_TH)
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// {
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// return FAILURE;
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// }
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//
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// // begin to calibrate the 2nd ad9361
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// XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 1);
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// mdelay(1);
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// XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 0);
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//
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// // read calibration status
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// time_out_cnt = 0;
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// do
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// {
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// mdelay(1); // Wait 1ms
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// time_out_cnt++;
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// } while (((XGpioPs_ReadPin(&Gpio, AD9361_2_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
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//
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// if (time_out_cnt == AD9361_TIMEOUT_TH)
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// {
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// return FAILURE;
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// }
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//
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// // enable single ad9361 tx channels
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// Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels
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//
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// // switch ad9361 tx & rx channel
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// Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03);
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// Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03);
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//
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// // switch to higher frequency
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// Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125);
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// XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 0);
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//
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Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0109, 0x14); // Rx Gain
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Status = ad9361_reg_write(ad9361_1_reg_inst, 0x010C, 0x14); // Rx Gain
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Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0109, 0x14); // Rx Gain
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Status = ad9361_reg_write(ad9361_2_reg_inst, 0x010C, 0x14); // Rx Gain
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#endif
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#ifdef AD9653
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Status = ad9653_init(&ad9653_inst, &ad9653_default_init_param);
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for(int i = 0; i < ad9653_default_config_len; i++){
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Status = ad9653_write(ad9653_inst, ad9653_default_config[i].addr,
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ad9653_default_config[i].value);
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if (ad9653_default_config[i].addr == 0x0000){
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mdelay(500);
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}
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}
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#endif
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#ifdef AD9694
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/**********************************************************/
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/****************** AD9694 Configuration ******************/
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/**********************************************************/
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Status = ad9694_init(&ad9694_inst, &ad9694_default_init_param);
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for(int i = 0; i < ad9694_default_config_len; i++){
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Status = ad9694_write(ad9694_inst, ad9694_default_config[i].addr, ad9694_default_config[i].value);
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if (ad9694_default_config[i].addr == 0x0000){
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mdelay(500);
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}
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}
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// uint8_t reg0008;
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// uint8_t reg056F;
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// uint8_t reg0571;
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//
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// ad9694_read(ad9694_inst,0x008,®0008);
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// ad9694_read(ad9694_inst,0x56F,®056F);
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// ad9694_read(ad9694_inst,0x571,®0571);
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#endif
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#ifdef RFSOC
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/*
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* DAC Mapping:
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* Number Tile Block
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* 1 (VOUT_00) 228 (XRFDC_TILE_ID0) DAC 0/DUC 0 (XRFDC_BLK_ID0)
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* 2 (VOUT_02) 228 (XRFDC_TILE_ID0) DAC 1/DUC 2 (XRFDC_BLK_ID2)
|
|
* 3 (VOUT_10) 229 (XRFDC_TILE_ID1) DAC 1/DUC 0 (XRFDC_BLK_ID0)
|
|
* 4 (VOUT_12) 229 (XRFDC_TILE_ID1) DAC 1/DUC 2 (XRFDC_BLK_ID2)
|
|
* 5 (VOUT_20) 230 (XRFDC_TILE_ID2) DAC 0/DUC 0 (XRFDC_BLK_ID0)
|
|
* 6 (VOUT_22) 230 (XRFDC_TILE_ID2) DAC 1/DUC 2 (XRFDC_BLK_ID2)
|
|
* 7 (VOUT_30) 231 (XRFDC_TILE_ID3) DAC 0/DUC 0 (XRFDC_BLK_ID0)
|
|
* 8 (VOUT_32) 231 (XRFDC_TILE_ID3) DAC 1/DUC 2 (XRFDC_BLK_ID2)
|
|
*
|
|
*/
|
|
|
|
// get & set mixer settings
|
|
XRFdc_Mixer_Settings Mixer_Settings_DAC;
|
|
|
|
// 3th channel
|
|
Status = XRFdc_GetMixerSettings(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
|
|
XRFDC_BLK_ID0, &Mixer_Settings_DAC);
|
|
if (Status != XST_SUCCESS) {
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
Mixer_Settings_DAC.Freq = 1500;
|
|
|
|
Status = XRFdc_SetMixerSettings(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
|
|
XRFDC_BLK_ID0, &Mixer_Settings_DAC);
|
|
if (Status != XST_SUCCESS) {
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
mdelay(100);
|
|
|
|
Status = XRFdc_UpdateEvent(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
|
|
XRFDC_BLK_ID0, XRFDC_EVENT_MIXER);
|
|
if (Status != XST_SUCCESS) {
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/*
|
|
* ADC Mapping:
|
|
* Number Tile Block
|
|
* 1 (VIN0_01) 224 (XRFDC_TILE_ID0) ADC 0 (XRFDC_BLK_ID0)
|
|
* 2 (VIN0_12) 224 (XRFDC_TILE_ID0) ADC 1 (XRFDC_BLK_ID1)
|
|
* 3 (VIN1_01) 225 (XRFDC_TILE_ID1) ADC 0 (XRFDC_BLK_ID0)
|
|
* 4 (VIN1_23) 225 (XRFDC_TILE_ID1) ADC 1 (XRFDC_BLK_ID1)
|
|
* 5 (VIN2_01) 226 (XRFDC_TILE_ID2) ADC 0 (XRFDC_BLK_ID0)
|
|
* 6 (VIN2_23) 227 (XRFDC_TILE_ID2) ADC 1 (XRFDC_BLK_ID1)
|
|
* 7 (VIN3_01) 224 (XRFDC_TILE_ID0) ADC 0 (XRFDC_BLK_ID0)
|
|
* 8 (VIN3_23) 227 (XRFDC_TILE_ID3) ADC 1 (XRFDC_BLK_ID1)
|
|
*
|
|
*/
|
|
|
|
// get & set mixer settings
|
|
XRFdc_Mixer_Settings Mixer_Settings_ADC;
|
|
|
|
// 3rd channel
|
|
Status = XRFdc_GetMixerSettings(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
|
|
XRFDC_BLK_ID0, &Mixer_Settings_ADC);
|
|
if (Status != XST_SUCCESS) {
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
Mixer_Settings_ADC.Freq = 1500;
|
|
Mixer_Settings_ADC.EventSource = XRFDC_EVNT_SRC_TILE;
|
|
|
|
Status = XRFdc_SetMixerSettings(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
|
|
XRFDC_BLK_ID0, &Mixer_Settings_ADC);
|
|
if (Status != XST_SUCCESS) {
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
mdelay(100);
|
|
|
|
Status = XRFdc_UpdateEvent(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
|
|
XRFDC_BLK_ID0, XRFDC_EVENT_MIXER);
|
|
if (Status != XST_SUCCESS) {
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
#endif
|
|
|
|
DBG_INFO("HDWR: Configuration Done.\n");
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* @brief Hardware_SwitchFreq
|
|
*
|
|
* @param devSysMonitor_UpdateHardwareStatus(newHwState);
|
|
* @param freq
|
|
*
|
|
* @return None.
|
|
*
|
|
******************************************************************************/
|
|
int32_t Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq)
|
|
{
|
|
int32_t status = 0;
|
|
uint8_t value = 0;
|
|
int32_t time_out_cnt = 0;
|
|
|
|
switch (freq)
|
|
{
|
|
case TX_FREQ_125:
|
|
{
|
|
//************************************************************
|
|
// Setup Tx Frequency-Dependent Syntheisizer Registers
|
|
//************************************************************
|
|
status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
|
|
status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
|
|
status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
|
|
status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
|
|
status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
|
|
status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
|
|
status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
|
|
status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp)
|
|
status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
|
|
status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3
|
|
status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
|
|
|
|
//************************************************************
|
|
// Write Tx Frequency Words
|
|
//************************************************************
|
|
status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
|
|
status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
|
|
status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
|
|
status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
|
|
status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
|
|
status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
|
|
|
|
//************************************************************
|
|
// Tx Quadrature Calibration Settings
|
|
//************************************************************
|
|
status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
|
|
status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
|
|
status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
|
|
status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
|
|
status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
|
|
status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
|
|
status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
|
|
status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
|
|
status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
|
|
status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
|
|
|
|
status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
|
|
status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
|
|
|
|
break;
|
|
}
|
|
case TX_FREQ_126:
|
|
{
|
|
//************************************************************
|
|
// Setup Tx Frequency-Dependent Syntheisizer Registers
|
|
//************************************************************
|
|
status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
|
|
status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
|
|
status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
|
|
status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
|
|
status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
|
|
status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
|
|
status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
|
|
status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
|
|
status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
|
|
status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3
|
|
status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
|
|
|
|
//************************************************************
|
|
// Write Tx Frequency Words
|
|
//************************************************************
|
|
status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0]
|
|
status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8]
|
|
status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16]
|
|
status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
|
|
status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
|
|
status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
|
|
|
|
//************************************************************
|
|
// Tx Quadrature Calibration Settings
|
|
//************************************************************
|
|
status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
|
|
status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
|
|
status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
|
|
status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
|
|
status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
|
|
status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
|
|
status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
|
|
status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
|
|
status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
|
|
status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
|
|
|
|
status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
|
|
status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
|
|
|
|
break;
|
|
}
|
|
case TX_FREQ_4125:
|
|
{
|
|
//************************************************************
|
|
// Setup Tx Frequency-Dependent Syntheisizer Registers
|
|
//************************************************************
|
|
status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
|
|
status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
|
|
status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
|
|
status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
|
|
status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
|
|
status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
|
|
status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
|
|
status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
|
|
status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
|
|
status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3
|
|
status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
|
|
|
|
//************************************************************
|
|
// Write Rx Frequency Words
|
|
//************************************************************
|
|
status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
|
|
status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
|
|
status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
|
|
status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
|
|
status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
|
|
status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting
|
|
|
|
//************************************************************
|
|
// Tx Quadrature Calibration Settings
|
|
//************************************************************
|
|
status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
|
|
status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
|
|
status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
|
|
status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
|
|
status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
|
|
status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
|
|
status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
|
|
status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index
|
|
status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
|
|
status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used
|
|
|
|
status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
|
|
status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
|
|
|
|
break;
|
|
}
|
|
|
|
// Wait for cal to complete (Done when 0x016[4]==0)
|
|
time_out_cnt = 0;
|
|
do
|
|
{
|
|
status |= ad9361_reg_read(dev, 0x0016, &value);
|
|
mdelay(1); // Wait 1ms
|
|
time_out_cnt++;
|
|
} while ((value & 0x10) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
// @ Get AD9361 - 1 temperature (Celsius Degree)
|
|
/**
|
|
* Read corresponding register to get AD9361 - 1 current temperature.
|
|
*/
|
|
int8_t Hardware_GetAD9361Temp_1(void)
|
|
{
|
|
int8_t scaleTemp;
|
|
double temp;
|
|
|
|
ad9361_reg_write(ad9361_1_reg_inst, 0x000B, -64);
|
|
ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x01); // disable aux adc
|
|
ad9361_reg_read(ad9361_1_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
|
|
ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x00); // enable aux adc
|
|
|
|
temp = ((double)scaleTemp + 64)/1.16;
|
|
return ((temp > INT8_MAX) ? INT8_MAX : (int8_t)temp);
|
|
}
|
|
|
|
// @ Get AD9361 - 2 temperature (Celsius Degree)
|
|
/**
|
|
* Read corresponding register to get AD9361 - 2 current temperature.
|
|
*/
|
|
int8_t Hardware_GetAD9361Temp_2(void)
|
|
{
|
|
int8_t scaleTemp;
|
|
double temp;
|
|
|
|
ad9361_reg_write(ad9361_2_reg_inst, 0x000B, -64);
|
|
ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x01); // disable aux adc
|
|
ad9361_reg_read(ad9361_2_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
|
|
ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x00); // enable aux adc
|
|
temp = ((double)scaleTemp + 64)/1.16;
|
|
return ((temp > INT8_MAX) ? INT8_MAX : (int8_t)temp);
|
|
}
|
|
|
|
// @ Determine AD9361 lock state
|
|
/**
|
|
* Read corresponding register to determine AD9361(both) lock state.
|
|
*/
|
|
uint8_t Hardware_GetAD9361LockStatus(void)
|
|
{
|
|
uint8_t ret = 0;
|
|
uint8_t regVal;
|
|
|
|
// bbpll
|
|
ad9361_reg_read(ad9361_1_reg_inst, 0x005E, ®Val); // [D7] is lock indicator
|
|
ret |= ((regVal & 0x80) == 0x80) ? CLK_AD0_BBPLL_LOCK : 0;
|
|
ad9361_reg_read(ad9361_2_reg_inst, 0x005E, ®Val); // [D7] is lock indicator
|
|
ret |= ((regVal & 0x80) == 0x80) ? CLK_AD1_BBPLL_LOCK : 0;
|
|
|
|
// rfpll
|
|
ad9361_reg_read(ad9361_1_reg_inst, 0x0287, ®Val); // [D1] is lock indicator
|
|
ret |= ((regVal & 0x02) == 0x02) ? CLK_AD0_RFPLL_LOCK : 0;
|
|
ad9361_reg_read(ad9361_2_reg_inst, 0x0287, ®Val); // [D1] is lock indicator
|
|
ret |= ((regVal & 0x02) == 0x02) ? CLK_AD1_RFPLL_LOCK : 0;
|
|
|
|
return ret;
|
|
}
|
|
|
|
// @ Determine HMC7044 lock state
|
|
/**
|
|
* Read corresponding register to determine clock lock state.
|
|
*/
|
|
uint8_t Hardware_GetHMC7044LockStatus(void)
|
|
{
|
|
uint8_t ret = 0;
|
|
uint8_t regVal;
|
|
|
|
// pll1
|
|
hmc7044_read(hmc7044_inst, 0x007C, ®Val); // [D5] is lock indicator
|
|
ret |= ((regVal & 0xE0) != 0x00) ? CLK_SP_PLL0_LOCK : 0;
|
|
|
|
// pll2
|
|
hmc7044_read(hmc7044_inst, 0x007D, ®Val); // [D0] is lock indicator
|
|
ret |= ((regVal & 0x01) == 0x01) ? CLK_SP_PLL1_LOCK : 0;
|
|
|
|
return ret;
|
|
}
|