feat: 迁移demo工程,升级版本,更换发端程序

rfsoc_eval_demo/.gitignore

@@ -0,0 +1,119 @@
+################################################################################
+############################### Project Specific ###############################
+################################################################################
+# everything
+*
+
+# git related
+!/.gitignore
+!/.gitattributes
+
+# project documents
+!/*.md
+!/*.txt
+
+################################################################################
+############################### Vivado Specific ################################
+################################################################################
+
+# xpr: needed for recreating design
+!/*.xpr
+
+# source: include everything
+!/*.srcs/
+!/*.srcs/**/*
+
+# runs: exclude everything but design run results
+!/*.runs/
+!/*.runs/impl_*/
+!/*.runs/impl_*/*.bit
+!/*.runs/impl_*/*.ltx
+
+# xsa (Xilinx support archive): include for ps
+!/*.xsa
+
+################################################################################
+################################ Vitis Specific ################################
+################################################################################
+
+# include sdk directory and everything in it
+!/vitis*/
+!/vitis*/**
+/vitis*/**.log
+/vitis*/.analytics
+
+# exclude some obscure hidden SDK folders
+/vitis*/.metadata/
+/vitis*/.sdk/
+/vitis*/RemoteSystemsTempFiles/
+/vitis*/webtalk/
+
+# hw_platform: exclude the entire hw_platform folder, as everything can be
+# generated from the .hdf file. Make sure to include the bitstream in the .hdf
+# file when exporting from Vivado!
+/vitis*/*_hw_platform_*/
+
+# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
+# Makefile, ps lib files are regenerated automatically
+/vitis*/*_bsp/*
+!/vitis*/*_bsp/*.cproject
+!/vitis*/*_bsp/*.project
+!/vitis*/*_bsp/*.sdkproject
+!/vitis*/*_bsp/system.mss
+!/vitis*/*_bsp/Makefile
+
+# Application: ignored file patterns, exclude Debug & Release folders
+/vitis*/**/*.o
+/vitis*/**/*.d
+/vitis*/**/*.a
+/vitis*/*/Debug/
+/vitis*/*/Release/
+
+################################################################################
+############################ Vivado & Vitis Common #############################
+################################################################################
+
+# file patterns that should always be ignored (journal files, log files, dump
+# files that are created upon Vivado/SDK errors)
+*.jou
+*.log
+*.backup.jou
+*.backup.log
+*.upgrade_log
+*.dmp
+*.debug
+vivado_pid*
+
+# vivado workspace files
+xsim.dir/
+xvlog.pb
+
+# Xilinx tools generated files
+.metadata/
+.settings/
+.wsdata/
+.Xil/
+logs/
+Packages/
+*.log*
+
+# System generated files
+# -- macOS
+.DS_Store
+.AppleDouble
+.LSOverride
+._*
+
+# -- Windows
+Thumbs.db
+ehthumbs.db
+Desktop.ini
+
+# -- Linux
+*~
+
+# IDEs and editors' files
+*.idea
+*.vscode
+*.sublime-workspace
+*.sublime-project

rfsoc_eval_demo/README.md

@@ -0,0 +1,27 @@
+<!-- omit in toc -->
+# Josh & RFSoC EVB
+
+- [`20241110` - 升级到 Vivado 2024.1.2 更新发端程序](#20241110---升级到-vivado-202412-更新发端程序)
+- [`20240629` - 使用 Vivado 2024.1 进行开发，MTS 通过](#20240629---使用-vivado-20241-进行开发mts-通过)
+
+## `20241110` - 升级到 Vivado 2024.1.2 更新发端程序
+
+将工程迁移到了 Vivado 2024.1.2 版本，并将发端 QPSK 程序修改为多符号速率 QPSK 发送端。发端根升余弦滤波器参数在 200 MHz 时钟下计算得到，本程序时钟为 245.76 MHz，在实测时需要对应换算。
+
+## `20240629` - 使用 Vivado 2024.1 进行开发，MTS 通过
+
+将工程迁移到了 Vivado 2024.1 版本，并进行以下改动：
+
+- 按照 PG269 的推荐，修改了 PL CLK 和 PL SYSREF 接入 FPGA 的方法，原来使用 RF Data Converter 输出的时钟对 PL SYSREF 采样并输入到 RF Data Converter 中，但是 PG269 不允许这样操作，因此改为使用输入 FPGA 管脚的 PL CLK 对 PL SYSREF 进行采样。
+
+- FPGA 的 PL CLK 接入了 HD Bank 的 HDGC 管脚，但是 HD Bank 旁边没有 CMT，需要通过 BUFG 接入相邻的 CMT，因此在约束中使用了 `set property CLOCK_DEDICATED_ROUTE FALSE [get_nets <net for clock input to MMCM/PLL>]` 来消除 Place 过程中的 Error。
+
+  > First, make sure you are bringing your clock into the FPGA on a global clock (GC) pin. Then note from page 10 of UG572 that HD I/O banks do not have a CMT (eg. MMCM/PLL) next to them. However, from an HD I/O bank, you can reach a CMT via a BUFGCE (BUFG). Routing the clock from the GC pin and through a BUFGCE will cause the warnings you are seeing, which can be safely avoided by placing the following constraint in your in your xdc file.
+  >
+  > REF: [[PLace 30-716] Clock input driving MMCM/PLL in HDIO bank with BUFGCE](https://support.xilinx.com/s/question/0D52E00006lLh0DSAS/place-30716-clock-input-driving-mmcmpll-in-hdio-bank-with-bufgce?language=en_US)
+
+- RF Data Converter 中开启了 8 个 RF-ADC 和 8 个 RF-DAC，各 RF-ADC 和 RF-DAC 配置相同，均为 4.9152 Gsps 采样率、x40 抽取/内插，和 PL 数据交互的速率为 245.76 MHz。
+
+- PS 端有两个 Demo 工程，一个是可以修改部分 ADC/DAC 配置的扫频程序，一个是 RFSoC Multi-tile sync 多通道同步的程序，仅供参考。
+
+- 启用了动态 DDR 配置，依赖于 FSBL 启动，在启动时 FSBL 会使用 I2C 读取 DDR 的 SPD EEPROM 获得 DDR 参数，并初始化 DDR 控制器。此部分原理图与 Xilinx 开发板 I2C Mux Slave 连接一致，因此重新建立工程时除了需要同时建立 FSBL 外不需要额外操作。

rfsoc_eval_demo/rfsoc_eval_demo.srcs/constrs_1/new/rfsoc_eval.xdc

@@ -0,0 +1,10 @@
+set_property  -dict  {PACKAGE_PIN B8    IOSTANDARD LVPECL  }  [get_ports pl_refclk_p            ] ;# PL_CLK_P
+set_property  -dict  {PACKAGE_PIN B10   IOSTANDARD LVPECL  }  [get_ports pl_sysref_p            ] ;# PL_SYSREF_P
+
+set_property  -dict  {PACKAGE_PIN AW5   IOSTANDARD LVCMOS18}  [get_ports lmk_spi_sck            ] ;# LMK_SPI_CS_LS
+set_property  -dict  {PACKAGE_PIN AW3   IOSTANDARD LVCMOS18}  [get_ports lmk_spi_cs             ] ;# LMK_SPI_SCK_LS
+set_property  -dict  {PACKAGE_PIN AW6   IOSTANDARD LVCMOS18}  [get_ports lmk_spi_mosi_sdio      ] ;# LMK_SPI_SDI_LS
+set_property  -dict  {PACKAGE_PIN AW4   IOSTANDARD LVCMOS18}  [get_ports lmk_spi_miso           ] ;# LMK_SPI_SDO_LS
+
+# Route HDGC clock through BUFG to adjacent CMT
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O]

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sim_1/new/tb_baseband.v

@@ -0,0 +1,56 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2022/03/23 20:39:14
+// Design Name:
+// Module Name: tb_baseband_new
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_baseband();
+
+reg             clk = 'b0;
+reg             rst = 'b1;
+wire    [15:0]  tx_data_i;
+wire    [15:0]  tx_data_q;
+
+reg     [ 1:0]  waveform_sel = 2'b00;
+reg             sweep_on = 1'b0;
+reg     [31:0]  freq_set = 32'd0; // 20 / 245.76 * 2^31
+reg     [ 1:0]  iq_sel = 2'b11;
+reg     [ 3:0]  bb_rshift = 4'd0;
+
+baseband_tx u_baseband_tx
+(
+    .clk            (clk            ),
+    .rst            (rst            ),
+    .tx_data_i      (tx_data_i      ),
+    .tx_data_q      (tx_data_q      ),
+
+    .waveform_sel   (waveform_sel   ),
+    .sweep_on       (sweep_on       ),
+    .freq_set       (freq_set       ),
+    .iq_sel         (iq_sel         ),
+    .bb_rshift      (bb_rshift      )
+);
+
+initial begin
+    #101 rst = 1'b0;
+end
+
+always #3 clk = ~clk;
+
+endmodule

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_ds_0/system_bd_auto_ds_0.xci

@@ -0,0 +1,336 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_auto_ds_0",
+    "cell_name": "ps8_axi_periph/s00_couplers/auto_ds",
+    "component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1",
+    "ip_revision": "32",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_auto_ds_0",
+    "parameters": {
+      "component_parameters": {
+        "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PACKING_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SI_DATA_WIDTH": [ { "value": "128", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MI_DATA_WIDTH": [ { "value": "32", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SI_ID_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MAX_SPLIT_BEATS": [ { "value": "256", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "FIFO_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ACLK_ASYNC": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ACLK_RATIO": [ { "value": "1:2", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_auto_ds_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ID_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SUPPORTS_ID": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FIFO_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ACLK_RATIO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_ACLK_RATIO": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MAX_SPLIT_BEATS": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PACKING_LEVEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_auto_ds_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_awid": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
+        "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
+        "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
+        "s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0xFFFF" } ],
+        "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bid": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_arid": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
+        "s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
+        "s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
+        "s_axi_arlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_arready": [ { "direction": "out" } ],
+        "s_axi_rid": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_rlast": [ { "direction": "out" } ],
+        "s_axi_rvalid": [ { "direction": "out" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axi_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
+        "m_axi_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awvalid": [ { "direction": "out" } ],
+        "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_wlast": [ { "direction": "out" } ],
+        "m_axi_wvalid": [ { "direction": "out" } ],
+        "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bready": [ { "direction": "out" } ],
+        "m_axi_araddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_arlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "m_axi_arsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_arburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axi_arlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
+        "m_axi_arcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_arregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_arqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_arvalid": [ { "direction": "out" } ],
+        "m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
+        "m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_rlast": [ { "direction": "in", "driver_value": "0x1" } ],
+        "m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_rready": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "128", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "16", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWID": [ { "physical_name": "s_axi_awid" } ],
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "s_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "s_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BID": [ { "physical_name": "s_axi_bid" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "ARID": [ { "physical_name": "s_axi_arid" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARLEN": [ { "physical_name": "s_axi_arlen" } ],
+            "ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
+            "ARBURST": [ { "physical_name": "s_axi_arburst" } ],
+            "ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
+            "ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
+            "ARPROT": [ { "physical_name": "s_axi_arprot" } ],
+            "ARREGION": [ { "physical_name": "s_axi_arregion" } ],
+            "ARQOS": [ { "physical_name": "s_axi_arqos" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "RID": [ { "physical_name": "s_axi_rid" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RLAST": [ { "physical_name": "s_axi_rlast" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ]
+          }
+        },
+        "M_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "m_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "m_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "m_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "m_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "m_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "m_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "m_axi_awready" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "m_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "m_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "m_axi_wready" } ],
+            "BRESP": [ { "physical_name": "m_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "m_axi_araddr" } ],
+            "ARLEN": [ { "physical_name": "m_axi_arlen" } ],
+            "ARSIZE": [ { "physical_name": "m_axi_arsize" } ],
+            "ARBURST": [ { "physical_name": "m_axi_arburst" } ],
+            "ARLOCK": [ { "physical_name": "m_axi_arlock" } ],
+            "ARCACHE": [ { "physical_name": "m_axi_arcache" } ],
+            "ARPROT": [ { "physical_name": "m_axi_arprot" } ],
+            "ARREGION": [ { "physical_name": "m_axi_arregion" } ],
+            "ARQOS": [ { "physical_name": "m_axi_arqos" } ],
+            "ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "m_axi_arready" } ],
+            "RDATA": [ { "physical_name": "m_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "m_axi_rresp" } ],
+            "RLAST": [ { "physical_name": "m_axi_rlast" } ],
+            "RVALID": [ { "physical_name": "m_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "m_axi_rready" } ]
+          }
+        },
+        "SI_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "SI_RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci

@@ -0,0 +1,296 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_auto_pc_0",
+    "cell_name": "ps8_axi_periph/s00_couplers/auto_pc",
+    "component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
+    "ip_revision": "32",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0",
+    "parameters": {
+      "component_parameters": {
+        "SI_PROTOCOL": [ { "value": "AXI4", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_auto_pc_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IGNORE_ID": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
+        "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
+        "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
+        "s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
+        "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
+        "s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
+        "s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
+        "s_axi_arlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_arready": [ { "direction": "out" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_rlast": [ { "direction": "out" } ],
+        "s_axi_rvalid": [ { "direction": "out" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awvalid": [ { "direction": "out" } ],
+        "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_wvalid": [ { "direction": "out" } ],
+        "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bready": [ { "direction": "out" } ],
+        "m_axi_araddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_arvalid": [ { "direction": "out" } ],
+        "m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
+        "m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_rready": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "s_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "s_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARLEN": [ { "physical_name": "s_axi_arlen" } ],
+            "ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
+            "ARBURST": [ { "physical_name": "s_axi_arburst" } ],
+            "ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
+            "ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
+            "ARPROT": [ { "physical_name": "s_axi_arprot" } ],
+            "ARREGION": [ { "physical_name": "s_axi_arregion" } ],
+            "ARQOS": [ { "physical_name": "s_axi_arqos" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RLAST": [ { "physical_name": "s_axi_rlast" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ]
+          }
+        },
+        "M_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
+            "AWPROT": [ { "physical_name": "m_axi_awprot" } ],
+            "AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "m_axi_awready" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "m_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "m_axi_wready" } ],
+            "BRESP": [ { "physical_name": "m_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "m_axi_araddr" } ],
+            "ARPROT": [ { "physical_name": "m_axi_arprot" } ],
+            "ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "m_axi_arready" } ],
+            "RDATA": [ { "physical_name": "m_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "m_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "m_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "m_axi_rready" } ]
+          }
+        },
+        "CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.xci

@@ -0,0 +1,294 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_axi_spi_engine_0",
+    "cell_name": "axi_spi_engine",
+    "component_reference": "analog.com:user:axi_spi_engine:1.0",
+    "ip_revision": "1",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0",
+    "parameters": {
+      "component_parameters": {
+        "CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MM_IF_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "NUM_OFFLOAD": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CFG_INFO_0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CFG_INFO_1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CFG_INFO_2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CFG_INFO_3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_axi_spi_engine_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "MM_IF_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "NUM_OFFLOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CFG_INFO_0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CFG_INFO_1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CFG_INFO_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CFG_INFO_3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "1" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_aresetn": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awready": [ { "direction": "out", "driver_value": "0" } ],
+        "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wready": [ { "direction": "out", "driver_value": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out", "driver_value": "0" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arready": [ { "direction": "out", "driver_value": "0" } ],
+        "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_rvalid": [ { "direction": "out", "driver_value": "0" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "irq": [ { "direction": "out" } ],
+        "spi_clk": [ { "direction": "in" } ],
+        "spi_resetn": [ { "direction": "out" } ],
+        "cmd_ready": [ { "direction": "in" } ],
+        "cmd_valid": [ { "direction": "out" } ],
+        "cmd_data": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
+        "sdo_data_ready": [ { "direction": "in", "driver_value": "0" } ],
+        "sdo_data_valid": [ { "direction": "out" } ],
+        "sdo_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "sdi_data_ready": [ { "direction": "out" } ],
+        "sdi_data_valid": [ { "direction": "in", "driver_value": "0" } ],
+        "sdi_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "sync_ready": [ { "direction": "out" } ],
+        "sync_valid": [ { "direction": "in" } ],
+        "sync_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "s_axi": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "s_axi",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARPROT": [ { "physical_name": "s_axi_arprot" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ]
+          }
+        },
+        "s_axi_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "s_axi_aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        },
+        "spi_engine_ctrl": {
+          "vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
+          "abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
+          "mode": "master",
+          "port_maps": {
+            "cmd_ready": [ { "physical_name": "cmd_ready" } ],
+            "cmd_valid": [ { "physical_name": "cmd_valid" } ],
+            "cmd_data": [ { "physical_name": "cmd_data" } ],
+            "sdo_ready": [ { "physical_name": "sdo_data_ready" } ],
+            "sdo_valid": [ { "physical_name": "sdo_data_valid" } ],
+            "sdo_data": [ { "physical_name": "sdo_data" } ],
+            "sdi_ready": [ { "physical_name": "sdi_data_ready" } ],
+            "sdi_valid": [ { "physical_name": "sdi_data_valid" } ],
+            "sdi_data": [ { "physical_name": "sdi_data" } ],
+            "sync_ready": [ { "physical_name": "sync_ready" } ],
+            "sync_valid": [ { "physical_name": "sync_valid" } ],
+            "sync_data": [ { "physical_name": "sync_data" } ]
+          }
+        },
+        "spi_engine_ctrl_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "spi_clk" } ]
+          }
+        },
+        "spi_engine_ctrl_signal_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "spi_resetn" } ]
+          }
+        },
+        "spi_engine_offload_ctrl0_s_axi_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "spi_engine_offload_ctrl0_s_axi_signal_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "s_axi": {
+          "address_blocks": {
+            "axi_lite": {
+              "base_address": "0",
+              "range": "65536"
+            }
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_pl_clk_0/system_bd_clk_wiz_pl_clk_0.xci

@@ -0,0 +1,658 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_clk_wiz_pl_clk_0",
+    "cell_name": "mts_clk_gen/clk_wiz_pl_clk",
+    "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+    "ip_revision": "14",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_clk_wiz_pl_clk_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_bd_clk_wiz_pl_clk_0", "resolve_type": "user", "usage": "all" } ],
+        "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+        "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+        "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_PHASE_ALIGNMENT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_IN_FREQ": [ { "value": "245.76", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+        "PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "user", "usage": "all" } ],
+        "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+        "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+        "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SECONDARY_IN_FREQ": [ { "value": "100.000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+        "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+        "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN1_JITTER_PS": [ { "value": "40.69", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_USED": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "NUM_OUT_CLKS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+        "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+        "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+        "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+        "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+        "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+        "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+        "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+        "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+        "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+        "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+        "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "245.76", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT2_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT3_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT4_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT5_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT6_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT7_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+        "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+        "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
+        "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+        "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+        "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+        "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+        "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+        "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKIN1_PERIOD": [ { "value": "4.069", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+        "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+        "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+        "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_JITTER": [ { "value": "85.228", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_PHASE_ERROR": [ { "value": "77.902", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_JITTER": [ { "value": "101.652", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_PHASE_ERROR": [ { "value": "77.902", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+        "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+        "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "c_component_name": [ { "value": "system_bd_clk_wiz_pl_clk_0", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_PHASE_ALIGNMENT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_FREQ": [ { "value": "245.76", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW0": [ { "value": "Input Clock   Freq (MHz)    Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW1": [ { "value": "__primary__________245.76____________0.010", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0A": [ { "value": " Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0B": [ { "value": "  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__245.76000______0.000______50.0_______85.228_____77.902", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "245.76", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_OUT_FREQ": [ { "value": "245.76000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN1_PERIOD": [ { "value": "4.069", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+        "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+        "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+        "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+        "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+        "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+        "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+        "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+        "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKIN1_JITTER_PS": [ { "value": "40.69", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+        "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE2_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE3_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE4_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE5_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE6_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE7_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "245.76000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_M_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MIN": [ { "value": "800.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MAX": [ { "value": "1600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "14" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_clk_wiz_pl_clk_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clk_in1": [ { "direction": "in" } ],
+        "clk_out1": [ { "direction": "out" } ],
+        "locked": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "clock_CLK_IN1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_pl_clk_0_IBUF_OUT", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "value_permission": "bd", "usage": "all", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_IN1": [ { "physical_name": "clk_in1" } ]
+          }
+        },
+        "clock_CLK_OUT1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_clk_wiz_pl_clk_0_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_ps8_axi_periph_0/system_bd_ps8_axi_periph_0.xci

@@ -0,0 +1,353 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_ps8_axi_periph_0",
+    "cell_name": "ps8_axi_periph",
+    "component_reference": "xilinx.com:ip:axi_interconnect:2.1",
+    "ip_revision": "33",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_ps8_axi_periph_0",
+    "parameters": {
+      "component_parameters": {
+        "NUM_SI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_MI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "XBAR_DATA_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PCHK_WAITS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PCHK_MAX_RD_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PCHK_MAX_WR_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SYNCHRONIZATION_STAGES": [ { "value": "3", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M00_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M01_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M02_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M03_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M04_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M05_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M06_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M07_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M08_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M09_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M10_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M11_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M12_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M13_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M14_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M16_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M17_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M18_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M19_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M20_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M21_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M22_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M23_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M24_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M25_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M26_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M27_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M28_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M29_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M30_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M31_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M32_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M33_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M34_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M35_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M36_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M37_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M38_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M39_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M40_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M41_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M42_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M43_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M44_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M45_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M46_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M47_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M48_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M49_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M50_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M51_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M52_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M53_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M54_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M55_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M56_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M57_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M58_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M59_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M60_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M61_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M62_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M63_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M00_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M01_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M07_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M08_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M09_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M10_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M11_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M12_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M13_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M14_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M15_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M16_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M17_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M18_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M19_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M20_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M21_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M22_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M23_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M24_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M25_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M26_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M27_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M28_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M29_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M30_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M31_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M32_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M33_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M34_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M35_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M36_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M37_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M38_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M39_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M40_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M41_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M42_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M43_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M44_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M45_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M46_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M47_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M48_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M49_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M50_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M51_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M52_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M53_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M54_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M55_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M56_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M57_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M58_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M59_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M60_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M61_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M62_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M63_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S00_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S01_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S02_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S03_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S04_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S05_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S06_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S07_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S08_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S09_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S10_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S11_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S12_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S13_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S14_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S00_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S01_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S07_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S08_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S09_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S10_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S11_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S12_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S13_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S14_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S15_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M00_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M01_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M02_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M03_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M04_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M05_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M06_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M07_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M08_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M09_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M10_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M11_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M12_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M13_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M14_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M15_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M16_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M17_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M18_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M19_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M20_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M21_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M22_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M23_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M24_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M25_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M26_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M27_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M28_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M29_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M30_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M31_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M32_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M33_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M34_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M35_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M36_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M37_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M38_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M39_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M40_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M41_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M42_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M43_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M44_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M45_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M46_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M47_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M48_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M49_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M50_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M51_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M52_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M53_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M54_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M55_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M56_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M57_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M58_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M59_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M60_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M61_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M62_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M63_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M00_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M01_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M02_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M03_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M04_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M05_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M06_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M07_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M08_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M09_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M10_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M11_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M12_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M13_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M14_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M15_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M16_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M17_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M18_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M19_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M20_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M21_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M22_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M23_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M24_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M25_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M26_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M27_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M28_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M29_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M30_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M31_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M32_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M33_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M34_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M35_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M36_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M37_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M38_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M39_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M40_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M41_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M42_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M43_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M44_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M45_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M46_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M47_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M48_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M49_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M50_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M51_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M52_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M53_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M54_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M55_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M56_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M57_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M58_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M59_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M60_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M61_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M62_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M63_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S00_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S01_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S02_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S03_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S04_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S05_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S06_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S07_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S08_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S09_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S10_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S11_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S12_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S13_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S14_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S15_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_ps8_axi_periph_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator_AppCore" } ],
+        "IPREVISION": [ { "value": "33" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_ps8_axi_periph_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_rst_ps8_96M_0/system_bd_rst_ps8_96M_0.xci

@@ -0,0 +1,196 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_rst_ps8_96M_0",
+    "cell_name": "rst_ps8_96M",
+    "component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
+    "ip_revision": "15",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps8_96M_0",
+    "parameters": {
+      "component_parameters": {
+        "C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_AUX_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_EXT_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_rst_ps8_96M_0", "resolve_type": "user", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "15" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps8_96M_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "slowest_sync_clk": [ { "direction": "in" } ],
+        "ext_reset_in": [ { "direction": "in" } ],
+        "aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
+        "mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
+        "dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
+        "mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
+        "bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
+        "peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
+      },
+      "interfaces": {
+        "clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "slowest_sync_clk" } ]
+          }
+        },
+        "ext_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "ext_reset_in" } ]
+          }
+        },
+        "aux_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aux_reset_in" } ]
+          }
+        },
+        "dbg_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "mb_debug_sys_rst" } ]
+          }
+        },
+        "mb_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "mb_reset" } ]
+          }
+        },
+        "bus_struct_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "bus_struct_reset" } ]
+          }
+        },
+        "interconnect_low_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "interconnect_aresetn" } ]
+          }
+        },
+        "peripheral_high_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "peripheral_reset" } ]
+          }
+        },
+        "peripheral_low_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "peripheral_aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.xci

@@ -0,0 +1,176 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_spi_engine_execution_0",
+    "cell_name": "spi_engine_execution",
+    "component_reference": "analog.com:user:spi_engine_execution:1.0",
+    "ip_revision": "1",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0",
+    "parameters": {
+      "component_parameters": {
+        "NUM_OF_CS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "ECHO_SCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SDI_DELAY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_spi_engine_execution_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "NUM_OF_CS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "1" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clk": [ { "direction": "in" } ],
+        "resetn": [ { "direction": "in" } ],
+        "active": [ { "direction": "out" } ],
+        "cmd_ready": [ { "direction": "out" } ],
+        "cmd_valid": [ { "direction": "in" } ],
+        "cmd": [ { "direction": "in", "size_left": "15", "size_right": "0" } ],
+        "sdo_data_valid": [ { "direction": "in", "driver_value": "0" } ],
+        "sdo_data_ready": [ { "direction": "out" } ],
+        "sdo_data": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
+        "sdi_data_ready": [ { "direction": "in", "driver_value": "0" } ],
+        "sdi_data_valid": [ { "direction": "out" } ],
+        "sdi_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "sync_ready": [ { "direction": "in" } ],
+        "sync_valid": [ { "direction": "out" } ],
+        "sync": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "sclk": [ { "direction": "out" } ],
+        "sdo": [ { "direction": "out" } ],
+        "sdo_t": [ { "direction": "out" } ],
+        "sdi": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
+        "cs": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
+        "three_wire": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "ctrl": {
+          "vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
+          "abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "cmd_ready": [ { "physical_name": "cmd_ready" } ],
+            "cmd_valid": [ { "physical_name": "cmd_valid" } ],
+            "cmd_data": [ { "physical_name": "cmd" } ],
+            "sdo_ready": [ { "physical_name": "sdo_data_ready" } ],
+            "sdo_valid": [ { "physical_name": "sdo_data_valid" } ],
+            "sdo_data": [ { "physical_name": "sdo_data" } ],
+            "sdi_ready": [ { "physical_name": "sdi_data_ready" } ],
+            "sdi_valid": [ { "physical_name": "sdi_data_valid" } ],
+            "sdi_data": [ { "physical_name": "sdi_data" } ],
+            "sync_ready": [ { "physical_name": "sync_ready" } ],
+            "sync_valid": [ { "physical_name": "sync_valid" } ],
+            "sync_data": [ { "physical_name": "sync" } ]
+          }
+        },
+        "ctrl_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "clk" } ]
+          }
+        },
+        "ctrl_signal_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "resetn" } ]
+          }
+        },
+        "spi": {
+          "vlnv": "analog.com:interface:spi_engine:1.0",
+          "abstraction_type": "analog.com:interface:spi_engine_rtl:1.0",
+          "mode": "master",
+          "port_maps": {
+            "sclk": [ { "physical_name": "sclk" } ],
+            "sdi": [ { "physical_name": "sdi" } ],
+            "sdo": [ { "physical_name": "sdo" } ],
+            "sdo_t": [ { "physical_name": "sdo_t" } ],
+            "three_wire": [ { "physical_name": "three_wire" } ],
+            "cs": [ { "physical_name": "cs" } ]
+          }
+        },
+        "spi_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "clk" } ]
+          }
+        },
+        "spi_signal_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "resetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_util_bufg_pl_clk_0/system_bd_util_bufg_pl_clk_0.xci

@@ -0,0 +1,102 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_util_bufg_pl_clk_0",
+    "cell_name": "mts_clk_gen/util_bufg_pl_clk",
+    "component_reference": "xilinx.com:ip:util_ds_buf:2.2",
+    "ip_revision": "32",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_util_bufg_pl_clk_0",
+    "parameters": {
+      "component_parameters": {
+        "C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_BUF_TYPE": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_util_bufg_pl_clk_0", "resolve_type": "user", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
+        "FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_BUF_TYPE": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
+        "C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_util_bufg_pl_clk_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "BUFG_I": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "BUFG_O": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "BUFG_I": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_pl_clk_0_IBUF_OUT", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "BUFG_I" } ]
+          }
+        },
+        "BUFG_O": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_pl_clk_0_IBUF_OUT", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "BUFG_O" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_pl_clk_0/system_bd_util_ds_buf_pl_clk_0.xci

@@ -0,0 +1,99 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_util_ds_buf_pl_clk_0",
+    "cell_name": "mts_clk_gen/util_ds_buf_pl_clk",
+    "component_reference": "xilinx.com:ip:util_ds_buf:2.2",
+    "ip_revision": "32",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_pl_clk_0",
+    "parameters": {
+      "component_parameters": {
+        "C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_util_ds_buf_pl_clk_0", "resolve_type": "user", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
+        "FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "generated", "usage": "all" } ],
+        "C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
+        "C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_pl_clk_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "IBUF_DS_P": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "IBUF_DS_N": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "IBUF_OUT": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "CLK_IN_D": {
+          "vlnv": "xilinx.com:interface:diff_clock:1.0",
+          "abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "DIFF_CLK_IN_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "CAN_DEBUG": [ { "value": "false", "value_permission": "bd", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_P": [ { "physical_name": "IBUF_DS_P" } ],
+            "CLK_N": [ { "physical_name": "IBUF_DS_N" } ]
+          }
+        },
+        "IBUF_OUT": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_pl_clk_0_IBUF_OUT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "IBUF_OUT" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_pl_sysref_0/system_bd_util_ds_buf_pl_sysref_0.xci

@@ -0,0 +1,99 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_util_ds_buf_pl_sysref_0",
+    "cell_name": "mts_clk_gen/util_ds_buf_pl_sysref",
+    "component_reference": "xilinx.com:ip:util_ds_buf:2.2",
+    "ip_revision": "32",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_pl_sysref_0",
+    "parameters": {
+      "component_parameters": {
+        "C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_util_ds_buf_pl_sysref_0", "resolve_type": "user", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
+        "FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "generated", "usage": "all" } ],
+        "C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
+        "C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_pl_sysref_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "IBUF_DS_P": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "IBUF_DS_N": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "IBUF_OUT": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "CLK_IN_D": {
+          "vlnv": "xilinx.com:interface:diff_clock:1.0",
+          "abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "DIFF_CLK_IN_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "CAN_DEBUG": [ { "value": "false", "value_permission": "bd", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_P": [ { "physical_name": "IBUF_DS_P" } ],
+            "CLK_N": [ { "physical_name": "IBUF_DS_N" } ]
+          }
+        },
+        "IBUF_OUT": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_pl_sysref_0_IBUF_OUT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "IBUF_OUT" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xlconcat_irq_0/system_bd_xlconcat_irq_0.xci

@@ -0,0 +1,308 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_xlconcat_irq_0",
+    "cell_name": "xlconcat_irq",
+    "component_reference": "xilinx.com:ip:xlconcat:2.1",
+    "ip_revision": "6",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_irq_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_bd_xlconcat_irq_0", "resolve_type": "user", "usage": "all" } ],
+        "NUM_PORTS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN22_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN23_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN24_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN25_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN26_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN27_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN28_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN29_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN30_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN31_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN32_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN33_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN34_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN35_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN36_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN37_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN38_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN39_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN40_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN41_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN42_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN43_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN44_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN45_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN46_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN47_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN48_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN49_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN50_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN51_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN52_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN53_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN54_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN55_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN56_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN57_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN58_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN59_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN60_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN61_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN62_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN63_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN64_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN65_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN66_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN67_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN68_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN69_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN70_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN71_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN72_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN73_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN74_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN75_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN76_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN77_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN78_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN79_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN80_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN81_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN82_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN83_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN84_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN85_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN86_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN87_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN88_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN89_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN90_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN91_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN92_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN93_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN94_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN95_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN96_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN97_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN98_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN99_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN100_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN101_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN102_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN103_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN104_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN105_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN106_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN107_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN108_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN109_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN110_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN111_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN112_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN113_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN114_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN115_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN116_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN117_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN118_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN119_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN120_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN121_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN122_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN123_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN124_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN125_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN126_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN127_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "dout_width": [ { "value": "2", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "IN0_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN1_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN2_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN3_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN4_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN5_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN6_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN7_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN8_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN9_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN10_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN11_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN12_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN13_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN14_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN15_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN16_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN17_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN18_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN19_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN20_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN21_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN22_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN23_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN24_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN25_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN26_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN27_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN28_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN29_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN30_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN31_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN32_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN33_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN34_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN35_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN36_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN37_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN38_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN39_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN40_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN41_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN42_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN43_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN44_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN45_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN46_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN47_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN48_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN49_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN50_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN51_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN52_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN53_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN54_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN55_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN56_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN57_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN58_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN59_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN60_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN61_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN62_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN63_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN64_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN65_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN66_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN67_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN68_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN69_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN70_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN71_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN72_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN73_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN74_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN75_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN76_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN77_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN78_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN79_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN80_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN81_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN82_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN83_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN84_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN85_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN86_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN87_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN88_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN89_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN90_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN91_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN92_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN93_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN94_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN95_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN96_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN97_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN98_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN99_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN100_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN101_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN102_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN103_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN104_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN105_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN106_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN107_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN108_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN109_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN110_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN111_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN112_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN113_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN114_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN115_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN116_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN117_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN118_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN119_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN120_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN121_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN122_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN123_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN124_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN125_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN126_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "IN127_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "dout_width": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "NUM_PORTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "6" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_irq_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "dout": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xlconstant_0_0/system_bd_xlconstant_0_0.xci

@@ -0,0 +1,50 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_xlconstant_0_0",
+    "cell_name": "mts_clk_gen/xlconstant_0",
+    "component_reference": "xilinx.com:ip:xlconstant:1.1",
+    "ip_revision": "9",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_xlconstant_0_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_bd_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
+        "CONST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "CONST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CONST_VAL": [ { "value": "0x0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "9" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_xlconstant_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_mts_sysref_0/system_bd_xpm_cdc_gen_mts_sysref_0.xci

@@ -0,0 +1,126 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_xpm_cdc_gen_mts_sysref_0",
+    "cell_name": "mts_clk_gen/xpm_cdc_gen_mts_sysref",
+    "component_reference": "xilinx.com:ip:xpm_cdc_gen:1.0",
+    "ip_revision": "4",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_mts_sysref_0",
+    "parameters": {
+      "component_parameters": {
+        "CDC_TYPE": [ { "value": "xpm_cdc_single", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "SRC_CLK_PERIOD": [ { "value": "5000", "resolve_type": "user", "usage": "all" } ],
+        "DEST_CLK_PERIOD": [ { "value": "2500", "resolve_type": "user", "usage": "all" } ],
+        "SIM_ASSERT_CHK": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "DEST_SYNC_FF": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INIT_SYNC_FF": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SRC_INPUT_REG": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SIM_LOSSLESS_GRAY_CHK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "DEST_EXT_HSK": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "REG_OUTPUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RST_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "INIT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SRC_SYNC_FF": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RST_ACTIVE_HIGH": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_xpm_cdc_gen_mts_sysref_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_CDC_TYPE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SRC_CLK_PERIOD": [ { "value": "5000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DEST_CLK_PERIOD": [ { "value": "2500", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SIM_ASSERT_CHK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DEST_SYNC_FF": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "INIT_SYNC_FF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SRC_INPUT_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "REG_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "SIM_LOSSLESS_GRAY_CHK": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "SRC_SYNC_FF": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "DEST_EXT_HSK": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "RST_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "INIT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "RST_ACTIVE_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "4" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_mts_sysref_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "src_clk": [ { "direction": "in", "driver_value": "1" } ],
+        "dest_clk": [ { "direction": "in", "driver_value": "1" } ],
+        "src_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
+        "dest_out": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "dest_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_clk_wiz_pl_clk_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "dest_clk" } ]
+          }
+        },
+        "src_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "src_clk" } ]
+          }
+        },
+        "RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_pl_sysref_0/system_bd_xpm_cdc_gen_pl_sysref_0.xci

@@ -0,0 +1,126 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_xpm_cdc_gen_pl_sysref_0",
+    "cell_name": "mts_clk_gen/xpm_cdc_gen_pl_sysref",
+    "component_reference": "xilinx.com:ip:xpm_cdc_gen:1.0",
+    "ip_revision": "4",
+    "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_pl_sysref_0",
+    "parameters": {
+      "component_parameters": {
+        "CDC_TYPE": [ { "value": "xpm_cdc_single", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "SRC_CLK_PERIOD": [ { "value": "5000", "resolve_type": "user", "usage": "all" } ],
+        "DEST_CLK_PERIOD": [ { "value": "2500", "resolve_type": "user", "usage": "all" } ],
+        "SIM_ASSERT_CHK": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "DEST_SYNC_FF": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INIT_SYNC_FF": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SRC_INPUT_REG": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SIM_LOSSLESS_GRAY_CHK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "DEST_EXT_HSK": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "REG_OUTPUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RST_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "INIT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SRC_SYNC_FF": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RST_ACTIVE_HIGH": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_xpm_cdc_gen_pl_sysref_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_CDC_TYPE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SRC_CLK_PERIOD": [ { "value": "5000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DEST_CLK_PERIOD": [ { "value": "2500", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SIM_ASSERT_CHK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DEST_SYNC_FF": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "INIT_SYNC_FF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SRC_INPUT_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "REG_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "SIM_LOSSLESS_GRAY_CHK": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "SRC_SYNC_FF": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "DEST_EXT_HSK": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "RST_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "INIT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "RST_ACTIVE_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "4" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_pl_sysref_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "src_clk": [ { "direction": "in", "driver_value": "1" } ],
+        "dest_clk": [ { "direction": "in", "driver_value": "1" } ],
+        "src_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
+        "dest_out": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "dest_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_pl_clk_0_IBUF_OUT", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "dest_clk" } ]
+          }
+        },
+        "src_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "src_clk" } ]
+          }
+        },
+        "RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/system_bd.bda

@@ -0,0 +1,249 @@
+{
+    "graphjs": {
+        "version": "1.0",
+        "keys": [
+            {
+                "abrv": "VH",
+                "name": "vert_hid",
+                "type": "int",
+                "for": "node"
+            },
+            {
+                "abrv": "VM",
+                "name": "vert_name",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "VT",
+                "name": "vert_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "BA",
+                "name": "base_addr",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "HA",
+                "name": "high_addr",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "BP",
+                "name": "base_param",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "HP",
+                "name": "high_param",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MA",
+                "name": "master_addrspace",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MX",
+                "name": "master_instance",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MI",
+                "name": "master_interface",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MS",
+                "name": "master_segment",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MV",
+                "name": "master_vlnv",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SX",
+                "name": "slave_instance",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SI",
+                "name": "slave_interface",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MM",
+                "name": "slave_memmap",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SS",
+                "name": "slave_segment",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SV",
+                "name": "slave_vlnv",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "TM",
+                "name": "memory_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "TU",
+                "name": "usage_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "LT",
+                "name": "lock_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "BT",
+                "name": "boot_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "EH",
+                "name": "edge_hid",
+                "type": "int",
+                "for": "edge"
+            }
+        ],
+        "vertice_type_order": [
+            {
+                "abrv": "BC",
+                "desc": "Block Container"
+            },
+            {
+                "abrv": "PR",
+                "desc": "Parital Reference"
+            },
+            {
+                "abrv": "VR",
+                "desc": "Variant"
+            },
+            {
+                "abrv": "PM",
+                "desc": "Variant Permutations"
+            },
+            {
+                "abrv": "CX",
+                "desc": "Boundary Connection"
+            },
+            {
+                "abrv": "AC",
+                "desc": "Assignment Coordinate"
+            },
+            {
+                "abrv": "ACE",
+                "desc": "Excluded Assign Coordinate"
+            },
+            {
+                "abrv": "APX",
+                "desc": "Boundary Aperture"
+            },
+            {
+                "abrv": "CIP",
+                "desc": "High level Processing System"
+            }
+        ],
+        "vertices": {
+            "V0": {
+                "VM": "system_bd",
+                "VT": "BC"
+            },
+            "V1": {
+                "VH": "2",
+                "VM": "system_bd",
+                "VT": "VR"
+            },
+            "V2": {
+                "VH": "2",
+                "VT": "PM",
+                "TU": "active"
+            },
+            "V3": {
+                "VT": "AC",
+                "BA": "0x00A0000000",
+                "HA": "0x00A000FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/zynq_ultra_ps_e",
+                "MI": "M_AXI_HPM0_FPD",
+                "MS": "SEG_axi_spi_engine_axi_lite",
+                "MV": "xilinx.com:ip:zynq_ultra_ps_e:3.5",
+                "SX": "/axi_spi_engine/axi_spi_engine",
+                "SI": "s_axi",
+                "SS": "axi_lite",
+                "SV": "analog.com:user:axi_spi_engine:1.0",
+                "TM": "both",
+                "TU": "register"
+            },
+            "V4": {
+                "VT": "AC",
+                "BA": "0x00A0040000",
+                "HA": "0x00A007FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/zynq_ultra_ps_e",
+                "MI": "M_AXI_HPM0_FPD",
+                "MS": "SEG_usp_rf_data_converter_Reg",
+                "MV": "xilinx.com:ip:zynq_ultra_ps_e:3.5",
+                "SX": "/usp_rf_data_converter",
+                "SI": "s_axi",
+                "SS": "Reg",
+                "SV": "xilinx.com:ip:usp_rf_data_converter:2.6",
+                "TM": "both",
+                "TU": "register"
+            }
+        },
+        "edges": [
+            {
+                "src": "V0",
+                "trg": "V1"
+            },
+            {
+                "src": "V1",
+                "trg": "V2"
+            },
+            {
+                "src": "V3",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V4",
+                "trg": "V2",
+                "EH": "2"
+            }
+        ]
+    }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ui/bd_2942602e.ui

@@ -0,0 +1,34 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.0",
+   "Default View_TopLeft":"-365,-139",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
+#  -string -flagsOSRD
+preplace port pl_clk -pg 1 -lvl 0 -x -10 -y 150 -defaultsOSRD
+preplace port pl_sysref -pg 1 -lvl 0 -x -10 -y 250 -defaultsOSRD
+preplace port port-id_sys_clk -pg 1 -lvl 5 -x 1050 -y 250 -defaultsOSRD
+preplace port port-id_sys_rstn -pg 1 -lvl 5 -x 1050 -y 410 -defaultsOSRD
+preplace portBus mts_sysref -pg 1 -lvl 5 -x 1050 -y 330 -defaultsOSRD
+preplace inst util_bufg_pl_clk -pg 1 -lvl 2 -x 400 -y 150 -defaultsOSRD
+preplace inst util_ds_buf_pl_clk -pg 1 -lvl 1 -x 140 -y 150 -defaultsOSRD
+preplace inst util_ds_buf_pl_sysref -pg 1 -lvl 2 -x 400 -y 250 -defaultsOSRD
+preplace inst clk_wiz_pl_clk -pg 1 -lvl 3 -x 660 -y 400 -defaultsOSRD
+preplace inst xpm_cdc_gen_pl_sysref -pg 1 -lvl 3 -x 660 -y 230 -defaultsOSRD
+preplace inst xpm_cdc_gen_mts_sysref -pg 1 -lvl 4 -x 910 -y 330 -defaultsOSRD
+preplace inst xlconstant_0 -pg 1 -lvl 2 -x 400 -y 50 -defaultsOSRD
+preplace netloc clk_wiz_pl_clk_clk_out1 1 3 2 790 250 NJ
+preplace netloc clk_wiz_pl_clk_locked 1 3 2 NJ 410 NJ
+preplace netloc util_bufg_pl_clk_BUFG_O 1 2 1 530 150n
+preplace netloc util_ds_buf_pl_clk_IBUF_OUT 1 1 1 NJ 150
+preplace netloc util_ds_buf_pl_sysref_IBUF_OUT 1 2 1 NJ 250
+preplace netloc xlconstant_0_dout 1 2 2 540 310 NJ
+preplace netloc xpm_cdc_gen_mts_sysref_dest_out 1 4 1 NJ 330
+preplace netloc xpm_cdc_gen_pl_sysref_dest_out 1 3 1 780 230n
+preplace netloc Conn1 1 0 1 NJ 150
+preplace netloc Conn2 1 0 2 NJ 250 NJ
+levelinfo -pg 1 -10 140 400 660 910 1050
+pagesize -pg 1 -db -bbox -sgen -130 -10 1220 470
+"
+}
+

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui

@@ -0,0 +1,176 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"0.510573",
+   "Default View_TopLeft":"-736,133",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
+#  -string -flagsOSRD
+preplace port adc1_clk -pg 1 -lvl 0 -x 0 -y 700 -defaultsOSRD
+preplace port dac0_clk -pg 1 -lvl 0 -x 0 -y 720 -defaultsOSRD
+preplace port m00_axis -pg 1 -lvl 3 -x 1130 -y 630 -defaultsOSRD
+preplace port m01_axis -pg 1 -lvl 3 -x 1130 -y 650 -defaultsOSRD
+preplace port m02_axis -pg 1 -lvl 3 -x 1130 -y 670 -defaultsOSRD
+preplace port m03_axis -pg 1 -lvl 3 -x 1130 -y 690 -defaultsOSRD
+preplace port m10_axis -pg 1 -lvl 3 -x 1130 -y 710 -defaultsOSRD
+preplace port m11_axis -pg 1 -lvl 3 -x 1130 -y 730 -defaultsOSRD
+preplace port m12_axis -pg 1 -lvl 3 -x 1130 -y 750 -defaultsOSRD
+preplace port m13_axis -pg 1 -lvl 3 -x 1130 -y 770 -defaultsOSRD
+preplace port m20_axis -pg 1 -lvl 3 -x 1130 -y 790 -defaultsOSRD
+preplace port m21_axis -pg 1 -lvl 3 -x 1130 -y 810 -defaultsOSRD
+preplace port m22_axis -pg 1 -lvl 3 -x 1130 -y 830 -defaultsOSRD
+preplace port m23_axis -pg 1 -lvl 3 -x 1130 -y 850 -defaultsOSRD
+preplace port m30_axis -pg 1 -lvl 3 -x 1130 -y 870 -defaultsOSRD
+preplace port m31_axis -pg 1 -lvl 3 -x 1130 -y 890 -defaultsOSRD
+preplace port m32_axis -pg 1 -lvl 3 -x 1130 -y 910 -defaultsOSRD
+preplace port m33_axis -pg 1 -lvl 3 -x 1130 -y 930 -defaultsOSRD
+preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 1530 -defaultsOSRD
+preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 1550 -defaultsOSRD
+preplace port s00_axis -pg 1 -lvl 0 -x 0 -y 540 -defaultsOSRD
+preplace port s02_axis -pg 1 -lvl 0 -x 0 -y 560 -defaultsOSRD
+preplace port s10_axis -pg 1 -lvl 0 -x 0 -y 580 -defaultsOSRD
+preplace port s12_axis -pg 1 -lvl 0 -x 0 -y 600 -defaultsOSRD
+preplace port s20_axis -pg 1 -lvl 0 -x 0 -y 620 -defaultsOSRD
+preplace port s22_axis -pg 1 -lvl 0 -x 0 -y 640 -defaultsOSRD
+preplace port s30_axis -pg 1 -lvl 0 -x 0 -y 660 -defaultsOSRD
+preplace port s32_axis -pg 1 -lvl 0 -x 0 -y 680 -defaultsOSRD
+preplace port sysref_in -pg 1 -lvl 0 -x 0 -y 900 -defaultsOSRD
+preplace port vin0_01 -pg 1 -lvl 0 -x 0 -y 740 -defaultsOSRD
+preplace port vin0_23 -pg 1 -lvl 0 -x 0 -y 760 -defaultsOSRD
+preplace port vin1_01 -pg 1 -lvl 0 -x 0 -y 780 -defaultsOSRD
+preplace port vin1_23 -pg 1 -lvl 0 -x 0 -y 800 -defaultsOSRD
+preplace port vin2_01 -pg 1 -lvl 0 -x 0 -y 820 -defaultsOSRD
+preplace port vin2_23 -pg 1 -lvl 0 -x 0 -y 840 -defaultsOSRD
+preplace port vin3_01 -pg 1 -lvl 0 -x 0 -y 860 -defaultsOSRD
+preplace port vin3_23 -pg 1 -lvl 0 -x 0 -y 880 -defaultsOSRD
+preplace port vout00 -pg 1 -lvl 3 -x 1130 -y 950 -defaultsOSRD
+preplace port vout02 -pg 1 -lvl 3 -x 1130 -y 970 -defaultsOSRD
+preplace port vout10 -pg 1 -lvl 3 -x 1130 -y 990 -defaultsOSRD
+preplace port vout12 -pg 1 -lvl 3 -x 1130 -y 1010 -defaultsOSRD
+preplace port vout20 -pg 1 -lvl 3 -x 1130 -y 1030 -defaultsOSRD
+preplace port vout22 -pg 1 -lvl 3 -x 1130 -y 1050 -defaultsOSRD
+preplace port vout30 -pg 1 -lvl 3 -x 1130 -y 1070 -defaultsOSRD
+preplace port vout32 -pg 1 -lvl 3 -x 1130 -y 1090 -defaultsOSRD
+preplace port spi -pg 1 -lvl 3 -x 1130 -y 340 -defaultsOSRD
+preplace port port-id_clk_adc0 -pg 1 -lvl 3 -x 1130 -y 1110 -defaultsOSRD
+preplace port port-id_clk_adc1 -pg 1 -lvl 3 -x 1130 -y 1130 -defaultsOSRD
+preplace port port-id_clk_adc2 -pg 1 -lvl 3 -x 1130 -y 1150 -defaultsOSRD
+preplace port port-id_clk_adc3 -pg 1 -lvl 3 -x 1130 -y 1170 -defaultsOSRD
+preplace port port-id_clk_dac0 -pg 1 -lvl 3 -x 1130 -y 1190 -defaultsOSRD
+preplace port port-id_clk_dac1 -pg 1 -lvl 3 -x 1130 -y 1210 -defaultsOSRD
+preplace port port-id_clk_dac2 -pg 1 -lvl 3 -x 1130 -y 1230 -defaultsOSRD
+preplace port port-id_clk_dac3 -pg 1 -lvl 3 -x 1130 -y 1250 -defaultsOSRD
+preplace port port-id_m0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1100 -defaultsOSRD
+preplace port port-id_m0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1080 -defaultsOSRD
+preplace port port-id_m1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1140 -defaultsOSRD
+preplace port port-id_m1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1120 -defaultsOSRD
+preplace port port-id_m2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1180 -defaultsOSRD
+preplace port port-id_m2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1160 -defaultsOSRD
+preplace port port-id_m3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1220 -defaultsOSRD
+preplace port port-id_m3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1200 -defaultsOSRD
+preplace port port-id_ps_clk0 -pg 1 -lvl 3 -x 1130 -y 440 -defaultsOSRD
+preplace port port-id_s0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1260 -defaultsOSRD
+preplace port port-id_s0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1240 -defaultsOSRD
+preplace port port-id_s1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1300 -defaultsOSRD
+preplace port port-id_s1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1280 -defaultsOSRD
+preplace port port-id_s2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1340 -defaultsOSRD
+preplace port port-id_s2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1320 -defaultsOSRD
+preplace port port-id_s3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1380 -defaultsOSRD
+preplace port port-id_s3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1360 -defaultsOSRD
+preplace port port-id_spi_active -pg 1 -lvl 3 -x 1130 -y 360 -defaultsOSRD
+preplace port port-id_sys_clk -pg 1 -lvl 3 -x 1130 -y 470 -defaultsOSRD
+preplace port port-id_sys_rstn -pg 1 -lvl 3 -x 1130 -y 490 -defaultsOSRD
+preplace inst axi_spi_engine -pg 1 -lvl 2 -x 920 -y 360 -defaultsOSRD
+preplace inst mts_clk_gen -pg 1 -lvl 1 -x 370 -y 1540 -defaultsOSRD
+preplace inst ps8_axi_periph -pg 1 -lvl 1 -x 370 -y 340 -defaultsOSRD
+preplace inst rst_ps8_96M -pg 1 -lvl 2 -x 920 -y 140 -defaultsOSRD
+preplace inst usp_rf_data_converter -pg 1 -lvl 1 -x 370 -y 950 -defaultsOSRD
+preplace inst xlconcat_irq -pg 1 -lvl 2 -x 920 -y 560 -defaultsOSRD
+preplace inst zynq_ultra_ps_e -pg 1 -lvl 1 -x 370 -y 120 -defaultsOSRD
+preplace netloc axi_spi_engine_active_0 1 2 1 N 360
+preplace netloc axi_spi_engine_irq 1 1 2 740 270 1100
+preplace netloc m0_axis_aclk_0_1 1 0 1 NJ 1100
+preplace netloc m0_axis_aresetn_0_1 1 0 1 NJ 1080
+preplace netloc m1_axis_aclk_0_1 1 0 1 NJ 1140
+preplace netloc m1_axis_aresetn_0_1 1 0 1 NJ 1120
+preplace netloc m2_axis_aclk_0_1 1 0 1 NJ 1180
+preplace netloc m2_axis_aresetn_0_1 1 0 1 NJ 1160
+preplace netloc m3_axis_aclk_0_1 1 0 1 NJ 1220
+preplace netloc m3_axis_aresetn_0_1 1 0 1 NJ 1200
+preplace netloc mts_clk_gen_mts_sysref 1 0 2 20 1460 680
+preplace netloc mts_clk_gen_sys_clk 1 1 2 710 470 N
+preplace netloc mts_clk_gen_sys_rstn 1 1 2 730 490 N
+preplace netloc rst_ps8_96M_peripheral_aresetn 1 0 3 20 10 730 40 1100
+preplace netloc s0_axis_aclk_0_1 1 0 1 NJ 1260
+preplace netloc s0_axis_aresetn_0_1 1 0 1 NJ 1240
+preplace netloc s1_axis_aclk_0_1 1 0 1 NJ 1300
+preplace netloc s1_axis_aresetn_0_1 1 0 1 NJ 1280
+preplace netloc s2_axis_aclk_0_1 1 0 1 NJ 1340
+preplace netloc s2_axis_aresetn_0_1 1 0 1 NJ 1320
+preplace netloc s3_axis_aclk_0_1 1 0 1 NJ 1380
+preplace netloc s3_axis_aresetn_0_1 1 0 1 NJ 1360
+preplace netloc usp_rf_data_converter_clk_adc0 1 1 2 N 1110 N
+preplace netloc usp_rf_data_converter_clk_adc1 1 1 2 N 1130 N
+preplace netloc usp_rf_data_converter_clk_adc2 1 1 2 N 1150 N
+preplace netloc usp_rf_data_converter_clk_adc3 1 1 2 N 1170 N
+preplace netloc usp_rf_data_converter_clk_dac0 1 1 2 N 1190 N
+preplace netloc usp_rf_data_converter_clk_dac1 1 1 2 N 1210 N
+preplace netloc usp_rf_data_converter_clk_dac2 1 1 2 N 1230 N
+preplace netloc usp_rf_data_converter_clk_dac3 1 1 2 N 1250 N
+preplace netloc usp_rf_data_converter_irq 1 1 1 720 550n
+preplace netloc xlconcat_irq_dout 1 0 3 40 1450 N 1450 1100
+preplace netloc zynq_ultra_ps_e_pl_clk0 1 0 3 60 1440 700 440 N
+preplace netloc zynq_ultra_ps_e_pl_resetn0 1 1 1 N 120
+preplace netloc adc1_clk_1 1 0 1 NJ 700
+preplace netloc dac0_clk_1 1 0 1 NJ 720
+preplace netloc pl_clk_0_1 1 0 1 NJ 1530
+preplace netloc pl_sysref_0_1 1 0 1 NJ 1550
+preplace netloc ps8_axi_periph_M00_AXI 1 1 1 N 330
+preplace netloc ps8_axi_periph_M01_AXI 1 0 2 30 20 690
+preplace netloc s00_axis_0_1 1 0 1 NJ 540
+preplace netloc s02_axis_0_1 1 0 1 NJ 560
+preplace netloc s10_axis_0_1 1 0 1 NJ 580
+preplace netloc s12_axis_0_1 1 0 1 NJ 600
+preplace netloc s20_axis_0_1 1 0 1 NJ 620
+preplace netloc s22_axis_0_1 1 0 1 NJ 640
+preplace netloc s30_axis_0_1 1 0 1 NJ 660
+preplace netloc s32_axis_0_1 1 0 1 NJ 680
+preplace netloc sysref_in_1 1 0 1 NJ 900
+preplace netloc usp_rf_data_converter_m00_axis 1 1 2 N 630 N
+preplace netloc usp_rf_data_converter_m01_axis 1 1 2 N 650 N
+preplace netloc usp_rf_data_converter_m02_axis 1 1 2 N 670 N
+preplace netloc usp_rf_data_converter_m03_axis 1 1 2 N 690 N
+preplace netloc usp_rf_data_converter_m10_axis 1 1 2 N 710 N
+preplace netloc usp_rf_data_converter_m11_axis 1 1 2 N 730 N
+preplace netloc usp_rf_data_converter_m12_axis 1 1 2 N 750 N
+preplace netloc usp_rf_data_converter_m13_axis 1 1 2 N 770 N
+preplace netloc usp_rf_data_converter_m20_axis 1 1 2 N 790 N
+preplace netloc usp_rf_data_converter_m21_axis 1 1 2 N 810 N
+preplace netloc usp_rf_data_converter_m22_axis 1 1 2 N 830 N
+preplace netloc usp_rf_data_converter_m23_axis 1 1 2 N 850 N
+preplace netloc usp_rf_data_converter_m30_axis 1 1 2 N 870 N
+preplace netloc usp_rf_data_converter_m31_axis 1 1 2 N 890 N
+preplace netloc usp_rf_data_converter_m32_axis 1 1 2 N 910 N
+preplace netloc usp_rf_data_converter_m33_axis 1 1 2 N 930 N
+preplace netloc usp_rf_data_converter_vout00 1 1 2 N 950 N
+preplace netloc usp_rf_data_converter_vout02 1 1 2 N 970 N
+preplace netloc usp_rf_data_converter_vout10 1 1 2 N 990 N
+preplace netloc usp_rf_data_converter_vout12 1 1 2 N 1010 N
+preplace netloc usp_rf_data_converter_vout20 1 1 2 N 1030 N
+preplace netloc usp_rf_data_converter_vout22 1 1 2 N 1050 N
+preplace netloc usp_rf_data_converter_vout30 1 1 2 N 1070 N
+preplace netloc usp_rf_data_converter_vout32 1 1 2 N 1090 N
+preplace netloc vin0_01_1 1 0 1 NJ 740
+preplace netloc vin0_23_1 1 0 1 NJ 760
+preplace netloc vin1_01_1 1 0 1 NJ 780
+preplace netloc vin1_23_1 1 0 1 NJ 800
+preplace netloc vin2_01_0_1 1 0 1 NJ 820
+preplace netloc vin2_23_0_1 1 0 1 NJ 840
+preplace netloc vin3_01_0_1 1 0 1 NJ 860
+preplace netloc vin3_23_0_1 1 0 1 NJ 880
+preplace netloc zynq_ultra_ps_e_M_AXI_HPM0_FPD 1 0 2 50 30 680
+preplace netloc axi_spi_engine_spi_1 1 2 1 N 340
+levelinfo -pg 1 0 370 920 1130
+pagesize -pg 1 -db -bbox -sgen -170 0 1250 1610
+"
+}
+0

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui

@@ -0,0 +1,28 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.0",
+   "Default View_TopLeft":"-668,-290",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
+#  -string -flagsOSRD
+preplace port s_axi -pg 1 -lvl 0 -x 0 -y 50 -defaultsOSRD
+preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD
+preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y 90 -defaultsOSRD
+preplace port port-id_active -pg 1 -lvl 3 -x 530 -y 90 -defaultsOSRD
+preplace port port-id_spi_clk -pg 1 -lvl 0 -x 0 -y 110 -defaultsOSRD
+preplace port port-id_irq -pg 1 -lvl 3 -x 530 -y 160 -defaultsOSRD
+preplace inst spi_engine_execution -pg 1 -lvl 2 -x 410 -y 80 -defaultsOSRD
+preplace inst axi_spi_engine -pg 1 -lvl 1 -x 160 -y 80 -defaultsOSRD
+preplace netloc axi_spi_engine_irq 1 1 2 300J 160 NJ
+preplace netloc axi_spi_engine_spi_resetn 1 1 1 N 100
+preplace netloc s_axi_aclk_0_1 1 0 2 20 170 310J
+preplace netloc s_axi_aresetn_1 1 0 1 NJ 90
+preplace netloc spi_clk_0_1 1 0 1 NJ 110
+preplace netloc spi_engine_execution_active 1 2 1 NJ 90
+preplace netloc Conn1 1 0 1 NJ 50
+preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N 60
+levelinfo -pg 1 0 160 410 530
+pagesize -pg 1 -db -bbox -sgen -150 0 630 180
+"
+}
+

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/ip/cmpy_18x8/cmpy_18x8.xci

@@ -0,0 +1,213 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "cmpy_18x8",
+    "component_reference": "xilinx.com:ip:cmpy:6.0",
+    "ip_revision": "24",
+    "gen_directory": "../../../../rfsoc_eval_demo.gen/sources_1/ip/cmpy_18x8",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "cmpy_18x8", "resolve_type": "user", "usage": "all" } ],
+        "APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HasATUSER": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ATUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BPortWidth": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HasBTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HasBTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "BTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MultType": [ { "value": "Use_LUTs", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "OptimizeGoal": [ { "value": "Resources", "resolve_type": "user", "usage": "all" } ],
+        "FlowControl": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
+        "RoundMode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
+        "OutputWidth": [ { "value": "27", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HasCTRLTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HasCTRLTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CTRLTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "OutTLASTBehv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
+        "LatencyConfig": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "MinimumLatency": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICE": [ { "value": "xczu48dr", "resolve_type": "generated", "usage": "all" } ],
+        "C_A_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_B_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUT_WIDTH": [ { "value": "27", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MULT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "HAS_NEGATE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SINGLE_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "ROUND": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "USE_DSP_CASCADES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_A_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_A_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_B_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_B_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_CTRL_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_CTRL_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_A_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_A_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_B_TDATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_B_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_CTRL_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_CTRL_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "24" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../rfsoc_eval_demo.gen/sources_1/ip/cmpy_18x8" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_a_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_a_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
+        "s_axis_b_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_b_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_dout_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "M_AXIS_DOUT": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "S_AXIS_A": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_a_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_a_tvalid" } ]
+          }
+        },
+        "S_AXIS_B": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_b_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_b_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/ip/coe/hrc_25_12_03.coe

@@ -0,0 +1,308 @@
+; XILINX CORE Generator v1.0 
+; Copyright 2023 Gatsby Van <[email protected]>
+;	generated by MATLAB 24.2 (R2024b)
+;	generated at: 5-Nov-2024 11:50:36 +0800
+
+RADIX = 10;
+COEFDATA = 
+ -203,
+ -179,
+ -150,
+ -116,
+  -78,
+  -38,
+    5,
+   49,
+   93,
+  136,
+  176,
+  213,
+  246,
+  273,
+  295,
+  309,
+  316,
+  315,
+  307,
+  290,
+  266,
+  235,
+  197,
+  154,
+  106,
+   55,
+    1,
+  -53,
+ -107,
+ -158,
+ -206,
+ -249,
+ -286,
+ -315,
+ -335,
+ -347,
+ -349,
+ -340,
+ -321,
+ -293,
+ -255,
+ -208,
+ -153,
+  -93,
+  -27,
+   41,
+  111,
+  180,
+  245,
+  306,
+  360,
+  405,
+  438,
+  460,
+  468,
+  461,
+  439,
+  402,
+  349,
+  281,
+  199,
+  105,
+    0,
+ -113,
+ -231,
+ -353,
+ -474,
+ -592,
+ -702,
+ -802,
+ -888,
+ -957,
+-1005,
+-1030,
+-1031,
+-1003,
+ -948,
+ -863,
+ -749,
+ -607,
+ -437,
+ -243,
+  -27,
+  208,
+  457,
+  714,
+  976,
+ 1236,
+ 1487,
+ 1724,
+ 1939,
+ 2127,
+ 2280,
+ 2394,
+ 2463,
+ 2481,
+ 2445,
+ 2352,
+ 2200,
+ 1987,
+ 1714,
+ 1382,
+  994,
+  555,
+   69,
+ -456,
+-1012,
+-1590,
+-2179,
+-2768,
+-3346,
+-3898,
+-4413,
+-4877,
+-5276,
+-5597,
+-5828,
+-5957,
+-5972,
+-5864,
+-5624,
+-5246,
+-4724,
+-4055,
+-3237,
+-2272,
+-1162,
+   87,
+ 1469,
+ 2973,
+ 4588,
+ 6302,
+ 8097,
+ 9959,
+11868,
+13805,
+15749,
+17681,
+19578,
+21419,
+23184,
+24852,
+26402,
+27818,
+29082,
+30179,
+31095,
+31819,
+32343,
+32660,
+32767,
+32660,
+32343,
+31819,
+31095,
+30179,
+29082,
+27818,
+26402,
+24852,
+23184,
+21419,
+19578,
+17681,
+15749,
+13805,
+11868,
+ 9959,
+ 8097,
+ 6302,
+ 4588,
+ 2973,
+ 1469,
+   87,
+-1162,
+-2272,
+-3237,
+-4055,
+-4724,
+-5246,
+-5624,
+-5864,
+-5972,
+-5957,
+-5828,
+-5597,
+-5276,
+-4877,
+-4413,
+-3898,
+-3346,
+-2768,
+-2179,
+-1590,
+-1012,
+ -456,
+   69,
+  555,
+  994,
+ 1382,
+ 1714,
+ 1987,
+ 2200,
+ 2352,
+ 2445,
+ 2481,
+ 2463,
+ 2394,
+ 2280,
+ 2127,
+ 1939,
+ 1724,
+ 1487,
+ 1236,
+  976,
+  714,
+  457,
+  208,
+  -27,
+ -243,
+ -437,
+ -607,
+ -749,
+ -863,
+ -948,
+-1003,
+-1031,
+-1030,
+-1005,
+ -957,
+ -888,
+ -802,
+ -702,
+ -592,
+ -474,
+ -353,
+ -231,
+ -113,
+    0,
+  105,
+  199,
+  281,
+  349,
+  402,
+  439,
+  461,
+  468,
+  460,
+  438,
+  405,
+  360,
+  306,
+  245,
+  180,
+  111,
+   41,
+  -27,
+  -93,
+ -153,
+ -208,
+ -255,
+ -293,
+ -321,
+ -340,
+ -349,
+ -347,
+ -335,
+ -315,
+ -286,
+ -249,
+ -206,
+ -158,
+ -107,
+  -53,
+    1,
+   55,
+  106,
+  154,
+  197,
+  235,
+  266,
+  290,
+  307,
+  315,
+  316,
+  309,
+  295,
+  273,
+  246,
+  213,
+  176,
+  136,
+   93,
+   49,
+    5,
+  -38,
+  -78,
+ -116,
+ -150,
+ -179,
+ -203;

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/ip/coe/hrc_50_12_03.coe

@@ -0,0 +1,608 @@
+; XILINX CORE Generator v1.0 
+; Copyright 2023 Gatsby Van <[email protected]>
+;	generated by MATLAB 24.2 (R2024b)
+;	generated at: 5-Nov-2024 11:50:31 +0800
+
+RADIX = 10;
+COEFDATA = 
+ -203,
+ -192,
+ -179,
+ -165,
+ -150,
+ -134,
+ -116,
+  -98,
+  -78,
+  -58,
+  -38,
+  -16,
+    5,
+   27,
+   49,
+   71,
+   93,
+  115,
+  136,
+  156,
+  176,
+  195,
+  213,
+  230,
+  246,
+  260,
+  273,
+  285,
+  295,
+  303,
+  309,
+  313,
+  316,
+  317,
+  315,
+  312,
+  307,
+  299,
+  290,
+  279,
+  266,
+  251,
+  235,
+  217,
+  197,
+  176,
+  154,
+  130,
+  106,
+   81,
+   55,
+   28,
+    1,
+  -26,
+  -53,
+  -80,
+ -107,
+ -133,
+ -158,
+ -183,
+ -206,
+ -228,
+ -249,
+ -268,
+ -286,
+ -301,
+ -315,
+ -326,
+ -335,
+ -342,
+ -347,
+ -349,
+ -349,
+ -346,
+ -340,
+ -332,
+ -321,
+ -308,
+ -293,
+ -275,
+ -255,
+ -232,
+ -208,
+ -181,
+ -153,
+ -124,
+  -93,
+  -60,
+  -27,
+    7,
+   41,
+   76,
+  111,
+  145,
+  180,
+  213,
+  245,
+  277,
+  306,
+  334,
+  360,
+  383,
+  405,
+  423,
+  438,
+  451,
+  460,
+  466,
+  468,
+  467,
+  461,
+  452,
+  439,
+  422,
+  402,
+  377,
+  349,
+  317,
+  281,
+  242,
+  199,
+  154,
+  105,
+   54,
+    0,
+  -55,
+ -113,
+ -171,
+ -231,
+ -292,
+ -353,
+ -414,
+ -474,
+ -534,
+ -592,
+ -648,
+ -702,
+ -754,
+ -802,
+ -847,
+ -888,
+ -925,
+ -957,
+ -984,
+-1005,
+-1021,
+-1030,
+-1034,
+-1031,
+-1020,
+-1003,
+ -979,
+ -948,
+ -909,
+ -863,
+ -810,
+ -749,
+ -681,
+ -607,
+ -525,
+ -437,
+ -343,
+ -243,
+ -137,
+  -27,
+   89,
+  208,
+  331,
+  457,
+  585,
+  714,
+  845,
+  976,
+ 1107,
+ 1236,
+ 1363,
+ 1487,
+ 1608,
+ 1724,
+ 1834,
+ 1939,
+ 2037,
+ 2127,
+ 2208,
+ 2280,
+ 2343,
+ 2394,
+ 2434,
+ 2463,
+ 2478,
+ 2481,
+ 2470,
+ 2445,
+ 2406,
+ 2352,
+ 2283,
+ 2200,
+ 2101,
+ 1987,
+ 1858,
+ 1714,
+ 1555,
+ 1382,
+ 1195,
+  994,
+  780,
+  555,
+  317,
+   69,
+ -189,
+ -456,
+ -730,
+-1012,
+-1299,
+-1590,
+-1883,
+-2179,
+-2474,
+-2768,
+-3059,
+-3346,
+-3626,
+-3898,
+-4161,
+-4413,
+-4652,
+-4877,
+-5085,
+-5276,
+-5447,
+-5597,
+-5725,
+-5828,
+-5906,
+-5957,
+-5979,
+-5972,
+-5934,
+-5864,
+-5761,
+-5624,
+-5453,
+-5246,
+-5003,
+-4724,
+-4408,
+-4055,
+-3664,
+-3237,
+-2773,
+-2272,
+-1735,
+-1162,
+ -554,
+   87,
+  762,
+ 1469,
+ 2206,
+ 2973,
+ 3768,
+ 4588,
+ 5434,
+ 6302,
+ 7190,
+ 8097,
+ 9021,
+ 9959,
+10908,
+11868,
+12834,
+13805,
+14777,
+15749,
+16718,
+17681,
+18635,
+19578,
+20507,
+21419,
+22312,
+23184,
+24031,
+24852,
+25643,
+26402,
+27128,
+27818,
+28470,
+29082,
+29652,
+30179,
+30660,
+31095,
+31482,
+31819,
+32107,
+32343,
+32528,
+32660,
+32740,
+32767,
+32740,
+32660,
+32528,
+32343,
+32107,
+31819,
+31482,
+31095,
+30660,
+30179,
+29652,
+29082,
+28470,
+27818,
+27128,
+26402,
+25643,
+24852,
+24031,
+23184,
+22312,
+21419,
+20507,
+19578,
+18635,
+17681,
+16718,
+15749,
+14777,
+13805,
+12834,
+11868,
+10908,
+ 9959,
+ 9021,
+ 8097,
+ 7190,
+ 6302,
+ 5434,
+ 4588,
+ 3768,
+ 2973,
+ 2206,
+ 1469,
+  762,
+   87,
+ -554,
+-1162,
+-1735,
+-2272,
+-2773,
+-3237,
+-3664,
+-4055,
+-4408,
+-4724,
+-5003,
+-5246,
+-5453,
+-5624,
+-5761,
+-5864,
+-5934,
+-5972,
+-5979,
+-5957,
+-5906,
+-5828,
+-5725,
+-5597,
+-5447,
+-5276,
+-5085,
+-4877,
+-4652,
+-4413,
+-4161,
+-3898,
+-3626,
+-3346,
+-3059,
+-2768,
+-2474,
+-2179,
+-1883,
+-1590,
+-1299,
+-1012,
+ -730,
+ -456,
+ -189,
+   69,
+  317,
+  555,
+  780,
+  994,
+ 1195,
+ 1382,
+ 1555,
+ 1714,
+ 1858,
+ 1987,
+ 2101,
+ 2200,
+ 2283,
+ 2352,
+ 2406,
+ 2445,
+ 2470,
+ 2481,
+ 2478,
+ 2463,
+ 2434,
+ 2394,
+ 2343,
+ 2280,
+ 2208,
+ 2127,
+ 2037,
+ 1939,
+ 1834,
+ 1724,
+ 1608,
+ 1487,
+ 1363,
+ 1236,
+ 1107,
+  976,
+  845,
+  714,
+  585,
+  457,
+  331,
+  208,
+   89,
+  -27,
+ -137,
+ -243,
+ -343,
+ -437,
+ -525,
+ -607,
+ -681,
+ -749,
+ -810,
+ -863,
+ -909,
+ -948,
+ -979,
+-1003,
+-1020,
+-1031,
+-1034,
+-1030,
+-1021,
+-1005,
+ -984,
+ -957,
+ -925,
+ -888,
+ -847,
+ -802,
+ -754,
+ -702,
+ -648,
+ -592,
+ -534,
+ -474,
+ -414,
+ -353,
+ -292,
+ -231,
+ -171,
+ -113,
+  -55,
+    0,
+   54,
+  105,
+  154,
+  199,
+  242,
+  281,
+  317,
+  349,
+  377,
+  402,
+  422,
+  439,
+  452,
+  461,
+  467,
+  468,
+  466,
+  460,
+  451,
+  438,
+  423,
+  405,
+  383,
+  360,
+  334,
+  306,
+  277,
+  245,
+  213,
+  180,
+  145,
+  111,
+   76,
+   41,
+    7,
+  -27,
+  -60,
+  -93,
+ -124,
+ -153,
+ -181,
+ -208,
+ -232,
+ -255,
+ -275,
+ -293,
+ -308,
+ -321,
+ -332,
+ -340,
+ -346,
+ -349,
+ -349,
+ -347,
+ -342,
+ -335,
+ -326,
+ -315,
+ -301,
+ -286,
+ -268,
+ -249,
+ -228,
+ -206,
+ -183,
+ -158,
+ -133,
+ -107,
+  -80,
+  -53,
+  -26,
+    1,
+   28,
+   55,
+   81,
+  106,
+  130,
+  154,
+  176,
+  197,
+  217,
+  235,
+  251,
+  266,
+  279,
+  290,
+  299,
+  307,
+  312,
+  315,
+  317,
+  316,
+  313,
+  309,
+  303,
+  295,
+  285,
+  273,
+  260,
+  246,
+  230,
+  213,
+  195,
+  176,
+  156,
+  136,
+  115,
+   93,
+   71,
+   49,
+   27,
+    5,
+  -16,
+  -38,
+  -58,
+  -78,
+  -98,
+ -116,
+ -134,
+ -150,
+ -165,
+ -179,
+ -192,
+ -203;

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/ip/coe/sweep_freq.coe

@@ -0,0 +1,258 @@
+MEMORY_INITIALIZATION_RADIX = 10;
+MEMORY_INITIALIZATION_VECTOR = 
+-2147483647,
+-2130640638,
+-2113797629,
+-2096954620,
+-2080111611,
+-2063268602,
+-2046425593,
+-2029582584,
+-2012739575,
+-1995896566,
+-1979053557,
+-1962210548,
+-1945367539,
+-1928524530,
+-1911681521,
+-1894838512,
+-1877995503,
+-1861152494,
+-1844309485,
+-1827466476,
+-1810623467,
+-1793780458,
+-1776937449,
+-1760094440,
+-1743251431,
+-1726408422,
+-1709565413,
+-1692722404,
+-1675879395,
+-1659036386,
+-1642193377,
+-1625350368,
+-1608507359,
+-1591664350,
+-1574821341,
+-1557978332,
+-1541135323,
+-1524292314,
+-1507449305,
+-1490606296,
+-1473763287,
+-1456920278,
+-1440077269,
+-1423234260,
+-1406391251,
+-1389548242,
+-1372705233,
+-1355862224,
+-1339019215,
+-1322176206,
+-1305333197,
+-1288490188,
+-1271647179,
+-1254804170,
+-1237961161,
+-1221118152,
+-1204275143,
+-1187432134,
+-1170589125,
+-1153746116,
+-1136903107,
+-1120060098,
+-1103217089,
+-1086374080,
+-1069531071,
+-1052688062,
+-1035845053,
+-1019002044,
+-1002159035,
+-985316026,
+-968473017,
+-951630008,
+-934786999,
+-917943990,
+-901100981,
+-884257972,
+-867414963,
+-850571954,
+-833728945,
+-816885936,
+-800042927,
+-783199918,
+-766356909,
+-749513900,
+-732670891,
+-715827882,
+-698984873,
+-682141864,
+-665298855,
+-648455846,
+-631612837,
+-614769828,
+-597926819,
+-581083810,
+-564240801,
+-547397792,
+-530554783,
+-513711774,
+-496868765,
+-480025756,
+-463182747,
+-446339738,
+-429496729,
+-412653720,
+-395810711,
+-378967702,
+-362124693,
+-345281684,
+-328438675,
+-311595666,
+-294752657,
+-277909648,
+-261066639,
+-244223630,
+-227380621,
+-210537612,
+-193694603,
+-176851594,
+-160008585,
+-143165576,
+-126322567,
+-109479558,
+-92636549,
+-75793540,
+-58950531,
+-42107522,
+-25264513,
+-8421504,
+8421504,
+25264513,
+42107522,
+58950531,
+75793540,
+92636549,
+109479558,
+126322567,
+143165576,
+160008585,
+176851594,
+193694603,
+210537612,
+227380621,
+244223630,
+261066639,
+277909648,
+294752657,
+311595666,
+328438675,
+345281684,
+362124693,
+378967702,
+395810711,
+412653720,
+429496729,
+446339738,
+463182747,
+480025756,
+496868765,
+513711774,
+530554783,
+547397792,
+564240801,
+581083810,
+597926819,
+614769828,
+631612837,
+648455846,
+665298855,
+682141864,
+698984873,
+715827882,
+732670891,
+749513900,
+766356909,
+783199918,
+800042927,
+816885936,
+833728945,
+850571954,
+867414963,
+884257972,
+901100981,
+917943990,
+934786999,
+951630008,
+968473017,
+985316026,
+1002159035,
+1019002044,
+1035845053,
+1052688062,
+1069531071,
+1086374080,
+1103217089,
+1120060098,
+1136903107,
+1153746116,
+1170589125,
+1187432134,
+1204275143,
+1221118152,
+1237961161,
+1254804170,
+1271647179,
+1288490188,
+1305333197,
+1322176206,
+1339019215,
+1355862224,
+1372705233,
+1389548242,
+1406391251,
+1423234260,
+1440077269,
+1456920278,
+1473763287,
+1490606296,
+1507449305,
+1524292314,
+1541135323,
+1557978332,
+1574821341,
+1591664350,
+1608507359,
+1625350368,
+1642193377,
+1659036386,
+1675879395,
+1692722404,
+1709565413,
+1726408422,
+1743251431,
+1760094440,
+1776937449,
+1793780458,
+1810623467,
+1827466476,
+1844309485,
+1861152494,
+1877995503,
+1894838512,
+1911681521,
+1928524530,
+1945367539,
+1962210548,
+1979053557,
+1995896566,
+2012739575,
+2029582584,
+2046425593,
+2063268602,
+2080111611,
+2096954620,
+2113797629,
+2130640638,
+2147483647;

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/ip/dds_32b_8b/dds_32b_8b.xci

@@ -0,0 +1,358 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "dds_32b_8b",
+    "component_reference": "xilinx.com:ip:dds_compiler:6.0",
+    "ip_revision": "25",
+    "gen_directory": "../../../../rfsoc_eval_demo.gen/sources_1/ip/dds_32b_8b",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "dds_32b_8b", "resolve_type": "user", "usage": "all" } ],
+        "PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "resolve_type": "user", "usage": "all" } ],
+        "DDS_Clock_Rate": [ { "value": "245.76", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
+        "Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Output_Type": [ { "value": "Integer", "resolve_type": "user", "usage": "all" } ],
+        "Parameter_Entry": [ { "value": "Hardware_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Spurious_Free_Dynamic_Range": [ { "value": "45", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Frequency_Resolution": [ { "value": "0.4", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Noise_Shaping": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Output_Width": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Phase_Increment": [ { "value": "Programmable", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Resync": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Phase_offset": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Selection": [ { "value": "Sine_and_Cosine", "resolve_type": "user", "usage": "all" } ],
+        "Negative_Sine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Negative_Cosine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Amplitude_Mode": [ { "value": "Full_Range", "resolve_type": "user", "usage": "all" } ],
+        "Memory_Type": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
+        "Optimization_Goal": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
+        "DSP48_Use": [ { "value": "Minimal", "resolve_type": "user", "usage": "all" } ],
+        "Has_Phase_Out": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "DATA_Has_TLAST": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "S_PHASE_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "S_PHASE_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M_DATA_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "M_PHASE_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
+        "S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
+        "OUTPUT_FORM": [ { "value": "Twos_Complement", "resolve_type": "user", "usage": "all" } ],
+        "Latency_Configuration": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
+        "Latency": [ { "value": "3", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Has_ARESETn": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Has_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Output_Frequency1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC1": [ { "value": "1101101001110100", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles1": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF1": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency11": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC11": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles11": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF11": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency12": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC12": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles12": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF12": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency13": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC13": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles13": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF13": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency14": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC14": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles14": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF14": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency15": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC15": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles15": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF15": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Output_Frequency16": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PINC16": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Offset_Angles16": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "POFF16": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "POR_mode": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ],
+        "explicit_period": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "period": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_MODE_OF_OPERATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MODULUS": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ACCUMULATOR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PHASE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PHASEGEN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SINCOS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NEGATIVE_COSINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NEGATIVE_SINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NOISE_SHAPING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUTPUTS_REQUIRED": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUTPUT_FORM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUTPUT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUTPUT_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PHASE_ANGLE_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PHASE_INCREMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PHASE_INCREMENT_VALUE": [ { "value": "1101101001110100,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0", "resolve_type": "generated", "usage": "all" } ],
+        "C_RESYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PHASE_OFFSET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PHASE_OFFSET_VALUE": [ { "value": "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0", "resolve_type": "generated", "usage": "all" } ],
+        "C_OPTIMISE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DSP48": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POR_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AMPLITUDE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_TREADY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_PHASE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_PHASE_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_PHASE_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_PHASE_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_CONFIG": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_CONFIG_SYNC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_CONFIG_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_M_DATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_TDATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_M_PHASE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_PHASE_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_PHASE_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_PHASE_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEBUG_INTERFACE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CHAN_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "25" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../rfsoc_eval_demo.gen/sources_1/ip/dds_32b_8b" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_config_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_config_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_data_tdata": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "event_pinc_invalid_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_poff_invalid_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_phase_in_invalid_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_phase_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_phase_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_phase_chanid_incorrect_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "M_AXIS_DATA": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
+          }
+        },
+        "S_AXIS_CONFIG": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_config_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_config_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/ip/hop_rom/hop_rom.xci

@@ -0,0 +1,254 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "hop_rom",
+    "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+    "ip_revision": "8",
+    "gen_directory": "../../../../rfsoc_eval_demo.gen/sources_1/ip/hop_rom",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "hop_rom", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
+        "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "Single_Port_ROM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
+        "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
+        "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Write_Depth_A": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Write_Width_B": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Read_Width_B": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coe_File": [ { "value": "../coe/sweep_freq.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Write_Rate": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
+        "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
+        "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
+        "EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
+        "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LOAD_INIT_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INIT_FILE_NAME": [ { "value": "hop_rom.mif", "resolve_type": "generated", "usage": "all" } ],
+        "C_INIT_FILE": [ { "value": "hop_rom.mem", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
+        "C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_36K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     3.163063 mW", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "8" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../rfsoc_eval_demo.gen/sources_1/ip/hop_rom" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clka": [ { "direction": "in", "driver_value": "0" } ],
+        "addra": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "CLK.ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "RST.ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "BRAM_PORTA": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_ADDRESS_MODE": [ { "value": "BYTE_ADDRESS", "resolve_type": "user", "usage": "all" } ],
+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addra" } ],
+            "CLK": [ { "physical_name": "clka" } ],
+            "DOUT": [ { "physical_name": "douta" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_1": {
+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/ip/hrc_25_12_03/hrc_25_12_03.xci

@@ -0,0 +1,350 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "hrc_25_12_03",
+    "component_reference": "xilinx.com:ip:fir_compiler:7.2",
+    "ip_revision": "22",
+    "gen_directory": "../../../../rfsoc_eval_demo.gen/sources_1/ip/hrc_25_12_03",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "hrc_25_12_03", "resolve_type": "user", "usage": "all" } ],
+        "GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ],
+        "CoefficientSource": [ { "value": "COE_File", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "CoefficientVector": [ { "value": "6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_File": [ { "value": "../coe/hrc_25_12_03.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_Sets": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Coefficient_Reload": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Filter_Type": [ { "value": "Interpolation", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Rate_Change_Type": [ { "value": "Fixed_Fractional", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Interpolation_Rate": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Decimation_Rate": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Zero_Pack_Factor": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Channel_Sequence": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ],
+        "Number_Channels": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Select_Pattern": [ { "value": "All", "resolve_type": "user", "usage": "all" } ],
+        "Pattern_List": [ { "value": "P4-0,P4-1,P4-2,P4-3,P4-4", "resolve_type": "user", "usage": "all" } ],
+        "Number_Paths": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RateSpecification": [ { "value": "Frequency_Specification", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "HardwareOversamplingRate": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SamplePeriod": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Sample_Frequency": [ { "value": "48", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Clock_Frequency": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Coefficient_Sign": [ { "value": "Signed", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Quantization": [ { "value": "Integer_Coefficients", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BestPrecision": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coefficient_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Coefficient_Structure": [ { "value": "Non_Symmetric", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Data_Sign": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
+        "Data_Width": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Data_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Output_Rounding_Mode": [ { "value": "Full_Precision", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Width": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Filter_Architecture": [ { "value": "Systolic_Multiply_Accumulate", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Optimization_Goal": [ { "value": "Area", "resolve_type": "user", "usage": "all" } ],
+        "Optimization_Selection": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "Data_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Pre_Adder_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coefficient_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Control_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Control_Column_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Control_Broadcast_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Control_LUT_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "No_BRAM_Read_First_Mode": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Optimal_Column_Lengths": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Data_Path_Broadcast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Disable_Half_Band_Centre_Tap": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "No_SRL_Attributes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Other": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Optimization_List": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "Data_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Input_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Output_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Preference_For_Other_Storage": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Multi_Column_Support": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Inter_Column_Pipe_Length": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ColumnConfig": [ { "value": "13", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "DATA_Has_TLAST": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
+        "M_DATA_Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "S_DATA_Has_FIFO": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "S_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
+        "M_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
+        "DATA_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
+        "S_CONFIG_Method": [ { "value": "Single", "resolve_type": "user", "usage": "all" } ],
+        "Num_Reload_Slots": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Has_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Has_ARESETn": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Data_Vector": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Blank_Output": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Gen_MIF_from_Spec": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Gen_MIF_from_COE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reload_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "usage": "all" } ],
+        "Gen_MIF_Files": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "DisplayReloadOrder": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Passband_Min": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Passband_Max": [ { "value": "0.5", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Stopband_Min": [ { "value": "0.5", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Stopband_Max": [ { "value": "1.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Filter_Selection": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
+        "C_COMPONENT_NAME": [ { "value": "hrc_25_12_03", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_FILE": [ { "value": "hrc_25_12_03.mif", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_FILE_LINES": [ { "value": "325", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FILTER_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERP_RATE": [ { "value": "25", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DECIM_RATE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ZERO_PACKING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SYMMETRY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_FILTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_TAPS": [ { "value": "301", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CHANNEL_PATTERN": [ { "value": "fixed", "resolve_type": "generated", "usage": "all" } ],
+        "C_ROUND_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_RELOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_RELOAD_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COL_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COL_PIPE_LEN": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COL_CONFIG": [ { "value": "13", "resolve_type": "generated", "usage": "all" } ],
+        "C_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_IP_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PX_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_PATH_WIDTHS": [ { "value": "16", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_PX_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PATH_SIGN": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_PATH_SIGN": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_ACCUM_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTPUT_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUTPUT_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
+        "C_ACCUM_OP_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
+        "C_EXT_MULT_CNFG": [ { "value": "none", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PATH_PSAMP_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_OP_PATH_PSAMP_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_NUM_MADDS": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPT_MADDS": [ { "value": "none", "resolve_type": "generated", "usage": "all" } ],
+        "C_OVERSAMPLING_RATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INPUT_RATE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUTPUT_RATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_MEMTYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IPBUFF_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPBUFF_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATAPATH_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_ARRANGEMENT": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_MEM_PACKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_MEM_PACKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FILTS_PACKED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "19", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ARESETn": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_HAS_FIFO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_HAS_TREADY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_CONFIG_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_SYNC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_PACKET_SIZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RELOAD_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "22" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../rfsoc_eval_demo.gen/sources_1/ip/hrc_25_12_03" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "s_axis_data_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_data_tready": [ { "direction": "out", "driver_value": "0x1" } ],
+        "s_axis_data_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_data_tdata": [ { "direction": "out", "size_left": "23", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "event_s_data_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_data_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_data_chanid_incorrect_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_reload_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_reload_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "S_AXIS_DATA": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_data_tdata" } ],
+            "TREADY": [ { "physical_name": "s_axis_data_tready" } ],
+            "TVALID": [ { "physical_name": "s_axis_data_tvalid" } ]
+          }
+        },
+        "M_AXIS_DATA": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/ip/hrc_400_12_03/hrc_400_12_03.xci

@@ -0,0 +1,350 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "hrc_400_12_03",
+    "component_reference": "xilinx.com:ip:fir_compiler:7.2",
+    "ip_revision": "22",
+    "gen_directory": "../../../../rfsoc_eval_demo.gen/sources_1/ip/hrc_400_12_03",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "hrc_400_12_03", "resolve_type": "user", "usage": "all" } ],
+        "GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ],
+        "CoefficientSource": [ { "value": "COE_File", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "CoefficientVector": [ { "value": "6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_File": [ { "value": "../coe/hrc_400_12_03.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_Sets": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Coefficient_Reload": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Filter_Type": [ { "value": "Interpolation", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Rate_Change_Type": [ { "value": "Fixed_Fractional", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Interpolation_Rate": [ { "value": "400", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Decimation_Rate": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Zero_Pack_Factor": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Channel_Sequence": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ],
+        "Number_Channels": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Select_Pattern": [ { "value": "All", "resolve_type": "user", "usage": "all" } ],
+        "Pattern_List": [ { "value": "P4-0,P4-1,P4-2,P4-3,P4-4", "resolve_type": "user", "usage": "all" } ],
+        "Number_Paths": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RateSpecification": [ { "value": "Frequency_Specification", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "HardwareOversamplingRate": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SamplePeriod": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Sample_Frequency": [ { "value": "1.5", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Clock_Frequency": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Coefficient_Sign": [ { "value": "Signed", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Quantization": [ { "value": "Integer_Coefficients", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BestPrecision": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coefficient_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Coefficient_Structure": [ { "value": "Non_Symmetric", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Data_Sign": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
+        "Data_Width": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Data_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Output_Rounding_Mode": [ { "value": "Full_Precision", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Width": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Filter_Architecture": [ { "value": "Systolic_Multiply_Accumulate", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Optimization_Goal": [ { "value": "Area", "resolve_type": "user", "usage": "all" } ],
+        "Optimization_Selection": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "Data_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Pre_Adder_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coefficient_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Control_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Control_Column_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Control_Broadcast_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Control_LUT_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "No_BRAM_Read_First_Mode": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Optimal_Column_Lengths": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Data_Path_Broadcast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Disable_Half_Band_Centre_Tap": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "No_SRL_Attributes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Other": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Optimization_List": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "Data_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Input_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Output_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Preference_For_Other_Storage": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Multi_Column_Support": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Inter_Column_Pipe_Length": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ColumnConfig": [ { "value": "13", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "DATA_Has_TLAST": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
+        "M_DATA_Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "S_DATA_Has_FIFO": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "S_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
+        "M_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
+        "DATA_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
+        "S_CONFIG_Method": [ { "value": "Single", "resolve_type": "user", "usage": "all" } ],
+        "Num_Reload_Slots": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Has_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Has_ARESETn": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Data_Vector": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Blank_Output": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Gen_MIF_from_Spec": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Gen_MIF_from_COE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reload_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "usage": "all" } ],
+        "Gen_MIF_Files": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "DisplayReloadOrder": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Passband_Min": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Passband_Max": [ { "value": "0.5", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Stopband_Min": [ { "value": "0.5", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Stopband_Max": [ { "value": "1.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Filter_Selection": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
+        "C_COMPONENT_NAME": [ { "value": "hrc_400_12_03", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_FILE": [ { "value": "hrc_400_12_03.mif", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_FILE_LINES": [ { "value": "5200", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FILTER_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERP_RATE": [ { "value": "400", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DECIM_RATE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ZERO_PACKING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SYMMETRY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_FILTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_TAPS": [ { "value": "4801", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CHANNEL_PATTERN": [ { "value": "fixed", "resolve_type": "generated", "usage": "all" } ],
+        "C_ROUND_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_RELOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_RELOAD_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COL_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COL_PIPE_LEN": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COL_CONFIG": [ { "value": "13", "resolve_type": "generated", "usage": "all" } ],
+        "C_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_IP_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PX_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_PATH_WIDTHS": [ { "value": "16", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_PX_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PATH_SIGN": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_PATH_SIGN": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_ACCUM_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTPUT_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUTPUT_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
+        "C_ACCUM_OP_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
+        "C_EXT_MULT_CNFG": [ { "value": "none", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PATH_PSAMP_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_OP_PATH_PSAMP_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_NUM_MADDS": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPT_MADDS": [ { "value": "none", "resolve_type": "generated", "usage": "all" } ],
+        "C_OVERSAMPLING_RATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INPUT_RATE": [ { "value": "133", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUTPUT_RATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_MEMTYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IPBUFF_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPBUFF_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATAPATH_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_ARRANGEMENT": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_MEM_PACKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_MEM_PACKING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FILTS_PACKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ARESETn": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_HAS_FIFO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_HAS_TREADY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_CONFIG_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_SYNC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_PACKET_SIZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RELOAD_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "22" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../rfsoc_eval_demo.gen/sources_1/ip/hrc_400_12_03" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "s_axis_data_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_data_tready": [ { "direction": "out", "driver_value": "0x1" } ],
+        "s_axis_data_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_data_tdata": [ { "direction": "out", "size_left": "23", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "event_s_data_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_data_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_data_chanid_incorrect_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_reload_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_reload_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "S_AXIS_DATA": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_data_tdata" } ],
+            "TREADY": [ { "physical_name": "s_axis_data_tready" } ],
+            "TVALID": [ { "physical_name": "s_axis_data_tvalid" } ]
+          }
+        },
+        "M_AXIS_DATA": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/ip/hrc_50_12_03/hrc_50_12_03.xci

@@ -0,0 +1,350 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "hrc_50_12_03",
+    "component_reference": "xilinx.com:ip:fir_compiler:7.2",
+    "ip_revision": "22",
+    "gen_directory": "../../../../rfsoc_eval_demo.gen/sources_1/ip/hrc_50_12_03",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "hrc_50_12_03", "resolve_type": "user", "usage": "all" } ],
+        "GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ],
+        "CoefficientSource": [ { "value": "COE_File", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "CoefficientVector": [ { "value": "6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_File": [ { "value": "../coe/hrc_50_12_03.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_Sets": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Coefficient_Reload": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Filter_Type": [ { "value": "Interpolation", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Rate_Change_Type": [ { "value": "Fixed_Fractional", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Interpolation_Rate": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Decimation_Rate": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Zero_Pack_Factor": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Channel_Sequence": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ],
+        "Number_Channels": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Select_Pattern": [ { "value": "All", "resolve_type": "user", "usage": "all" } ],
+        "Pattern_List": [ { "value": "P4-0,P4-1,P4-2,P4-3,P4-4", "resolve_type": "user", "usage": "all" } ],
+        "Number_Paths": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RateSpecification": [ { "value": "Frequency_Specification", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "HardwareOversamplingRate": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SamplePeriod": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Sample_Frequency": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Clock_Frequency": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Coefficient_Sign": [ { "value": "Signed", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Quantization": [ { "value": "Integer_Coefficients", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BestPrecision": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coefficient_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Coefficient_Structure": [ { "value": "Non_Symmetric", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Data_Sign": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
+        "Data_Width": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Data_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Output_Rounding_Mode": [ { "value": "Full_Precision", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Width": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Filter_Architecture": [ { "value": "Systolic_Multiply_Accumulate", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Optimization_Goal": [ { "value": "Area", "resolve_type": "user", "usage": "all" } ],
+        "Optimization_Selection": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "Data_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Pre_Adder_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coefficient_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Control_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Control_Column_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Control_Broadcast_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Control_LUT_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "No_BRAM_Read_First_Mode": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Optimal_Column_Lengths": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Data_Path_Broadcast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Disable_Half_Band_Centre_Tap": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "No_SRL_Attributes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Other": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Optimization_List": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "Data_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Input_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Output_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Preference_For_Other_Storage": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Multi_Column_Support": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "Inter_Column_Pipe_Length": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ColumnConfig": [ { "value": "13", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "DATA_Has_TLAST": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
+        "M_DATA_Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "S_DATA_Has_FIFO": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "S_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
+        "M_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
+        "DATA_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
+        "S_CONFIG_Method": [ { "value": "Single", "resolve_type": "user", "usage": "all" } ],
+        "Num_Reload_Slots": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Has_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Has_ARESETn": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Data_Vector": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Blank_Output": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Gen_MIF_from_Spec": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Gen_MIF_from_COE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reload_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "usage": "all" } ],
+        "Gen_MIF_Files": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "DisplayReloadOrder": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Passband_Min": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Passband_Max": [ { "value": "0.5", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Stopband_Min": [ { "value": "0.5", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Stopband_Max": [ { "value": "1.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Filter_Selection": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
+        "C_COMPONENT_NAME": [ { "value": "hrc_50_12_03", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_FILE": [ { "value": "hrc_50_12_03.mif", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_FILE_LINES": [ { "value": "650", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FILTER_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERP_RATE": [ { "value": "50", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DECIM_RATE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ZERO_PACKING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SYMMETRY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_FILTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_TAPS": [ { "value": "601", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CHANNEL_PATTERN": [ { "value": "fixed", "resolve_type": "generated", "usage": "all" } ],
+        "C_ROUND_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_RELOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_RELOAD_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COL_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COL_PIPE_LEN": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COL_CONFIG": [ { "value": "13", "resolve_type": "generated", "usage": "all" } ],
+        "C_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_IP_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PX_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_PATH_WIDTHS": [ { "value": "16", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_PX_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PATH_SIGN": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_PATH_SIGN": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_ACCUM_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTPUT_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUTPUT_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
+        "C_ACCUM_OP_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
+        "C_EXT_MULT_CNFG": [ { "value": "none", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PATH_PSAMP_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_OP_PATH_PSAMP_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_NUM_MADDS": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPT_MADDS": [ { "value": "none", "resolve_type": "generated", "usage": "all" } ],
+        "C_OVERSAMPLING_RATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INPUT_RATE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUTPUT_RATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_MEMTYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IPBUFF_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPBUFF_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATAPATH_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_ARRANGEMENT": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_MEM_PACKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_MEM_PACKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FILTS_PACKED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "19", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ARESETn": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_HAS_FIFO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_HAS_TREADY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_CONFIG_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_SYNC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_PACKET_SIZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RELOAD_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu48dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "22" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../rfsoc_eval_demo.gen/sources_1/ip/hrc_50_12_03" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2024.1.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "s_axis_data_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_data_tready": [ { "direction": "out", "driver_value": "0x1" } ],
+        "s_axis_data_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_data_tdata": [ { "direction": "out", "size_left": "23", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "event_s_data_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_data_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_data_chanid_incorrect_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_reload_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_reload_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "S_AXIS_DATA": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_data_tdata" } ],
+            "TREADY": [ { "physical_name": "s_axis_data_tready" } ],
+            "TVALID": [ { "physical_name": "s_axis_data_tvalid" } ]
+          }
+        },
+        "M_AXIS_DATA": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/new/m_seq_gen.v

@@ -0,0 +1,135 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2024/11/01 22:53:18
+// Design Name:
+// Module Name: m_seq_gen
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module m_seq_gen
+#(
+    POLYNOMIAL = "PRBS7",
+    BIT_WIDTH = 2
+)
+(
+    aclk,
+    aresetn,
+    m_axis_tvalid,
+    m_axis_tready,
+    m_axis_tdata
+);
+
+// integer and genvar
+integer ii;
+
+// local parameters
+localparam POLY_PRBS7 = 7'b110_0000;
+localparam POLY_PRBS9 = 9'b1_0001_0000;
+localparam POLY_PRBS11 = 11'b101_0000_0000;
+localparam POLY_PRBS13 = 13'b1_1000_0000_0011;
+localparam POLY_PRBS15 = 15'b110_0000_0000_0000;
+localparam POLY_PRBS20 = 20'b1000_0000_0000_0000_0100;
+localparam POLY_PRBS23 = 23'b100_0010_0000_0000_0000_0000;
+localparam POLY_PRBS31 = 31'b100_1000_0000_0000_0000_0000_0000_0000;
+localparam POLY_COEFF =
+    (POLYNOMIAL == "PRBS7" ) ? POLY_PRBS7  :
+    (POLYNOMIAL == "PRBS9" ) ? POLY_PRBS9  :
+    (POLYNOMIAL == "PRBS11") ? POLY_PRBS11 :
+    (POLYNOMIAL == "PRBS13") ? POLY_PRBS13 :
+    (POLYNOMIAL == "PRBS15") ? POLY_PRBS15 :
+    (POLYNOMIAL == "PRBS20") ? POLY_PRBS20 :
+    (POLYNOMIAL == "PRBS23") ? POLY_PRBS23 :
+    (POLYNOMIAL == "PRBS31") ? POLY_PRBS31 :
+    POLY_PRBS31; // default value
+
+localparam SHIFT_LEN_PRBS7 =  7 ;
+localparam SHIFT_LEN_PRBS9 =  9 ;
+localparam SHIFT_LEN_PRBS11 = 11;
+localparam SHIFT_LEN_PRBS13 = 13;
+localparam SHIFT_LEN_PRBS15 = 15;
+localparam SHIFT_LEN_PRBS20 = 20;
+localparam SHIFT_LEN_PRBS23 = 23;
+localparam SHIFT_LEN_PRBS31 = 31;
+localparam SHIFT_LEN =
+    (POLYNOMIAL == "PRBS7")  ? SHIFT_LEN_PRBS7  :
+    (POLYNOMIAL == "PRBS9")  ? SHIFT_LEN_PRBS9  :
+    (POLYNOMIAL == "PRBS11") ? SHIFT_LEN_PRBS11 :
+    (POLYNOMIAL == "PRBS13") ? SHIFT_LEN_PRBS13 :
+    (POLYNOMIAL == "PRBS15") ? SHIFT_LEN_PRBS15 :
+    (POLYNOMIAL == "PRBS20") ? SHIFT_LEN_PRBS20 :
+    (POLYNOMIAL == "PRBS23") ? SHIFT_LEN_PRBS23 :
+    (POLYNOMIAL == "PRBS31") ? SHIFT_LEN_PRBS31 :
+    SHIFT_LEN_PRBS31;  // default value
+
+// port declaration
+input aclk;
+input aresetn;
+output reg m_axis_tvalid = 'b0;
+input m_axis_tready;
+output [8*((BIT_WIDTH-1)/8+1)-1:0] m_axis_tdata;
+
+// function
+function feedback;
+    input [SHIFT_LEN-1 : 0] shift_reg;
+    input [SHIFT_LEN-1 : 0] poly_coeffs;
+
+    reg [SHIFT_LEN-1 : 0] feedback_raw;
+
+    begin
+        for(ii = 0; ii < SHIFT_LEN; ii = ii + 1) begin
+            feedback_raw[ii] = (shift_reg[ii] & poly_coeffs[SHIFT_LEN-ii-1]);
+        end
+        feedback = ^feedback_raw;
+    end
+endfunction
+
+// shift register
+reg [SHIFT_LEN-1 : 0] shift_reg = {SHIFT_LEN{1'b1}};
+reg [BIT_WIDTH-1 : 0] m_seq_buf = 'b0;
+reg [$clog2(BIT_WIDTH)-1 : 0] m_seq_cnt = 'b0;
+
+always @(posedge aclk) begin
+    if (!aresetn) begin
+        shift_reg <= {SHIFT_LEN{1'b1}};
+        m_seq_buf <= 'b0;
+        m_seq_cnt <= 'b0;
+        m_axis_tvalid <= 'b0;
+    end
+    else begin
+        if (m_axis_tready) begin
+            // feedback
+            shift_reg[SHIFT_LEN-1] <= feedback(shift_reg,POLY_COEFF);
+            // shift register
+            shift_reg[0 +: SHIFT_LEN-1] <= shift_reg[1 +: SHIFT_LEN-1];
+            // multi-bit combination
+            m_seq_buf <= {m_seq_buf[0 +: BIT_WIDTH-1],shift_reg[0]};
+            m_seq_cnt <= (m_seq_cnt >= BIT_WIDTH-1) ? 'b0 : m_seq_cnt + 1'b1;
+            // valid indicator
+            m_axis_tvalid <= (m_seq_cnt == 'b0) ? 1'b1 : 1'b0;
+        end
+        else begin
+            shift_reg <= shift_reg;
+            m_seq_buf <= m_seq_buf;
+            m_seq_cnt <= m_seq_cnt;
+            m_axis_tvalid <= 1'b0;
+        end
+    end
+end
+
+assign m_axis_tdata =
+    {{(8*((BIT_WIDTH-1)/8+1)-BIT_WIDTH){1'b0}},m_seq_buf};
+
+endmodule

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/new/system_top.v

@@ -0,0 +1,688 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 03/15/2022 08:34:01 PM
+// Design Name:
+// Module Name: system_top
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module system_top
+(
+    // *************************************************************************
+    // *************************** Clocks and SYSREF ***************************
+    // *************************************************************************
+    // adc clock
+    input       adc1_clk_in_p       ,
+    input       adc1_clk_in_n       ,
+    input       adc2_clk_in_p       ,
+    input       adc2_clk_in_n       ,
+    // dac clock
+    input       dac0_clk_in_p       ,
+    input       dac0_clk_in_n       ,
+    input       dac2_clk_in_p       ,
+    input       dac2_clk_in_n       ,
+    // sysref for rf
+    input       rf_sysref_p         ,
+    input       rf_sysref_n         ,
+    // sysref for pl
+    input       pl_sysref_p         ,
+    input       pl_sysref_n         ,
+    // fpga clock
+    input       pl_refclk_p         ,
+    input       pl_refclk_n         ,
+    // reset
+    input       sys_rst_in          ,
+    // *************************************************************************
+    // ******************************** RF-DAC *********************************
+    // *************************************************************************
+    input       adc0_01_in_p        ,
+    input       adc0_01_in_n        ,
+    input       adc0_23_in_p        ,
+    input       adc0_23_in_n        ,
+    input       adc1_01_in_p        ,
+    input       adc1_01_in_n        ,
+    input       adc1_23_in_p        ,
+    input       adc1_23_in_n        ,
+    input       adc2_01_in_p        ,
+    input       adc2_01_in_n        ,
+    input       adc2_23_in_p        ,
+    input       adc2_23_in_n        ,
+    input       adc3_01_in_p        ,
+    input       adc3_01_in_n        ,
+    input       adc3_23_in_p        ,
+    input       adc3_23_in_n        ,
+    // *************************************************************************
+    // ******************************** RF-DAC *********************************
+    // *************************************************************************
+    output      dac00_out_p         ,
+    output      dac00_out_n         ,
+    output      dac02_out_p         ,
+    output      dac02_out_n         ,
+    output      dac10_out_p         ,
+    output      dac10_out_n         ,
+    output      dac12_out_p         ,
+    output      dac12_out_n         ,
+    output      dac20_out_p         ,
+    output      dac20_out_n         ,
+    output      dac22_out_p         ,
+    output      dac22_out_n         ,
+    output      dac30_out_p         ,
+    output      dac30_out_n         ,
+    output      dac32_out_p         ,
+    output      dac32_out_n         ,
+    // *************************************************************************
+    // ********************** LMK04828 Control Interface ***********************
+    // *************************************************************************
+    output      lmk_spi_sck         ,
+    output      lmk_spi_cs          ,
+    inout       lmk_spi_mosi_sdio   ,
+    input       lmk_spi_miso
+);
+
+////////////////////////////////////////////////////////////////////////////////
+//////////////////////////// Block Design Interface ////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+wire ps_clk0;
+wire sys_clk;
+wire sys_rstn;
+
+// spi interface
+wire spi_sclk      ;
+wire spi_cs        ;
+wire spi_sdi       ;
+wire spi_sdo       ;
+wire spi_sdo_t     ;
+wire spi_three_wire;
+wire spi_active    ;
+
+assign lmk_spi_sck = spi_sclk;
+assign lmk_spi_cs = spi_cs;
+assign spi_sdi = spi_three_wire ? lmk_spi_mosi_sdio : lmk_spi_miso;
+assign lmk_spi_mosi_sdio = spi_sdo_t ? 1'bz : spi_sdo;
+
+// -----------------------------------------------------------------------------
+// ADC Tile & Channel Mapping (Dual RF-ADC)
+// -----------------------------------------------------------------------------
+// m00_axis     adc00       adc tile 224 (adc0), channel 0
+// m01_axis     adc01       adc tile 224 (adc0), channel 1
+// m02_axis     adc02       adc tile 224 (adc0), channel 2
+// m03_axis     adc03       adc tile 224 (adc0), channel 3
+// -----------------------------------------------------------------------------
+// m10_axis     adc10       adc tile 225 (adc1), channel 0
+// m11_axis     adc11       adc tile 225 (adc1), channel 1
+// m12_axis     adc12       adc tile 225 (adc1), channel 2
+// m13_axis     adc13       adc tile 225 (adc1), channel 3
+// -----------------------------------------------------------------------------
+// m20_axis     adc20       adc tile 226 (adc2), channel 0
+// m21_axis     adc21       adc tile 226 (adc2), channel 1
+// m22_axis     adc22       adc tile 226 (adc2), channel 2
+// m23_axis     adc23       adc tile 226 (adc2), channel 3
+// -----------------------------------------------------------------------------
+// m30_axis     adc30       adc tile 227 (adc3), channel 0
+// m31_axis     adc31       adc tile 227 (adc3), channel 1
+// m32_axis     adc32       adc tile 227 (adc3), channel 2
+// m33_axis     adc33       adc tile 227 (adc3), channel 3
+// -----------------------------------------------------------------------------
+// Note:
+// 1) If digital output data is set to real, only channel 0/2 is enabled; if
+// digital output data is set to i/q, both channel 0/2 and 1/3 are enabled,
+// since i/q data are transferred in different channels.
+// 2) When modify the following wire definition, **ONLY** change the data width.
+// The extra definition will be optimized automatically.
+// -----------------------------------------------------------------------------
+wire [15:0] adc00_data, adc01_data;
+wire adc00_data_ready, adc01_data_ready;
+wire adc00_data_valid, adc01_data_valid;
+
+wire [15:0] adc02_data, adc03_data;
+wire adc02_data_ready, adc03_data_ready;
+wire adc02_data_valid, adc03_data_valid;
+
+wire [15:0] adc10_data, adc11_data;
+wire adc10_data_ready, adc11_data_ready;
+wire adc10_data_valid, adc11_data_valid;
+
+wire [15:0] adc12_data, adc13_data;
+wire adc12_data_ready, adc13_data_ready;
+wire adc12_data_valid, adc13_data_valid;
+
+wire [15:0] adc20_data, adc21_data;
+wire adc20_data_ready, adc21_data_ready;
+wire adc20_data_valid, adc21_data_valid;
+
+wire [15:0] adc22_data, adc23_data;
+wire adc22_data_ready, adc23_data_ready;
+wire adc22_data_valid, adc23_data_valid;
+
+wire [15:0] adc30_data, adc31_data;
+wire adc30_data_ready, adc31_data_ready;
+wire adc30_data_valid, adc31_data_valid;
+
+wire [15:0] adc32_data, adc33_data;
+wire adc32_data_ready, adc33_data_ready;
+wire adc32_data_valid, adc33_data_valid;
+
+// -----------------------------------------------------------------------------
+// DAC Tile & Channel Mapping (Dual RF-DAC)
+// -----------------------------------------------------------------------------
+// s00_axis     dac00       dac tile 228 (dac0), channel 0
+// s01_axis     dac00       dac tile 228 (dac0), channel 1
+// s02_axis     dac02       dac tile 228 (dac0), channel 2
+// s03_axis     dac02       dac tile 228 (dac0), channel 3
+// -----------------------------------------------------------------------------
+// s10_axis     dac10       dac tile 229 (dac1), channel 0
+// s11_axis     dac10       dac tile 229 (dac1), channel 1
+// s12_axis     dac12       dac tile 229 (dac1), channel 2
+// s13_axis     dac12       dac tile 229 (dac1), channel 3
+// -----------------------------------------------------------------------------
+// s20_axis     dac20       dac tile 230 (dac2), channel 0
+// s21_axis     dac20       dac tile 230 (dac2), channel 1
+// s22_axis     dac22       dac tile 230 (dac2), channel 2
+// s23_axis     dac22       dac tile 230 (dac2), channel 3
+// -----------------------------------------------------------------------------
+// s30_axis     dac30       dac tile 231 (dac3), channel 0
+// s31_axis     dac30       dac tile 231 (dac3), channel 1
+// s32_axis     dac32       dac tile 231 (dac3), channel 2
+// s33_axis     dac32       dac tile 231 (dac3), channel 3
+// -----------------------------------------------------------------------------
+// Note:
+// 1) In most single-band cases, only channel 0/2 is enabled since i/q data are
+// transferred in one signle channel; when multi-band is used, multiple digital
+// channel may be enabled.
+// 2) When modify the following wire definition, **ONLY** change the data width.
+// The extra definition will be optimized automatically.
+// -----------------------------------------------------------------------------
+wire [31:0] dac00_data, dac01_data;
+wire dac00_data_ready, dac01_data_ready;
+wire dac00_data_valid, dac01_data_valid;
+
+wire [31:0] dac02_data, dac03_data;
+wire dac02_data_ready, dac03_data_ready;
+wire dac02_data_valid, dac03_data_valid;
+
+wire [31:0] dac10_data, dac11_data;
+wire dac10_data_ready, dac11_data_ready;
+wire dac10_data_valid, dac11_data_valid;
+
+wire [31:0] dac12_data, dac13_data;
+wire dac12_data_ready, dac13_data_ready;
+wire dac12_data_valid, dac13_data_valid;
+
+wire [31:0] dac20_data, dac21_data;
+wire dac20_data_ready, dac21_data_ready;
+wire dac20_data_valid, dac21_data_valid;
+
+wire [31:0] dac22_data, dac23_data;
+wire dac22_data_ready, dac23_data_ready;
+wire dac22_data_valid, dac23_data_valid;
+
+wire [31:0] dac30_data, dac31_data;
+wire dac30_data_ready, dac31_data_ready;
+wire dac30_data_valid, dac31_data_valid;
+
+wire [31:0] dac32_data, dac33_data;
+wire dac32_data_ready, dac33_data_ready;
+wire dac32_data_valid, dac33_data_valid;
+
+system_bd_wrapper u_system_bd_wrapper
+(
+    // *************************************************************************
+    // ********************* PL SYSREF & Reference Clocks **********************
+    // *************************************************************************
+    .ps_clk0            (ps_clk0            ),
+
+    .pl_clk_clk_p       (pl_refclk_p        ),
+    .pl_clk_clk_n       (pl_refclk_n        ),
+
+    .pl_sysref_clk_p    (pl_sysref_p        ),
+    .pl_sysref_clk_n    (pl_sysref_n        ),
+
+    .sys_clk            (sys_clk            ),
+    .sys_rstn           (sys_rstn           ),
+
+    // *************************************************************************
+    // ********************* RF SYSREF & Reference Clocks **********************
+    // *************************************************************************
+    .spi_sclk           (spi_sclk           ),
+    .spi_cs             (spi_cs             ),
+    .spi_sdi            (spi_sdi            ),
+    .spi_sdo            (spi_sdo            ),
+    .spi_sdo_t          (spi_sdo_t          ),
+    .spi_three_wire     (spi_three_wire     ),
+    .spi_active         (spi_active         ),
+
+    // *************************************************************************
+    // ********************* RF SYSREF & Reference Clocks **********************
+    // *************************************************************************
+    // rf sysref
+    .sysref_in_diff_p   (rf_sysref_p        ), // input sysref_in_diff_p
+    .sysref_in_diff_n   (rf_sysref_n        ), // input sysref_in_diff_n
+
+    // -------------------------------------------------------------------------
+    // RF ADC Reference Clocks Mapping
+    // -------------------------------------------------------------------------
+    // adc0_clk_clk     adc tile 224 (adc0) ref clock input, nc on borad
+    // adc1_clk_clk     adc tile 225 (adc1) ref clock input, from lmk04828
+    // adc2_clk_clk     adc tile 226 (adc2) ref clock input, from sma
+    // adc3_clk_clk     adc tile 227 (adc3) ref clock input, nc on borad
+    // clk_adc0         adc tile 224 (adc0) clock output
+    // clk_adc1         adc tile 225 (adc1) clock output
+    // clk_adc2         adc tile 226 (adc2) clock output
+    // clk_adc3         adc tile 227 (adc3) clock output
+    // -------------------------------------------------------------------------
+    // Note:
+    // When modify the following wire connections, **ONLY** uncomment the needed
+    // ports and comment the not-needed ones.
+    // -------------------------------------------------------------------------
+    .adc1_clk_clk_p     (adc1_clk_in_p      ), // input adc1_clk_clk_p
+    .adc1_clk_clk_n     (adc1_clk_in_n      ), // input adc1_clk_clk_n
+    // .adc2_clk_clk_p     (adc2_clk_in_p      ), // input adc2_clk_clk_p
+    // .adc2_clk_clk_n     (adc2_clk_in_n      ), // input adc2_clk_clk_n
+    .clk_adc0           (                   ), // output clk_adc0
+    .clk_adc1           (                   ), // output clk_adc1
+    .clk_adc2           (                   ), // output clk_adc2
+    .clk_adc3           (                   ), // output clk_adc3
+
+    // -------------------------------------------------------------------------
+    // RF DAC Reference Clocks Mapping
+    // -------------------------------------------------------------------------
+    // dac0_clk_clk     dac tile 228 (dac0) ref clock input, from lmk04828
+    // dac1_clk_clk     dac tile 229 (dac1) ref clock input, none for zu48dr
+    // dac2_clk_clk     dac tile 230 (dac2) ref clock input, from sma
+    // dac3_clk_clk     dac tile 231 (dac3) ref clock input, none for zu48dr
+    // clk_dac0         dac tile 228 (dac0) clock output
+    // clk_dac1         dac tile 229 (dac1) clock output
+    // clk_dac2         dac tile 230 (dac2) clock output
+    // clk_dac3         dac tile 231 (dac3) clock output
+    // -------------------------------------------------------------------------
+    // Note:
+    // When modify the following wire connections, **ONLY** uncomment the needed
+    // ports and comment the not-needed ones.
+    // -------------------------------------------------------------------------
+    .dac0_clk_clk_p     (dac0_clk_in_p      ), // input dac0_clk_clk_p
+    .dac0_clk_clk_n     (dac0_clk_in_n      ), // input dac0_clk_clk_n
+    // .dac2_clk_clk_p     (dac2_clk_in_p      ), // input dac2_clk_clk_p
+    // .dac2_clk_clk_n     (dac2_clk_in_n      ), // input dac2_clk_clk_n
+    .clk_dac0           (                   ), // output clk_dac0
+    .clk_dac1           (                   ), // output clk_dac1
+    .clk_dac2           (                   ), // output clk_dac2
+    .clk_dac3           (                   ), // output clk_dac3
+
+    // *************************************************************************
+    // *********** RF-ADC Tile 224 (adc0) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .m0_axis_aclk       (sys_clk            ), // input m0_axis_aclk
+    .m0_axis_aresetn    (sys_rstn           ), // input m0_axis_aresetn
+
+    // channel 0 data
+    .m00_axis_tdata     (adc00_data         ), // output [15:0]m00_axis_tdata
+    .m00_axis_tready    (adc00_data_ready   ), // input m00_axis_tready
+    .m00_axis_tvalid    (adc00_data_valid   ), // output m00_axis_tvalid
+    // channel 1 data
+    .m01_axis_tdata     (adc01_data         ), // output [15:0]m01_axis_tdata
+    .m01_axis_tready    (adc01_data_ready   ), // input m01_axis_tready
+    .m01_axis_tvalid    (adc01_data_valid   ), // output m01_axis_tvalid
+    // analog input signal, J3 on board
+    .vin0_01_v_p        (adc0_01_in_p       ), // input vin0_01_v_p
+    .vin0_01_v_n        (adc0_01_in_n       ), // input vin0_01_v_n
+
+    // channel 2 data
+    .m02_axis_tdata     (adc02_data         ), // output [15:0]m02_axis_tdata
+    .m02_axis_tready    (adc02_data_ready   ), // input m02_axis_tready
+    .m02_axis_tvalid    (adc02_data_valid   ), // output m02_axis_tvalid
+    // channel 3 data
+    .m03_axis_tdata     (adc03_data         ), // output [15:0]m03_axis_tdata
+    .m03_axis_tready    (adc03_data_ready   ), // input m03_axis_tready
+    .m03_axis_tvalid    (adc03_data_valid   ), // output m03_axis_tvalid
+    // analog input signal, J5 on board
+    .vin0_23_v_p        (adc0_23_in_p       ), // input vin0_23_v_p
+    .vin0_23_v_n        (adc0_23_in_n       ), // input vin0_23_v_n
+
+    // *************************************************************************
+    // *********** RF-ADC Tile 225 (adc1) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .m1_axis_aclk       (sys_clk            ), // input m1_axis_aclk
+    .m1_axis_aresetn    (sys_rstn           ), // input m1_axis_aresetn
+
+    // channel 0 data
+    .m10_axis_tdata     (adc10_data         ), // output [15:0]m10_axis_tdata
+    .m10_axis_tready    (adc10_data_ready   ), // input m10_axis_tready
+    .m10_axis_tvalid    (adc10_data_valid   ), // output m10_axis_tvalid
+    // channel 1 data
+    .m11_axis_tdata     (adc11_data         ), // output [15:0]m11_axis_tdata
+    .m11_axis_tready    (adc11_data_ready   ), // input m11_axis_tready
+    .m11_axis_tvalid    (adc11_data_valid   ), // output m11_axis_tvalid
+    // analog input signal, J6 on board
+    .vin1_01_v_p        (adc1_01_in_p       ), // input vin1_01_v_p
+    .vin1_01_v_n        (adc1_01_in_n       ), // input vin1_01_v_n
+
+    // channel 2 data
+    .m12_axis_tdata     (adc12_data         ), // output [15:0]m12_axis_tdata
+    .m12_axis_tready    (adc12_data_ready   ), // input m12_axis_tready
+    .m12_axis_tvalid    (adc12_data_valid   ), // output m12_axis_tvalid
+    // channel 3 data
+    .m13_axis_tdata     (adc13_data         ), // output [15:0]m13_axis_tdata
+    .m13_axis_tready    (adc13_data_ready   ), // input m13_axis_tready
+    .m13_axis_tvalid    (adc13_data_valid   ), // output m13_axis_tvalid
+    // analog input signal, J7 on board
+    .vin1_23_v_p        (adc1_23_in_p       ), // input vin1_23_v_p
+    .vin1_23_v_n        (adc1_23_in_n       ), // input vin1_23_v_n
+
+    // *************************************************************************
+    // *********** RF-ADC Tile 226 (adc2) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .m2_axis_aclk       (sys_clk            ), // input m2_axis_aclk
+    .m2_axis_aresetn    (sys_rstn           ), // input m2_axis_aresetn
+
+    // channel 0 data
+    .m20_axis_tdata     (adc20_data         ), // output [15:0]m20_axis_tdata
+    .m20_axis_tready    (adc20_data_ready   ), // input m20_axis_tready
+    .m20_axis_tvalid    (adc20_data_valid   ), // output m20_axis_tvalid
+    // channel 1 data
+    .m21_axis_tdata     (adc21_data         ), // output [15:0]m21_axis_tdata
+    .m21_axis_tready    (adc21_data_ready   ), // input m21_axis_tready
+    .m21_axis_tvalid    (adc21_data_valid   ), // output m21_axis_tvalid
+    // analog input signal, J8 on board
+    .vin2_01_v_p        (adc2_01_in_p       ), // input vin2_01_v_p
+    .vin2_01_v_n        (adc2_01_in_n       ), // input vin2_01_v_n
+
+    // channel 2 data
+    .m22_axis_tdata     (adc22_data         ), // output [15:0]m22_axis_tdata
+    .m22_axis_tready    (adc22_data_ready   ), // input m22_axis_tready
+    .m22_axis_tvalid    (adc22_data_valid   ), // output m22_axis_tvalid
+    // channel 3 data
+    .m23_axis_tdata     (adc23_data         ), // output [15:0]m23_axis_tdata
+    .m23_axis_tready    (adc23_data_ready   ), // input m23_axis_tready
+    .m23_axis_tvalid    (adc23_data_valid   ), // output m23_axis_tvalid
+    // analog input signal, J9 on board
+    .vin2_23_v_p        (adc2_23_in_p       ), // input vin2_23_v_p
+    .vin2_23_v_n        (adc2_23_in_n       ), // input vin2_23_v_n
+
+    // *************************************************************************
+    // *********** RF-ADC Tile 227 (adc3) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .m3_axis_aclk       (sys_clk            ), // input m3_axis_aclk
+    .m3_axis_aresetn    (sys_rstn           ), // input m3_axis_aresetn
+
+    // channel 0 data
+    .m30_axis_tdata     (adc30_data         ), // output [15:0]m30_axis_tdata
+    .m30_axis_tready    (adc30_data_ready   ), // input m30_axis_tready
+    .m30_axis_tvalid    (adc30_data_valid   ), // output m30_axis_tvalid
+    // channel 1 data
+    .m31_axis_tdata     (adc31_data         ), // output [15:0]m31_axis_tdata
+    .m31_axis_tready    (adc31_data_ready   ), // input m31_axis_tready
+    .m31_axis_tvalid    (adc31_data_valid   ), // output m31_axis_tvalid
+    // analog input signal, J10 on board
+    .vin3_01_v_p        (adc3_01_in_p       ), // input vin3_01_v_p
+    .vin3_01_v_n        (adc3_01_in_n       ), // input vin3_01_v_n
+
+    // channel 2 data
+    .m32_axis_tdata     (adc32_data         ), // output [15:0]m32_axis_tdata
+    .m32_axis_tready    (adc32_data_ready   ), // input m32_axis_tready
+    .m32_axis_tvalid    (adc32_data_valid   ), // output m32_axis_tvalid
+    // channel 3 data
+    .m33_axis_tdata     (adc33_data         ), // output [15:0]m33_axis_tdata
+    .m33_axis_tready    (adc33_data_ready   ), // input m33_axis_tready
+    .m33_axis_tvalid    (adc33_data_valid   ), // output m33_axis_tvalid
+    // analog input signal, J12 on board
+    .vin3_23_v_p        (adc3_23_in_p       ), // input vin3_23_v_p
+    .vin3_23_v_n        (adc3_23_in_n       ), // input vin3_23_v_n
+
+    // *************************************************************************
+    // *********** RF-DAC Tile 228 (dac0) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .s0_axis_aclk       (sys_clk            ), // input s0_axis_aclk
+    .s0_axis_aresetn    (sys_rstn           ), // input s0_axis_aresetn
+
+    // channel 0 data
+    .s00_axis_tdata     (dac00_data         ), // input [31:0]s00_axis_tdata
+    .s00_axis_tready    (dac00_data_ready   ), // output s00_axis_tready
+    .s00_axis_tvalid    (dac00_data_valid   ), // input s00_axis_tvalid
+    // channel 1 data
+    // .s01_axis_tdata     (dac01_data         ), // input [31:0]s01_axis_tdata
+    // .s01_axis_tready    (dac01_data_ready   ), // output s01_axis_tready
+    // .s01_axis_tvalid    (dac01_data_valid   ), // input s01_axis_tvalid
+    // analog output signal, J14 on board
+    .vout00_v_p         (dac00_out_p        ), // output vout00_v_p
+    .vout00_v_n         (dac00_out_n        ), // output vout00_v_n
+
+    // channel 2 data
+    .s02_axis_tdata     (dac02_data         ), // input [31:0]s02_axis_tdata
+    .s02_axis_tready    (dac02_data_ready   ), // output s02_axis_tready
+    .s02_axis_tvalid    (dac02_data_valid   ), // input s02_axis_tvalid
+    // channel 3 data
+    // .s03_axis_tdata     (dac03_data         ), // input [31:0]s03_axis_tdata
+    // .s03_axis_tready    (dac03_data_ready   ), // output s03_axis_tready
+    // .s03_axis_tvalid    (dac03_data_valid   ), // input s03_axis_tvalid
+    // analog output signal, J16 on board
+    .vout02_v_p         (dac02_out_p        ), // output vout02_v_p
+    .vout02_v_n         (dac02_out_n        ), // output vout02_v_n
+
+    // *************************************************************************
+    // *********** RF-DAC Tile 229 (dac1) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .s1_axis_aclk       (sys_clk            ), // input s1_axis_aclk
+    .s1_axis_aresetn    (sys_rstn           ), // input s1_axis_aresetn
+
+    // channel 0 data
+    .s10_axis_tdata     (dac10_data         ), // input [31:0]s10_axis_tdata
+    .s10_axis_tready    (dac10_data_ready   ), // output s10_axis_tready
+    .s10_axis_tvalid    (dac10_data_valid   ), // input s10_axis_tvalid
+    // channel 1 data
+    // .s11_axis_tdata     (dac11_data         ), // input [31:0]s11_axis_tdata
+    // .s11_axis_tready    (dac11_data_ready   ), // output s11_axis_tready
+    // .s11_axis_tvalid    (dac11_data_valid   ), // input s11_axis_tvalid
+    // analog output signal, J17 on board
+    .vout10_v_p         (dac10_out_p        ), // output vout10_v_p
+    .vout10_v_n         (dac10_out_n        ), // output vout10_v_n
+
+    // channel 2 data
+    .s12_axis_tdata     (dac12_data         ), // input [31:0]s12_axis_tdata
+    .s12_axis_tready    (dac12_data_ready   ), // output s12_axis_tready
+    .s12_axis_tvalid    (dac12_data_valid   ), // input s12_axis_tvalid
+    // channel 3 data
+    // .s13_axis_tdata     (dac13_data         ), // input [31:0]s13_axis_tdata
+    // .s13_axis_tready    (dac13_data_ready   ), // output s13_axis_tready
+    // .s13_axis_tvalid    (dac13_data_valid   ), // input s13_axis_tvalid
+    // analog output signal, J18 on board
+    .vout12_v_p         (dac12_out_p        ), // output vout12_v_p
+    .vout12_v_n         (dac12_out_n        ), // output vout12_v_n
+
+    // *************************************************************************
+    // *********** RF-DAC Tile 230 (dac2) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .s2_axis_aclk       (sys_clk            ), // input s2_axis_aclk
+    .s2_axis_aresetn    (sys_rstn           ), // input s2_axis_aresetn
+
+    // channel 0 data
+    .s20_axis_tdata     (dac20_data         ), // input [31:0]s20_axis_tdata
+    .s20_axis_tready    (dac20_data_ready   ), // output s20_axis_tready
+    .s20_axis_tvalid    (dac20_data_valid   ), // input s20_axis_tvalid
+    // channel 1 data
+    // .s21_axis_tdata     (dac21_data         ), // input [31:0]s21_axis_tdata
+    // .s21_axis_tready    (dac21_data_ready   ), // output s21_axis_tready
+    // .s21_axis_tvalid    (dac21_data_valid   ), // input s21_axis_tvalid
+    // analog output signal, J19 on board
+    .vout20_v_p         (dac20_out_p        ), // output vout20_v_p
+    .vout20_v_n         (dac20_out_n        ), // output vout20_v_n
+
+    // channel 2 data
+    .s22_axis_tdata     (dac22_data         ), // input [31:0]s22_axis_tdata
+    .s22_axis_tready    (dac22_data_ready   ), // output s22_axis_tready
+    .s22_axis_tvalid    (dac22_data_valid   ), // input s22_axis_tvalid
+    // channel 3 data
+    // .s23_axis_tdata     (dac23_data         ), // input [31:0]s23_axis_tdata
+    // .s23_axis_tready    (dac23_data_ready   ), // output s23_axis_tready
+    // .s23_axis_tvalid    (dac23_data_valid   ), // input s23_axis_tvalid
+    // analog output signal, J20 on board
+    .vout22_v_p         (dac22_out_p        ), // output vout22_v_p
+    .vout22_v_n         (dac22_out_n        ), // output vout22_v_n
+
+    // *************************************************************************
+    // *********** RF-DAC Tile 231 (dac3) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .s3_axis_aclk       (sys_clk            ), // input s3_axis_aclk
+    .s3_axis_aresetn    (sys_rstn           ), // input s3_axis_aresetn
+
+    // channel 0 data
+    .s30_axis_tdata     (dac30_data         ), // input [31:0]s30_axis_tdata
+    .s30_axis_tready    (dac30_data_ready   ), // output s30_axis_tready
+    .s30_axis_tvalid    (dac30_data_valid   ), // input s30_axis_tvalid
+    // channel 1 data
+    // .s31_axis_tdata     (dac31_data         ), // input [31:0]s31_axis_tdata
+    // .s31_axis_tready    (dac31_data_ready   ), // output s31_axis_tready
+    // .s31_axis_tvalid    (dac31_data_valid   ), // input s31_axis_tvalid
+    // analog output signal, J21 on board
+    .vout30_v_p         (dac30_out_p        ), // output vout30_v_p
+    .vout30_v_n         (dac30_out_n        ), // output vout30_v_n
+
+    // channel 2 data
+    .s32_axis_tdata     (dac32_data         ), // input [31:0]s32_axis_tdata
+    .s32_axis_tready    (dac32_data_ready   ), // output s32_axis_tready
+    .s32_axis_tvalid    (dac32_data_valid   ), // input s32_axis_tvalid
+    // channel 3 data
+    // .s33_axis_tdata     (dac33_data         ), // input [31:0]s33_axis_tdata
+    // .s33_axis_tready    (dac33_data_ready   ), // output s33_axis_tready
+    // .s33_axis_tvalid    (dac33_data_valid   ), // input s33_axis_tvalid
+    // analog output signal, J23 on board
+    .vout32_v_p         (dac32_out_p        ), // output vout32_v_p
+    .vout32_v_n         (dac32_out_n        )  // output vout32_v_n
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////// Tx Signal ///////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// tx signal mapping
+wire    [15:0]  tx_data_i, tx_data_q;
+
+assign dac00_data = {tx_data_q, tx_data_i};
+assign dac02_data = {tx_data_q, tx_data_i};
+assign dac10_data = {tx_data_q, tx_data_i};
+assign dac12_data = {tx_data_q, tx_data_i};
+assign dac20_data = {tx_data_q, tx_data_i};
+assign dac22_data = {tx_data_q, tx_data_i};
+assign dac30_data = {tx_data_q, tx_data_i};
+assign dac32_data = {tx_data_q, tx_data_i};
+
+// transmitter logic
+wire    [ 1:0]  waveform_sel;
+wire            sweep_on    ;
+wire    [31:0]  freq_set    ;
+wire    [ 1:0]  iq_sel      ;
+wire    [ 3:0]  bb_rshift   ;
+
+tx_multi_rate_qpsk u_tx_qpsk
+(
+    // clock & reset
+    .aclk           (sys_clk        ),
+    .aresetn        (sys_rstn       ),
+    // data control
+    .waveform_sel   (waveform_sel   ),
+    .sweep_on       (sweep_on       ),
+    .freq_set       (freq_set       ),
+    .iq_sel         (iq_sel         ),
+    .bb_rshift      (bb_rshift      ),
+    // data output
+    .m_axis_tvalid  (               ),
+    .m_axis_tready  (1'b1           ),
+    .m_axis_tdata   ({tx_data_q,tx_data_i})
+);
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////// Rx Signal ///////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// rx signal mapping
+wire    [15:0]  rx_ch1_i, rx_ch1_q;
+wire    [15:0]  rx_ch2_i, rx_ch2_q;
+wire    [15:0]  rx_ch3_i, rx_ch3_q;
+wire    [15:0]  rx_ch4_i, rx_ch4_q;
+wire    [15:0]  rx_ch5_i, rx_ch5_q;
+wire    [15:0]  rx_ch6_i, rx_ch6_q;
+wire    [15:0]  rx_ch7_i, rx_ch7_q;
+wire    [15:0]  rx_ch8_i, rx_ch8_q;
+
+assign rx_ch1_i = adc00_data;
+assign rx_ch1_q = adc01_data;
+assign rx_ch2_i = adc02_data;
+assign rx_ch2_q = adc03_data;
+assign rx_ch3_i = adc10_data;
+assign rx_ch3_q = adc11_data;
+assign rx_ch4_i = adc12_data;
+assign rx_ch4_q = adc13_data;
+assign rx_ch5_i = adc20_data;
+assign rx_ch5_q = adc21_data;
+assign rx_ch6_i = adc22_data;
+assign rx_ch6_q = adc23_data;
+assign rx_ch7_i = adc30_data;
+assign rx_ch7_q = adc31_data;
+assign rx_ch8_i = adc32_data;
+assign rx_ch8_q = adc33_data;
+
+// receiver logic
+
+
+////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////// ILAs and VIOs /////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+ila_adc u_ila_adc
+(
+    .clk    (sys_clk            ), // input wire clk
+    .probe0 (rx_ch1_i           ), // input wire [15:0]  probe0
+    .probe1 (rx_ch1_q           ), // input wire [15:0]  probe1
+    .probe2 (rx_ch2_i           ), // input wire [15:0]  probe2
+    .probe3 (rx_ch2_q           ), // input wire [15:0]  probe3
+    .probe4 (rx_ch3_i           ), // input wire [15:0]  probe4
+    .probe5 (rx_ch3_q           ), // input wire [15:0]  probe5
+    .probe6 (rx_ch4_i           ), // input wire [15:0]  probe6
+    .probe7 (rx_ch4_q           ), // input wire [15:0]  probe7
+    .probe8 (rx_ch5_i           ), // input wire [15:0]  probe8
+    .probe9 (rx_ch5_q           ), // input wire [15:0]  probe9
+    .probe10(rx_ch6_i           ), // input wire [15:0]  probe10
+    .probe11(rx_ch6_q           ), // input wire [15:0]  probe11
+    .probe12(rx_ch7_i           ), // input wire [15:0]  probe12
+    .probe13(rx_ch7_q           ), // input wire [15:0]  probe13
+    .probe14(rx_ch8_i           ), // input wire [15:0]  probe14
+    .probe15(rx_ch8_q           )  // input wire [15:0]  probe15
+);
+
+ila_dac u_ila_dac
+(
+    .clk    (sys_clk            ), // input wire clk
+    .probe0 (tx_data_i          ), // input wire [15:0]  probe0
+    .probe1 (tx_data_q          )  // input wire [15:0]  probe1
+);
+
+vio_manual_ctrl u_vio_manual_ctrl
+(
+    .clk        (sys_clk            ), // input wire clk
+    .probe_out0 (waveform_sel[1:0]  ), // output wire [1 : 0] probe_out0
+    .probe_out1 (sweep_on           ), // output wire [0 : 0] probe_out1
+    .probe_out2 (freq_set[31:0]     ), // output wire [31 : 0] probe_out2
+    .probe_out3 (iq_sel[1:0]        ), // output wire [1 : 0] probe_out3
+    .probe_out4 (bb_rshift[3:0]     )  // output wire [3 : 0] probe_out4
+);
+
+endmodule

rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/new/tx_multi_rate_qpsk.v

@@ -0,0 +1,482 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 11/05/2024 10:47:12 AM
+// Design Name:
+// Module Name: tx_multi_rate_qpsk
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tx_multi_rate_qpsk
+#(
+    parameter POLYNOMIAL = "PRBS23",
+    parameter DATA_WIDTH = 16 // need to be <= 16
+)
+(
+    // clock & reset
+    aclk            ,
+    aresetn         ,
+    // data control
+    waveform_sel    ,
+    sweep_on        ,
+    freq_set        ,
+    iq_sel          ,
+    bb_rshift       ,
+    // data output
+    m_axis_tvalid   ,
+    m_axis_tready   ,
+    m_axis_tdata
+);
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////// Top Level Port Declaration //////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+
+// clock & reset
+input aclk;
+input aresetn;
+// data control
+input [1:0] waveform_sel;
+input sweep_on;
+input [31:0] freq_set;
+input [1:0] iq_sel;
+input [3:0] bb_rshift;
+// data output
+output reg m_axis_tvalid = 'b0;
+input m_axis_tready;
+output [31:0] m_axis_tdata;
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////// Bit Data Generator //////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// 1.5 Msps m sequence generator
+wire m_seq_1m5_valid;
+wire m_seq_1m5_ready;
+wire [1:0] m_seq_1m5_tdata;
+wire [7:0] m_seq_1m5_axis_tdata;
+
+assign m_seq_1m5_tdata = m_seq_1m5_axis_tdata[1:0];
+
+m_seq_gen #(
+    .POLYNOMIAL(POLYNOMIAL),
+    .BIT_WIDTH(2)
+)
+u_m_seq_1m5_gen
+(
+    .aclk           (aclk                   ),
+    .aresetn        (aresetn                ),
+    .m_axis_tvalid  (m_seq_1m5_valid        ),
+    .m_axis_tready  (m_seq_1m5_ready        ),
+    .m_axis_tdata   (m_seq_1m5_axis_tdata   )
+);
+
+// 12 Msps m sequence generator
+wire m_seq_12m_valid;
+wire m_seq_12m_ready;
+wire [1:0] m_seq_12m_tdata;
+wire [7:0] m_seq_12m_axis_tdata;
+
+assign m_seq_12m_tdata = m_seq_12m_axis_tdata[1:0];
+
+m_seq_gen #(
+    .POLYNOMIAL(POLYNOMIAL),
+    .BIT_WIDTH(2)
+)
+u_m_seq_12m_gen
+(
+    .aclk           (aclk                   ),
+    .aresetn        (aresetn                ),
+    .m_axis_tvalid  (m_seq_12m_valid        ),
+    .m_axis_tready  (m_seq_12m_ready        ),
+    .m_axis_tdata   (m_seq_12m_axis_tdata   )
+);
+
+// 48 Msps m sequence generator
+wire m_seq_48m_valid;
+wire m_seq_48m_ready;
+wire [1:0] m_seq_48m_tdata;
+wire [7:0] m_seq_48m_axis_tdata;
+
+assign m_seq_48m_tdata = m_seq_48m_axis_tdata[1:0];
+
+m_seq_gen #(
+    .POLYNOMIAL(POLYNOMIAL),
+    .BIT_WIDTH(2)
+)
+u_m_seq_48m_gen
+(
+    .aclk           (aclk                   ),
+    .aresetn        (aresetn                ),
+    .m_axis_tvalid  (m_seq_48m_valid        ),
+    .m_axis_tready  (m_seq_48m_ready        ),
+    .m_axis_tdata   (m_seq_48m_axis_tdata   )
+);
+
+////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////// Shaping Filter ////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// 1.5 Msps shaping filter
+wire hrc_data_1m5_i_valid;
+wire hrc_data_1m5_i_ready;
+wire [7:0] hrc_data_1m5_i_tdata;
+
+wire hrc_wave_1m5_i_valid;
+wire [17:0] hrc_wave_1m5_i_tdata;
+wire [23:0] hrc_wave_1m5_i_axis_tdata;
+
+wire hrc_data_1m5_q_valid;
+wire hrc_data_1m5_q_ready;
+wire [7:0] hrc_data_1m5_q_tdata;
+
+wire hrc_wave_1m5_q_valid;
+wire [17:0] hrc_wave_1m5_q_tdata;
+wire [23:0] hrc_wave_1m5_q_axis_tdata;
+
+assign hrc_data_1m5_i_valid = m_seq_1m5_valid;
+assign m_seq_1m5_ready = hrc_data_1m5_i_ready;
+assign hrc_data_1m5_i_tdata = {{7{m_seq_1m5_tdata[0]}},1'b1};
+assign hrc_wave_1m5_i_tdata = hrc_wave_1m5_i_axis_tdata[0 +: 18];
+
+assign hrc_data_1m5_q_valid = m_seq_1m5_valid;
+// assign m_seq_1m5_ready = hrc_data_1m5_q_ready;
+assign hrc_data_1m5_q_tdata = {{7{m_seq_1m5_tdata[1]}},1'b1};
+assign hrc_wave_1m5_q_tdata = hrc_wave_1m5_q_axis_tdata[0 +: 18];
+
+hrc_400_12_03 i_hrc_400_12_03
+(
+    .aclk               (aclk                       ), // input wire aclk
+    .s_axis_data_tvalid (hrc_data_1m5_i_valid       ), // input wire s_axis_data_tvalid
+    .s_axis_data_tready (hrc_data_1m5_i_ready       ), // output wire s_axis_data_tready
+    .s_axis_data_tdata  (hrc_data_1m5_i_tdata       ), // input wire [7 : 0] s_axis_data_tdata
+    .m_axis_data_tvalid (hrc_wave_1m5_i_valid       ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata  (hrc_wave_1m5_i_axis_tdata  )  // output wire [23 : 0] m_axis_data_tdata
+);
+
+hrc_400_12_03 q_hrc_400_12_03
+(
+    .aclk               (aclk                       ), // input wire aclk
+    .s_axis_data_tvalid (hrc_data_1m5_q_valid       ), // input wire s_axis_data_tvalid
+    .s_axis_data_tready (hrc_data_1m5_q_ready       ), // output wire s_axis_data_tready
+    .s_axis_data_tdata  (hrc_data_1m5_q_tdata       ), // input wire [7 : 0] s_axis_data_tdata
+    .m_axis_data_tvalid (hrc_wave_1m5_q_valid       ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata  (hrc_wave_1m5_q_axis_tdata  )  // output wire [23 : 0] m_axis_data_tdata
+);
+
+// 12 Msps shaping filter
+wire hrc_data_12m_i_valid;
+wire hrc_data_12m_i_ready;
+wire [7:0] hrc_data_12m_i_tdata;
+
+wire hrc_wave_12m_i_valid;
+wire [17:0] hrc_wave_12m_i_tdata;
+wire [23:0] hrc_wave_12m_i_axis_tdata;
+
+wire hrc_data_12m_q_valid;
+wire hrc_data_12m_q_ready;
+wire [7:0] hrc_data_12m_q_tdata;
+
+wire hrc_wave_12m_q_valid;
+wire [17:0] hrc_wave_12m_q_tdata;
+wire [23:0] hrc_wave_12m_q_axis_tdata;
+
+assign hrc_data_12m_i_valid = m_seq_12m_valid;
+assign m_seq_12m_ready = hrc_data_12m_i_ready;
+assign hrc_data_12m_i_tdata = {{7{m_seq_12m_tdata[0]}},1'b1};
+assign hrc_wave_12m_i_tdata = hrc_wave_12m_i_axis_tdata[0 +: 18];
+
+assign hrc_data_12m_q_valid = m_seq_12m_valid;
+// assign m_seq_12m_ready = hrc_data_12m_q_ready;
+assign hrc_data_12m_q_tdata = {{7{m_seq_12m_tdata[1]}},1'b1};
+assign hrc_wave_12m_q_tdata = hrc_wave_12m_q_axis_tdata[0 +: 18];
+
+hrc_50_12_03 i_hrc_50_12_03
+(
+    .aclk               (aclk                       ), // input wire aclk
+    .s_axis_data_tvalid (hrc_data_12m_i_valid       ), // input wire s_axis_data_tvalid
+    .s_axis_data_tready (hrc_data_12m_i_ready       ), // output wire s_axis_data_tready
+    .s_axis_data_tdata  (hrc_data_12m_i_tdata       ), // input wire [7 : 0] s_axis_data_tdata
+    .m_axis_data_tvalid (hrc_wave_12m_i_valid       ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata  (hrc_wave_12m_i_axis_tdata  )  // output wire [23 : 0] m_axis_data_tdata
+);
+
+hrc_50_12_03 q_hrc_50_12_03
+(
+    .aclk               (aclk                       ), // input wire aclk
+    .s_axis_data_tvalid (hrc_data_12m_q_valid       ), // input wire s_axis_data_tvalid
+    .s_axis_data_tready (hrc_data_12m_q_ready       ), // output wire s_axis_data_tready
+    .s_axis_data_tdata  (hrc_data_12m_q_tdata       ), // input wire [7 : 0] s_axis_data_tdata
+    .m_axis_data_tvalid (hrc_wave_12m_q_valid       ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata  (hrc_wave_12m_q_axis_tdata  )  // output wire [23 : 0] m_axis_data_tdata
+);
+
+// 48 Msps shaping filter
+wire hrc_data_48m_i_valid;
+wire hrc_data_48m_i_ready;
+wire [7:0] hrc_data_48m_i_tdata;
+
+wire hrc_wave_48m_i_valid;
+wire [17:0] hrc_wave_48m_i_tdata;
+wire [23:0] hrc_wave_48m_i_axis_tdata;
+
+wire hrc_data_48m_q_valid;
+wire hrc_data_48m_q_ready;
+wire [7:0] hrc_data_48m_q_tdata;
+
+wire hrc_wave_48m_q_valid;
+wire [17:0] hrc_wave_48m_q_tdata;
+wire [23:0] hrc_wave_48m_q_axis_tdata;
+
+assign hrc_data_48m_i_valid = m_seq_48m_valid;
+assign m_seq_48m_ready = hrc_data_48m_i_ready;
+assign hrc_data_48m_i_tdata = {{7{m_seq_48m_tdata[0]}},1'b1};
+assign hrc_wave_48m_i_tdata = hrc_wave_48m_i_axis_tdata[0 +: 18];
+
+assign hrc_data_48m_q_valid = m_seq_48m_valid;
+// assign m_seq_48m_ready = hrc_data_48m_q_ready;
+assign hrc_data_48m_q_tdata = {{7{m_seq_48m_tdata[1]}},1'b1};
+assign hrc_wave_48m_q_tdata = hrc_wave_48m_q_axis_tdata[0 +: 18];
+
+hrc_25_12_03 i_hrc_25_12_03
+(
+    .aclk               (aclk                       ), // input wire aclk
+    .s_axis_data_tvalid (hrc_data_48m_i_valid       ), // input wire s_axis_data_tvalid
+    .s_axis_data_tready (hrc_data_48m_i_ready       ), // output wire s_axis_data_tready
+    .s_axis_data_tdata  (hrc_data_48m_i_tdata       ), // input wire [7 : 0] s_axis_data_tdata
+    .m_axis_data_tvalid (hrc_wave_48m_i_valid       ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata  (hrc_wave_48m_i_axis_tdata  )  // output wire [23 : 0] m_axis_data_tdata
+);
+
+hrc_25_12_03 q_hrc_25_12_03
+(
+    .aclk               (aclk                       ), // input wire aclk
+    .s_axis_data_tvalid (hrc_data_48m_q_valid       ), // input wire s_axis_data_tvalid
+    .s_axis_data_tready (hrc_data_48m_q_ready       ), // output wire s_axis_data_tready
+    .s_axis_data_tdata  (hrc_data_48m_q_tdata       ), // input wire [7 : 0] s_axis_data_tdata
+    .m_axis_data_tvalid (hrc_wave_48m_q_valid       ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata  (hrc_wave_48m_q_axis_tdata  )  // output wire [23 : 0] m_axis_data_tdata
+);
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////// Waveform Selection & Hopping Control /////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// baseband signal select
+reg [17:0] baseband_sel_i = 'b0;
+reg [17:0] baseband_sel_q = 'b0;
+
+always @(posedge aclk) begin
+    if (!aresetn) begin
+        baseband_sel_i <= 'b0;
+        baseband_sel_q <= 'b0;
+    end
+    else begin
+        case (waveform_sel[1:0])
+            2'd0: begin
+                baseband_sel_i <= {hrc_wave_48m_i_tdata[16:0],1'b0};
+                baseband_sel_q <= {hrc_wave_48m_q_tdata[16:0],1'b0};
+            end
+            2'd1: begin
+                baseband_sel_i <= {hrc_wave_12m_i_tdata[16:0],1'b0};
+                baseband_sel_q <= {hrc_wave_12m_q_tdata[16:0],1'b0};
+            end
+            2'd2: begin
+                baseband_sel_i <= {hrc_wave_1m5_i_tdata[16:0],1'b0};
+                baseband_sel_q <= {hrc_wave_1m5_q_tdata[16:0],1'b0};
+            end
+            2'd3: begin
+				baseband_sel_i <= 18'b01_1111_1111_1111_1111;
+                baseband_sel_q <= 18'b0;
+            end
+            default: begin
+                baseband_sel_i <= {hrc_wave_48m_i_tdata[16:0],1'b0};
+                baseband_sel_q <= {hrc_wave_48m_q_tdata[16:0],1'b0};
+            end
+        endcase
+    end
+end
+
+// hopping control, 3750hop/s
+reg     [23:0]  sweep_rom_addr = 'b0;
+wire    [31:0]  freq_sweep;
+
+always @(posedge aclk) begin
+    if (!aresetn) begin
+        sweep_rom_addr <= 'b0;
+    end
+    else if (sweep_on) begin
+        sweep_rom_addr <= sweep_rom_addr + 24'b1;
+    end
+    else begin
+        sweep_rom_addr <= 'b0;
+    end
+end
+
+hop_rom u_sweep_rom
+(
+    .clka       (aclk                   ), // input wire clka
+    .addra      (sweep_rom_addr[23:16]  ), // input wire [7 : 0] addra
+    .douta      (freq_sweep             )  // output wire [31 : 0] douta
+);
+
+// choose the actual frequency word
+reg     [31:0]  freq_word = 'b0;
+
+always @(posedge aclk) begin
+    if (!aresetn) begin
+        freq_word <= 'b0;
+    end
+    else if (sweep_on) begin
+        // frequency sweep
+        freq_word <= freq_sweep;
+    end
+    else begin
+        // normal operation
+        freq_word <= freq_set;
+    end
+end
+
+// baseband frequency shift carrier generation
+wire    [ 7:0] cos_dds;
+wire    [ 7:0] sin_dds;
+reg     [ 7:0] cos = 'b0;
+reg     [ 7:0] sin = 'b0;
+
+dds_32b_8b u_dds_bb_shift (
+    .aclk                 (aclk             ), // input wire aclk
+    .s_axis_config_tvalid (aresetn          ), // input wire s_axis_config_tvalid
+    .s_axis_config_tdata  (freq_word        ), // input wire [31 : 0] s_axis_config_tdata
+    .m_axis_data_tvalid   (                 ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata    ({sin_dds,cos_dds})  // output wire [31 : 0] m_axis_data_tdata
+);
+
+always @(posedge aclk) begin
+    if (!aresetn) begin
+        cos <= 'b0;
+        sin <= 'b0;
+    end
+    else if (freq_word == 'b0) begin
+        // to make sure the carriers stay at the right position when freq = 0
+        cos <= 8'b0111_1111;
+        sin <= 8'b0111_1111;
+    end
+    else begin
+        cos <= cos_dds;
+        sin <= sin_dds;
+    end
+end
+
+// baseband frequency shift modulation
+wire    [47:0]  mod_cmpy_a;
+wire    [15:0]  mod_cmpy_b;
+wire    [63:0]  mod_cmpy_out;
+
+wire    [26:0]  baseband_mult_i;
+wire    [26:0]  baseband_mult_q;
+
+assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
+assign mod_cmpy_b = {-sin,cos};
+
+assign baseband_mult_i = mod_cmpy_out[58:32];
+assign baseband_mult_q = mod_cmpy_out[26: 0];
+
+cmpy_18x8 u_cmpy_18x8
+(
+    .aclk               (aclk           ), // input wire aclk
+    .s_axis_a_tvalid    (aresetn        ), // input wire s_axis_a_tvalid
+    .s_axis_a_tdata     (mod_cmpy_a     ), // input wire [47 : 0] s_axis_a_tdata
+    .s_axis_b_tvalid    (aresetn        ), // input wire s_axis_b_tvalid
+    .s_axis_b_tdata     (mod_cmpy_b     ), // input wire [15 : 0] s_axis_b_tdata
+    .m_axis_dout_tvalid (               ), // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata  (mod_cmpy_out   )  // output wire [63 : 0] m_axis_dout_tdata
+);
+
+// truncate to 16-bit
+reg signed  [15:0]  baseband_i = 'b0;
+reg signed  [15:0]  baseband_q = 'b0;
+
+always @(posedge aclk) begin
+    if (!aresetn) begin
+        baseband_i <= 'b0;
+        baseband_q <= 'b0;
+    end
+    else begin
+        case (waveform_sel[1:0])
+            2'd0: begin
+                // scale raised-cosine-shaped bpsk signal by 1.125 or 1.625
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[25:10];
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[25:10];
+            end
+            2'd1: begin
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[25:10];
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[25:10];
+            end
+            2'd2: begin
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[25:10];
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[25:10];
+            end
+            2'd3: begin
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
+            end
+            default: begin
+                // scale raised-cosine-shaped bpsk signal by 1.125
+                baseband_i <= baseband_mult_i[25:10];
+                baseband_q <= baseband_mult_q[25:10];
+            end
+        endcase
+    end
+end
+
+// iq selection & baseband right shift
+reg signed [15:0] baseband_data_i = 'b0;
+reg signed [15:0] baseband_data_q = 'b0;
+
+always @(posedge aclk) begin
+    if (!aresetn) begin
+        baseband_data_i <= 'b0;
+        baseband_data_q <= 'b0;
+    end
+    else begin
+        // inphase selection
+        if (iq_sel[1]) begin
+            baseband_data_i <= baseband_i >>> bb_rshift;
+        end
+        else begin
+            baseband_data_i <= 'b0;
+        end
+        // quadrature selection
+        if (iq_sel[0]) begin
+            baseband_data_q <= baseband_q >>> bb_rshift;
+        end
+        else begin
+            baseband_data_q <= 'b0;
+        end
+    end
+end
+
+always @(posedge aclk) begin
+    if (!aresetn) begin
+        m_axis_tvalid <= 'b0;
+    end
+    else begin
+        m_axis_tvalid <= m_axis_tready;
+    end
+end
+
+// output data to ports
+assign m_axis_tdata[0 +: 16] = {{(16-DATA_WIDTH){baseband_data_i[15]}},baseband_data_i[15 -: DATA_WIDTH]};
+assign m_axis_tdata[16 +: 16] = {{(16-DATA_WIDTH){baseband_data_q[15]}},baseband_data_q[15 -: DATA_WIDTH]};
+
+endmodule

rfsoc_eval_demo/vitis_classic_autobuild/.gitignore

@@ -0,0 +1,35 @@
+# keep compiled libs
+!*.a
+
+# Buid folder
+build/
+
+# Xilinx tools generated files
+.metadata/
+.settings/
+.wsdata/
+.Xil/
+logs/
+Packages/
+*.log*
+
+# System generated files
+# -- macOS
+.DS_Store
+.AppleDouble
+.LSOverride
+._*
+
+# -- Windows
+Thumbs.db
+ehthumbs.db
+Desktop.ini
+
+# -- Linux
+*~
+
+# IDEs and editors' files
+*.idea
+*.vscode
+*.sublime-workspace
+*.sublime-project

rfsoc_eval_demo/vitis_classic_autobuild/Makefile

@@ -0,0 +1,8 @@
+include ../../scripts/generic_variables.mk
+
+PLATFORM := xilinx
+CONFIG_FILE := $(PROJECT)/config.json
+XILINX_VITIS_CLASSIC = y
+SCRIPT_DIR = ../../scripts
+
+include ../../scripts/generic.mk

rfsoc_eval_demo/vitis_classic_autobuild/autobuild.bat

@@ -0,0 +1,32 @@
+@echo off
+set "platform=xilinx"
+set "pltform_ver=2024.1"
+set "work_dir=%~dp0build"
+set "config=%~dp0config.json"
+set "tools_dir=%~dp0..\..\scripts\platform\%platform%"
+
+REM Set up enviroment
+call "%tools_dir%\setenv.bat" "%pltform_ver%"
+if "%ERRORLEVEL%" neq "0" (
+    echo Error: Failed to installize enviroment.
+    pause >nul
+    exit /b 1
+)
+
+REM Build project
+call "%tools_dir%\build.bat"  "%config%" "%work_dir%"
+if "%ERRORLEVEL%" neq "0" (
+    echo Error: Failed to build project.
+    pause >nul
+    exit /b 1
+)
+
+REM Lauch SDK
+call "%tools_dir%\launch.bat" "%pltform_ver%" "%work_dir%"
+if "%ERRORLEVEL%" neq "0" (
+    echo Error: Failed to launch SDK.
+    pause >nul
+    exit /b 1
+)
+
+exit /b 0

rfsoc_eval_demo/vitis_classic_autobuild/config.json

@@ -0,0 +1,28 @@
+{
+    "project_name": "rfsoc_eval_demo",
+    "version": "0.0.2",
+    "hw_design": "../system_top.xsa",
+    "hw_version": "rfsoc_eval_demo-HW-0.0.2",
+    "apps": {
+        "app_rfsoc_mts": {
+            "sources": ["source_mts/"],
+            "target_cpu": "psu_cortexa53_0",
+            "os": "standalone",
+            "language": "C",
+            "mem_layout" : {
+                "heap_size": "0x80000",
+                "stack_size": "0x4000"
+            }
+        },
+        "app_rfsoc_sweep": {
+            "sources": ["source_adc_dac_sweep/"],
+            "target_cpu": "psu_cortexa53_0",
+            "os": "standalone",
+            "language": "C",
+            "mem_layout" : {
+                "heap_size": "0x80000",
+                "stack_size": "0x4000"
+            }
+        }
+    }
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/adc/ad9694/ad9694.c

@@ -0,0 +1,128 @@
+/***************************************************************************//**
+ * @file ad9694.c
+ * @brief Implementation of AD9680 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdlib.h>
+#include <stdio.h>
+#include "ad9694.h"
+#include "../../../include/error.h"
+
+/***************************************************************************//**
+ * @brief ad9694_read
+ *******************************************************************************/
+int32_t ad9694_read(struct ad9694_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data)
+{
+	uint8_t tx_buf[2];
+	uint8_t rx_buf[1];
+	int32_t ret;
+
+	tx_buf[0] = 0x80 | (reg_addr >> 8);
+	tx_buf[1] = reg_addr & 0xFF;
+	
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+			tx_buf, rx_buf, 2, 1);
+
+	*reg_data = rx_buf[0];
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief ad9694_write
+ *******************************************************************************/
+int32_t ad9694_write(struct ad9694_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data)
+{
+	uint8_t buf[3];
+
+	int32_t ret;
+
+	buf[0] = reg_addr >> 8;
+	buf[1] = reg_addr & 0xFF;
+	buf[2] = reg_data;
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+				 buf, NULL, 3, 0);
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief ad9694_init
+ *******************************************************************************/
+int32_t ad9694_init(struct ad9694_dev **device,
+		     const struct ad9694_init_param *init_param)
+{
+	int ret = SUCCESS;
+	struct ad9694_dev *dev;
+
+	dev = (struct ad9694_dev *)malloc(sizeof(*dev));
+	if (!dev)
+		return FAILURE;
+
+	/* SPI */
+	ret = spi_init(&dev->spi_desc, init_param->spi_init);
+
+	*device = dev;
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief Free the resources allocated by ad9694_setup().
+ *
+ * @param dev - The device structure.
+ *
+ * @return SUCCESS in case of success, negative error code otherwise.
+*******************************************************************************/
+int32_t ad9694_remove(struct ad9694_dev *dev)
+{
+	int32_t ret;
+
+	ret = spi_remove(dev->spi_desc);
+
+	free(dev);
+
+	return ret;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/adc/ad9694/ad9694.h

@@ -0,0 +1,231 @@
+/***************************************************************************//**
+ * @file ad9694.h
+ * @brief Header file of AD9694 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+#ifndef AD9694_H_
+#define AD9694_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include "../../../include/delay.h"
+#include "../../../include/spi.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+#define AD9694_REG_GLOBAL_MAP_SPI_CONF_A						0x0000
+#define AD9694_REG_GLOBAL_MAP_SPI_CONF_B						0x0001
+#define AD9694_REG_CH_MAP_CHIP_CONF								0x0002
+#define AD9694_REG_PAIR_MAP_CHIP_TYPE							0x0003
+#define AD9694_REG_PAIR_MAP_CHIP_ID_LSB							0x0004
+#define AD9694_REG_PAIR_MAP_CHIP_GRADE							0x0006
+#define AD9694_REG_PAIR_MAP_DEV_INDEX							0x0008
+#define AD9694_REG_GLOBAL_MAP_PAIR_INDEX						0x0009
+#define AD9694_REG_PAIR_MAP_SCRATCH_PAD							0x000A
+#define AD9694_REG_PAIR_MAP_SPI_REVISION						0x000B
+#define AD9694_REG_PAIR_MAP_VENDOR_ID_LSB						0x000C
+#define AD9694_REG_PAIR_MAP_VENDOR_ID_MSB						0x000D
+#define AD9694_REG_CH_MAP_CHIP_PD_PIN							0x003F
+#define AD9694_REG_PAIR_MAP_CHIP_PIN_CTRL_1						0x0040
+#define AD9694_REG_PAIR_MAP_CLK_DIV_CTRL						0x0108
+#define AD9694_REG_CH_MAP_CLK_DIV_PHASE							0x0109
+#define AD9694_REG_PAIR_MAP_CLK_DIV_SYSREF_CTRL					0x010A
+#define AD9694_REG_PAIR_MAP_CLK_DELAY_CTRL						0x0110
+#define AD9694_REG_CH_MAP_CLK_SUPER_FINE_DELAY					0x0111
+#define AD9694_REG_CH_MAP_CLK_FINE_DELAY						0x0112
+#define AD9694_REG_CLK_DETN_CTRL								0x011A
+#define AD9694_REG_PAIR_MAP_CLK_STAT							0x011B
+#define AD9694_REG_CLK_DCS_CTRL_1								0x011C
+#define AD9694_REG_CLK_DCS_CTRL_2								0x011E
+#define AD9694_REG_CLK_DCS_CTRL_3								0x011F
+#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_1						0x0120
+#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_2						0x0121
+#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_4						0x0123
+#define AD9694_REG_PAIR_MAP_SYSREF_STAT_1						0x0128
+#define AD9694_REG_PAIR_MAP_SYSREF_STAT_2						0x0129
+#define AD9694_REG_PAIR_MAP_SYSREF_STAT_3						0x012A
+#define AD9694_REG_PAIR_MAP_CHIP_SYNC							0x01FF
+#define AD9694_REG_PAIR_MAP_CHIP_MODE							0x0200
+#define AD9694_REG_PAIR_MAP_CHIP_DEC_RATIO						0x0201
+#define AD9694_REG_CH_MAP_CUSTOM_OFFSET							0x0228
+#define AD9694_REG_CH_MAP_FD_CTRL								0x0245
+#define AD9694_REG_CH_MAP_FD_UT_LSB								0x0247
+#define AD9694_REG_CH_MAP_FD_UT_MSB								0x0248
+#define AD9694_REG_CH_MAP_FD_LT_LSB								0x0249
+#define AD9694_REG_CH_MAP_FD_LT_MSB								0x024A
+#define AD9694_REG_CH_MAP_FD_DWELL_TIME_LSB						0x024B
+#define AD9694_REG_CH_MAP_FD_DWELL_TIME_MSB						0x024C
+#define AD9694_REG_PAIR_MAP_SIG_MON_SYNC_CTRL					0x026F
+#define AD9694_REG_CH_MAP_SIG_MON_CTRL							0x0270
+#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_0						0x0271
+#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_1						0x0272
+#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_2						0x0273
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_CTRL						0x0274
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_0						0x0275
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_1						0x0276
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_2						0x0277
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_FRAME_CNT				0x0278
+#define AD9694_REG_CH_MAP_SIG_MON_SERIAL_FRAMER_CTRL			0x0279
+#define AD9694_REG_SPORT_OVER_JESD204B_INPUT_SEL				0x027A
+#define AD9694_REG_PAIR_MAP_DDC_SYNC_CTRL						0x0300
+#define AD9694_REG_PAIR_MAP_DDC_0_CTRL							0x0310
+#define AD9694_REG_PAIR_MAP_DDC_0_INPUT_SEL						0x0311
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_0					0x0314
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_1					0x0315
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_2					0x0316
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_3					0x0317
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_4					0x0318
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_5					0x031A
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_0				0x031D
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_1				0x031E
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_2				0x031F
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_3				0x0320
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_4				0x0321
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_5				0x0322
+#define AD9694_REG_PAIR_MAP_DDC_0_TEST_ENABLE					0x0327
+#define AD9694_REG_PAIR_MAP_DDC_1_CTRL							0x0330
+#define AD9694_REG_PAIR_MAP_DDC_1_INPUT_SEL						0x0331
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_0					0x0334
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_1					0x0335
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_2					0x0336
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_3					0x0337
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_4					0x0338
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_5					0x033A
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_0				0x033D
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_1				0x033E
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_2				0x033F
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_3				0x0340
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_4				0x0341
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_5				0x0342
+#define AD9694_REG_PAIR_MAP_DDC_1_TEST_ENABLE					0x0347
+#define AD9694_REG_CH_MAP_TEST_MODE_CTRL						0x0550
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_LSB					0x0551
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_MSB					0x0552
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_LSB					0x0553
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_MSB					0x0554
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_LSB					0x0555
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_MSB					0x0556
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_LSB					0x0557
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_MSB					0x0558
+#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_0					0x0559
+#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_1					0x055A
+#define AD9694_REG_PAIR_MAP_OUTPUT_SAMPLE_MODE					0x0561
+#define AD9694_REG_PAIR_MAP_OUTPUT_CH_SEL						0x0564
+#define AD9694_REG_JESD204B_MAP_PLL_CTRL						0x056E
+#define AD9694_REG_JESD204B_MAP_PLL_STAT						0x056F
+#define AD9694_REG_JESD204B_MAP_JTX_QUICK_CONF					0x0570
+#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_1					0x0571
+#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_2					0x0572
+#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_3					0x0573
+#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_4					0x0574
+#define AD9694_REG_JESD204B_MAP_JTX_LMFC_OFFSET					0x0578
+#define AD9694_REG_JESD204B_MAP_JTX_DID_CONF					0x0580
+#define AD9694_REG_JESD204B_MAP_JTX_BID_CONF					0x0581
+#define AD9694_REG_JESD204B_MAP_JTX_LID_0_CONF					0x0583
+#define AD9694_REG_JESD204B_MAP_JTX_LID_1_CONF					0x0585
+#define AD9694_REG_JESD204B_MAP_JTX_SCR_L_CONF					0x058B
+#define AD9694_REG_JESD204B_MAP_JTX_F_CONF						0x058C
+#define AD9694_REG_JESD204B_MAP_JTX_K_CONF						0x058D
+#define AD9694_REG_JESD204B_MAP_JTX_M_CONF						0x058E
+#define AD9694_REG_JESD204B_MAP_JTX_CS_N_CONF					0x058F
+#define AD9694_REG_JESD204B_MAP_JTX_SUBCLASS_CONF				0x0590
+#define AD9694_REG_JESD204B_MAP_JTX_S_CONF						0x0591
+#define AD9694_REG_JESD204B_MAP_JTX_HD_CF_CONF					0x0592
+#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_0_CONF				0x05A0
+#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_1_CONF				0x05A1
+#define AD9694_REG_SERDOUTX0_SERDOUTX1_LANE_PD					0x05B0
+#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_1				0x05B2
+#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_2				0x05B3
+#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_0					0x05C0
+#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_1					0x05C1
+#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_0					0x05C4
+#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_1					0x05C6
+#define AD9694_REG_LARGE_DITHER_CTRL							0x0922
+#define AD9694_REG_PLL_CAL										0x1222
+#define AD9694_REG_JESD204B_STARTUP_CIRCUIT_RST					0x1228
+#define AD9694_REG_PLL_LOSS_OF_LOCK_CTRL						0x1262
+#define AD9694_REG_DC_OFFSET_CAL_CTRL							0x0701
+#define AD9694_REG_DC_OFFSET_CAL_CTRL_2							0x073B
+#define AD9694_REG_PAIR_MAP_VREF_CTRL							0x18A6
+#define AD9694_REG_EXT_VCM_BUF_CTRL_1							0x18E0
+#define AD9694_REG_EXT_VCM_BUF_CTRL_2							0x18E1
+#define AD9694_REG_EXT_VCM_BUF_CTRL_3							0x18E2
+#define AD9694_REG_EXT_VCM_BUF_CTRL								0x18E3
+#define AD9694_REG_TEMP_DIODE_EXPORT							0x18E6
+#define AD9694_REG_CH_MAP_ANALOG_INPUT_CTRL						0x1908
+#define AD9694_REG_CH_MAP_INPUT_FULLSCALE_RANGE					0x1910
+#define AD9694_REG_CH_MAP_BUF_CTRL_1							0x1A4C
+#define AD9694_REG_CH_MAP_BUF_CTRL_2							0x1A4D
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+struct ad9694_dev {
+	/* SPI */
+	spi_desc	*spi_desc;
+};
+
+struct ad9694_init_param {
+	/* SPI */
+	spi_init_param	*spi_init;
+};
+
+struct ad9694_config {
+	uint16_t addr;
+	uint8_t value;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+int32_t ad9694_read(struct ad9694_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data);
+
+int32_t ad9694_write(struct ad9694_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data);
+
+int32_t ad9694_init(struct ad9694_dev **device,
+		     const struct ad9694_init_param *init_param);
+
+int32_t ad9694_remove(struct ad9694_dev *dev);
+
+#endif

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/api/gpio.c

@@ -0,0 +1,184 @@
+/***************************************************************************//**
+ *   @file   gpio.c
+ *   @brief  Implementation of the GPIO Interface
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2020(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include "../../include/gpio.h"
+#include "../../include/error.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Obtain the GPIO decriptor.
+ * @param desc - The GPIO descriptor.
+ * @param param - GPIO Initialization parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get(struct gpio_desc **desc,
+		 const struct gpio_init_param *param)
+{
+	if (!param)
+		return FAILURE;
+
+	if ((param->platform_ops->gpio_ops_get(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Get the value of an optional GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param param - GPIO Initialization parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_optional(struct gpio_desc **desc,
+			  const struct gpio_init_param *param)
+{
+	if (!param || (param->number == -1)) {
+		*desc = NULL;
+		return SUCCESS;
+	}
+
+	if ((param->platform_ops->gpio_ops_get_optional(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+/**
+ * @brief Free the resources allocated by gpio_get().
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_remove(struct gpio_desc *desc)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_remove(desc);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Enable the input direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_direction_input(struct gpio_desc *desc)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_direction_input(desc);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Enable the output direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_direction_output(struct gpio_desc *desc,
+			      uint8_t value)
+{
+	if (desc)
+		return desc->platform_ops->
+		       gpio_ops_direction_output(desc, value);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Get the direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param direction - The direction.
+ *                    Example: GPIO_OUT
+ *                             GPIO_IN
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_direction(struct gpio_desc *desc,
+			   uint8_t *direction)
+{
+	if (desc)
+		return desc->platform_ops->
+		       gpio_ops_get_direction(desc, direction);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Set the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_set_value(struct gpio_desc *desc,
+		       uint8_t value)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_set_value(desc, value);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Get the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_value(struct gpio_desc *desc,
+		       uint8_t *value)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_get_value(desc, value);
+	else
+		return SUCCESS;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/api/irq.c

@@ -0,0 +1,153 @@
+/***************************************************************************//**
+ *   @file   irq.c
+ *   @brief  Implementation of the IRQ Interface
+ *   @author Andrei Porumb ([email protected])
+********************************************************************************
+ * Copyright 2021(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include "../../include/irq.h"
+#include "../../include/error.h"
+
+/**
+ * @brief Initialize the IRQ interrupts.
+ * @param desc - The IRQ descriptor.
+ * @param param - The structure that contains the IRQ parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_ctrl_init(struct irq_ctrl_desc **desc,
+		      const struct irq_init_param *param)
+{
+	if (!param)
+		return FAILURE;
+
+	if ((param->platform_ops->init(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by irq_ctrl_init().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc)
+{
+	return desc->platform_ops->remove(desc);
+}
+
+/**
+ * @brief Register a callback to handle the irq events.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param callback_desc - Callback descriptor
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
+			      struct callback_desc *callback_desc)
+{
+	return desc->platform_ops->register_callback(desc, irq_id, callback_desc);
+}
+
+/**
+ * @brief Unregisters a generic IRQ handling function.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	return desc->platform_ops->unregister(desc, irq_id);
+}
+
+/**
+ * @brief Enable global interrupts.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_global_enable(struct irq_ctrl_desc *desc)
+{
+	return desc->platform_ops->global_enable(desc);
+}
+
+/**
+ * @brief Disable global interrupts.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_global_disable(struct irq_ctrl_desc *desc)
+{
+	return desc->platform_ops->global_disable(desc);
+}
+
+/**
+ * @brief Set interrupt trigger level.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param trig - New trigger level for the interrupt.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
+			      enum irq_trig_level trig)
+{
+	if(desc->platform_ops->trigger_level_set)
+		return desc->platform_ops->trigger_level_set(desc, irq_id, trig);
+	else
+		return ENOSYS;
+}
+
+/**
+ * @brief Enable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	return desc->platform_ops->enable(desc, irq_id);
+}
+
+/**
+ * @brief Disable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	return desc->platform_ops->disable(desc, irq_id);
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/api/spi.c

@@ -0,0 +1,144 @@
+/***************************************************************************//**
+ *   @file   spi.c
+ *   @brief  Implementation of the SPI Interface
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2020(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include "../../include/spi.h"
+#include "../../include/error.h"
+
+/**
+ * @brief Initialize the SPI communication peripheral.
+ * @param desc - The SPI descriptor.
+ * @param param - The structure that contains the SPI parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_init(struct spi_desc **desc,
+		 const struct spi_init_param *param)
+{
+	if (!param)
+		return FAILURE;
+
+	if ((param->platform_ops->init(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by spi_init().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_remove(struct spi_desc *desc)
+{
+	return desc->platform_ops->remove(desc);
+}
+
+/**
+ * @brief Write and read data to/from SPI.
+ * @param desc - The SPI descriptor.
+ * @param data - The buffer with the transmitted/received data.
+ * @param bytes_number - Number of bytes to write/read.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_write_and_read(struct spi_desc *desc,
+			   uint8_t *data,
+			   uint16_t bytes_number)
+{
+	return desc->platform_ops->write_and_read(desc, data, bytes_number);
+}
+
+/**
+ * @brief Write and read data to/from SPI in 3 wire mode.
+ * @param desc - The SPI descriptor.
+ * @param write_data - The buffer with the transmitted data.
+ * @param read_data - The buffer with the received data.
+ * @param write_bytes_number - Number of bytes to write.
+ * @param read_bytes_number - Number of bytes to read.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_write_and_read_3wire(struct spi_desc *desc,
+			   uint8_t *write_data,
+			   uint8_t *read_data,
+			   uint16_t write_bytes_number,
+			   uint16_t read_bytes_number)
+{
+	int ret;
+	if(desc->platform_ops->write_and_read_3wire != NULL){
+		return desc->platform_ops->write_and_read_3wire(desc, write_data, read_data,
+			write_bytes_number, read_bytes_number);
+	}
+	else{
+		return FAILURE;
+	}
+}
+
+
+/**
+ * @brief  Iterate over head list and send all spi messages
+ * @param desc - The SPI descriptor.
+ * @param msgs - Array of messages.
+ * @param len - Number of messages in the array.
+ * @return SUCCESS in case of success, negativ error code otherwise.
+ */
+int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len)
+{
+	int32_t  ret;
+	uint32_t i;
+
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (desc->platform_ops->transfer)
+		return desc->platform_ops->transfer(desc, msgs, len);
+
+	for (i = 0; i < len; i++) {
+		if (msgs[i].rx_buff != msgs[i].tx_buff || !msgs[i].tx_buff)
+			return -EINVAL;
+		ret = spi_write_and_read(desc, msgs[i].rx_buff,
+					 msgs[i].bytes_number);
+		if (IS_ERR_VALUE(ret))
+			return ret;
+	}
+
+	return SUCCESS;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c

@@ -0,0 +1,328 @@
+/***************************************************************************//**
+ *   @file   axi_dmac.c
+ *   @brief  Driver for the Analog Devices AXI-DMAC core.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include "../../../include/axi_io.h"
+#include "../../../include/error.h"
+#include "../axi_dmac/axi_dmac.h"
+
+/***************************************************************************//**
+ * @brief dma_isr
+*******************************************************************************/
+void axi_dmac_default_isr(void *instance)
+{
+	struct axi_dmac *dmac = (struct axi_dmac *)instance;
+	uint32_t remaining_size, burst_size;
+	uint32_t reg_val;
+
+	/* Get interrupt sources and clear interrupts. */
+	axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
+
+	if ((reg_val & AXI_DMAC_IRQ_SOT) && (dmac->big_transfer.size != 0)) {
+		remaining_size = dmac->big_transfer.size -
+				 dmac->big_transfer.size_done;
+		burst_size = (remaining_size <= dmac->transfer_max_size) ?
+			     remaining_size : dmac->transfer_max_size;
+
+		dmac->big_transfer.size_done += burst_size;
+		dmac->big_transfer.address += burst_size;
+		switch (dmac->direction) {
+		case DMA_DEV_TO_MEM:
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS,
+				       dmac->big_transfer.address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
+			break;
+		case DMA_MEM_TO_DEV:
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS,
+				       dmac->big_transfer.address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
+			break;
+		default:
+			return; // Other directions are not supported yet
+		}
+		/* The current transfer was started and a new one is queued. */
+		axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+			       burst_size);
+		axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+	}
+	if (reg_val & AXI_DMAC_IRQ_EOT) {
+		dmac->big_transfer.transfer_done = true;
+		dmac->big_transfer.address = 0;
+		dmac->big_transfer.size = 0;
+		dmac->big_transfer.size_done = 0;
+	}
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_read
+ *******************************************************************************/
+int32_t axi_dmac_read(struct axi_dmac *dmac,
+		      uint32_t reg_addr,
+		      uint32_t *reg_data)
+{
+	axi_io_read(dmac->base, reg_addr, reg_data);
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_write
+ *******************************************************************************/
+int32_t axi_dmac_write(struct axi_dmac *dmac,
+		       uint32_t reg_addr,
+		       uint32_t reg_data)
+{
+	axi_io_write(dmac->base, reg_addr, reg_data);
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_transfer_nonblock
+ *******************************************************************************/
+int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
+				      uint32_t address, uint32_t size)
+{
+	uint32_t reg_val;
+
+	if (size == 0)
+		return SUCCESS; /* nothing to do */
+
+	axi_dmac_read(dmac, AXI_DMAC_REG_CTRL, &reg_val);
+	if (!(reg_val & AXI_DMAC_CTRL_ENABLE)) {
+		axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
+		axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
+		axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
+	}
+
+	axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, &reg_val);
+	if (!(reg_val & 1)) {
+		switch (dmac->direction) {
+		case DMA_DEV_TO_MEM:
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
+			break;
+		case DMA_MEM_TO_DEV:
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
+			break;
+		default:
+			return FAILURE; // Other directions are not supported yet
+		}
+		if ((size - 1) > dmac->transfer_max_size) {
+			dmac->big_transfer.address = address;
+			dmac->big_transfer.size = size - 1;
+			dmac->big_transfer.size_done = dmac->transfer_max_size;
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+				       dmac->transfer_max_size);
+			axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+		} else {
+			axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+				       size - 1);
+			axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+		}
+	} else {
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_is_transfer_ready
+ *******************************************************************************/
+int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy)
+{
+	*rdy = dmac->big_transfer.transfer_done;
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_transfer
+ *******************************************************************************/
+int32_t axi_dmac_transfer(struct axi_dmac *dmac,
+			  uint32_t address, uint32_t size)
+{
+	uint32_t transfer_id;
+	uint32_t reg_val;
+	uint32_t timeout = 0;
+
+	if (size == 0)
+		return SUCCESS; /* nothing to do */
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
+	axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
+
+	axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID, &transfer_id);
+	axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
+
+	switch (dmac->direction) {
+	case DMA_DEV_TO_MEM:
+		axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
+		axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
+		break;
+	case DMA_MEM_TO_DEV:
+		axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
+		axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
+		break;
+	default:
+		return FAILURE; // Other directions are not supported yet
+	}
+
+	if ((size - 1) > dmac->transfer_max_size) {
+		dmac->big_transfer.address = address;
+		dmac->big_transfer.size = size - 1;
+		dmac->big_transfer.size_done = dmac->transfer_max_size;
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+			       dmac->transfer_max_size);
+		axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+
+		while(!dmac->big_transfer.transfer_done) {
+			timeout++;
+			if (timeout == UINT32_MAX)
+				return FAILURE;
+		}
+
+		dmac->big_transfer.address = 0;
+		dmac->big_transfer.size = 0;
+		dmac->big_transfer.size_done = 0;
+
+		return SUCCESS;
+	}
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, size - 1);
+	axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+
+	if (dmac->flags & DMA_CYCLIC)
+		return SUCCESS;
+
+	/* Wait until the new transfer is queued. */
+	do {
+		axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, &reg_val);
+	} while(reg_val == 1);
+
+	/* Wait until the current transfer is completed. */
+	do {
+		axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
+		if (reg_val == (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
+			break;
+	} while(!dmac->big_transfer.transfer_done);
+	if (reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
+		axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
+
+	/* Wait until the transfer with the ID transfer_id is completed. */
+	do {
+		axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE, &reg_val);
+	} while((reg_val & (1u << transfer_id)) != (1u << transfer_id));
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_init
+ *******************************************************************************/
+int32_t axi_dmac_init(struct axi_dmac **dmac_core,
+		      const struct axi_dmac_init *init)
+{
+	struct axi_dmac *dmac;
+
+	dmac = (struct axi_dmac *)malloc(sizeof(*dmac));
+	if (!dmac)
+		return FAILURE;
+
+	dmac->name = init->name;
+	dmac->base = init->base;
+	dmac->direction = init->direction;
+	dmac->flags = init->flags;
+	dmac->transfer_max_size = -1;
+	dmac->big_transfer.address = 0;
+	dmac->big_transfer.size = 0;
+	dmac->big_transfer.size_done = 0;
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, dmac->transfer_max_size);
+	axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH, &dmac->transfer_max_size);
+
+	*dmac_core = dmac;
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_remove
+ *******************************************************************************/
+int32_t axi_dmac_remove(struct axi_dmac *dmac)
+{
+	if(!dmac)
+		return FAILURE;
+
+	free(dmac);
+
+	return SUCCESS;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h

@@ -0,0 +1,124 @@
+/***************************************************************************//**
+ *   @file   axi_dmac.h
+ *   @brief  Driver for the Analog Devices AXI-DMAC core.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef AXI_DMAC_H_
+#define AXI_DMAC_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include "../../../include/util.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+#define AXI_DMAC_REG_IRQ_MASK		0x80
+#define AXI_DMAC_REG_IRQ_PENDING	0x84
+#define AXI_DMAC_IRQ_SOT			BIT(0)
+#define AXI_DMAC_IRQ_EOT			BIT(1)
+
+#define AXI_DMAC_REG_CTRL			0x400
+#define AXI_DMAC_CTRL_ENABLE		BIT(0)
+#define AXI_DMAC_CTRL_PAUSE			BIT(1)
+
+#define AXI_DMAC_REG_TRANSFER_ID	0x404
+#define AXI_DMAC_REG_START_TRANSFER	0x408
+#define AXI_DMAC_REG_FLAGS			0x40c
+#define AXI_DMAC_REG_DEST_ADDRESS	0x410
+#define AXI_DMAC_REG_SRC_ADDRESS	0x414
+#define AXI_DMAC_REG_X_LENGTH		0x418
+#define AXI_DMAC_REG_Y_LENGTH		0x41c
+#define AXI_DMAC_REG_DEST_STRIDE	0x420
+#define AXI_DMAC_REG_SRC_STRIDE		0x424
+#define AXI_DMAC_REG_TRANSFER_DONE	0x428
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+enum dma_direction {
+	DMA_DEV_TO_MEM,
+	DMA_MEM_TO_DEV
+};
+
+enum dma_flags {
+	DMA_CYCLIC = 1,
+	DMA_LAST = 2
+};
+
+struct axi_dma_transfer {
+	uint32_t size;
+	uint32_t address;
+	uint32_t size_done;
+	volatile bool transfer_done;
+};
+
+struct axi_dmac {
+	const char *name;
+	uint32_t base;
+	enum dma_direction direction;
+	uint32_t flags;
+	uint32_t transfer_max_size;
+	volatile struct axi_dma_transfer big_transfer;
+};
+
+struct axi_dmac_init {
+	const char *name;
+	uint32_t base;
+	enum dma_direction direction;
+	uint32_t flags;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+void axi_dmac_default_isr(void *instance);
+int32_t axi_dmac_read(struct axi_dmac *dmac, uint32_t reg_addr,
+		      uint32_t *reg_data);
+int32_t axi_dmac_write(struct axi_dmac *dmac, uint32_t reg_addr,
+		       uint32_t reg_data);
+int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
+				      uint32_t address, uint32_t size);
+int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy);
+int32_t axi_dmac_transfer(struct axi_dmac *dmac,
+			  uint32_t address, uint32_t size);
+int32_t axi_dmac_init(struct axi_dmac **adc_core,
+		      const struct axi_dmac_init *init);
+int32_t axi_dmac_remove(struct axi_dmac *dmac);
+
+#endif

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/axi_core/spi_engine/spi_engine.c

@@ -0,0 +1,978 @@
+/*******************************************************************************
+ *   @file   spi_engine.c
+ *   @brief  Core implementation of the SPI Engine Driver.
+ *   @author Sergiu Cuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+/* In debug mode the printf function used in displaying the messages is causing
+significant delays */
+//#define DEBUG_LEVEL 2
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sleep.h>
+#include <inttypes.h>
+
+#include "spi_engine.h"
+#include "../axi_dmac/axi_dmac.h"
+#include "../../../include/axi_io.h"
+#include "../../../include/error.h"
+
+/**
+ * @brief Spi engine platform specific SPI platform ops structure
+ */
+const struct spi_platform_ops spi_eng_platform_ops = {
+	.init = &spi_engine_init,
+	.write_and_read = &spi_engine_spi_write_and_read,
+	.write_and_read_3wire = &spi_engine_spi_write_and_read_3wire,
+	.remove = &spi_engine_remove
+};
+
+/******************************************************************************/
+/***************************** Static variables *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Static variable used to sync transfers
+ *
+ */
+static uint8_t _sync_id = 0x01;
+
+/******************************************************************************/
+/************************** Functions Implementation **************************/
+/******************************************************************************/
+
+/**
+ * @brief Write SPI Engine's axi registers
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param reg_addr The address of the SPI Engine's axi register where the data
+ * 	will be written
+ * @param reg_data Data that will be written
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_write(struct spi_engine_desc *desc,
+			 uint32_t reg_addr,
+			 uint32_t reg_data)
+{
+	axi_io_write(desc->spi_engine_baseaddr, reg_addr, reg_data);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Read SPI Engine's axi registers
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param reg_addr The address of the SPI Engine's axi register from where the
+ * 	data where the data will be read
+ * @param reg_data Pointer where the read that will be stored
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_read(struct spi_engine_desc *desc,
+			uint32_t reg_addr,
+			uint32_t *reg_data)
+{
+	axi_io_read(desc->spi_engine_baseaddr, reg_addr, reg_data);
+	return SUCCESS;
+}
+
+/**
+ * @brief Set width of the transferred word over SPI
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param data_width The desired data width
+ * 	The supported values are:
+ * 		- 8
+ * 		- 16
+ * 		- 24
+ * 		- 32
+ */
+int32_t spi_engine_set_transfer_width(struct spi_desc *desc,
+				      uint8_t data_width)
+{
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	if (data_width > desc_extra->max_data_width)
+		desc_extra->data_width = desc_extra->max_data_width;
+	else
+		desc_extra->data_width = data_width;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Set SPI engine clock frequency
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param speed_hz SPI engine transfer speed
+ */
+void spi_engine_set_speed(struct spi_desc *desc,
+			  uint32_t speed_hz)
+{
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	desc_extra->clk_div =  desc_extra->ref_clk_hz /
+			       (2 * speed_hz) - 1;
+}
+
+/**
+ * @brief Set the number of words transferred in a single transaction
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param bytes_number The number of bytes to be converted
+ * @return uint8_t A number of words in which bytes_number can be grouped
+ */
+static uint8_t spi_get_words_number(struct spi_engine_desc *desc,
+				    uint8_t bytes_number)
+{
+	uint8_t xfer_word_len;
+	uint8_t words_number;
+
+	xfer_word_len = desc->data_width / 8;
+	words_number = bytes_number / xfer_word_len;
+
+	if ((bytes_number % xfer_word_len) != 0)
+		words_number++;
+
+	return words_number;
+}
+
+/**
+ * @brief Get the word length in bytes
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @return uint8_t Number of bytes that fit in one word
+ */
+static uint8_t spi_get_word_length(struct spi_engine_desc *desc)
+{
+	uint8_t word_length;
+
+	word_length = desc->data_width / 8;
+
+	return word_length;
+}
+
+/**
+ * @brief Compute the prescaler used to set the sleep period.
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param sleep_time_ns The amount of time where the transfer hangs
+ * @param sleep_div Clock prescaler
+ * @return int32_t This function allways returns SUCCESS
+ */
+static int32_t spi_get_sleep_div(struct spi_desc *desc,
+				 uint32_t sleep_time_ns,
+				 uint32_t *sleep_div)
+{
+	struct spi_engine_desc	*eng_desc;
+
+	eng_desc = desc->extra;
+
+	/*
+	 * Engine Wiki:
+	 *
+	 * The frequency of the SCLK signal is derived from the
+	 * module clock frequency using the following formula:
+	 * f_sclk = f_clk / ((div + 1) * 2)
+	 */
+
+	*sleep_div = (desc->max_speed_hz / 1000000 * sleep_time_ns / 1000) /
+		     ((eng_desc->clk_div + 1) * 2) - 1;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Create a new commands queue used in a spi transfer
+ *
+ * @param fifo Command buffer, usually used in fifo mode
+ * @param cmd Command with witch the buffer will be initiated
+ * @return int32_t Failure if the memory allocation failed
+ */
+static int32_t spi_engine_queue_new_cmd(struct spi_engine_cmd_queue **fifo,
+					uint32_t cmd)
+{
+	struct spi_engine_cmd_queue *local_fifo;
+
+	local_fifo = (spi_engine_cmd_queue*)malloc(sizeof(*local_fifo));
+
+	if(!local_fifo)
+		return FAILURE;
+
+	local_fifo->cmd = cmd;
+	local_fifo->next = NULL;
+	*fifo = local_fifo;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Add a command at the end of an existing queue
+ *
+ * @param fifo Command buffer, usually used in fifo mode
+ * @param cmd Command to be added
+ */
+static void spi_engine_queue_add_cmd(struct spi_engine_cmd_queue **fifo,
+				     uint32_t cmd)
+{
+	struct spi_engine_cmd_queue *to_add = NULL;
+	struct spi_engine_cmd_queue *local_fifo;
+
+	local_fifo = *fifo;
+	while (local_fifo->next != NULL) {
+		// Get the last element
+		local_fifo = local_fifo->next;
+	}
+
+	// Create a new element
+	spi_engine_queue_new_cmd(&to_add, cmd);
+	// Add as the next element
+	local_fifo->next = to_add;
+}
+
+/**
+ * @brief Add a command at the beginning of an existing queue
+ *
+ * @param fifo Command buffer, usually used in fifo mode
+ * @param cmd Command to be added
+ */
+static void spi_engine_queue_append_cmd(struct spi_engine_cmd_queue **fifo,
+					uint32_t cmd)
+{
+	struct spi_engine_cmd_queue *to_add = NULL;
+
+	// Create a new element
+	spi_engine_queue_new_cmd(&to_add, cmd);
+	// Interchange the addresses
+	to_add->next = *fifo;
+	*fifo = to_add;
+}
+
+
+/**
+ * @brief Get the command from the beginning of the queue
+ *
+ * @param fifo Command buffer, usually used in fifo mode
+ * @param cmd Value of the command that was extracted
+ * @return int32_t Return FAILURE if the queue is empty
+ */
+static int32_t spi_engine_queue_get_cmd(struct spi_engine_cmd_queue **fifo,
+					uint32_t *cmd)
+{
+	struct spi_engine_cmd_queue *local_fifo;
+
+	if (!*fifo)
+		return FAILURE;
+
+	local_fifo = *fifo;
+	*cmd = local_fifo->cmd;
+	if ((*fifo)->next) {
+		*fifo = local_fifo->next;
+		free(local_fifo);
+	} else {
+		free(*fifo);
+		*fifo = NULL;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the memory allocated by a queue
+ *
+ * @param fifo The queue that needs it's memory freed
+ * @return int32_t This function allways return SUCCESS
+ */
+static int32_t spi_engine_queue_free(struct spi_engine_cmd_queue **fifo)
+{
+	if(*fifo && (*fifo)->next)
+		spi_engine_queue_free(&(*fifo)->next);
+	if((*fifo) != NULL) {
+		free(*fifo);
+		*fifo = NULL;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Write the SPI engine's command fifo
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param cmd The command that will be written
+ * @return int32_t Returns FAILURE if the the axi transfer failed
+ */
+static int32_t spi_engine_write_cmd_reg(struct spi_engine_desc *desc,
+					uint32_t cmd)
+{
+	int32_t ret;
+
+	/* Check if offload is enabled */
+	if(desc->offload_config & (OFFLOAD_TX_EN | OFFLOAD_RX_EN)) {
+		ret = spi_engine_write(desc,
+				       SPI_ENGINE_REG_OFFLOAD_CMD_MEM(0),
+				       cmd);
+
+	} else {
+		ret = spi_engine_write(desc,
+				       SPI_ENGINE_REG_CMD_FIFO,
+				       cmd);
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Write a transfer command to the SPI engine's command fifo
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param read_write Read/Write operation flag
+ * @param bytes_number Number of bytes to transfer
+ * @return int32_t This function allways returns SUCCESS
+ */
+static int32_t spi_engine_transfer(struct spi_engine_desc *desc,
+				   uint8_t read_write,
+				   uint8_t bytes_number)
+{
+	uint8_t words_number;
+
+	words_number = spi_get_words_number(desc, bytes_number);
+
+	desc->offload_tx_len += words_number;
+
+	/*
+	 * Engine Wiki:
+	 *
+	 * https://wiki.analog.com/resources/fpga/peripherals/spi_engine
+	 *
+	 * The words number is zero based
+	 */
+
+	spi_engine_write_cmd_reg(desc,
+				 SPI_ENGINE_CMD_TRANSFER(read_write,
+						 words_number  - 1));
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Change the state of the chip select port
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param assert Chip select state.
+ * 		 The supported values are :
+ * 			-true (HIGH)
+ * 			-false (LOW)
+ */
+static void spi_engine_set_cs(struct spi_desc *desc,
+			      bool assert)
+{
+	uint8_t			mask;
+	struct spi_engine_desc	*eng_desc;
+
+	eng_desc = desc->extra;
+
+	mask = 0xFF;
+	/* Switch the state only of the selected chip select */
+	if (!assert)
+		mask ^= BIT(desc->chip_select);
+
+	spi_engine_write_cmd_reg(eng_desc,
+				 SPI_ENGINE_CMD_ASSERT(eng_desc->cs_delay,
+						 mask));
+}
+
+/**
+ * @brief Add a delay between the engine commands
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param sleep_time_ns Number of nanoseconds to sleep between commands
+ */
+static void spi_gen_sleep_ns(struct spi_desc *desc,
+			     uint32_t sleep_time_ns)
+{
+	uint32_t 		sleep_div;
+	struct spi_engine_desc	*eng_desc;
+
+	eng_desc = desc->extra;
+
+	spi_get_sleep_div(desc, sleep_time_ns, &sleep_div);
+
+	spi_engine_write_cmd_reg(eng_desc, SPI_ENGINE_CMD_SLEEP(sleep_div));
+}
+
+/**
+ * @brief Spi engine command interpreter
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param cmd Command to send to the engine
+ * @return int32_t - SUCCESS if the command is transferred
+ *		   - FAILURE if the command format is invalid
+ */
+static int32_t spi_engine_write_cmd(struct spi_desc *desc,
+				    uint32_t cmd)
+{
+	uint8_t				engine_command;
+	uint8_t				parameter;
+	uint8_t				modifier;
+	struct spi_engine_desc		*desc_extra;
+
+	desc_extra = desc->extra;
+
+	engine_command = (cmd >> 12) & 0x0F;
+	modifier = (cmd >> 8) & 0x0F;
+	parameter = cmd & 0xFF;
+
+	switch(engine_command) {
+	case SPI_ENGINE_INST_TRANSFER:
+		spi_engine_transfer(desc_extra, modifier, parameter);
+		break;
+
+	case SPI_ENGINE_INST_ASSERT:
+		if(parameter == 0xFF) {
+			/* Set the CS HIGH */
+			spi_engine_set_cs(desc, true);
+		} else if(parameter == 0x00) {
+			/* Set the CS LOW */
+			spi_engine_set_cs(desc, false);
+		}
+		break;
+
+	/* The SYNC and SLEEP commands got the same value but different
+	modifier */
+	case SPI_ENGINE_INST_SYNC_SLEEP:
+		/* SYNC instruction */
+		if(modifier == 0x00) {
+			spi_engine_write_cmd_reg(desc_extra, cmd);
+		} else if(modifier == 0x01) {
+			spi_gen_sleep_ns(desc, parameter);
+		}
+		break;
+	case SPI_ENGINE_INST_CONFIG:
+		spi_engine_write_cmd_reg(desc_extra, cmd);
+
+		break;
+
+	default:
+
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Prepare the command queue before sending it to the engine
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param msg Structure used to store the transfer messages
+ * @return int32_t This function allways returns SUCCESS
+ */
+static int32_t spi_engine_compile_message(struct spi_desc *desc,
+		struct spi_engine_msg *msg)
+{
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	/* Configure the prescaler */
+	spi_engine_queue_append_cmd(&msg->cmds,
+				    SPI_ENGINE_CMD_CONFIG(
+					    SPI_ENGINE_CMD_REG_CLK_DIV,
+					    desc_extra->clk_div));
+
+	/* Set the data transfer length */
+	spi_engine_queue_append_cmd(&msg->cmds,
+				    SPI_ENGINE_CMD_CONFIG(
+					    SPI_ENGINE_CMD_DATA_TRANSFER_LEN,
+					    desc_extra->data_width));
+	/*
+	 * Configure the spi mode :
+	 *	- 3 wire
+	 *	- CPOL
+	 *	- CPHA
+	 */
+	spi_engine_queue_append_cmd(&msg->cmds,
+				    SPI_ENGINE_CMD_CONFIG(
+					    SPI_ENGINE_CMD_REG_CONFIG,
+					    desc->mode));
+
+	/* Add a sync command to signal that the transfer has finished */
+	spi_engine_queue_add_cmd(&msg->cmds, SPI_ENGINE_CMD_SYNC(_sync_id));
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Initiate a spi transfer (Blocking)
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param msg Structure used to store the transfer messages
+ * @return int32_t - SUCCESS if the transfer finished
+ *		   - FAILURE if the memory allocation failed
+ */
+static int32_t spi_engine_transfer_message(struct spi_desc *desc,
+		struct spi_engine_msg *msg)
+{
+	uint32_t		i;
+	uint32_t		data;
+	uint32_t		sync_id;
+	bool 			offload_en;
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	spi_engine_compile_message(desc, msg);
+
+	offload_en = (desc_extra->offload_config & OFFLOAD_TX_EN) |
+		     (desc_extra->offload_config & OFFLOAD_RX_EN);
+
+	/* Write the command fifo buffer */
+	while(msg->cmds != NULL) {
+		spi_engine_queue_get_cmd(&msg->cmds, &data);
+		spi_engine_write_cmd(desc, data);
+	}
+
+	/* Write a number of tx_length WORDS on the SDO line */
+	if(offload_en) {
+		for(i = 0; i < desc_extra->offload_tx_len; i++)
+			spi_engine_write(desc_extra,
+					 SPI_ENGINE_REG_OFFLOAD_SDO_MEM(0),
+					 msg->tx_buf[i]);
+
+	} else {
+		if(msg->tx_buf != NULL){
+			for(i = 0; i < msg->tx_length; i++)
+			spi_engine_write(desc_extra,
+					 SPI_ENGINE_REG_SDO_DATA_FIFO,
+					 msg->tx_buf[i]);
+		}
+		do {
+			spi_engine_read(desc_extra,
+					SPI_ENGINE_REG_SYNC_ID,
+					&sync_id);
+		}
+		/* Wait for the end sync signal */
+		while(sync_id != _sync_id);
+		_sync_id++;
+
+		/* Read a number of rx_length WORDS from the SDI line and store
+		them */
+		for(i = 0; i < msg->rx_length; i++) {
+			spi_engine_read(desc_extra,
+					SPI_ENGINE_REG_SDI_DATA_FIFO,
+					&data);
+			/* Store the rx data if rx buffer valid, flush sdi_fifo if
+			rx buffer is invalid.*/
+			if(msg->rx_buf != NULL){
+				msg->rx_buf[i] = data;
+			}
+		}
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Initialize the spi engine
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param param Structure containing the spi init parameters
+ * @return int32_t - SUCCESS if the transfer finished
+ *		   - FAILURE if the memory allocation failed
+ */
+int32_t spi_engine_init(struct spi_desc **desc,
+			const struct spi_init_param *param)
+{
+	uint32_t			data_width = 0;
+	uint32_t			spi_engine_version = 0;
+	struct spi_engine_desc		*eng_desc;
+	struct spi_engine_init_param	*spi_engine_init;
+
+	if (!param) {
+		return FAILURE;
+	}
+
+	*desc = malloc(sizeof(**desc));
+	if(! *desc) {
+		free(*desc);
+		return FAILURE;
+	}
+
+	eng_desc = (struct spi_engine_desc*)malloc(sizeof(*eng_desc));
+
+	if (!eng_desc)
+		return FAILURE;
+
+	spi_engine_init = param->extra;
+
+	(*desc)->max_speed_hz = param->max_speed_hz;
+	(*desc)->chip_select = param->chip_select;
+	(*desc)->mode = param->mode;
+	(*desc)->extra = eng_desc;
+
+	eng_desc->offload_config = OFFLOAD_DISABLED;
+	eng_desc->spi_engine_baseaddr = spi_engine_init->spi_engine_baseaddr;
+	eng_desc->type = spi_engine_init->type;
+	eng_desc->cs_delay = spi_engine_init->cs_delay;
+	eng_desc->ref_clk_hz = spi_engine_init->ref_clk_hz;
+	eng_desc->clk_div =  eng_desc->ref_clk_hz /
+			     (2 * param->max_speed_hz) - 1;
+
+	/* Perform a reset */
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x01);
+	usleep(1000);
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x00);
+
+	/* Get current data width */
+	spi_engine_read(eng_desc, SPI_ENGINE_REG_DATA_WIDTH, &data_width);
+	eng_desc->max_data_width = data_width;
+
+	spi_engine_set_transfer_width(*desc, spi_engine_init->data_width);
+
+	/* Get spi engine version */
+	spi_engine_read(eng_desc, SPI_ENGINE_REG_VERSION, &spi_engine_version);
+
+	printf("Spi engine v%"PRIu32".%"PRIu32".%"PRIu32" successfully initialized.\n",
+	       (spi_engine_version >> 16),
+	       ((spi_engine_version >> 8) & 0xFF),
+	       (spi_engine_version & 0xFF));
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Write and read on the spi interface in 4-wire mode (full-duplex)
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param data Pointer to data buffer
+ * @param bytes_number Number of bytes to transfer
+ * @return int32_t - SUCCESS if the transfer finished
+ *		   - FAILURE if the memory allocation or transfer failed
+ */
+int32_t spi_engine_spi_write_and_read(struct spi_desc *desc,
+				  uint8_t *data,
+				  uint16_t bytes_number)
+{
+	uint8_t 		word_len;
+	uint8_t 		words_number;
+	int32_t 		ret;
+	struct spi_engine_msg	msg;
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	/* If we want to access SPI interface and SPI engine offload module was
+	 * activated, we need to disable it
+	 * This is set in spi_engine_offload_init() */
+	desc_extra->offload_config = OFFLOAD_DISABLED;
+	/* This is set in spi_engine_offload_transfer() */
+	spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0);
+
+	words_number = spi_get_words_number(desc_extra, bytes_number);
+
+	msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds));
+	if (!msg.cmds)
+		return FAILURE;
+
+	msg.tx_buf =(uint32_t*)calloc(words_number, sizeof(msg.tx_buf[0]));
+	msg.rx_buf =(uint32_t*)calloc(words_number, sizeof(msg.rx_buf[0]));
+	msg.tx_length = words_number;
+	msg.rx_length = words_number;
+
+	/* Get the length of transferred word */
+	word_len = spi_get_word_length(desc_extra);
+
+	/* Make sure the CS is HIGH before starting a transaction */
+	msg.cmds->next = NULL;
+	msg.cmds->cmd = CS_HIGH;
+	// Assert select.
+	spi_engine_queue_add_cmd(&msg.cmds, CS_LOW);
+	// add read/write command
+	spi_engine_queue_add_cmd(&msg.cmds, WRITE_READ(bytes_number));
+	// Disable select.
+	spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH);
+
+	/* Pack the bytes into engine WORDS */
+	for (int i = 0; i < bytes_number; i++)
+		msg.tx_buf[i / word_len] |= data[i] << (desc_extra->data_width-
+							(i % word_len + 1) * 8);
+
+	ret = spi_engine_transfer_message(desc, &msg);
+
+	for (int i = 0; i < bytes_number; i++)
+	data[i] = msg.rx_buf[(i) / word_len] >>
+		  (desc_extra->data_width -
+		   ((i) % word_len + 1) * 8);
+	
+	spi_engine_queue_free(&msg.cmds);
+	free(msg.tx_buf);
+	free(msg.rx_buf);
+
+	return ret;
+}
+
+/**
+ * @brief Write and read on the spi interface in 3-wire mode (half-duplex)
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param data Pointer to data buffer
+ * @param bytes_number Number of bytes to transfer
+ * @return int32_t - SUCCESS if the transfer finished
+ *		   - FAILURE if the memory allocation or transfer failed
+ */
+int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc,
+		   uint8_t *write_data,
+		   uint8_t *read_data,
+		   uint16_t write_bytes_number,
+		   uint16_t read_bytes_number)
+{
+	uint8_t 		word_len;
+	uint8_t 		wr_words_number;
+	uint8_t 		rd_words_number;
+	int32_t 		ret;
+	struct spi_engine_msg	msg;
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	/* If we want to access SPI interface and SPI engine offload module was
+	 * activated, we need to disable it
+	 * This is set in spi_engine_offload_init() */
+	desc_extra->offload_config = OFFLOAD_DISABLED;
+	/* This is set in spi_engine_offload_transfer() */
+	spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0);
+
+	wr_words_number = spi_get_words_number(desc_extra, write_bytes_number);
+	rd_words_number = spi_get_words_number(desc_extra, read_bytes_number);
+
+	msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds));
+	if (!msg.cmds)
+		return FAILURE;
+
+	msg.tx_buf =(wr_words_number>0)?(uint32_t*)calloc(wr_words_number, sizeof(msg.tx_buf[0])):NULL;
+	msg.rx_buf =(rd_words_number>0)?(uint32_t*)calloc(rd_words_number, sizeof(msg.rx_buf[0])):NULL;
+	msg.tx_length = wr_words_number;
+	msg.rx_length = rd_words_number;
+
+	/* Get the length of transferred word */
+	word_len = spi_get_word_length(desc_extra);
+
+	/* Make sure the CS is HIGH before starting a transaction */
+	msg.cmds->next = NULL;
+	msg.cmds->cmd = CS_HIGH;
+
+	// Assert select.
+	spi_engine_queue_add_cmd(&msg.cmds, CS_LOW);
+
+	// add read/write command
+	if(write_bytes_number > 0)
+	spi_engine_queue_add_cmd(&msg.cmds, WRITE(write_bytes_number));
+	if(read_bytes_number > 0)
+	spi_engine_queue_add_cmd(&msg.cmds, READ(read_bytes_number));
+
+	// Disable select.
+	spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH);
+
+	/* Pack the bytes into engine WORDS */
+	for (int i = 0; i < write_bytes_number; i++)
+		msg.tx_buf[i / word_len] |= write_data[i] << (desc_extra->data_width-
+							(i % word_len + 1) * 8);
+
+	ret = spi_engine_transfer_message(desc, &msg);
+
+	for (int i = 0; i < read_bytes_number; i++)
+		read_data[i] = msg.rx_buf[(i) / word_len] >>
+		  (desc_extra->data_width -
+		   ((i) % word_len + 1) * 8);
+
+	spi_engine_queue_free(&msg.cmds);
+	free(msg.tx_buf);
+	free(msg.rx_buf);
+
+	return ret;
+}
+
+/**
+ * @brief Initialize the SPI engine's offload module
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param param Structure containing the offload init parameters
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_offload_init(struct spi_desc *desc,
+				const struct spi_engine_offload_init_param *param)
+{
+	struct spi_engine_desc	*eng_desc;
+	struct axi_dmac_init	dmac_init;
+	uint32_t dma_flags;
+
+	eng_desc = desc->extra;
+
+	eng_desc->offload_config = param->offload_config;
+
+	if(!(param->dma_flags))
+		dma_flags = DMA_CYCLIC;
+	else
+		dma_flags = *(param->dma_flags);
+
+	if(param->offload_config & OFFLOAD_TX_EN) {
+		dmac_init.name = "DAC DMAC";
+		dmac_init.base = param->tx_dma_baseaddr;
+		dmac_init.direction = DMA_MEM_TO_DEV;
+		dmac_init.flags = dma_flags;
+		axi_dmac_init(&eng_desc->offload_tx_dma, &dmac_init);
+		if(!eng_desc->offload_tx_dma)
+			return FAILURE;
+	}
+	if(param->offload_config & OFFLOAD_RX_EN) {
+		dmac_init.name = "ADC DMAC";
+		dmac_init.base = param->rx_dma_baseaddr;
+		dmac_init.direction = DMA_DEV_TO_MEM;
+		dmac_init.flags = dma_flags;
+		axi_dmac_init(&eng_desc->offload_rx_dma, &dmac_init);
+		if(!eng_desc->offload_rx_dma)
+			return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Initiate a SPI transfer in offload mode
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param msg Offload message that get's to be transferred
+ * @param no_samples Number of time the messages will be transferred
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_offload_transfer(struct spi_desc *desc,
+				    struct spi_engine_offload_message msg,
+				    uint32_t no_samples)
+{
+	struct spi_engine_msg	transfer;
+	struct spi_engine_desc	*eng_desc;
+	uint32_t 		i;
+	uint8_t 		word_length;
+
+	eng_desc = desc->extra;
+
+	/* Check if offload is disabled */
+	if(!((eng_desc->offload_config & OFFLOAD_TX_EN) |
+	     (eng_desc->offload_config & OFFLOAD_RX_EN)))
+		return FAILURE;
+
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 1);
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 0);
+
+	eng_desc->offload_tx_len = 0;
+	eng_desc->offload_rx_len = 0;
+
+	transfer.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*transfer.cmds));
+
+	if (!transfer.cmds)
+		return FAILURE;
+
+	transfer.tx_buf = msg.commands_data;
+
+	/* Load the commands into the message */
+	transfer.cmds->next = NULL;
+	transfer.cmds->cmd = msg.commands[0];
+	i = 1;
+	while(i < msg.no_commands) {
+		spi_engine_queue_add_cmd(&transfer.cmds, msg.commands[i++]);
+
+	}
+
+	spi_engine_transfer_message(desc, &transfer);
+
+	/* Start transfer */
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0x0001);
+
+	word_length = spi_get_word_length(eng_desc);
+	if(eng_desc->offload_config & OFFLOAD_TX_EN) {
+		axi_dmac_transfer(eng_desc->offload_tx_dma,
+				  msg.tx_addr,
+				  word_length * eng_desc->offload_tx_len *
+				  no_samples);
+	}
+
+	if(eng_desc->offload_config & OFFLOAD_RX_EN) {
+		axi_dmac_transfer(eng_desc->offload_rx_dma,
+				  msg.rx_addr,
+				  word_length * eng_desc->offload_tx_len *
+				  no_samples);
+	}
+
+	usleep(1000);
+
+	spi_engine_queue_free(&transfer.cmds);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by spi_init().
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_remove(struct spi_desc *desc)
+{
+	struct spi_engine_desc	*eng_desc;
+
+	eng_desc = desc->extra;
+
+	if(eng_desc->offload_config & OFFLOAD_TX_EN)
+		axi_dmac_remove(eng_desc->offload_tx_dma);
+	if(eng_desc->offload_config & OFFLOAD_RX_EN)
+		axi_dmac_remove(eng_desc->offload_rx_dma);
+	free(desc->extra);
+	free(desc);
+
+	return SUCCESS;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/axi_core/spi_engine/spi_engine.h

@@ -0,0 +1,231 @@
+/*******************************************************************************
+ *   @file   spi_engine.h
+ *   @brief  Header file of SPI Engine core features.
+ *   @author Sergiu Cuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef SPI_ENGINE_H
+#define SPI_ENGINE_H
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+#include "spi_engine_private.h"
+#include "../../platform/spi_extra.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define OFFLOAD_DISABLED		0x00
+#define OFFLOAD_TX_EN			BIT(0)
+#define OFFLOAD_RX_EN			BIT(1)
+#define OFFLOAD_TX_RX_EN		OFFLOAD_TX_EN | OFFLOAD_RX_EN
+
+#define SPI_ENGINE_MSG_QUEUE_END	0xFFFFFFFF
+
+/* Spi engine commands */
+#define	WRITE_OR_READ(mode, no_bytes)	((SPI_ENGINE_INST_TRANSFER << 12) |\
+((mode) << 8) | (no_bytes))
+
+#define	WRITE(no_bytes)			((SPI_ENGINE_INST_TRANSFER << 12) |\
+	(SPI_ENGINE_INSTRUCTION_TRANSFER_W << 8) | (no_bytes))
+
+#define	READ(no_bytes)			((SPI_ENGINE_INST_TRANSFER << 12) |\
+	(SPI_ENGINE_INSTRUCTION_TRANSFER_R << 8) | (no_bytes))
+
+#define	WRITE_READ(no_bytes)		((SPI_ENGINE_INST_TRANSFER << 12) |\
+	(SPI_ENGINE_INSTRUCTION_TRANSFER_RW << 8) | (no_bytes))
+
+
+
+#define SLEEP(time)			SPI_ENGINE_CMD_SLEEP(time & 0xF)
+
+/* The delay and chip select parmeters are passed over the engine descriptor
+and will be used inside the function call */
+#define CS_HIGH			SPI_ENGINE_CMD_ASSERT(0x00, 0xFF)
+#define CS_LOW			SPI_ENGINE_CMD_ASSERT(0x00, 0x00)
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @struct spi_engine_init_param
+ * @brief  Structure containing the init parameters needed by the SPI engine
+ */
+struct spi_engine_init_param {
+	/** SPI engine reference clock */
+	uint32_t	ref_clk_hz;
+	/** Type of implementation */
+	enum xil_spi_type	type;
+	/** Base address where the HDL core is situated */
+	uint32_t 		spi_engine_baseaddr;
+	/** Delay between the CS toggle and the start of SCLK */
+	uint32_t		cs_delay;
+	/** Data with of one SPI transfer ( in bits ) */
+	uint8_t			data_width;
+};
+
+
+/**
+ * @struct spi_engine_desc
+ * @brief  Structure representing an SPI engine device
+ */
+struct spi_engine_desc {
+	/** SPI engine reference clock */
+	uint32_t	ref_clk_hz;
+	/** Type of implementation */
+	enum xil_spi_type	type;
+	/** Pointer to a DMAC used in transmission */
+	struct axi_dmac		*offload_tx_dma;
+	/** Pointer to a DMAC used in reception */
+	struct axi_dmac		*offload_rx_dma;
+	/** Offload's module transfer direction : TX, RX or both */
+	uint8_t			offload_config;
+	/** Number of words that the module has to send */
+	uint8_t			offload_tx_len;
+	/** Number of words that the module has to receive */
+	uint8_t			offload_rx_len;
+	/** Base address where the HDL core is situated */
+	uint32_t		spi_engine_baseaddr;
+	/** Base address where the RX DMAC core is situated */
+	uint32_t		rx_dma_baseaddr;
+	/** Base address where the TX DMAC core is situated */
+	uint32_t		tx_dma_baseaddr;
+	/** Delay between the CS toggle and the start of SCLK */
+	uint8_t			cs_delay;
+	/** Clock divider used in transmission delays */
+	uint32_t		clk_div;
+	/** Data with of one SPI transfer ( in bits ) */
+	uint8_t			data_width;
+	/** The maximum data width supported by the engine */
+	uint8_t 		max_data_width;
+};
+
+
+/**
+ * @struct spi_engine_offload_init_param
+ * @brief  Structure containing the init parameters needed by the offload module
+ */
+struct spi_engine_offload_init_param {
+	/** Base address where the RX DMAC core is situated */
+	uint32_t	rx_dma_baseaddr;
+	/** Base address where the TX DMAC core is situated */
+	uint32_t	tx_dma_baseaddr;
+	/** DMAC flags - if not initialized, the default value is DMA_CYCLIC */
+	uint32_t	*dma_flags;
+	/** Offload's module transfer direction : TX, RX or both */
+	uint8_t		offload_config;
+};
+
+/**
+ * @struct spi_engine_offload_message
+ * @brief  Structure representing an offload message
+ */
+struct spi_engine_offload_message {
+	/** Pointer to the SPI engine commands buffer that will be sent.
+	 * The available commands can be found at:
+	 * https://wiki.analog.com/resources/fpga/peripherals/spi_engine/
+	*/
+	uint32_t *commands;
+	/** Length of the SPI engine commands buffer */
+	uint32_t no_commands;
+	/** Pointer of the data that will be sent over spi */
+	uint32_t *commands_data;
+	/** The address where the data that will be transmitted is situated */
+	uint32_t tx_addr;
+	/** The address where the data that will be received is situated */
+	uint32_t rx_addr;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/**
+ * @brief Spi engine platform specific SPI platform ops structure
+ */
+extern const struct spi_platform_ops xil_spi_ops;
+
+/* Write SPI Engine's axi registers */
+int32_t spi_engine_write(struct spi_engine_desc *desc,
+			 uint32_t reg_addr,
+			 uint32_t reg_data);
+
+/* Read SPI Engine's axi registers */
+int32_t spi_engine_read(struct spi_engine_desc *desc,
+			uint32_t reg_addr,
+			uint32_t *reg_data);
+/* Initialize the SPI engine device */
+int32_t spi_engine_init(struct spi_desc **desc,
+			const struct spi_init_param *param);
+
+/* Write and read data over SPI using the SPI engine */
+int32_t spi_engine_spi_write_and_read(struct spi_desc *desc,
+				  uint8_t *data,
+				  uint16_t bytes_number);
+
+/* Write and read data over SPI using the SPI engine in 3-wire mode */
+int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc,
+		   uint8_t *write_data,
+		   uint8_t *read_data,
+		   uint16_t write_bytes_number,
+		   uint16_t read_bytes_number);
+/* Free the resources used by the SPI engine device */
+int32_t spi_engine_remove(struct spi_desc *desc);
+
+/* Initialize the SPI engine offload module */
+int32_t spi_engine_offload_init(struct spi_desc *desc,
+				const struct spi_engine_offload_init_param *param);
+
+/* Write and read data over SPI using the offload module */
+int32_t spi_engine_offload_transfer(struct spi_desc *desc,
+				    struct spi_engine_offload_message msg,
+				    uint32_t no_samples);
+
+/* Set SPI transfer width */
+int32_t spi_engine_set_transfer_width(struct spi_desc *desc,
+				      uint8_t data_wdith);
+
+/* Set SPI transfer speed */
+void spi_engine_set_speed(struct spi_desc *desc,
+			  uint32_t speed_hz);
+
+#endif // SPI_ENGINE_H

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h

@@ -0,0 +1,154 @@
+/*******************************************************************************
+ *   @file   spi_engine_private.h
+ *   @brief  Private definitions of the SPI Engine
+ *   @author Sergiu Cuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef SPI_ENGINE_PRIVATE_H
+#define SPI_ENGINE_PRIVATE_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "../../../include/spi.h"
+#include "../../../include/util.h"
+
+/******************************************************************************/
+/*************************** Spi Engine registers *****************************/
+/******************************************************************************/
+
+#define SPI_ENGINE_REG_VERSION			0x00
+#define SPI_ENGINE_REG_DATA_WIDTH		0x0C
+#define SPI_ENGINE_REG_RESET			0x40
+#define SPI_ENGINE_REG_INT_ENABLE		0x80
+#define SPI_ENGINE_REG_INT_PENDING		0x84
+#define SPI_ENGINE_REG_INT_SOURCE		0x88
+#define SPI_ENGINE_REG_SYNC_ID			0xC0
+#define SPI_ENGINE_REG_CMD_FIFO_ROOM		0xD0
+#define SPI_ENGINE_REG_SDO_FIFO_ROOM		0xD4
+#define SPI_ENGINE_REG_SDI_FIFO_LEVEL		0xD8
+#define SPI_ENGINE_REG_CMD_FIFO 		0xE0
+#define SPI_ENGINE_REG_SDO_DATA_FIFO		0xE4
+#define SPI_ENGINE_REG_SDI_DATA_FIFO		0xE8
+#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK	0xEC
+
+/******************************************************************************/
+/************************ Spi Engine register parameters **********************/
+/******************************************************************************/
+
+#define SPI_ENGINE_INST_TRANSFER		0x00
+#define SPI_ENGINE_INST_ASSERT			0x01
+#define SPI_ENGINE_INST_CONFIG			0x02
+#define SPI_ENGINE_INST_SYNC_SLEEP		0x03
+#define SPI_ENGINE_INST_MISC			0x03
+#define SPI_ENGINE_CMD_REG_CLK_DIV		0x00
+#define SPI_ENGINE_CMD_REG_CONFIG		0x01
+#define SPI_ENGINE_CMD_DATA_TRANSFER_LEN	0x02
+#define SPI_ENGINE_MISC_SYNC			0x00
+#define SPI_ENGINE_MISC_SLEEP			0x01
+#define SPI_ENGINE_SYNC_TRANSFER_BEGIN		BIT(1)
+#define SPI_ENGINE_SYNC_TRANSFER_END		BIT(2)
+#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY		BIT(0)
+#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY		BIT(1)
+#define SPI_ENGINE_INT_SDI_ALMOST_FULL		BIT(2)
+#define SPI_ENGINE_INT_SYNC			BIT(3)
+#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE		BIT(0)
+#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED	BIT(0)
+#define SPI_ENGINE_CONFIG_CPHA			BIT(0)
+#define SPI_ENGINE_CONFIG_CPOL			BIT(1)
+#define SPI_ENGINE_CONFIG_3WIRE			BIT(2)
+#define SPI_ENGINE_VERSION_MAJOR(x) 		((x >> 16) & 0xff)
+#define SPI_ENGINE_VERSION_MINOR(x) 		((x >> 8) & 0xff)
+#define SPI_ENGINE_VERSION_PATCH(x) 		(x & 0xff)
+
+/******************************************************************************/
+/**************************** Spi Engine commands *****************************/
+/******************************************************************************/
+
+#define SPI_ENGINE_INSTRUCTION_TRANSFER_W	0x01
+#define SPI_ENGINE_INSTRUCTION_TRANSFER_R	0x02
+#define SPI_ENGINE_INSTRUCTION_TRANSFER_RW	0x03
+
+#define SPI_ENGINE_REG_OFFLOAD_CTRL(x)		(0x100 + (0x20 * x))
+#define SPI_ENGINE_REG_OFFLOAD_STATUS(x)	(0x104 + (0x20 * x))
+#define SPI_ENGINE_REG_OFFLOAD_RESET(x)		(0x108 + (0x20 * x))
+#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM(x)	(0x110 + (0x20 * x))
+#define SPI_ENGINE_REG_OFFLOAD_SDO_MEM(x)	(0x114 + (0x20 * x))
+
+#define SPI_ENGINE_CMD(inst, arg1, arg2) 				\
+			(((inst & 0x03) << 12) | 			\
+			((arg1 & 0x03) << 8) | arg2 )
+
+#define SPI_ENGINE_CMD_TRANSFER(readwrite, n)				\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER,			\
+			(readwrite), (n))
+
+#define SPI_ENGINE_CMD_ASSERT(delay, cs) 				\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT,				\
+			(delay), (cs))
+
+#define SPI_ENGINE_CMD_CONFIG(reg, val)					\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_CONFIG,				\
+			(reg), (val))
+
+#define SPI_ENGINE_CMD_SLEEP(delay) 					\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, 				\
+			SPI_ENGINE_MISC_SLEEP, 				\
+			(delay))
+
+#define SPI_ENGINE_CMD_SYNC(id) 					\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, 				\
+			SPI_ENGINE_MISC_SYNC, 				\
+			(id))
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+typedef struct spi_engine_cmd_queue {
+	uint32_t	cmd;
+	struct		spi_engine_cmd_queue *next;
+} spi_engine_cmd_queue;
+
+typedef struct spi_engine_msg {
+	uint32_t			*tx_buf;
+	uint32_t			*rx_buf;
+	uint32_t			tx_length;
+	uint32_t			rx_length;
+	struct spi_engine_cmd_queue	*cmds;
+} spi_engine_msg;
+
+#endif // SPI_ENGINE_PRIVATE_H

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/frequency/lmk04828/lmk04828.c

@@ -0,0 +1,128 @@
+/***************************************************************************//**
+ * @file lmk04828.c
+ * @brief Implementation of AD9680 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdlib.h>
+#include <stdio.h>
+#include "lmk04828.h"
+#include "../../../include/error.h"
+
+/***************************************************************************//**
+ * @brief lmk04828_read
+ *******************************************************************************/
+int32_t lmk04828_read(struct lmk04828_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data)
+{
+	uint8_t tx_buf[2];
+	uint8_t rx_buf[1];
+	int32_t ret;
+
+	tx_buf[0] = 0x80 | (reg_addr >> 8);
+	tx_buf[1] = reg_addr & 0xFF;
+
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+			tx_buf, rx_buf, 2, 1);
+
+	*reg_data = rx_buf[0];
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief lmk04828_write
+ *******************************************************************************/
+int32_t lmk04828_write(struct lmk04828_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data)
+{
+	uint8_t buf[3];
+
+	int32_t ret;
+
+	buf[0] = reg_addr >> 8;
+	buf[1] = reg_addr & 0xFF;
+	buf[2] = reg_data;
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+				 buf, NULL, 3, 0);
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief lmk04828_init
+ *******************************************************************************/
+int32_t lmk04828_init(struct lmk04828_dev **device,
+		     const struct lmk04828_init_param *init_param)
+{
+	int ret = SUCCESS;
+	struct lmk04828_dev *dev;
+
+	dev = (struct lmk04828_dev *)malloc(sizeof(*dev));
+	if (!dev)
+		return FAILURE;
+
+	/* SPI */
+	ret = spi_init(&dev->spi_desc, init_param->spi_init);
+
+	*device = dev;
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief Free the resources allocated by lmk04828_setup().
+ *
+ * @param dev - The device structure.
+ *
+ * @return SUCCESS in case of success, negative error code otherwise.
+*******************************************************************************/
+int32_t lmk04828_remove(struct lmk04828_dev *dev)
+{
+	int32_t ret;
+
+	ret = spi_remove(dev->spi_desc);
+
+	free(dev);
+
+	return ret;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/frequency/lmk04828/lmk04828.h

@@ -0,0 +1,89 @@
+/***************************************************************************//**
+ * @file lmk04828.h
+ * @brief Header file of lmk04828 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+#ifndef LMK04828_H_
+#define LMK04828_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include "../../../include/delay.h"
+#include "../../../include/spi.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+struct lmk04828_dev {
+	/* SPI */
+	spi_desc	*spi_desc;
+};
+
+struct lmk04828_init_param {
+	/* SPI */
+	spi_init_param	*spi_init;
+};
+
+struct lmk04828_config {
+	uint16_t addr;
+	uint8_t value;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+int32_t lmk04828_read(struct lmk04828_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data);
+
+int32_t lmk04828_write(struct lmk04828_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data);
+
+int32_t lmk04828_init(struct lmk04828_dev **device,
+		     const struct lmk04828_init_param *init_param);
+
+int32_t lmk04828_remove(struct lmk04828_dev *dev);
+
+#endif

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/platform/axi_io.c

@@ -0,0 +1,79 @@
+/***************************************************************************//**
+ *   @file   xilinx/axi_io.c
+ *   @brief  Implementation of Xilinx AXI IO.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <xil_io.h>
+#include "../../include/error.h"
+#include "../../include/axi_io.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief AXI IO Xilinx specific read function.
+ * @param base - Base address
+ * @param offset - Address offset
+ * @param data - variable where returned data is stored
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
+{
+	*data = Xil_In32(base + offset);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief AXI IO Xilinx specific write function.
+ * @param base - Base address
+ * @param offset - Address offset
+ * @param data - data to be written.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
+{
+	Xil_Out32(base + offset, data);
+
+	return SUCCESS;
+}
+

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/platform/delay.c

@@ -0,0 +1,77 @@
+/***************************************************************************//**
+ *   @file   xilinx/delay.c
+ *   @brief  Implementation of Xilinx Delay Functions.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include "../../include/delay.h"
+#include <sleep.h>
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Generate microseconds delay.
+ * @param usecs - Delay in microseconds.
+ * @return None.
+ */
+void udelay(uint32_t usecs)
+{
+#ifdef _XPARAMETERS_PS_H_
+	usleep(usecs);
+#else
+	usleep(usecs / 20);	// FIXME
+#endif
+}
+
+/**
+ * @brief Generate miliseconds delay.
+ * @param msecs - Delay in miliseconds.
+ * @return None.
+ */
+void mdelay(uint32_t msecs)
+{
+#ifdef _XPARAMETERS_PS_H_
+	usleep(msecs * 1000);
+#else
+	usleep(msecs * 50);	// FIXME
+#endif
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/platform/gpio_extra.h

@@ -0,0 +1,95 @@
+/*******************************************************************************
+ *   @file   xilinx/gpio_extra.h
+ *   @brief  Header containing extra types used in the gpio driver
+ *   @author scuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef GPIO_EXTRA_H_
+#define GPIO_EXTRA_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum xil_gpio_type
+ * @brief Xilinx platform architecture sections
+ */
+typedef enum xil_gpio_type {
+	/** Programmable Logic */
+	GPIO_PL,
+	/** Processing System */
+	GPIO_PS
+} xil_gpio_type;
+
+/**
+ * @struct xil_gpio_init_param
+ * @brief Structure holding the initialization parameters for Xilinx platform
+ * specific GPIO parameters.
+ */
+typedef struct xil_gpio_init_param {
+	/** Xilinx architecture */
+	enum xil_gpio_type	type;
+	/** Device ID */
+	uint32_t		device_id;
+} xil_gpio_init_param;
+
+/**
+ * @struct xil_gpio_desc
+ * @brief Xilinx platform specific GPIO descriptor
+ */
+typedef struct xil_gpio_desc {
+	/** Xilinx architecture */
+	enum xil_gpio_type	type;
+	/** Xilinx GPIO configuration */
+	void			*config;
+	/** Xilinx GPIO Instance */
+	void			*instance;
+} xil_gpio_desc;
+
+/**
+ * @brief Xilinx platform specific gpio platform ops structure
+ */
+extern const struct gpio_platform_ops xil_gpio_ops;
+
+#endif

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/platform/irq_extra.h

@@ -0,0 +1,91 @@
+/*******************************************************************************
+ *   @file   irq_extra.h
+ *   @brief  Header containing types used in the irq driver.
+ *   @author Cristian Pop ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef IRQ_EXTRA_H_
+#define IRQ_EXTRA_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+#include "../../include/irq.h"
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum xil_irq_type
+ * @brief Xilinx platform architecture sections
+ */
+enum xil_irq_type {
+	/** Programmable Logic */
+	IRQ_PL,
+	/** Processing System */
+	IRQ_PS
+};
+
+/**
+ * @struct xil_irq_init_param
+ * @brief Structure holding the initialization parameters for Xilinx platform
+ * specific IRQ parameters.
+ */
+struct xil_irq_init_param {
+	/** Xilinx architecture */
+	enum xil_irq_type	type;
+};
+
+/**
+ * @struct xil_irq_desc
+ * @brief Xilinx platform specific IRQ descriptor
+ */
+struct xil_irq_desc {
+	/** Xilinx architecture */
+	enum xil_irq_type	type;
+	/** Xilinx IRQ Instance */
+	void				*instance;
+};
+
+/**
+ * @brief Xilinx specific IRQ platform ops structure
+ */
+extern const struct irq_platform_ops xil_irq_ops;
+
+#endif

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/platform/spi_extra.h

@@ -0,0 +1,115 @@
+/*******************************************************************************
+ *   @file   xilinx/spi_extra.h
+ *   @brief  Header containing extra types used in the spi driver.
+ *   @author scuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef SPI_EXTRA_H_
+#define SPI_EXTRA_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+#include "../../include/spi.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define SPI_CS_DECODE			0x01
+#define SPI_DEASSERT_CURRENT_SS	0x0F
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum xil_spi_type
+ * @brief Xilinx platform architecture sections
+ */
+enum xil_spi_type {
+	/** Programmable Logic */
+	SPI_PL,
+	/** Processing System */
+	SPI_PS,
+	/** SPI Engine */
+	SPI_ENGINE
+};
+
+/**
+ * @struct xil_spi_init_param
+ * @brief Structure holding the initialization parameters for Xilinx platform
+ * specific SPI parameters when using xil_spi_ops.
+ */
+typedef struct xil_spi_init_param {
+	/** Xilinx architecture */
+	enum xil_spi_type	type;
+	/** SPI flags */
+	uint32_t		flags;
+} xil_spi_init_param;
+
+/**
+ * @struct xil_spi_desc
+ * @brief Xilinx platform specific SPI descriptor
+ */
+typedef struct xil_spi_desc {
+	/** Xilinx architecture */
+	enum xil_spi_type	type;
+	/** SPI flags */
+	uint32_t		flags;
+	/** SPI configuration */
+	void			*config;
+	/** SPI instance */
+	void			*instance;
+} xil_spi_desc;
+
+/**
+ * @brief SPI engine platform ops structure
+ */
+extern const struct spi_platform_ops spi_eng_platform_ops;
+
+/**
+ * @brief Xilinx specific SPI platform ops structure
+ */
+extern const struct spi_platform_ops xil_spi_ops;
+
+/**
+ * @brief Xilinx SPI PS register functions. No extra param needed
+ */
+extern const struct spi_platform_ops xil_spi_reg_ops_pl;
+
+#endif // SPI_EXTRA_H_

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/platform/uart_extra.h

@@ -0,0 +1,107 @@
+/*******************************************************************************
+ *   @file   xilinx/uart_extra.h
+ *   @brief  Header containing types used in the uart driver.
+ *   @author Cristian Pop ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef UART_EXTRA_H_
+#define UART_EXTRA_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define UART_BUFF_LENGTH 256
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum xil_uart_type
+ * @brief Xilinx platform architecture sections
+ */
+enum xil_uart_type {
+	/** Programmable Logic */
+	UART_PL,
+	/** Processing System */
+	UART_PS
+};
+
+/**
+ * @struct xil_uart_init_param
+ * @brief Structure holding the initialization parameters for Xilinx platform
+ * specific UART parameters.
+ */
+struct xil_uart_init_param {
+	/** Xilinx architecture */
+	enum xil_uart_type	type;
+	/** Interrupt Request ID */
+	uint32_t			irq_id;
+	/** Interrupt Request Descriptor */
+	struct irq_ctrl_desc *irq_desc;
+};
+
+/**
+ * @struct xil_uart_desc
+ * @brief Xilinx platform specific UART descriptor
+ */
+struct xil_uart_desc {
+	/** Xilinx architecture */
+	enum xil_uart_type	type;
+	/** Interrupt Request ID */
+	uint32_t			irq_id;
+	/** Interrupt Request Descriptor */
+	struct irq_ctrl_desc *irq_desc;
+	/** FIFO */
+	struct fifo_element	*fifo;
+	/** FIFO read offset */
+	uint32_t 			fifo_read_offset;
+	/** UART Buffer */
+	char 				buff[UART_BUFF_LENGTH];
+	/** Number of bytes received */
+	uint32_t 			bytes_received;
+	/** Total number of errors */
+	uint32_t 			total_error_count;
+	/** UART Instance */
+	void				*instance;
+};
+
+#endif

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/platform/xilinx_gpio.c

@@ -0,0 +1,464 @@
+/***************************************************************************//**
+ *   @file   xilinx/xilinx_gpio.c
+ *   @brief  Implementation of Xilinx GPIO Generic Driver.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdlib.h>
+
+#include <xparameters.h>
+#ifdef XPAR_XGPIO_NUM_INSTANCES
+#include <xgpio.h>
+#endif
+#ifdef XPAR_XGPIOPS_NUM_INSTANCES
+#include <xgpiops.h>
+#endif
+
+#include "gpio_extra.h"
+#include "../../include/error.h"
+#include "../../include/gpio.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Prepare the GPIO decriptor.
+ * @param desc - The GPIO descriptor.
+ * @param param - The structure that contains the GPIO parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t _gpio_init(struct gpio_desc *desc,
+		   const struct gpio_init_param *param)
+{
+	int32_t				ret;
+	struct xil_gpio_desc		*xdesc;
+	struct xil_gpio_init_param	*xinit;
+
+	ret = FAILURE;
+
+	xdesc = desc->extra;
+	xinit = param->extra;
+
+	xdesc->type = xinit->type;
+	desc->number = param->number;
+
+	switch (xinit->type) {
+	case GPIO_PL:
+#ifdef XGPIO_H
+		xdesc->instance = (XGpio *)malloc(sizeof(XGpio));
+		if(!xdesc->instance)
+			goto pl_error;
+
+		xdesc->config = XGpio_LookupConfig(xinit->device_id);
+		if(xdesc->config == NULL)
+			goto pl_error;
+
+		ret = XGpio_CfgInitialize(xdesc->instance,
+					  xdesc->config,
+					  ((XGpio_Config*)xdesc->config)
+					  ->BaseAddress);
+		if(ret < 0)
+			goto pl_error;
+
+		break;
+pl_error:
+		free(xdesc->instance);
+#endif
+		goto error;
+	case GPIO_PS:
+#ifdef XGPIOPS_H
+		xdesc->instance = (XGpioPs *)malloc(sizeof(XGpioPs));
+		if(!xdesc->instance)
+			goto ps_error;
+
+		xdesc->config = XGpioPs_LookupConfig(xinit->device_id);
+		if(xdesc->config == NULL)
+			goto ps_error;
+
+		ret = XGpioPs_CfgInitialize(xdesc->instance,
+					    xdesc->config,
+					    ((XGpioPs_Config*)xdesc->config)->BaseAddr);
+		if(ret < 0)
+			goto ps_error;
+		break;
+ps_error:
+		free(xdesc->instance);
+#endif
+		goto error;
+error:
+	default:
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Obtain the GPIO decriptor.
+ * @param desc - The GPIO descriptor.
+ * @param param - GPIO initialization parameters
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_get(struct gpio_desc **desc,
+		     const struct gpio_init_param *param)
+{
+	struct gpio_desc	*descriptor;
+	struct xil_gpio_desc	*extra;
+	int32_t			ret;
+
+	descriptor = (struct gpio_desc *)malloc(sizeof(*descriptor));
+	extra = (struct xil_gpio_desc*)malloc(sizeof(*extra));
+
+	if (!descriptor || !extra)
+		return FAILURE;
+
+	descriptor->extra = extra;
+	ret = _gpio_init(descriptor, param);
+
+	if(ret != SUCCESS)
+		goto error;
+
+	*desc = descriptor;
+
+	return SUCCESS;
+error:
+	free(extra);
+	free(descriptor);
+
+	return FAILURE;
+}
+
+/**
+ * @brief Get the value of an optional GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param param - GPIO Initialization parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_get_optional(struct gpio_desc **desc,
+			      const struct gpio_init_param *param)
+{
+	if(param == NULL) {
+		*desc = NULL;
+		return SUCCESS;
+	}
+
+	return xil_gpio_get(desc, param);
+}
+
+/**
+ * @brief Free the resources allocated by gpio_get().
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_remove(struct gpio_desc *desc)
+{
+	if (desc != NULL) {
+		free(((xil_gpio_desc *)(desc->extra))->instance);
+		free(desc->extra);
+		free(desc);
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Enable the input direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_direction_input(struct gpio_desc *desc)
+{
+	struct xil_gpio_desc	*extra;
+#ifdef XGPIO_H
+	uint8_t pin = desc->number;
+	uint32_t channel = 1;
+	uint32_t config	 = 0;
+#endif
+	extra = desc->extra;
+
+	switch (extra->type) {
+	case GPIO_PL:
+#ifdef XGPIO_H
+		/* We assume that pin 32 is the first pin from channel 2 */
+		if (pin >= 32) {
+			channel = 2;
+			pin -= 32;
+		}
+
+		config = XGpio_GetDataDirection((XGpio *)extra->instance,
+						channel);
+		config |= (1 << pin);
+		XGpio_SetDataDirection((XGpio *)extra->instance,
+				       channel,
+				       config);
+#endif
+		break;
+	case GPIO_PS:
+#ifdef XGPIOPS_H
+		XGpioPs_SetDirectionPin(extra->instance,
+					desc->number,
+					GPIO_IN);
+#endif
+		break;
+	default:
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Enable the output direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_direction_output(struct gpio_desc *desc,
+				  uint8_t value)
+{
+	struct xil_gpio_desc	*extra;
+#ifdef XGPIO_H
+	uint8_t pin = desc->number;
+	uint8_t channel;
+	uint32_t reg_val;
+#endif
+	extra = desc->extra;
+
+	switch (extra->type) {
+	case GPIO_PL:
+#ifdef XGPIO_H
+		if (pin >= 32) {
+			channel = 2;
+			pin -= 32;
+		} else
+			channel = 1;
+
+		reg_val = XGpio_GetDataDirection(extra->instance,
+						 channel);
+		reg_val &= ~(1 << pin);
+		XGpio_SetDataDirection(extra->instance,
+				       channel,
+				       reg_val);
+		reg_val = XGpio_DiscreteRead(extra->instance,
+					     channel);
+		if(value)
+			reg_val |= (1 << pin);
+		else
+			reg_val &= ~(1 << pin);
+		XGpio_DiscreteWrite(extra->instance,
+				    channel,
+				    reg_val);
+#endif
+		break;
+	case GPIO_PS:
+#ifdef XGPIOPS_H
+		XGpioPs_SetDirectionPin(extra->instance,
+					desc->number,
+					GPIO_OUT);
+		XGpioPs_SetOutputEnablePin(extra->instance,
+					   desc->number,
+					   GPIO_OUT);
+		XGpioPs_WritePin(extra->instance,
+				 desc->number,
+				 value);
+#endif
+		break;
+	default:
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Get the direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param direction - The direction.
+ *                    Example: GPIO_OUT
+ *                             GPIO_IN
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_get_direction(struct gpio_desc *desc,
+			       uint8_t *direction)
+{
+	if (!desc)
+		return FAILURE;
+
+	struct xil_gpio_desc	*extra;
+	uint8_t pin = desc->number;
+
+#ifdef XGPIO_H
+	uint8_t channel;
+#endif
+	extra = desc->extra;
+
+	switch (extra->type) {
+	case GPIO_PL:
+#ifdef XGPIO_H
+		if (pin >= 32) {
+			channel = 2;
+			pin -= 32;
+		} else
+			channel = 1;
+		*direction = ((XGpio_GetDataDirection(extra->instance,
+						      channel) >> pin) & 0x1) ^ 0x1;
+#endif
+		break;
+	case GPIO_PS:
+#ifdef XGPIOPS_H
+		*direction = XGpioPs_GetDirectionPin(extra->instance, pin);
+#endif
+		break;
+	default:
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Set the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_set_value(struct gpio_desc *desc,
+			   uint8_t value)
+{
+	struct xil_gpio_desc	*extra;
+#ifdef XGPIO_H
+	uint8_t pin = desc->number;
+	uint8_t channel;
+	uint32_t reg_val;
+#endif
+	extra = desc->extra;
+
+	switch (extra->type) {
+	case GPIO_PL:
+#ifdef XGPIO_H
+		if (pin >= 32) {
+			channel = 2;
+			pin -= 32;
+		} else
+			channel = 1;
+
+		reg_val = XGpio_DiscreteRead(extra->instance, channel);
+		if(value)
+			reg_val |= (1 << pin);
+		else
+			reg_val &= ~(1 << pin);
+		XGpio_DiscreteWrite(extra->instance, channel, reg_val);
+#endif
+		break;
+	case GPIO_PS:
+#ifdef XGPIOPS_H
+		XGpioPs_WritePin(extra->instance, desc->number, value);
+#endif
+		break;
+	default:
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Get the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_get_value(struct gpio_desc *desc,
+			   uint8_t *value)
+{
+	if (!desc)
+		return FAILURE;
+
+	struct xil_gpio_desc	*extra;
+	uint8_t pin = desc->number;
+
+#ifdef XGPIO_H
+	uint8_t channel;
+#endif
+	extra = desc->extra;
+
+	switch (extra->type) {
+	case GPIO_PL:
+#ifdef XGPIO_H
+		if (pin >= 32) {
+			channel = 2;
+			pin -= 32;
+		} else
+			channel = 1;
+		*value = (XGpio_DiscreteRead(extra->instance, channel) >> pin) & 0x01;
+#endif
+		break;
+	case GPIO_PS:
+#ifdef XGPIOPS_H
+		*value = XGpioPs_ReadPin(extra->instance, pin);
+#endif
+		break;
+	default:
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Xilinx platform specific GPIO platform ops structure
+ */
+const struct gpio_platform_ops xil_gpio_ops = {
+	.gpio_ops_get = &xil_gpio_get,
+	.gpio_ops_get_optional = &xil_gpio_get_optional,
+	.gpio_ops_remove = &xil_gpio_remove,
+	.gpio_ops_direction_input = &xil_gpio_direction_input,
+	.gpio_ops_direction_output = &xil_gpio_direction_output,
+	.gpio_ops_get_direction = &xil_gpio_get_direction,
+	.gpio_ops_set_value = &xil_gpio_set_value,
+	.gpio_ops_get_value = &xil_gpio_get_value,
+};

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/platform/xilinx_irq.c

@@ -0,0 +1,384 @@
+/***************************************************************************//**
+ *   @file   xilinx/xilinx_irq.c
+ *   @brief  Implementation of Xilinx IRQ Generic Driver.
+ *   @author Cristian Pop ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <xparameters.h>
+#include <stdlib.h>
+#include "irq_extra.h"
+#include "../../include/irq.h"
+#include "../../include/error.h"
+#ifdef XPAR_XSCUGIC_NUM_INSTANCES
+#include <xscugic.h>
+#endif
+#ifdef XPAR_XINTC_NUM_INSTANCES
+#include <xintc.h>
+#endif
+#ifdef XPAR_XTMRCTR_NUM_INSTANCES
+#include <xtmrctr.h>
+#endif
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Initialize the IRQ interrupts.
+ * @param desc - The IRQ controller descriptor.
+ * @param param - The structure that contains the IRQ parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_ctrl_init(struct irq_ctrl_desc **desc,
+			  const struct irq_init_param *param)
+{
+	int32_t status;
+	struct irq_ctrl_desc *descriptor;
+	struct xil_irq_desc *xil_dev;
+#ifdef XSCUGIC_H
+	void *config;
+#endif
+
+	descriptor = (struct irq_ctrl_desc *)calloc(1, sizeof *descriptor);
+	if(!descriptor)
+		return FAILURE;
+	xil_dev = (struct xil_irq_desc *)calloc(1, sizeof *xil_dev);
+	if(!xil_dev) {
+		free(descriptor);
+		return FAILURE;
+	}
+
+	Xil_ExceptionInit();
+
+	descriptor->irq_ctrl_id = param->irq_ctrl_id;
+	descriptor->extra = xil_dev;
+	xil_dev->type = ((struct xil_irq_init_param *)param->extra)->type;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		xil_dev->instance = calloc(1, sizeof(XScuGic));
+		if(!xil_dev->instance)
+			goto error;
+
+		config = XScuGic_LookupConfig(descriptor->irq_ctrl_id);
+		if(!config)
+			goto ps_error;
+
+		status = XScuGic_CfgInitialize(xil_dev->instance, config,
+					       ((XScuGic_Config *)config)->CpuBaseAddress);
+		if (status != SUCCESS)
+			goto ps_error;
+
+		Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+					     (Xil_ExceptionHandler)XScuGic_InterruptHandler,
+					     xil_dev->instance);
+
+		break;
+ps_error:
+		free(xil_dev->instance);
+#endif
+		goto error;
+	case IRQ_PL:
+#ifdef XINTC_H
+		xil_dev->instance = calloc(1, sizeof(XIntc));
+		if(!xil_dev->instance)
+			goto error;
+
+		status = XIntc_Initialize(xil_dev->instance, descriptor->irq_ctrl_id);
+		if(status != SUCCESS)
+			goto pl_error;
+
+		status = XIntc_Start(xil_dev->instance, XIN_REAL_MODE);
+		if(status != SUCCESS)
+			goto pl_error;
+
+		break;
+pl_error:
+		free(xil_dev->instance);
+#endif
+		goto error;
+	default:
+		goto error;
+
+		break;
+	}
+
+	*desc = descriptor;
+
+	return SUCCESS;
+
+error:
+	free(xil_dev);
+	free(descriptor);
+
+	return FAILURE;
+}
+
+/**
+ * @brief Enable global interrupts.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_global_enable(struct irq_ctrl_desc *desc)
+{
+	/* Enable interrupts */
+	Xil_ExceptionEnable();
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Disable global interrupts.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_global_disable(struct irq_ctrl_desc *desc)
+{
+	/* Disable interrupts */
+	Xil_ExceptionDisable();
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Enable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		XScuGic_Enable(xil_dev->instance, irq_id);
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		XIntc_Enable(xil_dev->instance, irq_id);
+#endif
+		break;
+	default:
+
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Disable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		XScuGic_Disable(xil_dev->instance, irq_id);
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		XIntc_Disable(xil_dev->instance, irq_id);
+#endif
+		break;
+	default:
+
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Register a callback to handle the irq events.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param callback_desc - Callback descriptor
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
+				  struct callback_desc *callback_desc)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		return XScuGic_Connect(xil_dev->instance, irq_id,
+				       (Xil_InterruptHandler) callback_desc->callback,
+				       callback_desc->ctx);
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		if (irq_id == XPAR_AXI_INTC_AXI_TIMER_INTERRUPT_INTR) {
+			int32_t ret;
+
+			ret = XIntc_Connect(xil_dev->instance, irq_id,
+					    XTmrCtr_InterruptHandler, callback_desc->config);
+			if (IS_ERR_VALUE(ret))
+				return FAILURE;
+			XTmrCtr_SetHandler(callback_desc->config,
+					   (XTmrCtr_Handler)callback_desc->callback,
+					   callback_desc->ctx);
+
+			return SUCCESS;
+		}
+		return XIntc_Connect(xil_dev->instance, irq_id,
+				     (XInterruptHandler) callback_desc->callback,
+				     callback_desc->ctx);
+#endif
+		break;
+	default:
+		break;
+	}
+
+	return FAILURE;
+}
+
+/**
+ * @brief Set interrupt trigger level.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param trig - New trigger level for the interrupt.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
+				  enum irq_trig_level trig)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	if(trig == IRQ_EDGE_BOTH)
+		return -EINVAL;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		;
+		uint8_t priority, trigger;
+
+		XScuGic_GetPriorityTriggerType(xil_dev->instance, irq_id, &priority,
+					       &trigger);
+		trigger = trig;
+		XScuGic_SetPriorityTriggerType(xil_dev->instance, irq_id, priority,
+					       trigger);
+
+		return SUCCESS;
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		/* Interrupt trigger determined in hardware. TODO: verify */
+		return SUCCESS;
+#endif
+		break;
+	default:
+		break;
+	}
+
+	return FAILURE;
+}
+
+/**
+ * @brief Unregisters a generic IRQ handling function.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		XScuGic_Disconnect(xil_dev->instance, irq_id);
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		XIntc_Disconnect(xil_dev->instance, irq_id);
+#endif
+		break;
+	default:
+
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by irq_ctrl_init().
+ * @param desc - The IRQ control descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_ctrl_remove(struct irq_ctrl_desc *desc)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+	free(xil_dev->instance);
+	free(desc->extra);
+	free(desc);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Xilinx platform specific IRQ platform ops structure
+ */
+const struct irq_platform_ops xil_irq_ops = {
+	.init = &xil_irq_ctrl_init,
+	.register_callback = &xil_irq_register_callback,
+	.unregister = &xil_irq_unregister,
+	.global_enable = &xil_irq_global_enable,
+	.global_disable = &xil_irq_global_disable,
+	.trigger_level_set = &xil_irq_trigger_level_set,
+	.enable = &xil_irq_enable,
+	.disable = &xil_irq_disable,
+	.remove = &xil_irq_ctrl_remove
+};

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/platform/xilinx_spi.c

@@ -0,0 +1,461 @@
+/***************************************************************************//**
+ *   @file   xilinx/xilinx_spi.c
+ *   @brief  Implementation of Xilinx SPI Generic Driver.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdlib.h>
+
+#include <xparameters.h>
+#ifdef XPAR_XSPI_NUM_INSTANCES
+#include <xspi.h>
+#endif
+#ifdef XPAR_XSPIPS_NUM_INSTANCES
+#include <xspips.h>
+#endif
+
+#include "../../include/error.h"
+#include "../../include/spi.h"
+#include "spi_extra.h"
+
+#if defined(PLATFORM_ZYNQ)
+#define SPI_CLK_FREQ_HZ(dev)	(XPAR_PS7_SPI_ ## dev ## _SPI_CLK_FREQ_HZ)
+#define SPI_NUM_INSTANCES	XPAR_XSPIPS_NUM_INSTANCES
+#elif defined(PLATFORM_ZYNQMP)
+#define SPI_CLK_FREQ_HZ(dev)	(XPAR_PSU_SPI_ ## dev ## _SPI_CLK_FREQ_HZ)
+#define SPI_NUM_INSTANCES	XPAR_XSPIPS_NUM_INSTANCES
+#else
+#define SPI_NUM_INSTANCES	0
+#endif
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Initialize the hardware SPI peripherial
+ *
+ * @param xdesc Platform specific SPI descriptor
+ * @param xinit Platform specific SPI init param
+ * @return int32_t FAILURE if the device couldn't be found or configured
+ */
+static int32_t spi_init_pl(struct spi_desc *desc,
+			   const struct spi_init_param *param)
+{
+#ifdef XSPI_H
+	int32_t				ret;
+	struct xil_spi_desc 		*xdesc;
+	struct xil_spi_init_param	*xinit;
+
+	xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc));
+	if(!xdesc) {
+		free(xdesc);
+		return FAILURE;
+	}
+
+	desc->extra = xdesc;
+	xinit = param->extra;
+	xdesc->type = xinit->type;
+	xdesc->flags = xinit->flags;
+
+	xdesc->instance = (XSpi*)calloc(1, sizeof(XSpi));
+	if(!xdesc->instance)
+		goto pl_error;
+
+	xdesc->config = XSpi_LookupConfig(param->device_id);
+	if(xdesc->config == NULL)
+		goto pl_error;
+
+	ret = XSpi_CfgInitialize(xdesc->instance,
+				 xdesc->config,
+				 ((XSpi_Config*)xdesc->config)
+				 ->BaseAddress);
+	if(ret != SUCCESS)
+		goto pl_error;
+
+	ret = XSpi_Initialize(xdesc->instance, param->device_id);
+	if (ret != SUCCESS)
+		goto pl_error;
+
+	ret = XSpi_SetOptions(xdesc->instance,
+			      XSP_MASTER_OPTION |
+			      ((desc->mode & SPI_CPOL) ?
+			       XSP_CLK_ACTIVE_LOW_OPTION : 0) |
+			      ((desc->mode & SPI_CPHA) ?
+			       XSP_CLK_PHASE_1_OPTION : 0));
+	if (ret != SUCCESS)
+		goto pl_error;
+
+	ret = XSpi_Start(xdesc->instance);
+	if (ret != SUCCESS)
+		goto pl_error;
+
+	XSpi_IntrGlobalDisable((XSpi *)(xdesc->instance));
+
+	return SUCCESS;
+
+pl_error:
+	free(xdesc->instance);
+	free(xdesc);
+#endif
+	return FAILURE;
+}
+
+/**
+ * @brief Initialize the hardware SPI peripherial
+ *
+ * @param xdesc Platform specific SPI descriptor
+ * @param xinit Platform specific SPI init param
+ * @return int32_t FAILURE if the device couldn't be found or configured
+ */
+static int32_t spi_init_ps(struct spi_desc *desc,
+			   const struct spi_init_param *param)
+{
+#ifdef XSPIPS_H
+	int32_t				ret;
+	struct xil_spi_desc 		*xdesc;
+	struct xil_spi_init_param	*xinit;
+	const uint32_t			prescaler_default = XSPIPS_CLK_PRESCALE_64;
+	const uint32_t			prescaler_min = XSPIPS_CLK_PRESCALE_4;
+	const uint32_t			prescaler_max = XSPIPS_CLK_PRESCALE_256;
+	uint32_t			prescaler = 0u;
+	uint32_t			input_clock = 0u;
+
+	xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc));
+	if(!xdesc) {
+		free(xdesc);
+		return FAILURE;
+	}
+
+	desc->extra = xdesc;
+	xinit = param->extra;
+	xdesc->type = xinit->type;
+	xdesc->flags = xinit->flags;
+
+	xdesc->instance = (XSpiPs*)malloc(sizeof(XSpiPs));
+	if(!xdesc->instance)
+		goto ps_error;
+
+	xdesc->config = XSpiPs_LookupConfig(param->device_id);
+	if(xdesc->config == NULL)
+		goto ps_error;
+
+	ret = XSpiPs_CfgInitialize(xdesc->instance,
+				   xdesc->config,
+				   ((XSpiPs_Config*)xdesc->config)
+				   ->BaseAddress);
+	if(ret != SUCCESS)
+		goto ps_error;
+
+	switch (param->device_id) {
+#if (SPI_NUM_INSTANCES >= 1)
+	case 0:
+		input_clock = SPI_CLK_FREQ_HZ(0);
+		break;
+#endif
+#if (SPI_NUM_INSTANCES >= 2)
+	case 1:
+		input_clock = SPI_CLK_FREQ_HZ(1);
+		break;
+#endif
+	default:
+		goto ps_error;
+	};
+
+	if (desc->max_speed_hz != 0u) {
+		uint32_t div = input_clock / desc->max_speed_hz;
+		uint32_t rem = input_clock % desc->max_speed_hz;
+		uint32_t po2 = !(div & (div - 1)) && !rem;
+
+		// find the power of two just higher than div and
+		// store the exponent in prescaler
+		while(div) {
+			prescaler += 1;
+			div >>= 1u;
+		}
+
+		// this exponent - 1 is needed because of the way
+		// xilinx stores it into registers
+		if (prescaler)
+			prescaler -= 1;
+
+		// this exponent - 1 is needed when initial div was
+		// precisely a power of two
+		if (prescaler && po2)
+			prescaler -= 1;
+
+		if (prescaler < prescaler_min)
+			prescaler = prescaler_min;
+
+		if (prescaler > prescaler_max)
+			prescaler = prescaler_max;
+	} else
+		prescaler = prescaler_default;
+
+	ret = XSpiPs_SetClkPrescaler(xdesc->instance, prescaler);
+
+	if(ret != SUCCESS)
+		goto ps_error;
+
+	return SUCCESS;
+
+ps_error:
+	free(xdesc->instance);
+	free(xdesc);
+#endif
+	return FAILURE;
+}
+
+/**
+ * @brief Initialize the SPI communication peripheral.
+ * @param desc - The SPI descriptor.
+ * @param param - The structure that contains the SPI parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_spi_init(struct spi_desc **desc,
+		     const struct spi_init_param *param)
+{
+	int32_t				ret;
+	enum xil_spi_type		*spi_type;
+
+	if (!param) {
+		return FAILURE;
+	}
+
+	*desc = malloc(sizeof(**desc));
+	if(! *desc) {
+		free(*desc);
+		return FAILURE;
+	}
+
+	spi_type = param->extra;
+
+	if(!spi_type)
+		goto init_error;
+
+	(*desc)->max_speed_hz = param->max_speed_hz;
+	(*desc)->mode = param->mode;
+	(*desc)->bit_order = param->bit_order;
+	(*desc)->chip_select = param->chip_select;
+
+	switch (*spi_type) {
+	case SPI_PL:
+		ret = spi_init_pl(*desc, param);
+		break;
+	case SPI_PS:
+		ret = spi_init_ps(*desc, param);
+		break;
+
+	default:
+		goto init_error;
+		break;
+	}
+
+	if (ret != SUCCESS) {
+init_error:
+		free(*desc);
+
+		return FAILURE;
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Free the resources allocated by spi_init().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_spi_remove(struct spi_desc *desc)
+{
+#ifdef XSPI_H
+	int32_t				ret;
+#endif
+	struct xil_spi_desc	*xdesc = NULL;
+	enum xil_spi_type	*spi_type;
+
+	spi_type = desc->extra;
+
+	if(!spi_type)
+		return FAILURE;
+
+	switch (*spi_type ) {
+	case SPI_PL:
+#ifdef XSPI_H
+		xdesc = desc->extra;
+
+		if(!xdesc)
+			return FAILURE;
+
+		ret = XSpi_Stop((XSpi *)(xdesc->instance));
+		if(ret != SUCCESS)
+			goto error;
+#endif
+		break;
+	case SPI_PS:
+#ifdef XSPIPS_H
+		xdesc = desc->extra;
+
+		if(!xdesc)
+			return FAILURE;
+#endif
+		break;
+
+		/* Intended fallthrough */
+#ifdef XSPI_H
+error:
+#endif
+	default:
+		return FAILURE;
+	}
+
+	if(xdesc)
+		free(xdesc->instance);
+	free(desc->extra);
+	free(desc);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Write and read data to/from SPI.
+ * @param desc - The SPI descriptor.
+ * @param data - The buffer with the transmitted/received data.
+ * @param bytes_number - Number of bytes to write/read.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_spi_write_and_read(struct spi_desc *desc,
+			       uint8_t *data,
+			       uint16_t bytes_number)
+{
+	int32_t			ret;
+#ifdef XSPI_H
+	uint32_t		ctrl_reg;
+#endif
+	struct xil_spi_desc	*xdesc;
+	enum xil_spi_type	*spi_type;
+
+	ret = FAILURE;
+
+	spi_type = desc->extra;
+
+	if(!spi_type)
+		return FAILURE;
+
+	xdesc = desc->extra;
+
+	switch (*spi_type) {
+	case SPI_PL:
+#ifdef XSPI_H
+		ret = XSpi_SetOptions(xdesc->instance,
+				      XSP_MASTER_OPTION |
+				      ((desc->mode & SPI_CPOL) ?
+				       XSP_CLK_ACTIVE_LOW_OPTION : 0) |
+				      ((desc->mode & SPI_CPHA) ?
+				       XSP_CLK_PHASE_1_OPTION : 0));
+		if (ret != SUCCESS)
+			goto error;
+
+		ctrl_reg = XSpi_GetControlReg(((XSpi*)xdesc->instance));
+		if (desc->bit_order == SPI_BIT_ORDER_LSB_FIRST)
+			ctrl_reg |= XSP_CR_LSB_MSB_FIRST_MASK;
+		else
+			ctrl_reg &= ~ XSP_CR_LSB_MSB_FIRST_MASK;
+		XSpi_SetControlReg(((XSpi*)xdesc->instance), ctrl_reg);
+
+		ret = XSpi_SetSlaveSelect(xdesc->instance,
+					  0x01 << desc->chip_select);
+		if (ret != SUCCESS)
+			goto error;
+
+		ret = XSpi_Transfer(xdesc->instance,
+				    data,
+				    data,
+				    bytes_number);
+		if (ret != SUCCESS)
+			goto error;
+#endif
+		break;
+	case SPI_PS:
+#ifdef XSPIPS_H
+		ret = XSpiPs_SetOptions(xdesc->instance,
+					XSPIPS_MASTER_OPTION |
+					((xdesc->flags & SPI_CS_DECODE) ?
+					 XSPIPS_DECODE_SSELECT_OPTION : 0) |
+					XSPIPS_FORCE_SSELECT_OPTION |
+					((desc->mode & SPI_CPOL) ?
+					 XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) |
+					((desc->mode & SPI_CPHA) ?
+					 XSPIPS_CLK_PHASE_1_OPTION : 0));
+		if (ret != SUCCESS)
+			goto error;
+
+		ret = XSpiPs_SetSlaveSelect(xdesc->instance,
+					    desc->chip_select);
+		if (ret != SUCCESS)
+			goto error;
+		ret = XSpiPs_PolledTransfer(xdesc->instance,
+					    data,
+					    data,
+					    bytes_number);
+		if (ret != SUCCESS)
+			goto error;
+		ret = XSpiPs_SetSlaveSelect(xdesc->instance, SPI_DEASSERT_CURRENT_SS);
+		if (ret != SUCCESS)
+			goto error;
+#endif
+		break;
+error:
+	default:
+		return FAILURE;
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Xilinx platform specific SPI platform ops structure
+ */
+const struct spi_platform_ops xil_spi_ops = {
+	.init = &xil_spi_init,
+	.write_and_read = &xil_spi_write_and_read,
+	.write_and_read_3wire = NULL, // Not support.
+	.remove = &xil_spi_remove
+};

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/drivers/platform/xilinx_spi_pl.c

@@ -0,0 +1,531 @@
+/*******************************************************************************
+ *   @file   xilinx/xilinx_spi_pl.c
+ *   @brief  Driver for spi pl device using registers
+ *   @author Mihail Chindris ([email protected])
+********************************************************************************
+ * Copyright 2021(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <xparameters.h>
+
+#ifdef XPAR_XSPI_NUM_INSTANCES
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <xspi.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "spi.h"
+#include "error.h"
+#include "delay.h"
+#include "util.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define XPS_TYPE_WRITE		0x1
+#define XPS_TYPE_READ		0x2
+#define XSP_DEFAULT_SR_VALUE	0x25
+#define XSP_DUMMY_DATA		0xFF
+
+/*
+ * Used to store current spi device configuration in order to not update it for
+ * each spi transaction if not needed.
+ */
+static struct spi_desc g_spi_desc[XPAR_XSPI_NUM_INSTANCES];
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/* Xilinx PL spi specific data */
+struct xspi_desc {
+	uint32_t base_addr;
+	uint32_t disable_slaves_mask;
+	uint32_t fifo_depth;
+	uint8_t  cs_asserted;
+};
+
+/* Structure used to iterate over SPI messages */
+struct msg_iter {
+	struct spi_msg	*msgs;
+	uint32_t	len;
+	uint32_t	i;
+	uint32_t	buff_i;
+	uint8_t		is_wr;
+};
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/* Read device register */
+static inline uint32_t _read(struct xspi_desc *xdesc, uint32_t reg)
+{
+	return Xil_In32(xdesc->base_addr + reg);
+}
+
+/* Write device register */
+static inline void _write(struct xspi_desc *xdesc, uint32_t reg, uint32_t val)
+{
+	Xil_Out32(xdesc->base_addr + reg, val);
+}
+
+/* Update device register. Only bits set to 1 in mask will be modified */
+static inline void _wr_mask(struct xspi_desc *xdesc, uint32_t reg,
+			    uint32_t val, uint32_t mask)
+{
+	uint32_t tmp;
+
+	tmp = _read(xdesc, reg);
+	tmp &= ~mask;
+	tmp |= val & mask;
+	_write(xdesc, reg, tmp);
+}
+
+/* Update spi device configuration if needed */
+static void _update_mode(struct spi_desc *desc)
+{
+	uint32_t		val;
+	uint32_t		mask;
+
+	if (desc->mode == g_spi_desc[desc->device_id].mode &&
+	    desc->bit_order == g_spi_desc[desc->device_id].bit_order)
+		return ;
+
+	/* Update mode */
+	val = desc->mode | SPI_CPOL ? XSP_CR_CLK_POLARITY_MASK : 0;
+	val |= desc->mode | SPI_CPHA ? XSP_CR_CLK_PHASE_MASK : 0;
+	mask = XSP_CR_CLK_POLARITY_MASK | XSP_CR_CLK_PHASE_MASK;
+
+	val |= desc->bit_order == SPI_BIT_ORDER_LSB_FIRST ?
+	       XSP_CR_LSB_MSB_FIRST_MASK : 0;
+	mask |= XSP_CR_LSB_MSB_FIRST_MASK;
+
+	_wr_mask(desc->extra, XSP_CR_OFFSET, val, mask);
+	g_spi_desc[desc->device_id] = *desc;
+}
+
+/* Configure SPI PL device */
+static int32_t _xil_spi_init_dev(struct xspi_desc *xdesc)
+{
+	uint32_t val;
+
+	/* Software reset */
+	_write(xdesc, XSP_SRR_OFFSET, XSP_SRR_RESET_MASK);
+	mdelay(1);
+
+	/* Check if success reset */
+	val = _read(xdesc, XSP_SR_OFFSET);
+	if (val != XSP_DEFAULT_SR_VALUE)
+		return -ENODEV;
+
+	/* Disable interrupts. Drivers only works with pooled mode */
+	_write(xdesc, XSP_IIER_OFFSET, 0);
+
+	/* Deasert chip selects */
+	_write(xdesc, XSP_SSR_OFFSET, 0xFFFFFFFF);
+
+	/* Get fifo depth */
+	while (!(_read(xdesc, XSP_SR_OFFSET) & XSP_SR_TX_FULL_MASK))
+		_write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA);
+	xdesc->fifo_depth = _read(xdesc, XSP_TFO_OFFSET) + 1;
+
+	/* Configure spi device */
+	val = XSP_CR_ENABLE_MASK |
+	      XSP_CR_MANUAL_SS_MASK |
+	      XSP_CR_TXFIFO_RESET_MASK |
+	      XSP_CR_RXFIFO_RESET_MASK |
+	      XSP_CR_MASTER_MODE_MASK |
+	      XSP_CR_TRANS_INHIBIT_MASK;
+
+	_write(xdesc, XSP_CR_OFFSET, val);
+
+	return SUCCESS;
+}
+
+/* Initialize spi_desc structure and device */
+static int32_t xil_spi_init_pl(struct spi_desc **desc,
+			       const struct spi_init_param *param)
+{
+	struct spi_desc		*ldesc;
+	struct xspi_desc	*xdesc;
+	int32_t			err;
+	XSpi_Config		*cfg;
+
+	if (!desc || !param || param->device_id >= XPAR_XSPI_NUM_INSTANCES)
+		return -EINVAL;
+
+	cfg = XSpi_LookupConfig(param->device_id);
+	if (!cfg)
+		return -EINVAL;
+
+	if (param->chip_select > cfg->NumSlaveBits)
+		return -EINVAL;
+
+	ldesc = (struct spi_desc *)calloc(1, sizeof(*ldesc));
+	if (!ldesc)
+		return -ENOMEM;
+
+	xdesc = (struct xspi_desc *)calloc(1, sizeof(*xdesc));
+	if (!xdesc) {
+		err = -ENOMEM;
+		goto error;
+	}
+
+	ldesc->bit_order = param->bit_order;
+	ldesc->chip_select = param->chip_select;
+	ldesc->mode = param->mode;
+	xdesc->base_addr = cfg->BaseAddress;
+	xdesc->disable_slaves_mask = (1 << cfg->NumSlaveBits) - 1;
+	xdesc->cs_asserted = 0;
+
+	err = _xil_spi_init_dev(xdesc);
+	if (IS_ERR_VALUE(err))
+		goto error;
+
+	ldesc->extra = xdesc;
+	*desc = ldesc;
+
+	return SUCCESS;
+
+error:
+	free(xdesc);
+	free(ldesc);
+
+	return err;
+}
+
+/* Remove allocated resources */
+static int32_t xil_spi_remove_pl(struct spi_desc *desc)
+{
+	if (!desc)
+		return -EINVAL;
+
+	free(desc->extra);
+	free(desc);
+
+	return SUCCESS;
+}
+
+/*
+ * Fill fifo until fifo is full or no more data available.
+ * Return the number of written bytes.
+ */
+static uint32_t _wr_fifo(struct xspi_desc *xdesc, uint8_t *data,
+			 uint32_t len)
+{
+	uint32_t i;
+	uint32_t to_write;
+	uint32_t tx_available;
+
+	tx_available = xdesc->fifo_depth - _read(xdesc, XSP_TFO_OFFSET);
+	to_write = min(tx_available, len);
+	for (i = 0; i < to_write; ++i)
+		if (data)
+			_write(xdesc, XSP_DTR_OFFSET, data[i]);
+		else
+			_write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA);
+
+	return to_write;
+}
+
+/*
+ * Read fifo until fifo is empty or no more buffer available to read into
+ * Returns the number of read bytes
+ */
+static uint32_t _rd_fifo(struct xspi_desc *xdesc, uint8_t *data,
+			 uint32_t len)
+{
+	uint32_t rx_available;
+	uint32_t to_read;
+	uint32_t tmp;
+	uint32_t i;
+
+	tmp = _read(xdesc, XSP_SR_OFFSET);
+	if (tmp & XSP_SR_RX_EMPTY_MASK)
+		return 0;
+
+	rx_available = _read(xdesc, XSP_RFO_OFFSET) + 1;
+	to_read = min(rx_available, len);
+	for (i = 0; i < to_read; ++i) {
+		tmp = _read(xdesc, XSP_DRR_OFFSET);
+		if (data)
+			data[i] = tmp;
+	}
+
+	return to_read;
+}
+
+/* If start is 0 stop transfer, else start it.
+ * CS will be asserted if needed. If different CS othere than the one needed
+ * is asserted. Deassert it and assert correct one */
+static void _xil_spi_start_transfer(struct spi_desc *desc, uint8_t start)
+{
+	struct xspi_desc	*xdesc;
+
+	xdesc = desc->extra;
+	if (start) {
+		if (xdesc->cs_asserted) {
+			if (desc->chip_select ==
+			    g_spi_desc[desc->device_id].chip_select)
+				return ;
+			else
+				/* Stop transfer to start again with new CS */
+				_xil_spi_start_transfer(desc, 0);
+		}
+		_write(xdesc, XSP_SSR_OFFSET, ~(1 << desc->chip_select));
+		_wr_mask(xdesc, XSP_CR_OFFSET, 0, XSP_CR_TRANS_INHIBIT_MASK);
+	} else {
+		_wr_mask(xdesc, XSP_CR_OFFSET, XSP_CR_TRANS_INHIBIT_MASK,
+			 XSP_CR_TRANS_INHIBIT_MASK);
+		_write(xdesc, XSP_SSR_OFFSET, xdesc->disable_slaves_mask);
+	}
+	xdesc->cs_asserted = start;
+}
+
+
+/* SPI polled transfer */
+static int32_t xil_spi_write_and_read_pl(struct spi_desc *desc, uint8_t *data,
+		uint16_t bytes_number)
+{
+	struct xspi_desc	*xdesc;
+	uint32_t		rx;
+	uint32_t		tx;
+
+	if (!desc || !desc->extra)
+		return -EINVAL;
+
+	xdesc = desc->extra;
+	_update_mode(desc);
+
+	_xil_spi_start_transfer(desc, 1);
+	rx = 0;
+	tx = 0;
+	while (rx < bytes_number) {
+		if (tx < bytes_number)
+			tx += _wr_fifo(xdesc, data + tx, bytes_number - tx);
+		rx += _rd_fifo(xdesc, data + rx, bytes_number - rx);
+	}
+	_xil_spi_start_transfer(desc, 0);
+
+	return SUCCESS;
+}
+
+/* Get type of message. It can be READ, WRITE or both */
+static uint32_t _get_msg_type(struct spi_msg *msg)
+{
+	uint32_t	type;
+
+	type = 0;
+	if (msg->tx_buff)
+		type |= XPS_TYPE_WRITE;
+	if (msg->rx_buff)
+		type |= XPS_TYPE_READ;
+
+	return type;
+}
+
+/* Get information based on current iterator position */
+static void _get_data(struct msg_iter *it, uint8_t **buff, uint32_t *len,
+		      uint32_t *type)
+{
+	struct spi_msg *msg;
+
+	if (it->i == it->len) {
+		*len = 0;
+		return ;
+	}
+
+	msg = it->msgs + it->i;
+	if (it->is_wr)
+		*buff = msg->tx_buff;
+	else
+		*buff = msg->rx_buff;
+
+	if (*buff)
+		*buff += it->buff_i;
+
+	*len = msg->bytes_number - it->buff_i;
+	if (type)
+		*type = _get_msg_type(msg);
+}
+
+/*
+ * Increment iterator position with desired length.
+ * If the new position has a different message type, new_type will be set to 1
+ * If a CS change is needed, cs_change is set
+ */
+static void _increment_iter(struct msg_iter *it, uint32_t len,
+			    uint8_t *cs_change, uint8_t *new_type)
+{
+	struct spi_msg	*msg;
+	uint32_t	type;
+	uint32_t	extra_len;
+
+	if (!len)
+		return ;
+
+	*cs_change = 0;
+	*new_type = 0;
+	msg = it->msgs + it->i;
+	if (it->buff_i + len > msg->bytes_number)
+		extra_len = it->buff_i + len - msg->bytes_number;
+	else
+		extra_len = 0;
+	len -= extra_len;
+	it->buff_i += len;
+	if (it->buff_i == msg->bytes_number) {
+		type = _get_msg_type(msg);
+		++it->i;
+		it->buff_i = 0;
+		if (cs_change && msg->cs_change)
+			*cs_change = 1;
+		if (new_type)
+			if (it->i == it->len ||
+			    type != _get_msg_type(it->msgs + it->i))
+				*new_type = 1;
+	}
+	if (extra_len)
+		_increment_iter(it, extra_len, cs_change, new_type);
+}
+
+/*
+ * SPI polling transfer of multiple messages.
+ */
+static int32_t xil_spi_transfer_pl(struct spi_desc *desc, struct spi_msg *msgs,
+				   uint32_t len)
+
+{
+	struct xspi_desc	*xdesc;
+	uint8_t			cs_change;
+	uint8_t			new_type;
+	struct msg_iter		rx = {.msgs = msgs, .len = len, .is_wr = 0};
+	struct msg_iter		tx = {.msgs = msgs, .len = len, .is_wr = 1};
+	uint8_t			*buff;
+	uint32_t		bytes;
+	uint32_t		type;
+	/* Bytes to increment rx when only a write transaction is executed */
+	uint32_t		to_inc_rx;
+	/* Difference between rx and tx iterators in bytes */
+	uint32_t		tx_advance;
+	/* Save bytes sent during a write loop */
+	uint32_t		tx_sent;
+	/* Used to loop if need to empty the RX FIFO */
+	uint32_t		loop;
+
+	if (!desc || !desc->extra)
+		return -EINVAL;
+
+	xdesc = desc->extra;
+	_update_mode(desc);
+
+	tx_advance = 0;
+	to_inc_rx = 0;
+	buff = NULL;
+	type = 0;
+	do {
+		_xil_spi_start_transfer(desc, 1);
+
+		tx_sent = 0;
+		/* Writing loop */
+		do {
+			_get_data(&tx, &buff, &bytes, &type);
+			if (type & XPS_TYPE_READ)
+				/*
+				 * Do not write more bytes than fifo_depth if
+				 * they haven't been read.
+				 */
+				bytes = min(bytes,
+					    xdesc->fifo_depth - tx_advance);
+			bytes = _wr_fifo(xdesc, buff, bytes);
+			tx_sent += bytes;
+			_increment_iter(&tx, bytes, &cs_change, &new_type);
+			tx_advance += bytes;
+		} while (!cs_change && !new_type && bytes);
+
+		if (type & XPS_TYPE_READ) {
+			loop = 1;
+			/*
+			 * Loop only when no more data to write otherwise read
+			 * only available data.
+			 */
+			while (loop) {
+				if (!new_type)
+					loop = 0;
+				_get_data(&rx, &buff, &bytes, NULL);
+				bytes = _rd_fifo(xdesc, buff, bytes);
+				_increment_iter(&rx, bytes, &cs_change, &new_type);
+				tx_advance -= bytes;
+				if (loop && new_type)
+					break;
+			}
+		} else {
+			/* Clean RX FIFO if it was only a WRITE message */
+			to_inc_rx += tx_sent;
+			if (new_type) {
+				/* Wait for TX to be sent */
+				while (!(_read(xdesc, XSP_SR_OFFSET) &
+					 XSP_SR_TX_EMPTY_MASK))
+					;
+				/* Reset fifo. Only write was performed */
+				_wr_mask(xdesc, XSP_CR_OFFSET,
+					 XSP_CR_RXFIFO_RESET_MASK,
+					 XSP_CR_RXFIFO_RESET_MASK);
+
+				_increment_iter(&rx, to_inc_rx, NULL, NULL);
+				tx_advance -= to_inc_rx;
+				to_inc_rx = 0;
+			}
+		}
+
+		if ((cs_change && rx.i != len) || (!cs_change && rx.i == len))
+			_xil_spi_start_transfer(desc, 0);
+	} while (rx.i < len);
+
+	return SUCCESS;
+}
+
+const struct spi_platform_ops xil_spi_reg_ops_pl = {
+	.init = xil_spi_init_pl,
+	.remove = xil_spi_remove_pl,
+	.write_and_read = xil_spi_write_and_read_pl,
+	.write_and_read_3wire = NULL, // Not support.
+	.transfer = xil_spi_transfer_pl
+};
+
+#endif // XPAR_XSPI_NUM_INSTANCES

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/include/axi_io.h

@@ -0,0 +1,59 @@
+/***************************************************************************//**
+ *   @file   axi_io.h
+ *   @brief  Header file of AXI IO.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef AXI_IO_H_
+#define AXI_IO_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* AXI IO Read data */
+int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data);
+
+/* AXI IO Write data */
+int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data);
+
+#endif // AXI_IO_H_

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/include/delay.h

@@ -0,0 +1,59 @@
+/***************************************************************************//**
+ *   @file   delay.h
+ *   @brief  Header file of Delay functions
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef DELAY_H_
+#define DELAY_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Generate microseconds delay. */
+void udelay(uint32_t usecs);
+
+/* Generate miliseconds delay. */
+void mdelay(uint32_t msecs);
+
+#endif // DELAY_H_

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/include/error.h

@@ -0,0 +1,67 @@
+/***************************************************************************//**
+ *   @file   error.h
+ *   @brief  Error codes definition
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef ERROR_H_
+#define ERROR_H_
+
+#include <errno.h>
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#ifdef SUCCESS
+#undef SUCCESS
+#endif
+#define SUCCESS		0
+#ifdef FAILURE
+#undef FAILURE
+#endif
+#define FAILURE		-1
+
+#ifndef __ELASTERROR
+#define __ELASTERROR 2000
+#endif
+
+#define EOVERRUN	(__ELASTERROR + 1) /* Circular buffer overrun */
+
+
+#define IS_ERR_VALUE(x)	((x) < 0)
+
+#endif // ERROR_H_

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/include/gpio.h

@@ -0,0 +1,165 @@
+/***************************************************************************//**
+ *   @file   gpio.h
+ *   @brief  Header file of GPIO Interface
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef GPIO_H_
+#define GPIO_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define GPIO_OUT	0x01
+#define GPIO_IN		0x00
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @struct gpio_platform_ops
+ * @brief Structure holding gpio function pointers that point to the platform
+ * specific function
+ */
+struct gpio_platform_ops ;
+
+/**
+ * @struct gpio_init_param
+ * @brief Structure holding the parameters for GPIO initialization.
+ */
+typedef struct gpio_init_param {
+	/** GPIO number */
+	int32_t		number;
+	/** GPIO platform specific functions */
+	const struct gpio_platform_ops *platform_ops;
+	/** GPIO extra parameters (device specific) */
+	void		*extra;
+} gpio_init_param;
+
+/**
+ * @struct gpio_desc
+ * @brief Structure holding the GPIO descriptor.
+ */
+typedef struct gpio_desc {
+	/** GPIO number */
+	int32_t		number;
+	/** GPIO platform specific functions */
+	const struct gpio_platform_ops *platform_ops;
+	/** GPIO extra parameters (device specific) */
+	void		*extra;
+} gpio_desc;
+
+/**
+ * @enum gpio_values
+ * @brief Enum that holds the possible output states of a GPIO.
+ */
+enum gpio_values {
+	/** GPIO logic low */
+	GPIO_LOW,
+	/** GPIO logic high */
+	GPIO_HIGH,
+	/** GPIO high impedance */
+	GPIO_HIGH_Z
+};
+
+/**
+ * @struct gpio_platform_ops
+ * @brief Structure holding gpio function pointers that point to the platform
+ * specific function
+ */
+struct gpio_platform_ops {
+	/** gpio initialization function pointer */
+	int32_t (*gpio_ops_get)(struct gpio_desc **, const struct gpio_init_param *);
+	/** gpio optional descriptor function pointer */
+	int32_t (*gpio_ops_get_optional)(struct gpio_desc **,
+					 const struct gpio_init_param *);
+	/** gpio remove function pointer */
+	int32_t (*gpio_ops_remove)(struct gpio_desc *);
+	/** gpio direction input function pointer */
+	int32_t (*gpio_ops_direction_input)(struct gpio_desc *);
+	/** gpio direction output function pointer */
+	int32_t (*gpio_ops_direction_output)(struct gpio_desc *, uint8_t);
+	/** gpio get direction function pointer */
+	int32_t (*gpio_ops_get_direction)(struct gpio_desc *, uint8_t *);
+	/** gpio set value function pointer */
+	int32_t (*gpio_ops_set_value)(struct gpio_desc *, uint8_t);
+	/** gpio get value function pointer */
+	int32_t (*gpio_ops_get_value)(struct gpio_desc *, uint8_t *);
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Obtain the GPIO decriptor. */
+int32_t gpio_get(struct gpio_desc **desc,
+		 const struct gpio_init_param *param);
+
+/* Obtain optional GPIO descriptor. */
+int32_t gpio_get_optional(struct gpio_desc **desc,
+			  const struct gpio_init_param *param);
+
+/* Free the resources allocated by gpio_get() */
+int32_t gpio_remove(struct gpio_desc *desc);
+
+/* Enable the input direction of the specified GPIO. */
+int32_t gpio_direction_input(struct gpio_desc *desc);
+
+/* Enable the output direction of the specified GPIO. */
+int32_t gpio_direction_output(struct gpio_desc *desc,
+			      uint8_t value);
+
+/* Get the direction of the specified GPIO. */
+int32_t gpio_get_direction(struct gpio_desc *desc,
+			   uint8_t *direction);
+
+/* Set the value of the specified GPIO. */
+int32_t gpio_set_value(struct gpio_desc *desc,
+		       uint8_t value);
+
+/* Get the value of the specified GPIO. */
+int32_t gpio_get_value(struct gpio_desc *desc,
+		       uint8_t *value);
+
+#endif // GPIO_H_

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/include/irq.h

@@ -0,0 +1,188 @@
+/***************************************************************************//**
+ *   @file   irq.h
+ *   @brief  Header file of IRQ interface.
+ *   @author Cristian Pop ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef IRQ_H_
+#define IRQ_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum irq_uart_event_e
+ * @brief Possible events for uart interrupt
+ */
+enum irq_uart_event_e {
+	/** Write operation finalized */
+	IRQ_WRITE_DONE,
+	/** Read operation finalized */
+	IRQ_READ_DONE,
+	/** An error occurred */
+	IRQ_ERROR
+};
+
+enum irq_trig_level {
+	IRQ_LEVEL_LOW,
+	IRQ_LEVEL_HIGH,
+	IRQ_EDGE_FALLING,
+	IRQ_EDGE_RISING,
+	IRQ_EDGE_BOTH
+};
+
+/**
+ * @struct irq_platform_ops
+ * @brief Structure holding IRQ function pointers that point to the platform
+ * specific function
+ */
+struct irq_platform_ops ;
+
+/**
+ * @struct irq_init_param
+ * @brief Structure holding the initial parameters for Interrupt Request.
+ */
+struct irq_init_param {
+	/** Interrupt request controller ID. */
+	uint32_t	irq_ctrl_id;
+	/** Platform specific IRQ platform ops structure. */
+	const struct irq_platform_ops *platform_ops;
+	/** IRQ extra parameters (device specific) */
+	void		*extra;
+};
+
+/**
+ * @struct irq_desc
+ * @brief Structure for Interrupt Request descriptor.
+ */
+struct irq_ctrl_desc {
+	/** Interrupt request controller ID. */
+	uint32_t	irq_ctrl_id;
+	/** Platform specific IRQ platform ops structure. */
+	const struct irq_platform_ops *platform_ops;
+	/** IRQ extra parameters (device specific) */
+	void		*extra;
+};
+
+/**
+ * @struct callback_desc
+ * @brief Structure describing a callback to be registered
+ */
+struct callback_desc {
+	/**
+	 * Callback to be called when the event an event occurs
+	 *  @param ctx - Same as \ref callback_desc.ctx
+	 *  @param event - Event that generated the callback
+	 *  @param extra - Platform specific data
+	 */
+	void (*callback)(void *ctx, uint32_t event, void *extra);
+	/** Parameter to be passed when the callback is called */
+	void *ctx;
+	/** Platform specific configuration for a callback */
+	void *config;
+};
+
+/**
+ * @struct irq_platform_ops
+ * @brief Structure holding IRQ function pointers that point to the platform
+ * specific function
+ */
+struct irq_platform_ops {
+	/** Initialize a interrupt controller peripheral. */
+	int32_t (*init)(struct irq_ctrl_desc **desc,
+			const struct irq_init_param *param);
+	/** Register a callback to handle the irq events */
+	int32_t (*register_callback)(struct irq_ctrl_desc *desc, uint32_t irq_id,
+				     struct callback_desc *callback_desc);
+	/** Unregisters a generic IRQ handling function */
+	int32_t (*unregister)(struct irq_ctrl_desc *desc, uint32_t irq_id);
+	/** Global interrupt enable */
+	int32_t (*global_enable)(struct irq_ctrl_desc *desc);
+	/** Global interrupt disable */
+	int32_t (*global_disable)(struct irq_ctrl_desc *desc);
+	/** Set interrupt trigger level. */
+	int32_t (*trigger_level_set)(struct irq_ctrl_desc *desc, uint32_t irq_id,
+				     enum irq_trig_level trig);
+	/** Enable specific interrupt */
+	int32_t (*enable)(struct irq_ctrl_desc *desc, uint32_t irq_id);
+	/** Disable specific interrupt */
+	int32_t (*disable)(struct irq_ctrl_desc *desc, uint32_t irq_id);
+	/** IRQ remove function pointer */
+	int32_t (*remove)(struct irq_ctrl_desc *desc);
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Initialize a interrupt controller peripheral. */
+int32_t irq_ctrl_init(struct irq_ctrl_desc **desc,
+		      const struct irq_init_param *param);
+
+/* Free the resources allocated by irq_ctrl_init(). */
+int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc);
+
+/* Register a callback to handle the irq events */
+int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
+			      struct callback_desc *callback_desc);
+
+/* Unregisters a generic IRQ handling function */
+int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id);
+
+/* Global interrupt enable */
+int32_t irq_global_enable(struct irq_ctrl_desc *desc);
+
+/* Global interrupt disable */
+int32_t irq_global_disable(struct irq_ctrl_desc *desc);
+
+/* Set interrupt trigger level. */
+int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
+			      enum irq_trig_level trig);
+
+/* Enable specific interrupt */
+int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id);
+
+/* Disable specific interrupt */
+int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id);
+
+#endif // IRQ_H_

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/include/spi.h

@@ -0,0 +1,194 @@
+/***************************************************************************//**
+ *   @file   spi.h
+ *   @brief  Header file of SPI Interface
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef SPI_H_
+#define SPI_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define	SPI_CPHA	0x01
+#define	SPI_CPOL	0x02
+#define	SPI_3WIRE	0x04
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum spi_mode
+ * @brief SPI configuration for clock phase and polarity.
+ */
+typedef enum spi_mode {
+	/** Data on rising, shift out on falling */
+	SPI_MODE_0 = (0 | 0),
+	/** Data on falling, shift out on rising */
+	SPI_MODE_1 = (0 | SPI_CPHA),
+	/** Data on falling, shift out on rising */
+	SPI_MODE_2 = (SPI_CPOL | 0),
+	/** Data on rising, shift out on falling */
+	SPI_MODE_3 = (SPI_CPOL | SPI_CPHA),
+	/** Data on rising, shift out on falling */
+	SPI_MODE_4 = SPI_3WIRE
+} spi_mode;
+
+/**
+ * @enum spi_bit_order
+ * @brief SPI configuration for bit order (MSB/LSB).
+ */
+typedef enum spi_bit_order {
+	/** Most-significant bit (MSB) first */
+	SPI_BIT_ORDER_MSB_FIRST = 0,
+	/** Least-significant bit (LSB) first */
+	SPI_BIT_ORDER_LSB_FIRST = 1,
+} spi_bit_order;
+
+/**
+ * @struct spi_msg_list
+ * @brief List item describing a SPI transfer
+ */
+struct spi_msg {
+	/** Buffer with data to send. If NULL, 0x00 will be sent */
+	uint8_t			*tx_buff;
+	/** Buffer where to store data. If NULL, incoming data won't be saved */
+	uint8_t			*rx_buff;
+	/** Length of buffers. Must have equal size. */
+	uint32_t		bytes_number;
+	/** If set, CS will be deasserted after the transfer */
+	uint8_t			cs_change;
+};
+
+/**
+ * @struct spi_platform_ops
+ * @brief Structure holding SPI function pointers that point to the platform
+ * specific function
+ */
+struct spi_platform_ops ;
+
+/**
+ * @struct spi_init_param
+ * @brief Structure holding the parameters for SPI initialization
+ */
+typedef struct spi_init_param {
+	/** Device ID */
+	uint32_t	device_id;
+	/** maximum transfer speed */
+	uint32_t	max_speed_hz;
+	/** SPI chip select */
+	uint8_t		chip_select;
+	/** SPI mode */
+	enum spi_mode	mode;
+	/** SPI bit order */
+	enum spi_bit_order	bit_order;
+	const struct spi_platform_ops *platform_ops;
+	/**  SPI extra parameters (device specific) */
+	void		*extra;
+} spi_init_param;
+
+/**
+ * @struct spi_desc
+ * @brief Structure holding SPI descriptor.
+ */
+typedef struct spi_desc {
+	/** Device ID */
+	uint32_t	device_id;
+	/** maximum transfer speed */
+	uint32_t	max_speed_hz;
+	/** SPI chip select */
+	uint8_t		chip_select;
+	/** SPI mode */
+	enum spi_mode	mode;
+	/** SPI bit order */
+	enum spi_bit_order	bit_order;
+	const struct spi_platform_ops *platform_ops;
+	/**  SPI extra parameters (device specific) */
+	void		*extra;
+} spi_desc;
+
+/**
+ * @struct spi_platform_ops
+ * @brief Structure holding SPI function pointers that point to the platform
+ * specific function
+ */
+struct spi_platform_ops {
+	/** SPI initialization function pointer */
+	int32_t (*init)(struct spi_desc **, const struct spi_init_param *);
+	/** SPI write/read function pointer */
+	int32_t (*write_and_read)(struct spi_desc *, uint8_t *, uint16_t);
+	/** SPI write function pointer */
+	int32_t (*write_and_read_3wire)(struct spi_desc *, uint8_t *,uint8_t *,uint16_t, uint16_t);
+	/** Iterate over the spi_msg array and send all messages at once */
+	int32_t (*transfer)(struct spi_desc *, struct spi_msg *, uint32_t);
+	/** SPI remove function pointer */
+	int32_t (*remove)(struct spi_desc *);
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Initialize the SPI communication peripheral. */
+int32_t spi_init(struct spi_desc **desc,
+		 const struct spi_init_param *param);
+
+/* Free the resources allocated by spi_init(). */
+int32_t spi_remove(struct spi_desc *desc);
+
+/* Write and read data to/from SPI. */
+int32_t spi_write_and_read(struct spi_desc *desc,
+			   uint8_t *data,
+			   uint16_t bytes_number);
+int32_t spi_write_and_read_3wire(struct spi_desc *desc,
+			   uint8_t *write_data,
+			   uint8_t *read_data,
+			   uint16_t write_bytes_number,
+			   uint16_t read_bytes_number);
+
+/* Iterate over the spi_msg array and send all messages at once */
+int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len);
+
+
+#endif // SPI_H_

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/include/util.h

@@ -0,0 +1,165 @@
+/***************************************************************************//**
+ *   @file   util.h
+ *   @brief  Implementation of utility functions.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef UTIL_H_
+#define UTIL_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+#define BIT(x)	(1 << (x))
+
+#define ARRAY_SIZE(x) \
+	(sizeof(x) / sizeof((x)[0]))
+
+#define DIV_ROUND_UP(x,y) \
+	(((x) + (y) - 1) / (y))
+#define DIV_ROUND_CLOSEST(x, y) \
+	(((x) + (y) / 2) / (y))
+#define DIV_ROUND_CLOSEST_ULL(x, y) \
+	DIV_ROUND_CLOSEST(x, y)
+
+#define min(x, y) \
+	(((x) < (y)) ? (x) : (y))
+#define min_t(type, x, y) \
+	(type)min((type)(x), (type)(y))
+
+#define max(x, y) \
+	(((x) > (y)) ? (x) : (y))
+#define max_t(type, x, y) \
+	(type)max((type)(x), (type)(y))
+
+#define clamp(val, min_val, max_val) \
+	(max(min((val), (max_val)), (min_val)))
+#define clamp_t(type, val, min_val, max_val) \
+	(type)clamp((type)(val), (type)(min_val), (type)(max_val))
+
+#define swap(x, y) \
+	{typeof(x) _tmp_ = (x); (x) = (y); (y) = _tmp_;}
+
+#define round_up(x,y) \
+		(((x)+(y)-1)/(y))
+
+#define BITS_PER_LONG 32
+
+#define GENMASK(h, l) ({ 					\
+		uint32_t t = (uint32_t)(~0UL);			\
+		t = t << (BITS_PER_LONG - (h - l + 1));		\
+		t = t >> (BITS_PER_LONG - (h + 1));		\
+		t;						\
+})
+
+#define bswap_constant_32(x) \
+	((((x) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >>  8) | \
+	 (((x) & 0x0000ff00) <<  8) | (((x) & 0x000000ff) << 24))
+
+#define bswap_constant_16(x) ((((x) & (uint16_t)0xff00) >> 8) | \
+				 (((x) & (uint16_t)0x00ff) << 8))
+
+#define bit_swap_constant_8(x) \
+	((((x) & 0x80) >> 7) | \
+	 (((x) & 0x40) >> 5) | \
+	 (((x) & 0x20) >> 3) | \
+	 (((x) & 0x10) >> 1) | \
+	 (((x) & 0x08) << 1) | \
+	 (((x) & 0x04) << 3) | \
+	 (((x) & 0x02) << 5) | \
+	 (((x) & 0x01) << 7))
+
+#define U16_MAX		((uint16_t)~0U)
+#define S16_MAX		((int16_t)(U16_MAX>>1))
+
+#define DIV_U64(x, y) (x / y)
+
+#define UNUSED_PARAM(x) ((void)x)
+
+#define shift_right(x, s) ((x) < 0 ? -(-(x) >> (s)) : (x) >> (s))
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+/* Find first set bit in word. */
+uint32_t find_first_set_bit(uint32_t word);
+/* Find last set bit in word. */
+uint32_t find_last_set_bit(uint32_t word);
+/* Locate the closest element in an array. */
+uint32_t find_closest(int32_t val,
+		      const int32_t *array,
+		      uint32_t size);
+/* Shift the value and apply the specified mask. */
+uint32_t field_prep(uint32_t mask, uint32_t val);
+/* Get a field specified by a mask from a word. */
+uint32_t field_get(uint32_t mask, uint32_t word);
+/* Log base 2 of the given number. */
+int32_t log_base_2(uint32_t x);
+/* Find greatest common divisor of the given two numbers. */
+uint32_t greatest_common_divisor(uint32_t a,
+				 uint32_t b);
+/* Calculate best rational approximation for a given fraction. */
+void rational_best_approximation(uint32_t given_numerator,
+				 uint32_t given_denominator,
+				 uint32_t max_numerator,
+				 uint32_t max_denominator,
+				 uint32_t *best_numerator,
+				 uint32_t *best_denominator);
+/* Calculate the number of set bits. */
+uint32_t hweight8(uint32_t word);
+/* Calculate the quotient and the remainder of an integer division. */
+uint64_t do_div(uint64_t* n,
+		uint64_t base);
+/* Unsigned 64bit divide with 64bit divisor and remainder */
+uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor,
+		       uint64_t *remainder);
+/* Unsigned 64bit divide with 32bit divisor with remainder */
+uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder);
+int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder);
+/* Unsigned 64bit divide with 32bit divisor */
+uint64_t div_u64(uint64_t dividend, uint32_t divisor);
+int64_t div_s64(int64_t dividend, int32_t divisor);
+/* Converts from string to int32_t */
+int32_t str_to_int32(const char *str);
+/* Converts from string to uint32_t */
+uint32_t srt_to_uint32(const char *str);
+#endif // UTIL_H_
+

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/adi_noos/util/util.c

@@ -0,0 +1,283 @@
+/***************************************************************************//**
+ *   @file   util.c
+ *   @brief  Implementation of utility functions.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <string.h>
+#include <stdlib.h>
+#include "errno.h"
+#include "../include/util.h"
+
+/******************************************************************************/
+/************************** Functions Implementation **************************/
+/******************************************************************************/
+
+/**
+ * Find first set bit in word.
+ */
+uint32_t find_first_set_bit(uint32_t word)
+{
+	uint32_t first_set_bit = 0;
+
+	while (word) {
+		if (word & 0x1)
+			return first_set_bit;
+		word >>= 1;
+		first_set_bit ++;
+	}
+
+	return 32;
+}
+
+/**
+ * Find last set bit in word.
+ */
+uint32_t find_last_set_bit(uint32_t word)
+{
+	uint32_t bit = 0;
+	uint32_t last_set_bit = 32;
+
+	while (word) {
+		if (word & 0x1)
+			last_set_bit = bit;
+		word >>= 1;
+		bit ++;
+	}
+
+	return last_set_bit;
+}
+
+/**
+ * Locate the closest element in an array.
+ */
+uint32_t find_closest(int32_t val,
+		      const int32_t *array,
+		      uint32_t size)
+{
+	int32_t diff = abs(array[0] - val);
+	uint32_t ret = 0;
+	uint32_t i;
+
+	for (i = 1; i < size; i++) {
+		if (abs(array[i] - val) < diff) {
+			diff = abs(array[i] - val);
+			ret = i;
+		}
+	}
+
+	return ret;
+}
+
+/**
+ * Shift the value and apply the specified mask.
+ */
+uint32_t field_prep(uint32_t mask, uint32_t val)
+{
+	return (val << find_first_set_bit(mask)) & mask;
+}
+
+/**
+ * Get a field specified by a mask from a word.
+ */
+uint32_t field_get(uint32_t mask, uint32_t word)
+{
+	return (word & mask) >> find_first_set_bit(mask);
+}
+
+/**
+ * Log base 2 of the given number.
+ */
+int32_t log_base_2(uint32_t x)
+{
+	return find_last_set_bit(x);
+}
+
+/**
+ * Find greatest common divisor of the given two numbers.
+ */
+uint32_t greatest_common_divisor(uint32_t a,
+				 uint32_t b)
+{
+	uint32_t div;
+	uint32_t common_div = 1;
+
+	if ((a == 0) || (b == 0))
+		return max(a, b);
+
+	for (div = 1; (div <= a) && (div <= b); div++)
+		if (!(a % div) && !(b % div))
+			common_div = div;
+
+	return common_div;
+}
+
+/**
+ * Calculate best rational approximation for a given fraction.
+ */
+void rational_best_approximation(uint32_t given_numerator,
+				 uint32_t given_denominator,
+				 uint32_t max_numerator,
+				 uint32_t max_denominator,
+				 uint32_t *best_numerator,
+				 uint32_t *best_denominator)
+{
+	uint32_t gcd;
+
+	gcd = greatest_common_divisor(given_numerator, given_denominator);
+
+	*best_numerator = given_numerator / gcd;
+	*best_denominator = given_denominator / gcd;
+
+	if ((*best_numerator > max_numerator) ||
+	    (*best_denominator > max_denominator)) {
+		*best_numerator = 0;
+		*best_denominator = 0;
+	}
+}
+
+/**
+ * Calculate the number of set bits.
+ */
+uint32_t hweight8(uint32_t word)
+{
+	uint32_t count = 0;
+
+	while (word) {
+		if (word & 0x1)
+			count++;
+		word >>= 1;
+	}
+
+	return count;
+}
+
+/**
+ * Calculate the quotient and the remainder of an integer division.
+ */
+uint64_t do_div(uint64_t* n,
+		uint64_t base)
+{
+	uint64_t mod = 0;
+
+	mod = *n % base;
+	*n = *n / base;
+
+	return mod;
+}
+
+/**
+ * Unsigned 64bit divide with 64bit divisor and remainder
+ */
+uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor, uint64_t *remainder)
+{
+	*remainder = dividend % divisor;
+
+	return dividend / divisor;
+}
+
+/**
+ * Unsigned 64bit divide with 32bit divisor with remainder
+ */
+uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder)
+{
+	*remainder = do_div(&dividend, divisor);
+
+	return dividend;
+}
+
+/**
+ * Signed 64bit divide with 32bit divisor with remainder
+ */
+int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder)
+{
+	*remainder = dividend % divisor;
+	return dividend / divisor;
+}
+
+/**
+ * Unsigned 64bit divide with 32bit divisor
+ */
+uint64_t div_u64(uint64_t dividend, uint32_t divisor)
+{
+	uint32_t remainder;
+
+	return div_u64_rem(dividend, divisor, &remainder);
+}
+
+/**
+ * Signed 64bit divide with 32bit divisor
+ */
+int64_t div_s64(int64_t dividend, int32_t divisor)
+{
+	int32_t remainder;
+	return div_s64_rem(dividend, divisor, &remainder);
+}
+
+/**
+ * Converts from string to int32_t
+ * @param *str
+ * @return int32_t
+ */
+int32_t str_to_int32(const char *str)
+{
+	char *end;
+	int32_t value = strtol(str, &end, 0);
+
+	if (end == str)
+		return -EINVAL;
+	else
+		return value;
+}
+
+/**
+ * Converts from string to uint32_t
+ * @param *str
+ * @return uint32_t
+ */
+uint32_t srt_to_uint32(const char *str)
+{
+	char *end;
+	uint32_t value = strtoul(str, &end, 0);
+
+	if (end == str)
+		return -EINVAL;
+	else
+		return value;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/app_config.h

@@ -0,0 +1,66 @@
+/*****************************************************************************/
+/**
+ * Description: Global configurations.
+ *
+ * Date: 2021-04-28 13:19
+ * Last Edit Time: 2022-05-23 20:32
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2021-04-28]: Initial edition.
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+#ifndef CONFIG_H_
+#define CONFIG_H_
+
+#define XILINX_PLATFORM
+
+#include "xparameters.h"
+#include "xparameters_ps.h"
+
+/************ Hardware Configs ************/
+#define FCLK_CLK0_HZ                XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
+
+/********* Zynq Platform Configs **********/
+
+//Hardware Parameter
+#define SPI_INTERFACE_SPI_ENGINE
+
+#define HAVE_SPLIT_GAIN_TABLE	1 /* only set to 0 in case split_gain_table_mode_enable = 0*/
+#define HAVE_TDD_SYNTH_TABLE	1 /* only set to 0 in case split_gain_table_mode_enable = 0*/
+
+#define HAVE_VERBOSE_MESSAGES /* Recommended during development prints errors and warnings */
+//#define HAVE_DEBUG_MESSAGES /* For Debug purposes only */
+
+// interrupt controller
+#define INTC_DEVICE_ID              XPAR_SCUGIC_SINGLE_DEVICE_ID
+
+// gpio
+#define GPIO_DEVICE_ID              XPAR_PSU_GPIO_0_DEVICE_ID
+#define GPIO_INTR_ID                XPS_GPIO_INT_ID
+
+#define GPIO_OFFSET                 78
+#define GPIO_INPUT                  0
+#define GPIO_OUTPUT                 1
+#define GPIO_DISABLE                0
+#define GPIO_ENABLE                 1
+
+// rfdc
+#define RFDC_DEVICE_ID              XPAR_XRFDC_0_DEVICE_ID
+#define RFDC_INTR_ID                XPAR_FABRIC_RFDC_0_VEC_ID
+
+// spi
+#define SPI_DEVICE_ID               0
+#define SPI_ENGINE_REF_CLK          FCLK_CLK0_HZ
+#define SPI_ENGINE_MAX_SPEED        2500000
+#define SPI_ENGINE_BASEADDR         XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
+#define SPI_ENGINE_DATA_WIDTH       8
+#define SPI_ENGINE_CS_DELAY         3
+
+#define SPI_CS_LMK04828             0x00
+
+#endif

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/dev_profile/dev_profile.h

@@ -0,0 +1,34 @@
+#ifndef DEV_PROFILE_H_
+#define DEV_PROFILE_H_
+
+#include <inttypes.h>
+#include "../app_config.h"
+#include "../adi_noos/include/spi.h"
+#include "../adi_noos/include/gpio.h"
+#include "../adi_noos/include/delay.h"
+#include "../adi_noos/include/irq.h"
+#include "../adi_noos/include/error.h"
+#include "../adi_noos/drivers/frequency/lmk04828/lmk04828.h"
+
+// Platform includes
+#include "../adi_noos/drivers/platform/spi_extra.h"
+#include "../adi_noos/drivers/platform/gpio_extra.h"
+#include "../adi_noos/drivers/platform/irq_extra.h"
+
+// AXI-Cores includes
+#include "../adi_noos/drivers/axi_core/spi_engine/spi_engine.h"
+
+// Declare in mian.c
+extern struct spi_engine_init_param spi_engine_param;
+extern struct xil_gpio_init_param xil_gpio_param;
+
+#define GPIO_PARAM	&xil_gpio_param
+#define SPI_PARAM	&spi_engine_param
+#define GPIO_OPS	&xil_gpio_ops
+#define SPI_OPS		&spi_eng_platform_ops
+
+extern struct lmk04828_init_param lmk04828_default_init_param;
+extern const struct lmk04828_config lmk04828_default_config[];
+extern const uint32_t lmk04828_default_config_len;
+
+#endif /* SRC_DEV_PROFILE_H_ */

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/dev_profile/lmk04828_profile.c

@@ -0,0 +1,158 @@
+#include "dev_profile.h"
+#include "../app_config.h"
+#include "../adi_noos/drivers/frequency/lmk04828/lmk04828.h"
+
+
+static spi_init_param lmk04828_spi_init = {
+	.device_id = SPI_DEVICE_ID,
+    .max_speed_hz = SPI_ENGINE_MAX_SPEED,
+	.mode = SPI_MODE_0,
+	.chip_select = SPI_CS_LMK04828,
+	.platform_ops = SPI_OPS,
+	.extra = SPI_PARAM
+};
+
+struct lmk04828_init_param lmk04828_default_init_param = {
+	/* SPI */
+	.spi_init = &lmk04828_spi_init
+};
+
+const uint32_t lmk04828_default_config_len = 136;
+const struct lmk04828_config lmk04828_default_config[] = {
+	{0x0000, 0x90},
+	{0x0000, 0x10},
+	{0x0002, 0x00},
+	{0x0003, 0x06},
+	{0x0004, 0xD0},
+	{0x0005, 0x5B},
+	{0x0006, 0x00},
+	{0x000C, 0x51},
+	{0x000D, 0x04},
+	{0x0100, 0x03},
+	{0x0101, 0x55},
+	{0x0102, 0x55},
+	{0x0103, 0x01},
+	{0x0104, 0x02},
+	{0x0105, 0x00},
+	{0x0106, 0xF9},
+	{0x0107, 0x55},
+	{0x0108, 0x0C},
+	{0x0109, 0x55},
+	{0x010A, 0x55},
+	{0x010B, 0x00},
+	{0x010C, 0x22},
+	{0x010D, 0x00},
+	{0x010E, 0xF0},
+	{0x010F, 0x50},
+	{0x0110, 0x08},
+	{0x0111, 0x55},
+	{0x0112, 0x55},
+	{0x0113, 0x00},
+	{0x0114, 0x02},
+	{0x0115, 0x00},
+	{0x0116, 0xF9},
+	{0x0117, 0x00},
+	{0x0118, 0x0C},
+	{0x0119, 0x55},
+	{0x011A, 0x55},
+	{0x011B, 0x00},
+	{0x011C, 0x02},
+	{0x011D, 0x00},
+	{0x011E, 0xF1},
+	{0x011F, 0x55},
+	{0x0120, 0x0C},
+	{0x0121, 0x55},
+	{0x0122, 0x55},
+	{0x0123, 0x00},
+	{0x0124, 0x22},
+	{0x0125, 0x00},
+	{0x0126, 0xF0},
+	{0x0127, 0x55},
+	{0x0128, 0x00},
+	{0x0129, 0x55},
+	{0x012A, 0x55},
+	{0x012B, 0x00},
+	{0x012C, 0x02},
+	{0x012D, 0x00},
+	{0x012E, 0xF0},
+	{0x012F, 0x50},
+	{0x0130, 0x0C},
+	{0x0131, 0x55},
+	{0x0132, 0x55},
+	{0x0133, 0x00},
+	{0x0134, 0x22},
+	{0x0135, 0x00},
+	{0x0136, 0xF1},
+	{0x0137, 0x55},
+	{0x0138, 0x20},
+	{0x0139, 0x03},
+	{0x013A, 0x0C},
+	{0x013B, 0x00},
+	{0x013C, 0x00},
+	{0x013D, 0x08},
+	{0x013E, 0x03},
+	{0x013F, 0x00},
+	{0x0140, 0x0B},
+	{0x0141, 0x00},
+	{0x0142, 0x00},
+	{0x0143, 0x10},
+	{0x0144, 0xFF},
+	{0x0145, 0x7F},
+	{0x0146, 0x1A},
+	{0x0147, 0x1A},
+	{0x0148, 0x03},
+	{0x0149, 0x05},
+	{0x014A, 0x1B},
+	{0x014B, 0x16},
+	{0x014C, 0x00},
+	{0x014D, 0x00},
+	{0x014E, 0xC0},
+	{0x014F, 0x7F},
+	{0x0150, 0x03},
+	{0x0151, 0x02},
+	{0x0152, 0x00},
+	{0x0153, 0x00},
+	{0x0154, 0x78},
+	{0x0155, 0x00},
+	{0x0156, 0x0A},
+	{0x0157, 0x00},
+	{0x0158, 0x96},
+	{0x0159, 0x00},
+	{0x015A, 0x60},
+	{0x015B, 0xD4},
+	{0x015C, 0x20},
+	{0x015D, 0x00},
+	{0x015E, 0x00},
+	{0x015F, 0x3B},
+	{0x0160, 0x00},
+	{0x0161, 0x01},
+	{0x0162, 0x44},
+	{0x0163, 0x00},
+	{0x0164, 0x00},
+	{0x0165, 0x0C},
+	{0x0171, 0xAA},
+	{0x0172, 0x02},
+	{0x017C, 0x15},
+	{0x017D, 0x33},
+	{0x0166, 0x00},
+	{0x0167, 0x00},
+	{0x0168, 0x0C},
+	{0x0169, 0x59},
+	{0x016A, 0x20},
+	{0x016B, 0x00},
+	{0x016C, 0x00},
+	{0x016D, 0x00},
+	{0x016E, 0x1B},
+	{0x0173, 0x00},
+	{0x0182, 0x00},
+	{0x0183, 0x00},
+	{0x0184, 0x00},
+	{0x0185, 0x00},
+	{0x0188, 0x00},
+	{0x0189, 0x00},
+	{0x018A, 0x00},
+	{0x018B, 0x00},
+	{0x1FFD, 0x00},
+	{0x1FFE, 0x00},
+	{0x1FFF, 0x53}
+};

rfsoc_eval_demo/vitis_classic_autobuild/source_adc_dac_sweep/main.c

@@ -0,0 +1,700 @@
+/*****************************************************************************/
+/**
+ * Description: main.c
+ *
+ * Date: 2021-11-13 13:19
+ * Last Edit Time: [2023-04-23 21:32]
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2021-11-13]: Initial edition.
+ * [2022-03-28]: Add bit error test mode.
+ * [2023-04-23]: Bug fixed,
+ *
+ * Copyright(c) 2021 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+/******************************************************************************/
+/******************************* Include Files ********************************/
+/******************************************************************************/
+
+// Standard
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+
+// Xilinx
+#include "xscugic.h"        // The generic interrupt controller driver component
+#include "xil_exception.h"  // ARM Cortex A9 specific exception related APIs
+#include "sleep.h"
+#include "xgpiops.h"
+#include "xrfdc.h"
+
+// ADI Drivers
+#include "dev_profile/dev_profile.h"
+#include "adi_noos/drivers/axi_core/spi_engine/spi_engine.h"
+#include "adi_noos/drivers/platform/gpio_extra.h"
+
+// User
+#include "app_config.h"
+
+/******************************************************************************/
+/**************************** Function Prototypes *****************************/
+/******************************************************************************/
+
+int SetupInterruptSystem(XScuGic* GicInstPtr, u32 IntcDevId);
+int SetupGpioPs(XGpioPs* GpioPsInstPtr, u32 GpioPsDevId);
+int SetupRFdc(XRFdc* RFdcInstPtr, u32 RFdcDevId, XScuGic* GicInstPtr,
+        u32 IntcDevId);
+void XRFdc_IntrHandlerWrapper(void* callbackRef);
+void RFdcHandler(void* CallBackRef, u32 Type, u32 Tile_Id, u32 Block_Id,
+        u32 Event);
+int RFdc_DisableInvSyncFIR(XRFdc* RFdcInstPtr);
+int RFdc_DacTestCase(XRFdc* RFdcInstPtr, u32 Tile_Id, u32 Block_Id,
+        u32 NyquistZone, u32 DataPathMode, u32 DecoderMode);
+
+/******************************************************************************/
+/**************************** Constant Definitions ****************************/
+/******************************************************************************/
+
+struct spi_engine_init_param spi_engine_param = {
+    .ref_clk_hz = SPI_ENGINE_REF_CLK,
+    .type = SPI_ENGINE,
+    .spi_engine_baseaddr = SPI_ENGINE_BASEADDR,
+    .cs_delay = SPI_ENGINE_CS_DELAY,
+    .data_width = SPI_ENGINE_DATA_WIDTH
+};
+
+struct xil_gpio_init_param xil_gpio_param = {
+    .type = GPIO_PS,
+    .device_id = GPIO_DEVICE_ID
+};
+
+struct lmk04828_dev *lmk04828_inst;
+
+/******************************************************************************/
+/************************ Driver Instance Definitions *************************/
+/******************************************************************************/
+
+static XScuGic Intc; // General interrupt controller instance
+static XRFdc RFdc;
+static XGpioPs GpioPs;
+
+
+//static uint64_t my_io_read(struct metal_io_region *io,
+//                   unsigned long offset,
+//                   memory_order order,
+//                   int width){
+//    metal_assert(offset <= io->size);
+//    unsigned long addr = offset + *(io->physmap);
+//    switch (width) {
+//    case 1:
+//        return Xil_In8(addr);
+//    case 2:
+//        return Xil_In16(addr);
+//    case 4:
+//        return Xil_In32(addr);
+//    case 8:
+//        return Xil_In64(addr);
+//    default:
+//        metal_assert(0);
+//        return -1;
+//    }
+//}
+//
+//
+//static void my_io_write(struct metal_io_region *io,
+//                unsigned long offset,
+//                uint64_t value,
+//                memory_order order,
+//                int width){
+//    metal_assert(offset <= io->size);
+//    unsigned long addr = offset + *(io->physmap);
+//    switch (width) {
+//    case 1:
+//        return Xil_Out8(addr, value);
+//    case 2:
+//        return Xil_Out16(addr, value);
+//    case 4:
+//        return Xil_Out32(addr, value);
+//    case 8:
+//        return Xil_Out64(addr, value);
+//    default:
+//        metal_assert(0);
+//    }
+//
+//}
+
+/****************************************************************************/
+/**
+ * @brief   This function initializes the SCUGIC instance. It looks for the
+ *          device configuration based on the unique device ID, initializes a
+ *          SCUGIC and enables system interrupts.
+ *
+ * @param   GicInstPtr is a reference to the XScuGic driver Instance.
+ * @param   IntcDevId is the XPAR_<SCUGIC_instance>_DEVICE_ID value from
+ *          "xparameters.h".
+ *
+ * @return  SUCCESS if initialization succeed.
+ *          XST_FAILURE if initialization failed.
+ *
+ *****************************************************************************/
+int SetupInterruptSystem(XScuGic* GicInstPtr, u32 IntcDevId){
+
+	int Status;
+
+	XScuGic_Config* IntcConfig; /* Instance of the interrupt controller */
+
+	Xil_ExceptionInit();
+
+	/*
+     * Initialize the interrupt controller driver so that it is ready to
+     * use.
+     */
+	IntcConfig = XScuGic_LookupConfig(IntcDevId);
+    if (NULL == IntcConfig) {
+        return XST_FAILURE;
+    }
+
+    Status = XScuGic_CfgInitialize(GicInstPtr, IntcConfig,
+            IntcConfig->CpuBaseAddress);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    /*
+     * Connect the interrupt controller interrupt handler to the hardware
+     * interrupt handling logic in the processor.
+     */
+    Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+                     (Xil_ExceptionHandler)XScuGic_InterruptHandler,
+                     GicInstPtr);
+
+    /* Enable interrupts in the Processor. */
+    Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
+
+	return SUCCESS;
+} // SetupInterruptSystem
+
+
+/****************************************************************************/
+/**
+ * @brief   This function initializes the PS GPIO instance. It looks for the
+ *          device configuration based on the unique device ID and initializes a
+ *          GpioPs instance.
+ *
+ * @param   GpioPsInstPtr is a reference to the XGpioPs driver Instance.
+ * @param   GpioPsDevId is the XPAR_<GPIO_instance>_DEVICE_ID value from
+ *          "xparameters.h".
+ *
+ * @return  SUCCESS if initialize successful.
+ *          XST_FAILURE if initialization failed.
+ *
+ *****************************************************************************/
+int SetupGpioPs(XGpioPs* GpioPsInstPtr, u32 GpioPsDevId){
+
+    int Status;
+
+    XGpioPs_Config *ConfigPtr;
+
+    /* Initialize the Gpio driver. */
+    ConfigPtr = XGpioPs_LookupConfig(GpioPsDevId);
+    if (ConfigPtr == NULL) {
+        return XST_FAILURE;
+    }
+
+    Status = XGpioPs_CfgInitialize(GpioPsInstPtr, ConfigPtr,
+            ConfigPtr->BaseAddr);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    /* Run a self-test on the GPIO device. */
+    Status = XGpioPs_SelfTest(GpioPsInstPtr);
+
+    return Status;
+} // SetupGpioPs
+
+
+/****************************************************************************/
+/**
+ * @brief   This function initializes the PS GPIO instance. It looks for the
+ *          device configuration based on the unique device ID and initializes a
+ *          GpioPs instance.
+ *
+ * @param   RFdcInstPtr is a reference to the XRFdc driver Instance.
+ * @param   RFdcDevId is the XPAR_<RFdc_instance>_DEVICE_ID value from
+ *          "xparameters.h".
+ * @param   GicInstPtr is a reference to the XScuGic driver Instance.
+ * @param   IntcDevId is the XPAR_<SCUGIC_instance>_DEVICE_ID value from
+ *          "xparameters.h".
+ *
+ * @return  SUCCESS if initialize successful.
+ *          XST_FAILURE if initialization failed.
+ *
+ *****************************************************************************/
+int SetupRFdc(XRFdc* RFdcInstPtr, u32 RFdcDevId, XScuGic* GicInstPtr,
+        u32 RFdcIntrId) {
+
+    int Status;
+
+    XRFdc_Config *RFdcConfigPtr;
+
+    RFdcConfigPtr = XRFdc_LookupConfig(RFdcDevId);
+
+    Status = XRFdc_CfgInitialize(RFdcInstPtr, RFdcConfigPtr);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+//    RFdc.io->ops.read = my_io_read;
+//    RFdc.io->ops.write = my_io_write;
+
+    // interrupt
+    /*
+     * Connect the device driver handler that will be called when an
+     * interrupt for the device occurs, the handler defined above performs
+     * the specific interrupt processing for the device.
+     */
+    Status = XScuGic_Connect(GicInstPtr, RFdcIntrId, XRFdc_IntrHandlerWrapper,
+            RFdcInstPtr);
+    if (Status != XST_SUCCESS) {
+        return Status;
+    }
+
+    /* Set the handler for RFdc interrupts. */
+    XRFdc_SetStatusHandler(RFdcInstPtr, RFdcInstPtr, RFdcHandler);
+
+    /* Enable the interrupt for the RFdc device. */
+    XScuGic_Enable(GicInstPtr, RFdcIntrId);
+
+    return Status;
+} // SetupRFdc
+
+/****************************************************************************/
+/**
+ * This function is wrapper for XRFdc_IntrHandler() when libmetal is not used,
+ * to fit the Xil_InterruptHandler() type in ScuGic.
+ *
+ * @param   CallBackRef is a pointer to the upper layer callback reference.
+ *
+ * @return  None.
+ *
+ * @note    None.
+ *
+ ******************************************************************************/
+void XRFdc_IntrHandlerWrapper(void* callbackRef) {
+    XRFdc_IntrHandler(RFDC_INTR_ID, callbackRef);
+}
+
+
+/****************************************************************************/
+/**
+ * This function is the user layer callback function for rfdc interrupts. It
+ * prints information about the interrupts then clear them.
+ *
+ * @param   CallBackRef is a pointer to the upper layer callback reference.
+ * @param   Type is ADC or DAC. 0 for ADC and 1 for DAC, and can be
+ *          XRFDC_<Type>_TILE value from "xrfdc.h".
+ * @param   Tile_Id Valid values are 0-3 and can be the XRFDC_TILE_<Tile_Id>
+ *          value from "xrfdc.h".
+ * @param   Block_Id is DAC block number inside the tile. Valid values are 0-3.
+ * @param   NyquistZone Valid values are 1 (Odd), 2 (Even) and can be the
+ *          XRFDC_<NyquistZone>_NYQUIST_ZONE value from "xrfdc.h".
+ *
+ * @return  None.
+ *
+ * @note    None.
+ *
+ ******************************************************************************/
+void RFdcHandler(void* CallBackRef, u32 Type, u32 Tile_Id, u32 Block_Id,
+        u32 Event) {
+
+    XRFdc* RFdc = (XRFdc *)CallBackRef;
+
+    // Check the type of interrupt event
+    if (Type == XRFDC_DAC_TILE) {
+        xil_printf("\nInterrupt occurred for ADC%d,%d :", Tile_Id, Block_Id);
+        if (Event & (XRFDC_IXR_FIFOUSRDAT_OF_MASK |
+                XRFDC_IXR_FIFOUSRDAT_UF_MASK)) {
+            xil_printf("FIFO Actual Overflow\r\n");
+            XRFdc_IntrClr(RFdc, Type, Tile_Id, Block_Id,
+                    XRFDC_IXR_FIFOUSRDAT_OF_MASK |
+                    XRFDC_IXR_FIFOUSRDAT_UF_MASK);
+        }
+        if (Event & (XRFDC_IXR_FIFOMRGNIND_OF_MASK |
+                XRFDC_IXR_FIFOMRGNIND_UF_MASK)) {
+            xil_printf("FIFO Marginal Overflow\r\n");
+        }
+        if(Event & XRFDC_DAC_IXR_INTP_STG_MASK) {
+            xil_printf("Interpolation Stages Overflow\r\n");
+        }
+    // ... Other handling code ...
+    } else {
+        xil_printf("\nInterrupt occurred for ADC%d,%d :\r\n", Tile_Id, Block_Id);
+        if (Event & XRFDC_ADC_OVR_RANGE_MASK) {
+            xil_printf("ADC Over range for ADC%d,%d :\r\n", Tile_Id, Block_Id);
+            XRFdc_IntrClr(RFdc, Type, Tile_Id, Block_Id,
+                    XRFDC_ADC_OVR_RANGE_MASK);
+        }
+        if (Event & XRFDC_ADC_OVR_VOLTAGE_MASK) {
+            xil_printf("ADC Over voltage for ADC%d,%d :\r\n", Tile_Id, Block_Id);
+            XRFdc_IntrClr(RFdc, Type, Tile_Id, Block_Id,
+                    XRFDC_ADC_OVR_VOLTAGE_MASK);
+        }
+        if (Event & XRFDC_ADC_DAT_OVR_MASK) {
+            xil_printf("ADC data path interrupt for ADC%d,%d :\r\n", Tile_Id,
+                    Block_Id);
+            XRFdc_IntrClr(RFdc, Type, Tile_Id, Block_Id,
+                    XRFDC_ADC_DAT_OVR_MASK);
+        }
+    }
+}
+
+/****************************************************************************/
+/**
+ * @brief   This function disables inverse sync filter for all RF-DACs.
+ *
+ * @param   RFdcInstPtr is a reference to the XRFdc driver Instance.
+ *
+ * @return  XRFDC_SUCCESS if successful.
+*           XRFDC_FAILURE if block not enabled/invalid mode.
+ *
+ *****************************************************************************/
+int RFdc_DisableInvSyncFIR(XRFdc* RFdcInstPtr){
+
+    int Status;
+    uint16_t InvSyncFirMode;
+
+    for (uint32_t Tile_Id = 0; Tile_Id <= XRFDC_TILE_ID3; Tile_Id++) {
+        for (uint32_t Block_Id = 0; Block_Id <= XRFDC_BLK_ID3; Block_Id += 2) {
+            Status = XRFdc_GetInvSincFIR(RFdcInstPtr, Tile_Id, Block_Id,
+                    &InvSyncFirMode);
+            if (Status != XST_SUCCESS) {
+                return XST_FAILURE;
+            }
+
+            if (InvSyncFirMode != 0) {
+                Status = XRFdc_SetInvSincFIR(RFdcInstPtr, Tile_Id, Block_Id,
+                        XRFDC_DISABLED);
+                if (Status != XST_SUCCESS) {
+                    return XST_FAILURE;
+                }
+            }
+        }
+    }
+
+    return Status;
+} // RFdc_DisableInvSyncFIR
+
+
+/****************************************************************************/
+/**
+ * @brief   This function performs sweep frequency tests for specific RF-DAC
+ *          with certain nyquist zone, data path mode and decoder mode.
+ *
+ * @param   RFdcInstPtr is a reference to the XRFdc driver Instance.
+ * @param   Tile_Id Valid values are 0-3 and can be the XRFDC_TILE_<Tile_Id>
+ *          value from "xrfdc.h".
+ * @param   Block_Id is DAC block number inside the tile. Valid values are 0-3.
+ * @param   NyquistZone Valid values are 1 (Odd), 2 (Even) and can be the
+ *          XRFDC_<NyquistZone>_NYQUIST_ZONE value from "xrfdc.h".
+ * @param   DataPathMode Valid values are 1-4, and can be
+ *          XRFDC_DATAPATH_MODE_<DataPathMode> value from "xrfdc.h".
+ * @param   DecoderMode Valid values are 1 (Maximum SNR, for non-
+ *          randomized decoder), 2 (Maximum Linearity, for randomized decoder),
+ *          and can be XRFDC_DECODER_<DecoderMode> value from "xrfdc.h".
+ *
+ * @return  SUCCESS if test succeed.
+ *          XST_FAILURE if test failed.
+ *
+ *****************************************************************************/
+int RFdc_DacTestCase(XRFdc* RFdcInstPtr, u32 Tile_Id, u32 Block_Id,
+        u32 NyquistZone, u32 DataPathMode, u32 DecoderMode){
+
+    int Status;
+
+    // set nyquist zone
+    Status = XRFdc_SetNyquistZone(RFdcInstPtr, XRFDC_DAC_TILE, Tile_Id,
+            Block_Id, NyquistZone);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    // set data path mode
+    Status = XRFdc_SetDataPathMode(RFdcInstPtr, Tile_Id, Block_Id,
+            DataPathMode);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    // set decoder mode
+    Status = XRFdc_SetDecoderMode(RFdcInstPtr, Tile_Id, Block_Id,
+            DecoderMode);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    // get & set mixer settings
+    XRFdc_Mixer_Settings Mixer_Settings_DAC;
+
+    Status = XRFdc_GetMixerSettings(RFdcInstPtr, XRFDC_DAC_TILE, Tile_Id,
+            Block_Id, &Mixer_Settings_DAC);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+//    for (double freq = 5;freq <= 9600; freq += 1) {
+//        Mixer_Settings_DAC.Freq = freq;
+//
+//        Status = XRFdc_SetMixerSettings(RFdcInstPtr, XRFDC_DAC_TILE, Tile_Id,
+//                Block_Id,  &Mixer_Settings_DAC);
+//        if (Status != XST_SUCCESS) {
+//            return XST_FAILURE;
+//        }
+//
+//        XRFdc_UpdateEvent(&RFdc, XRFDC_DAC_TILE, Tile_Id, Block_Id,
+//                XRFDC_EVENT_MIXER);
+//
+//        mdelay(10);
+//    }
+
+    mdelay(10);
+
+    // target frequency range sweep
+    for (double freq = 3700;freq <= 4300; freq += 1) {
+        Mixer_Settings_DAC.Freq = freq;
+
+        Status = XRFdc_SetMixerSettings(RFdcInstPtr, XRFDC_DAC_TILE, Tile_Id,
+                Block_Id,  &Mixer_Settings_DAC);
+        if (Status != XST_SUCCESS) {
+            return XST_FAILURE;
+        }
+
+        XRFdc_UpdateEvent(&RFdc, XRFDC_DAC_TILE, Tile_Id, Block_Id,
+                XRFDC_EVENT_MIXER);
+
+        mdelay(25);
+    }
+
+    return Status;
+} // RFdc_DacTestCase
+
+
+/****************************************************************************/
+/**
+ * @brief   This function performs sweep frequency tests for specific RF-DAC
+ *          with certain nyquist zone, calibration mode and dither mode.
+ *
+ * @param   RFdcInstPtr is a reference to the XRFdc driver Instance.
+ * @param   Tile_Id Valid values are 0-3 and can be the XRFDC_TILE_<Tile_Id>
+ *          value from "xrfdc.h".
+ * @param   Block_Id is DAC block number inside the tile. Valid values are 0-3.
+ * @param   NyquistZone Valid values are 1 (Odd), 2 (Even) and can be the
+ *          XRFDC_<NyquistZone>_NYQUIST_ZONE value from "xrfdc.h".
+ * @param   DataPathMode Valid values are 1-4, and can be
+ *          XRFDC_DATAPATH_MODE_<DataPathMode> value from "xrfdc.h".
+ * @param   DecoderMode Valid values are 1 (Maximum SNR, for non-
+ *          randomized decoder), 2 (Maximum Linearity, for randomized decoder),
+ *          and can be XRFDC_DECODER_<DecoderMode> value from "xrfdc.h".
+ *
+ * @return  SUCCESS if test succeed.
+ *          XST_FAILURE if test failed.
+ *
+ *****************************************************************************/
+int RFdc_AdcTestCase(XRFdc* RFdcInstPtr, u32 Tile_Id, u32 Block_Id,
+        u32 NyquistZone, u32 CalibMode, u32 DitherMode){
+
+    int Status;
+
+    // set nyquist zone
+    Status = XRFdc_SetNyquistZone(RFdcInstPtr, XRFDC_ADC_TILE, Tile_Id,
+            Block_Id, NyquistZone);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    // set calibration mode
+    XRFdc_SetCalibrationMode(RFdcInstPtr, Tile_Id, Block_Id, CalibMode);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    // set dither mode; Dither should be enabled unless the sample rate is
+    // under 0.75 times the maximum sampling rate for the RF-ADC.
+    Status = XRFdc_SetDither(RFdcInstPtr, Tile_Id, Block_Id, DitherMode);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    // get & set mixer settings
+    XRFdc_Mixer_Settings Mixer_Settings_ADC;
+
+    Status = XRFdc_GetMixerSettings(RFdcInstPtr, XRFDC_ADC_TILE, Tile_Id,
+            Block_Id, &Mixer_Settings_ADC);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    // target frequency range sweep
+    for (double freq = 4000;freq <= 4000; freq += 100) {
+        Mixer_Settings_ADC.Freq = freq;
+        Mixer_Settings_ADC.EventSource = XRFDC_EVNT_SRC_TILE;
+
+        Status = XRFdc_SetMixerSettings(RFdcInstPtr, XRFDC_ADC_TILE, Tile_Id,
+                Block_Id, &Mixer_Settings_ADC);
+        if (Status != XST_SUCCESS) {
+            return XST_FAILURE;
+        }
+
+        Status = XRFdc_UpdateEvent(&RFdc, XRFDC_ADC_TILE, Tile_Id, Block_Id,
+                XRFDC_EVENT_MIXER);
+        if (Status != XST_SUCCESS) {
+            return XST_FAILURE;
+        }
+
+        mdelay(25);
+    }
+
+    return Status;
+} // RFdc_AdcTestCase
+
+
+/***************************************************************************//**
+ * @brief main
+*******************************************************************************/
+int main(void) {
+    int32_t Status;
+
+    struct metal_init_params params = METAL_INIT_DEFAULTS;
+
+    params.log_level = METAL_LOG_DEBUG;
+    Status = metal_init(&params);
+    if (Status != XST_SUCCESS)
+        return Status;
+
+
+    /**********************************************************/
+    /***************** Xilinx Initialization ******************/
+    /**********************************************************/
+    // gic
+    Status = SetupInterruptSystem(&Intc, INTC_DEVICE_ID);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    // gpio
+    Status = SetupGpioPs(&GpioPs, GPIO_DEVICE_ID);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    // rf data converter initialization
+    Status = SetupRFdc(&RFdc, RFDC_DEVICE_ID, &Intc, RFDC_INTR_ID);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    /**********************************************************/
+    /***************** LMK04828 Configuration *****************/
+    /**********************************************************/
+    // configuration
+    Status = lmk04828_init(&lmk04828_inst, &lmk04828_default_init_param);
+    for(uint32_t i = 0; i < lmk04828_default_config_len; i++) {
+        Status = lmk04828_write(lmk04828_inst, lmk04828_default_config[i].addr, lmk04828_default_config[i].value);
+        if (lmk04828_default_config[i].addr == 0x0000) {
+            // wait for reset
+            mdelay(500);
+        }
+    }
+
+    // check pll2 lock status
+    uint8_t reg183;
+    Status = lmk04828_read(lmk04828_inst, 0x0183, &reg183);
+    if (reg183 & 0x02) {
+        xil_printf("LMK04828 Config Done.\n");
+    }
+    else {
+        xil_printf("LMK04828 not lock!\n");
+        return XST_FAILURE;
+    }
+
+    /**********************************************************/
+    /***************** RF DAC Reconfiguration *****************/
+    /**********************************************************/
+
+//#define DAC_TEST
+
+    /*
+     * The following DAC and sampling rate are used to measure performance:
+     *   Number       Tile                  Block                        Sample Rate
+     *   1 (VOUT_00)  228 (XRFDC_TILE_ID0)  DAC 0/DUC 0 (XRFDC_BLK_ID0)  4.9152 Gsps
+     *   8 (VOUT_32)  231 (XRFDC_TILE_ID3)  DAC 1/DUC 2 (XRFDC_BLK_ID2)  9.8304 Gsps
+     *
+     */
+
+#ifdef DAC_TEST
+    // turn off inverse sinc filter
+    Status = RFdc_DisableInvSyncFIR(&RFdc);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    // turn on inverse sinc filter
+//    Status = XRFdc_SetInvSincFIR(&RFdc, XRFDC_TILE_ID0, XRFDC_BLK_ID0,
+//            XRFDC_ODD_NYQUIST_ZONE);
+//    if (Status != XST_SUCCESS) {
+//        return XST_FAILURE;
+//    }
+
+//    Status = RFdc_DacTestCase(&RFdc, XRFDC_TILE_ID3, XRFDC_BLK_ID2,
+//            XRFDC_ODD_NYQUIST_ZONE, XRFDC_DATAPATH_MODE_DUC_0_FSDIVFOUR,
+//            XRFDC_DECODER_MAX_SNR_MODE);
+//    if (Status != XST_SUCCESS) {
+//        return XST_FAILURE;
+//    }
+
+    Status = RFdc_DacTestCase(&RFdc, XRFDC_TILE_ID0, XRFDC_BLK_ID0,
+            XRFDC_EVEN_NYQUIST_ZONE, XRFDC_DATAPATH_MODE_DUC_0_FSDIVTWO,
+            XRFDC_DECODER_MAX_SNR_MODE);
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+#endif
+
+    /**********************************************************/
+    /***************** RF ADC Reconfiguration *****************/
+    /**********************************************************/
+
+#define ADC_TEST
+
+    /*
+     * The following ADC and sampling rate are used to measure performance:
+     *   Number       Tile                  Block                  Sample Rate
+     *   1 (VIN0_01)  224 (XRFDC_TILE_ID0)  ADC 0 (XRFDC_BLK_ID0)  4.9152 Gsps
+     *   8 (VIN3_23)  227 (XRFDC_TILE_ID3)  ADC 1 (XRFDC_BLK_ID1)  4.9152 Gsps
+     *
+     */
+
+#ifdef ADC_TEST
+    /* Enable the RFdc interrupts. */
+    Status = XRFdc_IntrEnable(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID0,
+            XRFDC_BLK_ID0, XRFDC_ADC_OVR_VOLTAGE_MASK |
+            XRFDC_ADC_OVR_RANGE_MASK |
+            XRFDC_ADC_DAT_OVR_MASK);
+
+    if (Status != XST_SUCCESS) {
+        return XST_FAILURE;
+    }
+
+    Status = RFdc_AdcTestCase(&RFdc, XRFDC_TILE_ID0, XRFDC_BLK_ID0,
+            XRFDC_EVEN_NYQUIST_ZONE, XRFDC_CALIB_MODE2,
+            XRFDC_DITH_ENABLE);
+
+    while(1);
+#endif
+
+    return XST_SUCCESS;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/adc/ad9694/ad9694.c

@@ -0,0 +1,128 @@
+/***************************************************************************//**
+ * @file ad9694.c
+ * @brief Implementation of AD9680 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdlib.h>
+#include <stdio.h>
+#include "ad9694.h"
+#include "../../../include/error.h"
+
+/***************************************************************************//**
+ * @brief ad9694_read
+ *******************************************************************************/
+int32_t ad9694_read(struct ad9694_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data)
+{
+	uint8_t tx_buf[2];
+	uint8_t rx_buf[1];
+	int32_t ret;
+
+	tx_buf[0] = 0x80 | (reg_addr >> 8);
+	tx_buf[1] = reg_addr & 0xFF;
+	
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+			tx_buf, rx_buf, 2, 1);
+
+	*reg_data = rx_buf[0];
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief ad9694_write
+ *******************************************************************************/
+int32_t ad9694_write(struct ad9694_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data)
+{
+	uint8_t buf[3];
+
+	int32_t ret;
+
+	buf[0] = reg_addr >> 8;
+	buf[1] = reg_addr & 0xFF;
+	buf[2] = reg_data;
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+				 buf, NULL, 3, 0);
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief ad9694_init
+ *******************************************************************************/
+int32_t ad9694_init(struct ad9694_dev **device,
+		     const struct ad9694_init_param *init_param)
+{
+	int ret = SUCCESS;
+	struct ad9694_dev *dev;
+
+	dev = (struct ad9694_dev *)malloc(sizeof(*dev));
+	if (!dev)
+		return FAILURE;
+
+	/* SPI */
+	ret = spi_init(&dev->spi_desc, init_param->spi_init);
+
+	*device = dev;
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief Free the resources allocated by ad9694_setup().
+ *
+ * @param dev - The device structure.
+ *
+ * @return SUCCESS in case of success, negative error code otherwise.
+*******************************************************************************/
+int32_t ad9694_remove(struct ad9694_dev *dev)
+{
+	int32_t ret;
+
+	ret = spi_remove(dev->spi_desc);
+
+	free(dev);
+
+	return ret;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/adc/ad9694/ad9694.h

@@ -0,0 +1,231 @@
+/***************************************************************************//**
+ * @file ad9694.h
+ * @brief Header file of AD9694 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+#ifndef AD9694_H_
+#define AD9694_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include "../../../include/delay.h"
+#include "../../../include/spi.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+#define AD9694_REG_GLOBAL_MAP_SPI_CONF_A						0x0000
+#define AD9694_REG_GLOBAL_MAP_SPI_CONF_B						0x0001
+#define AD9694_REG_CH_MAP_CHIP_CONF								0x0002
+#define AD9694_REG_PAIR_MAP_CHIP_TYPE							0x0003
+#define AD9694_REG_PAIR_MAP_CHIP_ID_LSB							0x0004
+#define AD9694_REG_PAIR_MAP_CHIP_GRADE							0x0006
+#define AD9694_REG_PAIR_MAP_DEV_INDEX							0x0008
+#define AD9694_REG_GLOBAL_MAP_PAIR_INDEX						0x0009
+#define AD9694_REG_PAIR_MAP_SCRATCH_PAD							0x000A
+#define AD9694_REG_PAIR_MAP_SPI_REVISION						0x000B
+#define AD9694_REG_PAIR_MAP_VENDOR_ID_LSB						0x000C
+#define AD9694_REG_PAIR_MAP_VENDOR_ID_MSB						0x000D
+#define AD9694_REG_CH_MAP_CHIP_PD_PIN							0x003F
+#define AD9694_REG_PAIR_MAP_CHIP_PIN_CTRL_1						0x0040
+#define AD9694_REG_PAIR_MAP_CLK_DIV_CTRL						0x0108
+#define AD9694_REG_CH_MAP_CLK_DIV_PHASE							0x0109
+#define AD9694_REG_PAIR_MAP_CLK_DIV_SYSREF_CTRL					0x010A
+#define AD9694_REG_PAIR_MAP_CLK_DELAY_CTRL						0x0110
+#define AD9694_REG_CH_MAP_CLK_SUPER_FINE_DELAY					0x0111
+#define AD9694_REG_CH_MAP_CLK_FINE_DELAY						0x0112
+#define AD9694_REG_CLK_DETN_CTRL								0x011A
+#define AD9694_REG_PAIR_MAP_CLK_STAT							0x011B
+#define AD9694_REG_CLK_DCS_CTRL_1								0x011C
+#define AD9694_REG_CLK_DCS_CTRL_2								0x011E
+#define AD9694_REG_CLK_DCS_CTRL_3								0x011F
+#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_1						0x0120
+#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_2						0x0121
+#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_4						0x0123
+#define AD9694_REG_PAIR_MAP_SYSREF_STAT_1						0x0128
+#define AD9694_REG_PAIR_MAP_SYSREF_STAT_2						0x0129
+#define AD9694_REG_PAIR_MAP_SYSREF_STAT_3						0x012A
+#define AD9694_REG_PAIR_MAP_CHIP_SYNC							0x01FF
+#define AD9694_REG_PAIR_MAP_CHIP_MODE							0x0200
+#define AD9694_REG_PAIR_MAP_CHIP_DEC_RATIO						0x0201
+#define AD9694_REG_CH_MAP_CUSTOM_OFFSET							0x0228
+#define AD9694_REG_CH_MAP_FD_CTRL								0x0245
+#define AD9694_REG_CH_MAP_FD_UT_LSB								0x0247
+#define AD9694_REG_CH_MAP_FD_UT_MSB								0x0248
+#define AD9694_REG_CH_MAP_FD_LT_LSB								0x0249
+#define AD9694_REG_CH_MAP_FD_LT_MSB								0x024A
+#define AD9694_REG_CH_MAP_FD_DWELL_TIME_LSB						0x024B
+#define AD9694_REG_CH_MAP_FD_DWELL_TIME_MSB						0x024C
+#define AD9694_REG_PAIR_MAP_SIG_MON_SYNC_CTRL					0x026F
+#define AD9694_REG_CH_MAP_SIG_MON_CTRL							0x0270
+#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_0						0x0271
+#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_1						0x0272
+#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_2						0x0273
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_CTRL						0x0274
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_0						0x0275
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_1						0x0276
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_2						0x0277
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_FRAME_CNT				0x0278
+#define AD9694_REG_CH_MAP_SIG_MON_SERIAL_FRAMER_CTRL			0x0279
+#define AD9694_REG_SPORT_OVER_JESD204B_INPUT_SEL				0x027A
+#define AD9694_REG_PAIR_MAP_DDC_SYNC_CTRL						0x0300
+#define AD9694_REG_PAIR_MAP_DDC_0_CTRL							0x0310
+#define AD9694_REG_PAIR_MAP_DDC_0_INPUT_SEL						0x0311
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_0					0x0314
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_1					0x0315
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_2					0x0316
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_3					0x0317
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_4					0x0318
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_5					0x031A
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_0				0x031D
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_1				0x031E
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_2				0x031F
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_3				0x0320
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_4				0x0321
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_5				0x0322
+#define AD9694_REG_PAIR_MAP_DDC_0_TEST_ENABLE					0x0327
+#define AD9694_REG_PAIR_MAP_DDC_1_CTRL							0x0330
+#define AD9694_REG_PAIR_MAP_DDC_1_INPUT_SEL						0x0331
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_0					0x0334
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_1					0x0335
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_2					0x0336
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_3					0x0337
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_4					0x0338
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_5					0x033A
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_0				0x033D
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_1				0x033E
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_2				0x033F
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_3				0x0340
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_4				0x0341
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_5				0x0342
+#define AD9694_REG_PAIR_MAP_DDC_1_TEST_ENABLE					0x0347
+#define AD9694_REG_CH_MAP_TEST_MODE_CTRL						0x0550
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_LSB					0x0551
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_MSB					0x0552
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_LSB					0x0553
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_MSB					0x0554
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_LSB					0x0555
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_MSB					0x0556
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_LSB					0x0557
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_MSB					0x0558
+#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_0					0x0559
+#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_1					0x055A
+#define AD9694_REG_PAIR_MAP_OUTPUT_SAMPLE_MODE					0x0561
+#define AD9694_REG_PAIR_MAP_OUTPUT_CH_SEL						0x0564
+#define AD9694_REG_JESD204B_MAP_PLL_CTRL						0x056E
+#define AD9694_REG_JESD204B_MAP_PLL_STAT						0x056F
+#define AD9694_REG_JESD204B_MAP_JTX_QUICK_CONF					0x0570
+#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_1					0x0571
+#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_2					0x0572
+#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_3					0x0573
+#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_4					0x0574
+#define AD9694_REG_JESD204B_MAP_JTX_LMFC_OFFSET					0x0578
+#define AD9694_REG_JESD204B_MAP_JTX_DID_CONF					0x0580
+#define AD9694_REG_JESD204B_MAP_JTX_BID_CONF					0x0581
+#define AD9694_REG_JESD204B_MAP_JTX_LID_0_CONF					0x0583
+#define AD9694_REG_JESD204B_MAP_JTX_LID_1_CONF					0x0585
+#define AD9694_REG_JESD204B_MAP_JTX_SCR_L_CONF					0x058B
+#define AD9694_REG_JESD204B_MAP_JTX_F_CONF						0x058C
+#define AD9694_REG_JESD204B_MAP_JTX_K_CONF						0x058D
+#define AD9694_REG_JESD204B_MAP_JTX_M_CONF						0x058E
+#define AD9694_REG_JESD204B_MAP_JTX_CS_N_CONF					0x058F
+#define AD9694_REG_JESD204B_MAP_JTX_SUBCLASS_CONF				0x0590
+#define AD9694_REG_JESD204B_MAP_JTX_S_CONF						0x0591
+#define AD9694_REG_JESD204B_MAP_JTX_HD_CF_CONF					0x0592
+#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_0_CONF				0x05A0
+#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_1_CONF				0x05A1
+#define AD9694_REG_SERDOUTX0_SERDOUTX1_LANE_PD					0x05B0
+#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_1				0x05B2
+#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_2				0x05B3
+#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_0					0x05C0
+#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_1					0x05C1
+#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_0					0x05C4
+#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_1					0x05C6
+#define AD9694_REG_LARGE_DITHER_CTRL							0x0922
+#define AD9694_REG_PLL_CAL										0x1222
+#define AD9694_REG_JESD204B_STARTUP_CIRCUIT_RST					0x1228
+#define AD9694_REG_PLL_LOSS_OF_LOCK_CTRL						0x1262
+#define AD9694_REG_DC_OFFSET_CAL_CTRL							0x0701
+#define AD9694_REG_DC_OFFSET_CAL_CTRL_2							0x073B
+#define AD9694_REG_PAIR_MAP_VREF_CTRL							0x18A6
+#define AD9694_REG_EXT_VCM_BUF_CTRL_1							0x18E0
+#define AD9694_REG_EXT_VCM_BUF_CTRL_2							0x18E1
+#define AD9694_REG_EXT_VCM_BUF_CTRL_3							0x18E2
+#define AD9694_REG_EXT_VCM_BUF_CTRL								0x18E3
+#define AD9694_REG_TEMP_DIODE_EXPORT							0x18E6
+#define AD9694_REG_CH_MAP_ANALOG_INPUT_CTRL						0x1908
+#define AD9694_REG_CH_MAP_INPUT_FULLSCALE_RANGE					0x1910
+#define AD9694_REG_CH_MAP_BUF_CTRL_1							0x1A4C
+#define AD9694_REG_CH_MAP_BUF_CTRL_2							0x1A4D
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+struct ad9694_dev {
+	/* SPI */
+	spi_desc	*spi_desc;
+};
+
+struct ad9694_init_param {
+	/* SPI */
+	spi_init_param	*spi_init;
+};
+
+struct ad9694_config {
+	uint16_t addr;
+	uint8_t value;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+int32_t ad9694_read(struct ad9694_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data);
+
+int32_t ad9694_write(struct ad9694_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data);
+
+int32_t ad9694_init(struct ad9694_dev **device,
+		     const struct ad9694_init_param *init_param);
+
+int32_t ad9694_remove(struct ad9694_dev *dev);
+
+#endif

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/api/gpio.c

@@ -0,0 +1,184 @@
+/***************************************************************************//**
+ *   @file   gpio.c
+ *   @brief  Implementation of the GPIO Interface
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2020(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include "../../include/gpio.h"
+#include "../../include/error.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Obtain the GPIO decriptor.
+ * @param desc - The GPIO descriptor.
+ * @param param - GPIO Initialization parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get(struct gpio_desc **desc,
+		 const struct gpio_init_param *param)
+{
+	if (!param)
+		return FAILURE;
+
+	if ((param->platform_ops->gpio_ops_get(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Get the value of an optional GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param param - GPIO Initialization parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_optional(struct gpio_desc **desc,
+			  const struct gpio_init_param *param)
+{
+	if (!param || (param->number == -1)) {
+		*desc = NULL;
+		return SUCCESS;
+	}
+
+	if ((param->platform_ops->gpio_ops_get_optional(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+/**
+ * @brief Free the resources allocated by gpio_get().
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_remove(struct gpio_desc *desc)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_remove(desc);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Enable the input direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_direction_input(struct gpio_desc *desc)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_direction_input(desc);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Enable the output direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_direction_output(struct gpio_desc *desc,
+			      uint8_t value)
+{
+	if (desc)
+		return desc->platform_ops->
+		       gpio_ops_direction_output(desc, value);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Get the direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param direction - The direction.
+ *                    Example: GPIO_OUT
+ *                             GPIO_IN
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_direction(struct gpio_desc *desc,
+			   uint8_t *direction)
+{
+	if (desc)
+		return desc->platform_ops->
+		       gpio_ops_get_direction(desc, direction);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Set the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_set_value(struct gpio_desc *desc,
+		       uint8_t value)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_set_value(desc, value);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Get the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_value(struct gpio_desc *desc,
+		       uint8_t *value)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_get_value(desc, value);
+	else
+		return SUCCESS;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/api/irq.c

@@ -0,0 +1,153 @@
+/***************************************************************************//**
+ *   @file   irq.c
+ *   @brief  Implementation of the IRQ Interface
+ *   @author Andrei Porumb ([email protected])
+********************************************************************************
+ * Copyright 2021(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include "../../include/irq.h"
+#include "../../include/error.h"
+
+/**
+ * @brief Initialize the IRQ interrupts.
+ * @param desc - The IRQ descriptor.
+ * @param param - The structure that contains the IRQ parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_ctrl_init(struct irq_ctrl_desc **desc,
+		      const struct irq_init_param *param)
+{
+	if (!param)
+		return FAILURE;
+
+	if ((param->platform_ops->init(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by irq_ctrl_init().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc)
+{
+	return desc->platform_ops->remove(desc);
+}
+
+/**
+ * @brief Register a callback to handle the irq events.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param callback_desc - Callback descriptor
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
+			      struct callback_desc *callback_desc)
+{
+	return desc->platform_ops->register_callback(desc, irq_id, callback_desc);
+}
+
+/**
+ * @brief Unregisters a generic IRQ handling function.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	return desc->platform_ops->unregister(desc, irq_id);
+}
+
+/**
+ * @brief Enable global interrupts.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_global_enable(struct irq_ctrl_desc *desc)
+{
+	return desc->platform_ops->global_enable(desc);
+}
+
+/**
+ * @brief Disable global interrupts.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_global_disable(struct irq_ctrl_desc *desc)
+{
+	return desc->platform_ops->global_disable(desc);
+}
+
+/**
+ * @brief Set interrupt trigger level.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param trig - New trigger level for the interrupt.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
+			      enum irq_trig_level trig)
+{
+	if(desc->platform_ops->trigger_level_set)
+		return desc->platform_ops->trigger_level_set(desc, irq_id, trig);
+	else
+		return ENOSYS;
+}
+
+/**
+ * @brief Enable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	return desc->platform_ops->enable(desc, irq_id);
+}
+
+/**
+ * @brief Disable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	return desc->platform_ops->disable(desc, irq_id);
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/api/spi.c

@@ -0,0 +1,144 @@
+/***************************************************************************//**
+ *   @file   spi.c
+ *   @brief  Implementation of the SPI Interface
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2020(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include "../../include/spi.h"
+#include "../../include/error.h"
+
+/**
+ * @brief Initialize the SPI communication peripheral.
+ * @param desc - The SPI descriptor.
+ * @param param - The structure that contains the SPI parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_init(struct spi_desc **desc,
+		 const struct spi_init_param *param)
+{
+	if (!param)
+		return FAILURE;
+
+	if ((param->platform_ops->init(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by spi_init().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_remove(struct spi_desc *desc)
+{
+	return desc->platform_ops->remove(desc);
+}
+
+/**
+ * @brief Write and read data to/from SPI.
+ * @param desc - The SPI descriptor.
+ * @param data - The buffer with the transmitted/received data.
+ * @param bytes_number - Number of bytes to write/read.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_write_and_read(struct spi_desc *desc,
+			   uint8_t *data,
+			   uint16_t bytes_number)
+{
+	return desc->platform_ops->write_and_read(desc, data, bytes_number);
+}
+
+/**
+ * @brief Write and read data to/from SPI in 3 wire mode.
+ * @param desc - The SPI descriptor.
+ * @param write_data - The buffer with the transmitted data.
+ * @param read_data - The buffer with the received data.
+ * @param write_bytes_number - Number of bytes to write.
+ * @param read_bytes_number - Number of bytes to read.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_write_and_read_3wire(struct spi_desc *desc,
+			   uint8_t *write_data,
+			   uint8_t *read_data,
+			   uint16_t write_bytes_number,
+			   uint16_t read_bytes_number)
+{
+	int ret;
+	if(desc->platform_ops->write_and_read_3wire != NULL){
+		return desc->platform_ops->write_and_read_3wire(desc, write_data, read_data,
+			write_bytes_number, read_bytes_number);
+	}
+	else{
+		return FAILURE;
+	}
+}
+
+
+/**
+ * @brief  Iterate over head list and send all spi messages
+ * @param desc - The SPI descriptor.
+ * @param msgs - Array of messages.
+ * @param len - Number of messages in the array.
+ * @return SUCCESS in case of success, negativ error code otherwise.
+ */
+int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len)
+{
+	int32_t  ret;
+	uint32_t i;
+
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (desc->platform_ops->transfer)
+		return desc->platform_ops->transfer(desc, msgs, len);
+
+	for (i = 0; i < len; i++) {
+		if (msgs[i].rx_buff != msgs[i].tx_buff || !msgs[i].tx_buff)
+			return -EINVAL;
+		ret = spi_write_and_read(desc, msgs[i].rx_buff,
+					 msgs[i].bytes_number);
+		if (IS_ERR_VALUE(ret))
+			return ret;
+	}
+
+	return SUCCESS;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c

@@ -0,0 +1,328 @@
+/***************************************************************************//**
+ *   @file   axi_dmac.c
+ *   @brief  Driver for the Analog Devices AXI-DMAC core.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include "../../../include/axi_io.h"
+#include "../../../include/error.h"
+#include "../axi_dmac/axi_dmac.h"
+
+/***************************************************************************//**
+ * @brief dma_isr
+*******************************************************************************/
+void axi_dmac_default_isr(void *instance)
+{
+	struct axi_dmac *dmac = (struct axi_dmac *)instance;
+	uint32_t remaining_size, burst_size;
+	uint32_t reg_val;
+
+	/* Get interrupt sources and clear interrupts. */
+	axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
+
+	if ((reg_val & AXI_DMAC_IRQ_SOT) && (dmac->big_transfer.size != 0)) {
+		remaining_size = dmac->big_transfer.size -
+				 dmac->big_transfer.size_done;
+		burst_size = (remaining_size <= dmac->transfer_max_size) ?
+			     remaining_size : dmac->transfer_max_size;
+
+		dmac->big_transfer.size_done += burst_size;
+		dmac->big_transfer.address += burst_size;
+		switch (dmac->direction) {
+		case DMA_DEV_TO_MEM:
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS,
+				       dmac->big_transfer.address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
+			break;
+		case DMA_MEM_TO_DEV:
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS,
+				       dmac->big_transfer.address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
+			break;
+		default:
+			return; // Other directions are not supported yet
+		}
+		/* The current transfer was started and a new one is queued. */
+		axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+			       burst_size);
+		axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+	}
+	if (reg_val & AXI_DMAC_IRQ_EOT) {
+		dmac->big_transfer.transfer_done = true;
+		dmac->big_transfer.address = 0;
+		dmac->big_transfer.size = 0;
+		dmac->big_transfer.size_done = 0;
+	}
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_read
+ *******************************************************************************/
+int32_t axi_dmac_read(struct axi_dmac *dmac,
+		      uint32_t reg_addr,
+		      uint32_t *reg_data)
+{
+	axi_io_read(dmac->base, reg_addr, reg_data);
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_write
+ *******************************************************************************/
+int32_t axi_dmac_write(struct axi_dmac *dmac,
+		       uint32_t reg_addr,
+		       uint32_t reg_data)
+{
+	axi_io_write(dmac->base, reg_addr, reg_data);
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_transfer_nonblock
+ *******************************************************************************/
+int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
+				      uint32_t address, uint32_t size)
+{
+	uint32_t reg_val;
+
+	if (size == 0)
+		return SUCCESS; /* nothing to do */
+
+	axi_dmac_read(dmac, AXI_DMAC_REG_CTRL, &reg_val);
+	if (!(reg_val & AXI_DMAC_CTRL_ENABLE)) {
+		axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
+		axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
+		axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
+	}
+
+	axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, &reg_val);
+	if (!(reg_val & 1)) {
+		switch (dmac->direction) {
+		case DMA_DEV_TO_MEM:
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
+			break;
+		case DMA_MEM_TO_DEV:
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
+			break;
+		default:
+			return FAILURE; // Other directions are not supported yet
+		}
+		if ((size - 1) > dmac->transfer_max_size) {
+			dmac->big_transfer.address = address;
+			dmac->big_transfer.size = size - 1;
+			dmac->big_transfer.size_done = dmac->transfer_max_size;
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+				       dmac->transfer_max_size);
+			axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+		} else {
+			axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+				       size - 1);
+			axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+		}
+	} else {
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_is_transfer_ready
+ *******************************************************************************/
+int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy)
+{
+	*rdy = dmac->big_transfer.transfer_done;
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_transfer
+ *******************************************************************************/
+int32_t axi_dmac_transfer(struct axi_dmac *dmac,
+			  uint32_t address, uint32_t size)
+{
+	uint32_t transfer_id;
+	uint32_t reg_val;
+	uint32_t timeout = 0;
+
+	if (size == 0)
+		return SUCCESS; /* nothing to do */
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
+	axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
+
+	axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID, &transfer_id);
+	axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
+
+	switch (dmac->direction) {
+	case DMA_DEV_TO_MEM:
+		axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
+		axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
+		break;
+	case DMA_MEM_TO_DEV:
+		axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
+		axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
+		break;
+	default:
+		return FAILURE; // Other directions are not supported yet
+	}
+
+	if ((size - 1) > dmac->transfer_max_size) {
+		dmac->big_transfer.address = address;
+		dmac->big_transfer.size = size - 1;
+		dmac->big_transfer.size_done = dmac->transfer_max_size;
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+			       dmac->transfer_max_size);
+		axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+
+		while(!dmac->big_transfer.transfer_done) {
+			timeout++;
+			if (timeout == UINT32_MAX)
+				return FAILURE;
+		}
+
+		dmac->big_transfer.address = 0;
+		dmac->big_transfer.size = 0;
+		dmac->big_transfer.size_done = 0;
+
+		return SUCCESS;
+	}
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, size - 1);
+	axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+
+	if (dmac->flags & DMA_CYCLIC)
+		return SUCCESS;
+
+	/* Wait until the new transfer is queued. */
+	do {
+		axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, &reg_val);
+	} while(reg_val == 1);
+
+	/* Wait until the current transfer is completed. */
+	do {
+		axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
+		if (reg_val == (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
+			break;
+	} while(!dmac->big_transfer.transfer_done);
+	if (reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
+		axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
+
+	/* Wait until the transfer with the ID transfer_id is completed. */
+	do {
+		axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE, &reg_val);
+	} while((reg_val & (1u << transfer_id)) != (1u << transfer_id));
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_init
+ *******************************************************************************/
+int32_t axi_dmac_init(struct axi_dmac **dmac_core,
+		      const struct axi_dmac_init *init)
+{
+	struct axi_dmac *dmac;
+
+	dmac = (struct axi_dmac *)malloc(sizeof(*dmac));
+	if (!dmac)
+		return FAILURE;
+
+	dmac->name = init->name;
+	dmac->base = init->base;
+	dmac->direction = init->direction;
+	dmac->flags = init->flags;
+	dmac->transfer_max_size = -1;
+	dmac->big_transfer.address = 0;
+	dmac->big_transfer.size = 0;
+	dmac->big_transfer.size_done = 0;
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, dmac->transfer_max_size);
+	axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH, &dmac->transfer_max_size);
+
+	*dmac_core = dmac;
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_remove
+ *******************************************************************************/
+int32_t axi_dmac_remove(struct axi_dmac *dmac)
+{
+	if(!dmac)
+		return FAILURE;
+
+	free(dmac);
+
+	return SUCCESS;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h

@@ -0,0 +1,124 @@
+/***************************************************************************//**
+ *   @file   axi_dmac.h
+ *   @brief  Driver for the Analog Devices AXI-DMAC core.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef AXI_DMAC_H_
+#define AXI_DMAC_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include "../../../include/util.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+#define AXI_DMAC_REG_IRQ_MASK		0x80
+#define AXI_DMAC_REG_IRQ_PENDING	0x84
+#define AXI_DMAC_IRQ_SOT			BIT(0)
+#define AXI_DMAC_IRQ_EOT			BIT(1)
+
+#define AXI_DMAC_REG_CTRL			0x400
+#define AXI_DMAC_CTRL_ENABLE		BIT(0)
+#define AXI_DMAC_CTRL_PAUSE			BIT(1)
+
+#define AXI_DMAC_REG_TRANSFER_ID	0x404
+#define AXI_DMAC_REG_START_TRANSFER	0x408
+#define AXI_DMAC_REG_FLAGS			0x40c
+#define AXI_DMAC_REG_DEST_ADDRESS	0x410
+#define AXI_DMAC_REG_SRC_ADDRESS	0x414
+#define AXI_DMAC_REG_X_LENGTH		0x418
+#define AXI_DMAC_REG_Y_LENGTH		0x41c
+#define AXI_DMAC_REG_DEST_STRIDE	0x420
+#define AXI_DMAC_REG_SRC_STRIDE		0x424
+#define AXI_DMAC_REG_TRANSFER_DONE	0x428
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+enum dma_direction {
+	DMA_DEV_TO_MEM,
+	DMA_MEM_TO_DEV
+};
+
+enum dma_flags {
+	DMA_CYCLIC = 1,
+	DMA_LAST = 2
+};
+
+struct axi_dma_transfer {
+	uint32_t size;
+	uint32_t address;
+	uint32_t size_done;
+	volatile bool transfer_done;
+};
+
+struct axi_dmac {
+	const char *name;
+	uint32_t base;
+	enum dma_direction direction;
+	uint32_t flags;
+	uint32_t transfer_max_size;
+	volatile struct axi_dma_transfer big_transfer;
+};
+
+struct axi_dmac_init {
+	const char *name;
+	uint32_t base;
+	enum dma_direction direction;
+	uint32_t flags;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+void axi_dmac_default_isr(void *instance);
+int32_t axi_dmac_read(struct axi_dmac *dmac, uint32_t reg_addr,
+		      uint32_t *reg_data);
+int32_t axi_dmac_write(struct axi_dmac *dmac, uint32_t reg_addr,
+		       uint32_t reg_data);
+int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
+				      uint32_t address, uint32_t size);
+int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy);
+int32_t axi_dmac_transfer(struct axi_dmac *dmac,
+			  uint32_t address, uint32_t size);
+int32_t axi_dmac_init(struct axi_dmac **adc_core,
+		      const struct axi_dmac_init *init);
+int32_t axi_dmac_remove(struct axi_dmac *dmac);
+
+#endif

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/axi_core/spi_engine/spi_engine.c

@@ -0,0 +1,978 @@
+/*******************************************************************************
+ *   @file   spi_engine.c
+ *   @brief  Core implementation of the SPI Engine Driver.
+ *   @author Sergiu Cuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+/* In debug mode the printf function used in displaying the messages is causing
+significant delays */
+//#define DEBUG_LEVEL 2
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sleep.h>
+#include <inttypes.h>
+
+#include "spi_engine.h"
+#include "../axi_dmac/axi_dmac.h"
+#include "../../../include/axi_io.h"
+#include "../../../include/error.h"
+
+/**
+ * @brief Spi engine platform specific SPI platform ops structure
+ */
+const struct spi_platform_ops spi_eng_platform_ops = {
+	.init = &spi_engine_init,
+	.write_and_read = &spi_engine_spi_write_and_read,
+	.write_and_read_3wire = &spi_engine_spi_write_and_read_3wire,
+	.remove = &spi_engine_remove
+};
+
+/******************************************************************************/
+/***************************** Static variables *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Static variable used to sync transfers
+ *
+ */
+static uint8_t _sync_id = 0x01;
+
+/******************************************************************************/
+/************************** Functions Implementation **************************/
+/******************************************************************************/
+
+/**
+ * @brief Write SPI Engine's axi registers
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param reg_addr The address of the SPI Engine's axi register where the data
+ * 	will be written
+ * @param reg_data Data that will be written
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_write(struct spi_engine_desc *desc,
+			 uint32_t reg_addr,
+			 uint32_t reg_data)
+{
+	axi_io_write(desc->spi_engine_baseaddr, reg_addr, reg_data);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Read SPI Engine's axi registers
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param reg_addr The address of the SPI Engine's axi register from where the
+ * 	data where the data will be read
+ * @param reg_data Pointer where the read that will be stored
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_read(struct spi_engine_desc *desc,
+			uint32_t reg_addr,
+			uint32_t *reg_data)
+{
+	axi_io_read(desc->spi_engine_baseaddr, reg_addr, reg_data);
+	return SUCCESS;
+}
+
+/**
+ * @brief Set width of the transferred word over SPI
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param data_width The desired data width
+ * 	The supported values are:
+ * 		- 8
+ * 		- 16
+ * 		- 24
+ * 		- 32
+ */
+int32_t spi_engine_set_transfer_width(struct spi_desc *desc,
+				      uint8_t data_width)
+{
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	if (data_width > desc_extra->max_data_width)
+		desc_extra->data_width = desc_extra->max_data_width;
+	else
+		desc_extra->data_width = data_width;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Set SPI engine clock frequency
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param speed_hz SPI engine transfer speed
+ */
+void spi_engine_set_speed(struct spi_desc *desc,
+			  uint32_t speed_hz)
+{
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	desc_extra->clk_div =  desc_extra->ref_clk_hz /
+			       (2 * speed_hz) - 1;
+}
+
+/**
+ * @brief Set the number of words transferred in a single transaction
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param bytes_number The number of bytes to be converted
+ * @return uint8_t A number of words in which bytes_number can be grouped
+ */
+static uint8_t spi_get_words_number(struct spi_engine_desc *desc,
+				    uint8_t bytes_number)
+{
+	uint8_t xfer_word_len;
+	uint8_t words_number;
+
+	xfer_word_len = desc->data_width / 8;
+	words_number = bytes_number / xfer_word_len;
+
+	if ((bytes_number % xfer_word_len) != 0)
+		words_number++;
+
+	return words_number;
+}
+
+/**
+ * @brief Get the word length in bytes
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @return uint8_t Number of bytes that fit in one word
+ */
+static uint8_t spi_get_word_length(struct spi_engine_desc *desc)
+{
+	uint8_t word_length;
+
+	word_length = desc->data_width / 8;
+
+	return word_length;
+}
+
+/**
+ * @brief Compute the prescaler used to set the sleep period.
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param sleep_time_ns The amount of time where the transfer hangs
+ * @param sleep_div Clock prescaler
+ * @return int32_t This function allways returns SUCCESS
+ */
+static int32_t spi_get_sleep_div(struct spi_desc *desc,
+				 uint32_t sleep_time_ns,
+				 uint32_t *sleep_div)
+{
+	struct spi_engine_desc	*eng_desc;
+
+	eng_desc = desc->extra;
+
+	/*
+	 * Engine Wiki:
+	 *
+	 * The frequency of the SCLK signal is derived from the
+	 * module clock frequency using the following formula:
+	 * f_sclk = f_clk / ((div + 1) * 2)
+	 */
+
+	*sleep_div = (desc->max_speed_hz / 1000000 * sleep_time_ns / 1000) /
+		     ((eng_desc->clk_div + 1) * 2) - 1;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Create a new commands queue used in a spi transfer
+ *
+ * @param fifo Command buffer, usually used in fifo mode
+ * @param cmd Command with witch the buffer will be initiated
+ * @return int32_t Failure if the memory allocation failed
+ */
+static int32_t spi_engine_queue_new_cmd(struct spi_engine_cmd_queue **fifo,
+					uint32_t cmd)
+{
+	struct spi_engine_cmd_queue *local_fifo;
+
+	local_fifo = (spi_engine_cmd_queue*)malloc(sizeof(*local_fifo));
+
+	if(!local_fifo)
+		return FAILURE;
+
+	local_fifo->cmd = cmd;
+	local_fifo->next = NULL;
+	*fifo = local_fifo;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Add a command at the end of an existing queue
+ *
+ * @param fifo Command buffer, usually used in fifo mode
+ * @param cmd Command to be added
+ */
+static void spi_engine_queue_add_cmd(struct spi_engine_cmd_queue **fifo,
+				     uint32_t cmd)
+{
+	struct spi_engine_cmd_queue *to_add = NULL;
+	struct spi_engine_cmd_queue *local_fifo;
+
+	local_fifo = *fifo;
+	while (local_fifo->next != NULL) {
+		// Get the last element
+		local_fifo = local_fifo->next;
+	}
+
+	// Create a new element
+	spi_engine_queue_new_cmd(&to_add, cmd);
+	// Add as the next element
+	local_fifo->next = to_add;
+}
+
+/**
+ * @brief Add a command at the beginning of an existing queue
+ *
+ * @param fifo Command buffer, usually used in fifo mode
+ * @param cmd Command to be added
+ */
+static void spi_engine_queue_append_cmd(struct spi_engine_cmd_queue **fifo,
+					uint32_t cmd)
+{
+	struct spi_engine_cmd_queue *to_add = NULL;
+
+	// Create a new element
+	spi_engine_queue_new_cmd(&to_add, cmd);
+	// Interchange the addresses
+	to_add->next = *fifo;
+	*fifo = to_add;
+}
+
+
+/**
+ * @brief Get the command from the beginning of the queue
+ *
+ * @param fifo Command buffer, usually used in fifo mode
+ * @param cmd Value of the command that was extracted
+ * @return int32_t Return FAILURE if the queue is empty
+ */
+static int32_t spi_engine_queue_get_cmd(struct spi_engine_cmd_queue **fifo,
+					uint32_t *cmd)
+{
+	struct spi_engine_cmd_queue *local_fifo;
+
+	if (!*fifo)
+		return FAILURE;
+
+	local_fifo = *fifo;
+	*cmd = local_fifo->cmd;
+	if ((*fifo)->next) {
+		*fifo = local_fifo->next;
+		free(local_fifo);
+	} else {
+		free(*fifo);
+		*fifo = NULL;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the memory allocated by a queue
+ *
+ * @param fifo The queue that needs it's memory freed
+ * @return int32_t This function allways return SUCCESS
+ */
+static int32_t spi_engine_queue_free(struct spi_engine_cmd_queue **fifo)
+{
+	if(*fifo && (*fifo)->next)
+		spi_engine_queue_free(&(*fifo)->next);
+	if((*fifo) != NULL) {
+		free(*fifo);
+		*fifo = NULL;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Write the SPI engine's command fifo
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param cmd The command that will be written
+ * @return int32_t Returns FAILURE if the the axi transfer failed
+ */
+static int32_t spi_engine_write_cmd_reg(struct spi_engine_desc *desc,
+					uint32_t cmd)
+{
+	int32_t ret;
+
+	/* Check if offload is enabled */
+	if(desc->offload_config & (OFFLOAD_TX_EN | OFFLOAD_RX_EN)) {
+		ret = spi_engine_write(desc,
+				       SPI_ENGINE_REG_OFFLOAD_CMD_MEM(0),
+				       cmd);
+
+	} else {
+		ret = spi_engine_write(desc,
+				       SPI_ENGINE_REG_CMD_FIFO,
+				       cmd);
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Write a transfer command to the SPI engine's command fifo
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param read_write Read/Write operation flag
+ * @param bytes_number Number of bytes to transfer
+ * @return int32_t This function allways returns SUCCESS
+ */
+static int32_t spi_engine_transfer(struct spi_engine_desc *desc,
+				   uint8_t read_write,
+				   uint8_t bytes_number)
+{
+	uint8_t words_number;
+
+	words_number = spi_get_words_number(desc, bytes_number);
+
+	desc->offload_tx_len += words_number;
+
+	/*
+	 * Engine Wiki:
+	 *
+	 * https://wiki.analog.com/resources/fpga/peripherals/spi_engine
+	 *
+	 * The words number is zero based
+	 */
+
+	spi_engine_write_cmd_reg(desc,
+				 SPI_ENGINE_CMD_TRANSFER(read_write,
+						 words_number  - 1));
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Change the state of the chip select port
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param assert Chip select state.
+ * 		 The supported values are :
+ * 			-true (HIGH)
+ * 			-false (LOW)
+ */
+static void spi_engine_set_cs(struct spi_desc *desc,
+			      bool assert)
+{
+	uint8_t			mask;
+	struct spi_engine_desc	*eng_desc;
+
+	eng_desc = desc->extra;
+
+	mask = 0xFF;
+	/* Switch the state only of the selected chip select */
+	if (!assert)
+		mask ^= BIT(desc->chip_select);
+
+	spi_engine_write_cmd_reg(eng_desc,
+				 SPI_ENGINE_CMD_ASSERT(eng_desc->cs_delay,
+						 mask));
+}
+
+/**
+ * @brief Add a delay between the engine commands
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param sleep_time_ns Number of nanoseconds to sleep between commands
+ */
+static void spi_gen_sleep_ns(struct spi_desc *desc,
+			     uint32_t sleep_time_ns)
+{
+	uint32_t 		sleep_div;
+	struct spi_engine_desc	*eng_desc;
+
+	eng_desc = desc->extra;
+
+	spi_get_sleep_div(desc, sleep_time_ns, &sleep_div);
+
+	spi_engine_write_cmd_reg(eng_desc, SPI_ENGINE_CMD_SLEEP(sleep_div));
+}
+
+/**
+ * @brief Spi engine command interpreter
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param cmd Command to send to the engine
+ * @return int32_t - SUCCESS if the command is transferred
+ *		   - FAILURE if the command format is invalid
+ */
+static int32_t spi_engine_write_cmd(struct spi_desc *desc,
+				    uint32_t cmd)
+{
+	uint8_t				engine_command;
+	uint8_t				parameter;
+	uint8_t				modifier;
+	struct spi_engine_desc		*desc_extra;
+
+	desc_extra = desc->extra;
+
+	engine_command = (cmd >> 12) & 0x0F;
+	modifier = (cmd >> 8) & 0x0F;
+	parameter = cmd & 0xFF;
+
+	switch(engine_command) {
+	case SPI_ENGINE_INST_TRANSFER:
+		spi_engine_transfer(desc_extra, modifier, parameter);
+		break;
+
+	case SPI_ENGINE_INST_ASSERT:
+		if(parameter == 0xFF) {
+			/* Set the CS HIGH */
+			spi_engine_set_cs(desc, true);
+		} else if(parameter == 0x00) {
+			/* Set the CS LOW */
+			spi_engine_set_cs(desc, false);
+		}
+		break;
+
+	/* The SYNC and SLEEP commands got the same value but different
+	modifier */
+	case SPI_ENGINE_INST_SYNC_SLEEP:
+		/* SYNC instruction */
+		if(modifier == 0x00) {
+			spi_engine_write_cmd_reg(desc_extra, cmd);
+		} else if(modifier == 0x01) {
+			spi_gen_sleep_ns(desc, parameter);
+		}
+		break;
+	case SPI_ENGINE_INST_CONFIG:
+		spi_engine_write_cmd_reg(desc_extra, cmd);
+
+		break;
+
+	default:
+
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Prepare the command queue before sending it to the engine
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param msg Structure used to store the transfer messages
+ * @return int32_t This function allways returns SUCCESS
+ */
+static int32_t spi_engine_compile_message(struct spi_desc *desc,
+		struct spi_engine_msg *msg)
+{
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	/* Configure the prescaler */
+	spi_engine_queue_append_cmd(&msg->cmds,
+				    SPI_ENGINE_CMD_CONFIG(
+					    SPI_ENGINE_CMD_REG_CLK_DIV,
+					    desc_extra->clk_div));
+
+	/* Set the data transfer length */
+	spi_engine_queue_append_cmd(&msg->cmds,
+				    SPI_ENGINE_CMD_CONFIG(
+					    SPI_ENGINE_CMD_DATA_TRANSFER_LEN,
+					    desc_extra->data_width));
+	/*
+	 * Configure the spi mode :
+	 *	- 3 wire
+	 *	- CPOL
+	 *	- CPHA
+	 */
+	spi_engine_queue_append_cmd(&msg->cmds,
+				    SPI_ENGINE_CMD_CONFIG(
+					    SPI_ENGINE_CMD_REG_CONFIG,
+					    desc->mode));
+
+	/* Add a sync command to signal that the transfer has finished */
+	spi_engine_queue_add_cmd(&msg->cmds, SPI_ENGINE_CMD_SYNC(_sync_id));
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Initiate a spi transfer (Blocking)
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param msg Structure used to store the transfer messages
+ * @return int32_t - SUCCESS if the transfer finished
+ *		   - FAILURE if the memory allocation failed
+ */
+static int32_t spi_engine_transfer_message(struct spi_desc *desc,
+		struct spi_engine_msg *msg)
+{
+	uint32_t		i;
+	uint32_t		data;
+	uint32_t		sync_id;
+	bool 			offload_en;
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	spi_engine_compile_message(desc, msg);
+
+	offload_en = (desc_extra->offload_config & OFFLOAD_TX_EN) |
+		     (desc_extra->offload_config & OFFLOAD_RX_EN);
+
+	/* Write the command fifo buffer */
+	while(msg->cmds != NULL) {
+		spi_engine_queue_get_cmd(&msg->cmds, &data);
+		spi_engine_write_cmd(desc, data);
+	}
+
+	/* Write a number of tx_length WORDS on the SDO line */
+	if(offload_en) {
+		for(i = 0; i < desc_extra->offload_tx_len; i++)
+			spi_engine_write(desc_extra,
+					 SPI_ENGINE_REG_OFFLOAD_SDO_MEM(0),
+					 msg->tx_buf[i]);
+
+	} else {
+		if(msg->tx_buf != NULL){
+			for(i = 0; i < msg->tx_length; i++)
+			spi_engine_write(desc_extra,
+					 SPI_ENGINE_REG_SDO_DATA_FIFO,
+					 msg->tx_buf[i]);
+		}
+		do {
+			spi_engine_read(desc_extra,
+					SPI_ENGINE_REG_SYNC_ID,
+					&sync_id);
+		}
+		/* Wait for the end sync signal */
+		while(sync_id != _sync_id);
+		_sync_id++;
+
+		/* Read a number of rx_length WORDS from the SDI line and store
+		them */
+		for(i = 0; i < msg->rx_length; i++) {
+			spi_engine_read(desc_extra,
+					SPI_ENGINE_REG_SDI_DATA_FIFO,
+					&data);
+			/* Store the rx data if rx buffer valid, flush sdi_fifo if
+			rx buffer is invalid.*/
+			if(msg->rx_buf != NULL){
+				msg->rx_buf[i] = data;
+			}
+		}
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Initialize the spi engine
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param param Structure containing the spi init parameters
+ * @return int32_t - SUCCESS if the transfer finished
+ *		   - FAILURE if the memory allocation failed
+ */
+int32_t spi_engine_init(struct spi_desc **desc,
+			const struct spi_init_param *param)
+{
+	uint32_t			data_width = 0;
+	uint32_t			spi_engine_version = 0;
+	struct spi_engine_desc		*eng_desc;
+	struct spi_engine_init_param	*spi_engine_init;
+
+	if (!param) {
+		return FAILURE;
+	}
+
+	*desc = malloc(sizeof(**desc));
+	if(! *desc) {
+		free(*desc);
+		return FAILURE;
+	}
+
+	eng_desc = (struct spi_engine_desc*)malloc(sizeof(*eng_desc));
+
+	if (!eng_desc)
+		return FAILURE;
+
+	spi_engine_init = param->extra;
+
+	(*desc)->max_speed_hz = param->max_speed_hz;
+	(*desc)->chip_select = param->chip_select;
+	(*desc)->mode = param->mode;
+	(*desc)->extra = eng_desc;
+
+	eng_desc->offload_config = OFFLOAD_DISABLED;
+	eng_desc->spi_engine_baseaddr = spi_engine_init->spi_engine_baseaddr;
+	eng_desc->type = spi_engine_init->type;
+	eng_desc->cs_delay = spi_engine_init->cs_delay;
+	eng_desc->ref_clk_hz = spi_engine_init->ref_clk_hz;
+	eng_desc->clk_div =  eng_desc->ref_clk_hz /
+			     (2 * param->max_speed_hz) - 1;
+
+	/* Perform a reset */
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x01);
+	usleep(1000);
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x00);
+
+	/* Get current data width */
+	spi_engine_read(eng_desc, SPI_ENGINE_REG_DATA_WIDTH, &data_width);
+	eng_desc->max_data_width = data_width;
+
+	spi_engine_set_transfer_width(*desc, spi_engine_init->data_width);
+
+	/* Get spi engine version */
+	spi_engine_read(eng_desc, SPI_ENGINE_REG_VERSION, &spi_engine_version);
+
+	printf("Spi engine v%"PRIu32".%"PRIu32".%"PRIu32" successfully initialized.\n",
+	       (spi_engine_version >> 16),
+	       ((spi_engine_version >> 8) & 0xFF),
+	       (spi_engine_version & 0xFF));
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Write and read on the spi interface in 4-wire mode (full-duplex)
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param data Pointer to data buffer
+ * @param bytes_number Number of bytes to transfer
+ * @return int32_t - SUCCESS if the transfer finished
+ *		   - FAILURE if the memory allocation or transfer failed
+ */
+int32_t spi_engine_spi_write_and_read(struct spi_desc *desc,
+				  uint8_t *data,
+				  uint16_t bytes_number)
+{
+	uint8_t 		word_len;
+	uint8_t 		words_number;
+	int32_t 		ret;
+	struct spi_engine_msg	msg;
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	/* If we want to access SPI interface and SPI engine offload module was
+	 * activated, we need to disable it
+	 * This is set in spi_engine_offload_init() */
+	desc_extra->offload_config = OFFLOAD_DISABLED;
+	/* This is set in spi_engine_offload_transfer() */
+	spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0);
+
+	words_number = spi_get_words_number(desc_extra, bytes_number);
+
+	msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds));
+	if (!msg.cmds)
+		return FAILURE;
+
+	msg.tx_buf =(uint32_t*)calloc(words_number, sizeof(msg.tx_buf[0]));
+	msg.rx_buf =(uint32_t*)calloc(words_number, sizeof(msg.rx_buf[0]));
+	msg.tx_length = words_number;
+	msg.rx_length = words_number;
+
+	/* Get the length of transferred word */
+	word_len = spi_get_word_length(desc_extra);
+
+	/* Make sure the CS is HIGH before starting a transaction */
+	msg.cmds->next = NULL;
+	msg.cmds->cmd = CS_HIGH;
+	// Assert select.
+	spi_engine_queue_add_cmd(&msg.cmds, CS_LOW);
+	// add read/write command
+	spi_engine_queue_add_cmd(&msg.cmds, WRITE_READ(bytes_number));
+	// Disable select.
+	spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH);
+
+	/* Pack the bytes into engine WORDS */
+	for (int i = 0; i < bytes_number; i++)
+		msg.tx_buf[i / word_len] |= data[i] << (desc_extra->data_width-
+							(i % word_len + 1) * 8);
+
+	ret = spi_engine_transfer_message(desc, &msg);
+
+	for (int i = 0; i < bytes_number; i++)
+	data[i] = msg.rx_buf[(i) / word_len] >>
+		  (desc_extra->data_width -
+		   ((i) % word_len + 1) * 8);
+	
+	spi_engine_queue_free(&msg.cmds);
+	free(msg.tx_buf);
+	free(msg.rx_buf);
+
+	return ret;
+}
+
+/**
+ * @brief Write and read on the spi interface in 3-wire mode (half-duplex)
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param data Pointer to data buffer
+ * @param bytes_number Number of bytes to transfer
+ * @return int32_t - SUCCESS if the transfer finished
+ *		   - FAILURE if the memory allocation or transfer failed
+ */
+int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc,
+		   uint8_t *write_data,
+		   uint8_t *read_data,
+		   uint16_t write_bytes_number,
+		   uint16_t read_bytes_number)
+{
+	uint8_t 		word_len;
+	uint8_t 		wr_words_number;
+	uint8_t 		rd_words_number;
+	int32_t 		ret;
+	struct spi_engine_msg	msg;
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	/* If we want to access SPI interface and SPI engine offload module was
+	 * activated, we need to disable it
+	 * This is set in spi_engine_offload_init() */
+	desc_extra->offload_config = OFFLOAD_DISABLED;
+	/* This is set in spi_engine_offload_transfer() */
+	spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0);
+
+	wr_words_number = spi_get_words_number(desc_extra, write_bytes_number);
+	rd_words_number = spi_get_words_number(desc_extra, read_bytes_number);
+
+	msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds));
+	if (!msg.cmds)
+		return FAILURE;
+
+	msg.tx_buf =(wr_words_number>0)?(uint32_t*)calloc(wr_words_number, sizeof(msg.tx_buf[0])):NULL;
+	msg.rx_buf =(rd_words_number>0)?(uint32_t*)calloc(rd_words_number, sizeof(msg.rx_buf[0])):NULL;
+	msg.tx_length = wr_words_number;
+	msg.rx_length = rd_words_number;
+
+	/* Get the length of transferred word */
+	word_len = spi_get_word_length(desc_extra);
+
+	/* Make sure the CS is HIGH before starting a transaction */
+	msg.cmds->next = NULL;
+	msg.cmds->cmd = CS_HIGH;
+
+	// Assert select.
+	spi_engine_queue_add_cmd(&msg.cmds, CS_LOW);
+
+	// add read/write command
+	if(write_bytes_number > 0)
+	spi_engine_queue_add_cmd(&msg.cmds, WRITE(write_bytes_number));
+	if(read_bytes_number > 0)
+	spi_engine_queue_add_cmd(&msg.cmds, READ(read_bytes_number));
+
+	// Disable select.
+	spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH);
+
+	/* Pack the bytes into engine WORDS */
+	for (int i = 0; i < write_bytes_number; i++)
+		msg.tx_buf[i / word_len] |= write_data[i] << (desc_extra->data_width-
+							(i % word_len + 1) * 8);
+
+	ret = spi_engine_transfer_message(desc, &msg);
+
+	for (int i = 0; i < read_bytes_number; i++)
+		read_data[i] = msg.rx_buf[(i) / word_len] >>
+		  (desc_extra->data_width -
+		   ((i) % word_len + 1) * 8);
+
+	spi_engine_queue_free(&msg.cmds);
+	free(msg.tx_buf);
+	free(msg.rx_buf);
+
+	return ret;
+}
+
+/**
+ * @brief Initialize the SPI engine's offload module
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param param Structure containing the offload init parameters
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_offload_init(struct spi_desc *desc,
+				const struct spi_engine_offload_init_param *param)
+{
+	struct spi_engine_desc	*eng_desc;
+	struct axi_dmac_init	dmac_init;
+	uint32_t dma_flags;
+
+	eng_desc = desc->extra;
+
+	eng_desc->offload_config = param->offload_config;
+
+	if(!(param->dma_flags))
+		dma_flags = DMA_CYCLIC;
+	else
+		dma_flags = *(param->dma_flags);
+
+	if(param->offload_config & OFFLOAD_TX_EN) {
+		dmac_init.name = "DAC DMAC";
+		dmac_init.base = param->tx_dma_baseaddr;
+		dmac_init.direction = DMA_MEM_TO_DEV;
+		dmac_init.flags = dma_flags;
+		axi_dmac_init(&eng_desc->offload_tx_dma, &dmac_init);
+		if(!eng_desc->offload_tx_dma)
+			return FAILURE;
+	}
+	if(param->offload_config & OFFLOAD_RX_EN) {
+		dmac_init.name = "ADC DMAC";
+		dmac_init.base = param->rx_dma_baseaddr;
+		dmac_init.direction = DMA_DEV_TO_MEM;
+		dmac_init.flags = dma_flags;
+		axi_dmac_init(&eng_desc->offload_rx_dma, &dmac_init);
+		if(!eng_desc->offload_rx_dma)
+			return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Initiate a SPI transfer in offload mode
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param msg Offload message that get's to be transferred
+ * @param no_samples Number of time the messages will be transferred
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_offload_transfer(struct spi_desc *desc,
+				    struct spi_engine_offload_message msg,
+				    uint32_t no_samples)
+{
+	struct spi_engine_msg	transfer;
+	struct spi_engine_desc	*eng_desc;
+	uint32_t 		i;
+	uint8_t 		word_length;
+
+	eng_desc = desc->extra;
+
+	/* Check if offload is disabled */
+	if(!((eng_desc->offload_config & OFFLOAD_TX_EN) |
+	     (eng_desc->offload_config & OFFLOAD_RX_EN)))
+		return FAILURE;
+
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 1);
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 0);
+
+	eng_desc->offload_tx_len = 0;
+	eng_desc->offload_rx_len = 0;
+
+	transfer.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*transfer.cmds));
+
+	if (!transfer.cmds)
+		return FAILURE;
+
+	transfer.tx_buf = msg.commands_data;
+
+	/* Load the commands into the message */
+	transfer.cmds->next = NULL;
+	transfer.cmds->cmd = msg.commands[0];
+	i = 1;
+	while(i < msg.no_commands) {
+		spi_engine_queue_add_cmd(&transfer.cmds, msg.commands[i++]);
+
+	}
+
+	spi_engine_transfer_message(desc, &transfer);
+
+	/* Start transfer */
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0x0001);
+
+	word_length = spi_get_word_length(eng_desc);
+	if(eng_desc->offload_config & OFFLOAD_TX_EN) {
+		axi_dmac_transfer(eng_desc->offload_tx_dma,
+				  msg.tx_addr,
+				  word_length * eng_desc->offload_tx_len *
+				  no_samples);
+	}
+
+	if(eng_desc->offload_config & OFFLOAD_RX_EN) {
+		axi_dmac_transfer(eng_desc->offload_rx_dma,
+				  msg.rx_addr,
+				  word_length * eng_desc->offload_tx_len *
+				  no_samples);
+	}
+
+	usleep(1000);
+
+	spi_engine_queue_free(&transfer.cmds);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by spi_init().
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_remove(struct spi_desc *desc)
+{
+	struct spi_engine_desc	*eng_desc;
+
+	eng_desc = desc->extra;
+
+	if(eng_desc->offload_config & OFFLOAD_TX_EN)
+		axi_dmac_remove(eng_desc->offload_tx_dma);
+	if(eng_desc->offload_config & OFFLOAD_RX_EN)
+		axi_dmac_remove(eng_desc->offload_rx_dma);
+	free(desc->extra);
+	free(desc);
+
+	return SUCCESS;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/axi_core/spi_engine/spi_engine.h

@@ -0,0 +1,231 @@
+/*******************************************************************************
+ *   @file   spi_engine.h
+ *   @brief  Header file of SPI Engine core features.
+ *   @author Sergiu Cuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef SPI_ENGINE_H
+#define SPI_ENGINE_H
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+#include "spi_engine_private.h"
+#include "../../platform/spi_extra.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define OFFLOAD_DISABLED		0x00
+#define OFFLOAD_TX_EN			BIT(0)
+#define OFFLOAD_RX_EN			BIT(1)
+#define OFFLOAD_TX_RX_EN		OFFLOAD_TX_EN | OFFLOAD_RX_EN
+
+#define SPI_ENGINE_MSG_QUEUE_END	0xFFFFFFFF
+
+/* Spi engine commands */
+#define	WRITE_OR_READ(mode, no_bytes)	((SPI_ENGINE_INST_TRANSFER << 12) |\
+((mode) << 8) | (no_bytes))
+
+#define	WRITE(no_bytes)			((SPI_ENGINE_INST_TRANSFER << 12) |\
+	(SPI_ENGINE_INSTRUCTION_TRANSFER_W << 8) | (no_bytes))
+
+#define	READ(no_bytes)			((SPI_ENGINE_INST_TRANSFER << 12) |\
+	(SPI_ENGINE_INSTRUCTION_TRANSFER_R << 8) | (no_bytes))
+
+#define	WRITE_READ(no_bytes)		((SPI_ENGINE_INST_TRANSFER << 12) |\
+	(SPI_ENGINE_INSTRUCTION_TRANSFER_RW << 8) | (no_bytes))
+
+
+
+#define SLEEP(time)			SPI_ENGINE_CMD_SLEEP(time & 0xF)
+
+/* The delay and chip select parmeters are passed over the engine descriptor
+and will be used inside the function call */
+#define CS_HIGH			SPI_ENGINE_CMD_ASSERT(0x00, 0xFF)
+#define CS_LOW			SPI_ENGINE_CMD_ASSERT(0x00, 0x00)
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @struct spi_engine_init_param
+ * @brief  Structure containing the init parameters needed by the SPI engine
+ */
+struct spi_engine_init_param {
+	/** SPI engine reference clock */
+	uint32_t	ref_clk_hz;
+	/** Type of implementation */
+	enum xil_spi_type	type;
+	/** Base address where the HDL core is situated */
+	uint32_t 		spi_engine_baseaddr;
+	/** Delay between the CS toggle and the start of SCLK */
+	uint32_t		cs_delay;
+	/** Data with of one SPI transfer ( in bits ) */
+	uint8_t			data_width;
+};
+
+
+/**
+ * @struct spi_engine_desc
+ * @brief  Structure representing an SPI engine device
+ */
+struct spi_engine_desc {
+	/** SPI engine reference clock */
+	uint32_t	ref_clk_hz;
+	/** Type of implementation */
+	enum xil_spi_type	type;
+	/** Pointer to a DMAC used in transmission */
+	struct axi_dmac		*offload_tx_dma;
+	/** Pointer to a DMAC used in reception */
+	struct axi_dmac		*offload_rx_dma;
+	/** Offload's module transfer direction : TX, RX or both */
+	uint8_t			offload_config;
+	/** Number of words that the module has to send */
+	uint8_t			offload_tx_len;
+	/** Number of words that the module has to receive */
+	uint8_t			offload_rx_len;
+	/** Base address where the HDL core is situated */
+	uint32_t		spi_engine_baseaddr;
+	/** Base address where the RX DMAC core is situated */
+	uint32_t		rx_dma_baseaddr;
+	/** Base address where the TX DMAC core is situated */
+	uint32_t		tx_dma_baseaddr;
+	/** Delay between the CS toggle and the start of SCLK */
+	uint8_t			cs_delay;
+	/** Clock divider used in transmission delays */
+	uint32_t		clk_div;
+	/** Data with of one SPI transfer ( in bits ) */
+	uint8_t			data_width;
+	/** The maximum data width supported by the engine */
+	uint8_t 		max_data_width;
+};
+
+
+/**
+ * @struct spi_engine_offload_init_param
+ * @brief  Structure containing the init parameters needed by the offload module
+ */
+struct spi_engine_offload_init_param {
+	/** Base address where the RX DMAC core is situated */
+	uint32_t	rx_dma_baseaddr;
+	/** Base address where the TX DMAC core is situated */
+	uint32_t	tx_dma_baseaddr;
+	/** DMAC flags - if not initialized, the default value is DMA_CYCLIC */
+	uint32_t	*dma_flags;
+	/** Offload's module transfer direction : TX, RX or both */
+	uint8_t		offload_config;
+};
+
+/**
+ * @struct spi_engine_offload_message
+ * @brief  Structure representing an offload message
+ */
+struct spi_engine_offload_message {
+	/** Pointer to the SPI engine commands buffer that will be sent.
+	 * The available commands can be found at:
+	 * https://wiki.analog.com/resources/fpga/peripherals/spi_engine/
+	*/
+	uint32_t *commands;
+	/** Length of the SPI engine commands buffer */
+	uint32_t no_commands;
+	/** Pointer of the data that will be sent over spi */
+	uint32_t *commands_data;
+	/** The address where the data that will be transmitted is situated */
+	uint32_t tx_addr;
+	/** The address where the data that will be received is situated */
+	uint32_t rx_addr;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/**
+ * @brief Spi engine platform specific SPI platform ops structure
+ */
+extern const struct spi_platform_ops xil_spi_ops;
+
+/* Write SPI Engine's axi registers */
+int32_t spi_engine_write(struct spi_engine_desc *desc,
+			 uint32_t reg_addr,
+			 uint32_t reg_data);
+
+/* Read SPI Engine's axi registers */
+int32_t spi_engine_read(struct spi_engine_desc *desc,
+			uint32_t reg_addr,
+			uint32_t *reg_data);
+/* Initialize the SPI engine device */
+int32_t spi_engine_init(struct spi_desc **desc,
+			const struct spi_init_param *param);
+
+/* Write and read data over SPI using the SPI engine */
+int32_t spi_engine_spi_write_and_read(struct spi_desc *desc,
+				  uint8_t *data,
+				  uint16_t bytes_number);
+
+/* Write and read data over SPI using the SPI engine in 3-wire mode */
+int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc,
+		   uint8_t *write_data,
+		   uint8_t *read_data,
+		   uint16_t write_bytes_number,
+		   uint16_t read_bytes_number);
+/* Free the resources used by the SPI engine device */
+int32_t spi_engine_remove(struct spi_desc *desc);
+
+/* Initialize the SPI engine offload module */
+int32_t spi_engine_offload_init(struct spi_desc *desc,
+				const struct spi_engine_offload_init_param *param);
+
+/* Write and read data over SPI using the offload module */
+int32_t spi_engine_offload_transfer(struct spi_desc *desc,
+				    struct spi_engine_offload_message msg,
+				    uint32_t no_samples);
+
+/* Set SPI transfer width */
+int32_t spi_engine_set_transfer_width(struct spi_desc *desc,
+				      uint8_t data_wdith);
+
+/* Set SPI transfer speed */
+void spi_engine_set_speed(struct spi_desc *desc,
+			  uint32_t speed_hz);
+
+#endif // SPI_ENGINE_H

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h

@@ -0,0 +1,154 @@
+/*******************************************************************************
+ *   @file   spi_engine_private.h
+ *   @brief  Private definitions of the SPI Engine
+ *   @author Sergiu Cuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef SPI_ENGINE_PRIVATE_H
+#define SPI_ENGINE_PRIVATE_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "../../../include/spi.h"
+#include "../../../include/util.h"
+
+/******************************************************************************/
+/*************************** Spi Engine registers *****************************/
+/******************************************************************************/
+
+#define SPI_ENGINE_REG_VERSION			0x00
+#define SPI_ENGINE_REG_DATA_WIDTH		0x0C
+#define SPI_ENGINE_REG_RESET			0x40
+#define SPI_ENGINE_REG_INT_ENABLE		0x80
+#define SPI_ENGINE_REG_INT_PENDING		0x84
+#define SPI_ENGINE_REG_INT_SOURCE		0x88
+#define SPI_ENGINE_REG_SYNC_ID			0xC0
+#define SPI_ENGINE_REG_CMD_FIFO_ROOM		0xD0
+#define SPI_ENGINE_REG_SDO_FIFO_ROOM		0xD4
+#define SPI_ENGINE_REG_SDI_FIFO_LEVEL		0xD8
+#define SPI_ENGINE_REG_CMD_FIFO 		0xE0
+#define SPI_ENGINE_REG_SDO_DATA_FIFO		0xE4
+#define SPI_ENGINE_REG_SDI_DATA_FIFO		0xE8
+#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK	0xEC
+
+/******************************************************************************/
+/************************ Spi Engine register parameters **********************/
+/******************************************************************************/
+
+#define SPI_ENGINE_INST_TRANSFER		0x00
+#define SPI_ENGINE_INST_ASSERT			0x01
+#define SPI_ENGINE_INST_CONFIG			0x02
+#define SPI_ENGINE_INST_SYNC_SLEEP		0x03
+#define SPI_ENGINE_INST_MISC			0x03
+#define SPI_ENGINE_CMD_REG_CLK_DIV		0x00
+#define SPI_ENGINE_CMD_REG_CONFIG		0x01
+#define SPI_ENGINE_CMD_DATA_TRANSFER_LEN	0x02
+#define SPI_ENGINE_MISC_SYNC			0x00
+#define SPI_ENGINE_MISC_SLEEP			0x01
+#define SPI_ENGINE_SYNC_TRANSFER_BEGIN		BIT(1)
+#define SPI_ENGINE_SYNC_TRANSFER_END		BIT(2)
+#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY		BIT(0)
+#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY		BIT(1)
+#define SPI_ENGINE_INT_SDI_ALMOST_FULL		BIT(2)
+#define SPI_ENGINE_INT_SYNC			BIT(3)
+#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE		BIT(0)
+#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED	BIT(0)
+#define SPI_ENGINE_CONFIG_CPHA			BIT(0)
+#define SPI_ENGINE_CONFIG_CPOL			BIT(1)
+#define SPI_ENGINE_CONFIG_3WIRE			BIT(2)
+#define SPI_ENGINE_VERSION_MAJOR(x) 		((x >> 16) & 0xff)
+#define SPI_ENGINE_VERSION_MINOR(x) 		((x >> 8) & 0xff)
+#define SPI_ENGINE_VERSION_PATCH(x) 		(x & 0xff)
+
+/******************************************************************************/
+/**************************** Spi Engine commands *****************************/
+/******************************************************************************/
+
+#define SPI_ENGINE_INSTRUCTION_TRANSFER_W	0x01
+#define SPI_ENGINE_INSTRUCTION_TRANSFER_R	0x02
+#define SPI_ENGINE_INSTRUCTION_TRANSFER_RW	0x03
+
+#define SPI_ENGINE_REG_OFFLOAD_CTRL(x)		(0x100 + (0x20 * x))
+#define SPI_ENGINE_REG_OFFLOAD_STATUS(x)	(0x104 + (0x20 * x))
+#define SPI_ENGINE_REG_OFFLOAD_RESET(x)		(0x108 + (0x20 * x))
+#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM(x)	(0x110 + (0x20 * x))
+#define SPI_ENGINE_REG_OFFLOAD_SDO_MEM(x)	(0x114 + (0x20 * x))
+
+#define SPI_ENGINE_CMD(inst, arg1, arg2) 				\
+			(((inst & 0x03) << 12) | 			\
+			((arg1 & 0x03) << 8) | arg2 )
+
+#define SPI_ENGINE_CMD_TRANSFER(readwrite, n)				\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER,			\
+			(readwrite), (n))
+
+#define SPI_ENGINE_CMD_ASSERT(delay, cs) 				\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT,				\
+			(delay), (cs))
+
+#define SPI_ENGINE_CMD_CONFIG(reg, val)					\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_CONFIG,				\
+			(reg), (val))
+
+#define SPI_ENGINE_CMD_SLEEP(delay) 					\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, 				\
+			SPI_ENGINE_MISC_SLEEP, 				\
+			(delay))
+
+#define SPI_ENGINE_CMD_SYNC(id) 					\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, 				\
+			SPI_ENGINE_MISC_SYNC, 				\
+			(id))
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+typedef struct spi_engine_cmd_queue {
+	uint32_t	cmd;
+	struct		spi_engine_cmd_queue *next;
+} spi_engine_cmd_queue;
+
+typedef struct spi_engine_msg {
+	uint32_t			*tx_buf;
+	uint32_t			*rx_buf;
+	uint32_t			tx_length;
+	uint32_t			rx_length;
+	struct spi_engine_cmd_queue	*cmds;
+} spi_engine_msg;
+
+#endif // SPI_ENGINE_PRIVATE_H

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/frequency/lmk04828/lmk04828.c

@@ -0,0 +1,128 @@
+/***************************************************************************//**
+ * @file lmk04828.c
+ * @brief Implementation of AD9680 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdlib.h>
+#include <stdio.h>
+#include "lmk04828.h"
+#include "../../../include/error.h"
+
+/***************************************************************************//**
+ * @brief lmk04828_read
+ *******************************************************************************/
+int32_t lmk04828_read(struct lmk04828_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data)
+{
+	uint8_t tx_buf[2];
+	uint8_t rx_buf[1];
+	int32_t ret;
+
+	tx_buf[0] = 0x80 | (reg_addr >> 8);
+	tx_buf[1] = reg_addr & 0xFF;
+
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+			tx_buf, rx_buf, 2, 1);
+
+	*reg_data = rx_buf[0];
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief lmk04828_write
+ *******************************************************************************/
+int32_t lmk04828_write(struct lmk04828_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data)
+{
+	uint8_t buf[3];
+
+	int32_t ret;
+
+	buf[0] = reg_addr >> 8;
+	buf[1] = reg_addr & 0xFF;
+	buf[2] = reg_data;
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+				 buf, NULL, 3, 0);
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief lmk04828_init
+ *******************************************************************************/
+int32_t lmk04828_init(struct lmk04828_dev **device,
+		     const struct lmk04828_init_param *init_param)
+{
+	int ret = SUCCESS;
+	struct lmk04828_dev *dev;
+
+	dev = (struct lmk04828_dev *)malloc(sizeof(*dev));
+	if (!dev)
+		return FAILURE;
+
+	/* SPI */
+	ret = spi_init(&dev->spi_desc, init_param->spi_init);
+
+	*device = dev;
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief Free the resources allocated by lmk04828_setup().
+ *
+ * @param dev - The device structure.
+ *
+ * @return SUCCESS in case of success, negative error code otherwise.
+*******************************************************************************/
+int32_t lmk04828_remove(struct lmk04828_dev *dev)
+{
+	int32_t ret;
+
+	ret = spi_remove(dev->spi_desc);
+
+	free(dev);
+
+	return ret;
+}

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/frequency/lmk04828/lmk04828.h

@@ -0,0 +1,89 @@
+/***************************************************************************//**
+ * @file lmk04828.h
+ * @brief Header file of lmk04828 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+#ifndef LMK04828_H_
+#define LMK04828_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include "../../../include/delay.h"
+#include "../../../include/spi.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+struct lmk04828_dev {
+	/* SPI */
+	spi_desc	*spi_desc;
+};
+
+struct lmk04828_init_param {
+	/* SPI */
+	spi_init_param	*spi_init;
+};
+
+struct lmk04828_config {
+	uint16_t addr;
+	uint8_t value;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+int32_t lmk04828_read(struct lmk04828_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data);
+
+int32_t lmk04828_write(struct lmk04828_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data);
+
+int32_t lmk04828_init(struct lmk04828_dev **device,
+		     const struct lmk04828_init_param *init_param);
+
+int32_t lmk04828_remove(struct lmk04828_dev *dev);
+
+#endif

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/platform/axi_io.c

@@ -0,0 +1,79 @@
+/***************************************************************************//**
+ *   @file   xilinx/axi_io.c
+ *   @brief  Implementation of Xilinx AXI IO.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <xil_io.h>
+#include "../../include/error.h"
+#include "../../include/axi_io.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief AXI IO Xilinx specific read function.
+ * @param base - Base address
+ * @param offset - Address offset
+ * @param data - variable where returned data is stored
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
+{
+	*data = Xil_In32(base + offset);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief AXI IO Xilinx specific write function.
+ * @param base - Base address
+ * @param offset - Address offset
+ * @param data - data to be written.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
+{
+	Xil_Out32(base + offset, data);
+
+	return SUCCESS;
+}
+

rfsoc_eval_demo/vitis_classic_autobuild/source_mts/adi_noos/drivers/platform/delay.c

@@ -0,0 +1,77 @@
+/***************************************************************************//**
+ *   @file   xilinx/delay.c
+ *   @brief  Implementation of Xilinx Delay Functions.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include "../../include/delay.h"
+#include <sleep.h>
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Generate microseconds delay.
+ * @param usecs - Delay in microseconds.
+ * @return None.
+ */
+void udelay(uint32_t usecs)
+{
+#ifdef _XPARAMETERS_PS_H_
+	usleep(usecs);
+#else
+	usleep(usecs / 20);	// FIXME
+#endif
+}
+
+/**
+ * @brief Generate miliseconds delay.
+ * @param msecs - Delay in miliseconds.
+ * @return None.
+ */
+void mdelay(uint32_t msecs)
+{
+#ifdef _XPARAMETERS_PS_H_
+	usleep(msecs * 1000);
+#else
+	usleep(msecs * 50);	// FIXME
+#endif
+}