diff --git a/rfsoc_eval_300M/rfsoc_eval_300M.runs/impl_1/system_top.bit b/rfsoc_eval_300M/rfsoc_eval_300M.runs/impl_1/system_top.bit index 39227bb..ee339d8 100644 --- a/rfsoc_eval_300M/rfsoc_eval_300M.runs/impl_1/system_top.bit +++ b/rfsoc_eval_300M/rfsoc_eval_300M.runs/impl_1/system_top.bit @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:11c61b903fd90b07a89b3a1f833ab670210592920986a5e3417b4febb12f04b2 +oid sha256:5ca2e7e5c20304aefb321b2adc53fa353e56fc2a7593943a2eea48a5951fceab size 34437474 diff --git a/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sim_1/new/tb_tx_qpsk.v b/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sim_1/new/tb_tx_qpsk.v index dd83afa..1d50d2a 100644 --- a/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sim_1/new/tb_tx_qpsk.v +++ b/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sim_1/new/tb_tx_qpsk.v @@ -64,4 +64,33 @@ initial begin #103 aresetn = 1'b1; end +integer i; +integer w_file; + +initial begin + + w_file = $fopen("./../../qpsk_sim.txt","w"); + + i = 0; + + forever begin + + @(posedge aclk) + $fdisplay(w_file,"%d,%d,%d,%d", + $signed(u_tx_qpsk_poly2.hrc_wave_i_tdata_1), + $signed(u_tx_qpsk_poly2.hrc_wave_i_tdata_2), + $signed(u_tx_qpsk_poly2.hrc_wave_q_tdata_1), + $signed(u_tx_qpsk_poly2.hrc_wave_q_tdata_2)); + + i = i + 1; + + if (i == 35000) begin + $fclose(w_file); + $stop; + end + + end + +end + endmodule diff --git a/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sources_1/ip/hrc_2_12_025.xcix b/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sources_1/ip/hrc_2_12_025.xcix deleted file mode 100644 index 828ed06..0000000 Binary files a/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sources_1/ip/hrc_2_12_025.xcix and /dev/null differ diff --git a/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sources_1/ip/hrc_2_12_025/hrc_2_12_025.xci b/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sources_1/ip/hrc_2_12_025/hrc_2_12_025.xci new file mode 100644 index 0000000..5416cb4 --- /dev/null +++ b/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sources_1/ip/hrc_2_12_025/hrc_2_12_025.xci @@ -0,0 +1,350 @@ +{ + "schema": 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"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_data_tlast_unexpected_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_data_chanid_incorrect_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_config_tlast_missing_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_config_tlast_unexpected_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_reload_tlast_missing_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_reload_tlast_unexpected_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "aclk_intf": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + }, + "aresetn_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "aclken_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "S_AXIS_DATA": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "slave", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "s_axis_data_tdata" } ], + "TREADY": [ { "physical_name": "s_axis_data_tready" } ], + "TVALID": [ { "physical_name": "s_axis_data_tvalid" } ] + } + }, + "M_AXIS_DATA": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "m_axis_data_tdata" } ], + "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sources_1/new/tx_qpsk.v b/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sources_1/new/tx_qpsk.v index 599ccce..8035f75 100644 --- a/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sources_1/new/tx_qpsk.v +++ b/rfsoc_eval_300M/rfsoc_eval_300M.srcs/sources_1/new/tx_qpsk.v @@ -22,8 +22,10 @@ module tx_qpsk_poly2 #( - parameter POLYNOMIAL = "PRBS23", - parameter DATA_WIDTH = 16 // need to be <= 16 + parameter DATA_WIDTH = 16, // need to be <= 16 + parameter BIT_DATA = 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// inverse pseudorandom bit sequence, [0,flip(PRSB7)] + parameter BIT_DATA_LEN = 8192, + parameter SQUARE_INTERP = 8 ) ( // clock & reset @@ -41,6 +43,9 @@ module tx_qpsk_poly2 m_axis_tdata ); +localparam RCOS_INTERP = 2; +localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP; + //////////////////////////////////////////////////////////////////////////////// ////////////////////////// Top Level Port Declaration ////////////////////////// //////////////////////////////////////////////////////////////////////////////// @@ -60,28 +65,56 @@ input m_axis_tready; output [63:0] m_axis_tdata; //////////////////////////////////////////////////////////////////////////////// -////////////////////////////// Bit Data Generator ////////////////////////////// +///////////////////////////////// Data Counter ///////////////////////////////// //////////////////////////////////////////////////////////////////////////////// -// 1.5 Msps m sequence generator -wire m_seq_1m5_valid; -wire m_seq_1m5_ready; -wire [1:0] m_seq_tdata; -wire [7:0] m_seq_axis_tdata; +// symbol & interpolation counter +reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0; -assign m_seq_tdata = m_seq_axis_tdata[1:0]; +always @(posedge aclk) begin + if (!aresetn) begin + cnt <= 'b0; + end + else begin + cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1; + end +end -m_seq_gen #( - .POLYNOMIAL(POLYNOMIAL), - .BIT_WIDTH(2) -) -u_m_seq_gen -( - .aclk (aclk ), - .aresetn (aresetn ), - .m_axis_tvalid (m_seq_valid ), - .m_axis_tready (m_seq_ready ), - .m_axis_tdata (m_seq_axis_tdata ) -); +// address +reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0; +reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1; + +always @(posedge aclk) begin + if (!aresetn) begin + hrc_data_addr_i <= 'b0; + hrc_data_addr_q <= 'b1; + end + else begin + hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0}; + hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1}; + end +end + +// bit data +reg hrc_data_i = 'b0; +reg hrc_data_q = 'b0; + +always @(posedge aclk) begin + if (!aresetn) begin + hrc_data_i <= 'b0; + hrc_data_q <= 'b0; + end + else begin + hrc_data_i <= BIT_DATA[hrc_data_addr_i]; + hrc_data_q <= BIT_DATA[hrc_data_addr_q]; + end +end + +// polarization +wire [ 7:0] hrc_data_polar_i; +wire [ 7:0] hrc_data_polar_q; + +assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1}; +assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1}; //////////////////////////////////////////////////////////////////////////////// //////////////////////////////// Shaping Filter //////////////////////////////// @@ -105,14 +138,12 @@ wire [17:0] hrc_wave_q_tdata_2; wire [47:0] hrc_wave_q_axis_tdata; assign hrc_data_i_valid = 1'b1; -assign m_seq_ready = hrc_data_i_ready; -assign hrc_data_i_tdata = {{7{m_seq_tdata[0]}},1'b1}; +assign hrc_data_i_tdata = hrc_data_polar_i; assign hrc_wave_i_tdata_1 = hrc_wave_i_axis_tdata[0 +: 18]; assign hrc_wave_i_tdata_2 = hrc_wave_i_axis_tdata[24 +: 18]; assign hrc_data_q_valid = 1'b1; -// assign m_seq_ready = hrc_data_q_ready; -assign hrc_data_q_tdata = {{7{m_seq_tdata[1]}},1'b1}; +assign hrc_data_q_tdata = hrc_data_polar_q; assign hrc_wave_q_tdata_1 = hrc_wave_q_axis_tdata[0 +: 18]; assign hrc_wave_q_tdata_2 = hrc_wave_q_axis_tdata[24 +: 18]; @@ -161,10 +192,10 @@ always @(posedge aclk) begin baseband_sel_q_2 <= {hrc_wave_q_tdata_2[16:0],1'b0}; end 2'd1: begin - baseband_sel_q_1 <= {hrc_wave_q_tdata_1[16:0],1'b0}; - baseband_sel_i_1 <= {hrc_wave_i_tdata_1[16:0],1'b0}; - baseband_sel_q_2 <= {hrc_wave_q_tdata_2[16:0],1'b0}; - baseband_sel_i_2 <= {hrc_wave_i_tdata_2[16:0],1'b0}; + baseband_sel_i_1 <= {hrc_wave_q_tdata_1[16:0],1'b0}; + baseband_sel_q_1 <= {hrc_wave_i_tdata_1[16:0],1'b0}; + baseband_sel_i_2 <= {hrc_wave_q_tdata_2[16:0],1'b0}; + baseband_sel_q_2 <= {hrc_wave_i_tdata_2[16:0],1'b0}; end 2'd2: begin baseband_sel_i_1 <= 18'b01_1111_1111_1111_1111; diff --git a/rfsoc_eval_300M/rfsoc_eval_300M.srcs/utils_1/imports/synth_1/system_top.dcp b/rfsoc_eval_300M/rfsoc_eval_300M.srcs/utils_1/imports/synth_1/system_top.dcp index 668d3c4..0d9a339 100644 --- a/rfsoc_eval_300M/rfsoc_eval_300M.srcs/utils_1/imports/synth_1/system_top.dcp +++ b/rfsoc_eval_300M/rfsoc_eval_300M.srcs/utils_1/imports/synth_1/system_top.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:06ef0b35c250ab2aa029df3d2d16ea6bb681b8289e7902122b2f55fbf1487752 -size 219445 +oid sha256:16d1de7149fd8f74ef0cb099cd1c5a5ea0e3abd106b405d8a6cdcb2734a4e1f7 +size 219057 diff --git a/rfsoc_eval_300M/rfsoc_eval_300M.xpr b/rfsoc_eval_300M/rfsoc_eval_300M.xpr index 38e11a9..4d6131b 100644 --- a/rfsoc_eval_300M/rfsoc_eval_300M.xpr +++ b/rfsoc_eval_300M/rfsoc_eval_300M.xpr @@ -59,20 +59,20 @@