diff --git a/rfsoc_eval_nco/rfsoc_eval_nco.runs/impl_1/system_top.bit b/rfsoc_eval_nco/rfsoc_eval_nco.runs/impl_1/system_top.bit index 3bb7e86..855728f 100644 --- a/rfsoc_eval_nco/rfsoc_eval_nco.runs/impl_1/system_top.bit +++ b/rfsoc_eval_nco/rfsoc_eval_nco.runs/impl_1/system_top.bit @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c2892a491d0b87e56c5e5eebb481fb4e3516aad76e231e439ecf239a7e93120e +oid sha256:74818f867e89af9d2e59f9fa52c7a6bd2817b98ed2dd10fed1d9ac55f9fcf69b size 34437474 diff --git a/rfsoc_eval_nco/rfsoc_eval_nco.srcs/sources_1/bd/system_ps/ip/system_ps_usp_rf_data_converter_0_0/system_ps_usp_rf_data_converter_0_0.xci b/rfsoc_eval_nco/rfsoc_eval_nco.srcs/sources_1/bd/system_ps/ip/system_ps_usp_rf_data_converter_0_0/system_ps_usp_rf_data_converter_0_0.xci index 877318f..f367b45 100644 --- a/rfsoc_eval_nco/rfsoc_eval_nco.srcs/sources_1/bd/system_ps/ip/system_ps_usp_rf_data_converter_0_0/system_ps_usp_rf_data_converter_0_0.xci +++ b/rfsoc_eval_nco/rfsoc_eval_nco.srcs/sources_1/bd/system_ps/ip/system_ps_usp_rf_data_converter_0_0/system_ps_usp_rf_data_converter_0_0.xci @@ -25,7 +25,7 @@ "DAC231_En": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "ADC_Debug": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "DAC_Debug": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "DAC_Output_Current": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DAC_Output_Current": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "DAC_VOP_Mode": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "ADC_RTS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "DAC_RTS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -887,7 +887,7 @@ "C_Converter_Setup": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ADC_Debug": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], "C_DAC_Debug": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], - "C_DAC_Output_Current": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DAC_Output_Current": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_DAC_VOP_Mode": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_DAC_RTS": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], "C_ADC_RTS": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], diff --git a/rfsoc_eval_nco/rfsoc_eval_nco.srcs/sources_1/bd/system_ps/system_ps.bd b/rfsoc_eval_nco/rfsoc_eval_nco.srcs/sources_1/bd/system_ps/system_ps.bd index 5d67007..f6dd7d5 100644 --- a/rfsoc_eval_nco/rfsoc_eval_nco.srcs/sources_1/bd/system_ps/system_ps.bd +++ b/rfsoc_eval_nco/rfsoc_eval_nco.srcs/sources_1/bd/system_ps/system_ps.bd @@ -4722,7 +4722,7 @@ "value": "1" }, "DAC_Output_Current": { - "value": "0" + "value": "1" }, "DAC_Slice00_Enable": { "value": "true" diff --git a/rfsoc_eval_nco/rfsoc_eval_nco.srcs/sources_1/bd/system_ps/ui/bd_59931e13.ui b/rfsoc_eval_nco/rfsoc_eval_nco.srcs/sources_1/bd/system_ps/ui/bd_59931e13.ui index 1854cb5..3ed60bd 100644 --- a/rfsoc_eval_nco/rfsoc_eval_nco.srcs/sources_1/bd/system_ps/ui/bd_59931e13.ui +++ b/rfsoc_eval_nco/rfsoc_eval_nco.srcs/sources_1/bd/system_ps/ui/bd_59931e13.ui @@ -5,27 +5,27 @@ "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS # -string -flagsOSRD -preplace port sysref_in -pg 1 -lvl 0 -x 0 -y 1150 -defaultsOSRD -preplace port vin0_01 -pg 1 -lvl 0 -x 0 -y 990 -defaultsOSRD -preplace port vin0_23 -pg 1 -lvl 0 -x 0 -y 1010 -defaultsOSRD -preplace port vin1_01 -pg 1 -lvl 0 -x 0 -y 1030 -defaultsOSRD -preplace port vin1_23 -pg 1 -lvl 0 -x 0 -y 1050 -defaultsOSRD +preplace port sysref_in -pg 1 -lvl 0 -x -10 -y 1150 -defaultsOSRD +preplace port vin0_01 -pg 1 -lvl 0 -x -10 -y 990 -defaultsOSRD +preplace port vin0_23 -pg 1 -lvl 0 -x -10 -y 1010 -defaultsOSRD +preplace port vin1_01 -pg 1 -lvl 0 -x -10 -y 1030 -defaultsOSRD +preplace port vin1_23 -pg 1 -lvl 0 -x -10 -y 1050 -defaultsOSRD preplace port vout00 -pg 1 -lvl 4 -x 1490 -y 1220 -defaultsOSRD preplace port vout02 -pg 1 -lvl 4 -x 1490 -y 1240 -defaultsOSRD preplace port vout10 -pg 1 -lvl 4 -x 1490 -y 1260 -defaultsOSRD preplace port vout12 -pg 1 -lvl 4 -x 1490 -y 1280 -defaultsOSRD -preplace port s00_axis -pg 1 -lvl 0 -x 0 -y 790 -defaultsOSRD -preplace port s10_axis -pg 1 -lvl 0 -x 0 -y 830 -defaultsOSRD -preplace port s02_axis -pg 1 -lvl 0 -x 0 -y 810 -defaultsOSRD -preplace port s12_axis -pg 1 -lvl 0 -x 0 -y 850 -defaultsOSRD +preplace port s00_axis -pg 1 -lvl 0 -x -10 -y 790 -defaultsOSRD +preplace port s10_axis -pg 1 -lvl 0 -x -10 -y 830 -defaultsOSRD +preplace port s02_axis -pg 1 -lvl 0 -x -10 -y 810 -defaultsOSRD +preplace port s12_axis -pg 1 -lvl 0 -x -10 -y 850 -defaultsOSRD preplace port m02_axis -pg 1 -lvl 4 -x 1490 -y 940 -defaultsOSRD preplace port m10_axis -pg 1 -lvl 4 -x 1490 -y 980 -defaultsOSRD preplace port m12_axis -pg 1 -lvl 4 -x 1490 -y 1020 -defaultsOSRD preplace port m11_axis -pg 1 -lvl 4 -x 1490 -y 1000 -defaultsOSRD preplace port m00_axis -pg 1 -lvl 4 -x 1490 -y 900 -defaultsOSRD preplace port m13_axis -pg 1 -lvl 4 -x 1490 -y 1040 -defaultsOSRD -preplace port adc1_clk -pg 1 -lvl 0 -x 0 -y 950 -defaultsOSRD -preplace port dac0_clk -pg 1 -lvl 0 -x 0 -y 970 -defaultsOSRD +preplace port adc1_clk -pg 1 -lvl 0 -x -10 -y 950 -defaultsOSRD +preplace port dac0_clk -pg 1 -lvl 0 -x -10 -y 970 -defaultsOSRD preplace port m20_axis -pg 1 -lvl 4 -x 1490 -y 1060 -defaultsOSRD preplace port m21_axis -pg 1 -lvl 4 -x 1490 -y 1080 -defaultsOSRD preplace port m32_axis -pg 1 -lvl 4 -x 1490 -y 1180 -defaultsOSRD @@ -34,51 +34,51 @@ preplace port m22_axis -pg 1 -lvl 4 -x 1490 -y 1100 -defaultsOSRD preplace port m23_axis -pg 1 -lvl 4 -x 1490 -y 1120 -defaultsOSRD preplace port m30_axis -pg 1 -lvl 4 -x 1490 -y 1140 -defaultsOSRD preplace port m33_axis -pg 1 -lvl 4 -x 1490 -y 1200 -defaultsOSRD -preplace port vin2_01 -pg 1 -lvl 0 -x 0 -y 1070 -defaultsOSRD -preplace port vin2_23 -pg 1 -lvl 0 -x 0 -y 1090 -defaultsOSRD -preplace port vin3_01 -pg 1 -lvl 0 -x 0 -y 1110 -defaultsOSRD -preplace port vin3_23 -pg 1 -lvl 0 -x 0 -y 1130 -defaultsOSRD +preplace port vin2_01 -pg 1 -lvl 0 -x -10 -y 1070 -defaultsOSRD +preplace port vin2_23 -pg 1 -lvl 0 -x -10 -y 1090 -defaultsOSRD +preplace port vin3_01 -pg 1 -lvl 0 -x -10 -y 1110 -defaultsOSRD +preplace port vin3_23 -pg 1 -lvl 0 -x -10 -y 1130 -defaultsOSRD preplace port m03_axis -pg 1 -lvl 4 -x 1490 -y 960 -defaultsOSRD preplace port m01_axis -pg 1 -lvl 4 -x 1490 -y 920 -defaultsOSRD -preplace port s20_axis -pg 1 -lvl 0 -x 0 -y 870 -defaultsOSRD -preplace port s22_axis -pg 1 -lvl 0 -x 0 -y 890 -defaultsOSRD -preplace port s30_axis -pg 1 -lvl 0 -x 0 -y 910 -defaultsOSRD -preplace port s32_axis -pg 1 -lvl 0 -x 0 -y 930 -defaultsOSRD +preplace port s20_axis -pg 1 -lvl 0 -x -10 -y 870 -defaultsOSRD +preplace port s22_axis -pg 1 -lvl 0 -x -10 -y 890 -defaultsOSRD +preplace port s30_axis -pg 1 -lvl 0 -x -10 -y 910 -defaultsOSRD +preplace port s32_axis -pg 1 -lvl 0 -x -10 -y 930 -defaultsOSRD preplace port vout20 -pg 1 -lvl 4 -x 1490 -y 1300 -defaultsOSRD preplace port vout22 -pg 1 -lvl 4 -x 1490 -y 1320 -defaultsOSRD preplace port vout30 -pg 1 -lvl 4 -x 1490 -y 1340 -defaultsOSRD preplace port vout32 -pg 1 -lvl 4 -x 1490 -y 1360 -defaultsOSRD preplace port spi -pg 1 -lvl 4 -x 1490 -y 480 -defaultsOSRD -preplace port dac0_nco -pg 1 -lvl 0 -x 0 -y 1170 -defaultsOSRD -preplace port dac1_nco -pg 1 -lvl 0 -x 0 -y 1190 -defaultsOSRD -preplace port dac2_nco -pg 1 -lvl 0 -x 0 -y 1210 -defaultsOSRD -preplace port dac3_nco -pg 1 -lvl 0 -x 0 -y 1230 -defaultsOSRD -preplace port adc0_nco -pg 1 -lvl 0 -x 0 -y 1250 -defaultsOSRD -preplace port adc1_nco -pg 1 -lvl 0 -x 0 -y 1270 -defaultsOSRD -preplace port adc2_nco -pg 1 -lvl 0 -x 0 -y 1290 -defaultsOSRD -preplace port adc3_nco -pg 1 -lvl 0 -x 0 -y 1310 -defaultsOSRD -preplace port hop_ram -pg 1 -lvl 0 -x 0 -y 340 -defaultsOSRD -preplace port vp_vn -pg 1 -lvl 0 -x 0 -y 100 -defaultsOSRD +preplace port dac0_nco -pg 1 -lvl 0 -x -10 -y 1170 -defaultsOSRD +preplace port dac1_nco -pg 1 -lvl 0 -x -10 -y 1190 -defaultsOSRD +preplace port dac2_nco -pg 1 -lvl 0 -x -10 -y 1210 -defaultsOSRD +preplace port dac3_nco -pg 1 -lvl 0 -x -10 -y 1230 -defaultsOSRD +preplace port adc0_nco -pg 1 -lvl 0 -x -10 -y 1250 -defaultsOSRD +preplace port adc1_nco -pg 1 -lvl 0 -x -10 -y 1270 -defaultsOSRD +preplace port adc2_nco -pg 1 -lvl 0 -x -10 -y 1290 -defaultsOSRD +preplace port adc3_nco -pg 1 -lvl 0 -x -10 -y 1310 -defaultsOSRD +preplace port hop_ram -pg 1 -lvl 0 -x -10 -y 340 -defaultsOSRD +preplace port vp_vn -pg 1 -lvl 0 -x -10 -y 100 -defaultsOSRD preplace port port-id_spi_active -pg 1 -lvl 4 -x 1490 -y 500 -defaultsOSRD -preplace port port-id_m0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1390 -defaultsOSRD -preplace port port-id_s1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1570 -defaultsOSRD -preplace port port-id_s0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1550 -defaultsOSRD -preplace port port-id_m0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1370 -defaultsOSRD -preplace port port-id_s0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1530 -defaultsOSRD -preplace port port-id_m1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1430 -defaultsOSRD -preplace port port-id_m1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1410 -defaultsOSRD -preplace port port-id_s1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1590 -defaultsOSRD +preplace port port-id_m0_axis_aclk -pg 1 -lvl 0 -x -10 -y 1390 -defaultsOSRD +preplace port port-id_s1_axis_aresetn -pg 1 -lvl 0 -x -10 -y 1570 -defaultsOSRD +preplace port port-id_s0_axis_aclk -pg 1 -lvl 0 -x -10 -y 1550 -defaultsOSRD +preplace port port-id_m0_axis_aresetn -pg 1 -lvl 0 -x -10 -y 1370 -defaultsOSRD +preplace port port-id_s0_axis_aresetn -pg 1 -lvl 0 -x -10 -y 1530 -defaultsOSRD +preplace port port-id_m1_axis_aclk -pg 1 -lvl 0 -x -10 -y 1430 -defaultsOSRD +preplace port port-id_m1_axis_aresetn -pg 1 -lvl 0 -x -10 -y 1410 -defaultsOSRD +preplace port port-id_s1_axis_aclk -pg 1 -lvl 0 -x -10 -y 1590 -defaultsOSRD preplace port port-id_ps_clk0 -pg 1 -lvl 4 -x 1490 -y 220 -defaultsOSRD -preplace port port-id_m2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1470 -defaultsOSRD -preplace port port-id_m2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1450 -defaultsOSRD -preplace port port-id_m3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1510 -defaultsOSRD -preplace port port-id_m3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1490 -defaultsOSRD -preplace port port-id_s2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1610 -defaultsOSRD -preplace port port-id_s2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1630 -defaultsOSRD -preplace port port-id_s3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1650 -defaultsOSRD -preplace port port-id_s3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1670 -defaultsOSRD -preplace port port-id_user_sysref_adc -pg 1 -lvl 0 -x 0 -y 20 -defaultsOSRD -preplace port port-id_user_sysref_dac -pg 1 -lvl 0 -x 0 -y 40 -defaultsOSRD +preplace port port-id_m2_axis_aclk -pg 1 -lvl 0 -x -10 -y 1470 -defaultsOSRD +preplace port port-id_m2_axis_aresetn -pg 1 -lvl 0 -x -10 -y 1450 -defaultsOSRD +preplace port port-id_m3_axis_aclk -pg 1 -lvl 0 -x -10 -y 1510 -defaultsOSRD +preplace port port-id_m3_axis_aresetn -pg 1 -lvl 0 -x -10 -y 1490 -defaultsOSRD +preplace port port-id_s2_axis_aresetn -pg 1 -lvl 0 -x -10 -y 1610 -defaultsOSRD +preplace port port-id_s2_axis_aclk -pg 1 -lvl 0 -x -10 -y 1630 -defaultsOSRD +preplace port port-id_s3_axis_aresetn -pg 1 -lvl 0 -x -10 -y 1650 -defaultsOSRD +preplace port port-id_s3_axis_aclk -pg 1 -lvl 0 -x -10 -y 1670 -defaultsOSRD +preplace port port-id_user_sysref_adc -pg 1 -lvl 0 -x -10 -y 20 -defaultsOSRD +preplace port port-id_user_sysref_dac -pg 1 -lvl 0 -x -10 -y 40 -defaultsOSRD preplace portBus ps_rstn -pg 1 -lvl 4 -x 1490 -y 700 -defaultsOSRD preplace inst axi_spi_engine -pg 1 -lvl 3 -x 1260 -y 500 -defaultsOSRD preplace inst rst_ps8_96M -pg 1 -lvl 3 -x 1260 -y 660 -defaultsOSRD @@ -101,7 +101,7 @@ preplace netloc m2_axis_aclk_0_1 1 0 2 NJ 1470 N preplace netloc m2_axis_aresetn_0_1 1 0 2 NJ 1450 N preplace netloc m3_axis_aclk_0_1 1 0 2 NJ 1510 N preplace netloc m3_axis_aresetn_0_1 1 0 2 NJ 1490 N -preplace netloc rst_ps8_96M_peripheral_aresetn1 1 0 4 20 110 350 110 1050 760 1470 +preplace netloc rst_ps8_96M_peripheral_aresetn1 1 0 4 50 110 350 120 1050 760 1470 preplace netloc s0_axis_aclk_0_1 1 0 2 NJ 1550 N preplace netloc s0_axis_aresetn_0_1 1 0 2 NJ 1530 N preplace netloc s1_axis_aclk_0_1 1 0 2 NJ 1590 N @@ -112,11 +112,11 @@ preplace netloc s3_axis_aclk_0_1 1 0 2 N 1670 N preplace netloc s3_axis_aresetn_0_1 1 0 2 N 1650 N preplace netloc system_management_ip2intc_irpt 1 3 1 1460 60n preplace netloc usp_rf_data_converter_irq 1 2 2 N 1540 1440 -preplace netloc xlconcat_irq_dout 1 1 2 380 1730 1020 -preplace netloc zynq_ultra_ps_e_pl_clk0 1 0 4 40 600 370 120 1080J 220 NJ +preplace netloc xlconcat_irq_dout 1 1 2 380 1730 1030 +preplace netloc zynq_ultra_ps_e_pl_clk0 1 0 4 30 80 370 110 1080J 220 NJ preplace netloc zynq_ultra_ps_e_pl_resetn0 1 2 1 1040 230n preplace netloc BRAM_PORTB_0_1 1 0 1 N 340 -preplace netloc Vp_Vn_0_1 1 0 3 NJ 100 NJ 100 NJ +preplace netloc Vp_Vn_0_1 1 0 3 10J 90 NJ 90 1080J preplace netloc adc0_nco_0_1 1 0 2 N 1250 N preplace netloc adc1_clk_1 1 0 2 N 950 N preplace netloc adc1_nco_0_1 1 0 2 N 1270 N @@ -131,9 +131,9 @@ preplace netloc dac2_nco_0_1 1 0 2 N 1210 N preplace netloc dac3_nco_0_1 1 0 2 N 1230 N preplace netloc ps8_axi_periph_M00_AXI 1 2 1 N 470 preplace netloc ps8_axi_periph_M01_AXI 1 1 2 390 710 1010 -preplace netloc ps8_axi_periph_M02_AXI 1 0 3 30 80 NJ 80 1020 +preplace netloc ps8_axi_periph_M02_AXI 1 0 3 20 70 NJ 70 1030 preplace netloc ps8_axi_periph_M03_AXI 1 2 1 1060 80n -preplace netloc ps8_axi_periph_M04_AXI 1 0 3 50 90 NJ 90 1030 +preplace netloc ps8_axi_periph_M04_AXI 1 0 3 40 100 NJ 100 1020 preplace netloc s00_axis_0_1 1 0 2 NJ 790 N preplace netloc s02_axis_0_1 1 0 2 NJ 810 N preplace netloc s10_axis_0_1 1 0 2 NJ 830 N @@ -176,8 +176,8 @@ preplace netloc vin2_23_0_1 1 0 2 N 1090 N preplace netloc vin3_01_0_1 1 0 2 N 1110 N preplace netloc vin3_23_0_1 1 0 2 N 1130 N preplace netloc zynq_ultra_ps_e_M_AXI_HPM0_FPD 1 1 2 390 140 1010 -levelinfo -pg 1 0 200 700 1260 1490 -pagesize -pg 1 -db -bbox -sgen -170 0 1630 1740 +levelinfo -pg 1 -10 200 700 1260 1490 +pagesize -pg 1 -db -bbox -sgen -180 0 1630 1740 " } { diff --git a/rfsoc_eval_nco/rfsoc_eval_nco.srcs/utils_1/imports/synth_1/system_top.dcp b/rfsoc_eval_nco/rfsoc_eval_nco.srcs/utils_1/imports/synth_1/system_top.dcp index 793c41e..612cfb2 100644 --- a/rfsoc_eval_nco/rfsoc_eval_nco.srcs/utils_1/imports/synth_1/system_top.dcp +++ b/rfsoc_eval_nco/rfsoc_eval_nco.srcs/utils_1/imports/synth_1/system_top.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ce9573a9949e386d7ebf696ca5c74bee9d41243fc72274cce5aff54b88ab3007 -size 493167 +oid sha256:4b0eee7fce266ea40039e3de3e71b1a544afbe677b78c0ca9e28814155535228 +size 493652 diff --git a/rfsoc_eval_nco/rfsoc_eval_nco.xpr b/rfsoc_eval_nco/rfsoc_eval_nco.xpr index df4fce2..99a0768 100644 --- a/rfsoc_eval_nco/rfsoc_eval_nco.xpr +++ b/rfsoc_eval_nco/rfsoc_eval_nco.xpr @@ -740,9 +740,7 @@ - - Vivado Synthesis Defaults - + @@ -1127,9 +1125,7 @@ - - Default settings for Implementation. - + diff --git a/rfsoc_eval_nco/system_top.xsa b/rfsoc_eval_nco/system_top.xsa index abb73f9..a313720 100644 --- a/rfsoc_eval_nco/system_top.xsa +++ b/rfsoc_eval_nco/system_top.xsa @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:17850daafe95f98a02d871228b066a87ad56ac9355dc9990e7bee1da6aacc40e -size 3007129 +oid sha256:2666a7be9462f366a63a0bb4948625605456d21bbd2bc12e018f8d29d74a4d92 +size 3007110 diff --git a/rfsoc_eval_nco/vitis_classic_autobuild/source/dev_profile/lmk04828_profile.c b/rfsoc_eval_nco/vitis_classic_autobuild/source/dev_profile/lmk04828_profile.c index ef93263..af831a3 100644 --- a/rfsoc_eval_nco/vitis_classic_autobuild/source/dev_profile/lmk04828_profile.c +++ b/rfsoc_eval_nco/vitis_classic_autobuild/source/dev_profile/lmk04828_profile.c @@ -87,7 +87,7 @@ const struct lmk04828_config lmk04828_default_config[] = { {0x0123, 0x00}, // DCLK: [7-3] analog delay (ADLY) value, 25 ps per lsb; [2] ADLY input mux; [1-0] DCLK input mux {0x0124, 0x22}, // [6] DCLK half step value; [5] SDCLK output MUX; [4-1] SDCLK DDLY; [0] SYSREF half step value {0x0125, 0x00}, // SYSREF: [4] ADLY enable; [3:0] ADLY value, 600 ps + 150 ps per lsb - {0x0126, 0xF1}, // [7] DCLK DDLY enable; [6] DCLK glitchless half step enable; [5] DCLK glitchless ADLY enable; [4] DCLK ADLY enable; [3]: clock group enable; [2-1] SYSREF disable mode; [0]: SYSREF disable + {0x0126, 0xF0}, // [7] DCLK DDLY enable; [6] DCLK glitchless half step enable; [5] DCLK glitchless ADLY enable; [4] DCLK ADLY enable; [3]: clock group enable; [2-1] SYSREF disable mode; [0]: SYSREF disable {0x0127, 0x55}, // [7] SDCLK output polarity; [6-4] SDCLK output format; [3] DCLK output polarity; [2:0] DCLK output format // device clock 10 {0x0128, 0x00}, // [6] output drive level (ODL); [5] input drive level (IDL); [4-0] device clock (DCLK) output divider