forked from 0xha0/df_datalink
feat: 更新L1帧类型定义, 更新天线控制相关结构体
This commit is contained in:
@@ -425,7 +425,7 @@ L1_FRAME_TYPE L2_L2frame2L1frame(L2_FRAME_TYPE l2Frame)
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case L2_SVC_FRAME:
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return L1_40KBPS_20MS_FRAME;
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default:
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return L1_NONE_FRAME;
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return L1_FRAME_NONE;
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}
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}
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/** @} LinkLayer_Utility*/
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@@ -1030,14 +1030,14 @@ int32_t Linklayer_Proc(L2_INST *instPtr)
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// Run Link layer routine, setup next slot procedure.
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if (L2_GetNodeType(instPtr) == L2_NODE_HEAD)
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{
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Phy_SetMode(phyRef, PHY_MODE_PULL);
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Phy_SetMode(phyRef, PHY_MODE_POLL);
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Status = Linklayer_Routine(instPtr);
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}
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else
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{ // L2_NODE_MEMBER
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if (L2_isCxn2Net(instPtr))
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{
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Phy_SetMode(phyRef, PHY_MODE_PULL);
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Phy_SetMode(phyRef, PHY_MODE_POLL);
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Status = Linklayer_Routine(instPtr);
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}
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else
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@@ -42,7 +42,7 @@
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/************************** Variable Definitions *****************************/
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// Pair by regex
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// Regex: ((\{\.oaxis = [0-9]+[ ,]+\.raxis = [0-9]+[ ]*\}, ){2})
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PHY_ANT_ANGLE antNrrwPattern_0[L1_NUM_ANT_NRRW_PATTERN] =
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PHY_ANT_ANGLE antNrrwPattern_0[L1_ANT_PATTERN_NUM] =
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{
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{.oaxis = 0 , .raxis = 0 },
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{.oaxis = 139, .raxis = 2225},
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@@ -83,7 +83,7 @@ PHY_ANT_ANGLE antNrrwPattern_0[L1_NUM_ANT_NRRW_PATTERN] =
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{.oaxis = 450, .raxis = 897 }
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};
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PHY_ANT_ANGLE antNrrwPattern_1[L1_NUM_ANT_NRRW_PATTERN] =
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PHY_ANT_ANGLE antNrrwPattern_1[L1_ANT_PATTERN_NUM] =
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{
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{.oaxis = 0 , .raxis = 0 },
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{.oaxis = 139, .raxis = 1155},
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@@ -272,7 +272,7 @@ static int32_t Scan_AdvHandler(L2_INST *instPtr)
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// since first time sync procedure is accomplished in ADV stage.
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(void)Phy_SetBeamWidth(phyRef, PHY_ANT_BEAM_16);
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(void)Phy_SetBeamNo(phyRef, scanFsmPtr->beamNo, PHY_ANT_BEAM_16);
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(void)Phy_SetMode(phyRef, PHY_MODE_PULL);
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(void)Phy_SetMode(phyRef, PHY_MODE_POLL);
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(void)L2_SetupNextSlot(instPtr, L2_TOR_RX, L2_CFM_FRAME);
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scanFsmPtr->cfmTimeout++; // increase counter.
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instPtr->log.lastBeamWidth = PHY_ANT_BEAM_16;
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@@ -334,7 +334,7 @@ static int32_t Scan_CfmHandler(L2_INST *instPtr)
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// since first time sync procedure is accomplished in ADV stage.
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(void)Phy_SetBeamWidth(phyRef, PHY_ANT_BEAM_16);
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(void)Phy_SetBeamNo(phyRef, scanFsmPtr->beamNo, PHY_ANT_BEAM_16);
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(void)Phy_SetMode(phyRef, PHY_MODE_PULL);
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(void)Phy_SetMode(phyRef, PHY_MODE_POLL);
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(void)L2_SetupNextSlot(instPtr, L2_TOR_RX, L2_CFM_FRAME);
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scanFsmPtr->cfmTimeout++; // increase counter.
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instPtr->log.lastBeamWidth = PHY_ANT_BEAM_16;
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@@ -54,7 +54,7 @@ int32_t L2_GetTimeDeviation(L2_INST *instPtr, uint32_t frameNum, uint32_t slotNu
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L1_FRAME_TYPE lastRecvdFrame;
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PHY_INST *phyRef = instPtr->config.phyInstPtr;
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lastRecvdFrame = Phy_GetLastRecvFrameType(phyRef);
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if (lastRecvdFrame == L1_NONE_FRAME)
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if (lastRecvdFrame == L1_FRAME_NONE)
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{
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DBG_ERROR("Invalid TimeAlign operation, no frame was received.");
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return EIGNORE;
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@@ -82,7 +82,7 @@ const uint16_t freqTable[L1_FRAME_MAX_HOPS] =
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2124U
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};
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const int16_t antCalTable[L1_FRAME_MAX_HOPS][L1_ANT_NUM_CH] =
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const int16_t antCalTable[L1_FRAME_MAX_HOPS][L1_ANT_CH_NUM] =
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//Antenna-JG01
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{
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{ 0, 2525, -7533, -6846}, { 0, 12726, -7818, -6860},
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@@ -128,12 +128,12 @@ const int16_t antCalTable[L1_FRAME_MAX_HOPS][L1_ANT_NUM_CH] =
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{ 0, 1767, -7775, -8328},
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};
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const uint8_t hopPattern_2KBPS_20MS[L1_FRAME_2KBPS_20MS_HOPS] =
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const uint8_t hopPattern_ADV_24MS[L1_FRAME_ADV_24MS_HOPS] =
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{
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0
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};
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const uint8_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS] =
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const uint8_t hopPattern_ACK_8MS[L1_FRAME_ACK_8MS_HOPS] =
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{
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0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
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8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
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@@ -148,44 +148,23 @@ const uint8_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS] =
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80U
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};
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const uint8_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS] =
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const uint8_t hopPattern_128KBPS_4MS[L1_FRAME_128KBPS_4MS_HOPS] =
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{
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80U
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};
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const uint8_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS] =
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const uint8_t hopPattern_512KBPS_4MS[L1_FRAME_512KBPS_4MS_HOPS] =
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{
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80U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
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8U, 9U, 10U
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};
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const uint8_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS] =
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const uint8_t hopPattern_2MBPS_4MS[L1_FRAME_2MBPS_4MS_HOPS] =
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{
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0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
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8U,
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};
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const uint8_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS] =
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{
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0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
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8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
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16U, 17U, 18U
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};
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const uint8_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS] =
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{
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0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
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8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
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16U, 17U, 18U, 19U
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};
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const uint8_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS] =
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{
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0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
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8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
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16U, 17U, 18U, 19U
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};
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/** @} PhysicalLayer_AntennaConfig_Constants*/
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/*****************************************************************************/
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@@ -298,12 +277,12 @@ void Phy_SetBeamTable(PHY_INST *instPtr, PHY_ANT_ANGLE *table, uint32_t offset)
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{
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ASSERT(instPtr != NULL);
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ASSERT(table != NULL);
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for (int i = 0; i < L1_NUM_ANT_NRRW_PATTERN; i++)
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for (int i = 0; i < L1_ANT_PATTERN_NUM; i++)
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{
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instPtr->antNrrwPattern[i] = table[(i + offset) % L1_NUM_ANT_NRRW_PATTERN];
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instPtr->antNrrwPattern[i] = table[(i + offset) % L1_ANT_PATTERN_NUM];
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}
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memcpy((uint32_t *)instPtr->antInfoAddr, instPtr->antNrrwPattern,
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L1_NUM_ANT_NRRW_PATTERN * sizeof(PHY_ANT_ANGLE));
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L1_ANT_PATTERN_NUM * sizeof(PHY_ANT_ANGLE));
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}
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/*****************************************************************************/
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@@ -323,7 +302,7 @@ int32_t Phy_SetBeamNo(PHY_INST *instPtr, size_t beamNo, PHY_ANT_BEAM_WIDTH beamW
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if (beamWidth == PHY_ANT_BEAM_16)
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{
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if (beamNo >= L1_NUM_ANT_NRRW_PATTERN)
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if (beamNo >= L1_ANT_PATTERN_NUM)
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{
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return FAILURE;
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}
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@@ -36,52 +36,40 @@
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#define PHY_TIME_WORD_H_MAX UINT32_MAX
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#define PHY_TIME_WORD_L_MAX 0x0007A120 // 5ms/10ns
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#define L1_FRAME_LEN_MAX (8192 / 8) // byte
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#define L1_FRAME_2KBPS_20MS_LEN 0 // byte
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#define L1_FRAME_2KBPS_100MS_LEN (312 / 8) // byte
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#define L1_FRAME_10KBPS_10MS_LEN 0 // byte
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#define L1_FRAME_10KBPS_20MS_LEN (232 / 8) // byte
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#define L1_FRAME_40KBPS_20MS_LEN (2152 / 8) // byte
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#define L1_FRAME_40KBPS_10MS_LEN (712 / 8) // byte
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#define L1_FRAME_200KBPS_5MS_LEN (2040 / 8) // byte
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#define L1_FRAME_1M2BPS_5MS_LEN (8176 / 8) // byte
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#define L1_FRAME_LEN_MAX (16384 / 8) // byte
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#define L1_FRAME_ADV_24MS_LEN (520 / 8) // byte
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#define L1_FRAME_ACK_8MS_LEN (520 / 8) // byte
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#define L1_FRAME_128KBPS_4MS_LEN (784 / 8) // byte
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#define L1_FRAME_512KBPS_4MS_LEN (2584 / 8) // byte
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#define L1_FRAME_2MBPS_4MS_LEN (10224 / 8) // byte
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#define L1_FRAME_2KBPS_20MS_COMP 1841158 // *10ns(Timer_L)
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#define L1_FRAME_2KBPS_100MS_COMP 1841158 // *10ns(Timer_L)
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#define L1_FRAME_10KBPS_10MS_COMP 850950 // *10ns(Timer_L)
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#define L1_FRAME_10KBPS_20MS_COMP 850950 // *10ns(Timer_L)
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#define L1_FRAME_40KBPS_20MS_COMP 111485 // *10ns(Timer_L)
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#define L1_FRAME_40KBPS_10MS_COMP 111485 // *10ns(Timer_L)
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#define L1_FRAME_200KBPS_5MS_COMP 22493 // *10ns(Timer_L)
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#define L1_FRAME_1M2BPS_5MS_COMP 22493 // *10ns(Timer_L)
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#define L1_FRAME_ADV_24MS_COMP 1841158 // FIXME: need update, *10ns(Timer_L)
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#define L1_FRAME_ACK_8MS_COMP 1841158 // FIXME: need update, *10ns(Timer_L)
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#define L1_FRAME_128KBPS_4MS_COMP 850950 // FIXME: need update, *10ns(Timer_L)
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#define L1_FRAME_512KBPS_4MS_COMP 850950 // FIXME: need update, *10ns(Timer_L)
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#define L1_FRAME_2MBPS_4MS_COMP 111485 // FIXME: need update, *10ns(Timer_L)
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#define L1_ANTCONFIG_MAX_LEN 8192
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#define L1_TXRXDATA_MAX_LEN 2048
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#define L1_TXRXDATA_MAX_LEN 16384
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#define ANT_COINFO_LEN 32 // bytes
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#define ANT_COINFO_LEN 32 // bytes, antenna configuration length of each hop
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#define ATTN_DEFAULT 0
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#define ATTN_2KBPS_100MS ATTN_DEFAULT
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#define ATTN_2KBPS_20MS ATTN_DEFAULT
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#define ATTN_10KBPS_10MS 12
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#define ATTN_10KBPS_20MS 12
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#define ATTN_40KBPS_10MS 0
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#define ATTN_40KBPS_20MS 0
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#define ATTN_200KBPS_5MS ATTN_DEFAULT
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#define ATTN_1M2BPS_5MS ATTN_DEFAULT
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#define ATTN_ADV_24MS ATTN_DEFAULT
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#define ATTN_ACK_8MS ATTN_DEFAULT
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#define ATTN_128KBPS_4MS ATTN_DEFAULT
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#define ATTN_512KBPS_4MS ATTN_DEFAULT
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#define ATTN_2MBPS_4MS ATTN_DEFAULT
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/** @} PhysicalLayer_Private_Constants*/
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/************************** Variable Definitions *****************************/
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extern const uint16_t freqTable[L1_FRAME_MAX_HOPS];
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extern const int16_t antCalTable[L1_FRAME_MAX_HOPS][L1_ANT_NUM_CH];
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extern const uint8_t hopPattern_2KBPS_20MS[L1_FRAME_2KBPS_20MS_HOPS];
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extern const uint8_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS];
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extern const uint8_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS];
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extern const uint8_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS];
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extern const uint8_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS];
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extern const uint8_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS];
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extern const uint8_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS];
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extern const uint8_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS];
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extern const int16_t antCalTable[L1_FRAME_MAX_HOPS][L1_ANT_CH_NUM];
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extern const uint8_t hopPattern_ADV_24MS[L1_FRAME_ADV_24MS_HOPS];
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extern const uint8_t hopPattern_ACK_8MS[L1_FRAME_ACK_8MS_HOPS];
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extern const uint8_t hopPattern_128KBPS_4MS[L1_FRAME_128KBPS_4MS_HOPS];
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extern const uint8_t hopPattern_512KBPS_4MS[L1_FRAME_512KBPS_4MS_HOPS];
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extern const uint8_t hopPattern_2MBPS_4MS[L1_FRAME_2MBPS_4MS_HOPS];
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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@@ -227,22 +215,16 @@ uint32_t Phy_GetFrameLen(L1_FRAME_TYPE frameType)
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{
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switch (frameType)
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{
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case L1_2KBPS_20MS_FRAME:
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return L1_FRAME_2KBPS_20MS_LEN;
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case L1_2KBPS_100MS_FRAME:
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return L1_FRAME_2KBPS_100MS_LEN;
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case L1_10KBPS_10MS_FRAME:
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return L1_FRAME_10KBPS_10MS_LEN;
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case L1_10KBPS_20MS_FRAME:
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return L1_FRAME_10KBPS_20MS_LEN;
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case L1_40KBPS_20MS_FRAME:
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return L1_FRAME_40KBPS_20MS_LEN;
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case L1_40KBPS_10MS_FRAME:
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return L1_FRAME_40KBPS_10MS_LEN;
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case L1_200KBPS_5MS_FRAME:
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return L1_FRAME_200KBPS_5MS_LEN;
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case L1_1M2BPS_5MS_FRAME:
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return L1_FRAME_1M2BPS_5MS_LEN;
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case L1_FRAME_ADV_24MS:
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return L1_FRAME_ADV_24MS_LEN;
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case L1_FRAME_ACK_8MS:
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return L1_FRAME_ACK_8MS_LEN;
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case L1_FRAME_128KBPS_4MS:
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return L1_FRAME_128KBPS_4MS_LEN;
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case L1_FRAME_512KBPS_4MS:
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return L1_FRAME_512KBPS_4MS_LEN;
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case L1_FRAME_2MBPS_4MS:
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return L1_FRAME_2MBPS_4MS_LEN;
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default:
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return L1_FRAME_NONE_LEN;
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}
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@@ -263,24 +245,18 @@ uint32_t Phy_GetHopLength(L1_FRAME_TYPE frameType)
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{
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switch (frameType)
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{
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case L1_2KBPS_20MS_FRAME:
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return L1_FRAME_2KBPS_20MS_HOPS;
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case L1_2KBPS_100MS_FRAME:
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return L1_FRAME_2KBPS_100MS_HOPS;
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case L1_10KBPS_10MS_FRAME:
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return L1_FRAME_10KBPS_10MS_HOPS;
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case L1_10KBPS_20MS_FRAME:
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return L1_FRAME_10KBPS_20MS_HOPS;
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case L1_40KBPS_20MS_FRAME:
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return L1_FRAME_40KBPS_20MS_HOPS;
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case L1_40KBPS_10MS_FRAME:
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return L1_FRAME_40KBPS_10MS_HOPS;
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case L1_200KBPS_5MS_FRAME:
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return L1_FRAME_200KBPS_5MS_HOPS;
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case L1_1M2BPS_5MS_FRAME:
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return L1_FRAME_1M2BPS_5MS_HOPS;
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case L1_FRAME_ADV_24MS:
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return L1_FRAME_ADV_24MS_HOPS;
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case L1_FRAME_ACK_8MS:
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return L1_FRAME_ACK_8MS_HOPS;
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case L1_FRAME_128KBPS_4MS:
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return L1_FRAME_128KBPS_4MS_HOPS;
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case L1_FRAME_512KBPS_4MS:
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return L1_FRAME_512KBPS_4MS_HOPS;
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case L1_FRAME_2MBPS_4MS:
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return L1_FRAME_2MBPS_4MS_HOPS;
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default:
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return L1_FRAME_NONE_LEN;
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return L1_FRAME_NONE_HOPS;
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}
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}
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@@ -298,24 +274,18 @@ uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType)
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{
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switch (frameType)
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{
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case L1_2KBPS_20MS_FRAME:
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return L1_FRAME_2KBPS_20MS_COMP;
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case L1_2KBPS_100MS_FRAME:
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return L1_FRAME_2KBPS_100MS_COMP;
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case L1_10KBPS_10MS_FRAME:
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return L1_FRAME_10KBPS_10MS_COMP;
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case L1_10KBPS_20MS_FRAME:
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return L1_FRAME_10KBPS_20MS_COMP;
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case L1_40KBPS_20MS_FRAME:
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return L1_FRAME_40KBPS_20MS_COMP;
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case L1_40KBPS_10MS_FRAME:
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return L1_FRAME_40KBPS_10MS_COMP;
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case L1_200KBPS_5MS_FRAME:
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return L1_FRAME_200KBPS_5MS_COMP;
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case L1_1M2BPS_5MS_FRAME:
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return L1_FRAME_1M2BPS_5MS_COMP;
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case L1_FRAME_ADV_24MS:
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return L1_FRAME_ADV_24MS_COMP;
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case L1_FRAME_ACK_8MS:
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return L1_FRAME_ACK_8MS_COMP;
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case L1_FRAME_128KBPS_4MS:
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return L1_FRAME_128KBPS_4MS_COMP;
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case L1_FRAME_512KBPS_4MS:
|
||||
return L1_FRAME_512KBPS_4MS_COMP;
|
||||
case L1_FRAME_2MBPS_4MS:
|
||||
return L1_FRAME_2MBPS_4MS_COMP;
|
||||
default:
|
||||
return L1_FRAME_NONE_LEN;
|
||||
return L1_FRAME_NONE_COMP;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -325,7 +295,7 @@ uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType)
|
||||
*
|
||||
* @param instPtr A pointer to physical layer control instance.
|
||||
*
|
||||
* @return Layer2 frame type. Refer "frame_def.h"
|
||||
* @return Layer1 frame type. Refer "frame_def.h"
|
||||
*
|
||||
******************************************************************************/
|
||||
inline L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr)
|
||||
@@ -333,29 +303,23 @@ inline L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr)
|
||||
ASSERT(instPtr != NULL);
|
||||
if (Phy_IsFrameReceived(instPtr) == false)
|
||||
{
|
||||
return L1_NONE_FRAME;
|
||||
return L1_FRAME_NONE;
|
||||
}
|
||||
uint32_t frame_type = (PhyRead(instPtr, COASE_FREQEST) & COASE_TYPE_MASK);
|
||||
switch (frame_type)
|
||||
{
|
||||
case COASE_TYPE_2KBPS_20MS:
|
||||
return L1_2KBPS_20MS_FRAME;
|
||||
case COASE_TYPE_2KBPS_100MS:
|
||||
return L1_2KBPS_100MS_FRAME;
|
||||
case COASE_TYPE_10KBPS_10MS:
|
||||
return L1_10KBPS_10MS_FRAME;
|
||||
case COASE_TYPE_10KBPS_20MS:
|
||||
return L1_10KBPS_20MS_FRAME;
|
||||
case COASE_TYPE_40KBPS_20MS:
|
||||
return L1_40KBPS_20MS_FRAME;
|
||||
case COASE_TYPE_40KBPS_10MS:
|
||||
return L1_40KBPS_10MS_FRAME;
|
||||
case COASE_TYPE_200KBPS_5MS:
|
||||
return L1_200KBPS_5MS_FRAME;
|
||||
case COASE_TYPE_1M2BPS_5MS:
|
||||
return L1_1M2BPS_5MS_FRAME;
|
||||
case COASE_TYPE_ADV_24MS:
|
||||
return L1_FRAME_ADV_24MS;
|
||||
case COASE_TYPE_ACK_8MS:
|
||||
return L1_FRAME_ACK_8MS;
|
||||
case COASE_TYPE_128KBPS_4MS:
|
||||
return L1_FRAME_128KBPS_4MS;
|
||||
case COASE_TYPE_512KBPS_4MS:
|
||||
return L1_FRAME_512KBPS_4MS;
|
||||
case COASE_TYPE_2MBPS_4MS:
|
||||
return L1_FRAME_2MBPS_4MS;
|
||||
default:
|
||||
return L1_NONE_FRAME;
|
||||
return L1_FRAME_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -365,7 +329,7 @@ inline L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr)
|
||||
*
|
||||
* @param instPtr A pointer to physical layer control instance.
|
||||
*
|
||||
* @return Layer2 frame type. Refer "frame_def.h"
|
||||
* @return Layer1 frame type. Refer "frame_def.h"
|
||||
*
|
||||
******************************************************************************/
|
||||
inline L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST *instPtr)
|
||||
@@ -373,7 +337,7 @@ inline L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST *instPtr)
|
||||
ASSERT(instPtr != NULL);
|
||||
if (instPtr->tor.last != PHY_TOR_TX)
|
||||
{
|
||||
return L1_NONE_FRAME;
|
||||
return L1_FRAME_NONE;
|
||||
}
|
||||
return instPtr->frameType.last;
|
||||
}
|
||||
@@ -539,7 +503,7 @@ int32_t Phy_Init(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
|
||||
uint32_t phyMainCtrl = PhyRead(*instPtr, PHY_MAIN_CTRL);
|
||||
phyMainCtrl &= ~PHY_MAIN_CTRL_NSCAN_MASK;
|
||||
phyMainCtrl |= PHY_MAIN_CTRL_NSCAN_MASK &
|
||||
(L1_NUM_ANT_NRRW_PATTERN << PHY_MAIN_CTRL_NSCAN_SHIFT);
|
||||
(L1_ANT_PATTERN_NUM << PHY_MAIN_CTRL_NSCAN_SHIFT);
|
||||
PhyWrite(*instPtr, PHY_MAIN_CTRL, phyMainCtrl);
|
||||
}
|
||||
else
|
||||
@@ -597,7 +561,7 @@ int32_t Phy_Init(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @brief Destroy physical layer inctance, free allocated memory.
|
||||
* @brief Destroy physical layer instance, free allocated memory.
|
||||
*
|
||||
* @param instPtr a pointer to physical instance
|
||||
*
|
||||
@@ -685,11 +649,8 @@ int32_t Phy_SetMode(PHY_INST *instPtr, PHY_MODE modeCod)
|
||||
case PHY_MODE_LISTEN:
|
||||
phyMainCtrl |= PHY_MAIN_CTRL_MODE_LISTEN;
|
||||
break;
|
||||
case PHY_MODE_SCHEDULE:
|
||||
phyMainCtrl |= PHY_MAIN_CTRL_MODE_SCHEDULE;
|
||||
break;
|
||||
case PHY_MODE_PULL:
|
||||
phyMainCtrl |= PHY_MAIN_CTRL_MODE_PULL;
|
||||
case PHY_MODE_POLL:
|
||||
phyMainCtrl |= PHY_MAIN_CTRL_MODE_POLL;
|
||||
break;
|
||||
default:
|
||||
return FAILURE;
|
||||
@@ -773,53 +734,30 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
|
||||
}
|
||||
switch (frameType)
|
||||
{
|
||||
case L1_2KBPS_20MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_2KBPS_20MS;
|
||||
hopNum = L1_FRAME_2KBPS_20MS_HOPS;
|
||||
hopPattern = hopPattern_2KBPS_20MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_2KBPS_20MS;
|
||||
case L1_FRAME_ADV_24MS:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_ADV_24MS;
|
||||
hopNum = L1_FRAME_ADV_24MS_HOPS;
|
||||
hopPattern = hopPattern_ADV_24MS;
|
||||
break;
|
||||
case L1_2KBPS_100MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_2KBPS_100MS;
|
||||
hopNum = L1_FRAME_2KBPS_100MS_HOPS;
|
||||
hopPattern = hopPattern_2KBPS_100MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_2KBPS_100MS;
|
||||
case L1_FRAME_ACK_8MS:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_ACK_8MS;
|
||||
hopNum = L1_FRAME_ACK_8MS_HOPS;
|
||||
hopPattern = hopPattern_ACK_8MS;
|
||||
break;
|
||||
case L1_10KBPS_10MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_10KBPS_10MS;
|
||||
hopNum = L1_FRAME_10KBPS_20MS_HOPS;
|
||||
hopPattern = hopPattern_10KBPS_20MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_10KBPS_10MS;
|
||||
case L1_FRAME_128KBPS_4MS:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_128KBPS_4MS;
|
||||
hopNum = L1_FRAME_128KBPS_4MS_HOPS;
|
||||
hopPattern = hopPattern_128KBPS_4MS;
|
||||
break;
|
||||
case L1_10KBPS_20MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_10KBPS_20MS;
|
||||
hopNum = L1_FRAME_10KBPS_20MS_HOPS;
|
||||
hopPattern = hopPattern_10KBPS_20MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_10KBPS_20MS;
|
||||
case L1_FRAME_512KBPS_4MS:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_512KBPS_4MS;
|
||||
hopNum = L1_FRAME_512KBPS_4MS_HOPS;
|
||||
hopPattern = hopPattern_512KBPS_4MS;
|
||||
break;
|
||||
case L1_40KBPS_20MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_40KBPS_20MS;
|
||||
hopNum = L1_FRAME_40KBPS_20MS_HOPS;
|
||||
hopPattern = hopPattern_40KBPS_20MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_40KBPS_20MS;
|
||||
break;
|
||||
case L1_40KBPS_10MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_40KBPS_10MS;
|
||||
hopNum = L1_FRAME_40KBPS_10MS_HOPS;
|
||||
hopPattern = hopPattern_40KBPS_10MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_40KBPS_10MS;
|
||||
break;
|
||||
case L1_200KBPS_5MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_200KBPS_5MS;
|
||||
hopNum = L1_FRAME_200KBPS_5MS_HOPS;
|
||||
hopPattern = hopPattern_200KBPS_5MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_200KBPS_5MS;
|
||||
break;
|
||||
case L1_1M2BPS_5MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_1M2BPS_5MS;
|
||||
hopNum = L1_FRAME_1M2BPS_5MS_HOPS;
|
||||
hopPattern = hopPattern_1M2BPS_5MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_1M2BPS_5MS;
|
||||
case L1_FRAME_2MBPS_4MS:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_2MBPS_4MS;
|
||||
hopNum = L1_FRAME_2MBPS_4MS_HOPS;
|
||||
hopPattern = hopPattern_2MBPS_4MS;
|
||||
break;
|
||||
default:
|
||||
return EPARAM;
|
||||
@@ -840,8 +778,6 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
|
||||
|
||||
// Frequency setting
|
||||
hopFreq = freqTable[hopIdx];
|
||||
instPtr->antConfig.antFreq[0] = (uint8_t)(hopFreq >> 8);
|
||||
instPtr->antConfig.antFreq[1] = (uint8_t)hopFreq;
|
||||
instPtr->antConfig.rfFreq[0] = (uint8_t)(hopFreq >> 8);
|
||||
instPtr->antConfig.rfFreq[1] = (uint8_t)hopFreq;
|
||||
// Calibration setting
|
||||
@@ -889,9 +825,7 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
|
||||
|
||||
Phy_RcdShift(&(instPtr->tor), txrxMode);
|
||||
Phy_RcdShift(&(instPtr->frameType), frameType);
|
||||
// TODO:
|
||||
Phy_RcdShift(&(instPtr->beamNo), L1_INIT_BEAM_NO);
|
||||
Phy_RcdShift(&(instPtr->beamWd), L1_INIT_ANT_WD);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
@@ -1121,45 +1055,42 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
|
||||
#else
|
||||
instPtr->hwSate.isSpOk = true;
|
||||
#endif
|
||||
/*** Voltage and Status ***/
|
||||
rawData = PhyRead(instPtr, ANT_STATUS);
|
||||
// -- Update Antenna Voltage Status: 1 - normal, 0 - error
|
||||
// [0] - ANT voltage status
|
||||
// [2] - RF voltage status
|
||||
// [4] - NIL voltage status
|
||||
// [6] - Antenna status
|
||||
instPtr->hwSate.antVolt = ((rawData & ANT_STATUS_ANT_VOLT_MASK) == ANT_STATUS_ANT_VOLT_OK) ? VOLT_ANT_PROC_OK : 0x00;
|
||||
instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_RF_VOLT_MASK) == ANT_STATUS_RF_VOLT_OK) ? VOLT_ANT_RF_OK : 0x00;
|
||||
instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_NIL_VOLT_MASK) == ANT_STATUS_NIL_VOLT_OK) ? VOLT_ANT_NIL_OK : 0x00;
|
||||
instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_CODE_MASK) == ANT_STATUS_CODE_OK) ? ANT_STATE_OK : 0x00;
|
||||
/*** Antenna Status Chunk 1 ***/
|
||||
rawData = PhyRead(instPtr, ANT_STATUS_1);
|
||||
// -- Update Antenna Frequency Status:
|
||||
// [15] - ANT1 PLL on-off status: 1 - PLL1 active, 0 - PLL2 active
|
||||
// [14:0] - ANT1 PLL frequency, base frequency is 3700 MHz
|
||||
// [31] - ANT2 PLL on-off status: 1 - PLL1 active, 0 - PLL2 active
|
||||
// [30:16] - ANT2 PLL frequency, base frequency is 3700 MHz
|
||||
instPtr->hwSate.ant1Freq = (rawData & ANT_STATUS_1_ANT1_STATUS_MASK) >> ANT_STATUS_1_ANT1_STATUS_SHIFT;
|
||||
instPtr->hwSate.ant2Freq = (rawData & ANT_STATUS_1_ANT2_STATUS_MASK) >> ANT_STATUS_1_ANT2_STATUS_SHIFT;
|
||||
|
||||
/*** Temperature and Lock Status ***/
|
||||
rawData = PhyRead(instPtr, ANT_RF_STATUS);
|
||||
/*** Antenna Status Chunk 2 ***/
|
||||
rawData = PhyRead(instPtr, ANT_STATUS_2);
|
||||
// -- Update Antenna Frequency Status:
|
||||
// [15] - ANT 3 PLL on-off status: 1 - PLL1 active, 0 - PLL2 active
|
||||
// [14:0] - ANT 3 PLL frequency, base frequency is 3700 MHz
|
||||
// [16] - PLL1 of ANT1 lock status: 1 - lock, 2 - unlock
|
||||
// [17] - PLL2 of ANT1 lock status: 1 - lock, 2 - unlock
|
||||
// [18] - PLL1 of ANT2 lock status: 1 - lock, 2 - unlock
|
||||
// [19] - PLL2 of ANT2 lock status: 1 - lock, 2 - unlock
|
||||
// [20] - PLL1 of ANT3 lock status: 1 - lock, 2 - unlock
|
||||
// [21] - PLL2 of ANT3 lock status: 1 - lock, 2 - unlock
|
||||
// [24] - Working mode of ANT1: 0 - normal mode, 1 - anti-jamming mode
|
||||
// [25] - Working mode of ANT2: 0 - normal mode, 1 - anti-jamming mode
|
||||
// [26] - Working mode of ANT3: 0 - normal mode, 1 - anti-jamming mode
|
||||
instPtr->hwSate.ant3Freq = (rawData & ANT_STATUS_2_ANT3_STATUS_MASK) >> ANT_STATUS_2_ANT3_STATUS_SHIFT;
|
||||
instPtr->hwSate.antPll = (rawData & ANT_STATUS_2_PLL_LK_MASK) >> ANT_STATUS_2_PLL_LK_SHIFT;
|
||||
instPtr->hwSate.antMode = (rawData & ANT_STATUS_2_MODE_MASK) >> ANT_STATUS_2_MODE_SHIFT;
|
||||
|
||||
/*** Temperature and Reserved Control ***/
|
||||
rawData = PhyRead(instPtr, ANT_STATUS_TEMP);
|
||||
//-- Update Antenna Temperature (signed 8bit integer, 1 centigrade per LSB)
|
||||
instPtr->hwSate.antTemp = (uint8_t)(rawData & ANT_RF_STATUS_TEMP_MASK);
|
||||
// -- Update Antenna PLL Lock Status: 1 - normal, 0 - error
|
||||
// [0] - BASEBAND lock status
|
||||
// [2] - PLLA lock status
|
||||
// [4] - PLLB lock status
|
||||
instPtr->hwSate.antPll = ((rawData & ANT_RF_STATUS_BBLOCK_MASK) == ANT_RF_STATUS_BBLOCK_OK) ? CLK_ANT_BBPLL_LOCK : 0x00;
|
||||
instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLA_MASK) == ANT_RF_STATUS_PLLA_OK) ? CLK_ANT_RFPLL1_LOCK : 0x00;
|
||||
instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLB_MASK) == ANT_RF_STATUS_PLLB_OK) ? CLK_ANT_RFPLL2_LOCK : 0x00;
|
||||
instPtr->hwSate.antTemp = (uint8_t)(rawData & ANT_STATUS_TEMP_MASK) >> ANT_STATUS_TEMP_SHIFT;
|
||||
instPtr->hwSate.antRsvd = (uint8_t)(rawData & ANT_STATUS_TEMP_RSVD_MASK) >> ANT_STATUS_TEMP_RSVD_SHIFT;
|
||||
|
||||
/*** MGCs ***/
|
||||
rawData = PhyRead(instPtr, ANT_RF_MGC);
|
||||
// -- Update Antenna MGC (0~15 dB)
|
||||
// [3:0] - Channel 1 MGC
|
||||
// [7:4] - Channel 2 MGC
|
||||
// [11:8] - Channel 3 MGC
|
||||
// [15:12] - Channel 4 MGC
|
||||
instPtr->hwSate.antMgc0 = (rawData & ANT_RF_MGC_CH1_MASK);
|
||||
instPtr->hwSate.antMgc0 |= (rawData & ANT_RF_MGC_CH2_MASK) >> 4;
|
||||
instPtr->hwSate.antMgc1 = (rawData & ANT_RF_MGC_CH3_MASK) >> 16;
|
||||
instPtr->hwSate.antMgc1 |= (rawData & ANT_RF_MGC_CH4_MASK) >> 24;
|
||||
|
||||
// Determin if antenna is ok.
|
||||
instPtr->hwSate.isAntOk = (instPtr->hwSate.antVolt == (VOLT_ANT_PROC_OK | VOLT_ANT_RF_OK | VOLT_ANT_NIL_OK | ANT_STATE_OK))
|
||||
&& (instPtr->hwSate.antPll == (CLK_ANT_BBPLL_LOCK | CLK_ANT_RFPLL1_LOCK | CLK_ANT_RFPLL2_LOCK));
|
||||
// Determine if antenna is ok.
|
||||
instPtr->hwSate.isAntOk = 1U; // FIXME: proper condition is required
|
||||
|
||||
instPtr->hwSate.phyId = instPtr->phyCofig.devId;
|
||||
|
||||
@@ -1208,7 +1139,7 @@ double Phy_GetFreqEst(PHY_INST *instPtr)
|
||||
double coarse, fine;
|
||||
|
||||
frameType = Phy_GetLastRecvFrameType(instPtr);
|
||||
if (frameType > L1_1M2BPS_5MS_FRAME || frameType <= L1_NONE_FRAME)
|
||||
if (frameType > L1_FRAME_2MBPS_4MS || frameType <= L1_FRAME_NONE)
|
||||
{
|
||||
return INFINITY; // FIXME
|
||||
}
|
||||
@@ -1218,7 +1149,7 @@ double Phy_GetFreqEst(PHY_INST *instPtr)
|
||||
syncFreqIdx = (coarseReg & COASE_FREQEST_SYNC_MASK) >> COASE_FREQEST_SYNC_SHIFT;
|
||||
fineReg = PhyRead(instPtr, FINE_FREQEST);
|
||||
estAbs = fineReg & FINE_FREQEST_VAL_MASK;
|
||||
if (frameType >= L1_200KBPS_5MS_FRAME)
|
||||
if (frameType >= L1_FRAME_128KBPS_4MS)
|
||||
{
|
||||
// 12M Rc
|
||||
coarse = (double)(8 - acqFreqIdx) * (250e3 / 4);
|
||||
@@ -1259,14 +1190,14 @@ double Phy_GetCoarseFreqEst(PHY_INST *instPtr)
|
||||
double freqEst;
|
||||
|
||||
frameType = Phy_GetLastRecvFrameType(instPtr);
|
||||
if ((frameType > L1_1M2BPS_5MS_FRAME) || (frameType <= L1_NONE_FRAME))
|
||||
if ((frameType > L1_FRAME_2MBPS_4MS) || (frameType <= L1_FRAME_NONE))
|
||||
{
|
||||
return INFINITY; // FIXME
|
||||
}
|
||||
regValue = PhyRead(instPtr, COASE_FREQEST);
|
||||
acqFreqIdx = (regValue & COASE_FREQEST_ACQ_MASK) >> COASE_FREQEST_ACQ_SHIFT;
|
||||
syncFreqIdx = (regValue & COASE_FREQEST_SYNC_MASK) >> COASE_FREQEST_SYNC_SHIFT;
|
||||
if (frameType >= L1_200KBPS_5MS_FRAME)
|
||||
if (frameType >= L1_FRAME_128KBPS_4MS)
|
||||
{
|
||||
// 12M Rc
|
||||
freqEst = (double)(8 - acqFreqIdx) * (250e3 / 4);
|
||||
@@ -1297,14 +1228,14 @@ double Phy_GetFineFreqEst(PHY_INST *instPtr)
|
||||
double freqEst;
|
||||
L1_FRAME_TYPE frameType;
|
||||
frameType = Phy_GetLastRecvFrameType(instPtr);
|
||||
if ((frameType > L1_1M2BPS_5MS_FRAME) || (frameType <= L1_NONE_FRAME))
|
||||
if ((frameType > L1_FRAME_2MBPS_4MS) || (frameType <= L1_FRAME_NONE))
|
||||
{
|
||||
return INFINITY; // FIXME
|
||||
}
|
||||
|
||||
regValue = PhyRead(instPtr, FINE_FREQEST);
|
||||
estAbs = regValue & FINE_FREQEST_VAL_MASK;
|
||||
if ((frameType >= L1_200KBPS_5MS_FRAME))
|
||||
if ((frameType >= L1_FRAME_128KBPS_4MS))
|
||||
{
|
||||
// 12M Rc
|
||||
freqEst = 48e6 / 2048 * ((double)estAbs) / 8192.0;
|
||||
|
||||
@@ -34,23 +34,20 @@
|
||||
* @name PhysicalLayer_Common_Constant
|
||||
* @{
|
||||
*/
|
||||
#define L1_NUM_ANT_NRRW_PATTERN 37U
|
||||
#define L1_ANT_PATTERN_NUM 3U // 1 beam per antenna, and 3 antennas in total
|
||||
#define L1_INIT_BEAM_NO 0U
|
||||
#define L1_INIT_ANT_WD PHY_ANT_BEAM_120
|
||||
#define L1_ANT_NUM_CH 4U
|
||||
#define L1_INIT_ANT_WD PHY_ANT_BEAM_FIXED
|
||||
#define L1_ANT_CH_NUM 4U // channel number per antenna
|
||||
|
||||
#define L1_FRAME_NONE_LEN UINT32_MAX // byte
|
||||
#define L1_FRAME_NONE_COMP UINT32_MAX // *10ns(Timer_L)
|
||||
#define L1_FRAME_NONE_HOPS UINT32_MAX
|
||||
#define L1_FRAME_MAX_HOPS 81U
|
||||
#define L1_FRAME_2KBPS_20MS_HOPS 1U
|
||||
#define L1_FRAME_2KBPS_100MS_HOPS 81U
|
||||
#define L1_FRAME_10KBPS_10MS_HOPS 1U
|
||||
#define L1_FRAME_10KBPS_20MS_HOPS 11U
|
||||
#define L1_FRAME_40KBPS_20MS_HOPS 19U
|
||||
#define L1_FRAME_40KBPS_10MS_HOPS 9U
|
||||
#define L1_FRAME_200KBPS_5MS_HOPS 20U
|
||||
#define L1_FRAME_1M2BPS_5MS_HOPS 20U
|
||||
#define L1_FRAME_MAX_HOPS 81
|
||||
#define L1_FRAME_ADV_24MS_HOPS 16U // sync 16 ms + data 8 ms, 2000 hops/s
|
||||
#define L1_FRAME_ACK_8MS_HOPS 4U // sync 6 ms + data 2 ms, 2000 hops/s
|
||||
#define L1_FRAME_128KBPS_4MS_HOPS 33U
|
||||
#define L1_FRAME_512KBPS_4MS_HOPS 36U
|
||||
#define L1_FRAME_2MBPS_4MS_HOPS 38U
|
||||
#define PHY_LOG_EXPIRE 40U // 50*5ms
|
||||
/** @} */
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
@@ -60,15 +57,12 @@
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
L1_NONE_FRAME = 0,
|
||||
L1_2KBPS_20MS_FRAME = 1,
|
||||
L1_2KBPS_100MS_FRAME = 2,
|
||||
L1_10KBPS_10MS_FRAME = 3,
|
||||
L1_10KBPS_20MS_FRAME = 4,
|
||||
L1_40KBPS_20MS_FRAME = 5,
|
||||
L1_40KBPS_10MS_FRAME = 6,
|
||||
L1_200KBPS_5MS_FRAME = 7,
|
||||
L1_1M2BPS_5MS_FRAME = 8
|
||||
L1_FRAME_NONE = 0,
|
||||
L1_FRAME_ADV_24MS = 1,
|
||||
L1_FRAME_ACK_8MS = 2,
|
||||
L1_FRAME_128KBPS_4MS = 3,
|
||||
L1_FRAME_512KBPS_4MS = 4,
|
||||
L1_FRAME_2MBPS_4MS = 5
|
||||
} L1_FRAME_TYPE;
|
||||
|
||||
/**
|
||||
@@ -77,44 +71,23 @@ typedef enum
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*** Ant Control ***/
|
||||
uint8_t ctrlWord; ///< Antenna control frame head 0xAA\n
|
||||
/// default 0, reserved for further use
|
||||
uint8_t antMode; ///< high 4 bits specified beam mode.\n
|
||||
/// low 4 bits specified power control
|
||||
uint8_t oaxis[2]; ///< off-axis angle range is 0~60 \n
|
||||
/// 0.1 degree each LSB
|
||||
uint8_t raxis[2]; ///< round-axis angle range is 0~360, \n
|
||||
/// 0.1 degree each LSB
|
||||
uint8_t antFreq[2]; ///< 0~3500Mhz, step 1MHz
|
||||
uint8_t trSlect; ///< in single tr mode, 0~63 specified tr channel \n
|
||||
/// in single subarray mode, 0~3 specified the subarray
|
||||
/// ! Only in debug mode!
|
||||
uint8_t antAtt; ///< Antenna attenuation 0~31, 0.5dB each LSB, Only in debug mode
|
||||
uint8_t phase; ///< 0~63, 5.625 degree each LSB, Only in debug mode
|
||||
uint8_t rxtxMode; ///< Only for debug \n
|
||||
/// default 0x00
|
||||
uint8_t calibrMode; ///< 0x00 Normal, 0x01 single tr calibration
|
||||
uint8_t antReserved; ///< reserved for further use
|
||||
|
||||
/*** RF Control ***/
|
||||
uint8_t rfCtrl; ///< [7:4]RF enable: 0-On, 1-Off(Default); [3:0]Work mode: 0(default)
|
||||
uint8_t rfFreq[2]; ///< 0~3500Mhz, step 1MHz
|
||||
uint8_t rfTxMgc; ///< RF MGC control: 0~31, 1dB each LSB
|
||||
uint8_t rf12CalMgc; ///< RF channel 1&2 calibration mgc\n
|
||||
/// [7:4] Channle1 - max 15db, 1dB each LSB \n
|
||||
/// [3:0] Channle2 - max 15db, 1dB each LSB
|
||||
uint8_t rf34CalMgc; ///< RF channel 3&4 calibration mgc\n
|
||||
/// [7:4] Channle3 - max 15db, 1dB each LSB
|
||||
/// [3:0] Channle4 - max 15db, 1dB each LSB
|
||||
uint8_t rcvMgc; ///< Receive channel 1-4 MGC: 0~31, 1dB each LSB
|
||||
uint8_t rfMonitor; ///< Receive monitor, 0-normal, 1-switch to monitor port
|
||||
uint8_t rfReserved0; ///< reserved for further use
|
||||
uint8_t rfReserved1; ///< reserved for further use
|
||||
uint8_t ch0Cal[2];
|
||||
uint8_t ch1Cal[2];
|
||||
uint8_t ch2Cal[2];
|
||||
uint8_t ch3Cal[2];
|
||||
/*** Antenna & RF Control ***/
|
||||
uint8_t antMode; ///< Antenna control mode
|
||||
uint8_t rfNormComp[L1_ANT_PATTERN_NUM][L1_ANT_CH_NUM];
|
||||
///< Normal mode RF phase compensation, 3 antennas
|
||||
/// and 4 channels each: 0~63, 5.625° step
|
||||
uint8_t rfNormAttn[L1_ANT_PATTERN_NUM][L1_ANT_CH_NUM + 1];
|
||||
///< Normal mode RF attenuation, 3 antennas with 4
|
||||
/// independent channel and 1 mix channel: 0~30 dB,
|
||||
/// 1dB step
|
||||
uint8_t rfAntiAttn[L1_ANT_CH_NUM];
|
||||
///< Anti-jamming mode RF attenuation, 4 channels:
|
||||
/// 0~60 dB, 1dB step
|
||||
uint8_t rfFreq[L1_ANT_PATTERN_NUM][2];
|
||||
///< RF synthesizer ping-pong frequency, 3 antennas
|
||||
/// and 2 byte each: 0~600 MHz, step 1MHz, with base
|
||||
/// frequency of 3700 MHz
|
||||
uint8_t rfRsvd; ///< reserved for further use
|
||||
} PHY_ANT_CONFIG;
|
||||
|
||||
/**
|
||||
@@ -148,7 +121,8 @@ typedef enum
|
||||
PHY_ANT_BEAM_120 = 1,
|
||||
PHY_ANT_BEAM_60 = 2,
|
||||
PHY_ANT_BEAM_25 = 3,
|
||||
PHY_ANT_BEAM_16 = 4
|
||||
PHY_ANT_BEAM_16 = 4,
|
||||
PHY_ANT_BEAM_FIXED = 5
|
||||
} PHY_ANT_BEAM_WIDTH;
|
||||
|
||||
/**
|
||||
@@ -168,8 +142,7 @@ typedef enum
|
||||
{
|
||||
PHY_MODE_NONE = 0,
|
||||
PHY_MODE_LISTEN = 1,
|
||||
PHY_MODE_SCHEDULE = 2,
|
||||
PHY_MODE_PULL = 3
|
||||
PHY_MODE_POLL = 2
|
||||
} PHY_MODE;
|
||||
|
||||
/**
|
||||
@@ -179,8 +152,8 @@ typedef enum
|
||||
{
|
||||
PHY_ANT_MODE_NONE = 0,
|
||||
PHY_ANT_MODE_STANDBY = 1,
|
||||
PHY_ANT_MODE_POWER_LOW = 2,
|
||||
PHY_ANT_MODE_POWER_FULL = 3,
|
||||
PHY_ANT_MODE_NORMAL = 2,
|
||||
PHY_ANT_MODE_ANTI_JAM = 3
|
||||
} PHY_ANT_MODE;
|
||||
|
||||
/**
|
||||
@@ -243,10 +216,10 @@ typedef struct
|
||||
#ifndef EMULATION
|
||||
XAdcPs hwXadc; ///< hardware Xadc instance
|
||||
#endif
|
||||
PHY_ANT_ANGLE antNrrwPattern[L1_NUM_ANT_NRRW_PATTERN]; ///< antenna beam scan pattern
|
||||
HWSTATE hwSate; ///< hardware state log
|
||||
PHYLOG phyLog; ///< physical state log
|
||||
uint32_t lastLogTime; /// physical state log time stamp
|
||||
PHY_ANT_ANGLE antNrrwPattern[L1_ANT_PATTERN_NUM]; ///< antenna beam scan pattern
|
||||
HWSTATE hwSate; ///< hardware state log
|
||||
PHYLOG phyLog; ///< physical state log
|
||||
uint32_t lastLogTime; /// physical state log time stamp
|
||||
} PHY_INST;
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
@@ -48,8 +48,7 @@
|
||||
#define PHY_MAIN_CTRL_EN_DSBL 0x00000000U
|
||||
#define PHY_MAIN_CTRL_MODE_NONE 0x00000000U
|
||||
#define PHY_MAIN_CTRL_MODE_LISTEN 0x00000100U
|
||||
#define PHY_MAIN_CTRL_MODE_SCHEDULE 0x00000200U
|
||||
#define PHY_MAIN_CTRL_MODE_PULL 0x00000300U
|
||||
#define PHY_MAIN_CTRL_MODE_POLL 0x00000200U
|
||||
|
||||
/**
|
||||
* Register: TXRX_CTRL
|
||||
@@ -70,14 +69,11 @@
|
||||
#define PHY_MODE_CTRL_TOR_RX 0x00000002U
|
||||
|
||||
#define PHY_MODE_CTRL_FRAME_NONE 0x00000000U
|
||||
#define PHY_MODE_CTRL_FRAME_2KBPS_20MS 0x00000100U
|
||||
#define PHY_MODE_CTRL_FRAME_2KBPS_100MS 0x00000200U
|
||||
#define PHY_MODE_CTRL_FRAME_10KBPS_10MS 0x00000300U // Initial Scan Frame
|
||||
#define PHY_MODE_CTRL_FRAME_10KBPS_20MS 0x00000400U // Benchmark Frame
|
||||
#define PHY_MODE_CTRL_FRAME_40KBPS_20MS 0x00000500U
|
||||
#define PHY_MODE_CTRL_FRAME_40KBPS_10MS 0x00000600U
|
||||
#define PHY_MODE_CTRL_FRAME_200KBPS_5MS 0x00000700U // 2-Way ACQ Frame, Management Frame, Service Frame
|
||||
#define PHY_MODE_CTRL_FRAME_1M2BPS_5MS 0x00000800U // Bistatic Synthetic Aperture Radar Frame
|
||||
#define PHY_MODE_CTRL_FRAME_ADV_24MS 0x00000100U
|
||||
#define PHY_MODE_CTRL_FRAME_ACK_8MS 0x00000200U
|
||||
#define PHY_MODE_CTRL_FRAME_128KBPS_4MS 0x00000300U
|
||||
#define PHY_MODE_CTRL_FRAME_512KBPS_4MS 0x00000400U
|
||||
#define PHY_MODE_CTRL_FRAME_2MBPS_4MS 0x00000500U
|
||||
|
||||
#define PHY_MODE_CTRL_CRC_EN 0x00010000U
|
||||
#define PHY_MODE_CTRL_CRC_DSBL 0x00000000U
|
||||
@@ -236,14 +232,11 @@
|
||||
#define COASE_TYPE_SHIFT 16
|
||||
#define COASE_TYPE_WIDTH 8
|
||||
#define COASE_TYPE_MASK 0x00FF0000U
|
||||
#define COASE_TYPE_2KBPS_20MS 0x00010000U
|
||||
#define COASE_TYPE_2KBPS_100MS 0x00020000U
|
||||
#define COASE_TYPE_10KBPS_10MS 0x00030000U
|
||||
#define COASE_TYPE_10KBPS_20MS 0x00040000U
|
||||
#define COASE_TYPE_40KBPS_20MS 0x00050000U
|
||||
#define COASE_TYPE_40KBPS_10MS 0x00060000U
|
||||
#define COASE_TYPE_200KBPS_5MS 0x00070000U
|
||||
#define COASE_TYPE_1M2BPS_5MS 0x00080000U
|
||||
#define COASE_TYPE_ADV_24MS 0x00010000U
|
||||
#define COASE_TYPE_ACK_8MS 0x00020000U
|
||||
#define COASE_TYPE_128KBPS_4MS 0x00030000U
|
||||
#define COASE_TYPE_512KBPS_4MS 0x00040000U
|
||||
#define COASE_TYPE_2MBPS_4MS 0x00050000U
|
||||
|
||||
/**
|
||||
* Register: FINE_FREQEST
|
||||
@@ -269,7 +262,7 @@
|
||||
/**
|
||||
* Register: BEAM_AXIS
|
||||
*/
|
||||
#define BEAM_AXIS 0x00000044U
|
||||
#define BEAM_AXIS 0x00000048U
|
||||
#define BEAM_AXIS_EL_SHIFT 0
|
||||
#define BEAM_AXIS_EL_WIDTH 16
|
||||
#define BEAM_AXIS_EL_MASK 0x0000FFFFU
|
||||
@@ -278,84 +271,107 @@
|
||||
#define BEAM_AXIS_AZ_MASK 0xFFFF0000U
|
||||
|
||||
/**
|
||||
* Register: ANT_STATUS
|
||||
* Register: ANT_STATUS_1
|
||||
*/
|
||||
#define ANT_STATUS 0x00000100U
|
||||
#define ANT_STATUS_ANT_VOLT_SHIFT 0
|
||||
#define ANT_STATUS_ANT_VOLT_WIDTH 8
|
||||
#define ANT_STATUS_ANT_VOLT_MASK 0x000000FFU
|
||||
#define ANT_STATUS_ANT_VOLT_OK 0x00000001U
|
||||
#define ANT_STATUS_1 0x00000100U
|
||||
|
||||
#define ANT_STATUS_RF_VOLT_SHIFT 8
|
||||
#define ANT_STATUS_RF_VOLT_WIDTH 8
|
||||
#define ANT_STATUS_RF_VOLT_MASK 0x0000FF00U
|
||||
#define ANT_STATUS_RF_VOLT_OK 0x00000100U
|
||||
#define ANT_STATUS_1_ANT1_STATUS_SHIFT 0
|
||||
#define ANT_STATUS_1_ANT1_STATUS_WIDTH 16
|
||||
#define ANT_STATUS_1_ANT1_STATUS_MASK 0x0000FFFFU
|
||||
|
||||
#define ANT_STATUS_NIL_VOLT_SHIFT 16
|
||||
#define ANT_STATUS_NIL_VOLT_WIDTH 8
|
||||
#define ANT_STATUS_NIL_VOLT_MASK 0x00FF0000U
|
||||
#define ANT_STATUS_NIL_VOLT_OK 0x00010000U
|
||||
#define ANT_STATUS_1_ANT1_FREQ_SHIFT 0
|
||||
#define ANT_STATUS_1_ANT1_FREQ_WIDTH 15
|
||||
#define ANT_STATUS_1_ANT1_FREQ_MASK 0x00003FFFU
|
||||
|
||||
#define ANT_STATUS_CODE_SHIFT 24
|
||||
#define ANT_STATUS_CODE_WIDTH 8
|
||||
#define ANT_STATUS_CODE_MASK 0xFF000000U
|
||||
#define ANT_STATUS_CODE_OK 0x00000000U
|
||||
#define ANT_STATUS_1_ANT1_PLL_SHIFT 15
|
||||
#define ANT_STATUS_1_ANT1_PLL_WIDTH 1
|
||||
#define ANT_STATUS_1_ANT1_PLL_MASK 0x00008000U
|
||||
|
||||
#define ANT_STATUS_1_ANT2_STATUS_SHIFT 16
|
||||
#define ANT_STATUS_1_ANT2_STATUS_WIDTH 16
|
||||
#define ANT_STATUS_1_ANT2_STATUS_MASK 0x0000FFFFU
|
||||
|
||||
#define ANT_STATUS_1_ANT2_FREQ_SHIFT 16
|
||||
#define ANT_STATUS_1_ANT2_FREQ_WIDTH 15
|
||||
#define ANT_STATUS_1_ANT2_FREQ_MASK 0x3FFF0000U
|
||||
|
||||
#define ANT_STATUS_1_ANT2_PLL_SHIFT 31
|
||||
#define ANT_STATUS_1_ANT2_PLL_WIDTH 1
|
||||
#define ANT_STATUS_1_ANT2_PLL_MASK 0x80000000U
|
||||
|
||||
/**
|
||||
* Register: ANT_FRAME_CNT
|
||||
* Register: ANT_STATUS_2
|
||||
*/
|
||||
#define ANT_FRAME_CNT 0x00000104U
|
||||
#define ANT_FRAME_CNT_SHIFT 0
|
||||
#define ANT_FRAME_CNT_WIDTH 32
|
||||
#define ANT_FRAME_CNT_MASK 0xFFFFFFFFU
|
||||
#define ANT_STATUS_2 0x00000104U
|
||||
|
||||
#define ANT_STATUS_2_ANT3_STATUS_SHIFT 0
|
||||
#define ANT_STATUS_2_ANT3_STATUS_WIDTH 16
|
||||
#define ANT_STATUS_2_ANT3_STATUS_MASK 0x0000FFFFU
|
||||
|
||||
#define ANT_STATUS_2_ANT3_FREQ_SHIFT 0
|
||||
#define ANT_STATUS_2_ANT3_FREQ_WIDTH 15
|
||||
#define ANT_STATUS_2_ANT3_FREQ_MASK 0x00003FFFU
|
||||
|
||||
#define ANT_STATUS_2_ANT3_PLL_SHIFT 15
|
||||
#define ANT_STATUS_2_ANT3_PLL_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT3_PLL_MASK 0x00008000U
|
||||
|
||||
#define ANT_STATUS_2_PLL_LK_SHIFT 16
|
||||
#define ANT_STATUS_2_PLL_LK_WIDTH 8
|
||||
#define ANT_STATUS_2_PLL_LK_MASK 0x00FF0000U
|
||||
|
||||
#define ANT_STATUS_2_ANT3_PLL2_LK_SHIFT 16
|
||||
#define ANT_STATUS_2_ANT3_PLL2_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT3_PLL2_LK_MASK 0x00010000U
|
||||
|
||||
#define ANT_STATUS_2_ANT3_PLL1_LK_SHIFT 17
|
||||
#define ANT_STATUS_2_ANT3_PLL1_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT3_PLL1_LK_MASK 0x00020000U
|
||||
|
||||
#define ANT_STATUS_2_ANT2_PLL2_LK_SHIFT 18
|
||||
#define ANT_STATUS_2_ANT2_PLL2_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT2_PLL2_LK_MASK 0x00040000U
|
||||
|
||||
#define ANT_STATUS_2_ANT2_PLL1_LK_SHIFT 19
|
||||
#define ANT_STATUS_2_ANT2_PLL1_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT2_PLL1_LK_MASK 0x00080000U
|
||||
|
||||
#define ANT_STATUS_2_ANT1_PLL2_LK_SHIFT 20
|
||||
#define ANT_STATUS_2_ANT1_PLL2_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT1_PLL2_LK_MASK 0x00100000U
|
||||
|
||||
#define ANT_STATUS_2_ANT1_PLL1_LK_SHIFT 21
|
||||
#define ANT_STATUS_2_ANT1_PLL1_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT1_PLL1_LK_MASK 0x00200000U
|
||||
|
||||
#define ANT_STATUS_2_MODE_SHIFT 24
|
||||
#define ANT_STATUS_2_MODE_WIDTH 8
|
||||
#define ANT_STATUS_2_MODE_MASK 0xFF000000U
|
||||
|
||||
#define ANT_STATUS_2_ANT1_MODE_SHIFT 24
|
||||
#define ANT_STATUS_2_ANT1_MODE_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT1_MODE_MASK 0x01000000U
|
||||
|
||||
#define ANT_STATUS_2_ANT2_MODE_SHIFT 25
|
||||
#define ANT_STATUS_2_ANT2_MODE_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT2_MODE_MASK 0x02000000U
|
||||
|
||||
#define ANT_STATUS_2_ANT3_MODE_SHIFT 26
|
||||
#define ANT_STATUS_2_ANT3_MODE_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT3_MODE_MASK 0x04000000U
|
||||
|
||||
/**
|
||||
* Register: ANT_RF_STATUS
|
||||
* Register: ANT_STATUS_TEMP
|
||||
*/
|
||||
#define ANT_RF_STATUS 0x00000108U
|
||||
#define ANT_RF_STATUS_TEMP_SHIFT 0
|
||||
#define ANT_RF_STATUS_TEMP_WIDTH 8
|
||||
#define ANT_RF_STATUS_TEMP_MASK 0x000000FFU
|
||||
#define ANT_STATUS_TEMP 0x00000108U
|
||||
|
||||
#define ANT_RF_STATUS_BBLOCK_SHIFT 8
|
||||
#define ANT_RF_STATUS_BBLOCK_WIDTH 8
|
||||
#define ANT_RF_STATUS_BBLOCK_MASK 0x0000FF00U
|
||||
#define ANT_RF_STATUS_BBLOCK_OK 0x00000100U
|
||||
#define ANT_STATUS_TEMP_SHIFT 0
|
||||
#define ANT_STATUS_TEMP_WIDTH 8
|
||||
#define ANT_STATUS_TEMP_MASK 0x000000FFU
|
||||
|
||||
#define ANT_RF_STATUS_PLLA_SHIFT 16
|
||||
#define ANT_RF_STATUS_PLLA_WIDTH 8
|
||||
#define ANT_RF_STATUS_PLLA_MASK 0x00FF0000U
|
||||
#define ANT_RF_STATUS_PLLA_OK 0x00010000U
|
||||
|
||||
#define ANT_RF_STATUS_PLLB_SHIFT 24
|
||||
#define ANT_RF_STATUS_PLLB_WIDTH 8
|
||||
#define ANT_RF_STATUS_PLLB_MASK 0xFF000000U
|
||||
#define ANT_RF_STATUS_PLLB_OK 0x01000000U
|
||||
|
||||
/**
|
||||
* Register: ANT_RF_MGC
|
||||
*/
|
||||
#define ANT_RF_MGC 0x0000010CU
|
||||
#define ANT_RF_MGC_CH1_SHIFT 0
|
||||
#define ANT_RF_MGC_CH1_WIDTH 4
|
||||
#define ANT_RF_MGC_CH1_MASK 0x0000000FU
|
||||
#define ANT_RF_MGC_CH2_SHIFT 8
|
||||
#define ANT_RF_MGC_CH2_WIDTH 4
|
||||
#define ANT_RF_MGC_CH2_MASK 0x00000F00U
|
||||
#define ANT_RF_MGC_CH3_SHIFT 16
|
||||
#define ANT_RF_MGC_CH3_WIDTH 4
|
||||
#define ANT_RF_MGC_CH3_MASK 0x000F0000U
|
||||
#define ANT_RF_MGC_CH4_SHIFT 24
|
||||
#define ANT_RF_MGC_CH4_WIDTH 4
|
||||
#define ANT_RF_MGC_CH4_MASK 0x0F000000U
|
||||
|
||||
/**
|
||||
* Register: ANT_RF_FRAME_CNT
|
||||
*/
|
||||
#define ANT_RF_FRAME_CNT 0x00000110U
|
||||
#define ANT_RF_FRAME_CNT_SHIFT 0
|
||||
#define ANT_RF_FRAME_CNT_WIDTH 32
|
||||
#define ANT_RF_FRAME_CNT_MASK 0xFFFFFFFFU
|
||||
#define ANT_STATUS_TEMP_RSVD_SHIFT 8
|
||||
#define ANT_STATUS_TEMP_RSVD_WIDTH 8
|
||||
#define ANT_STATUS_TEMP_RSVD_MASK 0x0000FF00U
|
||||
|
||||
/**
|
||||
* Register: PHY_ACQ_CNT
|
||||
|
||||
@@ -198,11 +198,13 @@ typedef struct __attribute__((packed))
|
||||
int8_t spAdTemp_1; ///< Signal processor adc1 temperature
|
||||
int8_t spFpgaTemp; ///< Signal processor FPGA temperature
|
||||
// -- Antenna status
|
||||
uint8_t antVolt; ///< Antenna voltage state indicator
|
||||
int8_t antTemp; ///< Antenna rf temperature
|
||||
uint8_t antPll; ///< Antenna rf lock state indicator
|
||||
uint8_t antMgc0; ///< Antenna rf mgc0~1 indicator
|
||||
uint8_t antMgc1; ///< Antenna rf mgc2~3 indicator
|
||||
uint16_t ant1Freq; ///< Antenna 1 frequency
|
||||
uint16_t ant2Freq; ///< Antenna 2 frequency
|
||||
uint16_t ant3Freq; ///< Antenna 3 frequency
|
||||
uint8_t antPll; ///< Antenna pll lock state indicator
|
||||
uint8_t antMode; ///< Antenna mode indicator
|
||||
int8_t antTemp; ///< Antenna rf temperature
|
||||
uint8_t antRsvd; ///< Antenna reserved status register
|
||||
uint8_t phyId;
|
||||
uint8_t reserve[1];
|
||||
} HWSTATE;
|
||||
|
||||
Reference in New Issue
Block a user