forked from 0xha0/df_datalink
feat: 根据HJSL硬件修改相关profile
This commit is contained in:
+19
-288
@@ -34,7 +34,7 @@
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/************************** Function Prototypes ******************************/
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/*********************** Driver Instance Definitions **************************/
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static struct hmc7044_dev *hmc7044_inst = NULL;
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ad9528Device_t *ad9528_inst = NULL;
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static struct ad9361_reg_dev *ad9361_1_reg_inst = NULL;
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static struct ad9361_reg_dev *ad9361_2_reg_inst = NULL;
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// static struct ad9361_rf_phy *ad9361_phy;
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@@ -62,12 +62,17 @@ int32_t Hardware_Init(void)
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}
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/**********************************************************/
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/****************** HMC7044 Configuration *****************/
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/****************** AD9528 Configuration ******************/
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/**********************************************************/
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Status = hmc7044_init(&hmc7044_inst, &hmc7044_default_init_param);
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if (Status != SUCCESS)
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{
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DBG_ERROR("hmc7044_init() error: %" PRId32 "\n", Status);
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Status = AD9528_init(&ad9528_inst, &ad9528_default_init_param);
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if (Status != SUCCESS) {
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DBG_ERROR("AD9528_init() error: %" PRId32 "\n", Status);
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return FAILURE;
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}
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Status = AD9528_config(ad9528_inst);
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if (Status != SUCCESS) {
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DBG_ERROR("AD9528_config() error: %" PRId32 "\n", Status);
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return FAILURE;
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}
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@@ -110,110 +115,6 @@ int32_t Hardware_Init(void)
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// Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back);
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// Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back);
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/**********************************************************/
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/******* AD9361 Baseband Multichip Synchronization ********/
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/**********************************************************/
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XGpioPs_SetDirectionPin(&Gpio, AD9361_SYNC, AD9361_GPIO_OUTPUT);
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XGpioPs_SetDirectionPin(&Gpio, AD9361_RX_FIFO_RST, AD9361_GPIO_OUTPUT);
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// SYNC BBPLL and DIGITAL SAMPLING CLOCKS
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ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable
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ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D);
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ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable
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ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80);
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XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
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mdelay(20);
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XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin
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mdelay(500);
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XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
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mdelay(2000);
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ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable
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ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B);
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XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin
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mdelay(500);
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XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0);
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ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits
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ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08);
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XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
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mdelay(20);
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XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 1);
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mdelay(20);
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XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0);
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/**********************************************************/
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/********* AD9361 Multichip Rx Phase Calibration **********/
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/**********************************************************/
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XGpioPs_SetDirectionPin(&Gpio, AD9361_TX_SWITCH, AD9361_GPIO_OUTPUT);
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XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_START, AD9361_GPIO_OUTPUT);
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XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_DONE, AD9361_GPIO_INPUT);
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XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_START, AD9361_GPIO_OUTPUT);
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XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_DONE, AD9361_GPIO_INPUT);
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// switch to lower frequency
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Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126);
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XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 1);
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mdelay(20);
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// switch rx channel
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Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30);
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Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30);
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// enable dual ad9361 tx channels
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Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels
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// switch ad9361 tx channel
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Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
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mdelay(20);
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// begin to calibrate the 1st ad9361
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XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
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XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 1);
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mdelay(1);
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XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0);
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// read calibration status
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int32_t time_out_cnt = 0;
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do
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{
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mdelay(1); // Wait 1ms
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time_out_cnt++;
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} while (((XGpioPs_ReadPin(&Gpio, AD9361_1_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
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if (time_out_cnt == AD9361_TIMEOUT_TH)
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{
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return FAILURE;
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}
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// begin to calibrate the 2nd ad9361
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XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 1);
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mdelay(1);
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XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 0);
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// read calibration status
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time_out_cnt = 0;
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do
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{
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mdelay(1); // Wait 1ms
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time_out_cnt++;
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} while (((XGpioPs_ReadPin(&Gpio, AD9361_2_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH));
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if (time_out_cnt == AD9361_TIMEOUT_TH)
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{
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return FAILURE;
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}
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// enable single ad9361 tx channels
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Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels
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// switch ad9361 tx & rx channel
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Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03);
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Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03);
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// switch to higher frequency
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Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125);
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XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 0);
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Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0109, 0x00); // Rx Gain
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Status = ad9361_reg_write(ad9361_1_reg_inst, 0x010C, 0x00); // Rx Gain
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Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0109, 0x00); // Rx Gain
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@@ -224,176 +125,6 @@ int32_t Hardware_Init(void)
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return SUCCESS;
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}
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/*****************************************************************************/
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/**
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* @brief Hardware_SwitchFreq
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*
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* @param devSysMonitor_UpdateHardwareStatus(newHwState);
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* @param freq
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*
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* @return None.
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*
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******************************************************************************/
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int32_t Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq)
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{
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int32_t status = 0;
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uint8_t value = 0;
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int32_t time_out_cnt = 0;
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switch (freq)
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{
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case TX_FREQ_125:
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{
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//************************************************************
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// Setup Tx Frequency-Dependent Syntheisizer Registers
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//************************************************************
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status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
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status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
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status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
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status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
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status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
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status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
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status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
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status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp)
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status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
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status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3
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status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
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//************************************************************
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// Write Tx Frequency Words
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//************************************************************
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status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
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status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
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status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
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status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
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status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
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status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
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//************************************************************
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// Tx Quadrature Calibration Settings
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//************************************************************
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status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
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status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
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status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
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status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
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status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
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status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
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status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
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status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
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status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
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status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
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status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
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status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
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break;
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}
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case TX_FREQ_126:
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{
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//************************************************************
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// Setup Tx Frequency-Dependent Syntheisizer Registers
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//************************************************************
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status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
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status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
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status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
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status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
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status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
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status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
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status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
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status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
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status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
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status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3
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status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
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//************************************************************
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// Write Tx Frequency Words
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//************************************************************
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status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0]
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status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8]
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status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16]
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status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
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status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
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status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting
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//************************************************************
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// Tx Quadrature Calibration Settings
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//************************************************************
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status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
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status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
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status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
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status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
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status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
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status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
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status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
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status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index
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status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
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status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used
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status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
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status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
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break;
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}
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case TX_FREQ_4125:
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{
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//************************************************************
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// Setup Tx Frequency-Dependent Syntheisizer Registers
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//************************************************************
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status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0]
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status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
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status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
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status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0]
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status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0]
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status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0]
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status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
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status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp)
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status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1
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status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3
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status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3
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//************************************************************
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// Write Rx Frequency Words
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//************************************************************
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status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0]
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status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8]
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status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16]
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status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8]
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status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
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status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting
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//************************************************************
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// Tx Quadrature Calibration Settings
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//************************************************************
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status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency
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status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6])
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status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
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status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
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status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
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status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold
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status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold
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status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index
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status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count
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status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used
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status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
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status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal
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break;
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}
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|
||||
// Wait for cal to complete (Done when 0x016[4]==0)
|
||||
time_out_cnt = 0;
|
||||
do
|
||||
{
|
||||
status |= ad9361_reg_read(dev, 0x0016, &value);
|
||||
mdelay(1); // Wait 1ms
|
||||
time_out_cnt++;
|
||||
} while ((value & 0x10) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
// @ Get AD9361 - 1 temperature (Celsius Degree)
|
||||
/**
|
||||
* Read corresponding register to get AD9361 - 1 current temperature.
|
||||
@@ -453,22 +184,22 @@ uint8_t Hardware_GetAD9361LockStatus(void)
|
||||
return ret;
|
||||
}
|
||||
|
||||
// @ Determine HMC7044 lock state
|
||||
// @ Determine AD9528 lock state
|
||||
/**
|
||||
* Read corresponding register to determine clock lock state.
|
||||
*/
|
||||
uint8_t Hardware_GetHMC7044LockStatus(void)
|
||||
uint8_t Hardware_GetAD9528LockStatus(void)
|
||||
{
|
||||
uint8_t ret = 0;
|
||||
uint8_t regVal;
|
||||
|
||||
// pll1
|
||||
hmc7044_read(hmc7044_inst, 0x007C, ®Val); // [D5] is lock indicator
|
||||
ret |= ((regVal & 0xE0) != 0x00) ? CLK_SP_PLL0_LOCK : 0;
|
||||
|
||||
// pll2
|
||||
hmc7044_read(hmc7044_inst, 0x007D, ®Val); // [D0] is lock indicator
|
||||
AD9528_spiReadByte(ad9528_inst, AD9528_ADDR_STATUS_READBACK0, ®Val); // [D0] is lock indicator
|
||||
ret |= ((regVal & 0x01) == 0x01) ? CLK_SP_PLL1_LOCK : 0;
|
||||
|
||||
// pll2
|
||||
AD9528_spiReadByte(ad9528_inst, AD9528_ADDR_STATUS_READBACK0, ®Val); // [D1] is lock indicator
|
||||
ret |= ((regVal & 0x02) == 0x02) ? CLK_SP_PLL2_LOCK : 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user