From 0d6a5491ad9465c28b293f3117613505e6da2cb9 Mon Sep 17 00:00:00 2001 From: Josh Gao Date: Thu, 5 Jun 2025 16:52:31 +0800 Subject: [PATCH] =?UTF-8?q?feat:=20=E6=B7=BB=E5=8A=A0LMK04828=E9=94=81?= =?UTF-8?q?=E5=AE=9A=E7=8A=B6=E6=80=81=E7=9A=84=E5=9B=9E=E8=AF=BB?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/hwconfig.c | 22 ++++++++++++++++++++++ src/hwconfig.h | 3 +-- src/main.c | 12 ++++++++---- 3 files changed, 31 insertions(+), 6 deletions(-) diff --git a/src/hwconfig.c b/src/hwconfig.c index 56f26f3..8bc0a1f 100644 --- a/src/hwconfig.c +++ b/src/hwconfig.c @@ -494,3 +494,25 @@ uint8_t Hardware_GetAD9528LockStatus(void) return ret; } + +// @ Determine LMK04828 lock state +/** + * Read corresponding register to determine clock lock state. + */ +uint8_t Hardware_GetLMK04828LockStatus(void) +{ + ASSERT(lmk04828_inst != NULL); + + uint8_t ret = 0; + uint8_t regVal; + + // pll1 + lmk04828_read(lmk04828_inst, 0x0182, ®Val); // [D1] is lock indicator + ret |= ((regVal & 0x02) == 0x02) ? CLK_SP_PLL1_LOCK : 0; + + // pll2 + lmk04828_read(ad9528_inst, 0x0183, ®Val); // [D1] is lock indicator + ret |= ((regVal & 0x02) == 0x02) ? CLK_SP_PLL2_LOCK : 0; + + return ret; +} diff --git a/src/hwconfig.h b/src/hwconfig.h index 766a967..726a028 100644 --- a/src/hwconfig.h +++ b/src/hwconfig.h @@ -27,5 +27,4 @@ int8_t Hardware_GetAD9361Temp_1(void); int8_t Hardware_GetAD9361Temp_2(void); uint8_t Hardware_GetAD9361LockStatus(void); uint8_t Hardware_GetHMC7044LockStatus(void); - - +uint8_t Hardware_GetLMK04828LockStatus(void); diff --git a/src/main.c b/src/main.c index 93b30c5..cc2f87e 100644 --- a/src/main.c +++ b/src/main.c @@ -104,13 +104,17 @@ static PHY_CONFIG phyConfig = { .rxBramId = PHY_RXBUFF_BRAM_DEVICE_ID, #ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+) .hwSysmonId = PHY_HW_SYSMON_DEVICE_ID, -#else - .hwXadcId = PHY_HW_XADC_DEVICE_ID, -#endif - .get_clk_state = NULL, + .get_clk_state = Hardware_GetLMK04828LockStatus, .get_ad_lock_state = NULL, .get_ad0_temp = NULL, .get_ad1_temp = NULL +#else + .hwXadcId = PHY_HW_XADC_DEVICE_ID, + .get_clk_state = Hardware_GetAD9528LockStatus, + .get_ad_lock_state = Hardware_GetAD9361LockStatus, + .get_ad0_temp = Hardware_GetAD9361Temp_1, + .get_ad1_temp = Hardware_GetAD9361Temp_2 +#endif }; TMC_CONFIG tmcConfig = {