From 413c984e8541066a4fd25619143f21422b51ec20 Mon Sep 17 00:00:00 2001
From: Gatsby Van <mail.gatsby.icu>
Date: Wed, 31 Jan 2024 16:07:12 +0800
Subject: [PATCH] *update self test response (add full hardware status info)

---
 df_datalink_sp/src/systembus/systembus.c | 63 +++++++++++++++++-------
 1 file changed, 46 insertions(+), 17 deletions(-)

diff --git a/df_datalink_sp/src/systembus/systembus.c b/df_datalink_sp/src/systembus/systembus.c
index b086ba3..44f7f4e 100644
--- a/df_datalink_sp/src/systembus/systembus.c
+++ b/df_datalink_sp/src/systembus/systembus.c
@@ -51,25 +51,33 @@
 #define WD_ST_RET 0x02
 #define ST_RET_OK 0xAA
 #define ST_RET_ERROR 0x55
-// -- -- Signal processor voltage
-#define WD_SP_VOLT 0x03
+
+// -- -- Signal processor PS voltage
+#define WD_SP_PS_VOLT 0x03
+// -- -- Signal processor PS AUX voltage
+#define WD_SP_PSAUX_VOLT 0x04
+// -- -- Signal processor DDR voltage
+#define WD_SP_DDR_VOLT 0x05
+// -- -- Signal processor PL voltage
+#define WD_SP_PL_VOLT 0x06
+// -- -- Signal processor PL AUX voltage
+#define WD_SP_PLAUX_VOLT 0x07
+// -- -- Signal processor Bram voltage
+#define WD_SP_BRAM_VOLT 0x08
 // -- -- Signal processor temperature
-#define WD_SP_TEMP 0x04
-// -- -- Signal processor chip status
-#define WD_SP_CS 0x05
-// -- -- Signal processor antenna voltage
-#define WD_ANT_VOLT 0x06
-// -- -- Signal processor antenna temperature
-#define WD_ANT_TEMP 0x07
+#define WD_SP_TEMP 0x09
+
+// -- -- Signal processor antenna voltage status
+#define WD_ANT_VOLT 0x0A
+// -- -- Signal processor antenna RF temperature
+#define WD_ANT_RF_TEMP 0x0B
 // -- -- Signal processor antenna PLL lock status
-#define WD_ANT_PLL 0x08
+#define WD_ANT_RF_PLL 0x0C
 // -- -- Signal processor antenna MGC
-#define WD_ANT_MGC_L 0x09
-#define WD_ANT_MGC_H 0x0A
-// -- -- Signal processor antenna status
-#define WD_ANT_ST 0x0B
+#define WD_ANT_MGC_0 0x0D
+#define WD_ANT_MGC_1 0x0E
 // -- -- Dummy must be 0x00
-#define WD_ST_DUMMY 0x0C
+#define WD_ST_DUMMY 0x0F
 
 // Data Send Test Command
 #define CMD_DATA_TEST_A 0xE2
@@ -281,6 +289,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 	{
 	case CMD_SELF_TEST:
 	{
+		const HWSTATE *hwStatsPtr;
 		sysbusRsp = malloc(sizeof(SYSBUS_UART_FRAME));
 		if (sysbusRsp == NULL) {
 			DBG_ERROR("Failed to allocate memory for SELF TEST Response!\n");
@@ -291,9 +300,29 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		memset(sysbusRsp->data, 0x00, ST_RSP_LEN);
 		sysbusRsp->data[WD_CMD] = CMD_SELF_TEST;
 		sysbusRsp->data[WD_PRD] = MY_PRD_ID;
+		hwStatsPtr = Phy_RefreshHwSate(linkInstPtr->config.phyInstPtr);
+		if (linkInstPtr->isEnable == false) 
+		{
+			sysbusRsp->data[WD_ST_RET] = (hwStatsPtr->isSpOk) ? ST_RET_OK : ST_RET_ERROR;
+		}
+		else 
+		{
+			sysbusRsp->data[WD_ST_RET] = (hwStatsPtr->isSpOk && hwStatsPtr->isAntOk) ? ST_RET_OK : ST_RET_ERROR;
+		}
+		sysbusRsp->data[WD_SP_PS_VOLT] = hwStatsPtr->spPsVolt;
+		sysbusRsp->data[WD_SP_PSAUX_VOLT] = hwStatsPtr->spPsAuxVolt;
+		sysbusRsp->data[WD_SP_DDR_VOLT] = hwStatsPtr->spDdrVolt;
+		sysbusRsp->data[WD_SP_PL_VOLT] = hwStatsPtr->spPlVolt;
+		sysbusRsp->data[WD_SP_PLAUX_VOLT] = hwStatsPtr->spPlAuxVolt;
+		sysbusRsp->data[WD_SP_BRAM_VOLT] = hwStatsPtr->spBramVolt;
+		sysbusRsp->data[WD_SP_TEMP] = hwStatsPtr->spTemp;
+		sysbusRsp->data[WD_ANT_VOLT] = hwStatsPtr->antVolt;
+		sysbusRsp->data[WD_ANT_RF_TEMP] = hwStatsPtr->antTemp;
+		sysbusRsp->data[WD_ANT_RF_PLL] = hwStatsPtr->antPll;
+		sysbusRsp->data[WD_ANT_MGC_0] = hwStatsPtr->antMgc0;
+		sysbusRsp->data[WD_ANT_MGC_1] = hwStatsPtr->antMgc1;
+		sysbusRsp->data[WD_ST_DUMMY] = 0; // dummy byte should always be 0
 
-		// FIXME: run self-test and insert result
-		sysbusRsp->data[WD_ST_RET] = ST_RET_OK;
 		if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false)
 		{
 			free(sysbusRsp);