diff --git a/src/dev_profile/ad9528_profile.c b/src/dev_profile/ad9528_profile.c
index c2116c1..ae39334 100644
--- a/src/dev_profile/ad9528_profile.c
+++ b/src/dev_profile/ad9528_profile.c
@@ -38,16 +38,30 @@ static struct gpio_init_param ad9528_gpio_sysref_req_init = {
 	.extra = &xil_gpio_param
 };
 
+// single board, without rf
+// static ad9528pll1Settings_t clockPll1Settings = {
+//    .refA_Frequency_Hz  = 50000000,
+//    .refA_Divider       = 1,
+//    .refA_bufferCtrl    = SINGLE_ENDED,
+//    .refB_Frequency_Hz  = 0,
+//    .refB_Divider       = 1,
+//    .refB_bufferCtrl    = DISABLED,
+//    .vcxo_Frequency_Hz  = 50000000,
+//    .vcxoBufferCtrl     = SINGLE_ENDED,
+//    .nDivider           = 1
+// };
+
+// with rf
 static ad9528pll1Settings_t clockPll1Settings = {
-    .refA_Frequency_Hz  = 50000000,
-    .refA_Divider       = 1,
-    .refA_bufferCtrl    = SINGLE_ENDED,
+    .refA_Frequency_Hz  = 40000000,
+    .refA_Divider       = 4,
+    .refA_bufferCtrl    = DIFFERENTIAL,
     .refB_Frequency_Hz  = 0,
     .refB_Divider       = 1,
     .refB_bufferCtrl    = DISABLED,
     .vcxo_Frequency_Hz  = 50000000,
     .vcxoBufferCtrl     = SINGLE_ENDED,
-    .nDivider           = 1
+    .nDivider           = 5
 };
 
 static ad9528pll2Settings_t clockPll2Settings = {
diff --git a/src/drivers/frequency/ad9528/ad9528.c b/src/drivers/frequency/ad9528/ad9528.c
index 7894fd6..bf2f4e7 100644
--- a/src/drivers/frequency/ad9528/ad9528.c
+++ b/src/drivers/frequency/ad9528/ad9528.c
@@ -668,7 +668,7 @@ int32_t AD9528_config(ad9528Device_t
 		if(AD9528_hasTimeoutExpired() > 0) {
 			return FAILURE;
 		}
-	} while((reg508 & 0x26) != 0x26);
+	} while((reg508 & 0xE7) != 0xE7);
 
 	return SUCCESS;
 }
diff --git a/src/hwconfig.c b/src/hwconfig.c
index 6d87ce7..56f26f3 100644
--- a/src/hwconfig.c
+++ b/src/hwconfig.c
@@ -312,31 +312,31 @@ int32_t Hardware_Init(void)
      *
      */
 
-    // get & set mixer settings
-    XRFdc_Mixer_Settings Mixer_Settings_DAC;
-
-    // 3th channel
-    Status = XRFdc_GetMixerSettings(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
-    		XRFDC_BLK_ID0, &Mixer_Settings_DAC);
-    if (Status != XST_SUCCESS) {
-        return XST_FAILURE;
-    }
-
-	Mixer_Settings_DAC.Freq = 1500;
-
-	Status = XRFdc_SetMixerSettings(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
-			XRFDC_BLK_ID0, &Mixer_Settings_DAC);
-	if (Status != XST_SUCCESS) {
-		return XST_FAILURE;
-	}
-
-	mdelay(100);
-
-	Status = XRFdc_UpdateEvent(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
-			XRFDC_BLK_ID0, XRFDC_EVENT_MIXER);
-	if (Status != XST_SUCCESS) {
-		return XST_FAILURE;
-	}
+//    // get & set mixer settings
+//    XRFdc_Mixer_Settings Mixer_Settings_DAC;
+//
+//    // 3th channel
+//    Status = XRFdc_GetMixerSettings(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
+//    		XRFDC_BLK_ID0, &Mixer_Settings_DAC);
+//    if (Status != XST_SUCCESS) {
+//        return XST_FAILURE;
+//    }
+//
+//	Mixer_Settings_DAC.Freq = 1500;
+//
+//	Status = XRFdc_SetMixerSettings(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
+//			XRFDC_BLK_ID0, &Mixer_Settings_DAC);
+//	if (Status != XST_SUCCESS) {
+//		return XST_FAILURE;
+//	}
+//
+//	mdelay(100);
+//
+//	Status = XRFdc_UpdateEvent(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
+//			XRFDC_BLK_ID0, XRFDC_EVENT_MIXER);
+//	if (Status != XST_SUCCESS) {
+//		return XST_FAILURE;
+//	}
 
 	 /*
 	 * ADC Mapping:
@@ -352,32 +352,32 @@ int32_t Hardware_Init(void)
 	 *
 	 */
 
-	// get & set mixer settings
-	XRFdc_Mixer_Settings Mixer_Settings_ADC;
-
-	// 3rd channel
-	Status = XRFdc_GetMixerSettings(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
-			XRFDC_BLK_ID0, &Mixer_Settings_ADC);
-	if (Status != XST_SUCCESS) {
-		return XST_FAILURE;
-	}
-
-	Mixer_Settings_ADC.Freq = 1500;
-	Mixer_Settings_ADC.EventSource = XRFDC_EVNT_SRC_TILE;
-
-	Status = XRFdc_SetMixerSettings(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
-			XRFDC_BLK_ID0, &Mixer_Settings_ADC);
-	if (Status != XST_SUCCESS) {
-		return XST_FAILURE;
-	}
-
-	mdelay(100);
-
-	Status = XRFdc_UpdateEvent(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
-			XRFDC_BLK_ID0, XRFDC_EVENT_MIXER);
-	if (Status != XST_SUCCESS) {
-		return XST_FAILURE;
-	}
+//	// get & set mixer settings
+//	XRFdc_Mixer_Settings Mixer_Settings_ADC;
+//
+//	// 3rd channel
+//	Status = XRFdc_GetMixerSettings(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
+//			XRFDC_BLK_ID0, &Mixer_Settings_ADC);
+//	if (Status != XST_SUCCESS) {
+//		return XST_FAILURE;
+//	}
+//
+//	Mixer_Settings_ADC.Freq = 1500;
+//	Mixer_Settings_ADC.EventSource = XRFDC_EVNT_SRC_TILE;
+//
+//	Status = XRFdc_SetMixerSettings(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
+//			XRFDC_BLK_ID0, &Mixer_Settings_ADC);
+//	if (Status != XST_SUCCESS) {
+//		return XST_FAILURE;
+//	}
+//
+//	mdelay(100);
+//
+//	Status = XRFdc_UpdateEvent(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
+//			XRFDC_BLK_ID0, XRFDC_EVENT_MIXER);
+//	if (Status != XST_SUCCESS) {
+//		return XST_FAILURE;
+//	}
 
 #endif
 
diff --git a/src/networking/link_layer/routine_table.c b/src/networking/link_layer/routine_table.c
index 45ff6a3..db77ac0 100644
--- a/src/networking/link_layer/routine_table.c
+++ b/src/networking/link_layer/routine_table.c
@@ -311,4 +311,4 @@ L2_RTNE_TABLE_ENTRY *normalTable[L2_NORMAL_RTNE_PERIOD] =
 };
 
 /** @} RoutineTable*/
-/** @} LinkLayer*/
\ No newline at end of file
+/** @} LinkLayer*/
diff --git a/src/networking/phy_layer/phy_antenna.c b/src/networking/phy_layer/phy_antenna.c
index 0aaf004..2251728 100644
--- a/src/networking/phy_layer/phy_antenna.c
+++ b/src/networking/phy_layer/phy_antenna.c
@@ -204,11 +204,12 @@ const uint8_t hopPattern_ADV_24MS[L1_FRAME_ADV_24MS_HOPS] =
 {
 	0U, 35U, 66U, 47U, 40U, 16U, 30U, 65U,
 	43U, 7U, 70U, 63U, 7U, 65U, 42U, 28U,
+	2U
 };
 
 const uint8_t hopPattern_ACK_8MS[L1_FRAME_ACK_8MS_HOPS] =
 {
-	0U,  5U, 49U, 25U,
+	0U,  5U, 49U, 25U, 7U
 };
 
 const uint8_t hopPattern_128KBPS_4MS[L1_FRAME_128KBPS_4MS_HOPS] =
diff --git a/src/networking/phy_layer/phy_layer.c b/src/networking/phy_layer/phy_layer.c
index 0b6d4af..1b89605 100644
--- a/src/networking/phy_layer/phy_layer.c
+++ b/src/networking/phy_layer/phy_layer.c
@@ -43,7 +43,7 @@
 #define L1_FRAME_2MBPS_4MS_LEN (10224 / 8)	// byte
 
 //#define L1_FRAME_ADV_24MS_COMP 1399800	// *10ns(Timer_L)
-#define L1_FRAME_ADV_24MS_COMP 1463848	// *10ns(Timer_L)
+#define L1_FRAME_ADV_24MS_COMP 1464362	// *10ns(Timer_L)
 #define L1_FRAME_ACK_8MS_COMP 598408	// *10ns(Timer_L)
 #define L1_FRAME_128KBPS_4MS_COMP 9950	// *10ns(Timer_L)
 #define L1_FRAME_512KBPS_4MS_COMP 9950	// *10ns(Timer_L)
@@ -1147,7 +1147,7 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
 	/*** Temperature and Reserved Control ***/
 	rawData = PhyRead(instPtr, ANT_STATUS_TEMP);
 	//-- Update Antenna Temperature (signed 8bit integer, 1 centigrade per LSB)
-	instPtr->hwSate.antTemp = (uint8_t)(rawData & ANT_STATUS_TEMP_MASK) >> ANT_STATUS_TEMP_SHIFT;
+	instPtr->hwSate.antTemp = (int8_t)(rawData & ANT_STATUS_TEMP_MASK) >> ANT_STATUS_TEMP_SHIFT;
 	instPtr->hwSate.antRsvd = (uint8_t)(rawData & ANT_STATUS_TEMP_RSVD_MASK) >> ANT_STATUS_TEMP_RSVD_SHIFT;
 
 	// Determine if antenna is ok.
diff --git a/src/networking/phy_layer/phy_layer.h b/src/networking/phy_layer/phy_layer.h
index 03da62a..3b0ae16 100644
--- a/src/networking/phy_layer/phy_layer.h
+++ b/src/networking/phy_layer/phy_layer.h
@@ -46,8 +46,8 @@
 #define L1_FRAME_NONE_COMP UINT32_MAX // *10ns(Timer_L)
 #define L1_FRAME_NONE_HOPS UINT32_MAX
 #define L1_FRAME_MAX_HOPS 81
-#define L1_FRAME_ADV_24MS_HOPS 16U // sync 16 ms + data 8 ms, 2000 hops/s
-#define L1_FRAME_ACK_8MS_HOPS 4U // sync 6 ms + data 2 ms, 2000 hops/s
+#define L1_FRAME_ADV_24MS_HOPS 17U // sync 16 ms + data 8 ms, 2000 hops/s
+#define L1_FRAME_ACK_8MS_HOPS 5U // sync 6 ms + data 2 ms, 2000 hops/s
 #define L1_FRAME_128KBPS_4MS_HOPS 33U
 #define L1_FRAME_512KBPS_4MS_HOPS 36U
 #define L1_FRAME_2MBPS_4MS_HOPS 38U