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update hardware validation constrain

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bit-cyber-fh
2024-06-12 10:28:38 +08:00
parent 5af74419e0
commit 884d9bcca9
2 changed files with 14 additions and 9 deletions
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df_datalink_sp/src/hwconfig.c
+8 -3
View File
@@ -401,12 +401,15 @@ int32_t Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq)
int8_t Hardware_GetAD9361Temp_1(void) int8_t Hardware_GetAD9361Temp_1(void)
{ {
int8_t scaleTemp; int8_t scaleTemp;
double temp;
ad9361_reg_write(ad9361_1_reg_inst, 0x000B, -64);
ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x01); // disable aux adc ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x01); // disable aux adc
ad9361_reg_read(ad9361_1_reg_inst, 0x000E, (uint8_t*)&scaleTemp); ad9361_reg_read(ad9361_1_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x00); // enable aux adc ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x00); // enable aux adc
return (int8_t) scaleTemp/1.16; temp = ((double)scaleTemp + 64)/1.16;
return ((temp > INT8_MAX) ? INT8_MAX : (int8_t)temp);
} }
// @ Get AD9361 - 2 temperature (Celsius Degree) // @ Get AD9361 - 2 temperature (Celsius Degree)
@@ -416,12 +419,14 @@ int8_t Hardware_GetAD9361Temp_1(void)
int8_t Hardware_GetAD9361Temp_2(void) int8_t Hardware_GetAD9361Temp_2(void)
{ {
int8_t scaleTemp; int8_t scaleTemp;
double temp;
ad9361_reg_write(ad9361_2_reg_inst, 0x000B, -64);
ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x01); // disable aux adc ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x01); // disable aux adc
ad9361_reg_read(ad9361_2_reg_inst, 0x000E, (uint8_t*)&scaleTemp); ad9361_reg_read(ad9361_2_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x00); // enable aux adc ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x00); // enable aux adc
temp = ((double)scaleTemp + 64)/1.16;
return (int8_t) scaleTemp/1.16; return ((temp > INT8_MAX) ? INT8_MAX : (int8_t)temp);
} }
// @ Determine AD9361 lock state // @ Determine AD9361 lock state
df_datalink_sp/src/system_monitor.h
+6 -6
View File
@@ -54,12 +54,12 @@
// #define IS_PL_VALID(x) (x <= 1.03 && x >= 0.97) // #define IS_PL_VALID(x) (x <= 1.03 && x >= 0.97)
// #define IS_PLAUX_VALID(x) (x <= 1.89 && x >= 1.71) // #define IS_PLAUX_VALID(x) (x <= 1.89 && x >= 1.71)
// #define IS_BRAM_VALID(x) (x <= 1.03 && x >= 0.97) // #define IS_BRAM_VALID(x) (x <= 1.03 && x >= 0.97)
#define IS_PS_VALID(x) (x <= 1.05 && x >= 0.95) #define IS_PS_VALID(x) (x <= 1.1 && x >= 0.9)
#define IS_PSAUX_VALID(x) (x <= 1.89 && x >= 1.71) #define IS_PSAUX_VALID(x) (x <= 2.0 && x >= 1.6)
#define IS_DDR_VALID(x) (x <= 1.89 && x >= 1.14) #define IS_DDR_VALID(x) (x <= 1.7 && x >= 1.3)
#define IS_PL_VALID(x) (x <= 1.03 && x >= 0.96) #define IS_PL_VALID(x) (x <= 1.1 && x >= 0.9)
#define IS_PLAUX_VALID(x) (x <= 1.89 && x >= 1.71) #define IS_PLAUX_VALID(x) (x <= 2.0 && x >= 1.6)
#define IS_BRAM_VALID(x) (x <= 1.03 && x >= 0.96) #define IS_BRAM_VALID(x) (x <= 1.1 && x >= 0.9)
#define CLK_SP_PLL0_LOCK BIT(0) #define CLK_SP_PLL0_LOCK BIT(0)
#define CLK_SP_PLL1_LOCK BIT(2) #define CLK_SP_PLL1_LOCK BIT(2)