forked from 0xha0/df_datalink
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2
Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 josh
|
08e1965a8e | ||
|
josh
|
0753c698f7 |
@@ -425,7 +425,7 @@ L1_FRAME_TYPE L2_L2frame2L1frame(L2_FRAME_TYPE l2Frame)
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case L2_SVC_FRAME:
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return L1_40KBPS_20MS_FRAME;
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default:
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return L1_NONE_FRAME;
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return L1_FRAME_NONE;
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}
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}
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/** @} LinkLayer_Utility*/
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@@ -1030,14 +1030,14 @@ int32_t Linklayer_Proc(L2_INST *instPtr)
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// Run Link layer routine, setup next slot procedure.
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if (L2_GetNodeType(instPtr) == L2_NODE_HEAD)
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{
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Phy_SetMode(phyRef, PHY_MODE_PULL);
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Phy_SetMode(phyRef, PHY_MODE_POLL);
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Status = Linklayer_Routine(instPtr);
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}
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else
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{ // L2_NODE_MEMBER
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if (L2_isCxn2Net(instPtr))
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{
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Phy_SetMode(phyRef, PHY_MODE_PULL);
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Phy_SetMode(phyRef, PHY_MODE_POLL);
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Status = Linklayer_Routine(instPtr);
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}
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else
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@@ -42,7 +42,7 @@
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/************************** Variable Definitions *****************************/
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// Pair by regex
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// Regex: ((\{\.oaxis = [0-9]+[ ,]+\.raxis = [0-9]+[ ]*\}, ){2})
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PHY_ANT_ANGLE antNrrwPattern_0[L1_NUM_ANT_NRRW_PATTERN] =
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PHY_ANT_ANGLE antNrrwPattern_0[L1_ANT_PATTERN_NUM] =
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{
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{.oaxis = 0 , .raxis = 0 },
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{.oaxis = 139, .raxis = 2225},
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@@ -83,7 +83,7 @@ PHY_ANT_ANGLE antNrrwPattern_0[L1_NUM_ANT_NRRW_PATTERN] =
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{.oaxis = 450, .raxis = 897 }
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};
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PHY_ANT_ANGLE antNrrwPattern_1[L1_NUM_ANT_NRRW_PATTERN] =
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PHY_ANT_ANGLE antNrrwPattern_1[L1_ANT_PATTERN_NUM] =
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{
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{.oaxis = 0 , .raxis = 0 },
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{.oaxis = 139, .raxis = 1155},
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@@ -272,7 +272,7 @@ static int32_t Scan_AdvHandler(L2_INST *instPtr)
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// since first time sync procedure is accomplished in ADV stage.
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(void)Phy_SetBeamWidth(phyRef, PHY_ANT_BEAM_16);
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(void)Phy_SetBeamNo(phyRef, scanFsmPtr->beamNo, PHY_ANT_BEAM_16);
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(void)Phy_SetMode(phyRef, PHY_MODE_PULL);
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(void)Phy_SetMode(phyRef, PHY_MODE_POLL);
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(void)L2_SetupNextSlot(instPtr, L2_TOR_RX, L2_CFM_FRAME);
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scanFsmPtr->cfmTimeout++; // increase counter.
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instPtr->log.lastBeamWidth = PHY_ANT_BEAM_16;
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@@ -334,7 +334,7 @@ static int32_t Scan_CfmHandler(L2_INST *instPtr)
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// since first time sync procedure is accomplished in ADV stage.
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(void)Phy_SetBeamWidth(phyRef, PHY_ANT_BEAM_16);
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(void)Phy_SetBeamNo(phyRef, scanFsmPtr->beamNo, PHY_ANT_BEAM_16);
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(void)Phy_SetMode(phyRef, PHY_MODE_PULL);
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(void)Phy_SetMode(phyRef, PHY_MODE_POLL);
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(void)L2_SetupNextSlot(instPtr, L2_TOR_RX, L2_CFM_FRAME);
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scanFsmPtr->cfmTimeout++; // increase counter.
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instPtr->log.lastBeamWidth = PHY_ANT_BEAM_16;
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@@ -54,7 +54,7 @@ int32_t L2_GetTimeDeviation(L2_INST *instPtr, uint32_t frameNum, uint32_t slotNu
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L1_FRAME_TYPE lastRecvdFrame;
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PHY_INST *phyRef = instPtr->config.phyInstPtr;
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lastRecvdFrame = Phy_GetLastRecvFrameType(phyRef);
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if (lastRecvdFrame == L1_NONE_FRAME)
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if (lastRecvdFrame == L1_FRAME_NONE)
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{
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DBG_ERROR("Invalid TimeAlign operation, no frame was received.");
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return EIGNORE;
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@@ -38,53 +38,48 @@
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#define CTRL_WORD_DEFAULT 0x00
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#define ANT_MODE_BEAM_MASK 0xF0
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#define ANT_BEAM_NARROR 0x00 // 8
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#define ANT_BEAM_SUBNARROR_0 0x10 // 25
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#define ANT_BEAM_SUBNARROR_1 0x20 // 60
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#define ANT_BEAM_WIDE 0x30 // 120
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#define ANT_MODE_TX_MASK 0x70
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#define ANT_MODE_RX_MASK 0x0F
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#define ANT_MODE_POWER_MASK 0x0F
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#define ANT_POWER_FULL 0x00
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#define ANT_POWER_LOW 0x04
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#define ANT_POWER_STANDBY 0x0F
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#define ATN_MODE_SILENT (ANT_BEAM_SUBNARROR_0 | ANT_POWER_STANDBY)
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#define ATN_MODE_LOWPOWER (ANT_BEAM_SUBNARROR_0 | ANT_POWER_LOW)
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#define ATN_MODE_FULLPOWER (ANT_BEAM_SUBNARROR_0 | ANT_POWER_FULL)
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#define ATN_MODE_DEFAULT ATN_MODE_SILENT
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#define ANT_MODE_TX_OFF 0x00
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#define ANT_MODE_TX1 BIT(4)
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#define ANT_MODE_TX2 BIT(5)
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#define ANT_MODE_TX3 BIT(6)
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#define DEFAULT_CENTRTAL_FREQ 0x06D7 // 26.25GHz
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#define ANT_MODE_RX_AJ BIT(0)
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#define ANT_MODE_RX_NORMAL 0x00
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#define RXTXMODE_RX 0x00
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#define RXTXMODE_TX 0x01
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#define ANT_MODE_RX_AJ1 (BIT(1) | ANT_MODE_RX_AJ)
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#define ANT_MODE_RX_AJ2 (BIT(2) | ANT_MODE_RX_AJ)
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#define ANT_MODE_RX_AJ3 (BIT(3) | ANT_MODE_RX_AJ)
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#define RXTXMODE_DEFAULT 0x00
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#define ATN_MODE_DEFAULT (ANT_MODE_TX_OFF | ANT_MODE_RX_NORMAL)
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#define CALIBRMODE_NORMAL 0x00
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#define CALIBRMODE_SINGLE_TR_CAL 0x01
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#define RF_CTRL_DEFAULT 0x00
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#define DEFAULT_CENTRTAL_FREQ 300U // 4 GHz
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// Pair by regex
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// Regex: (([0-9]+, ){8})
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const uint16_t freqTable[L1_FRAME_MAX_HOPS] =
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{
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1084U, 1097U, 1110U, 1123U, 1136U, 1149U, 1162U, 1175U,
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||||
1188U, 1201U, 1214U, 1227U, 1240U, 1253U, 1266U, 1279U,
|
||||
1292U, 1305U, 1318U, 1331U, 1344U, 1357U, 1370U, 1383U,
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||||
1396U, 1409U, 1422U, 1435U, 1448U, 1461U, 1474U, 1487U,
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1500U, 1513U, 1526U, 1539U, 1552U, 1565U, 1578U, 1591U,
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1604U, 1617U, 1630U, 1643U, 1656U, 1669U, 1682U, 1695U,
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1708U, 1721U, 1734U, 1747U, 1760U, 1773U, 1786U, 1799U,
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1812U, 1825U, 1838U, 1851U, 1864U, 1877U, 1890U, 1903U,
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1916U, 1929U, 1942U, 1955U, 1968U, 1981U, 1994U, 2007U,
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2020U, 2033U, 2046U, 2059U, 2072U, 2085U, 2098U, 2111U,
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2124U
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0U, 7U, 15U, 22U, 30U, 37U, 45U, 52U,
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60U, 67U, 75U, 82U, 90U, 97U, 105U, 112U,
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||||
120U, 127U, 135U, 142U, 150U, 157U, 165U, 172U,
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||||
180U, 187U, 195U, 202U, 210U, 217U, 225U, 232U,
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||||
240U, 247U, 255U, 262U, 270U, 277U, 285U, 292U,
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||||
300U, 307U, 315U, 322U, 330U, 337U, 345U, 352U,
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||||
360U, 367U, 375U, 382U, 390U, 397U, 405U, 412U,
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||||
420U, 427U, 435U, 442U, 450U, 457U, 465U, 472U,
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||||
480U, 487U, 495U, 502U, 510U, 517U, 525U, 532U,
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540U, 547U, 555U, 562U, 570U, 577U, 585U, 592U,
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600U,
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};
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const int16_t antCalTable[L1_FRAME_MAX_HOPS][L1_ANT_NUM_CH] =
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const uint8_t antCalTable[L1_ANT_NUM][L1_FRAME_MAX_HOPS][L1_ANT_CH_NUM] =
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//Antenna-JG01
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{
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// Antenna-1
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{
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{ 0, 2525, -7533, -6846}, { 0, 12726, -7818, -6860},
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{ 0, 2490, -7836, -6907}, { 0, 4479, -7716, -6837},
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{ 0, 6409, -7770, -6776}, { 0, 14616, -7977, -6816},
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@@ -126,64 +121,133 @@ const int16_t antCalTable[L1_FRAME_MAX_HOPS][L1_ANT_NUM_CH] =
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{ 0, 1616, -7436, -8572}, { 0, 1589, -7597, -8590},
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{ 0, 1722, -7550, -8568}, { 0, 1741, -7691, -8449},
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{ 0, 1767, -7775, -8328},
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},
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// Antenna-2
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{
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{ 0, 2525, -7533, -6846}, { 0, 12726, -7818, -6860},
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{ 0, 2490, -7836, -6907}, { 0, 4479, -7716, -6837},
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{ 0, 6409, -7770, -6776}, { 0, 14616, -7977, -6816},
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{ 0, -22557, -8002, -6911}, { 0, -22587, -8121, -6918},
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{ 0, -1124, -8123, -7030}, { 0, -152, -8219, -7042},
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{ 0, 1823, -8209, -7130}, { 0, 1790, -8290, -7214},
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{ 0, 1669, -8362, -7283}, { 0, 1634, -8459, -7276},
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{ 0, 1615, -8315, -7415}, { 0, 1698, -8168, -7366},
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{ 0, 1535, -8285, -7520}, { 0, 1619, -8285, -7532},
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{ 0, 1609, -8201, -7693}, { 0, 1671, -8145, -7769},
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||||
{ 0, 1676, -8135, -7805}, { 0, 951, -10279, -8871},
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{ 0, 976, -10235, -8978}, { 0, 1118, -10127, -9019},
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||||
{ 0, 1175, -10003, -9007}, { 0, 1386, -9847, -9039},
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||||
{ 0, 1535, -9572, -9058}, { 0, 1729, -9493, -9006},
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||||
{ 0, -1158, -9312, -9003}, { 0, 23771, -9147, -8928},
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||||
{ 0, 20733, -9074, -8924}, { 0, 2455, -8841, -8886},
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||||
{ 0, 2622, -8718, -8735}, { 0, 2791, -8615, -8705},
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||||
{ 0, 2861, -8168, -8331}, { 0, 3076, -8091, -8218},
|
||||
{ 0, 3257, -8046, -8100}, { 0, 3331, -7923, -8073},
|
||||
{ 0, 3396, -7826, -7994}, { 0, 3478, -7842, -8016},
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||||
{ 0, 3518, -7846, -7765}, { 0, 3585, -7753, -7715},
|
||||
{ 0, 150, -8145, -8591}, { 0, 192, -8090, -8570},
|
||||
{ 0, 207, -8150, -8597}, { 0, 178, -8142, -8656},
|
||||
{ 0, 89, -8557, -8688}, { 0, 107, -8614, -8733},
|
||||
{ 0, 194, -8605, -8782}, { 0, 153, -8655, -8881},
|
||||
{ 0, 70, -8615, -8952}, { 0, 35, -8596, -9148},
|
||||
{ 0, 49, -8636, -9286}, { 0, 6, -8587, -9435},
|
||||
{ 0, -51, -8540, -9549}, { 0, -65, -8588, -9700},
|
||||
{ 0, -55, -8503, -9820}, { 0, -20, -8414, -9907},
|
||||
{ 0, -112, -8481, -10031}, { 0, -69, -8535, -10185},
|
||||
{ 0, 2, -8550, -10052}, { 0, -1, -8493, -10291},
|
||||
{ 0, -73, -8441, -10380}, { 0, 1958, -6930, -8295},
|
||||
{ 0, -1148, -6939, -8396}, { 0, 1915, -6784, -8370},
|
||||
{ 0, 1871, -6970, -8514}, { 0, 1821, -6974, -8387},
|
||||
{ 0, 1781, -6906, -8431}, { 0, 1736, -6897, -8462},
|
||||
{ 0, 1664, -7024, -8377}, { 0, 1629, -7127, -8436},
|
||||
{ 0, 1603, -7148, -8528}, { 0, 1577, -7198, -8500},
|
||||
{ 0, 1528, -7311, -8512}, { 0, 1577, -7390, -8570},
|
||||
{ 0, 1616, -7436, -8572}, { 0, 1589, -7597, -8590},
|
||||
{ 0, 1722, -7550, -8568}, { 0, 1741, -7691, -8449},
|
||||
{ 0, 1767, -7775, -8328},
|
||||
},
|
||||
// Antenna-3
|
||||
{
|
||||
{ 0, 2525, -7533, -6846}, { 0, 12726, -7818, -6860},
|
||||
{ 0, 2490, -7836, -6907}, { 0, 4479, -7716, -6837},
|
||||
{ 0, 6409, -7770, -6776}, { 0, 14616, -7977, -6816},
|
||||
{ 0, -22557, -8002, -6911}, { 0, -22587, -8121, -6918},
|
||||
{ 0, -1124, -8123, -7030}, { 0, -152, -8219, -7042},
|
||||
{ 0, 1823, -8209, -7130}, { 0, 1790, -8290, -7214},
|
||||
{ 0, 1669, -8362, -7283}, { 0, 1634, -8459, -7276},
|
||||
{ 0, 1615, -8315, -7415}, { 0, 1698, -8168, -7366},
|
||||
{ 0, 1535, -8285, -7520}, { 0, 1619, -8285, -7532},
|
||||
{ 0, 1609, -8201, -7693}, { 0, 1671, -8145, -7769},
|
||||
{ 0, 1676, -8135, -7805}, { 0, 951, -10279, -8871},
|
||||
{ 0, 976, -10235, -8978}, { 0, 1118, -10127, -9019},
|
||||
{ 0, 1175, -10003, -9007}, { 0, 1386, -9847, -9039},
|
||||
{ 0, 1535, -9572, -9058}, { 0, 1729, -9493, -9006},
|
||||
{ 0, -1158, -9312, -9003}, { 0, 23771, -9147, -8928},
|
||||
{ 0, 20733, -9074, -8924}, { 0, 2455, -8841, -8886},
|
||||
{ 0, 2622, -8718, -8735}, { 0, 2791, -8615, -8705},
|
||||
{ 0, 2861, -8168, -8331}, { 0, 3076, -8091, -8218},
|
||||
{ 0, 3257, -8046, -8100}, { 0, 3331, -7923, -8073},
|
||||
{ 0, 3396, -7826, -7994}, { 0, 3478, -7842, -8016},
|
||||
{ 0, 3518, -7846, -7765}, { 0, 3585, -7753, -7715},
|
||||
{ 0, 150, -8145, -8591}, { 0, 192, -8090, -8570},
|
||||
{ 0, 207, -8150, -8597}, { 0, 178, -8142, -8656},
|
||||
{ 0, 89, -8557, -8688}, { 0, 107, -8614, -8733},
|
||||
{ 0, 194, -8605, -8782}, { 0, 153, -8655, -8881},
|
||||
{ 0, 70, -8615, -8952}, { 0, 35, -8596, -9148},
|
||||
{ 0, 49, -8636, -9286}, { 0, 6, -8587, -9435},
|
||||
{ 0, -51, -8540, -9549}, { 0, -65, -8588, -9700},
|
||||
{ 0, -55, -8503, -9820}, { 0, -20, -8414, -9907},
|
||||
{ 0, -112, -8481, -10031}, { 0, -69, -8535, -10185},
|
||||
{ 0, 2, -8550, -10052}, { 0, -1, -8493, -10291},
|
||||
{ 0, -73, -8441, -10380}, { 0, 1958, -6930, -8295},
|
||||
{ 0, -1148, -6939, -8396}, { 0, 1915, -6784, -8370},
|
||||
{ 0, 1871, -6970, -8514}, { 0, 1821, -6974, -8387},
|
||||
{ 0, 1781, -6906, -8431}, { 0, 1736, -6897, -8462},
|
||||
{ 0, 1664, -7024, -8377}, { 0, 1629, -7127, -8436},
|
||||
{ 0, 1603, -7148, -8528}, { 0, 1577, -7198, -8500},
|
||||
{ 0, 1528, -7311, -8512}, { 0, 1577, -7390, -8570},
|
||||
{ 0, 1616, -7436, -8572}, { 0, 1589, -7597, -8590},
|
||||
{ 0, 1722, -7550, -8568}, { 0, 1741, -7691, -8449},
|
||||
{ 0, 1767, -7775, -8328},
|
||||
},
|
||||
};
|
||||
|
||||
const uint8_t hopPattern_2KBPS_20MS[L1_FRAME_2KBPS_20MS_HOPS] =
|
||||
const uint8_t hopPattern_ADV_24MS[L1_FRAME_ADV_24MS_HOPS] =
|
||||
{
|
||||
0
|
||||
0U, 35U, 66U, 47U, 40U, 16U, 30U, 65U,
|
||||
43U, 7U, 70U, 63U, 7U, 65U, 42U, 28U,
|
||||
};
|
||||
|
||||
const uint8_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS] =
|
||||
const uint8_t hopPattern_ACK_8MS[L1_FRAME_ACK_8MS_HOPS] =
|
||||
{
|
||||
0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
|
||||
8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
|
||||
16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,
|
||||
24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,
|
||||
32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U,
|
||||
40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,
|
||||
48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,
|
||||
56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U,
|
||||
64U, 65U, 66U, 67U, 68U, 69U, 70U, 71U,
|
||||
72U, 73U, 74U, 75U, 76U, 77U, 78U, 79U,
|
||||
80U
|
||||
0U, 5U, 49U, 25U,
|
||||
};
|
||||
|
||||
const uint8_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS] =
|
||||
const uint8_t hopPattern_128KBPS_4MS[L1_FRAME_128KBPS_4MS_HOPS] =
|
||||
{
|
||||
80U
|
||||
80U, 16U, 17U, 65U, 60U, 54U, 31U, 15U,
|
||||
6U, 19U, 79U, 52U, 29U, 42U, 23U, 59U,
|
||||
60U, 58U, 76U, 67U, 31U, 76U, 77U, 79U,
|
||||
79U, 14U, 61U, 5U, 71U, 50U, 32U, 77U,
|
||||
60U,
|
||||
};
|
||||
|
||||
const uint8_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS] =
|
||||
const uint8_t hopPattern_512KBPS_4MS[L1_FRAME_512KBPS_4MS_HOPS] =
|
||||
{
|
||||
80U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
|
||||
8U, 9U, 10U
|
||||
80U, 62U, 40U, 66U, 65U, 33U, 55U, 33U,
|
||||
57U, 11U, 37U, 45U, 5U, 69U, 77U, 54U,
|
||||
37U, 63U, 14U, 64U, 76U, 31U, 45U, 52U,
|
||||
40U, 20U, 20U, 32U, 0U, 60U, 23U, 19U,
|
||||
15U, 38U, 62U, 18U,
|
||||
};
|
||||
|
||||
const uint8_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS] =
|
||||
const uint8_t hopPattern_2MBPS_4MS[L1_FRAME_2MBPS_4MS_HOPS] =
|
||||
{
|
||||
0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
|
||||
8U,
|
||||
};
|
||||
|
||||
const uint8_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS] =
|
||||
{
|
||||
0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
|
||||
8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
|
||||
16U, 17U, 18U
|
||||
};
|
||||
|
||||
const uint8_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS] =
|
||||
{
|
||||
0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
|
||||
8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
|
||||
16U, 17U, 18U, 19U
|
||||
};
|
||||
|
||||
const uint8_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS] =
|
||||
{
|
||||
0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
|
||||
8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
|
||||
16U, 17U, 18U, 19U
|
||||
0U, 13U, 37U, 44U, 16U, 0U, 59U, 50U,
|
||||
69U, 70U, 58U, 14U, 9U, 72U, 27U, 25U,
|
||||
21U, 76U, 20U, 35U, 30U, 58U, 22U, 59U,
|
||||
48U, 33U, 8U, 7U, 41U, 12U, 44U, 79U,
|
||||
77U, 38U, 76U, 75U, 48U, 56U,
|
||||
};
|
||||
|
||||
/** @} PhysicalLayer_AntennaConfig_Constants*/
|
||||
@@ -201,51 +265,26 @@ void Phy_AntConfigInit(PHY_ANT_CONFIG *antConfig)
|
||||
{
|
||||
ASSERT(antConfig != NULL);
|
||||
|
||||
antConfig->ctrlWord = CTRL_WORD_DEFAULT;
|
||||
antConfig->antMode = ATN_MODE_DEFAULT;
|
||||
antConfig->rfMode = ATN_MODE_DEFAULT;
|
||||
|
||||
// FIXME: Dummy default value.
|
||||
// off axis angle setting
|
||||
antConfig->oaxis[0] = 0;
|
||||
antConfig->oaxis[1] = 0;
|
||||
// round axis angle setting
|
||||
antConfig->raxis[0] = 0;
|
||||
antConfig->raxis[1] = 0;
|
||||
// ***********************
|
||||
for (uint8_t ii = 0; ii < L1_ANT_NUM; ii ++)
|
||||
{
|
||||
for (uint8_t jj = 0; jj < L1_ANT_CH_NUM; jj ++)
|
||||
{
|
||||
antConfig->rfNormComp[ii][jj] = 0;
|
||||
antConfig->rfNormIdpAttn[ii][jj] = 0;
|
||||
}
|
||||
antConfig->rfNormComAttn[ii] = 0;
|
||||
antConfig->rfFreq[ii][0] = (uint8_t)(DEFAULT_CENTRTAL_FREQ);
|
||||
antConfig->rfFreq[ii][1] = (uint8_t)(DEFAULT_CENTRTAL_FREQ >> 8);
|
||||
}
|
||||
|
||||
antConfig->antFreq[0] = (uint8_t)(DEFAULT_CENTRTAL_FREQ);
|
||||
antConfig->antFreq[1] = (uint8_t)(DEFAULT_CENTRTAL_FREQ >> 8);
|
||||
for (uint8_t ii = 0; ii < L1_ANT_CH_NUM; ii ++)
|
||||
{
|
||||
antConfig->rfAntiAttn[ii] = 0;
|
||||
}
|
||||
|
||||
// FIXME: Dummy default value.
|
||||
// trSelect
|
||||
antConfig->trSlect = 0;
|
||||
// Antenna attenuation setting
|
||||
antConfig->antAtt = 0;
|
||||
// phase setting
|
||||
antConfig->phase = 0;
|
||||
// ***********************
|
||||
|
||||
antConfig->rxtxMode = RXTXMODE_DEFAULT;
|
||||
antConfig->calibrMode = CALIBRMODE_NORMAL;
|
||||
antConfig->antReserved = 0x00;
|
||||
|
||||
// FIXME: Dummy default value.
|
||||
// RF mode control
|
||||
antConfig->rfCtrl = RF_CTRL_DEFAULT;
|
||||
// RF frequency
|
||||
antConfig->rfFreq[0] = (uint8_t)(DEFAULT_CENTRTAL_FREQ);
|
||||
antConfig->rfFreq[1] = (uint8_t)(DEFAULT_CENTRTAL_FREQ >> 8);
|
||||
// RF MGC control
|
||||
antConfig->rfTxMgc = 0;
|
||||
// RF channel 1&2 calibration mgc
|
||||
antConfig->rf12CalMgc = 0;
|
||||
// RF channel 2&3 calibration mgc
|
||||
antConfig->rf34CalMgc = 0;
|
||||
// Receive channel 1-4 MGC
|
||||
antConfig->rcvMgc = 0;
|
||||
antConfig->rfReserved0 = 0x00;
|
||||
antConfig->rfReserved1 = 0x00;
|
||||
// ***********************
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
@@ -261,168 +300,113 @@ void Phy_AntConfigInit(PHY_ANT_CONFIG *antConfig)
|
||||
void Phy_AntConfigMode(PHY_INST *instPtr, PHY_ANT_MODE mode)
|
||||
{
|
||||
ASSERT(instPtr != NULL);
|
||||
uint8_t config = instPtr->antConfig.antMode & ANT_MODE_BEAM_MASK;
|
||||
uint8_t config = instPtr->antConfig.rfMode;
|
||||
size_t antIndexCurr = Phy_GetCurrentAntIndex(instPtr);
|
||||
switch (mode)
|
||||
{
|
||||
case PHY_ANT_MODE_STANDBY:
|
||||
config |= ANT_POWER_STANDBY;
|
||||
config &= ~ANT_MODE_TX_MASK;
|
||||
config |= ANT_MODE_TX_OFF;
|
||||
break;
|
||||
case PHY_ANT_MODE_POWER_LOW:
|
||||
config |= ANT_POWER_LOW;
|
||||
case PHY_ANT_MODE_NORMAL:
|
||||
config &= ~(ANT_MODE_TX_MASK | ANT_MODE_RX_MASK);
|
||||
config |= ANT_MODE_RX_NORMAL;
|
||||
|
||||
switch (antIndexCurr)
|
||||
{
|
||||
case 0:
|
||||
config |= ANT_MODE_TX1;
|
||||
break;
|
||||
case PHY_ANT_MODE_POWER_FULL:
|
||||
config |= ANT_POWER_FULL;
|
||||
case 1:
|
||||
config |= ANT_MODE_TX2;
|
||||
break;
|
||||
case 2:
|
||||
config |= ANT_MODE_TX3;
|
||||
break;
|
||||
default:
|
||||
config |= ANT_MODE_TX_OFF;
|
||||
DBG_WARNING("Unknown tx antenna number: %" PRIu8 ", tx is off.\n", antIndexCurr);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case PHY_ANT_MODE_ANTI_JAM:
|
||||
config &= ~(ANT_MODE_TX_MASK | ANT_MODE_RX_MASK);
|
||||
|
||||
switch (antIndexCurr)
|
||||
{
|
||||
case 0:
|
||||
config |= ANT_MODE_TX1;
|
||||
config |= ANT_MODE_RX_AJ1;
|
||||
break;
|
||||
case 1:
|
||||
config |= ANT_MODE_TX2;
|
||||
config |= ANT_MODE_RX_AJ2;
|
||||
break;
|
||||
case 2:
|
||||
config |= ANT_MODE_TX3;
|
||||
config |= ANT_MODE_RX_AJ3;
|
||||
break;
|
||||
default:
|
||||
config |= ANT_MODE_TX_OFF;
|
||||
config |= ANT_MODE_RX_NORMAL;
|
||||
DBG_WARNING("Unknown tx antenna number: %" PRIu8 ", remain normal mode.\n", antIndexCurr);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DBG_ERROR("Unknown antenna mode: %" PRIu8 ", remain previous mode.\n", mode);
|
||||
return;
|
||||
}
|
||||
instPtr->phyLog.antMode = mode;
|
||||
instPtr->antConfig.antMode = config;
|
||||
instPtr->phyLog.rfMode = mode;
|
||||
instPtr->antConfig.rfMode = config;
|
||||
// Sync logs to system monitor
|
||||
SysMonitor_UpdatePhysicalLayerLog(&(instPtr->phyLog));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @brief Update antenna beam table
|
||||
* @brief Update antenna index of the next slot.
|
||||
*
|
||||
* @param instPtr pointer to physical layer instance
|
||||
* @param table new beam table
|
||||
* @param offset table offset
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
******************************************************************************/
|
||||
void Phy_SetBeamTable(PHY_INST *instPtr, PHY_ANT_ANGLE *table, uint32_t offset)
|
||||
{
|
||||
ASSERT(instPtr != NULL);
|
||||
ASSERT(table != NULL);
|
||||
for (int i = 0; i < L1_NUM_ANT_NRRW_PATTERN; i++)
|
||||
{
|
||||
instPtr->antNrrwPattern[i] = table[(i + offset) % L1_NUM_ANT_NRRW_PATTERN];
|
||||
}
|
||||
memcpy((uint32_t *)instPtr->antInfoAddr, instPtr->antNrrwPattern,
|
||||
L1_NUM_ANT_NRRW_PATTERN * sizeof(PHY_ANT_ANGLE));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @brief Update antenna point direction using predefined beam table
|
||||
*
|
||||
* @param instPtr pointer to physical layer instance
|
||||
* @param beamNo new beam index
|
||||
* @param AntIndex antenna index
|
||||
*
|
||||
* @return SUCCESS.
|
||||
* FAILURE beamNo exceeds the table size
|
||||
* EPARAM - antenna index exceeds predefined range
|
||||
*
|
||||
******************************************************************************/
|
||||
int32_t Phy_SetBeamNo(PHY_INST *instPtr, size_t beamNo, PHY_ANT_BEAM_WIDTH beamWidth)
|
||||
int32_t Phy_SetAntIndex(PHY_INST *instPtr, size_t antIndex)
|
||||
{
|
||||
ASSERT(instPtr != NULL);
|
||||
|
||||
if (beamWidth == PHY_ANT_BEAM_16)
|
||||
if (antIndex < 0 || antIndex >= L1_ANT_NUM)
|
||||
{
|
||||
if (beamNo >= L1_NUM_ANT_NRRW_PATTERN)
|
||||
{
|
||||
return FAILURE;
|
||||
}
|
||||
else
|
||||
{
|
||||
instPtr->beamNo.next = beamNo;
|
||||
instPtr->antConfig.oaxis[0] = (uint8_t)(instPtr->antNrrwPattern[beamNo].oaxis >> 8);
|
||||
instPtr->antConfig.oaxis[1] = (uint8_t)(instPtr->antNrrwPattern[beamNo].oaxis);
|
||||
instPtr->antConfig.raxis[0] = (uint8_t)(instPtr->antNrrwPattern[beamNo].raxis >> 8);
|
||||
instPtr->antConfig.raxis[1] = (uint8_t)(instPtr->antNrrwPattern[beamNo].raxis);
|
||||
return SUCCESS;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// Beam number assign not support.
|
||||
// Assign default angle (0,0)
|
||||
instPtr->beamNo.next = 0;
|
||||
instPtr->antConfig.oaxis[0] = 0;
|
||||
instPtr->antConfig.oaxis[1] = 0;
|
||||
instPtr->antConfig.raxis[0] = 0;
|
||||
instPtr->antConfig.raxis[1] = 0;
|
||||
DBG_WARNING("Using default beam number...\n");
|
||||
return SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @brief Update antenna beam width setting
|
||||
*
|
||||
* @param instPtr pointer to physical layer instance
|
||||
* @param beamWidth new beam width
|
||||
*
|
||||
* @return SUCCESS.
|
||||
* EPARAM
|
||||
*
|
||||
******************************************************************************/
|
||||
int32_t Phy_SetBeamWidth(PHY_INST *instPtr, PHY_ANT_BEAM_WIDTH beamWidth)
|
||||
{
|
||||
ASSERT(instPtr != NULL);
|
||||
uint8_t beamConfig = instPtr->antConfig.antMode & (~ANT_MODE_BEAM_MASK);
|
||||
switch (beamWidth)
|
||||
{
|
||||
case PHY_ANT_BEAM_120:
|
||||
beamConfig |= ANT_BEAM_WIDE;
|
||||
break;
|
||||
case PHY_ANT_BEAM_60:
|
||||
beamConfig |= ANT_BEAM_SUBNARROR_1;
|
||||
break;
|
||||
case PHY_ANT_BEAM_25:
|
||||
beamConfig |= ANT_BEAM_SUBNARROR_0;
|
||||
break;
|
||||
case PHY_ANT_BEAM_16:
|
||||
beamConfig |= ANT_BEAM_NARROR;
|
||||
break;
|
||||
default:
|
||||
DBG_ERROR("Beam width code: 0x%08X is illegal.\n\r", beamWidth);
|
||||
DBG_ERROR("Antenna index out of range: %" PRIu8 ". \n", antIndex);
|
||||
return EPARAM;
|
||||
}
|
||||
instPtr->antConfig.antMode = beamConfig;
|
||||
instPtr->beamWd.next = beamWidth;
|
||||
DBG_INFO("Set new antenna index: %" PRId8 "\n", antIndex);
|
||||
instPtr->antIndex.next = antIndex;
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @brief Set antenna to a specific direction
|
||||
*
|
||||
* @param instPtr pointer to physical layer instance
|
||||
* @param offAx elevation angle
|
||||
* @param rndAx azimuth angle
|
||||
*
|
||||
* @return SUCCESS.
|
||||
* EPARAM - the direction is exceeds predefined range
|
||||
*
|
||||
******************************************************************************/
|
||||
int32_t Phy_SetBeamAngle(PHY_INST *instPtr, double offAx, double rndAx)
|
||||
* @brief Get next antenna index.
|
||||
*/
|
||||
inline size_t Phy_GetCurrentAntIndex(PHY_INST *instPtr)
|
||||
{
|
||||
ASSERT(instPtr != NULL);
|
||||
uint16_t offAxDeg = 0;
|
||||
uint16_t rndAxDeg = 0;
|
||||
offAxDeg = (offAx >= 0) ? (((int32_t)(offAx * 180.0 / ANT_PI)) % 360) : (((int32_t)(offAx * 180.0 / ANT_PI)) % 360 + 360);
|
||||
rndAxDeg = (rndAx >= 0) ? (((int32_t)(rndAx * 180.0 / ANT_PI)) % 360) : (((int32_t)(rndAx * 180.0 / ANT_PI)) % 360 + 360);
|
||||
if (offAxDeg > 60)
|
||||
{
|
||||
DBG_ERROR("Angle out of range, off axis angle: %" PRIu16 " (should be 0~60), round axis angle: %" PRIu16 " (should be 0~360).\n",
|
||||
offAxDeg, rndAxDeg);
|
||||
return EPARAM;
|
||||
}
|
||||
offAxDeg = offAxDeg * 10;
|
||||
rndAxDeg = rndAxDeg * 10;
|
||||
instPtr->antConfig.oaxis[0] = (uint8_t)(offAxDeg >> 8);
|
||||
instPtr->antConfig.oaxis[1] = (uint8_t)offAxDeg;
|
||||
instPtr->antConfig.raxis[0] = (uint8_t)(rndAxDeg >> 8);
|
||||
instPtr->antConfig.raxis[1] = (uint8_t)rndAxDeg;
|
||||
return SUCCESS;
|
||||
return instPtr->antIndex.curr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get current antenna index.
|
||||
*/
|
||||
inline size_t Phy_GetNextAntIndex(PHY_INST *instPtr)
|
||||
{
|
||||
ASSERT(instPtr != NULL);
|
||||
return instPtr->antIndex.next;
|
||||
}
|
||||
|
||||
|
||||
/** @} PhysicalLayer_AntennaControl*/
|
||||
|
||||
/** @} PhysicalLayer*/
|
||||
@@ -36,52 +36,40 @@
|
||||
#define PHY_TIME_WORD_H_MAX UINT32_MAX
|
||||
#define PHY_TIME_WORD_L_MAX 0x0007A120 // 5ms/10ns
|
||||
|
||||
#define L1_FRAME_LEN_MAX (8192 / 8) // byte
|
||||
#define L1_FRAME_2KBPS_20MS_LEN 0 // byte
|
||||
#define L1_FRAME_2KBPS_100MS_LEN (312 / 8) // byte
|
||||
#define L1_FRAME_10KBPS_10MS_LEN 0 // byte
|
||||
#define L1_FRAME_10KBPS_20MS_LEN (232 / 8) // byte
|
||||
#define L1_FRAME_40KBPS_20MS_LEN (2152 / 8) // byte
|
||||
#define L1_FRAME_40KBPS_10MS_LEN (712 / 8) // byte
|
||||
#define L1_FRAME_200KBPS_5MS_LEN (2040 / 8) // byte
|
||||
#define L1_FRAME_1M2BPS_5MS_LEN (8176 / 8) // byte
|
||||
#define L1_FRAME_LEN_MAX (16384 / 8) // byte
|
||||
#define L1_FRAME_ADV_24MS_LEN (520 / 8) // byte
|
||||
#define L1_FRAME_ACK_8MS_LEN (520 / 8) // byte
|
||||
#define L1_FRAME_128KBPS_4MS_LEN (784 / 8) // byte
|
||||
#define L1_FRAME_512KBPS_4MS_LEN (2584 / 8) // byte
|
||||
#define L1_FRAME_2MBPS_4MS_LEN (10224 / 8) // byte
|
||||
|
||||
#define L1_FRAME_2KBPS_20MS_COMP 1841158 // *10ns(Timer_L)
|
||||
#define L1_FRAME_2KBPS_100MS_COMP 1841158 // *10ns(Timer_L)
|
||||
#define L1_FRAME_10KBPS_10MS_COMP 850950 // *10ns(Timer_L)
|
||||
#define L1_FRAME_10KBPS_20MS_COMP 850950 // *10ns(Timer_L)
|
||||
#define L1_FRAME_40KBPS_20MS_COMP 111485 // *10ns(Timer_L)
|
||||
#define L1_FRAME_40KBPS_10MS_COMP 111485 // *10ns(Timer_L)
|
||||
#define L1_FRAME_200KBPS_5MS_COMP 22493 // *10ns(Timer_L)
|
||||
#define L1_FRAME_1M2BPS_5MS_COMP 22493 // *10ns(Timer_L)
|
||||
#define L1_FRAME_ADV_24MS_COMP 1841158 // FIXME: need update, *10ns(Timer_L)
|
||||
#define L1_FRAME_ACK_8MS_COMP 1841158 // FIXME: need update, *10ns(Timer_L)
|
||||
#define L1_FRAME_128KBPS_4MS_COMP 850950 // FIXME: need update, *10ns(Timer_L)
|
||||
#define L1_FRAME_512KBPS_4MS_COMP 850950 // FIXME: need update, *10ns(Timer_L)
|
||||
#define L1_FRAME_2MBPS_4MS_COMP 111485 // FIXME: need update, *10ns(Timer_L)
|
||||
|
||||
#define L1_ANTCONFIG_MAX_LEN 8192
|
||||
#define L1_TXRXDATA_MAX_LEN 2048
|
||||
#define L1_TXRXDATA_MAX_LEN 16384
|
||||
|
||||
#define ANT_COINFO_LEN 32 // bytes
|
||||
#define ANT_COINFO_LEN 32 // bytes, antenna configuration length of each hop
|
||||
|
||||
#define ATTN_DEFAULT 0
|
||||
#define ATTN_2KBPS_100MS ATTN_DEFAULT
|
||||
#define ATTN_2KBPS_20MS ATTN_DEFAULT
|
||||
#define ATTN_10KBPS_10MS 12
|
||||
#define ATTN_10KBPS_20MS 12
|
||||
#define ATTN_40KBPS_10MS 0
|
||||
#define ATTN_40KBPS_20MS 0
|
||||
#define ATTN_200KBPS_5MS ATTN_DEFAULT
|
||||
#define ATTN_1M2BPS_5MS ATTN_DEFAULT
|
||||
#define ATTN_ADV_24MS ATTN_DEFAULT
|
||||
#define ATTN_ACK_8MS ATTN_DEFAULT
|
||||
#define ATTN_128KBPS_4MS ATTN_DEFAULT
|
||||
#define ATTN_512KBPS_4MS ATTN_DEFAULT
|
||||
#define ATTN_2MBPS_4MS ATTN_DEFAULT
|
||||
/** @} PhysicalLayer_Private_Constants*/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
extern const uint16_t freqTable[L1_FRAME_MAX_HOPS];
|
||||
extern const int16_t antCalTable[L1_FRAME_MAX_HOPS][L1_ANT_NUM_CH];
|
||||
extern const uint8_t hopPattern_2KBPS_20MS[L1_FRAME_2KBPS_20MS_HOPS];
|
||||
extern const uint8_t hopPattern_2KBPS_100MS[L1_FRAME_2KBPS_100MS_HOPS];
|
||||
extern const uint8_t hopPattern_10KBPS_10MS[L1_FRAME_10KBPS_10MS_HOPS];
|
||||
extern const uint8_t hopPattern_10KBPS_20MS[L1_FRAME_10KBPS_20MS_HOPS];
|
||||
extern const uint8_t hopPattern_40KBPS_10MS[L1_FRAME_40KBPS_10MS_HOPS];
|
||||
extern const uint8_t hopPattern_40KBPS_20MS[L1_FRAME_40KBPS_20MS_HOPS];
|
||||
extern const uint8_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS];
|
||||
extern const uint8_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS];
|
||||
extern const int16_t antCalTable[L1_FRAME_MAX_HOPS][L1_ANT_CH_NUM];
|
||||
extern const uint8_t hopPattern_ADV_24MS[L1_FRAME_ADV_24MS_HOPS];
|
||||
extern const uint8_t hopPattern_ACK_8MS[L1_FRAME_ACK_8MS_HOPS];
|
||||
extern const uint8_t hopPattern_128KBPS_4MS[L1_FRAME_128KBPS_4MS_HOPS];
|
||||
extern const uint8_t hopPattern_512KBPS_4MS[L1_FRAME_512KBPS_4MS_HOPS];
|
||||
extern const uint8_t hopPattern_2MBPS_4MS[L1_FRAME_2MBPS_4MS_HOPS];
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
/************************** Function Prototypes ******************************/
|
||||
@@ -227,22 +215,16 @@ uint32_t Phy_GetFrameLen(L1_FRAME_TYPE frameType)
|
||||
{
|
||||
switch (frameType)
|
||||
{
|
||||
case L1_2KBPS_20MS_FRAME:
|
||||
return L1_FRAME_2KBPS_20MS_LEN;
|
||||
case L1_2KBPS_100MS_FRAME:
|
||||
return L1_FRAME_2KBPS_100MS_LEN;
|
||||
case L1_10KBPS_10MS_FRAME:
|
||||
return L1_FRAME_10KBPS_10MS_LEN;
|
||||
case L1_10KBPS_20MS_FRAME:
|
||||
return L1_FRAME_10KBPS_20MS_LEN;
|
||||
case L1_40KBPS_20MS_FRAME:
|
||||
return L1_FRAME_40KBPS_20MS_LEN;
|
||||
case L1_40KBPS_10MS_FRAME:
|
||||
return L1_FRAME_40KBPS_10MS_LEN;
|
||||
case L1_200KBPS_5MS_FRAME:
|
||||
return L1_FRAME_200KBPS_5MS_LEN;
|
||||
case L1_1M2BPS_5MS_FRAME:
|
||||
return L1_FRAME_1M2BPS_5MS_LEN;
|
||||
case L1_FRAME_ADV_24MS:
|
||||
return L1_FRAME_ADV_24MS_LEN;
|
||||
case L1_FRAME_ACK_8MS:
|
||||
return L1_FRAME_ACK_8MS_LEN;
|
||||
case L1_FRAME_128KBPS_4MS:
|
||||
return L1_FRAME_128KBPS_4MS_LEN;
|
||||
case L1_FRAME_512KBPS_4MS:
|
||||
return L1_FRAME_512KBPS_4MS_LEN;
|
||||
case L1_FRAME_2MBPS_4MS:
|
||||
return L1_FRAME_2MBPS_4MS_LEN;
|
||||
default:
|
||||
return L1_FRAME_NONE_LEN;
|
||||
}
|
||||
@@ -263,24 +245,18 @@ uint32_t Phy_GetHopLength(L1_FRAME_TYPE frameType)
|
||||
{
|
||||
switch (frameType)
|
||||
{
|
||||
case L1_2KBPS_20MS_FRAME:
|
||||
return L1_FRAME_2KBPS_20MS_HOPS;
|
||||
case L1_2KBPS_100MS_FRAME:
|
||||
return L1_FRAME_2KBPS_100MS_HOPS;
|
||||
case L1_10KBPS_10MS_FRAME:
|
||||
return L1_FRAME_10KBPS_10MS_HOPS;
|
||||
case L1_10KBPS_20MS_FRAME:
|
||||
return L1_FRAME_10KBPS_20MS_HOPS;
|
||||
case L1_40KBPS_20MS_FRAME:
|
||||
return L1_FRAME_40KBPS_20MS_HOPS;
|
||||
case L1_40KBPS_10MS_FRAME:
|
||||
return L1_FRAME_40KBPS_10MS_HOPS;
|
||||
case L1_200KBPS_5MS_FRAME:
|
||||
return L1_FRAME_200KBPS_5MS_HOPS;
|
||||
case L1_1M2BPS_5MS_FRAME:
|
||||
return L1_FRAME_1M2BPS_5MS_HOPS;
|
||||
case L1_FRAME_ADV_24MS:
|
||||
return L1_FRAME_ADV_24MS_HOPS;
|
||||
case L1_FRAME_ACK_8MS:
|
||||
return L1_FRAME_ACK_8MS_HOPS;
|
||||
case L1_FRAME_128KBPS_4MS:
|
||||
return L1_FRAME_128KBPS_4MS_HOPS;
|
||||
case L1_FRAME_512KBPS_4MS:
|
||||
return L1_FRAME_512KBPS_4MS_HOPS;
|
||||
case L1_FRAME_2MBPS_4MS:
|
||||
return L1_FRAME_2MBPS_4MS_HOPS;
|
||||
default:
|
||||
return L1_FRAME_NONE_LEN;
|
||||
return L1_FRAME_NONE_HOPS;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -298,24 +274,18 @@ uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType)
|
||||
{
|
||||
switch (frameType)
|
||||
{
|
||||
case L1_2KBPS_20MS_FRAME:
|
||||
return L1_FRAME_2KBPS_20MS_COMP;
|
||||
case L1_2KBPS_100MS_FRAME:
|
||||
return L1_FRAME_2KBPS_100MS_COMP;
|
||||
case L1_10KBPS_10MS_FRAME:
|
||||
return L1_FRAME_10KBPS_10MS_COMP;
|
||||
case L1_10KBPS_20MS_FRAME:
|
||||
return L1_FRAME_10KBPS_20MS_COMP;
|
||||
case L1_40KBPS_20MS_FRAME:
|
||||
return L1_FRAME_40KBPS_20MS_COMP;
|
||||
case L1_40KBPS_10MS_FRAME:
|
||||
return L1_FRAME_40KBPS_10MS_COMP;
|
||||
case L1_200KBPS_5MS_FRAME:
|
||||
return L1_FRAME_200KBPS_5MS_COMP;
|
||||
case L1_1M2BPS_5MS_FRAME:
|
||||
return L1_FRAME_1M2BPS_5MS_COMP;
|
||||
case L1_FRAME_ADV_24MS:
|
||||
return L1_FRAME_ADV_24MS_COMP;
|
||||
case L1_FRAME_ACK_8MS:
|
||||
return L1_FRAME_ACK_8MS_COMP;
|
||||
case L1_FRAME_128KBPS_4MS:
|
||||
return L1_FRAME_128KBPS_4MS_COMP;
|
||||
case L1_FRAME_512KBPS_4MS:
|
||||
return L1_FRAME_512KBPS_4MS_COMP;
|
||||
case L1_FRAME_2MBPS_4MS:
|
||||
return L1_FRAME_2MBPS_4MS_COMP;
|
||||
default:
|
||||
return L1_FRAME_NONE_LEN;
|
||||
return L1_FRAME_NONE_COMP;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -325,7 +295,7 @@ uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType)
|
||||
*
|
||||
* @param instPtr A pointer to physical layer control instance.
|
||||
*
|
||||
* @return Layer2 frame type. Refer "frame_def.h"
|
||||
* @return Layer1 frame type. Refer "frame_def.h"
|
||||
*
|
||||
******************************************************************************/
|
||||
inline L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr)
|
||||
@@ -333,29 +303,23 @@ inline L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr)
|
||||
ASSERT(instPtr != NULL);
|
||||
if (Phy_IsFrameReceived(instPtr) == false)
|
||||
{
|
||||
return L1_NONE_FRAME;
|
||||
return L1_FRAME_NONE;
|
||||
}
|
||||
uint32_t frame_type = (PhyRead(instPtr, COASE_FREQEST) & COASE_TYPE_MASK);
|
||||
switch (frame_type)
|
||||
{
|
||||
case COASE_TYPE_2KBPS_20MS:
|
||||
return L1_2KBPS_20MS_FRAME;
|
||||
case COASE_TYPE_2KBPS_100MS:
|
||||
return L1_2KBPS_100MS_FRAME;
|
||||
case COASE_TYPE_10KBPS_10MS:
|
||||
return L1_10KBPS_10MS_FRAME;
|
||||
case COASE_TYPE_10KBPS_20MS:
|
||||
return L1_10KBPS_20MS_FRAME;
|
||||
case COASE_TYPE_40KBPS_20MS:
|
||||
return L1_40KBPS_20MS_FRAME;
|
||||
case COASE_TYPE_40KBPS_10MS:
|
||||
return L1_40KBPS_10MS_FRAME;
|
||||
case COASE_TYPE_200KBPS_5MS:
|
||||
return L1_200KBPS_5MS_FRAME;
|
||||
case COASE_TYPE_1M2BPS_5MS:
|
||||
return L1_1M2BPS_5MS_FRAME;
|
||||
case COASE_TYPE_ADV_24MS:
|
||||
return L1_FRAME_ADV_24MS;
|
||||
case COASE_TYPE_ACK_8MS:
|
||||
return L1_FRAME_ACK_8MS;
|
||||
case COASE_TYPE_128KBPS_4MS:
|
||||
return L1_FRAME_128KBPS_4MS;
|
||||
case COASE_TYPE_512KBPS_4MS:
|
||||
return L1_FRAME_512KBPS_4MS;
|
||||
case COASE_TYPE_2MBPS_4MS:
|
||||
return L1_FRAME_2MBPS_4MS;
|
||||
default:
|
||||
return L1_NONE_FRAME;
|
||||
return L1_FRAME_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -365,7 +329,7 @@ inline L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr)
|
||||
*
|
||||
* @param instPtr A pointer to physical layer control instance.
|
||||
*
|
||||
* @return Layer2 frame type. Refer "frame_def.h"
|
||||
* @return Layer1 frame type. Refer "frame_def.h"
|
||||
*
|
||||
******************************************************************************/
|
||||
inline L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST *instPtr)
|
||||
@@ -373,7 +337,7 @@ inline L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST *instPtr)
|
||||
ASSERT(instPtr != NULL);
|
||||
if (instPtr->tor.last != PHY_TOR_TX)
|
||||
{
|
||||
return L1_NONE_FRAME;
|
||||
return L1_FRAME_NONE;
|
||||
}
|
||||
return instPtr->frameType.last;
|
||||
}
|
||||
@@ -425,8 +389,7 @@ int32_t Phy_Init(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
|
||||
|
||||
memset(&((*instPtr))->tor, PHY_TOR_SUSPEND, sizeof(PHY_RCD));
|
||||
memset(&((*instPtr)->frameType), L1_NONE_FRAME, sizeof(PHY_RCD));
|
||||
memset(&((*instPtr)->beamNo), (int32_t)L1_INIT_BEAM_NO, sizeof(PHY_RCD));
|
||||
memset(&((*instPtr)->beamWd), (int32_t)L1_INIT_ANT_WD, sizeof(PHY_RCD));
|
||||
memset(&((*instPtr)->antIndex), (int32_t)L1_INIT_ANT_IDX, sizeof(PHY_RCD));
|
||||
memset(&((*instPtr)->hwSate), 0x00, sizeof(HWSTATE));
|
||||
memset(&((*instPtr)->phyLog), 0x00, sizeof(PHYLOG));
|
||||
|
||||
@@ -509,44 +472,6 @@ int32_t Phy_Init(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
|
||||
(*instPtr)->recvDataAddr = rxDataBram.Config.MemBaseAddress;
|
||||
(*instPtr)->sendDataAddr = txDataBram.Config.MemBaseAddress;
|
||||
|
||||
// Setup antenna presets
|
||||
XBram antInfoBram;
|
||||
if (phyConfig->antInfoBramId != -1)
|
||||
{
|
||||
bramConfigPtr = XBram_LookupConfig(phyConfig->antInfoBramId);
|
||||
if (bramConfigPtr == NULL)
|
||||
{
|
||||
Phy_Destroy(*instPtr);
|
||||
return EDCONF;
|
||||
}
|
||||
Status = XBram_CfgInitialize(&antInfoBram, bramConfigPtr,
|
||||
bramConfigPtr->CtrlBaseAddress);
|
||||
if (Status != SUCCESS)
|
||||
{
|
||||
Phy_Destroy(*instPtr);
|
||||
return Status;
|
||||
}
|
||||
/*
|
||||
* Execute the BRAM driver self test.
|
||||
*/
|
||||
Status = XBram_SelfTest(&antInfoBram, 0);
|
||||
if (Status != SUCCESS)
|
||||
{
|
||||
Phy_Destroy(*instPtr);
|
||||
return Status;
|
||||
}
|
||||
(*instPtr)->antInfoAddr = antInfoBram.Config.MemBaseAddress;
|
||||
uint32_t phyMainCtrl = PhyRead(*instPtr, PHY_MAIN_CTRL);
|
||||
phyMainCtrl &= ~PHY_MAIN_CTRL_NSCAN_MASK;
|
||||
phyMainCtrl |= PHY_MAIN_CTRL_NSCAN_MASK &
|
||||
(L1_NUM_ANT_NRRW_PATTERN << PHY_MAIN_CTRL_NSCAN_SHIFT);
|
||||
PhyWrite(*instPtr, PHY_MAIN_CTRL, phyMainCtrl);
|
||||
}
|
||||
else
|
||||
{
|
||||
(*instPtr)->antInfoAddr = (uintptr_t)NULL;
|
||||
}
|
||||
|
||||
/* Initialize the XAdc driver. */
|
||||
XAdcPs_Config *xadcConfigPtr;
|
||||
|
||||
@@ -597,7 +522,7 @@ int32_t Phy_Init(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @brief Destroy physical layer inctance, free allocated memory.
|
||||
* @brief Destroy physical layer instance, free allocated memory.
|
||||
*
|
||||
* @param instPtr a pointer to physical instance
|
||||
*
|
||||
@@ -685,11 +610,8 @@ int32_t Phy_SetMode(PHY_INST *instPtr, PHY_MODE modeCod)
|
||||
case PHY_MODE_LISTEN:
|
||||
phyMainCtrl |= PHY_MAIN_CTRL_MODE_LISTEN;
|
||||
break;
|
||||
case PHY_MODE_SCHEDULE:
|
||||
phyMainCtrl |= PHY_MAIN_CTRL_MODE_SCHEDULE;
|
||||
break;
|
||||
case PHY_MODE_PULL:
|
||||
phyMainCtrl |= PHY_MAIN_CTRL_MODE_PULL;
|
||||
case PHY_MODE_POLL:
|
||||
phyMainCtrl |= PHY_MAIN_CTRL_MODE_POLL;
|
||||
break;
|
||||
default:
|
||||
return FAILURE;
|
||||
@@ -773,53 +695,30 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
|
||||
}
|
||||
switch (frameType)
|
||||
{
|
||||
case L1_2KBPS_20MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_2KBPS_20MS;
|
||||
hopNum = L1_FRAME_2KBPS_20MS_HOPS;
|
||||
hopPattern = hopPattern_2KBPS_20MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_2KBPS_20MS;
|
||||
case L1_FRAME_ADV_24MS:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_ADV_24MS;
|
||||
hopNum = L1_FRAME_ADV_24MS_HOPS;
|
||||
hopPattern = hopPattern_ADV_24MS;
|
||||
break;
|
||||
case L1_2KBPS_100MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_2KBPS_100MS;
|
||||
hopNum = L1_FRAME_2KBPS_100MS_HOPS;
|
||||
hopPattern = hopPattern_2KBPS_100MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_2KBPS_100MS;
|
||||
case L1_FRAME_ACK_8MS:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_ACK_8MS;
|
||||
hopNum = L1_FRAME_ACK_8MS_HOPS;
|
||||
hopPattern = hopPattern_ACK_8MS;
|
||||
break;
|
||||
case L1_10KBPS_10MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_10KBPS_10MS;
|
||||
hopNum = L1_FRAME_10KBPS_20MS_HOPS;
|
||||
hopPattern = hopPattern_10KBPS_20MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_10KBPS_10MS;
|
||||
case L1_FRAME_128KBPS_4MS:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_128KBPS_4MS;
|
||||
hopNum = L1_FRAME_128KBPS_4MS_HOPS;
|
||||
hopPattern = hopPattern_128KBPS_4MS;
|
||||
break;
|
||||
case L1_10KBPS_20MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_10KBPS_20MS;
|
||||
hopNum = L1_FRAME_10KBPS_20MS_HOPS;
|
||||
hopPattern = hopPattern_10KBPS_20MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_10KBPS_20MS;
|
||||
case L1_FRAME_512KBPS_4MS:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_512KBPS_4MS;
|
||||
hopNum = L1_FRAME_512KBPS_4MS_HOPS;
|
||||
hopPattern = hopPattern_512KBPS_4MS;
|
||||
break;
|
||||
case L1_40KBPS_20MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_40KBPS_20MS;
|
||||
hopNum = L1_FRAME_40KBPS_20MS_HOPS;
|
||||
hopPattern = hopPattern_40KBPS_20MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_40KBPS_20MS;
|
||||
break;
|
||||
case L1_40KBPS_10MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_40KBPS_10MS;
|
||||
hopNum = L1_FRAME_40KBPS_10MS_HOPS;
|
||||
hopPattern = hopPattern_40KBPS_10MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_40KBPS_10MS;
|
||||
break;
|
||||
case L1_200KBPS_5MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_200KBPS_5MS;
|
||||
hopNum = L1_FRAME_200KBPS_5MS_HOPS;
|
||||
hopPattern = hopPattern_200KBPS_5MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_200KBPS_5MS;
|
||||
break;
|
||||
case L1_1M2BPS_5MS_FRAME:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_1M2BPS_5MS;
|
||||
hopNum = L1_FRAME_1M2BPS_5MS_HOPS;
|
||||
hopPattern = hopPattern_1M2BPS_5MS;
|
||||
instPtr->antConfig.rfTxMgc = ATTN_1M2BPS_5MS;
|
||||
case L1_FRAME_2MBPS_4MS:
|
||||
phyModeCtrl |= PHY_MODE_CTRL_FRAME_2MBPS_4MS;
|
||||
hopNum = L1_FRAME_2MBPS_4MS_HOPS;
|
||||
hopPattern = hopPattern_2MBPS_4MS;
|
||||
break;
|
||||
default:
|
||||
return EPARAM;
|
||||
@@ -831,36 +730,24 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
|
||||
|
||||
// TODO: Set antenna stand by, when suspend.
|
||||
const uint8_t *dataSrcPtr = (uint8_t *)(&(instPtr->antConfig));
|
||||
const size_t antIndexNext = Phy_GetNextAntIndex(instPtr);
|
||||
size_t hopIdx;
|
||||
uint16_t hopFreq;
|
||||
int16_t hopCal;
|
||||
uint8_t hopCal;
|
||||
for (int32_t i = 0; i < hopNum; i++)
|
||||
{
|
||||
hopIdx = hopPattern[i];
|
||||
|
||||
// Frequency setting
|
||||
hopFreq = freqTable[hopIdx];
|
||||
instPtr->antConfig.antFreq[0] = (uint8_t)(hopFreq >> 8);
|
||||
instPtr->antConfig.antFreq[1] = (uint8_t)hopFreq;
|
||||
instPtr->antConfig.rfFreq[0] = (uint8_t)(hopFreq >> 8);
|
||||
instPtr->antConfig.rfFreq[1] = (uint8_t)hopFreq;
|
||||
instPtr->antConfig.rfFreq[antIndexNext][0] = (uint8_t)(hopFreq >> 8);
|
||||
instPtr->antConfig.rfFreq[antIndexNext][1] = (uint8_t)hopFreq;
|
||||
// Calibration setting
|
||||
// -- CH0
|
||||
hopCal = antCalTable[hopIdx][0];
|
||||
instPtr->antConfig.ch0Cal[0] = (uint8_t)(hopCal >> 8);
|
||||
instPtr->antConfig.ch0Cal[1] = (uint8_t)hopCal;
|
||||
// -- CH1
|
||||
hopCal = antCalTable[hopIdx][1];
|
||||
instPtr->antConfig.ch1Cal[0] = (uint8_t)(hopCal >> 8);
|
||||
instPtr->antConfig.ch1Cal[1] = (uint8_t)hopCal;
|
||||
// -- CH2
|
||||
hopCal = antCalTable[hopIdx][2];
|
||||
instPtr->antConfig.ch2Cal[0] = (uint8_t)(hopCal >> 8);
|
||||
instPtr->antConfig.ch2Cal[1] = (uint8_t)hopCal;
|
||||
// -- CH3
|
||||
hopCal = antCalTable[hopIdx][3];
|
||||
instPtr->antConfig.ch3Cal[0] = (uint8_t)(hopCal >> 8);
|
||||
instPtr->antConfig.ch3Cal[1] = (uint8_t)hopCal;
|
||||
for (uint8_t ii = 0; ii < L1_ANT_CH_NUM; ii ++)
|
||||
{
|
||||
hopCal = antCalTable[antIndexNext][hopIdx][ii];
|
||||
instPtr->antConfig.rfNormComp[antIndexNext][ii] = hopCal;
|
||||
}
|
||||
|
||||
memcpy((uint8_t *)(antConfigAddr + i * ANT_COINFO_LEN),
|
||||
dataSrcPtr, sizeof(PHY_ANT_CONFIG));
|
||||
@@ -889,9 +776,7 @@ int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode,
|
||||
|
||||
Phy_RcdShift(&(instPtr->tor), txrxMode);
|
||||
Phy_RcdShift(&(instPtr->frameType), frameType);
|
||||
// TODO:
|
||||
Phy_RcdShift(&(instPtr->beamNo), L1_INIT_BEAM_NO);
|
||||
Phy_RcdShift(&(instPtr->beamWd), L1_INIT_ANT_WD);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
@@ -1121,45 +1006,42 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
|
||||
#else
|
||||
instPtr->hwSate.isSpOk = true;
|
||||
#endif
|
||||
/*** Voltage and Status ***/
|
||||
rawData = PhyRead(instPtr, ANT_STATUS);
|
||||
// -- Update Antenna Voltage Status: 1 - normal, 0 - error
|
||||
// [0] - ANT voltage status
|
||||
// [2] - RF voltage status
|
||||
// [4] - NIL voltage status
|
||||
// [6] - Antenna status
|
||||
instPtr->hwSate.antVolt = ((rawData & ANT_STATUS_ANT_VOLT_MASK) == ANT_STATUS_ANT_VOLT_OK) ? VOLT_ANT_PROC_OK : 0x00;
|
||||
instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_RF_VOLT_MASK) == ANT_STATUS_RF_VOLT_OK) ? VOLT_ANT_RF_OK : 0x00;
|
||||
instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_NIL_VOLT_MASK) == ANT_STATUS_NIL_VOLT_OK) ? VOLT_ANT_NIL_OK : 0x00;
|
||||
instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_CODE_MASK) == ANT_STATUS_CODE_OK) ? ANT_STATE_OK : 0x00;
|
||||
/*** Antenna Status Chunk 1 ***/
|
||||
rawData = PhyRead(instPtr, ANT_STATUS_1);
|
||||
// -- Update Antenna Frequency Status:
|
||||
// [15] - ANT1 PLL on-off status: 1 - PLL1 active, 0 - PLL2 active
|
||||
// [14:0] - ANT1 PLL frequency, base frequency is 3700 MHz
|
||||
// [31] - ANT2 PLL on-off status: 1 - PLL1 active, 0 - PLL2 active
|
||||
// [30:16] - ANT2 PLL frequency, base frequency is 3700 MHz
|
||||
instPtr->hwSate.ant1Freq = (rawData & ANT_STATUS_1_ANT1_STATUS_MASK) >> ANT_STATUS_1_ANT1_STATUS_SHIFT;
|
||||
instPtr->hwSate.ant2Freq = (rawData & ANT_STATUS_1_ANT2_STATUS_MASK) >> ANT_STATUS_1_ANT2_STATUS_SHIFT;
|
||||
|
||||
/*** Temperature and Lock Status ***/
|
||||
rawData = PhyRead(instPtr, ANT_RF_STATUS);
|
||||
/*** Antenna Status Chunk 2 ***/
|
||||
rawData = PhyRead(instPtr, ANT_STATUS_2);
|
||||
// -- Update Antenna Frequency Status:
|
||||
// [15] - ANT 3 PLL on-off status: 1 - PLL1 active, 0 - PLL2 active
|
||||
// [14:0] - ANT 3 PLL frequency, base frequency is 3700 MHz
|
||||
// [16] - PLL1 of ANT1 lock status: 1 - lock, 2 - unlock
|
||||
// [17] - PLL2 of ANT1 lock status: 1 - lock, 2 - unlock
|
||||
// [18] - PLL1 of ANT2 lock status: 1 - lock, 2 - unlock
|
||||
// [19] - PLL2 of ANT2 lock status: 1 - lock, 2 - unlock
|
||||
// [20] - PLL1 of ANT3 lock status: 1 - lock, 2 - unlock
|
||||
// [21] - PLL2 of ANT3 lock status: 1 - lock, 2 - unlock
|
||||
// [24] - Working mode of ANT1: 0 - normal mode, 1 - anti-jamming mode
|
||||
// [25] - Working mode of ANT2: 0 - normal mode, 1 - anti-jamming mode
|
||||
// [26] - Working mode of ANT3: 0 - normal mode, 1 - anti-jamming mode
|
||||
instPtr->hwSate.ant3Freq = (rawData & ANT_STATUS_2_ANT3_STATUS_MASK) >> ANT_STATUS_2_ANT3_STATUS_SHIFT;
|
||||
instPtr->hwSate.antPll = (rawData & ANT_STATUS_2_PLL_LK_MASK) >> ANT_STATUS_2_PLL_LK_SHIFT;
|
||||
instPtr->hwSate.antMode = (rawData & ANT_STATUS_2_MODE_MASK) >> ANT_STATUS_2_MODE_SHIFT;
|
||||
|
||||
/*** Temperature and Reserved Control ***/
|
||||
rawData = PhyRead(instPtr, ANT_STATUS_TEMP);
|
||||
//-- Update Antenna Temperature (signed 8bit integer, 1 centigrade per LSB)
|
||||
instPtr->hwSate.antTemp = (uint8_t)(rawData & ANT_RF_STATUS_TEMP_MASK);
|
||||
// -- Update Antenna PLL Lock Status: 1 - normal, 0 - error
|
||||
// [0] - BASEBAND lock status
|
||||
// [2] - PLLA lock status
|
||||
// [4] - PLLB lock status
|
||||
instPtr->hwSate.antPll = ((rawData & ANT_RF_STATUS_BBLOCK_MASK) == ANT_RF_STATUS_BBLOCK_OK) ? CLK_ANT_BBPLL_LOCK : 0x00;
|
||||
instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLA_MASK) == ANT_RF_STATUS_PLLA_OK) ? CLK_ANT_RFPLL1_LOCK : 0x00;
|
||||
instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLB_MASK) == ANT_RF_STATUS_PLLB_OK) ? CLK_ANT_RFPLL2_LOCK : 0x00;
|
||||
instPtr->hwSate.antTemp = (uint8_t)(rawData & ANT_STATUS_TEMP_MASK) >> ANT_STATUS_TEMP_SHIFT;
|
||||
instPtr->hwSate.antRsvd = (uint8_t)(rawData & ANT_STATUS_TEMP_RSVD_MASK) >> ANT_STATUS_TEMP_RSVD_SHIFT;
|
||||
|
||||
/*** MGCs ***/
|
||||
rawData = PhyRead(instPtr, ANT_RF_MGC);
|
||||
// -- Update Antenna MGC (0~15 dB)
|
||||
// [3:0] - Channel 1 MGC
|
||||
// [7:4] - Channel 2 MGC
|
||||
// [11:8] - Channel 3 MGC
|
||||
// [15:12] - Channel 4 MGC
|
||||
instPtr->hwSate.antMgc0 = (rawData & ANT_RF_MGC_CH1_MASK);
|
||||
instPtr->hwSate.antMgc0 |= (rawData & ANT_RF_MGC_CH2_MASK) >> 4;
|
||||
instPtr->hwSate.antMgc1 = (rawData & ANT_RF_MGC_CH3_MASK) >> 16;
|
||||
instPtr->hwSate.antMgc1 |= (rawData & ANT_RF_MGC_CH4_MASK) >> 24;
|
||||
|
||||
// Determin if antenna is ok.
|
||||
instPtr->hwSate.isAntOk = (instPtr->hwSate.antVolt == (VOLT_ANT_PROC_OK | VOLT_ANT_RF_OK | VOLT_ANT_NIL_OK | ANT_STATE_OK))
|
||||
&& (instPtr->hwSate.antPll == (CLK_ANT_BBPLL_LOCK | CLK_ANT_RFPLL1_LOCK | CLK_ANT_RFPLL2_LOCK));
|
||||
// Determine if antenna is ok.
|
||||
instPtr->hwSate.isAntOk = 1U; // FIXME: proper condition is required
|
||||
|
||||
instPtr->hwSate.phyId = instPtr->phyCofig.devId;
|
||||
|
||||
@@ -1176,17 +1058,17 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
|
||||
*/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @brief Get the last scan beam number after autoscan.
|
||||
* @brief Get the antenna number after physical listening.
|
||||
*
|
||||
* @param instPtr a pointer to physical instance
|
||||
*
|
||||
* @return beam number
|
||||
* @return antenna index
|
||||
*
|
||||
******************************************************************************/
|
||||
uint8_t Phy_LastScanBeamNo(PHY_INST *instPtr)
|
||||
uint8_t Phy_ListenAntIndex(PHY_INST *instPtr)
|
||||
{
|
||||
ASSERT(instPtr != NULL);
|
||||
return (uint8_t)PhyRead(instPtr, BEAM_SELECT_INDEX);
|
||||
return (uint8_t)PhyRead(instPtr, ANT_SELECT_INDEX);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
@@ -1208,7 +1090,7 @@ double Phy_GetFreqEst(PHY_INST *instPtr)
|
||||
double coarse, fine;
|
||||
|
||||
frameType = Phy_GetLastRecvFrameType(instPtr);
|
||||
if (frameType > L1_1M2BPS_5MS_FRAME || frameType <= L1_NONE_FRAME)
|
||||
if (frameType > L1_FRAME_2MBPS_4MS || frameType <= L1_FRAME_NONE)
|
||||
{
|
||||
return INFINITY; // FIXME
|
||||
}
|
||||
@@ -1218,7 +1100,7 @@ double Phy_GetFreqEst(PHY_INST *instPtr)
|
||||
syncFreqIdx = (coarseReg & COASE_FREQEST_SYNC_MASK) >> COASE_FREQEST_SYNC_SHIFT;
|
||||
fineReg = PhyRead(instPtr, FINE_FREQEST);
|
||||
estAbs = fineReg & FINE_FREQEST_VAL_MASK;
|
||||
if (frameType >= L1_200KBPS_5MS_FRAME)
|
||||
if (frameType >= L1_FRAME_128KBPS_4MS)
|
||||
{
|
||||
// 12M Rc
|
||||
coarse = (double)(8 - acqFreqIdx) * (250e3 / 4);
|
||||
@@ -1259,14 +1141,14 @@ double Phy_GetCoarseFreqEst(PHY_INST *instPtr)
|
||||
double freqEst;
|
||||
|
||||
frameType = Phy_GetLastRecvFrameType(instPtr);
|
||||
if ((frameType > L1_1M2BPS_5MS_FRAME) || (frameType <= L1_NONE_FRAME))
|
||||
if ((frameType > L1_FRAME_2MBPS_4MS) || (frameType <= L1_FRAME_NONE))
|
||||
{
|
||||
return INFINITY; // FIXME
|
||||
}
|
||||
regValue = PhyRead(instPtr, COASE_FREQEST);
|
||||
acqFreqIdx = (regValue & COASE_FREQEST_ACQ_MASK) >> COASE_FREQEST_ACQ_SHIFT;
|
||||
syncFreqIdx = (regValue & COASE_FREQEST_SYNC_MASK) >> COASE_FREQEST_SYNC_SHIFT;
|
||||
if (frameType >= L1_200KBPS_5MS_FRAME)
|
||||
if (frameType >= L1_FRAME_128KBPS_4MS)
|
||||
{
|
||||
// 12M Rc
|
||||
freqEst = (double)(8 - acqFreqIdx) * (250e3 / 4);
|
||||
@@ -1297,14 +1179,14 @@ double Phy_GetFineFreqEst(PHY_INST *instPtr)
|
||||
double freqEst;
|
||||
L1_FRAME_TYPE frameType;
|
||||
frameType = Phy_GetLastRecvFrameType(instPtr);
|
||||
if ((frameType > L1_1M2BPS_5MS_FRAME) || (frameType <= L1_NONE_FRAME))
|
||||
if ((frameType > L1_FRAME_2MBPS_4MS) || (frameType <= L1_FRAME_NONE))
|
||||
{
|
||||
return INFINITY; // FIXME
|
||||
}
|
||||
|
||||
regValue = PhyRead(instPtr, FINE_FREQEST);
|
||||
estAbs = regValue & FINE_FREQEST_VAL_MASK;
|
||||
if ((frameType >= L1_200KBPS_5MS_FRAME))
|
||||
if ((frameType >= L1_FRAME_128KBPS_4MS))
|
||||
{
|
||||
// 12M Rc
|
||||
freqEst = 48e6 / 2048 * ((double)estAbs) / 8192.0;
|
||||
|
||||
@@ -34,23 +34,19 @@
|
||||
* @name PhysicalLayer_Common_Constant
|
||||
* @{
|
||||
*/
|
||||
#define L1_NUM_ANT_NRRW_PATTERN 37U
|
||||
#define L1_INIT_BEAM_NO 0U
|
||||
#define L1_INIT_ANT_WD PHY_ANT_BEAM_120
|
||||
#define L1_ANT_NUM_CH 4U
|
||||
#define L1_ANT_NUM 3U // 1 beam per antenna, and 3 antennas in total
|
||||
#define L1_ANT_CH_NUM 4U // channel number per antenna
|
||||
#define L1_INIT_ANT_IDX 0U
|
||||
|
||||
#define L1_FRAME_NONE_LEN UINT32_MAX // byte
|
||||
#define L1_FRAME_NONE_COMP UINT32_MAX // *10ns(Timer_L)
|
||||
#define L1_FRAME_NONE_HOPS UINT32_MAX
|
||||
#define L1_FRAME_MAX_HOPS 81U
|
||||
#define L1_FRAME_2KBPS_20MS_HOPS 1U
|
||||
#define L1_FRAME_2KBPS_100MS_HOPS 81U
|
||||
#define L1_FRAME_10KBPS_10MS_HOPS 1U
|
||||
#define L1_FRAME_10KBPS_20MS_HOPS 11U
|
||||
#define L1_FRAME_40KBPS_20MS_HOPS 19U
|
||||
#define L1_FRAME_40KBPS_10MS_HOPS 9U
|
||||
#define L1_FRAME_200KBPS_5MS_HOPS 20U
|
||||
#define L1_FRAME_1M2BPS_5MS_HOPS 20U
|
||||
#define L1_FRAME_MAX_HOPS 81
|
||||
#define L1_FRAME_ADV_24MS_HOPS 16U // sync 16 ms + data 8 ms, 2000 hops/s
|
||||
#define L1_FRAME_ACK_8MS_HOPS 4U // sync 6 ms + data 2 ms, 2000 hops/s
|
||||
#define L1_FRAME_128KBPS_4MS_HOPS 33U
|
||||
#define L1_FRAME_512KBPS_4MS_HOPS 36U
|
||||
#define L1_FRAME_2MBPS_4MS_HOPS 38U
|
||||
#define PHY_LOG_EXPIRE 40U // 50*5ms
|
||||
/** @} */
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
@@ -60,15 +56,12 @@
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
L1_NONE_FRAME = 0,
|
||||
L1_2KBPS_20MS_FRAME = 1,
|
||||
L1_2KBPS_100MS_FRAME = 2,
|
||||
L1_10KBPS_10MS_FRAME = 3,
|
||||
L1_10KBPS_20MS_FRAME = 4,
|
||||
L1_40KBPS_20MS_FRAME = 5,
|
||||
L1_40KBPS_10MS_FRAME = 6,
|
||||
L1_200KBPS_5MS_FRAME = 7,
|
||||
L1_1M2BPS_5MS_FRAME = 8
|
||||
L1_FRAME_NONE = 0,
|
||||
L1_FRAME_ADV_24MS = 1,
|
||||
L1_FRAME_ACK_8MS = 2,
|
||||
L1_FRAME_128KBPS_4MS = 3, // 128kbps
|
||||
L1_FRAME_512KBPS_4MS = 4, // 512kbps
|
||||
L1_FRAME_2MBPS_4MS = 5 // 2 Mbps
|
||||
} L1_FRAME_TYPE;
|
||||
|
||||
/**
|
||||
@@ -77,58 +70,36 @@ typedef enum
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*** Ant Control ***/
|
||||
uint8_t ctrlWord; ///< Antenna control frame head 0xAA\n
|
||||
/// default 0, reserved for further use
|
||||
uint8_t antMode; ///< high 4 bits specified beam mode.\n
|
||||
/// low 4 bits specified power control
|
||||
uint8_t oaxis[2]; ///< off-axis angle range is 0~60 \n
|
||||
/// 0.1 degree each LSB
|
||||
uint8_t raxis[2]; ///< round-axis angle range is 0~360, \n
|
||||
/// 0.1 degree each LSB
|
||||
uint8_t antFreq[2]; ///< 0~3500Mhz, step 1MHz
|
||||
uint8_t trSlect; ///< in single tr mode, 0~63 specified tr channel \n
|
||||
/// in single subarray mode, 0~3 specified the subarray
|
||||
/// ! Only in debug mode!
|
||||
uint8_t antAtt; ///< Antenna attenuation 0~31, 0.5dB each LSB, Only in debug mode
|
||||
uint8_t phase; ///< 0~63, 5.625 degree each LSB, Only in debug mode
|
||||
uint8_t rxtxMode; ///< Only for debug \n
|
||||
/// default 0x00
|
||||
uint8_t calibrMode; ///< 0x00 Normal, 0x01 single tr calibration
|
||||
uint8_t antReserved; ///< reserved for further use
|
||||
|
||||
/*** RF Control ***/
|
||||
uint8_t rfCtrl; ///< [7:4]RF enable: 0-On, 1-Off(Default); [3:0]Work mode: 0(default)
|
||||
uint8_t rfFreq[2]; ///< 0~3500Mhz, step 1MHz
|
||||
uint8_t rfTxMgc; ///< RF MGC control: 0~31, 1dB each LSB
|
||||
uint8_t rf12CalMgc; ///< RF channel 1&2 calibration mgc\n
|
||||
/// [7:4] Channle1 - max 15db, 1dB each LSB \n
|
||||
/// [3:0] Channle2 - max 15db, 1dB each LSB
|
||||
uint8_t rf34CalMgc; ///< RF channel 3&4 calibration mgc\n
|
||||
/// [7:4] Channle3 - max 15db, 1dB each LSB
|
||||
/// [3:0] Channle4 - max 15db, 1dB each LSB
|
||||
uint8_t rcvMgc; ///< Receive channel 1-4 MGC: 0~31, 1dB each LSB
|
||||
uint8_t rfMonitor; ///< Receive monitor, 0-normal, 1-switch to monitor port
|
||||
uint8_t rfReserved0; ///< reserved for further use
|
||||
uint8_t rfReserved1; ///< reserved for further use
|
||||
uint8_t ch0Cal[2];
|
||||
uint8_t ch1Cal[2];
|
||||
uint8_t ch2Cal[2];
|
||||
uint8_t ch3Cal[2];
|
||||
/*** Antenna & RF Control ***/
|
||||
uint8_t rfNormComp[L1_ANT_NUM][L1_ANT_CH_NUM];
|
||||
///< Normal mode RF phase compensation, 3 antennas
|
||||
/// and 4 channels each: 0~63, 5.625° step
|
||||
uint8_t rfNormIdpAttn[L1_ANT_NUM][L1_ANT_CH_NUM];
|
||||
///< Normal mode RF attenuation for independent channel:
|
||||
/// 0~30 dB, 1dB step
|
||||
uint8_t rfNormComAttn[L1_ANT_NUM];
|
||||
///< Normal mode RF attenuation for combined channel:
|
||||
/// 0~30 dB, 1dB step
|
||||
uint8_t rfMode; ///< Mode control:
|
||||
/// [7]: reserved
|
||||
/// [6]: Antenna 3 tx control, 1 - enable, 0 - disable
|
||||
/// [5]: Antenna 2 tx control, 1 - enable, 0 - disable
|
||||
/// [4]: Antenna 1 tx control, 1 - enable, 0 - disable
|
||||
/// [3]: Anti-jamming antenna 3 select, 1 - enable, 0 - disable
|
||||
/// [2]: Anti-jamming antenna 2 select, 1 - enable, 0 - disable
|
||||
/// [1]: Anti-jamming antenna 1 select, 1 - enable, 0 - disable
|
||||
/// only one antenna can be selected in anti-jamming mode
|
||||
/// [0]: Anti-jamming mode control, 1 - enable, 0 - disable
|
||||
uint8_t rfAntiAttn[L1_ANT_CH_NUM];
|
||||
///< Anti-jamming mode RF attenuation, 4 channels:
|
||||
/// 0~60 dB, 1dB step
|
||||
uint8_t rfFreq[L1_ANT_NUM][2];
|
||||
///< RF synthesizer ping-pong frequency, 3 antennas
|
||||
/// and 2 byte each: 0~600 MHz, step 1MHz, with base
|
||||
/// frequency of 3700 MHz
|
||||
uint8_t rfRsvd; ///< reserved for further use
|
||||
} PHY_ANT_CONFIG;
|
||||
|
||||
/**
|
||||
* @struct PHY_ANT_ANGLE
|
||||
* @brief Describe the PhysicalLayer antenna angle
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t oaxis; ///< off-axis angle range is 0~60
|
||||
/// 0.1 degree each LSB
|
||||
uint16_t raxis; ///< round-axis angle range is 0~360
|
||||
/// 0.1 degree each LSB
|
||||
} PHY_ANT_ANGLE;
|
||||
|
||||
/**
|
||||
* @enum PHY_TIME_WORD_TYPE
|
||||
*/
|
||||
@@ -139,18 +110,6 @@ typedef enum
|
||||
PHY_TIME_WORD_LISTEN_TIMEOUT = 2
|
||||
} PHY_TIME_WORD_TYPE;
|
||||
|
||||
/**
|
||||
* @enum PHY_ANT_BEAM_WIDTH
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PHY_ANT_BEAM_NONE = 0,
|
||||
PHY_ANT_BEAM_120 = 1,
|
||||
PHY_ANT_BEAM_60 = 2,
|
||||
PHY_ANT_BEAM_25 = 3,
|
||||
PHY_ANT_BEAM_16 = 4
|
||||
} PHY_ANT_BEAM_WIDTH;
|
||||
|
||||
/**
|
||||
* @enum PHY_TOR_TYPE
|
||||
*/
|
||||
@@ -168,8 +127,7 @@ typedef enum
|
||||
{
|
||||
PHY_MODE_NONE = 0,
|
||||
PHY_MODE_LISTEN = 1,
|
||||
PHY_MODE_SCHEDULE = 2,
|
||||
PHY_MODE_PULL = 3
|
||||
PHY_MODE_POLL = 2
|
||||
} PHY_MODE;
|
||||
|
||||
/**
|
||||
@@ -179,8 +137,8 @@ typedef enum
|
||||
{
|
||||
PHY_ANT_MODE_NONE = 0,
|
||||
PHY_ANT_MODE_STANDBY = 1,
|
||||
PHY_ANT_MODE_POWER_LOW = 2,
|
||||
PHY_ANT_MODE_POWER_FULL = 3,
|
||||
PHY_ANT_MODE_NORMAL = 2,
|
||||
PHY_ANT_MODE_ANTI_JAM = 3
|
||||
} PHY_ANT_MODE;
|
||||
|
||||
/**
|
||||
@@ -204,7 +162,6 @@ typedef struct
|
||||
uint32_t txBramId; ///< tx bram ID
|
||||
uint32_t rxBramId; ///< rx bram ID
|
||||
uint32_t antBramId; ///< antenna config bram ID
|
||||
uint32_t antInfoBramId; ///< antenna beam info bram ID
|
||||
uint32_t hwXadcId; ///< hardware xadc device ID
|
||||
uintptr_t baseAddr; ///< Physical layer controller base address
|
||||
#ifndef EMULATION
|
||||
@@ -225,7 +182,6 @@ typedef struct
|
||||
uintptr_t recvDataAddr; ///< receive data bram address
|
||||
uintptr_t sendDataAddr; ///< send data bram address
|
||||
uintptr_t antConfigAddr; ///< antenna config data bram address
|
||||
uintptr_t antInfoAddr; ///< antenna beam info data bram address
|
||||
bool isPhyEn; ///< indicates if physical layer running
|
||||
bool isAcq; ///< indicates if last reception acquisition success
|
||||
bool isFrameSync; ///< indicates if last reception frame sync success
|
||||
@@ -233,8 +189,7 @@ typedef struct
|
||||
bool isValid; ///< indicates if last reception frame data valid (crc check pass)
|
||||
TIME_WORD recvSlotTime; ///< last slot start time stamp
|
||||
TIME_WORD recvFsTime; ///< last frame sync time stamp
|
||||
PHY_RCD beamNo; ///< beam number record
|
||||
PHY_RCD beamWd; ///< beam width record
|
||||
PHY_RCD antIndex; ///< antenna number record
|
||||
PHY_RCD tor; ///< tx rx state record
|
||||
PHY_RCD frameType; ///< frame type record
|
||||
uint32_t sendDataOffset; ///< antenna configuration bram offset (to implement ping-pong data flow)
|
||||
@@ -243,7 +198,7 @@ typedef struct
|
||||
#ifndef EMULATION
|
||||
XAdcPs hwXadc; ///< hardware Xadc instance
|
||||
#endif
|
||||
PHY_ANT_ANGLE antNrrwPattern[L1_NUM_ANT_NRRW_PATTERN]; ///< antenna beam scan pattern
|
||||
PHY_ANT_ANGLE antNrrwPattern[L1_ANT_PATTERN_NUM]; ///< antenna beam scan pattern
|
||||
HWSTATE hwSate; ///< hardware state log
|
||||
PHYLOG phyLog; ///< physical state log
|
||||
uint32_t lastLogTime; /// physical state log time stamp
|
||||
@@ -288,7 +243,7 @@ L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST *instPtr);
|
||||
* @defgroup PhysicalLayer_Receive_Estimations
|
||||
* @{
|
||||
*/
|
||||
uint8_t Phy_LastScanBeamNo(PHY_INST *instPtr);
|
||||
uint8_t Phy_ListenAntIndex(PHY_INST *instPtr);
|
||||
double Phy_GetFreqEst(PHY_INST *instPtr);
|
||||
double Phy_GetCoarseFreqEst(PHY_INST *instPtr);
|
||||
double Phy_GetFineFreqEst(PHY_INST *instPtr);
|
||||
@@ -304,10 +259,9 @@ void Phy_GetLastReceivedSlotStartTimeStamp(PHY_INST *instPtr, TIME_WORD *slotSta
|
||||
*/
|
||||
void Phy_AntConfigInit(PHY_ANT_CONFIG *antConfig);
|
||||
void Phy_AntConfigMode(PHY_INST *instPtr, PHY_ANT_MODE mode);
|
||||
void Phy_SetBeamTable(PHY_INST *instPtr, PHY_ANT_ANGLE *table, uint32_t offset);
|
||||
int32_t Phy_SetBeamWidth(PHY_INST *instPtr, PHY_ANT_BEAM_WIDTH beamWidth);
|
||||
int32_t Phy_SetBeamNo(PHY_INST *instPtr, size_t beamNo, PHY_ANT_BEAM_WIDTH beamWidth);
|
||||
int32_t Phy_SetBeamAngle(PHY_INST *phyInstPtr, double offAx, double rndAx);
|
||||
int32_t Phy_SetAntIndex(PHY_INST *instPtr, size_t antIndex);
|
||||
size_t Phy_GetCurrentAntIndex(PHY_INST *instPtr);
|
||||
size_t Phy_GetNextAntIndex(PHY_INST *instPtr);
|
||||
/** @} PhysicalLayer_AntennaControl*/
|
||||
|
||||
#endif // PHY_CTRL_H_
|
||||
|
||||
@@ -48,8 +48,7 @@
|
||||
#define PHY_MAIN_CTRL_EN_DSBL 0x00000000U
|
||||
#define PHY_MAIN_CTRL_MODE_NONE 0x00000000U
|
||||
#define PHY_MAIN_CTRL_MODE_LISTEN 0x00000100U
|
||||
#define PHY_MAIN_CTRL_MODE_SCHEDULE 0x00000200U
|
||||
#define PHY_MAIN_CTRL_MODE_PULL 0x00000300U
|
||||
#define PHY_MAIN_CTRL_MODE_POLL 0x00000200U
|
||||
|
||||
/**
|
||||
* Register: TXRX_CTRL
|
||||
@@ -70,14 +69,11 @@
|
||||
#define PHY_MODE_CTRL_TOR_RX 0x00000002U
|
||||
|
||||
#define PHY_MODE_CTRL_FRAME_NONE 0x00000000U
|
||||
#define PHY_MODE_CTRL_FRAME_2KBPS_20MS 0x00000100U
|
||||
#define PHY_MODE_CTRL_FRAME_2KBPS_100MS 0x00000200U
|
||||
#define PHY_MODE_CTRL_FRAME_10KBPS_10MS 0x00000300U // Initial Scan Frame
|
||||
#define PHY_MODE_CTRL_FRAME_10KBPS_20MS 0x00000400U // Benchmark Frame
|
||||
#define PHY_MODE_CTRL_FRAME_40KBPS_20MS 0x00000500U
|
||||
#define PHY_MODE_CTRL_FRAME_40KBPS_10MS 0x00000600U
|
||||
#define PHY_MODE_CTRL_FRAME_200KBPS_5MS 0x00000700U // 2-Way ACQ Frame, Management Frame, Service Frame
|
||||
#define PHY_MODE_CTRL_FRAME_1M2BPS_5MS 0x00000800U // Bistatic Synthetic Aperture Radar Frame
|
||||
#define PHY_MODE_CTRL_FRAME_ADV_24MS 0x00000100U
|
||||
#define PHY_MODE_CTRL_FRAME_ACK_8MS 0x00000200U
|
||||
#define PHY_MODE_CTRL_FRAME_128KBPS_4MS 0x00000300U
|
||||
#define PHY_MODE_CTRL_FRAME_512KBPS_4MS 0x00000400U
|
||||
#define PHY_MODE_CTRL_FRAME_2MBPS_4MS 0x00000500U
|
||||
|
||||
#define PHY_MODE_CTRL_CRC_EN 0x00010000U
|
||||
#define PHY_MODE_CTRL_CRC_DSBL 0x00000000U
|
||||
@@ -236,14 +232,11 @@
|
||||
#define COASE_TYPE_SHIFT 16
|
||||
#define COASE_TYPE_WIDTH 8
|
||||
#define COASE_TYPE_MASK 0x00FF0000U
|
||||
#define COASE_TYPE_2KBPS_20MS 0x00010000U
|
||||
#define COASE_TYPE_2KBPS_100MS 0x00020000U
|
||||
#define COASE_TYPE_10KBPS_10MS 0x00030000U
|
||||
#define COASE_TYPE_10KBPS_20MS 0x00040000U
|
||||
#define COASE_TYPE_40KBPS_20MS 0x00050000U
|
||||
#define COASE_TYPE_40KBPS_10MS 0x00060000U
|
||||
#define COASE_TYPE_200KBPS_5MS 0x00070000U
|
||||
#define COASE_TYPE_1M2BPS_5MS 0x00080000U
|
||||
#define COASE_TYPE_ADV_24MS 0x00010000U
|
||||
#define COASE_TYPE_ACK_8MS 0x00020000U
|
||||
#define COASE_TYPE_128KBPS_4MS 0x00030000U
|
||||
#define COASE_TYPE_512KBPS_4MS 0x00040000U
|
||||
#define COASE_TYPE_2MBPS_4MS 0x00050000U
|
||||
|
||||
/**
|
||||
* Register: FINE_FREQEST
|
||||
@@ -259,103 +252,115 @@
|
||||
#define FINE_FREQEST_SIGN_NEG 0x01000000U
|
||||
|
||||
/**
|
||||
* Register: BEAM_SELECT
|
||||
* Register: ANT_SELECT
|
||||
*/
|
||||
#define BEAM_SELECT_INDEX 0x00000044U
|
||||
#define BEAM_SELECT_INDEX_SHIFT 0
|
||||
#define BEAM_SELECT_INDEX_WIDTH 32
|
||||
#define BEAM_SELECT_INDEX_MASK 0xFFFFFFFFU
|
||||
#define ANT_SELECT_INDEX 0x00000044U
|
||||
#define ANT_SELECT_INDEX_SHIFT 0
|
||||
#define ANT_SELECT_INDEX_WIDTH 32
|
||||
#define ANT_SELECT_INDEX_MASK 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* Register: BEAM_AXIS
|
||||
* Register: ANT_STATUS_1
|
||||
*/
|
||||
#define BEAM_AXIS 0x00000044U
|
||||
#define BEAM_AXIS_EL_SHIFT 0
|
||||
#define BEAM_AXIS_EL_WIDTH 16
|
||||
#define BEAM_AXIS_EL_MASK 0x0000FFFFU
|
||||
#define BEAM_AXIS_AZ_SHIFT 16
|
||||
#define BEAM_AXIS_AZ_WIDTH 16
|
||||
#define BEAM_AXIS_AZ_MASK 0xFFFF0000U
|
||||
#define ANT_STATUS_1 0x00000100U
|
||||
|
||||
#define ANT_STATUS_1_ANT1_STATUS_SHIFT 0
|
||||
#define ANT_STATUS_1_ANT1_STATUS_WIDTH 16
|
||||
#define ANT_STATUS_1_ANT1_STATUS_MASK 0x0000FFFFU
|
||||
|
||||
#define ANT_STATUS_1_ANT1_FREQ_SHIFT 0
|
||||
#define ANT_STATUS_1_ANT1_FREQ_WIDTH 15
|
||||
#define ANT_STATUS_1_ANT1_FREQ_MASK 0x00003FFFU
|
||||
|
||||
#define ANT_STATUS_1_ANT1_PLL_SHIFT 15
|
||||
#define ANT_STATUS_1_ANT1_PLL_WIDTH 1
|
||||
#define ANT_STATUS_1_ANT1_PLL_MASK 0x00008000U
|
||||
|
||||
#define ANT_STATUS_1_ANT2_STATUS_SHIFT 16
|
||||
#define ANT_STATUS_1_ANT2_STATUS_WIDTH 16
|
||||
#define ANT_STATUS_1_ANT2_STATUS_MASK 0x0000FFFFU
|
||||
|
||||
#define ANT_STATUS_1_ANT2_FREQ_SHIFT 16
|
||||
#define ANT_STATUS_1_ANT2_FREQ_WIDTH 15
|
||||
#define ANT_STATUS_1_ANT2_FREQ_MASK 0x3FFF0000U
|
||||
|
||||
#define ANT_STATUS_1_ANT2_PLL_SHIFT 31
|
||||
#define ANT_STATUS_1_ANT2_PLL_WIDTH 1
|
||||
#define ANT_STATUS_1_ANT2_PLL_MASK 0x80000000U
|
||||
|
||||
/**
|
||||
* Register: ANT_STATUS
|
||||
* Register: ANT_STATUS_2
|
||||
*/
|
||||
#define ANT_STATUS 0x00000100U
|
||||
#define ANT_STATUS_ANT_VOLT_SHIFT 0
|
||||
#define ANT_STATUS_ANT_VOLT_WIDTH 8
|
||||
#define ANT_STATUS_ANT_VOLT_MASK 0x000000FFU
|
||||
#define ANT_STATUS_ANT_VOLT_OK 0x00000001U
|
||||
#define ANT_STATUS_2 0x00000104U
|
||||
|
||||
#define ANT_STATUS_RF_VOLT_SHIFT 8
|
||||
#define ANT_STATUS_RF_VOLT_WIDTH 8
|
||||
#define ANT_STATUS_RF_VOLT_MASK 0x0000FF00U
|
||||
#define ANT_STATUS_RF_VOLT_OK 0x00000100U
|
||||
#define ANT_STATUS_2_ANT3_STATUS_SHIFT 0
|
||||
#define ANT_STATUS_2_ANT3_STATUS_WIDTH 16
|
||||
#define ANT_STATUS_2_ANT3_STATUS_MASK 0x0000FFFFU
|
||||
|
||||
#define ANT_STATUS_NIL_VOLT_SHIFT 16
|
||||
#define ANT_STATUS_NIL_VOLT_WIDTH 8
|
||||
#define ANT_STATUS_NIL_VOLT_MASK 0x00FF0000U
|
||||
#define ANT_STATUS_NIL_VOLT_OK 0x00010000U
|
||||
#define ANT_STATUS_2_ANT3_FREQ_SHIFT 0
|
||||
#define ANT_STATUS_2_ANT3_FREQ_WIDTH 15
|
||||
#define ANT_STATUS_2_ANT3_FREQ_MASK 0x00003FFFU
|
||||
|
||||
#define ANT_STATUS_CODE_SHIFT 24
|
||||
#define ANT_STATUS_CODE_WIDTH 8
|
||||
#define ANT_STATUS_CODE_MASK 0xFF000000U
|
||||
#define ANT_STATUS_CODE_OK 0x00000000U
|
||||
#define ANT_STATUS_2_ANT3_PLL_SHIFT 15
|
||||
#define ANT_STATUS_2_ANT3_PLL_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT3_PLL_MASK 0x00008000U
|
||||
|
||||
#define ANT_STATUS_2_PLL_LK_SHIFT 16
|
||||
#define ANT_STATUS_2_PLL_LK_WIDTH 8
|
||||
#define ANT_STATUS_2_PLL_LK_MASK 0x00FF0000U
|
||||
|
||||
#define ANT_STATUS_2_ANT3_PLL2_LK_SHIFT 16
|
||||
#define ANT_STATUS_2_ANT3_PLL2_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT3_PLL2_LK_MASK 0x00010000U
|
||||
|
||||
#define ANT_STATUS_2_ANT3_PLL1_LK_SHIFT 17
|
||||
#define ANT_STATUS_2_ANT3_PLL1_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT3_PLL1_LK_MASK 0x00020000U
|
||||
|
||||
#define ANT_STATUS_2_ANT2_PLL2_LK_SHIFT 18
|
||||
#define ANT_STATUS_2_ANT2_PLL2_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT2_PLL2_LK_MASK 0x00040000U
|
||||
|
||||
#define ANT_STATUS_2_ANT2_PLL1_LK_SHIFT 19
|
||||
#define ANT_STATUS_2_ANT2_PLL1_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT2_PLL1_LK_MASK 0x00080000U
|
||||
|
||||
#define ANT_STATUS_2_ANT1_PLL2_LK_SHIFT 20
|
||||
#define ANT_STATUS_2_ANT1_PLL2_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT1_PLL2_LK_MASK 0x00100000U
|
||||
|
||||
#define ANT_STATUS_2_ANT1_PLL1_LK_SHIFT 21
|
||||
#define ANT_STATUS_2_ANT1_PLL1_LK_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT1_PLL1_LK_MASK 0x00200000U
|
||||
|
||||
#define ANT_STATUS_2_MODE_SHIFT 24
|
||||
#define ANT_STATUS_2_MODE_WIDTH 8
|
||||
#define ANT_STATUS_2_MODE_MASK 0xFF000000U
|
||||
|
||||
#define ANT_STATUS_2_ANT1_MODE_SHIFT 24
|
||||
#define ANT_STATUS_2_ANT1_MODE_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT1_MODE_MASK 0x01000000U
|
||||
|
||||
#define ANT_STATUS_2_ANT2_MODE_SHIFT 25
|
||||
#define ANT_STATUS_2_ANT2_MODE_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT2_MODE_MASK 0x02000000U
|
||||
|
||||
#define ANT_STATUS_2_ANT3_MODE_SHIFT 26
|
||||
#define ANT_STATUS_2_ANT3_MODE_WIDTH 1
|
||||
#define ANT_STATUS_2_ANT3_MODE_MASK 0x04000000U
|
||||
|
||||
/**
|
||||
* Register: ANT_FRAME_CNT
|
||||
* Register: ANT_STATUS_TEMP
|
||||
*/
|
||||
#define ANT_FRAME_CNT 0x00000104U
|
||||
#define ANT_FRAME_CNT_SHIFT 0
|
||||
#define ANT_FRAME_CNT_WIDTH 32
|
||||
#define ANT_FRAME_CNT_MASK 0xFFFFFFFFU
|
||||
#define ANT_STATUS_TEMP 0x00000108U
|
||||
|
||||
/**
|
||||
* Register: ANT_RF_STATUS
|
||||
*/
|
||||
#define ANT_RF_STATUS 0x00000108U
|
||||
#define ANT_RF_STATUS_TEMP_SHIFT 0
|
||||
#define ANT_RF_STATUS_TEMP_WIDTH 8
|
||||
#define ANT_RF_STATUS_TEMP_MASK 0x000000FFU
|
||||
#define ANT_STATUS_TEMP_SHIFT 0
|
||||
#define ANT_STATUS_TEMP_WIDTH 8
|
||||
#define ANT_STATUS_TEMP_MASK 0x000000FFU
|
||||
|
||||
#define ANT_RF_STATUS_BBLOCK_SHIFT 8
|
||||
#define ANT_RF_STATUS_BBLOCK_WIDTH 8
|
||||
#define ANT_RF_STATUS_BBLOCK_MASK 0x0000FF00U
|
||||
#define ANT_RF_STATUS_BBLOCK_OK 0x00000100U
|
||||
|
||||
#define ANT_RF_STATUS_PLLA_SHIFT 16
|
||||
#define ANT_RF_STATUS_PLLA_WIDTH 8
|
||||
#define ANT_RF_STATUS_PLLA_MASK 0x00FF0000U
|
||||
#define ANT_RF_STATUS_PLLA_OK 0x00010000U
|
||||
|
||||
#define ANT_RF_STATUS_PLLB_SHIFT 24
|
||||
#define ANT_RF_STATUS_PLLB_WIDTH 8
|
||||
#define ANT_RF_STATUS_PLLB_MASK 0xFF000000U
|
||||
#define ANT_RF_STATUS_PLLB_OK 0x01000000U
|
||||
|
||||
/**
|
||||
* Register: ANT_RF_MGC
|
||||
*/
|
||||
#define ANT_RF_MGC 0x0000010CU
|
||||
#define ANT_RF_MGC_CH1_SHIFT 0
|
||||
#define ANT_RF_MGC_CH1_WIDTH 4
|
||||
#define ANT_RF_MGC_CH1_MASK 0x0000000FU
|
||||
#define ANT_RF_MGC_CH2_SHIFT 8
|
||||
#define ANT_RF_MGC_CH2_WIDTH 4
|
||||
#define ANT_RF_MGC_CH2_MASK 0x00000F00U
|
||||
#define ANT_RF_MGC_CH3_SHIFT 16
|
||||
#define ANT_RF_MGC_CH3_WIDTH 4
|
||||
#define ANT_RF_MGC_CH3_MASK 0x000F0000U
|
||||
#define ANT_RF_MGC_CH4_SHIFT 24
|
||||
#define ANT_RF_MGC_CH4_WIDTH 4
|
||||
#define ANT_RF_MGC_CH4_MASK 0x0F000000U
|
||||
|
||||
/**
|
||||
* Register: ANT_RF_FRAME_CNT
|
||||
*/
|
||||
#define ANT_RF_FRAME_CNT 0x00000110U
|
||||
#define ANT_RF_FRAME_CNT_SHIFT 0
|
||||
#define ANT_RF_FRAME_CNT_WIDTH 32
|
||||
#define ANT_RF_FRAME_CNT_MASK 0xFFFFFFFFU
|
||||
#define ANT_STATUS_TEMP_RSVD_SHIFT 8
|
||||
#define ANT_STATUS_TEMP_RSVD_WIDTH 8
|
||||
#define ANT_STATUS_TEMP_RSVD_MASK 0x0000FF00U
|
||||
|
||||
/**
|
||||
* Register: PHY_ACQ_CNT
|
||||
|
||||
@@ -198,11 +198,13 @@ typedef struct __attribute__((packed))
|
||||
int8_t spAdTemp_1; ///< Signal processor adc1 temperature
|
||||
int8_t spFpgaTemp; ///< Signal processor FPGA temperature
|
||||
// -- Antenna status
|
||||
uint8_t antVolt; ///< Antenna voltage state indicator
|
||||
uint16_t ant1Freq; ///< Antenna 1 frequency
|
||||
uint16_t ant2Freq; ///< Antenna 2 frequency
|
||||
uint16_t ant3Freq; ///< Antenna 3 frequency
|
||||
uint8_t antPll; ///< Antenna pll lock state indicator
|
||||
uint8_t antMode; ///< Antenna mode indicator
|
||||
int8_t antTemp; ///< Antenna rf temperature
|
||||
uint8_t antPll; ///< Antenna rf lock state indicator
|
||||
uint8_t antMgc0; ///< Antenna rf mgc0~1 indicator
|
||||
uint8_t antMgc1; ///< Antenna rf mgc2~3 indicator
|
||||
uint8_t antRsvd; ///< Antenna reserved status register
|
||||
uint8_t phyId;
|
||||
uint8_t reserve[1];
|
||||
} HWSTATE;
|
||||
|
||||
Reference in New Issue
Block a user