/*****************************************************************************/
/**
 * @file phy_layer.h
 * @author FanHao (hao_fan_bit_ee@163.com)
 * @brief Physical layer controller register definition
 * @version 0.0
 * @date 2023-04-24
 *
 * @copyright Copyright(c) 2024 Beijing Institute of Technology.\n
 * Lab of Communication and Network
 *
 ******************************************************************************/
/**
 * @defgroup PhysicalLayer
 * @{
 */

/**
 * @name  PhysicalLayer_REG_Constants
 * @{
 */
#ifndef PHY_REG_H_
#define PHY_REG_H_

/***************************** Include Files *********************************/
#include "util.h"

/***************** Macros (Inline Functions) Definitions *********************/
#define PhyRead(instPtr, addr) IO_In32((instPtr)->phyCofig.baseAddr + (addr))
#define PhyWrite(instPtr, addr, value) IO_Out32((instPtr)->phyCofig.baseAddr + (addr), (value))

/************************** Constant Definitions *****************************/
/**
 * Register: PHY_MAIN_CTRL
 */
#define PHY_MAIN_CTRL 0x00000000U
#define PHY_MAIN_CTRL_EN_SHIFT 0
#define PHY_MAIN_CTRL_EN_WIDTH 1
#define PHY_MAIN_CTRL_EN_MASK 0x00000001U
#define PHY_MAIN_CTRL_MODE_SHIFT 8
#define PHY_MAIN_CTRL_MODE_WIDTH 8
#define PHY_MAIN_CTRL_MODE_MASK 0x0000FF00U
#define PHY_MAIN_CTRL_NSCAN_SHIFT 16
#define PHY_MAIN_CTRL_NSCAN_WIDTH 8
#define PHY_MAIN_CTRL_NSCAN_MASK 0x00FF0000U

#define PHY_MAIN_CTRL_EN_EN 0x00000001U
#define PHY_MAIN_CTRL_EN_DSBL 0x00000000U
#define PHY_MAIN_CTRL_MODE_NONE 0x00000000U
#define PHY_MAIN_CTRL_MODE_LISTEN 0x00000100U
#define PHY_MAIN_CTRL_MODE_SCHEDULE 0x00000200U // not used
#define PHY_MAIN_CTRL_MODE_POLL 0x00000300U

/**
 * Register: TXRX_CTRL
 */
#define PHY_MODE_CTRL 0x00000004U
#define PHY_MODE_CTRL_TOR_SHIFT 0
#define PHY_MODE_CTRL_TOR_WIDTH 8
#define PHY_MODE_CTRL_TOR_MASK 0x000000FFU
#define PHY_MODE_CTRL_FRAME_SHIFT 8
#define PHY_MODE_CTRL_FRAME_WIDTH 8
#define PHY_MODE_CTRL_FRAME_MASK 0x0000FF00U
#define PHY_MODE_CTRL_CRC_SHIFT 8
#define PHY_MODE_CTRL_CRC_WIDTH 16
#define PHY_MODE_CTRL_CRC_MASK 0x00FF0000U

#define PHY_MODE_CTRL_TOR_SUSPEND 0x00000000U
#define PHY_MODE_CTRL_TOR_TX 0x00000001U
#define PHY_MODE_CTRL_TOR_RX 0x00000002U

#define PHY_MODE_CTRL_FRAME_NONE 0x00000000U
#define PHY_MODE_CTRL_FRAME_ADV_24MS 0x00000100U
#define PHY_MODE_CTRL_FRAME_ACK_8MS 0x00000200U
#define PHY_MODE_CTRL_FRAME_128KBPS_4MS 0x00000300U
#define PHY_MODE_CTRL_FRAME_512KBPS_4MS 0x00000400U
#define PHY_MODE_CTRL_FRAME_2MBPS_4MS 0x00000500U

#define PHY_MODE_CTRL_CRC_EN 0x00010000U
#define PHY_MODE_CTRL_CRC_DSBL 0x00000000U
/**
 * Register: POLLTIME_L
 */
#define POLLTIME_L 0x00000008U
#define POLLTIME_L_SHIFT 0
#define POLLTIME_L_WIDTH 32
#define POLLTIME_L_MASK 0xFFFFFFFFU

/**
 * Register: POLLTIME_H
 */
#define POLLTIME_H 0x0000000CU
#define POLLTIME_H_SHIFT 0
#define POLLTIME_H_WIDTH 32
#define POLLTIME_H_MASK 0xFFFFFFFFU

/**
 * Register: TIMEOUT_L
 */
#define LISTENTIMEOUT_L 0x00000010U
#define LISTENTIMEOUT_L_SHIFT 0
#define LISTENTIMEOUT_L_WIDTH 32
#define LISTENTIMEOUT_L_MASK 0xFFFFFFFFU

/**
 * Register: TIMEOUT_H
 */
#define LISTENTIMEOUT_H 0x00000014U
#define LISTENTIMEOUT_H_SHIFT 0
#define LISTENTIMEOUT_H_WIDTH 32
#define LISTENTIMEOUT_H_MASK 0xFFFFFFFFU

/**
 * Register: ANT_CTRL
 */
#define ANT_CONFIG 0x00000018U
#define ANT_CONFIG_OFFSET_SHIFT 0
#define ANT_CONFIG_OFFSET_WIDTH 16
#define ANT_CONFIG_OFFSET_MASK 0x0000FFFFU
#define ANT_CONFIG_LEN_SHIFT 16
#define ANT_CONFIG_LEN_WIDTH 8
#define ANT_CONFIG_LEN_MASK 0x00FF0000U
#define ANT_CONFIG_NUM_SHIFT 24
#define ANT_CONFIG_NUM_WIDTH 8
#define ANT_CONFIG_NUM_MASK 0xFF000000U

/**
 * Register: SEND_DATA_CMD
 */
#define SEND_DATA_CMD 0x0000001CU
#define SEND_DATA_CMD_SHIFT 0
#define SEND_DATA_CMD_WIDTH 32
#define SEND_DATA_CMD_MASK 0xFFFFFFFFU

#define SEND_DATA_CMD_LEN_SHIFT 0
#define SEND_DATA_CMD_LEN_WIDTH 16
#define SEND_DATA_CMD_LEN_MASK 0x0000FFFFU
#define SEND_DATA_CMD_OFFSET_SHIFT 16
#define SEND_DATA_CMD_OFFSET_WIDTH 16
#define SEND_DATA_CMD_OFFSET_MASK 0xFFFF0000U

/**
 * Register: SLOT_CONFIG_CMD
 */
#define SLOT_CMD 0x00000020U
#define SLOT_CMD_SHIFT 0
#define SLOT_CMD_WIDTH 32
#define SLOT_CMD_MASK 0xFFFFFFFFU
#define SLOT_CMD_KEY 0x434D442EU

/**
 * Register: TXRX_STATE
 */
#define TXRX_STATE 0x00000024U
#define TXRX_STATE_ACQ_SHIFT 0
#define TXRX_STATE_ACQ_WIDTH 8
#define TXRX_STATE_ACQ_MASK 0x000000FFU
#define TXRX_STATE_ACQ_SUCCESS 0x00000001U
#define TXRX_STATE_ACQ_FAIL 0x00000002U

#define TXRX_STATE_FSYNC_SHIFT 8
#define TXRX_STATE_FSYNC_WIDTH 8
#define TXRX_STATE_FSYNC_MASK 0x0000FF00U
#define TXRX_STATE_FSYNC_SUCCESS 0x00000100U
#define TXRX_STATE_FSYNC_FAIL 0x00000200U

#define TXRX_STATE_DECODE_SHIFT 16
#define TXRX_STATE_DECODE_WIDTH 8
#define TXRX_STATE_DECODE_MASK 0x00FF0000U
#define TXRX_STATE_DECODE_SUCCESS 0x00010000U
#define TXRX_STATE_DECODE_FAIL 0x00020000U

#define TXRX_STATE_CRC_SHIFT 24
#define TXRX_STATE_CRC_WIDTH 8
#define TXRX_STATE_CRC_MASK 0xFF000000U
#define TXRX_STATE_CRC_OK 0x01000000U
#define TXRX_STATE_CRC_ERROR 0x02000000U

/**
 * Register: RECVDATA_STATE
 */
#define RECVDATA_STATE 0x00000028U
#define RECVDATA_STATE_LEN_SHIFT 0
#define RECVDATA_STATE_LEN_WIDTH 16
#define RECVDATA_STATE_LEN_MASK 0x0000FFFFU

#define RECVDATA_STATE_OFFSET_SHIFT 16
#define RECVDATA_STATE_OFFSET_WIDTH 16
#define RECVDATA_STATE_OFFSET_MASK 0xFFFF0000U

/**
 * Register: FSTIME_L
 */
#define FSTIME_L 0x0000002CU
#define FSTIME_L_SHIFT 0
#define FSTIME_L_WIDTH 32
#define FSTIME_L_MASK 0xFFFFFFFFU

/**
 * Register: FSTIME_INT1
 */
#define FSTIME_H 0x00000030U
#define FSTIME_H_SHIFT 0
#define FSTIME_H_WIDTH 32
#define FSTIME_H_MASK 0xFFFFFFFFU

/**
 * Register: TM_TARGET_L
 */
#define TM_TARGET_L 0x00000034U
#define TM_TARGET_L_SHIFT 0
#define TM_TARGET_L_WIDTH 32
#define TM_TARGET_L_MASK 0xFFFFFFFFU

/**
 * Register: TM_TARGET_H
 */
#define TM_TARGET_H 0x00000038U
#define TM_TARGET_H_SHIFT 0
#define TM_TARGET_H_WIDTH 32
#define TM_TARGET_H_MASK 0xFFFFFFFFU

/**
 * Register: COASEFREQEST
 */
#define COASE_FREQEST 0x0000003CU
#define COASE_FREQEST_ACQ_SHIFT 0
#define COASE_FREQEST_ACQ_WIDTH 8
#define COASE_FREQEST_ACQ_MASK 0x000000FFU
#define COASE_FREQEST_SYNC_SHIFT 8
#define COASE_FREQEST_SYNC_WIDTH 8
#define COASE_FREQEST_SYNC_MASK 0x0000FF00U
#define COASE_TYPE_SHIFT 16
#define COASE_TYPE_WIDTH 8
#define COASE_TYPE_MASK 0x00FF0000U
#define COASE_TYPE_ADV_24MS 0x00010000U
#define COASE_TYPE_ACK_8MS 0x00020000U
#define COASE_TYPE_128KBPS_4MS 0x00030000U
#define COASE_TYPE_512KBPS_4MS 0x00040000U
#define COASE_TYPE_2MBPS_4MS 0x00050000U

/**
 * Register: FINE_FREQEST
 */
#define FINE_FREQEST 0x00000040U
#define FINE_FREQEST_VAL_SHIFT 0
#define FINE_FREQEST_VAL_WIDTH 24
#define FINE_FREQEST_VAL_MASK 0x00FFFFFFU
#define FINE_FREQEST_SIGN_SHIFT 24
#define FINE_FREQEST_SIGN_WIDTH 8
#define FINE_FREQEST_SIGN_MASK 0xFF000000U
#define FINE_FREQEST_SIGN_POS 0x00000000U
#define FINE_FREQEST_SIGN_NEG 0x01000000U

/**
 * Register: ANT_SELECT
 */
#define ANT_SELECT_INDEX 0x00000044U
#define ANT_SELECT_INDEX_SHIFT 0
#define ANT_SELECT_INDEX_WIDTH 32
#define ANT_SELECT_INDEX_MASK 0xFFFFFFFFU

/**
 * Register: TX_MULFAC
 */
#define TX_MULFAC 0x00000048U
#define TX_MULFAC_SHIFT 0
#define TX_MULFAC_WIDTH 16
#define TX_MULFAC_MASK 0x0000FFFFU

/**
 * Register: ANT_STATUS_1
 */
#define ANT_STATUS_1 0x00000100U

#define ANT_STATUS_1_ANT1_STATUS_SHIFT 0
#define ANT_STATUS_1_ANT1_STATUS_WIDTH 16
#define ANT_STATUS_1_ANT1_STATUS_MASK 0x0000FFFFU

#define ANT_STATUS_1_ANT1_FREQ_SHIFT 0
#define ANT_STATUS_1_ANT1_FREQ_WIDTH 15
#define ANT_STATUS_1_ANT1_FREQ_MASK 0x00003FFFU

#define ANT_STATUS_1_ANT1_PLL_SHIFT 15
#define ANT_STATUS_1_ANT1_PLL_WIDTH 1
#define ANT_STATUS_1_ANT1_PLL_MASK 0x00008000U

#define ANT_STATUS_1_ANT2_STATUS_SHIFT 16
#define ANT_STATUS_1_ANT2_STATUS_WIDTH 16
#define ANT_STATUS_1_ANT2_STATUS_MASK 0x0000FFFFU

#define ANT_STATUS_1_ANT2_FREQ_SHIFT 16
#define ANT_STATUS_1_ANT2_FREQ_WIDTH 15
#define ANT_STATUS_1_ANT2_FREQ_MASK 0x3FFF0000U

#define ANT_STATUS_1_ANT2_PLL_SHIFT 31
#define ANT_STATUS_1_ANT2_PLL_WIDTH 1
#define ANT_STATUS_1_ANT2_PLL_MASK 0x80000000U

/**
 * Register: ANT_STATUS_2
 */
#define ANT_STATUS_2 0x00000104U

#define ANT_STATUS_2_ANT3_STATUS_SHIFT 0
#define ANT_STATUS_2_ANT3_STATUS_WIDTH 16
#define ANT_STATUS_2_ANT3_STATUS_MASK 0x0000FFFFU

#define ANT_STATUS_2_ANT3_FREQ_SHIFT 0
#define ANT_STATUS_2_ANT3_FREQ_WIDTH 15
#define ANT_STATUS_2_ANT3_FREQ_MASK 0x00003FFFU

#define ANT_STATUS_2_ANT3_PLL_SHIFT 15
#define ANT_STATUS_2_ANT3_PLL_WIDTH 1
#define ANT_STATUS_2_ANT3_PLL_MASK 0x00008000U

#define ANT_STATUS_2_PLL_LK_SHIFT 16
#define ANT_STATUS_2_PLL_LK_WIDTH 8
#define ANT_STATUS_2_PLL_LK_MASK 0x00FF0000U

#define ANT_STATUS_2_ANT3_PLL2_LK_SHIFT 16
#define ANT_STATUS_2_ANT3_PLL2_LK_WIDTH 1
#define ANT_STATUS_2_ANT3_PLL2_LK_MASK 0x00010000U

#define ANT_STATUS_2_ANT3_PLL1_LK_SHIFT 17
#define ANT_STATUS_2_ANT3_PLL1_LK_WIDTH 1
#define ANT_STATUS_2_ANT3_PLL1_LK_MASK 0x00020000U

#define ANT_STATUS_2_ANT2_PLL2_LK_SHIFT 18
#define ANT_STATUS_2_ANT2_PLL2_LK_WIDTH 1
#define ANT_STATUS_2_ANT2_PLL2_LK_MASK 0x00040000U

#define ANT_STATUS_2_ANT2_PLL1_LK_SHIFT 19
#define ANT_STATUS_2_ANT2_PLL1_LK_WIDTH 1
#define ANT_STATUS_2_ANT2_PLL1_LK_MASK 0x00080000U

#define ANT_STATUS_2_ANT1_PLL2_LK_SHIFT 20
#define ANT_STATUS_2_ANT1_PLL2_LK_WIDTH 1
#define ANT_STATUS_2_ANT1_PLL2_LK_MASK 0x00100000U

#define ANT_STATUS_2_ANT1_PLL1_LK_SHIFT 21
#define ANT_STATUS_2_ANT1_PLL1_LK_WIDTH 1
#define ANT_STATUS_2_ANT1_PLL1_LK_MASK 0x00200000U

#define ANT_STATUS_2_MODE_SHIFT 24
#define ANT_STATUS_2_MODE_WIDTH 8
#define ANT_STATUS_2_MODE_MASK 0xFF000000U

#define ANT_STATUS_2_ANT1_MODE_SHIFT 24
#define ANT_STATUS_2_ANT1_MODE_WIDTH 1
#define ANT_STATUS_2_ANT1_MODE_MASK 0x01000000U

#define ANT_STATUS_2_ANT2_MODE_SHIFT 25
#define ANT_STATUS_2_ANT2_MODE_WIDTH 1
#define ANT_STATUS_2_ANT2_MODE_MASK 0x02000000U

#define ANT_STATUS_2_ANT3_MODE_SHIFT 26
#define ANT_STATUS_2_ANT3_MODE_WIDTH 1
#define ANT_STATUS_2_ANT3_MODE_MASK 0x04000000U

/**
 * Register: ANT_STATUS_TEMP
 */
#define ANT_STATUS_TEMP 0x00000108U

#define ANT_STATUS_TEMP_SHIFT 0
#define ANT_STATUS_TEMP_WIDTH 8
#define ANT_STATUS_TEMP_MASK 0x000000FFU

#define ANT_STATUS_TEMP_RSVD_SHIFT 8
#define ANT_STATUS_TEMP_RSVD_WIDTH 8
#define ANT_STATUS_TEMP_RSVD_MASK 0x0000FF00U

/**
 * Register: PHY_ACQ_CNT
 */
#define PHY_ACQ_CNT 0x00000114U
#define PHY_ACQ_CNT_SHIFT 0
#define PHY_ACQ_CNT_WIDTH 32
#define PHY_ACQ_CNT_MASK 0xFFFFFFFFU

/**
 * Register: PHY_FRAME_SYNC_CNT
 */
#define PHY_FRAME_SYNC_CNT 0x00000118U
#define PHY_FRAME_SYNC_CNT_SHIFT 0
#define PHY_FRAME_SYNC_CNT_WIDTH 32
#define PHY_FRAME_SYNC_CNT_MASK 0xFFFFFFFFU

/**
 * Register: PHY_DECODE_CNT
 */
#define PHY_DECODE_CNT 0x0000011CU
#define PHY_DECODE_CNT_SHIFT 0
#define PHY_DECODE_CNT_WIDTH 32
#define PHY_DECODE_CNT_MASK 0xFFFFFFFFU

/**
 * Register: PHY_CRC_OK_CNT
 */
#define PHY_CRC_OK_CNT 0x00000120U
#define PHY_CRC_OK_CNT_SHIFT 0
#define PHY_CRC_OK_CNT_WIDTH 32
#define PHY_CRC_OK_CNT_MASK 0xFFFFFFFFU

/**
 * Register: PHY_ACQ_PEAK_H
 */
#define PHY_ACQ_PEAK_H 0x00000124U
#define PHY_ACQ_PEAK_H_SHIFT 0
#define PHY_ACQ_PEAK_H_WIDTH 32
#define PHY_ACQ_PEAK_H_MASK 0xFFFFFFFFU

/**
 * Register: PHY_ACQ_PEAK_L
 */
#define PHY_ACQ_PEAK_L 0x00000128U
#define PHY_ACQ_PEAK_L_SHIFT 0
#define PHY_ACQ_PEAK_L_WIDTH 32
#define PHY_ACQ_PEAK_L_MASK 0xFFFFFFFFU


/**
 * Register: PHY_ACQ_MEAN_H
 */
#define PHY_ACQ_MEAN_H 0x0000012CU
#define PHY_ACQ_MEAN_H_SHIFT 0
#define PHY_ACQ_MEAN_H_WIDTH 32
#define PHY_ACQ_MEAN_H_MASK 0xFFFFFFFFU

/**
 * Register: PHY_ACQ_MEAN_L
 */
#define PHY_ACQ_MEAN_L 0x00000130U
#define PHY_ACQ_MEAN_L_SHIFT 0
#define PHY_ACQ_MEAN_L_WIDTH 32
#define PHY_ACQ_MEAN_L_MASK 0xFFFFFFFFU

/**
 * Register: PHY_ACQ_FREQEST
 */
#define PHY_ACQ_FREQEST 0x00000134U
#define PHY_ACQ_FREQEST_SHIFT 0
#define PHY_ACQ_FREQEST_WIDTH 32
#define PHY_ACQ_FREQEST_MASK 0xFFFFFFFFU

#define PHY_ACQ_FREQEST_PHASE_SHIFT 0
#define PHY_ACQ_FREQEST_PHASE_WIDTH 8
#define PHY_ACQ_FREQEST_PHASE_MASK 0x000000FFU
#define PHY_ACQ_FREQEST_CHANNEL_SHIFT 8
#define PHY_ACQ_FREQEST_CHANNEL_WIDTH 8
#define PHY_ACQ_FREQEST_CHANNEL_MASK 0x0000FF00U

/**
 * Register: PHY_FRAME_SYNC_PEAK_H
 */
#define PHY_FRAME_SYNC_PEAK_H 0x00000138U
#define PHY_FRAME_SYNC_PEAK_H_SHIFT 0
#define PHY_FRAME_SYNC_PEAK_H_WIDTH 32
#define PHY_FRAME_SYNC_PEAK_H_MASK 0xFFFFFFFFU

/**
 * Register: PHY_FRAME_SYNC_PEAK_L
 */
#define PHY_FRAME_SYNC_PEAK_L 0x0000013CU
#define PHY_FRAME_SYNC_PEAK_L_SHIFT 0
#define PHY_FRAME_SYNC_PEAK_L_WIDTH 32
#define PHY_FRAME_SYNC_PEAK_L_MASK 0xFFFFFFFFU


/**
 * Register: PHY_FRAME_SYNC_MEAN_H
 */
#define PHY_FRAME_SYNC_MEAN_H 0x00000140U
#define PHY_FRAME_SYNC_MEAN_H_SHIFT 0
#define PHY_FRAME_SYNC_MEAN_H_WIDTH 32
#define PHY_FRAME_SYNC_MEAN_H_MASK 0xFFFFFFFFU

/**
 * Register: PHY_FRAME_SYNC_MEAN_L
 */
#define PHY_FRAME_SYNC_MEAN_L 0x00000144U
#define PHY_FRAME_SYNC_MEAN_L_SHIFT 0
#define PHY_FRAME_SYNC_MEAN_L_WIDTH 32
#define PHY_FRAME_SYNC_MEAN_L_MASK 0xFFFFFFFFU

/**
 * Register: PHY_FRAME_SYNC_FREQEST
 */
#define PHY_FRAME_SYNC_FREQEST 0x00000148U
#define PHY_FRAME_SYNC_FREQEST_SHIFT 0
#define PHY_FRAME_SYNC_FREQEST_WIDTH 32
#define PHY_FRAME_SYNC_FREQEST_MASK 0xFFFFFFFFU

#define PHY_FRAME_SYNC_FREQEST_CHANNEL_SHIFT 0
#define PHY_FRAME_SYNC_FREQEST_CHANNEL_WIDTH 8
#define PHY_FRAME_SYNC_FREQEST_CHANNEL_MASK 0x000000FFU

/**
 * Register: PHY_DEINTLV_AMPEST
 */
#define PHY_DEINTLV_AMPEST 0x0000014CU
#define PHY_DEINTLV_AMPEST_SHIFT 0
#define PHY_DEINTLV_AMPEST_WIDTH 16
#define PHY_DEINTLV_AMPEST_MASK 0x0000FFFFU

#endif /* PHY_REG_H_ */

/** @} PhysicalLayer_REG_Constants*/

/** @} PhysicalLayer*/