/*****************************************************************************/
/**
 * @file phy_layer.c
 * @author FanHao (hao_fan_bit_ee@163.com)
 * @brief Physical layer control header file.
 * @version 0.0
 * @date 2023-04-24
 *
 * @copyright Copyright(c) 2024 Beijing Institute of Technology.\n
 * Lab of Communication and Network
 *
 ******************************************************************************/

/**
 * @defgroup PhysicalLayer
 * @{
 */

#ifndef PHY_CTRL_H_
#define PHY_CTRL_H_

/***************************** Include Files *********************************/
#include <stdint.h>
#include "common.h"
#ifndef EMULATION
#include "xbram.h"
#ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+)
#include "xsysmon.h"
#else
#include "xadcps.h"
#endif
#include "../config/app_config.h"
#endif
#include "../../system_monitor.h"
#include "../../time_ctrl/time_ctrl.h"
/************************** Constant Definitions *****************************/
/**
 * @name PhysicalLayer_Common_Constant
 * @{
 */
#define L1_ANT_NUM 3U // 1 beam per antenna, and 3 antennas in total
#define L1_ANT_CH_NUM 4U // channel number per antenna
#define L1_INIT_ANT_IDX 0U

#define L1_FRAME_NONE_LEN UINT32_MAX  // byte
#define L1_FRAME_NONE_COMP UINT32_MAX // *10ns(Timer_L)
#define L1_FRAME_NONE_HOPS UINT32_MAX
#define L1_FRAME_MAX_HOPS 81
#define L1_FRAME_ADV_24MS_HOPS 16U // sync 16 ms + data 8 ms, 2000 hops/s
#define L1_FRAME_ACK_8MS_HOPS 4U // sync 6 ms + data 2 ms, 2000 hops/s
#define L1_FRAME_128KBPS_4MS_HOPS 33U
#define L1_FRAME_512KBPS_4MS_HOPS 36U
#define L1_FRAME_2MBPS_4MS_HOPS 38U
#define PHY_LOG_EXPIRE 50U // number of 2 ms slot
/** @} */
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/**
 * @enum L1_FRAME_TYPE
 */
typedef enum
{
	L1_FRAME_NONE		 = 0,
	L1_FRAME_ADV_24MS	 = 1,
	L1_FRAME_ACK_8MS	 = 2,
	L1_FRAME_128KBPS_4MS = 3, // 128kbps
	L1_FRAME_512KBPS_4MS = 4, // 512kbps
	L1_FRAME_2MBPS_4MS	 = 5  // 2 Mbps
} L1_FRAME_TYPE;

/**
 * @struct PHY_ANT_CONFIG
 * @brief PhysicalLayer antenna config
 */
typedef struct
{
	/*** Antenna & RF Control ***/
	uint8_t rfNormComp[L1_ANT_NUM][L1_ANT_CH_NUM];
						///< Normal mode RF phase compensation, 3 antennas
						/// and 4 channels each: 0~63, 5.625° step
	uint8_t rfNormIdpAttn[L1_ANT_NUM][L1_ANT_CH_NUM];
						///< Normal mode RF attenuation for independent channel:
						/// 0~30 dB, 1dB step
	uint8_t rfNormComAttn[L1_ANT_NUM];
						///< Normal mode RF attenuation for combined channel:
						/// 0~30 dB, 1dB step
	struct
	{
	  uint8_t antMode : 1; 	/// [0]: Anti-jamming mode control, 1 - enable, 0 - disable
							///      only one antenna can be selected in anti-jamming mode
	  uint8_t antRx1En : 1; /// [1]: Anti-jamming antenna 1 select, 1 - enable, 0 - disable
	  uint8_t antRx2En : 1; /// [2]: Anti-jamming antenna 2 select, 1 - enable, 0 - disable
	  uint8_t antRx3En : 1; /// [3]: Anti-jamming antenna 3 select, 1 - enable, 0 - disable
	  uint8_t antTx1En : 1;	/// [4]: Antenna 1 tx control, 1 - enable, 0 - disable
	  uint8_t antTx2En : 1;	/// [5]: Antenna 2 tx control, 1 - enable, 0 - disable
	  uint8_t antTx3En : 1;	/// [6]: Antenna 3 tx control, 1 - enable, 0 - disable
	  uint8_t antRsvd : 1;	/// [7]: reserved
	} antControl;

	uint8_t rfAntiAttn[L1_ANT_CH_NUM];
						///< Anti-jamming mode RF attenuation, 4 channels:
						/// 0~60 dB, 1dB step
	uint8_t rfFreq[L1_ANT_NUM][2];
						///< RF synthesizer ping-pong frequency, 3 antennas
						/// and 2 byte each: 0~600 MHz, step 1MHz, with base
						/// frequency of 3700 MHz
	uint8_t rfRsvd; 	///< reserved for further use
} PHY_ANT_CONFIG;

/**
 * @enum PHY_TIME_WORD_TYPE
 */
typedef enum
{
	PHY_TIME_WORD_NONE = 0,
	PHY_TIME_WORD_POLL = 1,
	PHY_TIME_WORD_LISTEN_TIMEOUT = 2
} PHY_TIME_WORD_TYPE;

/**
 * @enum PHY_TOR_TYPE
 */
typedef enum
{
	PHY_TOR_SUSPEND = 0,
	PHY_TOR_TX = 1,
	PHY_TOR_RX = 2
} PHY_TOR_TYPE;

/**
 * @enum PHY_MODE
 */
typedef enum
{
	PHY_MODE_NONE = 0,
	PHY_MODE_LISTEN = 1,
	PHY_MODE_POLL = 2
} PHY_MODE;

/**
 * @enum PHY_ANT_MODE
 */
typedef enum
{
	PHY_ANT_MODE_NONE = 0,
	PHY_ANT_MODE_STANDBY = 1,
	PHY_ANT_MODE_NORMAL = 2,
	PHY_ANT_MODE_ANTI_JAM = 3
} PHY_ANT_MODE;

/**
 * @enum PHY_ANT_RX_MODE
 */
typedef enum
{
	PHY_ANT_RX_MODE_NORMAL = 0,
	PHY_ANT_RX_MODE_AJ = 1
} PHY_ANT_RX_MODE;

/**
 * @enum PHY_ANT_INDEX
 */
typedef enum
{
	PHY_ANT_INDEX_NONE = 0,
	PHY_ANT_INDEX_1 = 1,
	PHY_ANT_INDEX_2 = 2,
	PHY_ANT_INDEX_3 = 3
} PHY_ANT_INDEX;

/**
 * @struct PHY_RCD
 * @brief Physical Layer recode buffer
 */
typedef struct
{
	int32_t last;
	int32_t curr;
	int32_t next;
} PHY_RCD;

/**
 * @struct PHY_CONFIG
 * @brief struct holds all physical layer initialization parameters
 */
typedef struct
{
	uint32_t devId;			///< device ID
	uint32_t txBramId;		///< tx bram ID
	uint32_t rxBramId;		///< rx bram ID
	uint32_t antBramId;		///< antenna config bram ID
#ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+)
	uint32_t hwSysmonId;	///< hardware system monitor device ID
#else
	uint32_t hwXadcId;		///< hardware xadc device ID
#endif
	uintptr_t baseAddr;		///< Physical layer controller base address
#ifndef EMULATION
	uint8_t (*get_clk_state)(void);		///< function handle returns hardware clock state
	uint8_t (*get_ad_lock_state)(void); ///< function handle returns adc lock state
	int8_t (*get_ad0_temp)(void);		///< function handle returns adc0 temperature state
	int8_t (*get_ad1_temp)(void);		///< function handle returns adc1 temperature state
#endif
} PHY_CONFIG;

/**
 * @struct PHY_INST
 * @brief Physical Layer operating instance
 */
typedef struct
{
	PHY_CONFIG phyCofig;	  ///< physical layer configuration parameters
	uintptr_t recvDataAddr;	  ///< receive data bram address
	uintptr_t sendDataAddr;	  ///< send data bram address
	uintptr_t antConfigAddr;  ///< antenna config data bram address
	bool isPhyEn;			  ///< indicates if physical layer running
	bool isAcq;				  ///< indicates if last reception acquisition success
	bool isFrameSync;		  ///< indicates if last reception frame sync success
	bool isDecode;			  ///< indicates if last reception decode success
	bool isValid;			  ///< indicates if last reception frame data valid (crc check pass)
	TIME_WORD recvSlotTime;	  ///< last slot start time stamp
	TIME_WORD recvFsTime;	  ///< last frame sync time stamp
	PHY_RCD antIndex;		  ///< antenna number record
	PHY_RCD tor;			  ///< tx rx state record
	PHY_RCD frameType;		  ///< frame type record
	uint32_t sendDataOffset;  ///< antenna configuration bram offset (to implement ping-pong data flow)
	uint32_t antConfigOffset; ///< antenna configuration bram offset (to implement ping-pong data flow)
	PHY_ANT_CONFIG antConfig; ///< antenna configuration pointer
#ifndef EMULATION
#ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+)
	XSysMon sysMon; ///< System monitor
#else
	XAdcPs hwXadc; ///< hardware Xadc instance
#endif
#endif
	HWSTATE hwSate;									  ///< hardware state log
	PHYLOG phyLog;									  ///< physical state log
	uint32_t lastLogTime;							  /// physical state log time stamp
} PHY_INST;

/************************** Function Prototypes ******************************/

/**
 * @defgroup PhysicalLayer_Main
 * @{
 */
int32_t Phy_Init(PHY_INST **instPtr, PHY_CONFIG *phyConfig);
void Phy_Destroy(PHY_INST *instPtr);
void Phy_Start(PHY_INST *instPtr);
void Phy_Halt(PHY_INST *instPtr);

int32_t Phy_SetMode(PHY_INST *instPtr, PHY_MODE modeCod);
int32_t Phy_SetTimeWord(PHY_INST *instPtr, const TIME_WORD *tmWord, PHY_TIME_WORD_TYPE tmType);
int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode, L1_FRAME_TYPE frameType, uint8_t *dataBuff);
void Phy_UpdateState(PHY_INST *instPtr);
void Phy_PeekRecvData(PHY_INST *instPtr, uint8_t *dataBuff);
void Phy_RetrieveRecvData(PHY_INST *instPtr, uint8_t *dataBuff);
void Phy_UpdateLogging(PHY_INST *instPtr);
void Phy_RefreshHwSate(PHY_INST *instPtr);
/** @} PhysicalLayer_Main*/

/**
 * @defgroup PhysicalLayer_Utility
 * @{
 */
bool Phy_IsFrameDetected(PHY_INST *instPtr);
bool Phy_IsFrameReceived(PHY_INST *instPtr);
bool Phy_IsFrameValid(PHY_INST *instPtr);
uint32_t Phy_GetFrameLen(L1_FRAME_TYPE frameType);
uint32_t Phy_GetHopLength(L1_FRAME_TYPE frameType);
uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType);
L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr);
L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST *instPtr);
/** @} PhysicalLayer_Utility*/

/**
 * @defgroup PhysicalLayer_Receive_Estimations
 * @{
 */
uint8_t Phy_ReceiveAntIndex(PHY_INST *instPtr);
double Phy_GetFreqEst(PHY_INST *instPtr);
double Phy_GetCoarseFreqEst(PHY_INST *instPtr);
double Phy_GetFineFreqEst(PHY_INST *instPtr);
void Phy_GetFrameSyncTimeStamp(PHY_INST *instPtr, TIME_WORD *frameSyncT);
void Phy_GetLastReceivedFrameSyncTimeStamp(PHY_INST *instPtr, TIME_WORD *frameSyncT);
void Phy_GetSlotStartTimeStamp(PHY_INST *instPtr, TIME_WORD *slotStart);
void Phy_GetLastReceivedSlotStartTimeStamp(PHY_INST *instPtr, TIME_WORD *slotStart);
/** @} PhysicalLayer_Receive_Estimations*/

/**
 * @defgroup PhysicalLayer_AntennaControl
 * @{
 */
void Phy_AntConfigInit(PHY_ANT_CONFIG *antConfig);
void Phy_SetTxAntIndex(PHY_INST *instPtr, PHY_ANT_INDEX antIndex);
void Phy_SetRxAntIndex(PHY_INST *instPtr, PHY_ANT_INDEX antRxIndex);
void Phy_SetRxMode(PHY_INST *instPtr, PHY_ANT_RX_MODE antRxMode);
int32_t Phy_SetAntIndex(PHY_INST *instPtr, PHY_ANT_INDEX antIndex);
size_t Phy_GetNextAntIndex(PHY_INST *instPtr);
/** @} PhysicalLayer_AntennaControl*/

#endif // PHY_CTRL_H_

/** @} PhysicalLayer*/