forked from gatsby/df_datalink
305 lines
9.3 KiB
C
305 lines
9.3 KiB
C
/*****************************************************************************/
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/**
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* @file phy_layer.c
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* @author FanHao ([email protected])
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* @brief Physical layer control header file.
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* @version 0.0
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* @date 2023-04-24
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*
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* @copyright Copyright(c) 2024 Beijing Institute of Technology.\n
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* Lab of Communication and Network
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*
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******************************************************************************/
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/**
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* @defgroup PhysicalLayer
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* @{
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*/
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#ifndef PHY_CTRL_H_
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#define PHY_CTRL_H_
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/***************************** Include Files *********************************/
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#include <stdint.h>
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#include "common.h"
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#ifndef EMULATION
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#include "xbram.h"
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#include "../config/app_config.h"
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#ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+)
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#include "xsysmon.h"
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#else
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#include "xadcps.h"
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#endif
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#endif
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#include "../../system_monitor.h"
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#include "../../time_ctrl/time_ctrl.h"
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/************************** Constant Definitions *****************************/
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/**
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* @name PhysicalLayer_Common_Constant
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* @{
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*/
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#define L1_ANT_NUM 3U // 1 beam per antenna, and 3 antennas in total
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#define L1_ANT_CH_NUM 4U // channel number per antenna
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#define L1_INIT_ANT_IDX 0U
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#define L1_FRAME_NONE_LEN UINT32_MAX // byte
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#define L1_FRAME_NONE_COMP UINT32_MAX // *10ns(Timer_L)
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#define L1_FRAME_NONE_HOPS UINT32_MAX
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#define L1_FRAME_MAX_HOPS 81
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#define L1_FRAME_ADV_24MS_HOPS 17U // sync 16 ms + data 8 ms, 2000 hops/s
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#define L1_FRAME_ACK_8MS_HOPS 5U // sync 6 ms + data 2 ms, 2000 hops/s
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#define L1_FRAME_128KBPS_4MS_HOPS 33U
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#define L1_FRAME_512KBPS_4MS_HOPS 36U
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#define L1_FRAME_2MBPS_4MS_HOPS 38U
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#define PHY_LOG_EXPIRE 50U // number of 2 ms slot
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/** @} */
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/***************** Macros (Inline Functions) Definitions *********************/
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/**************************** Type Definitions *******************************/
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/**
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* @enum L1_FRAME_TYPE
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*/
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typedef enum
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{
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L1_FRAME_NONE = 0,
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L1_FRAME_ADV_24MS = 1,
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L1_FRAME_ACK_8MS = 2,
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L1_FRAME_128KBPS_4MS = 3, // 128kbps
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L1_FRAME_512KBPS_4MS = 4, // 512kbps
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L1_FRAME_2MBPS_4MS = 5 // 2 Mbps
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} L1_FRAME_TYPE;
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/**
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* @struct PHY_ANT_CONFIG
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* @brief PhysicalLayer antenna config
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*/
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typedef struct
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{
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/*** Antenna & RF Control ***/
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uint8_t rfNormComp[L1_ANT_NUM][L1_ANT_CH_NUM];
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///< Normal mode RF phase compensation, 3 antennas
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/// and 4 channels each: 0~63, 5.625° step
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uint8_t rfNormIdpAttn[L1_ANT_NUM][L1_ANT_CH_NUM];
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///< Normal mode RF attenuation for independent channel:
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/// 0~30 dB, 1dB step
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uint8_t rfNormComAttn[L1_ANT_NUM];
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///< Normal mode RF attenuation for combined channel:
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/// 0~30 dB, 1dB step
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struct
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{
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uint8_t antMode : 1; /// [0]: Anti-jamming mode control, 1 - enable, 0 - disable
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/// only one antenna can be selected in anti-jamming mode
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uint8_t antRx1En : 1; /// [1]: Anti-jamming antenna 1 select, 1 - enable, 0 - disable
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uint8_t antRx2En : 1; /// [2]: Anti-jamming antenna 2 select, 1 - enable, 0 - disable
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uint8_t antRx3En : 1; /// [3]: Anti-jamming antenna 3 select, 1 - enable, 0 - disable
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uint8_t antTx1En : 1; /// [4]: Antenna 1 tx control, 1 - enable, 0 - disable
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uint8_t antTx2En : 1; /// [5]: Antenna 2 tx control, 1 - enable, 0 - disable
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uint8_t antTx3En : 1; /// [6]: Antenna 3 tx control, 1 - enable, 0 - disable
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uint8_t antRsvd : 1; /// [7]: reserved
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} antControl;
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uint8_t rfAntiAttn[L1_ANT_CH_NUM];
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///< Anti-jamming mode RF attenuation, 4 channels:
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/// 0~60 dB, 1dB step
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uint8_t rfFreq[L1_ANT_NUM][2];
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///< RF synthesizer ping-pong frequency, 3 antennas
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/// and 2 byte each: 0~600 MHz, step 1MHz, with base
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/// frequency of 3700 MHz
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uint16_t rfRsvd; ///< reserved for further use
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} PHY_ANT_CONFIG;
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/**
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* @enum PHY_TIME_WORD_TYPE
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*/
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typedef enum
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{
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PHY_TIME_WORD_NONE = 0,
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PHY_TIME_WORD_POLL = 1,
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PHY_TIME_WORD_LISTEN_TIMEOUT = 2
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} PHY_TIME_WORD_TYPE;
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/**
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* @enum PHY_TOR_TYPE
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*/
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typedef enum
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{
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PHY_TOR_SUSPEND = 0,
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PHY_TOR_TX = 1,
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PHY_TOR_RX = 2
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} PHY_TOR_TYPE;
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/**
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* @enum PHY_MODE
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*/
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typedef enum
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{
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PHY_MODE_NONE = 0,
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PHY_MODE_LISTEN = 1,
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PHY_MODE_POLL = 2
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} PHY_MODE;
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/**
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* @enum PHY_ANT_MODE
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*/
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typedef enum
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{
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PHY_ANT_MODE_NONE = 0,
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PHY_ANT_MODE_STANDBY = 1,
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PHY_ANT_MODE_NORMAL = 2,
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PHY_ANT_MODE_ANTI_JAM = 3
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} PHY_ANT_MODE;
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/**
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* @enum PHY_ANT_RX_MODE
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*/
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typedef enum
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{
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PHY_ANT_RX_MODE_NORMAL = 0,
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PHY_ANT_RX_MODE_AJ = 1
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} PHY_ANT_RX_MODE;
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/**
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* @enum PHY_ANT_INDEX
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*/
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typedef enum
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{
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PHY_ANT_INDEX_NONE = 0,
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PHY_ANT_INDEX_1 = 1,
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PHY_ANT_INDEX_2 = 2,
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PHY_ANT_INDEX_3 = 3
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} PHY_ANT_INDEX;
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/**
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* @struct PHY_RCD
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* @brief Physical Layer recode buffer
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*/
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typedef struct
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{
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int32_t last;
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int32_t curr;
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int32_t next;
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} PHY_RCD;
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/**
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* @struct PHY_CONFIG
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* @brief struct holds all physical layer initialization parameters
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*/
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typedef struct
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{
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uint32_t devId; ///< device ID
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uint32_t txBramId; ///< tx bram ID
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uint32_t rxBramId; ///< rx bram ID
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uint32_t antBramId; ///< antenna config bram ID
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#ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+)
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uint32_t hwSysmonId; ///< hardware system monitor device ID
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#else
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uint32_t hwXadcId; ///< hardware xadc device ID
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#endif
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uintptr_t baseAddr; ///< Physical layer controller base address
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#ifndef EMULATION
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uint8_t (*get_clk_state)(void); ///< function handle returns hardware clock state
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uint8_t (*get_ad_lock_state)(void); ///< function handle returns adc lock state
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int8_t (*get_ad0_temp)(void); ///< function handle returns adc0 temperature state
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int8_t (*get_ad1_temp)(void); ///< function handle returns adc1 temperature state
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#endif
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} PHY_CONFIG;
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/**
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* @struct PHY_INST
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* @brief Physical Layer operating instance
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*/
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typedef struct
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{
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PHY_CONFIG phyCofig; ///< physical layer configuration parameters
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uintptr_t recvDataAddr; ///< receive data bram address
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uintptr_t sendDataAddr; ///< send data bram address
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uintptr_t antConfigAddr; ///< antenna config data bram address
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bool isPhyEn; ///< indicates if physical layer running
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bool isAcq; ///< indicates if last reception acquisition success
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bool isFrameSync; ///< indicates if last reception frame sync success
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bool isDecode; ///< indicates if last reception decode success
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bool isValid; ///< indicates if last reception frame data valid (crc check pass)
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TIME_WORD recvSlotTime; ///< last slot start time stamp
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TIME_WORD recvFsTime; ///< last frame sync time stamp
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PHY_RCD antIndex; ///< antenna number record
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PHY_RCD tor; ///< tx rx state record
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PHY_RCD frameType; ///< frame type record
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uint32_t sendDataOffset; ///< antenna configuration bram offset (to implement ping-pong data flow)
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uint32_t antConfigOffset; ///< antenna configuration bram offset (to implement ping-pong data flow)
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PHY_ANT_CONFIG antConfig; ///< antenna configuration pointer
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#ifndef EMULATION
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#ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+)
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XSysMon sysMon; ///< System monitor
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#else
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XAdcPs hwXadc; ///< hardware Xadc instance
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#endif
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#endif
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HWSTATE hwSate; ///< hardware state log
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PHYLOG phyLog; ///< physical state log
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uint32_t lastLogTime; /// physical state log time stamp
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} PHY_INST;
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/************************** Function Prototypes ******************************/
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/**
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* @defgroup PhysicalLayer_Main
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* @{
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*/
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int32_t Phy_Init(PHY_INST **instPtr, PHY_CONFIG *phyConfig);
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void Phy_Destroy(PHY_INST *instPtr);
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void Phy_Start(PHY_INST *instPtr);
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void Phy_Halt(PHY_INST *instPtr);
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int32_t Phy_SetMode(PHY_INST *instPtr, PHY_MODE modeCod);
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int32_t Phy_SetTimeWord(PHY_INST *instPtr, const TIME_WORD *tmWord, PHY_TIME_WORD_TYPE tmType);
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int32_t Phy_SetupNextSlot(PHY_INST *instPtr, PHY_TOR_TYPE txrxMode, L1_FRAME_TYPE frameType, uint8_t *dataBuff);
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void Phy_UpdateState(PHY_INST *instPtr);
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void Phy_PeekRecvData(PHY_INST *instPtr, uint8_t *dataBuff);
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void Phy_RetrieveRecvData(PHY_INST *instPtr, uint8_t *dataBuff);
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void Phy_UpdateLogging(PHY_INST *instPtr);
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void Phy_RefreshHwSate(PHY_INST *instPtr);
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/** @} PhysicalLayer_Main*/
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/**
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* @defgroup PhysicalLayer_Utility
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* @{
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*/
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bool Phy_IsFrameDetected(PHY_INST *instPtr);
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bool Phy_IsFrameReceived(PHY_INST *instPtr);
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bool Phy_IsFrameValid(PHY_INST *instPtr);
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uint32_t Phy_GetFrameLen(L1_FRAME_TYPE frameType);
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uint32_t Phy_GetHopLength(L1_FRAME_TYPE frameType);
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uint32_t Phy_GetTimeComp(L1_FRAME_TYPE frameType);
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L1_FRAME_TYPE Phy_GetLastRecvFrameType(PHY_INST *instPtr);
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L1_FRAME_TYPE Phy_GetLastSendFrameType(PHY_INST *instPtr);
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/** @} PhysicalLayer_Utility*/
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/**
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* @defgroup PhysicalLayer_Receive_Estimations
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* @{
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*/
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uint8_t Phy_ReceiveAntIndex(PHY_INST *instPtr);
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double Phy_GetFreqEst(PHY_INST *instPtr);
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double Phy_GetCoarseFreqEst(PHY_INST *instPtr);
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double Phy_GetFineFreqEst(PHY_INST *instPtr);
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void Phy_GetFrameSyncTimeStamp(PHY_INST *instPtr, TIME_WORD *frameSyncT);
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void Phy_GetLastReceivedFrameSyncTimeStamp(PHY_INST *instPtr, TIME_WORD *frameSyncT);
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void Phy_GetSlotStartTimeStamp(PHY_INST *instPtr, TIME_WORD *slotStart);
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void Phy_GetLastReceivedSlotStartTimeStamp(PHY_INST *instPtr, TIME_WORD *slotStart);
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/** @} PhysicalLayer_Receive_Estimations*/
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/**
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* @defgroup PhysicalLayer_AntennaControl
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* @{
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*/
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void Phy_AntConfigInit(PHY_ANT_CONFIG *antConfig);
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void Phy_SetTxAntIndex(PHY_INST *instPtr, PHY_ANT_INDEX antIndex);
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void Phy_SetRxAntIndex(PHY_INST *instPtr, PHY_ANT_INDEX antRxIndex);
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void Phy_SetRxMode(PHY_INST *instPtr, PHY_ANT_RX_MODE antRxMode);
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int32_t Phy_SetAntIndex(PHY_INST *instPtr, PHY_ANT_INDEX antIndex);
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size_t Phy_GetNextAntIndex(PHY_INST *instPtr);
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/** @} PhysicalLayer_AntennaControl*/
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#endif // PHY_CTRL_H_
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/** @} PhysicalLayer*/
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