diff --git a/_config.yml b/_config.yml index 8c4918f..75090bc 100644 --- a/_config.yml +++ b/_config.yml @@ -90,9 +90,9 @@ time_format: HH:mm:ss ## updated_option supports 'mtime', 'date', 'empty' updated_option: 'mtime' -# Pagination +# Archive Pagination ## Set per_page to 0 to disable pagination -per_page: 10 +per_page: 15 pagination_dir: page # Include / Exclude file(s) diff --git a/package-lock.json b/package-lock.json index 655b5f7..863f898 100644 --- a/package-lock.json +++ b/package-lock.json @@ -9,7 +9,7 @@ "version": "0.0.0", "dependencies": { "@next-theme/plugins": "^8.19.1", - "hexo": "^7.0.0", + "hexo": "^7.1.0", "hexo-abbrlink": "^2.2.1", "hexo-deployer-git": "^4.0.0", "hexo-filter-github-emojis": "^3.0.5", @@ -24,7 +24,7 @@ "hexo-related-posts": "^1.5.1", "hexo-renderer-ejs": "^2.0.0", "hexo-renderer-pandoc": "^0.4.0", - "hexo-renderer-stylus": "^3.0.0", + "hexo-renderer-stylus": "^3.0.1", "hexo-server": "^3.0.0", "hexo-tag-cloud": "2.1.*", "hexo-theme-landscape": "^1.0.0", @@ -33,9 +33,9 @@ } }, "node_modules/@adobe/css-tools": { - "version": "4.2.0", - "resolved": "https://registry.npmjs.org/@adobe/css-tools/-/css-tools-4.2.0.tgz", - "integrity": "sha512-E09FiIft46CmH5Qnjb0wsW54/YQd69LsxeKUOWawmws1XWvyFGURnAChH0mlr7YPFR1ofwvUQfcL0J3lMxXqPA==" + "version": "4.3.2", + "resolved": "https://registry.npmjs.org/@adobe/css-tools/-/css-tools-4.3.2.tgz", + "integrity": "sha512-DA5a1C0gD/pLOvhv33YMrbf2FK3oUzwNl9oOJqE4XVjuEtt6XIakRcsd7eLiOSPkp1kTRQGICTA8cKra/vFbjw==" }, "node_modules/@algolia/cache-browser-local-storage": { "version": "4.20.0", @@ -4320,9 +4320,9 @@ "integrity": "sha512-2bsegYkkHO+h/9MGbn6KWcE45cHZgPANo5LXF7EvWdT0yT2EguSVO1nDgU5c8+ZOPwp2vMNa7YFsJhVcDR9Sdg==" }, "node_modules/hexo": { - "version": "7.0.0", - "resolved": "https://registry.npmjs.org/hexo/-/hexo-7.0.0.tgz", - "integrity": "sha512-3iRSYReDcYd+bdCrDYS53aFjR717M+eSwKVXdM1tF2QETi8urcwDdDDoD7Nm2E0trqN4oeoHJ7FoXbn2UsZxqw==", + "version": "7.1.0", + "resolved": "https://registry.npmjs.org/hexo/-/hexo-7.1.0.tgz", + "integrity": "sha512-FFjo8NwqSQVxASSKFGkFUak720sFC/p3IxkDIOHLXQ1axQ5w4ipFU0DNqDzwyb5EJOMFYuMxFcurhm9olQP13A==", "dependencies": { "abbrev": "^2.0.0", "archy": "^1.0.0", @@ -5215,12 +5215,12 @@ "integrity": "sha512-e913A2EZbhwbIfg+QvYUalEPHtK5qs9Rqj3ZrsQ3cYTbbiETMWhUQ7bzSlgUeh639eL0UDuBmv2vrEqj5RBchg==" }, "node_modules/hexo-renderer-stylus": { - "version": "3.0.0", - "resolved": "https://registry.npmjs.org/hexo-renderer-stylus/-/hexo-renderer-stylus-3.0.0.tgz", - "integrity": "sha512-wgKOcjUzq1i4Y70luoyYDbh91QeQcDzJO+v1598LgY+IdREFAm+vy1MWtl/TZsVXyPaEtsULNi3Vi22hdsPUSA==", + "version": "3.0.1", + "resolved": "https://registry.npmjs.org/hexo-renderer-stylus/-/hexo-renderer-stylus-3.0.1.tgz", + "integrity": "sha512-cFm8ZwShBBeFcQwOXc8EK7lIZnSYVD6OJykdL4GBw99hxc4eD5Hlsi32nRzE8sgKv00jhX1s9Da3GVVFMPAVQg==", "dependencies": { "nib": "^1.2.0", - "stylus": "^0.59.0" + "stylus": "^0.62.0" }, "engines": { "node": ">=14" @@ -10222,9 +10222,9 @@ "integrity": "sha512-YZo3K82SD7Riyi0E1EQPojLz7kpepnSQI9IyPbHHg1XXXevb5dJI7tpyN2ADxGcQbHG7vcyRHk0cbwqcQriUtg==" }, "node_modules/sax": { - "version": "1.2.4", - "resolved": "https://registry.npmmirror.com/sax/-/sax-1.2.4.tgz", - "integrity": "sha512-NqVDv9TpANUjFm0N8uM5GxL36UgKi9/atZw+x7YFnQ8ckwFGKrl4xX4yWtrey3UJm5nP1kUbnYgLopqWNSRhWw==" + "version": "1.3.0", + "resolved": "https://registry.npmjs.org/sax/-/sax-1.3.0.tgz", + "integrity": "sha512-0s+oAmw9zLl1V1cS9BtZN7JAd0cW5e0QH4W3LWEK6a4LaLEA2OTpGYWDY+6XasBLtz6wkm3u1xRw95mRuJ59WA==" }, "node_modules/scheduler": { "version": "0.19.1", @@ -10895,14 +10895,14 @@ "integrity": "sha512-EQepAV+wMsIaGVGX1RECzgrcqRRU/0sYOHkeLsZ3fzHaHXZy4DaOOX0vOlGQdlsjkh3mFHAIlVimpwAs4dslyQ==" }, "node_modules/stylus": { - "version": "0.59.0", - "resolved": "https://registry.npmjs.org/stylus/-/stylus-0.59.0.tgz", - "integrity": "sha512-lQ9w/XIOH5ZHVNuNbWW8D822r+/wBSO/d6XvtyHLF7LW4KaCIDeVbvn5DF8fGCJAUCwVhVi/h6J0NUcnylUEjg==", + "version": "0.62.0", + "resolved": "https://registry.npmjs.org/stylus/-/stylus-0.62.0.tgz", + "integrity": "sha512-v3YCf31atbwJQIMtPNX8hcQ+okD4NQaTuKGUWfII8eaqn+3otrbttGL1zSMZAAtiPsBztQnujVBugg/cXFUpyg==", "dependencies": { - "@adobe/css-tools": "^4.0.1", + "@adobe/css-tools": "~4.3.1", "debug": "^4.3.2", "glob": "^7.1.6", - "sax": "~1.2.4", + "sax": "~1.3.0", "source-map": "^0.7.3" }, "bin": { diff --git a/package.json b/package.json index 5d1e760..0db41de 100644 --- a/package.json +++ b/package.json @@ -9,11 +9,11 @@ "server": "hexo server" }, "hexo": { - "version": "7.0.0" + "version": "7.1.0" }, "dependencies": { "@next-theme/plugins": "^8.19.1", - "hexo": "^7.0.0", + "hexo": "^7.1.0", "hexo-abbrlink": "^2.2.1", "hexo-deployer-git": "^4.0.0", "hexo-filter-github-emojis": "^3.0.5", @@ -28,7 +28,7 @@ "hexo-related-posts": "^1.5.1", "hexo-renderer-ejs": "^2.0.0", "hexo-renderer-pandoc": "^0.4.0", - "hexo-renderer-stylus": "^3.0.0", + "hexo-renderer-stylus": "^3.0.1", "hexo-server": "^3.0.0", "hexo-tag-cloud": "2.1.*", "hexo-theme-landscape": "^1.0.0", diff --git a/source/_drafts/2021-11-27-josh-toi-part-1.md b/source/_drafts/2021-11-27-josh-toi-part-1.md index 9c29094..e679ed0 100644 --- a/source/_drafts/2021-11-27-josh-toi-part-1.md +++ b/source/_drafts/2021-11-27-josh-toi-part-1.md @@ -50,7 +50,7 @@ date: 2021-11-27 19:20:36 应用概率论、随机过程、数理统计等方法来研究信息的传输、提取和处理系统中的一般规律。
- 图1-1 信息传输系统的模型 + 图1-1 信息传输系统的模型
## 研究目的 diff --git a/source/_posts/2020-11-25-matlab-rcosdesign.md b/source/_posts/2020-11-25-matlab-rcosdesign.md index 5f89e4e..f6903f2 100644 --- a/source/_posts/2020-11-25-matlab-rcosdesign.md +++ b/source/_posts/2020-11-25-matlab-rcosdesign.md @@ -26,28 +26,30 @@ date: 2020-11-25 22:32:42 # 说明 -`b = rcosdesign(beta,span,sps)` 返回系数 `b`，该系数对应于具有由 `beta` 指定的衰减因子的平方根升余弦 FIR 滤波器。滤波器有 `span` 个符号，每个符号包含 `sps` 个样本。 滤波器的阶次，也即 `sps * span` 必须是偶数。滤波器的能量为 1。[举例](#Examples-01) +`b = rcosdesign(beta,span,sps)` 返回滚降因子为 `beta` 的根升余弦 FIR 滤波器的系数 `b`。滤波器被截断至 `span` 个符号，并且每个符号周期包含 `sps` 个样本。滤波器的阶数，即 `sps * span`，必须是偶数。滤波器的能量为 1。[举例](#Examples-01) -`b = rcosdesign(beta,span,sps,shape)` 根据 `shape` 返回不同的滤波器。当 `shape` 为 `sqrt` 时，将返回根升余弦滤波器；当 `shape` 为 `normal` 时，将返回升余弦 FIR 滤波器。[举例](#Examples-02) +`b = rcosdesign(beta,span,sps,shape)` 根据 `shape` 返回不同的滤波器。当 `shape` 为 `sqrt` 时，返回根升余弦滤波器；当 `shape` 为 `normal` 时，返回升余弦 FIR 滤波器。[举例](#Examples-02) # 示例 ## 设计根升余弦滤波器 -将滚降系数设为 `0.25`，波器的符号数设为 `6`，每个符号 `4` 个采样点。验证 `sqrt` 是 `shape` 参数的默认值。 +将滚降系数设为 `0.25`，滤波器的符号数设为 `6`，每个符号 `4` 个采样点。验证 `sqrt` 是参数 `shape` 的默认值。 ``` matlab h = rcosdesign(0.25,6,4); mx = max(abs(h-rcosdesign(0.25,6,4,'sqrt'))) ``` -> mx = 0
+> `mx = 0` ``` matlab fvtool(h,'Analysis','impulse') ``` -![ ](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-010-DesignASquareRootRaisedCosineFilterExample-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) + + +![ ](../images/post/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-010-DesignASquareRootRaisedCosineFilterExample-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) ## 升余弦和根升余弦滤波器的脉冲响应 @@ -64,7 +66,7 @@ h1 = rcosdesign(rf,span,sps,'normal'); fvtool(h1,'impulse') ``` -![ ](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-020-ImpulseResponsesOfNormalAndSquareRootRaisedCosineFiltersExample-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) +![ ](../images/post/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-020-ImpulseResponsesOfNormalAndSquareRootRaisedCosineFiltersExample-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) **升余弦滤波器在 `sps` 的整数倍处具有零值点**。因此，它满足无码间串扰（ISI）的 Nyquist 准则。但是，根升余弦滤波器没有这样的特性： @@ -73,7 +75,7 @@ h2 = rcosdesign(rf,span,sps,'sqrt'); fvtool(h2,'impulse') ``` -![ ](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-030-ImpulseResponsesOfNormalAndSquareRootRaisedCosineFiltersExample-02.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) +![ ](../images/post/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-030-ImpulseResponsesOfNormalAndSquareRootRaisedCosineFiltersExample-02.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) 将根升余弦滤波器与自身进行卷积。在最大值处截断脉冲响应，使其长度与 `h1` 相同。使用最大值将响应归一化。然后，将卷积后的根升余弦滤波器与升余弦滤波器进行比较。 @@ -90,7 +92,7 @@ ylabel('Normalized amplitude') legend('h1','h2 * h2') ``` -![ ](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-040-ImpulseResponsesOfNormalAndSquareRootRaisedCosineFiltersExample-03.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) +![ ](../images/post/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-040-ImpulseResponsesOfNormalAndSquareRootRaisedCosineFiltersExample-03.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) 卷积响应的长度是有限的，因此根升余弦滤波器与自身进行卷积得到的结果会与升余弦滤波器不一致。增加 `span` 可以在响应之间获得更紧密的一致性，并更好地符合 Nyquist 准则。 diff --git a/source/_posts/2020-11-26-matlab-gaussdesign.md b/source/_posts/2020-11-26-matlab-gaussdesign.md index f751198..fa675d0 100644 --- a/source/_posts/2020-11-26-matlab-gaussdesign.md +++ b/source/_posts/2020-11-26-matlab-gaussdesign.md @@ -40,7 +40,7 @@ h = gaussdesign(bt,span,sps); fvtool(h,'impulse') ``` -![ ](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-26-matlab-gaussdesign/2020-11-26-matlab-gaussdesign-010-GaussianFilterForAGSMGMSKDigitalCellularCommunicationSysExample-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) +![ ](../images/post/2020-11-26-matlab-gaussdesign/2020-11-26-matlab-gaussdesign-010-GaussianFilterForAGSMGMSKDigitalCellularCommunicationSysExample-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) # 输入参数 diff --git a/source/_posts/2020-11-27-josh-verilog-part-1.md b/source/_posts/2020-11-27-josh-verilog-part-1.md index e4bf369..856569f 100644 --- a/source/_posts/2020-11-27-josh-verilog-part-1.md +++ b/source/_posts/2020-11-27-josh-verilog-part-1.md @@ -113,7 +113,7 @@ HDL 的基本功能就是有效地描述并仿真硬件系统。在此部分， -![图 1-1 基于 HDL 的设计、仿真流程](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-27-josh-verilog-part-1/2020-11-27-josh-verilog-part-1-010-DesignSimulationFlowChartBasedonHDL.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5){width=800px} +![图 1-1 基于 HDL 的设计、仿真流程](../images/post/2020-11-27-josh-verilog-part-1/2020-11-27-josh-verilog-part-1-010-DesignSimulationFlowChartBasedonHDL.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5){width=800px} 下面对一些关键设计步骤与概念进行展开。 diff --git a/source/_posts/2020-11-27-matlab-awgn.md b/source/_posts/2020-11-27-matlab-awgn.md index 2fc54da..e1e41ea 100644 --- a/source/_posts/2020-11-27-matlab-awgn.md +++ b/source/_posts/2020-11-27-matlab-awgn.md @@ -67,7 +67,7 @@ plot(t,[x y]) legend('Original Signal','Signal with AWGN') ``` -![ ](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-27-matlab-awgn/2020-11-27-matlab-awgn-010-AddAWGNToSawtoothSignalExample-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) +![ ](../images/post/2020-11-27-matlab-awgn/2020-11-27-matlab-awgn-010-AddAWGNToSawtoothSignalExample-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) ## AWGN 信道中的常规 QAM 调制 @@ -108,7 +108,7 @@ grid hold off ``` -![ ](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-27-matlab-awgn/2020-11-27-matlab-awgn-020-GeneralQAMModulationInAnAWGNChannelExample-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/fontsize/15/dissolve/60/gravity/southeast/dx/5/dy/5) +![ ](../images/post/2020-11-27-matlab-awgn/2020-11-27-matlab-awgn-020-GeneralQAMModulationInAnAWGNChannelExample-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/fontsize/15/dissolve/60/gravity/southeast/dx/5/dy/5) 使用 `genqamdemod` 函数解调接收到的信号。计算误符号数和误符号率。 diff --git a/source/_posts/2020-11-28-hexo-miscellaneous.md b/source/_posts/2020-11-28-hexo-miscellaneous.md index 296f140..93c141b 100644 --- a/source/_posts/2020-11-28-hexo-miscellaneous.md +++ b/source/_posts/2020-11-28-hexo-miscellaneous.md @@ -245,15 +245,15 @@ busuanzi_count: 添加 Live2D 前的不蒜子显示情况如下。 -![添加 Live2D 前单篇博客的不蒜子显示情况](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-27-hexo-next-busuanzi-issues/2020-11-27-hexo-next-busuanzi-issues-010-Live2D-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) +![添加 Live2D 前单篇博客的不蒜子显示情况](../images/post/2020-11-27-hexo-next-busuanzi-issues/2020-11-27-hexo-next-busuanzi-issues-010-Live2D-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) -![添加 Live2D 前网站的不蒜子显示情况](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-27-hexo-next-busuanzi-issues/2020-11-27-hexo-next-busuanzi-issues-020-Live2D-02.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) +![添加 Live2D 前网站的不蒜子显示情况](../images/post/2020-11-27-hexo-next-busuanzi-issues/2020-11-27-hexo-next-busuanzi-issues-020-Live2D-02.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) 添加 Live2D 后，不蒜子在页面中不显示。 -![添加 Live2D 后单篇博客的不蒜子显示情况](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-27-hexo-next-busuanzi-issues/2020-11-27-hexo-next-busuanzi-issues-030-Live2D-03.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) +![添加 Live2D 后单篇博客的不蒜子显示情况](../images/post/2020-11-27-hexo-next-busuanzi-issues/2020-11-27-hexo-next-busuanzi-issues-030-Live2D-03.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) -![添加 Live2D 后网站的不蒜子显示情况](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-27-hexo-next-busuanzi-issues/2020-11-27-hexo-next-busuanzi-issues-040-Live2D-04.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) +![添加 Live2D 后网站的不蒜子显示情况](../images/post/2020-11-27-hexo-next-busuanzi-issues/2020-11-27-hexo-next-busuanzi-issues-040-Live2D-04.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) ### 问题原因 @@ -283,7 +283,7 @@ busuanzi_count: 在网页生成引擎中修改代码，去掉不蒜子部分的 `id` 和 `style` 属性，重新生成网页即可解决该问题。若将 `class` 属性一并删除，会导不蒜子部分和前面的其他显示部分缺少分隔符，如下图。 -![ ](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-27-hexo-next-busuanzi-issues/2020-11-27-hexo-next-busuanzi-issues-050-Delimeter-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) +![ ](../images/post/2020-11-27-hexo-next-busuanzi-issues/2020-11-27-hexo-next-busuanzi-issues-050-Delimeter-01.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5) 具体需要修改两个文件，`next/layout/_third-party/statistics/busuanzi-counter.swig` 中修改的是网页页脚部分的不蒜子显示，`next/layout/_macro/post.swig` 中修改的博客文章阅览数的不蒜子显示。 diff --git a/source/_posts/2020-11-28-josh-verilog-part-2.md b/source/_posts/2020-11-28-josh-verilog-part-2.md index 5424a11..772eecb 100644 --- a/source/_posts/2020-11-28-josh-verilog-part-2.md +++ b/source/_posts/2020-11-28-josh-verilog-part-2.md @@ -55,7 +55,7 @@ EDA 行业的先行者们发明了 Verilog 硬件描述语言，其最根本的 -![图 2-1 HelloVlog 模块](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-28-josh-verilog-part-2/2020-11-28-josh-verilog-part-2-010-JoshVerilog.png!sign){width=800px} +![图 2-1 HelloVlog 模块](../images/post/2020-11-28-josh-verilog-part-2/2020-11-28-josh-verilog-part-2-010-JoshVerilog.png){width=800px} 该电路首先在两个 2 位的输入数据 `A_in[1:0]` 的和 `B_in[1:0]` 之间，由 `sel` 信号做二选一。后面是一个 2-4 译码电路，将输入的信号 `result[1:0]`解析成 `eq0`、`eql`、`eq2` 和 `eq3` 这4个信号，它们同时只有一个为 1。 @@ -627,7 +627,7 @@ reg A_xor_wire -![图 2-2 异或门](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-28-josh-verilog-part-2/2020-11-28-josh-verilog-part-2-020-XORGate.png!sign){width=700px} +![图 2-2 异或门](../images/post/2020-11-28-josh-verilog-part-2/2020-11-28-josh-verilog-part-2-020-XORGate.png){width=700px} 下面从语义上的角度探讨两种描述方式的不同。 @@ -641,7 +641,7 @@ reg A_xor_wire -![图 2-3 D 触发器模型](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-28-josh-verilog-part-2/2020-11-28-josh-verilog-part-2-030-DFlipFlop.png!sign){width=300px} +![图 2-3 D 触发器模型](../images/post/2020-11-28-josh-verilog-part-2/2020-11-28-josh-verilog-part-2-030-DFlipFlop.png){width=300px} 在上述[实例代码](#HelloVlogCode)中相应的描述如下： diff --git a/source/_posts/2020-11-30-josh-verilog-part-3.md b/source/_posts/2020-11-30-josh-verilog-part-3.md index 252aa55..f88546a 100644 --- a/source/_posts/2020-11-30-josh-verilog-part-3.md +++ b/source/_posts/2020-11-30-josh-verilog-part-3.md @@ -49,7 +49,7 @@ description: Verilog 语言可以用多种方式来描述硬件，同时，使 -![图 3-1 一个电路模型](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-010-XORGate.png!sign){width=800px} +![图 3-1 一个电路模型](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-010-XORGate.png){width=800px} [图 3-1](#fig.3-1) 中的电路模型可以用如下的语句来描述： @@ -85,7 +85,7 @@ assign #1 A_xor_wire = eq0 ^ eq1; -![图 3-2 两个半加器和一个或门组成全加器](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-020-FullAdder.png!sign){width=800px} +![图 3-2 两个半加器和一个或门组成全加器](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-020-FullAdder.png){width=800px} 在[图 3-2](#fig.3-2) 中，用两个半加器和一个或门组成一个全加器，这里将使用连续赋值语句描述这个电路。代码如下。 @@ -226,7 +226,7 @@ endmodule -![图 3-3 线或的功能](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-030-WireOr.png!sign){width=700px} +![图 3-3 线或的功能](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-030-WireOr.png){width=700px} 同样，可以使用 `wand` 线网类型来将不同的输出“线与”在一起，如下： @@ -248,7 +248,7 @@ endmodule -![图 3-4 线与的功能](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-040-WireAnd.png!sign){width=700px} +![图 3-4 线与的功能](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-040-WireAnd.png){width=700px} ### 2.4.3. 三态总线功能 @@ -272,7 +272,7 @@ endmodule -![图 3-5 三态驱动总线电路](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-050-WireTri.png!sign){width=700px} +![图 3-5 三态驱动总线电路](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-050-WireTri.png){width=700px} # 3. 行为描述 @@ -362,7 +362,7 @@ end -![图 3-6 D 触发器模型](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-060-DFlipFlop.png!sign){width=600px} +![图 3-6 D 触发器模型](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-060-DFlipFlop.png){width=600px} 要实现[图 3-6](#fig.3-6) 中这样一个 D 触发器，通常用以下代码： @@ -510,7 +510,7 @@ end -![图 3-7 一个组合逻辑](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-070-ACombinationalLogic.png!sign){width=700px} +![图 3-7 一个组合逻辑](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-070-ACombinationalLogic.png){width=700px} 在以上代码仿真时，正是利用了阻塞赋值的这一特点才模拟了该组合逻辑的行为。 @@ -579,7 +579,7 @@ end -![图 3-8 三级流水的寄存器](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-080-ThreeFlowStateRegister.png!sign){width=600px} +![图 3-8 三级流水的寄存器](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-080-ThreeFlowStateRegister.png){width=600px} 正是利用了语句之间的非阻塞性，才实现了这个 3 级流水线的逻辑功能。 @@ -656,7 +656,7 @@ end -![图 3-9 顺序语句块的执行波形](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-090-SequentialWave.png!sign){width=500px} +![图 3-9 顺序语句块的执行波形](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-090-SequentialWave.png){width=500px} ### 3.3.2. 并行语句组 `fork ... join` @@ -676,7 +676,7 @@ join -![图 3-10 并行语句块的执行波形](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-100-ParallelWave.png!sign){width=500px} +![图 3-10 并行语句块的执行波形](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-100-ParallelWave.png){width=500px} ### 3.3.3. 语句组的标识符 @@ -736,7 +736,7 @@ end -![图 3-11 `if ... else` 语句](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-110-IfElseStatement.png!sign){width=600px} +![图 3-11 `if ... else` 语句](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-110-IfElseStatement.png){width=600px} 在 `if ... else` 语句中，条件是从上到下逐条检查的。因此，当满足一个条件时，就执行其后的语句，跳过 `else` 后面的语句、当所有条件都不满足，便执行最后一条 `else` 后面的语句。因此 `if ... else` 语句实际上是有优先级顺序的。 @@ -763,7 +763,7 @@ end -![图 3-12 产生锁存器](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-120-CombinationalLogicwithLatch.png!sign){width=800px} +![图 3-12 产生锁存器](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-120-CombinationalLogicwithLatch.png){width=800px} {% note warning %} @@ -790,7 +790,7 @@ end -![图 3-13 无锁存器的组合逻辑电路](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-130-CombinationalLogicwithoutLatch.png!sign){width=800px} +![图 3-13 无锁存器的组合逻辑电路](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-130-CombinationalLogicwithoutLatch.png){width=800px} 然而，在描述时序逻辑时，通常将利用 `if` 语句的隐式条件对带时钟使能的 D 触发器建模。代码如下： @@ -807,7 +807,7 @@ end -![图 3-14 带时钟使能的 D 触发器](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-140-DFlipFlopClock.png!sign){width=800px} +![图 3-14 带时钟使能的 D 触发器](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-140-DFlipFlopClock.png){width=800px} 其中，`en` 信号时 D 触发器的时钟使能端，`rst_n` 是 D 触发器的异步清零信号。 @@ -1004,7 +1004,7 @@ endmodule -![图 3-15 全加器](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-150-FullAdder.png!sign){width=800px} +![图 3-15 全加器](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-150-FullAdder.png){width=800px} 以上内容提到了实例化基本门和其他模块。 @@ -1032,7 +1032,7 @@ endmodule -![图 3-16 模块实例端口连接规则](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-160-ModuleConnection.png!sign){width=800px} +![图 3-16 模块实例端口连接规则](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-160-ModuleConnection.png){width=800px} 下面举例说明模块内部和外部的端口： @@ -1270,7 +1270,7 @@ Verilog 语言作为一种用户工具，提供给用户许多描述硬件的手 -![图 3-17 设计层次金字塔](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-170-DesignLevelPyramid.png!sign){width=600px} +![图 3-17 设计层次金字塔](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-170-DesignLevelPyramid.png){width=600px} 下面简单介绍几种不同角色的工作特点，以及它们所处的设计层次： @@ -1288,7 +1288,7 @@ Verilog 语言作为一种用户工具，提供给用户许多描述硬件的手 -![一个简单的握手协议状态机](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-180-ASimpleHandshakingStateMachine.png!sign){width=500px} +![一个简单的握手协议状态机](../images/post/2020-11-30-josh-verilog-part-3/2020-11-30-josh-verilog-part-3-180-ASimpleHandshakingStateMachine.png){width=500px} 上图中只有两个状态，当在左边的状态时，`REQ` 输出 1；当在右边的状态时，`REQ` 输出 0。`ACK` 是状态机的输入信号，决定了状态的跳转。 diff --git a/source/_posts/2020-12-02-josh-verilog-part-4.md b/source/_posts/2020-12-02-josh-verilog-part-4.md index fd1aca3..b794dc9 100644 --- a/source/_posts/2020-12-02-josh-verilog-part-4.md +++ b/source/_posts/2020-12-02-josh-verilog-part-4.md @@ -365,13 +365,13 @@ RTL 描述中时序逻辑和组合逻辑的连接关系和拓扑结构决定了 - ![图 4-1 某双沿加法电路与等价倍频时钟单沿加法电路结构示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-010-RegisterCircuitModeling-01.png!sign){width=900px} + ![图 4-1 某双沿加法电路与等价倍频时钟单沿加法电路结构示意图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-010-RegisterCircuitModeling-01.png){width=900px} RTL 仿真波形如[图 4-2](#fig.4-2) 所示。 - ![图 4-2 某双沿加法电路与等价倍频时钟单沿加法电路仿真波型图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-020-RegisterCircuitModeling-02.png!sign){width=900px} + ![图 4-2 某双沿加法电路与等价倍频时钟单沿加法电路仿真波型图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-020-RegisterCircuitModeling-02.png){width=900px} 通过这个例子可以看出 ，某些使用双沿操作的电路等价于使用倍频时钟的单沿电路，也就是说，这些电路使用了时钟的双沿触发寄存器，则**相当于提高了设计频率，提高了设计要求的时序难度**。对于这些电路，在附加时序约束和进行时序分析时一定要考虑充分。 @@ -423,7 +423,7 @@ RTL 描述中时序逻辑和组合逻辑的连接关系和拓扑结构决定了 - ![图 4-3 某组合逻辑译码电路的结构示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-030-CombinatorialLogictModeling.png!sign){width=700px} + ![图 4-3 某组合逻辑译码电路的结构示意图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-030-CombinatorialLogictModeling.png){width=700px} 2. `assign` 等语句描述的组合逻辑电路 @@ -946,7 +946,7 @@ endmodule - ![图 4-4 同步复位实现结构示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-040-SynchronousReset-01.png!sign){width=600px} + ![图 4-4 同步复位实现结构示意图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-040-SynchronousReset-01.png){width=600px} #### 3.9.1.2. 同步复位的优点 @@ -976,7 +976,7 @@ endmodule - ![图 4-5 同步复位实现结构示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-050-SynchronousReset-02.png!sign){width=800px} + ![图 4-5 同步复位实现结构示意图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-050-SynchronousReset-02.png){width=800px} ### 3.9.2. 异步复位 @@ -1018,7 +1018,7 @@ endmodule -![图 4-6 异步复位实现结构示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-060-AsynchronousReset-01.png!sign){width=500px} +![图 4-6 异步复位实现结构示意图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-060-AsynchronousReset-01.png){width=500px} #### 3.9.2.2. 异步复位的优点 @@ -1082,7 +1082,7 @@ endmodule -![图 4-7 异步复位同步化](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-070-AsynchronousReset-02.png!sign){width=500px} +![图 4-7 异步复位同步化](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-070-AsynchronousReset-02.png){width=500px} ## 3.10. 用 `case` 和 `if ... else` 建模 @@ -1182,29 +1182,29 @@ endmodule -![图 4-8 多 `if` 语句 Design Compiler 综合结构视图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-080-MultipleIf.png!sign){width=800px} +![图 4-8 多 `if` 语句 Design Compiler 综合结构视图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-080-MultipleIf.png){width=800px} -![图 4-9 单 `if` 语句和 `casex` 语句建模使用 Design Compiler 综合结构视图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-090-SingleIf.png!sign){width=800px} +![图 4-9 单 `if` 语句和 `casex` 语句建模使用 Design Compiler 综合结构视图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-090-SingleIf.png){width=800px} 但是由于综合工具的综合优化策略不同，即使对于相同的代码，其综合结果也不尽相同。为了加深理解，使用业界最流行的 PLD 综合工具 Synplify Pro 和 Precision RTL 对多 `if` 语句（`if ... if ... if ...`）、单 `if` 语句（`if ... else if ... else if ...`）和 `casex` 语句分别综合，其中多 `if` 语句的 Synplify Pro 综合结果对应的 RTL 视图和工艺结构视图分别如[图 4-10](#fig.4-10)、[图 4-11](#fig.4-11) 所示；多 `if` 语句的 Precision RTL 综合结果对应的 RTL 视图和工艺结构视图分别如[图 4-12](#fig.4-12)、[图 4-13](#fig.4-13) 所示。简单分析即可发现，这 3 种语句的 Synplify Pro 和 Precision RTL 综合结果基本一致，都没有明显的优先级结构。这是因为 Synplify Pro 和 Precision RTL 这两种综合工具为了节约硬件资源，根据其优化算法．优化掉了冗余的优先级判断结构。 -![图 4-10 多 `if` 语句的 Synplify Pro 综合结果 RTL 视图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-100-MultipleIfSynplifyProRTLView.png!sign){width=600px} +![图 4-10 多 `if` 语句的 Synplify Pro 综合结果 RTL 视图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-100-MultipleIfSynplifyProRTLView.png){width=600px} -![图 4-11 多 `if` 语句的 Synplify Pro 综合结果工艺结构视图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-110-MultipleIfSynplifyProTechView.png!sign){width=800px} +![图 4-11 多 `if` 语句的 Synplify Pro 综合结果工艺结构视图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-110-MultipleIfSynplifyProTechView.png){width=800px} -![图 4-12 多 `if` 语句的 Precision RTL 综合结果 RTL 视图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-120-MultipleIfPrecisionRTLRTLView.png!sign){width=800px} +![图 4-12 多 `if` 语句的 Precision RTL 综合结果 RTL 视图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-120-MultipleIfPrecisionRTLRTLView.png){width=800px} -![图 4-13 多 `if` 语句的 Precision RTL 综合结果工艺结构视图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-130-MultipleIfPrecisionRTLTechView.png!sign){width=800px} +![图 4-13 多 `if` 语句的 Precision RTL 综合结果工艺结构视图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-130-MultipleIfPrecisionRTLTechView.png){width=800px} 所以，从语法上讲，多 `if` 语句（`if ... if ... if ...`）可以建模具有优先级的条件判断结构，而单 `if` 语句（`if ... else if ... else if ...`）和 `case` 语句用于建模不带优先级的条件判断。但是随着综合工具优化能力的不断增强，新型的综合工具，大多时候会自动优化掉优先级结构，以减少芯片面积，提高时序性能。条件结构的综合结果是否带有优先级不但取决于综合工具的类型和版本．还和目标器件或目标库有直接关系。 @@ -1237,11 +1237,11 @@ endmodule -![图 4-14 多 `if` 语句无默认输出时 Synplify Pro 综合结果 RTL 视图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-140-MultipleIfSynplifyProRTLView.png!sign){width=800px} +![图 4-14 多 `if` 语句无默认输出时 Synplify Pro 综合结果 RTL 视图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-140-MultipleIfSynplifyProRTLView.png){width=800px} -![图 4-14 多 `if` 语句无默认输出时 Synplify Pro 综合结果工艺结构视图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-150-MultipleIfSynplifyProTechView.png!sign){width=800px} +![图 4-14 多 `if` 语句无默认输出时 Synplify Pro 综合结果工艺结构视图](../images/post/2020-12-02-josh-verilog-part-4/2020-12-02-josh-verilog-part-4-150-MultipleIfSynplifyProTechView.png){width=800px} 如果生成的 Latch 并非设计者意愿，则会造成与设计意图的偏离甚至是错误。而使用完整的 `if. .. else` 或 `case`（全译码或加有 `default` 关键字）语句，则可以有效地避免无意之中生成的 Latch 。在 [Part 3——描述方式和设计层次的 3.4 高级编程语句][]中也有防止产生不必要 Latch 的相关描述，可以参考。 diff --git a/source/_posts/2020-12-05-josh-verilog-part-5.md b/source/_posts/2020-12-05-josh-verilog-part-5.md index dcb26b2..1215ef3 100644 --- a/source/_posts/2020-12-05-josh-verilog-part-5.md +++ b/source/_posts/2020-12-05-josh-verilog-part-5.md @@ -87,7 +87,7 @@ WCDMA（宽带码分多址）系统中使用到了快速哈达码（Fast Hadamar -![图 5-1 FHT 原理图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-010-FastHadamardTransform.png!sign){width=1000px} +![图 5-1 FHT 原理图](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-010-FastHadamardTransform.png){width=1000px} FHT 单步算法如下： @@ -258,7 +258,7 @@ endmodule -![图 5-2 FHT 运算复用结构图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-020-FHTOperationReuseStructureDiagram.png!sign){width=600px} +![图 5-2 FHT 运算复用结构图](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-020-FHTOperationReuseStructureDiagram.png){width=600px} 代码如下： @@ -373,11 +373,11 @@ endmodule -![图 5-3 未采用复用方案的 `fhtpart` 模块综合所消耗的资源](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-030-FHTPARTResource.bmp!sign) +![图 5-3 未采用复用方案的 `fhtpart` 模块综合所消耗的资源](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-030-FHTPARTResource.bmp) -![图 5-4 采用复用方案的 `wch_fht` 模块综合所消耗的资源](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-040-WCHFHTResource.bmp!sign) +![图 5-4 采用复用方案的 `wch_fht` 模块综合所消耗的资源](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-040-WCHFHTResource.bmp) 通过对比可以清晰地观察到，采用复用实现方案所占面积约为原方案的 1/4，而得到这个好处的代价是，完成整个 FHT 运算的周期为原来的 4 倍。这个例子通过运算周期的加长，换取了消耗芯片面积的减少，是前面所述的用频率换面积的一种体现。本例所述“频率换面积”的前提是，FHT 模块频率较高，运算周期的余量较大，采用 4 步复用后，仍然能够满足系统流水线设计的要求。其实，如果流水线时序允许，FHT 运算甚至可以采用 1 bit 串行方案实现，该方案所消耗的芯片面积资源更少！ @@ -389,7 +389,7 @@ endmodule -![图 5-3 “面积换速度”示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-050-MoreAreaforSpeed.png!sign){width=700px} +![图 5-3 “面积换速度”示意图](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-050-MoreAreaforSpeed.png){width=700px} “面积复制换取速度提高”或者说“面积复制换取数据吞吐量的提高”是目前 FPGA 设计的常用技巧之一。现代高速FPGA 基本都有 DDR/DDR2/DDR3 的 I/O 硬件电路，通过这种 I/O 硬件电路，可以实现输入数据流的 1:2 和 1:4 的串/并变换和并/串变换，很多中高端 FPGA 在 I/O BANK 附近还专门设计了硬件的 DLL 或 PLL，配合 DDR/DDR2/DDR3 的 I/O 硬件电路完成对应的采样时钟的降速和倍速。调用这些 I/O 的硬件模块，可以方便、可靠地实现数据流的并行化（输入端）和串行化（输出端），从而更利于实现“面积复制换取速度提高”，或“面积复制换取数据吞吐量的提高”的设计思想。 @@ -495,7 +495,7 @@ case (var) -![图 5-6 系统规划的简化流程](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-060-SystemPlanningProc.png!sign){width=700px} +![图 5-6 系统规划的简化流程](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-060-SystemPlanningProc.png){width=700px} 对系统原则做一点引申，简单谈谈模块化设计方法。模块化设计是系统原则的一个很好的体现，它不仅是一种设计工具，它更是一种设计思路、设计方法，它是由顶向下、模块划分、分工协作设计思路的集中体现，是当代大型复杂系统的推荐设计方法。目前很多的 EDA 厂商都提高了模块化设计工具，通过这类工具划分每个模块的设计区域，然后单独设计和优化每个模块，最后将每个模块融合到顶层设计中，从而实现了团队协作、并行设计的模块化设计方法。合理使用模块化设计方法，能在最大程度上继承以往设计成果，并行分工协作，有效利用开发资源，缩短开发周期。 @@ -505,7 +505,7 @@ case (var) -![图 5-7 可编程匹配滤波器原理框图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-070-ProgrammableMatchFilter.png!sign){width=600px} +![图 5-7 可编程匹配滤波器原理框图](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-070-ProgrammableMatchFilter.png){width=600px} 其设计思想是：利用信道固有特点（如信道 pilot 导频、信道结构等），应用现代可编程数字信号处理的技术（如 DSP、FPGA 等），采取反馈与控制匹配滤波方式，实现对某信道的已扩信息的自动解扩解扰。该可编程 MF 的主要组成部分为本地码发生器、可编程信号 MF（S MF）、帧匹配滤波器（FRAME MF）和控制器。本地码发生器可生成各种所需的扩频、加扰序列，可接收控制器的指示脉冲，产生规定的本地解扩、解扰序列，作为 S MF 的参考序列；S MF 是完成匹配滤波的主体，可接收控制器的指示脉冲，将自己的匹配状态切换到下一匹配状态；FMF 完成对导频信号等特殊信号（信息位待选集有限）的检测，生成指示相关峰，通知控制器将 SMF 切换到下一匹配状态；控制器统一协调各部分工作。这种可编程滤波器可以在如越区切换、同步方面、CPCH 收发信机等多方面应用，如果适当安排时序流程，可以在较大程度上节约硬件资源。 @@ -565,7 +565,7 @@ case (var) 异步时钟域的转换的核心就是要保证下级时钟对上级数据采样的 Setup 时间和 Hold 时间。如果触发器的Setup 时间或者 Hold 时间不满足，就可能产生亚稳态，**此时触发器输出端 Q 在有效时钟沿之后比较长的一段时间内处于不确定的状态，在这段时间内 Q 端产生毛刺并不断振荡，最终固定在某一电压值，此电压值并不一定等于原来数据输入端 D 的数值**，这段时间称为决断时间（Resolution time）。经过 Resolution time 之后 Q 端将稳定到 0 或1, 但是究竟是 0 还是1，这是随机的，与输入没有必然的关系，其产生示意图如[图 5-8](#fig.5-8) 所示。 -![图 5-8 亚稳态产生示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-080-MetastableGenerate.png!sign){width=800px} +![图 5-8 亚稳态产生示意图](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-080-MetastableGenerate.png){width=800px} **亚稳态的危害主要体现在破坏系统的稳定性**。由于输出在稳定下来之前可能是毛刺、振荡、固定的某一电压值，因此亚稳态将**导致逻辑误判**，严重情况下输出 0~1 之间的中间电压值还会**使下一级产生亚稳态，即导致亚稳态的传播**。逻辑误判导致功能性错误，而亚稳态的传播则扩大了故障面。另外，在亚稳态状态下，任何诸如环境噪声、电源于扰等细微扰动都将导致更恶劣的状态不稳定。这时这个系统的传输延迟增大，状态输出错误，在某些情况下甚至会使寄存器在两个有效判定门限（$\mathrm{V_{oL}}$ 、$\mathrm{V_{oH}}$）之间长时间的振荡。 @@ -575,7 +575,7 @@ case (var) -![图 5-9 两级寄存器采样降低亚稳态概率](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-090-TwoStageRegisterSampling.png!sign){width=800px} +![图 5-9 两级寄存器采样降低亚稳态概率](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-090-TwoStageRegisterSampling.png){width=800px} 使用[图 5-9](#fig.5-9) 两级寄存器采样仅能降低亚稳态的概率，但是并不能保证第二级输出的稳态电平就是正确电平。前面说过经过 Resolution time 之后寄存器输出的电平是一个不确定的稳态值，也就是说**这种处理方法并不能排除采样错误的产生**，这时就**要求所设计的系统对采样错误有一定的容忍度**。有些应用本身就对采样错误不敏感，如一帧图像编码，一段话音编码等。而有些系统对错误采样比较敏感。这类由于亚稳态造成的采样是一些突发的错误，所以可以采用一些纠错编码手段完成错误的纠正。 @@ -632,7 +632,7 @@ case (var) - ![图 5-10 数据同步](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-100-DataSynchronization.png!sign){width=800px} + ![图 5-10 数据同步](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-100-DataSynchronization.png){width=800px} 可靠的做法是用 DPRAM 、FIFO 或者一段寄存器 Buffer 完成异步时钟域的数据转换。把数据存放在 DPRAM 或FIFO 的方法如下：将上级芯片提供的数据随路时钟作为写信号，将数据写入 DPRAM 或者FIFO, 然后使用本级的采样时钟（ 一般是数据处理的主时钟），将数据读出即可。由于时钟频率相同，所以 DPRAM 或 FIFO 两端的数据吞吐率一致，实现起来相对简单。 @@ -668,7 +668,7 @@ case (var) -![结构层次化编码示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-110-StructuredCoding.png!sign){width=600px} +![结构层次化编码示意图](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-110-StructuredCoding.png){width=600px} 结构层次化编码有如下注意事项： @@ -744,7 +744,7 @@ case (var) -![组合逻辑反馈环路示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-120-CombinatorialLogicFeedbackLoop.png!sign){width="400px"} +![组合逻辑反馈环路示意图](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-120-CombinatorialLogicFeedbackLoop.png){width="400px"} 组合逻辑反馈环路是一种**高风险**设计方式，主要原因如下： @@ -764,7 +764,7 @@ case (var) -![图 5-13 常用的异步脉冲产生方法示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-130-AsynchronousPulseGeneration.png!sign){width=600px} +![图 5-13 常用的异步脉冲产生方法示意图](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-130-AsynchronousPulseGeneration.png){width=600px} 这类异步方法设计的脉冲产生电路的脉冲宽度取决于 Delay Chains 的门延迟和线延迟，而在 FPGA/CPLD 中，大多数 Timing Driven 的综合、布线工具无法保证其布线延迟恒定。另外，PLD 器件本身在不同的 PVT（工艺、电压、温度）环境下其延时参数也有微小波动，所以脉冲宽度无法准确确定。而且 STA 工具也无法准确分析脉冲的特性，为时序仿真和验证带来了很多的不确定性。 @@ -774,7 +774,7 @@ case (var) -![图 5-14 常用的同步脉冲产生方法示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-140-SynchronousPulseGeneration.png!sign){width=600px} +![图 5-14 常用的同步脉冲产生方法示意图](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-140-SynchronousPulseGeneration.png){width=600px} ## 5.4. 慎用锁存器 @@ -807,7 +807,7 @@ endmodule -![图 5-15 Latch 的 RTL 示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-150-LatchRTL.png!sign){width=500px} +![图 5-15 Latch 的 RTL 示意图](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-150-LatchRTL.png){width=500px} 防止产生非目的性的Latch 的措施如下： @@ -832,7 +832,7 @@ endmodule -![图 5-16 内部时钟设计必须插入寄存器](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-160-InternalClockDesignwithRegister.png!sign){width=800px} +![图 5-16 内部时钟设计必须插入寄存器](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-160-InternalClockDesignwithRegister.png){width=800px} 另一方面，组合逻辑产生的时钟还会带来另外一个问题，组合逻辑电路的 Jitter 和 Skew 都比较大，如果时钟产生逻辑的延迟比数据路径的延迟更大，会带来负的 Skew，负的 Skew 同步逻辑设计是灾难性的。所以**使用组合逻辑产生内部时钟仅适用于时钟频率较低、时钟精度要求不高的情况**。另外，**这类时钟应该使用快速布线资源布线，而且需要对组合逻辑电路附加一定的约束条件，以确保时钟质质量**。 @@ -856,7 +856,7 @@ endmodule -![图 5-17 门控时钟](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-170-GatedClock.png!sign){width=800px} +![图 5-17 门控时钟](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-170-GatedClock.png){width=800px} 但是 Gated Clock 不是同步时序电路，其 Gating Logic（门控逻辑）会污染 Clock 的质量，通过控制门后会产生毛刺并使时钟的 Skew（偏斜）、Jitter（延时）等指标恶化。正如“[同步设计原则](#toc.2.1)” 一节所述，在同步时序电路中，应该尽量不使用 Gated Clock 。 @@ -864,7 +864,7 @@ endmodule -![图 5-18 门控时钟](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-180-ImprovedGatedClock.png!sign){width=800px} +![图 5-18 门控时钟](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-180-ImprovedGatedClock.png){width=800px} 如果功耗真的成为了 PLD 设计的首要问题，建议采用其他方法减少功耗。如果最近发展起来的低核电压芯片（Core 电压为 1.0V），芯片休眠功能，Clock MUX 等新技术器件能有效地节约芯片功耗。 @@ -876,7 +876,7 @@ endmodule -![图 5-19 同步使能端](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-190-EnableSynchronization.png!sign){width=500px} +![图 5-19 同步使能端](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-190-EnableSynchronization.png){width=500px} # 7. RTL 代码优化技巧 @@ -924,11 +924,11 @@ endmodule -![图 5-20 未 Resource Sharing，2 个乘法器的实现方案](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-200-TwoMultipliedwithoutResourceSharing.png!sign){width=800px} +![图 5-20 未 Resource Sharing，2 个乘法器的实现方案](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-200-TwoMultipliedwithoutResourceSharing.png){width=800px} -![图 5-21 Resource Sharing，1 个乘法器的实现方案](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-210-OneMultipliedwithResourceSharing.png!sign){width=800px} +![图 5-21 Resource Sharing，1 个乘法器的实现方案](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-210-OneMultipliedwithResourceSharing.png){width=800px} 对于综合后的 RTL 视图，这里需要强调以下几点： @@ -946,7 +946,7 @@ endmodule -![图 5-22 用逻辑复制改善扇出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-220-DuplicationtoImproveFanOut.png!sign){width=800px} +![图 5-22 用逻辑复制改善扇出](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-220-DuplicationtoImproveFanOut.png){width=800px} 需要说明的是，现在很多综合工具都可以自动设置最大扇出值（Max Fanout），如果某个信号的扇出值大于最大扇出，则该信号自动被综合工具复制。最大扇出值和器件的工艺密切相关，其合理值应该根据器件手册的声明和工程经验设置。这里举例用逻辑复制手段调整扇出，达到优化路径时延仅仅是为了讲述逻辑复制的概念，其实逻辑复制还有其他很多形式。例如，香农扩展（Shannon Expansion）等时序优化技术，香农扩展在后面将会有详细的介绍。 @@ -960,7 +960,7 @@ endmodule -![图 5-23 资源共享示例](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-230-ResourceSharingExample.png!sign){width=700px} +![图 5-23 资源共享示例](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-230-ResourceSharingExample.png){width=700px} 第一种写法，对应左边的 RTL 结构示意图： @@ -1043,7 +1043,7 @@ endmodule -![图 5-24 未使用香农扩展前的逻辑表达式对应的RTL视图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-240-BeforeShannonExtension.png!sign){width=1000px} +![图 5-24 未使用香农扩展前的逻辑表达式对应的RTL视图](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-240-BeforeShannonExtension.png){width=1000px} 从图中可以清晰地看到，未使用香农扩展时，从输入 PAD late 到输出 PAD out 之间共有4 个逻辑单元， 5 段路径。其综合结果使用了 8 个 2 输入或门，1 个 8 bit 输入加法器， 1 个 8 bit 比较器， 1 个 2 输入与门。 @@ -1068,7 +1068,7 @@ endmodule -![图 5-25 香农扩展后的逻辑表达式对应的RTL视图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-250-AfterShannonExtension.png!sign){width=1000px} +![图 5-25 香农扩展后的逻辑表达式对应的RTL视图](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-250-AfterShannonExtension.png){width=1000px} 在图中可以清晰地看到，使用香农扩展后，从输入 PAD late 到输出 PAD out 之间共有 1 个逻辑单元，2 段路径。其综合结果使用了 2 个 8 bit 输入加法器， 2 个 8 bit 比较器，2 个输入与门和一个 2 输入选择器。 @@ -1091,7 +1091,7 @@ endmodule -![图 5-26 RTL代码的设计目标](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-260-GoalsofRTLCode.png!sign){width=1000px} +![图 5-26 RTL代码的设计目标](../images/post/2020-12-05-josh-verilog-part-5/2020-12-05-josh-verilog-part-5-260-GoalsofRTLCode.png){width=1000px} 对一个 RTL 设计求全责备地要求它同时满足上述所有目标是非常困难的，应该根据这个RTL 设计的实现载体和具体应用，分析上述要求对本设计的重要性，然后综合考虑以上因素。 diff --git a/source/_posts/2020-12-15-music-lost-char-lloyd.md b/source/_posts/2020-12-15-music-lost-char-lloyd.md index f7d2a40..6b15131 100644 --- a/source/_posts/2020-12-15-music-lost-char-lloyd.md +++ b/source/_posts/2020-12-15-music-lost-char-lloyd.md @@ -25,13 +25,13 @@ date: 2020-12-15 11:35:17 | | "Lost" | |:--:|:------------:| -| Cover | | +| Cover | | | Singer | Cher Lloyd | | Album Type | Single | Released | 24 April 2020 | | Length | 2:55 | | Label | Universal, Polydor | -| Songwriter(s) | Raphaella, Casey Smith, Patrick Jordan-Patrikios, Boy Matthews, Youthonix, Cher Lloyd | +| Songwriter(s) | Raphaella, Casey Smith, Patrick Jordan-Patrikios, Boy Matthews, Youthonix, Cher Lloyd | | Producer(s) | Hitimpulse | diff --git a/source/_posts/2021-02-27-latex-miscellanea.md b/source/_posts/2021-02-27-latex-miscellanea.md index 5006e4a..0c75fae 100644 --- a/source/_posts/2021-02-27-latex-miscellanea.md +++ b/source/_posts/2021-02-27-latex-miscellanea.md @@ -41,7 +41,7 @@ date: 2021-02-27 15:58:53 ```
- 全文单栏效果图 + 全文单栏效果图
### 全文双栏 @@ -53,7 +53,7 @@ date: 2021-02-27 15:58:53 ```
- 全文双栏效果图 + 全文双栏效果图
### 部分双栏 @@ -71,15 +71,15 @@ date: 2021-02-27 15:58:53 \begin{multicols}{2} 通过对TC-OFDM信号系统仿真分析和传统弱信号捕获算法对比，提出了一种新 型的差分相干累加弱信号捕获算法；该算法采用一种差分相干累加损耗的补偿方法，能够有效提高捕获相对峰值，从而实现对弱信号的有效捕获。 - - 实验结果表明，在低信噪比的条件下，该算法能够提高TC-OFDM定位接收机捕获弱信号能力 1-2dB，从而提高弱信号的捕获概率。 + + 实验结果表明，在低信噪比的条件下，该算法能够提高TC-OFDM定位接收机捕获弱信号能力 1-2dB，从而提高弱信号的捕获概率。 \end{multicols} \end{document} ```
- 部分双栏效果图 + 部分双栏效果图
### 参考 diff --git a/source/_posts/2021-12-08-josh-msp-part-1.md b/source/_posts/2021-12-08-josh-msp-part-1.md index 40a3649..213481a 100644 --- a/source/_posts/2021-12-08-josh-msp-part-1.md +++ b/source/_posts/2021-12-08-josh-msp-part-1.md @@ -76,7 +76,7 @@ X_s\left( j\Omega \right) =\frac{1}{2\pi}X_c\left( j\Omega \right) \ast \frac{2\ -![图1.1 采样信号与模拟信号的关系](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2021-12-08-josh-msp-part-1/2021-12-08-josh-msp-part-1-010-RelationshipBetweenSampledSignalandAnalogSignal.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5){width=500px} +![图1.1 采样信号与模拟信号的关系](../images/post/2021-12-08-josh-msp-part-1/2021-12-08-josh-msp-part-1-010-RelationshipBetweenSampledSignalandAnalogSignal.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5){width=500px} **定理 1.1 (Nyquist-Shannon 采样定理)** 设 $x\left(t\right)$ 是带限信号，频带范围为 $\left(-\Omega_M,\Omega_M\right)$。如果采样率满足 @@ -134,7 +134,7 @@ y_D\left( nT_2 \right) =x\left( nDT_1 \right) -![图1.2 抽取](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2021-12-08-josh-msp-part-1/2021-12-08-josh-msp-part-1-020-DecimationDemostration.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5){width=500px} +![图1.2 抽取](../images/post/2021-12-08-josh-msp-part-1/2021-12-08-josh-msp-part-1-020-DecimationDemostration.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/14/dissolve/20/gravity/southeast/dx/5/dy/5){width=500px}   上述关系也可以简记为 diff --git a/source/_posts/2022-05-30-josh-systemverilog-1.md b/source/_posts/2022-05-30-josh-systemverilog-1.md index b51af5b..9d3d11d 100644 --- a/source/_posts/2022-05-30-josh-systemverilog-1.md +++ b/source/_posts/2022-05-30-josh-systemverilog-1.md @@ -90,7 +90,7 @@ Testbench 的用途在于**确定 DUT 的正确性**。包含下列步骤：
- 图 1.1 定向测试随时间的进展 + 图 1.1 定向测试随时间的进展
如果没有足够的时间和资源来完成定向测试该怎么办？如[图 1.1](#图1.1)，当在时间往前推进时，覆盖率 (coverage) 可能维持不变。如果设计复杂度翻倍，那么测试就需要增加一倍的时间或者人力，而这种情况是我们所不愿意看到的。因此为了达到 100% 覆盖率的目标，需要一种可以更快找出 bug 的方法。 @@ -99,7 +99,7 @@ Testbench 的用途在于**确定 DUT 的正确性**。包含下列步骤：
- 图 1.2 定向测试的覆盖率 + 图 1.2 定向测试的覆盖率
# 4. 方法学基础 @@ -118,7 +118,7 @@ Testbench 的用途在于**确定 DUT 的正确性**。包含下列步骤：
- 图 1.3 约束下的随机测试与定向测试随时间的进度比较 + 图 1.3 约束下的随机测试与定向测试随时间的进度比较
随机测试的前期准备工作看起来似乎令人不满意，但是其回报却很高。每个随机测试都可以共享这个通用的 testbench，不像每个定向测试都要从零开始编写。每个随机测试都会包含一部分代码，将激励约束到特定的方向上并触发期望的异常，比如创建一个协议违例。其结果是，约束下的随机 testbench 找起 bug 来会比很多定向测试快很多。随着 bug 出现率的下降，应该创建新的随机约束去探索新的区域。最后的几个 bug 可能只能通过定向测试来发现，但是绝大部分的 bug 都应该会在随机测试中出现。 @@ -135,7 +135,7 @@ Testbench 的用途在于**确定 DUT 的正确性**。包含下列步骤：
- 图 1.4 约束下的随机测试覆盖率 + 图 1.4 约束下的随机测试覆盖率
[图 1.5](#图1.5) 所示为达到完全覆盖的技术路线： @@ -146,7 +146,7 @@ Testbench 的用途在于**确定 DUT 的正确性**。包含下列步骤：
- 图 1.5 覆盖率收敛 + 图 1.5 覆盖率收敛
# 6. 我们的随机化对象是什么 @@ -214,7 +214,7 @@ Testbench 应该以多快的速度发送激励呢？使用**约束下的随机
- 图 1.6 带反馈和不带反馈的测试进展 + 图 1.6 带反馈和不带反馈的测试进展
Testbench 有没有可能为我们做到这一点呢？假设现在需要使用 testbench 在每个周期为处理器产生一个总线事件，并为总线事件做出终止判断（成功、校验错误、重试）。在没有使用 HVL 的时候，通常会编写一个很长的定向测试集，然后花费了很多天的工夫编排终止判断代码，并让它们在合适的周期里给出判断。经过了大量的手动分析以后才得出成功的结论达到 100 ％的覆盖率。但之后可能由于处理器的时序有了一点微小的改变，不得不重新分析测试并改变激励。 @@ -231,14 +231,14 @@ Testbench 有没有可能为我们做到这一点呢？假设现在需要使用
- 图 1.7 Testbench 与设计环境 + 图 1.7 Testbench 与设计环境
Testbench 模块里都包含了什么呢？有很多的 BFM (Bus Functional Models, 总线功能模型)，可以把它们看成是 testbench 构件 (components) ——从 DUT 的角度看，它们和真实的构件没什么两样，但它们其实只是 testbench 的组成部分，并非 RTL 设计。如果实际应用中设备被连接到 AMBA、USB、PCI 和 SPI 总线上，那么就必须**在 testbench 中建立能够产生激励并校验响应的等效构件**，如[图 1.8](#图1.8) 所示。这些构件并不是带有细节的可综合模型，而是遵循协议并且执行速度更快的高层次事件处理器。如果把设计原型在 FPGA 上实现或者是进行硬件仿真，那么这些 BFM 就需要是可综合的。
- 图 1.8 Testbench 构件 + 图 1.8 Testbench 构件
# 9. 分层 testbench @@ -335,7 +335,7 @@ endmodule
- 图 1.9 信号和命令层 + 图 1.9 信号和命令层
在底部的**信号层** (*signal*)，包含 DUT 和把 DUT 连接到 testbench 的信号。 @@ -348,7 +348,7 @@ endmodule
- 图 1.10 加上功能层的 testbench + 图 1.10 加上功能层的 testbench
## 9.4. 场景层 @@ -357,7 +357,7 @@ endmodule
- 图 1.11 加上场景层的 testbench + 图 1.11 加上场景层的 testbench
在 testbench **环境** (*environment*) 中的这些块 ([图 1.11](#图1.11) 虚线框内) 是在刚开始开发的时候画出来的。随着项目的进展，它们可能会有一些变化，也可能会加入一些功能，但是这些块对于每个独立的测试都是不应改变的。可以通过在代码中留下“hook”来做到这一点，这样即使这些块的行为需要在测试时改变，也不必重新编写代码。“hook”可以使用工厂模式 (factory patterns) 和回调函数 (callbacks) 来创建。 @@ -368,7 +368,7 @@ endmodule
- 图 1.12 带着所有层次的完整 testbench + 图 1.12 带着所有层次的完整 testbench
这个顶层的测试 (test) 就像一个指挥官：他不演奏任何乐器，但引领着其他人的表演。测试包含了用于创建激励的约束。 @@ -394,7 +394,7 @@ Testbench 中是否需要所有的层次呢？答案要视 DUT 而定。设计
- 图 1.13 带着所有层次的完整 testbench + 图 1.13 带着所有层次的完整 testbench
diff --git a/source/_posts/2022-05-31-josh-systemverilog-2.md b/source/_posts/2022-05-31-josh-systemverilog-2.md index ce8a90d..89711c3 100644 --- a/source/_posts/2022-05-31-josh-systemverilog-2.md +++ b/source/_posts/2022-05-31-josh-systemverilog-2.md @@ -157,7 +157,7 @@ bit [7:0] b_unpack[3]; // 非合并数组
- 图 2.1 非合并数组的存放 + 图 2.1 非合并数组的存放
仿真器通常使用两个或两个以上连续的字来存放 `logic` 和 `integer` 等四状态类型，这**比存放双状态变量多占用一倍的空间**。 @@ -342,7 +342,7 @@ $displayh(bytes,, // 显示所有的 32 比特
- 图 2.2 合井数组存放示意图 + 图 2.2 合井数组存放示意图
合并和非合并数组可以混合使用。可以使用数组来表示存储单元，这些单元可以按比特、字节或长字的方式进行存取。在[例 2.16](#例2.16) 中，`barray` 是一个具有 3 个合并元素的非合并数组。 @@ -363,7 +363,7 @@ nibbles = barray[0]; // 复制合并数组的元素值
- 图 2.3 合并数组存放示意图 + 图 2.3 合并数组存放示意图
- 使用一个下标，可以得到一个字的数据，如 `barray[2]`； @@ -503,7 +503,7 @@ SystemVerilog 提供了关联数组 (associative array) 类型，用来保存稀
- 图 2.4 关联数组 + 图 2.4 关联数组
仿真器可以采用树或哈希表的形式来存放关联数组，但有一定的额外开销。当保存索引值比较分散的数组时，例如使用 32 位地址或 64 位数据作为索引的数据包，这种额外开销显然是可以接受的。 diff --git a/source/_posts/2023-04-14-josh-dsp-part-1.md b/source/_posts/2023-04-14-josh-dsp-part-1.md index edac5bb..9b25ea6 100644 --- a/source/_posts/2023-04-14-josh-dsp-part-1.md +++ b/source/_posts/2023-04-14-josh-dsp-part-1.md @@ -264,7 +264,7 @@ X_e\left(e^{j\omega}\right)=\frac{1}{2}\left[X\left(e^{j\omega}\right)+X^\ast\le # 9. 傅里叶变换、拉氏变换和 $z$ 变换的关系 -![傅里叶变换、拉氏变换和 $z$ 变换的关系](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-14-josh-dsp-part-1/2023-04-14-josh-dsp-part-1-010-RelationshipBetweenTransform.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=600px} +![傅里叶变换、拉氏变换和 $z$ 变换的关系](../images/post/2023-04-14-josh-dsp-part-1/2023-04-14-josh-dsp-part-1-010-RelationshipBetweenTransform.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=600px} # 10. 参考文献 diff --git a/source/_posts/2023-04-14-josh-dsp-part-4.md b/source/_posts/2023-04-14-josh-dsp-part-4.md index 32ef184..76d0c37 100644 --- a/source/_posts/2023-04-14-josh-dsp-part-4.md +++ b/source/_posts/2023-04-14-josh-dsp-part-4.md @@ -114,11 +114,11 @@ X\left(k+\frac{N}{2}\right)&=X_1\left(k+\frac{N}{2}\right)+W_N^{\left(k+\frac{N} ## 3.2 蝶形运算流图符号 -![基-2 按时间抽取的 FFT 算法的鲽形图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-010-Radix2DITFFTButterfly.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} +![基-2 按时间抽取的 FFT 算法的鲽形图](../images/post/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-010-Radix2DITFFTButterfly.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} ## 3.3 8 点基-2 DIT-FFT 推导 -![8 点 radix-2 DIT-FFT 推导](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-020-Radix2DITFFTDerivation.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/40/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} +![8 点 radix-2 DIT-FFT 推导](../images/post/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-020-Radix2DITFFTDerivation.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/40/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px}   对于 8 点的序列，进行两次分解后每部分序列只含有两个点，可以直接计算 DFT。为了得到自然顺序输出的 DFT 序列，将第二级分解以后的结果作为输入。下面推导每级分解后序列的结果表示。 @@ -156,7 +156,7 @@ $$\begin{align} 将上述各式的旋转因子统一为 $W_{\frac{N}{2}}^k=W_N^{2k}$，则一个 8 点的 DFT 可以分解为四个 $\dfrac{N}{4}$ 点的 DFT ，先做 $\dfrac{N}{4}$ 点的 DFT，再用相应的两个 $\dfrac{N}{4}$ 点 DFT 的结果合成 $\dfrac{N}{2}$ 点的 DFT，从而得到 $X_1\left(k\right)、X_2\left(k\right)$，最后组合成为 $N$ 点的 DFT。上述过程的运算流图如下左图，实际绘制按照如下右图即可。 -![8 点 radix-2 DIT-FFT 的蝶形图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-030-8PointRadix2DITFFTButterfly.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} +![8 点 radix-2 DIT-FFT 的蝶形图](../images/post/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-030-8PointRadix2DITFFTButterfly.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} ## 3.4 算法特点 @@ -255,15 +255,15 @@ X\left(2r\right)=\sum_{n=0}^{\frac{N}{2}-1}{x_1\left(n\right)W_{\frac{N}{2}}^{rn ## 4.2 蝶形运算流图符号 -![基-2 按频率抽取的 FFT 算法的蝶形图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-040-Radix2DIFFFTButterfly.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} +![基-2 按频率抽取的 FFT 算法的蝶形图](../images/post/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-040-Radix2DIFFFTButterfly.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} ## 4.3 8 点基-2 DIF-FFT 推导简述 -![8 点 radix-2 DIF-FFT 推导](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-050-Radix2DIFFFTDerivation.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/40/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} +![8 点 radix-2 DIF-FFT 推导](../images/post/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-050-Radix2DIFFFTDerivation.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/40/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} 运算流图如下左图，实际绘制按照如下右图即可。 -![8 点 radix-2 DIF-FFT 的蝶形图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-060-8PointRadix2DIFFFTButterfly.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} +![8 点 radix-2 DIF-FFT 的蝶形图](../images/post/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-060-8PointRadix2DIFFFTButterfly.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} **对于任何流图，只要保持各节点所连的支路及其传输系数不变，则不论节点位置怎么排列，所得流图总是等效的，最后所得 DFT 结果也是正确的**，只是数据的提取和存放次序不同而已。 @@ -288,7 +288,7 @@ $$\begin{align} # 5. 基-2 DIT-FFT 和 基-2 DIF-FFT 的比较 -![radix-2 DIT-FFT 和 radix-2 DIF-FFT 的比较](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-070-Radix2DIFFFTRadix2DIFFFTComparison.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/40/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} +![radix-2 DIT-FFT 和 radix-2 DIF-FFT 的比较](../images/post/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-070-Radix2DIFFFTRadix2DIFFFTComparison.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/40/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} # 6. 分裂基 FFT 算法（split-radix FFT Method） @@ -379,11 +379,11 @@ X\left(4r+3\right)=\displaystyle\sum_{n=0}^{\frac{N}{4}-1}{x_4^2\left(n\right)W_ ## 6.2 L 蝶形运算流图符号 -![L 蝶形运算流图符号](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-080-Radix24LButterfly.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} +![L 蝶形运算流图符号](../images/post/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-080-Radix24LButterfly.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=1000px} ## 6.3 8 点 radix-2/4 FFT举例 -![8 点 radix-2/4 FFT举例](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-090-8PointRadix24LButterfly.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=600px} +![8 点 radix-2/4 FFT举例](../images/post/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-090-8PointRadix24LButterfly.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/80/dissolve/20/gravity/southeast/dx/5/dy/5){width=600px} ## 6.4 运算量分析 @@ -441,7 +441,7 @@ X_2\left(k\right)=-{jX}_{op}\left(k\right)=-\frac{j}{2}\left[X\left(k\right)-X^\ \end{equation}$$ 蝶形图如下： -![用一个 N点 DFT 同时计算两个 N 点实序列的 DFT的蝶形图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-100-ComputeNPointComplxDFT.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/40/dissolve/20/gravity/southeast/dx/5/dy/5){width=500px} +![用一个 N点 DFT 同时计算两个 N 点实序列的 DFT的蝶形图](../images/post/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-100-ComputeNPointComplxDFT.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/40/dissolve/20/gravity/southeast/dx/5/dy/5){width=500px} ## 7.2 用一个 $N$ 点 DFT 计算一个 $2N$ 点实序列的 DFT @@ -495,7 +495,7 @@ X\left(k+N\right)=X_1\left(k\right)-W_{2N}^kX_2\left(k\right),\ \ k=0,1,\cdots,N 蝶形图如下： -![用一个 N 点 DFT 计算一个 2N 点实序列的 DFT的蝶形图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-110-Compute2NPointRealDFT.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/40/dissolve/20/gravity/southeast/dx/5/dy/5){width=500px} +![用一个 N 点 DFT 计算一个 2N 点实序列的 DFT的蝶形图](../images/post/2023-04-14-josh-dsp-part-4/2023-04-14-josh-dsp-part-4-110-Compute2NPointRealDFT.png?imageMogr2/thumbnail/!100p|watermark/2/text/QEpvc2ggR2Fv/font/YWhyb25iZC50dGY=/fontsize/40/dissolve/20/gravity/southeast/dx/5/dy/5){width=500px} # 参考文献 diff --git a/source/_posts/2023-04-15-josh-dsp-part-5.md b/source/_posts/2023-04-15-josh-dsp-part-5.md index 613b26d..1443e92 100644 --- a/source/_posts/2023-04-15-josh-dsp-part-5.md +++ b/source/_posts/2023-04-15-josh-dsp-part-5.md @@ -30,31 +30,31 @@ categories: ### 1.1.1. 比特位反序输入、自然顺序输出 -![4-point radix-2 DIT-FFT 比特位反序输入、自然顺序输出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-010-4PointRadix2DITFFTIRON.png!sign){width=400px} +![4-point radix-2 DIT-FFT 比特位反序输入、自然顺序输出](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-010-4PointRadix2DITFFTIRON.png){width=400px} ### 1.1.2. 自然顺序输入、比特位反序输出 -![4-point radix-2 DIT-FFT 自然顺序输入、比特位反序输出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-020-4PointRadix2DITFFTINOR.png!sign){width=400px} +![4-point radix-2 DIT-FFT 自然顺序输入、比特位反序输出](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-020-4PointRadix2DITFFTINOR.png){width=400px} ## 1.2. 基-2 按频率抽取 FFT（4-point radix-2 DIF-FFT） ### 1.2.1. 比特位反序输入、自然顺序输出 -![4-point radix-2 DIF-FFT 比特位反序输入、自然顺序输出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-030-4PointRadix2DIFFFTIRON.png!sign){width=400px} +![4-point radix-2 DIF-FFT 比特位反序输入、自然顺序输出](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-030-4PointRadix2DIFFFTIRON.png){width=400px} ### 1.2.2. 自然顺序输入、比特位反序输出 -![4-point radix-2 DIF-FFT 自然顺序输入、比特位反序输出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-040-4PointRadix2DIFFFTINOR.png!sign){width=400px} +![4-point radix-2 DIF-FFT 自然顺序输入、比特位反序输出](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-040-4PointRadix2DIFFFTINOR.png){width=400px} ## 1.3. 分裂基按频率抽取 FFT（4-point split radix-2/4 DIF-FFT） -![4-point split radix-2/4 DIF-FFT](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-050-4PointSplitRadix24DIFFFT.png!sign){width=400px} +![4-point split radix-2/4 DIF-FFT](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-050-4PointSplitRadix24DIFFFT.png){width=400px} ## 1.4. 基-4 按频率抽取 FFT（4-point radix-4 DIF-FFT） -![4-point radix-4 DIF-FFT](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-060-4PointRadix4DIFFFT.png!sign){width=400px} +![4-point radix-4 DIF-FFT](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-060-4PointRadix4DIFFFT.png){width=400px} # 2. 8 点 FFT @@ -62,25 +62,25 @@ categories: ### 2.1.1. 比特位反序输入、自然顺序输出 -![8-point radix-2 DIT-FFT 比特位反序输入、自然顺序输出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-070-8PointRadix2DITFFTIRON.png!sign){width=600px} +![8-point radix-2 DIT-FFT 比特位反序输入、自然顺序输出](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-070-8PointRadix2DITFFTIRON.png){width=600px} ### 2.1.2. 自然顺序输入、比特位反序输出 -![8-point radix-2 DIT-FFT 自然顺序输入、比特位反序输出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-080-8PointRadix2DITFFTINOR.png!sign){width=600px} +![8-point radix-2 DIT-FFT 自然顺序输入、比特位反序输出](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-080-8PointRadix2DITFFTINOR.png){width=600px} ## 2.2. 基-2 按频率抽取 FFT（8-point radix-2 DIF-FFT） ### 2.2.1. 比特位反序输入、自然顺序输出 -![8-point radix-2 DIF-FFT 自然顺序输入、比特位反序输出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-090-8PointRadix2DIFFFTIRON.png!sign){width=600px} +![8-point radix-2 DIF-FFT 自然顺序输入、比特位反序输出](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-090-8PointRadix2DIFFFTIRON.png){width=600px} ### 2.2.2. 2自然顺序输入、比特位反序输出 -![8-point radix-2 DIF-FFT 自然顺序输入、比特位反序输出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-100-8PointRadix2DIFFFTINOR.png!sign){width=600px} +![8-point radix-2 DIF-FFT 自然顺序输入、比特位反序输出](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-100-8PointRadix2DIFFFTINOR.png){width=600px} ## 2.3. 分裂基按频率抽取 FFT（8-point split radix-2/4 DIF-FFT） -![8-point split radix-2/4 DIF-FFT](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-110-8PointSplitRadix24DIFFFT.png!sign){width=600px} +![8-point split radix-2/4 DIF-FFT](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-110-8PointSplitRadix24DIFFFT.png){width=600px} # 3. 16 点 FFT @@ -88,37 +88,37 @@ categories: ### 3.1.1. 比特位反序输入、自然顺序输出 -![16-point radix-2 DIT-FFT 比特位反序输入、自然顺序输出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-120-16PointRadix2DITFFTIRON.png!sign){width=1000px} +![16-point radix-2 DIT-FFT 比特位反序输入、自然顺序输出](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-120-16PointRadix2DITFFTIRON.png){width=1000px} ### 3.1.2. 自然顺序输入、比特位反序输出 -![16-point radix-2 DIT-FFT 自然顺序输入、比特位反序输出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-130-16PointRadix2DITFFTINOR.png!sign){width=1000px} +![16-point radix-2 DIT-FFT 自然顺序输入、比特位反序输出](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-130-16PointRadix2DITFFTINOR.png){width=1000px} ## 3.2. 基-2 按频率抽取 FFT（16-point radix-2 DIF-FFT） ### 3.2.1. 比特位反序输入、自然顺序输出 -![16-point radix-2 DIF-FFT 比特位反序输入、自然顺序输出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-140-16PointRadix2DIFFFTIRON.png!sign){width=1000px} +![16-point radix-2 DIF-FFT 比特位反序输入、自然顺序输出](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-140-16PointRadix2DIFFFTIRON.png){width=1000px} ### 3.2.2. 自然顺序输入、比特位反序输出 -![16-point radix-2 DIF-FFT 自然顺序输入、比特位反序输出](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-150-16PointRadix2DIFFFTINOR.png!sign){width=1000px} +![16-point radix-2 DIF-FFT 自然顺序输入、比特位反序输出](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-150-16PointRadix2DIFFFTINOR.png){width=1000px} ## 3.3. 分裂基按时间抽取 FFT（16-point split radix-2/4 DIT-FFT） -![16-point split radix-2 DIT-FFT](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-160-16PointSplitRadix24DITFFT.png!sign){width=1000px} +![16-point split radix-2 DIT-FFT](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-160-16PointSplitRadix24DITFFT.png){width=1000px} ## 3.4. 分裂基按频率抽取 FFT（16-point split radix-2/4 DIF-FFT） -![16-point split radix-2 DIF-FFT](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-170-16PointSplitRadix24DIFFFT.png!sign){width=1000px} +![16-point split radix-2 DIF-FFT](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-170-16PointSplitRadix24DIFFFT.png){width=1000px} ## 3.5. 基-4 按频率抽取 FFT（16-point radix-4 DIF-FFT） -![16-point radix-4 DIF-FFT](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-180-16PointRadix4DITFFT.png!sign){width=1000px} +![16-point radix-4 DIF-FFT](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-180-16PointRadix4DITFFT.png){width=1000px} 可以定义如下基-4 DIF-FFT 简化蝶形来简化流图表示的复杂程度 -![基-4 DIF-FFT 简化蝶形](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-190-SimplifiedRadix4Butterfly.png!sign){width=800px} +![基-4 DIF-FFT 简化蝶形](../images/post/2023-04-15-josh-dsp-part-5/2023-04-15-josh-dsp-part-5-190-SimplifiedRadix4Butterfly.png){width=800px} # 参考文献 diff --git a/source/_posts/2023-04-15-josh-dsp-part-6.md b/source/_posts/2023-04-15-josh-dsp-part-6.md index 1bc88c2..1fa9a3f 100644 --- a/source/_posts/2023-04-15-josh-dsp-part-6.md +++ b/source/_posts/2023-04-15-josh-dsp-part-6.md @@ -31,9 +31,9 @@ categories: | 基本运算单元 | 方框图 | 流图 | | :--: | :----: | :----: | -单位延时 | ![单位延时方框图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-010-UnitDelayBlock.png!sign){width=150px} | ![单位延时流图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-020-UnitDelayFlow.png!sign){width=150px} -常数乘法器 | ![常数乘法器方框图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-030-MultiplierBlock.png!sign){width=150px} | ![常数乘法器流图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-040-MultiplierFlow.png!sign){width=150px} -加法器 | ![加法器方框图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-050-AdderBlock.png!sign){width=150px} | ![加法器流图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-060-AdderFlow.png!sign){width=150px} +单位延时 | ![单位延时方框图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-010-UnitDelayBlock.png){width=150px} | ![单位延时流图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-020-UnitDelayFlow.png){width=150px} +常数乘法器 | ![常数乘法器方框图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-030-MultiplierBlock.png){width=150px} | ![常数乘法器流图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-040-MultiplierFlow.png){width=150px} +加法器 | ![加法器方框图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-050-AdderBlock.png){width=150px} | ![加法器流图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-060-AdderFlow.png){width=150px} @@ -62,7 +62,7 @@ H\left( z \right) =\frac{Y\left( z \right)}{X\left( z \right)}=\frac{\displaysty 则系统框图可表示为 -![直接Ⅰ型系统框图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-070-Direct1SystemBlock.png!sign){width=500px} +![直接Ⅰ型系统框图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-070-Direct1SystemBlock.png){width=500px} 由此可得系统的两级输入输出的微分方程 @@ -76,7 +76,7 @@ H_2\left(z\right)=\left(1-\sum_{k=1}^{N}{a_kz^{-k}}\right)^{-1}=\frac{Y\left(z\r 由微分方程可得直接Ⅰ型 IIR 滤波器的流图 -![直接Ⅰ型 IIR 滤波器的流图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-080-Direct1IIRFlow.png!sign){width=500px} +![直接Ⅰ型 IIR 滤波器的流图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-080-Direct1IIRFlow.png){width=500px} ## 2.2. 直接Ⅱ型（典范型） @@ -88,7 +88,7 @@ H\left( z \right) =\frac{Y\left( z \right)}{X\left( z \right)}=\frac{\displaysty 将系统框图变为 -![直接Ⅱ型系统框图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-090-Direct2SystemBlock.png!sign){width=500px} +![直接Ⅱ型系统框图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-090-Direct2SystemBlock.png){width=500px} 由此可得系统的两级输入输出的微分方程 @@ -102,7 +102,7 @@ H_1\left(z\right)=\sum_{k=0}^{M}{b_kz^{-k}}=\frac{Y\left(z\right)}{W\left(z\righ 由微分方程可得直接Ⅱ型 IIR 滤波器的流图 -![直接Ⅱ型 IIR 滤波器的流图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-100-Direct2IIRFlow.png!sign){width=400px} +![直接Ⅱ型 IIR 滤波器的流图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-100-Direct2IIRFlow.png){width=400px} - 直接型 IIR 滤波器的结构特点 @@ -151,11 +151,11 @@ H\left(z\right)=A\prod_{k=1}^{L}\left[\frac{1+\beta_{1k}z^{-1}+\beta_{2k}z^{-2}} 则系统框图可表示为 -![级联型 IIR 滤波器的系统框图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-110-CascadingIIRBlock.png!sign){width=700px} +![级联型 IIR 滤波器的系统框图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-110-CascadingIIRBlock.png){width=700px} 进一步可得级联型 IIR 滤波器的流图 -![级联型 IIR 滤波器的流图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-120-CascadingIIRFlow.png!sign){width=700px} +![级联型 IIR 滤波器的流图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-120-CascadingIIRFlow.png){width=700px} - 级联型 IIR 滤波器的结构特点 @@ -179,7 +179,7 @@ H\left(z\right)=G_0+\sum_{k=1}^{N_1}\frac{A_k}{1-g_kz^{-1}}+\sum_{k=1}^{N_2}\fra 可得 $M=N$ 时并联型 IIR 滤波器的系统框图和流图 -![并联型 IIR 滤波器的系统框图和流图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-130-ParallelIIRBlockFlow.png!sign){width=1000px} +![并联型 IIR 滤波器的系统框图和流图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-130-ParallelIIRBlockFlow.png){width=1000px} - 并联型IIR滤波器的结构特点 @@ -218,7 +218,7 @@ y\left(n\right)=\sum_{k=0}^{N=1}h\left(k\right)x\left(n-k\right)=h\left(n\right) 可得直接型 FIR 滤波器的流图 -![直接型 FIR 滤波器的流图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-140-Direct1FIRFlow.png!sign){width=600px} +![直接型 FIR 滤波器的流图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-140-Direct1FIRFlow.png){width=600px} ## 3.2. 级联型 @@ -230,7 +230,7 @@ H\left(z\right)=\sum_{n=0}^{N-1}{h\left(n\right)z^{-n}}=\sum_{k=1}^{\left\lfloor 可得级联型 FIR 滤波器的流图 -![级联型 FIR 滤波器的流图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-150-CascadingFIRFlow.png!sign){width=600px} +![级联型 FIR 滤波器的流图](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-150-CascadingFIRFlow.png){width=600px} - 级联型FIR滤波器的结构特点： @@ -250,7 +250,7 @@ H\left( z \right) =\underset{H_c\left( z \right)}{\underbrace{\left( 1-z^{-N} \r ### 3.3.1. 梳状滤波器 $H_c\left(z\right)$ -![梳状滤波器](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-160-CombFilter.png!sign){width=800px} +![梳状滤波器](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-160-CombFilter.png){width=800px}   子 FIR 系统 $H_c\left(z\right)=1-z^{-N}$ 是一个由 $N$ 节延迟单元组成的梳状滤波器，在单位圆上有 $N$ 个等分零点。可将梳状滤波器的频率响应写为 @@ -273,7 +273,7 @@ $$\begin{equation}   将梳状滤波器和谐振柜级联可得到频率取样型 FIR 滤波器的结构 -![频率取样型 FIR 滤波器的结构](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-170-FrequencySampling.png!sign){width=600px} +![频率取样型 FIR 滤波器的结构](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-170-FrequencySampling.png){width=600px} - 频率取样型 FIR 滤波器的结构特点： @@ -330,7 +330,7 @@ k&=1,2,\cdots,\frac{N}{2},&k为偶数 \end{cases} \end{equation}$$ -![修正频率取样型](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-180-ModifiedFrequencySampling.png!sign){width=800px} +![修正频率取样型](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-180-ModifiedFrequencySampling.png){width=800px}   当 $N$ 为偶数时，除了共轭根，还有一对实数根，分别位于 $k=0,\dfrac{N}{2}$ 两点，则此时系统函数为 @@ -352,7 +352,7 @@ H_0\left(z\right)=\frac{H\left(0\right)}{1-rz^{-1}},\ \ H_\frac{N}{2}\left(z\rig 则修正频率取样型 FIR 滤波器的结构为 -![修正频率取样型 FIR 滤波器的结构](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-190-ModifiedFrequencySamplingFIRStructure.png!sign){width=600px} +![修正频率取样型 FIR 滤波器的结构](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-190-ModifiedFrequencySamplingFIRStructure.png){width=600px} - 修正频率取样型 FIR 滤波器的结构特点： @@ -389,7 +389,7 @@ H\left(z\right)=\sum_{n=0}^{N-1}{h\left(n\right)z^{-n}}=\sum_{n=0}^{\frac{N}{2}- **当序列 $h\left(n\right)$ 偶对称时，取“$+$”号；当序列奇对称时，取“$-$”号**。则线性相位型 FIR 滤波器的结构为 -![线性相位型 FIR 滤波器的结构](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-200-LinearPhaseFIRStructure.png!sign){width=900px} +![线性相位型 FIR 滤波器的结构](../images/post/2023-04-15-josh-dsp-part-6/2023-04-15-josh-dsp-part-6-200-LinearPhaseFIRStructure.png){width=900px} ## 3.5. 快速卷积型（略） diff --git a/source/_posts/2023-04-15-josh-dsp-part-7.md b/source/_posts/2023-04-15-josh-dsp-part-7.md index 12fd91c..649e649 100644 --- a/source/_posts/2023-04-15-josh-dsp-part-7.md +++ b/source/_posts/2023-04-15-josh-dsp-part-7.md @@ -40,7 +40,7 @@ date: 2023-04-15 23:33:09 ## 1.2. 数字滤波器的技术指标 -![数字滤波器的技术指标](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-010-DigtalFilterBenchmark.png!sign){width=600px} +![数字滤波器的技术指标](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-010-DigtalFilterBenchmark.png){width=600px} 1. 通带截止频率（passband edge frequency）：$\omega_p$。 @@ -56,7 +56,7 @@ date: 2023-04-15 23:33:09 ## 2.1. 巴特沃斯（Butterworth）模拟原型滤波器 -![巴特沃斯（Butterworth）模拟原型滤波器](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-020-ButterworthAnalogFilter.png!sign){width=500px} +![巴特沃斯（Butterworth）模拟原型滤波器](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-020-ButterworthAnalogFilter.png){width=500px} ### 2.1.1. 幅度平方频率响应 @@ -292,7 +292,7 @@ $$\begin{align} &奇对称\qquad h\left(n\right)=-h\left(N-1-n\right) \end{align}$$ -![线性相位条件](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-030-LinearPhaseCondition.png!sign){width=700px} +![线性相位条件](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-030-LinearPhaseCondition.png){width=700px} ## 3.2. 线性相位 FIR 系统的频域特点（$h\left(n\right)$ 中心偶对称，$N$ 为奇数时） @@ -329,10 +329,10 @@ H\left(e^{j\omega}\right)=e^{-j\omega\left(\frac{N-1}{2}\right)}\sum_{n=0}^{\fra | | $h\left(n\right)$ | $N$ | 单位脉冲响应 |符幅频率响应 | 相位特性 | 特点 | | :--: | :--: | :--: | :--: | :--: | :--: | :--: | -| 情况 1 | 中
心
偶
对
称 | 奇数 | ![情况1-h](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-040-Case1h.png!sign){width=150px} ![情况1-a](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-050-Case1a.png!sign){width=150px} | $\displaystyle A\left(\omega\right)=\sum_{n=0}^{\frac{N-1}{2}}{a\left(n\right)\cos{\left(\omega n\right)}}$ ![情况1-A](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-060-Case1A.png!sign){width=200px} | $\displaystyle\varphi\left(\omega\right)=-\frac{N-1}{2}\omega$ ![情况1-相位](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-070-Case1phi.png!sign){width=1200px} | 可实现
低通
高通
带通
带阻 | -| 情况 2 | 中
心
偶
对
称 | 偶数 | ![情况2-h](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-080-Case2h.png!sign){width=200px} ![情况2-b](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-090-Case2b.png!sign){width=150px} | $\displaystyle B\left(\omega\right)=\sum_{n=0}^{\frac{N}{2}}{b\left(n\right)\cos{\left[\omega\left(n-\frac{1}{2}\right)\right]}}$ ![情况2-B](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-100-Case2B.png!sign){width=200px} | 同上 | 可实现
低通
带通 | -| 情况 3 | 中心奇对称 | 奇数 | ![情况3-h](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-110-Case3h.png!sign){width=200px} ![情况3-c](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-120-Case3c.png!sign){width=150px} | $\displaystyle C\left(\omega\right)=\sum_{n=0}^{\frac{N-1}{2}}{c\left(n\right)\sin{\left(\omega n\right)}}$ ![情况3-C](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-130-Case3C.png!sign){width=200px} | $\displaystyle\varphi\left(\omega\right)=\frac{\pi}{2}-\frac{N-1}{2}\omega$ ![情况3-相位](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-140-Case3phi.png!sign){width=120px} | 可实现
带通 | -| 情况 4 | 中心奇对称 | 偶数 | ![情况4-h](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-150-Case4h.png!sign){width=200px} ![情况4-h](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-160-Case4d.png!sign){width=150px} | $\displaystyle D\left(\omega\right)=\sum_{n=0}^{\frac{N}{2}}{d\left(n\right)\sin{\left[\omega\left(n-\frac{1}{2}\right)\right]}}$ ![情况4-h](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-170-Case4D.png!sign){width=200px} | 同上 | 可实现
高通
带阻 | +| 情况 1 | 中
心
偶
对
称 | 奇数 | ![情况1-h](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-040-Case1h.png){width=150px} ![情况1-a](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-050-Case1a.png){width=150px} | $\displaystyle A\left(\omega\right)=\sum_{n=0}^{\frac{N-1}{2}}{a\left(n\right)\cos{\left(\omega n\right)}}$ ![情况1-A](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-060-Case1A.png){width=200px} | $\displaystyle\varphi\left(\omega\right)=-\frac{N-1}{2}\omega$ ![情况1-相位](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-070-Case1phi.png){width=1200px} | 可实现
低通
高通
带通
带阻 | +| 情况 2 | 中
心
偶
对
称 | 偶数 | ![情况2-h](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-080-Case2h.png){width=200px} ![情况2-b](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-090-Case2b.png){width=150px} | $\displaystyle B\left(\omega\right)=\sum_{n=0}^{\frac{N}{2}}{b\left(n\right)\cos{\left[\omega\left(n-\frac{1}{2}\right)\right]}}$ ![情况2-B](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-100-Case2B.png){width=200px} | 同上 | 可实现
低通
带通 | +| 情况 3 | 中心奇对称 | 奇数 | ![情况3-h](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-110-Case3h.png){width=200px} ![情况3-c](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-120-Case3c.png){width=150px} | $\displaystyle C\left(\omega\right)=\sum_{n=0}^{\frac{N-1}{2}}{c\left(n\right)\sin{\left(\omega n\right)}}$ ![情况3-C](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-130-Case3C.png){width=200px} | $\displaystyle\varphi\left(\omega\right)=\frac{\pi}{2}-\frac{N-1}{2}\omega$ ![情况3-相位](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-140-Case3phi.png){width=120px} | 可实现
带通 | +| 情况 4 | 中心奇对称 | 偶数 | ![情况4-h](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-150-Case4h.png){width=200px} ![情况4-h](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-160-Case4d.png){width=150px} | $\displaystyle D\left(\omega\right)=\sum_{n=0}^{\frac{N}{2}}{d\left(n\right)\sin{\left[\omega\left(n-\frac{1}{2}\right)\right]}}$ ![情况4-h](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-170-Case4D.png){width=200px} | 同上 | 可实现
高通
带阻 | ## 3.3. 线性相位 FIR 滤波器的零点位置 @@ -359,7 +359,7 @@ H^\ast\left(z\right)=\left[\sum_{n=0}^{N-1}{h\left(n\right)z^{-n}}\right]^\ast=\ 即在实轴上又在单位圆上 | $z=+1$ 或 $z=-1$ | $z_2,z_3$ 不在实轴上但在单位圆上 | 一组共轭对 | $z_4$ 在实轴上但不在单位圆上 | 一组互为倒数的实数对 | $z_5$ -![线性相位 FIR 滤波器的零点位置](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-180-ZeroPointOfLinearPhaseFIR.png!sign){width=300px} | | +![线性相位 FIR 滤波器的零点位置](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-180-ZeroPointOfLinearPhaseFIR.png){width=300px} | | # 4. FIR 数字滤波器的设计 @@ -399,7 +399,7 @@ H^\ast\left(z\right)=\left[\sum_{n=0}^{N-1}{h\left(n\right)z^{-n}}\right]^\ast=\ ### 4.1.2. 窗函数法设计高通、带通、带阻滤波器 -![窗函数法设计高通、带通、带阻滤波器](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-190-WindowingMethod.png!sign){width=900px} +![窗函数法设计高通、带通、带阻滤波器](../images/post/2023-04-15-josh-dsp-part-7/2023-04-15-josh-dsp-part-7-190-WindowingMethod.png){width=900px} | 滤波器类型 | 理想滤波器的
频率响应 | 理想滤波器的
单位抽样响应 | | :--: | :--------: | :--------------: | diff --git a/source/_posts/2023-04-16-josh-verilog-part-6.md b/source/_posts/2023-04-16-josh-verilog-part-6.md index c9f1880..3f3eefc 100644 --- a/source/_posts/2023-04-16-josh-verilog-part-6.md +++ b/source/_posts/2023-04-16-josh-verilog-part-6.md @@ -45,13 +45,13 @@ description: 状态机是逻辑设计的重要内容，其设计水平直接反 -![图 6-1 某学生在校生活状态转移图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-010-SchoolLifeStateTransitionDiagramOfStudentA.png!sign){width=600} +![图 6-1 某学生在校生活状态转移图](../images/post/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-010-SchoolLifeStateTransitionDiagramOfStudentA.png){width=600} 如果你认为这张图描述的学生生活过于单调而怀疑状态机描述方法的能力，就再看另一位生活丰富多彩的同学的在校生活，他/她的在校生活方式可以用[图 6-2](#fig.6-2) 表示。 -![图 6-2 另一位学生在校生活状态转移图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-020-SchoolLifeStateTransitionDiagramOfStudentB.png!sign){width=600} +![图 6-2 另一位学生在校生活状态转移图](../images/post/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-020-SchoolLifeStateTransitionDiagramOfStudentB.png){width=600} {% note info %} @@ -285,7 +285,7 @@ ERROR 状态的输出为： {o1, o2, err} = 3'b111。 -![图 6-3 例子的状态转移图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-030-StateTransitionDiagramOfExample.png!sign){width=600} +![图 6-3 例子的状态转移图](../images/post/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-030-StateTransitionDiagramOfExample.png){width=600} ### 2.3.1. 一段式状态机描述方法（应该避免的写法） @@ -360,7 +360,7 @@ endmodule -![图 6-4 一段式 FSM 描述结构](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-040-OneStageFSM.png!sign){width=900} +![图 6-4 一段式 FSM 描述结构](../images/post/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-040-OneStageFSM.png){width=900} 一段式描述方法将状态转移判断的组合逻辑和状态寄存器转移的时序逻辑混写在同一个 always 模块中，**不符合将时序和组合逻辑分开描述的 Coding Style（代码风格）**，而且在描述当前状态时要考虑下个状态的输出，整个代码不清晰，不利于维护修改，并且不利于附加约束，不利于综合器和布局布线器对设计的优化。 @@ -466,7 +466,7 @@ endmodule -![图 6-5 两段式FSM描述结构图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-050-TwoStageFSM.png!sign){width=900px} +![图 6-5 两段式FSM描述结构图](../images/post/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-050-TwoStageFSM.png){width=900px} 本例中，同步时序描述状态转移的 `always` 模块代码如下： @@ -644,7 +644,7 @@ endmodule -![图 6-6 三段式FSM描述结构图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-060-ThreeStageFSM.png!sign){width=1000px} +![图 6-6 三段式FSM描述结构图](../images/post/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-060-ThreeStageFSM.png){width=1000px} 对比上节两段式 FSM 的描述，可以清晰发现三段式与两段式 FSM 描述的最大区别在于**两段式采用了组合逻辑输出**，而**三段式巧妙地根据下一状态的判断，用同步时序逻辑寄存 FSM 的输出**。本例中就是下面一段代码， @@ -705,7 +705,7 @@ case(NS) -![图 6-7 三段式建模结构与一段式建模结构的关系图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-070-ComparisonOfOneAndThreeStageFSM.png!sign){width=1000px} +![图 6-7 三段式建模结构与一段式建模结构的关系图](../images/post/2023-04-16-josh-verilog-part-6/2023-04-16-josh-verilog-part-6-070-ComparisonOfOneAndThreeStageFSM.png){width=1000px} #### 2.3.4.4. 两段式建模和三段式建模的关系 diff --git a/source/_posts/2023-04-16-josh-verilog-part-7.md b/source/_posts/2023-04-16-josh-verilog-part-7.md index 1feedd8..4b13b24 100644 --- a/source/_posts/2023-04-16-josh-verilog-part-7.md +++ b/source/_posts/2023-04-16-josh-verilog-part-7.md @@ -39,7 +39,7 @@ description: 验证是芯片设计过程中非常重要的一个环节。无缺 -![图 7-1 设计和验证的关系](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-010-DesignVersusVerification.png!sign){width=300px} +![图 7-1 设计和验证的关系](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-010-DesignVersusVerification.png){width=300px} @@ -47,7 +47,7 @@ description: 验证是芯片设计过程中非常重要的一个环节。无缺 -![图 7-2 设计和验证的过程](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-020-ProcessOfDesignAndVerification.png!sign){width=550} +![图 7-2 设计和验证的过程](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-020-ProcessOfDesignAndVerification.png){width=550} 其中，从设计规格到 RTL 的代码是由设计工程师手动完成的，而从 RTL 代码到门级网表则**由逻辑综合工具自动完成**。 @@ -67,7 +67,7 @@ testbench，顾名思义就是测试平台的意思。简单地讲，在仿真 -![图 7-3 testbench的概念](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-030-TheIdeaOfTestbench.png!sign){width=500px} +![图 7-3 testbench的概念](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-030-TheIdeaOfTestbench.png){width=500px} testbench 概念提供了一个很好的验证芯片的平台。 @@ -77,7 +77,7 @@ testbench 概念提供了一个很好的验证芯片的平台。 -![图 7-4 基于testbench的仿真流程](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-040-SimulationFlowBasedOnTestbench.png!sign){width=800px} +![图 7-4 基于testbench的仿真流程](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-040-SimulationFlowBasedOnTestbench.png){width=800px} 从图中可以清晰地看出 testbench 的主要功能： @@ -102,7 +102,7 @@ testbench 概念提供了一个很好的验证芯片的平台。 -![图 7-5 用户验证MPI接口功能的仿真平台](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-050-MPITestbench.png!sign){width=700px} +![图 7-5 用户验证MPI接口功能的仿真平台](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-050-MPITestbench.png){width=700px} 关于这个设计的验证，在后续笔记将重点介绍。 @@ -120,7 +120,7 @@ testbench 概念提供了一个很好的验证芯片的平台。 -![图 7-6 模块实例端口连接规则](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-060-ModuleInstancePortConnection.png!sign){width=800} +![图 7-6 模块实例端口连接规则](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-060-ModuleInstancePortConnection.png){width=800} 这里，需要提醒初学者注意的是，**对于双向信号，驱动它的也一定是一个三态的线网**。不能是寄存器类型，否则就会发生冲突。 @@ -185,7 +185,7 @@ always -![图 7-7 产生的时钟测试激励](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-070-GeneratedClockStimulus.png!sign){width=450} +![图 7-7 产生的时钟测试激励](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-070-GeneratedClockStimulus.png){width=450} #### 2.1.3.2. 非 `50%` 占空比时钟信号 @@ -208,7 +208,7 @@ end -![图 7-8 占空比不是50%的时钟](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-080-ClockWithOtherDutyCycle.png!sign){width=350} +![图 7-8 占空比不是50%的时钟](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-080-ClockWithOtherDutyCycle.png){width=350} 由于 `Clock` 在 `0` 时刻没有被初始化，而且 `Clock` 是寄存器类型变量， 因此在该信号的前 `5 ns`, 在仿真器中的值为 `x`。 @@ -261,7 +261,7 @@ assign # PHASE_SHIFT Derived_clock = Absolute_clock; -![图 7-9 绝对时钟和派生时钟](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-090-AbsoluteAndDerivedClock.png!sign){width=400px} +![图 7-9 绝对时钟和派生时钟](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-090-AbsoluteAndDerivedClock.png){width=400px} 值得注意的是，图中的 `Absolute_Clock` 为 `register`（寄存器）型变量，初始值为 `x`；而 `Derived_clock` 为 `net`（线网）型变量，初始值为 `z`。 @@ -304,7 +304,7 @@ end -![图 7-10 同步复位](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-100-SynchronousReset.png!sign){width=500px} +![图 7-10 同步复位](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-100-SynchronousReset.png){width=500px} 另一种同步复位信号产生的方法如下： @@ -323,13 +323,13 @@ end -![图 7-11 另一种同步复位](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-110-AnotherSynchronousReset.png!sign){width=500px} +![图 7-11 另一种同步复位](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-110-AnotherSynchronousReset.png){width=500px} ### 2.1.4. 产生值序列 -![图 7-12 一个波形图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-120-SignalWaveDiagram.png!sign){width=500px} +![图 7-12 一个波形图](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-120-SignalWaveDiagram.png){width=500px} 下面用 Verilog 来描述如[图 7-12](#fig.7-12) 中的一个波形。 @@ -581,7 +581,7 @@ ProductResult = Product(A,B); // 将 A 和 B 的乘积赋给 ProductResult -![图 7-13 搭建仿真环境](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-130-BuildTestbench.png!sign){width=700px} +![图 7-13 搭建仿真环境](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-130-BuildTestbench.png){width=700px} 图中的仿真平台是**单顶层**的 testbench，在后面还将介绍多顶层的 testbench 。 @@ -654,7 +654,7 @@ endmodule -![图 7-14 动态自检测仿真方法](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-140-DynamicSelfTest.png!sign){width=800px} +![图 7-14 动态自检测仿真方法](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-140-DynamicSelfTest.png){width=800px} 由于自动比较法通常用在非常庞大的设计验证中，在系列笔记中不重点介绍这种方式。 @@ -666,7 +666,7 @@ VCD 文件是一种标准格式的波形记录文件。该文件只记录发生 -![图 7-15 VCD文件调试和分析仿真过程](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-150-SimulationWithVCD.png!sign){width=400px} +![图 7-15 VCD文件调试和分析仿真过程](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-150-SimulationWithVCD.png){width=400px} 在系列笔记中，不对 VCD 文件进行过多的介绍。 @@ -688,7 +688,7 @@ VCD 文件是一种标准格式的波形记录文件。该文件只记录发生 -![图 7-16 HDL语言的使用层次示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-160-HDLDesignEntry.png!sign){width=600px} +![图 7-16 HDL语言的使用层次示意图](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-160-HDLDesignEntry.png){width=600px} 上图说明了不同的 HDL 语言种类对应的 HDL 描述层次的关系，图中实线框表示适用程度较高，虚线框表示适用程度较低。常用的 HDL 描述层次有门级、寄存器传输级和行为级等。 @@ -726,7 +726,7 @@ VCD 文件是一种标准格式的波形记录文件。该文件只记录发生 -![图 7-17 PowerPc和FPGA接口示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-170-PortConnectionDemo.png!sign){width=400px} +![图 7-17 PowerPc和FPGA接口示意图](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-170-PortConnectionDemo.png){width=400px} 所有的总线操作都由 PowerPC 发起。共分为两种总线操作方式：读操作和写操作。 @@ -734,11 +734,11 @@ VCD 文件是一种标准格式的波形记录文件。该文件只记录发生 -![图 7-18 读操作时序](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-180-ReadTiming.png!sign){width=600px} +![图 7-18 读操作时序](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-180-ReadTiming.png){width=600px} -![图 7-19 写操作时序](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-190-WriteTiming.png!sign){width=600px} +![图 7-19 写操作时序](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-190-WriteTiming.png){width=600px} 要注意的是，PowerPC 的读/写时序与许多配置参数有关，而且处理器使用不同的主频，时序也不太一样。这里为了简单明了，采用了特定的设置和主频。在实际系统中，如果采用不同的设置，需要参考 PowerPC 的数据手册。但是，这里的设计思想是可以借鉴的。 @@ -783,7 +783,7 @@ endmodule -![图 7-20 testbench结构](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-200-TestbenchStructure.png!sign){width=600px} +![图 7-20 testbench结构](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-200-TestbenchStructure.png){width=600px} 根据[图 7-20](#fig.7-20) 中的 testbench 结构，设计 testbench 顶层如下： @@ -861,7 +861,7 @@ endmodule -![图 7-21 ModelSim窗口](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-210-ModesimWindow.png!sign){width=900px} +![图 7-21 ModelSim窗口](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-210-ModesimWindow.png){width=900px} ### 3.2.3. 查看仿真结果 @@ -869,7 +869,7 @@ endmodule -![图 7-22 ModelSim仿真结果](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-220-ModesimSimulationResult.png!sign){width=900px} +![图 7-22 ModelSim仿真结果](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-220-ModesimSimulationResult.png){width=900px} 为了检查读/写数据是否一致，只需要查看以上的显示内容即可。另外，还可以通过查看具体的波形来调试。 @@ -953,7 +953,7 @@ endmodule -![图 7-23 结构化testbench示意](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-230-StructuralTestbench.png!sign){width=600px} +![图 7-23 结构化testbench示意](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-230-StructuralTestbench.png){width=600px} 结构化test bench 的好处是： @@ -985,7 +985,7 @@ BFM 是一种将物理的接口时序操作转化成更高抽象层次接口的 -![图 7-24 BFM示意图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-240-BFMDiagram.png!sign){width=800} +![图 7-24 BFM示意图](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-240-BFMDiagram.png){width=800} 在[图 7-24](#fig.7-24) 中，`uP_BFM` 是作为一个 Verilog HDL 中的 `module` 出现的。其中，在 BFM 面对 DUV 的一边将模拟 PowerPC 的访问时序，这是一个延时非常精确的总线模型。在该模型内部有两个用户定义的任务： `write` 和 `read`，供其他模块（如测试激励）调用。 @@ -999,7 +999,7 @@ BFM 是一种将物理的接口时序操作转化成更高抽象层次接口的 -![图 7-25 harness测试套具](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-250-Harness.png!sign){width=600px} +![图 7-25 harness测试套具](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-250-Harness.png){width=600px} ## 4.4. 测试用例 @@ -1009,7 +1009,7 @@ BFM 是一种将物理的接口时序操作转化成更高抽象层次接口的 -![图 7-26 testcase测试用例](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-260-Testcase.png!sign){width=700px} +![图 7-26 testcase测试用例](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-260-Testcase.png){width=700px} testcase 中的各种用例可以通过图中的虚线箭头来调用 harness 中的任务。关于测试用例和 harness 之间的层次关系，请参考下一小节的内容。 @@ -1025,7 +1025,7 @@ testcase 中的各种用例可以通过图中的虚线箭头来调用 harness -![图 7-27 单顶层的testbench结构](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-270-SingleTopTestbench.png!sign){width=650px} +![图 7-27 单顶层的testbench结构](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-270-SingleTopTestbench.png){width=650px} 假设 harness 在 testbench 顶层中的实例名叫 `inst_harness`，harness 实例化进来的模块 `uP_BFM` 里面有一个任务 `SEND_DATA`，该任务可以产生激励输入到 DUV，在 testcase 里调用该任务就可写为： @@ -1044,7 +1044,7 @@ Verilog 语言支持多顶层结构。 -![图 7-28 多顶层的testbench结构](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-280-MultiTopTestbench.png!sign){width=750px} +![图 7-28 多顶层的testbench结构](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-280-MultiTopTestbench.png){width=750px} harness 顶层由 DUV 和一些接口模型（BFM）构成一个狭义上的测试平台，其他测试用例模块可以调用 BFM 里面的 `task`、`function` 等，向 DUV 施加激励。 @@ -1087,7 +1087,7 @@ testbench 不是凭空设计的，它的根本起点还是一个设计的需求 -![图 7-29 单顶层testbench结构](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-290-SingleTopTestbenchDemo.png!sign){width=600px} +![图 7-29 单顶层testbench结构](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-290-SingleTopTestbenchDemo.png){width=600px} 在单顶层 testbench 中，实例化 harness，同时写了两个测试用例来调用 `uP_BFM` 实例中的读/写任务。 @@ -1220,7 +1220,7 @@ inst_harness.inst_BFM.Read(Data_in, i); // Data_in 为读数据, i 为读地 -![图 7-30 多顶层testbench结构](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-300-MultiTopTestbenchDemo.png!sign){width=600px} +![图 7-30 多顶层testbench结构](../images/post/2023-04-16-josh-verilog-part-7/2023-04-16-josh-verilog-part-7-300-MultiTopTestbenchDemo.png){width=600px} 在 testcase 代码中，如果需要调用 harness 下 `uP_BFM` 实例中的读/写任务，则需要在 testcase 中写类似如下代码： diff --git a/source/_posts/2023-04-18-josh-oap-part-1-1.md b/source/_posts/2023-04-18-josh-oap-part-1-1.md index ee44d44..1783633 100644 --- a/source/_posts/2023-04-18-josh-oap-part-1-1.md +++ b/source/_posts/2023-04-18-josh-oap-part-1-1.md @@ -21,13 +21,11 @@ tags: - 波束方向图 --- -# 阵列信号处理的目的及基本坐标系 - -  假设在空时场（space-time field）的某个区域内有一个或多个信号，同时在某些区域内存在噪声和/或干扰。在一些阵列信号处理的应用场景中，这些区域是部分重叠的。阵列可以利用信号的空域特征，对空时场域内的信号进行滤波。这种滤波可以用一种与角度或波数的相关性（in terms of a dependence upon angle or wavenumber）进行描述。从频域看，这种滤波是通过使用复增益对阵列输出进行加权，根据信号的空域相关性对信号进行增强或抑制来实现的。通常我们对空时场进行空域滤波的目的是：使得从一个（或一组）特定角度到来的信号通过有效的组合得到增强，抑制从其他角度到来的噪声或干扰。 +  假设空时场（space-time field）同时存在信号（signal）、噪声（noise）和/或干扰（interference），这些信号/干扰空时场中可能是重叠的。阵列（Array）可以利用信号的空域特征，对空时场域内的信号进行滤波，过滤的过程可以用角度或波数的函数来表示（in terms of a dependence upon angle or wavenumber）。从频域看，这种滤波通过使用复增益（complex gain）对阵列输出进行加权，可以根据信号的空域相关性对信号进行增强或抑制。对空时场进行空域滤波的目的是：使从一个或一组特定角度到来的信号通过有效的组合得到增强，抑制从其他角度到来的噪声或干扰。 -![图 1-1-1 球坐标系](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-010-SphericalCoordinareSystem.png!sign){width=600px} +![图 1-1-1 球坐标系](../images/post/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-010-SphericalCoordinareSystem.png){width=600px}   在分析之前首先需要明确采用的坐标系，如[图 1-1-1](#fig.1-1-1) 所示，直角坐标系和球坐标系的关系也在其中标明： @@ -43,6 +41,10 @@ z &= r \cos\theta # 阵列的基本模型 + + +![图 1-1-2 $N$ 阵元阵列](../images/post/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-020-NElementArray.png){width=600px} +   下面分析一个阵列对外部信号场的响应。阵列由一组全向阵元组成，阵元的位置为 $\left\{ \boldsymbol{p}_n \right\}_{n=0}^{N-1}$，如[图 1-1-2](#fig.1-1-2) 所示。阵列在各阵元处对信号场进行采样，产生一组信号，记为矢量 $\boldsymbol{f}\left(t, \boldsymbol{p}\right)$ $$\begin{equation} @@ -62,21 +64,17 @@ $$\begin{equation} {% endnote %} - - -![图 1-1-2 $N$ 阵元阵列](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-020-NElementArray.png!sign){width=600px} - -  将每个阵元的输出（即采样结果）通过冲激响应为 $h_n(\tau)$ 的线性时不变滤波器，求和可得阵列的输出 $y(t)$，如[图 1-1-3](#fig.1-1-3) 所示。假设观察间隔足够长（可以考虑为无限长），则阵列输出 $y(t)$ 可以写成卷积积分的形式： - -$$\begin{equation} -y(t) = \sum_{n=0}^{N-1} \int_{-\infty}^{\infty} h_n (t-\tau)f_n\left(\tau,\boldsymbol{p}_n\right) \mathrm{d} \tau -\end{equation}$$ - -![图 1-1-3 线性处理阵列](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-030-ArrayWithLinearProcessing.png!sign){width=600px} +![图 1-1-3 线性处理阵列](../images/post/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-030-ArrayWithLinearProcessing.png){width=600px} -可以用矢量符号表示为（即将标量结果向矢量模型进行直接扩展，a straightforward extension of scalar results to the vector model） +  将每个阵元的输出（即采样结果）通过冲激响应为 $h_n(t)$ 的线性时不变滤波器，求和可得阵列的输出 $y(t)$，如[图 1-1-3](#fig.1-1-3) 所示。假设观察间隔足够长（可以考虑为无限长），则阵列输出 $y(t)$ 可以写成卷积积分的形式： + +$$\begin{equation} +y(t) = \sum_{n=0}^{N-1} \int_{-\infty}^{\infty} h_n (t-\tau)f\left(\tau,\boldsymbol{p}_n\right) \mathrm{d} \tau +\end{equation}$$ + +用矢量符号表示为（即将标量结果向矢量模型进行直接扩展，a straightforward extension of scalar results to the vector model） @@ -87,11 +85,11 @@ y(t) = \int_{-\infty}^{\infty} \boldsymbol{h}^\mathrm{T} (t-\tau) \boldsymbol{f} 其中 $$\begin{equation} \label{ImpulseResponse} -\boldsymbol{h}(\tau) = \left[ \begin{array}{c} - h_0(\tau) \\ - h_1(\tau) \\ +\boldsymbol{h}(t) = \left[ \begin{array}{c} + h_0(t) \\ + h_1(t) \\ \vdots \\ - h_{N-1}(\tau) + h_{N-1}(t) \end{array} \right] \end{equation}$$ @@ -99,10 +97,7 @@ $$\begin{equation} \label{ImpulseResponse} 也可以把式 $\eqref{VectorFormOfLinearArrayOutputInTimeDomain}$ 给出的阵列输出在变换域表示为 $$\begin{equation} -\begin{aligned} - Y(\omega) &= \int_{-\infty}^{\infty} y(t) e^{-j\omega t} \mathrm{d} t \\ - &= \boldsymbol{H}^\mathrm{T}(\omega) \boldsymbol{F}(\omega) -\end{aligned} + Y(\omega) = \boldsymbol{H}^\mathrm{T}(\omega) \boldsymbol{F}(\omega) \end{equation}$$ 其中 @@ -112,7 +107,7 @@ $$\begin{equation} \end{equation}$$ $$\begin{equation} \label{SampleVectorInFreqDomain} -\boldsymbol{F} \left(\omega,\boldsymbol{p}\right) = \int_{-\infty}^{\infty} \boldsymbol{f}\left(\tau,\boldsymbol{p}\right) e^{-j\omega t} \mathrm{d} t +\boldsymbol{F} \left(\omega,\boldsymbol{p}\right) = \int_{-\infty}^{\infty} \boldsymbol{f}\left(t,\boldsymbol{p}\right) e^{-j\omega t} \mathrm{d} t \end{equation}$$ 在大多数情况下，可以去掉式 $\eqref{SampleVectorInFreqDomain}$ 中左边的 $\boldsymbol{p}$，直接使用 $\boldsymbol{F}(\omega)$ 。 @@ -123,9 +118,9 @@ $$\begin{equation} \label{SampleVectorInFreqDomain} -![图 1-1-4 具有平面波输入的阵列](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-040-ArrayWithPlaneWaveInput.png!sign){width=600px} +![图 1-1-4 具有平面波输入的阵列](../images/post/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-040-ArrayWithPlaneWaveInput.png){width=600px} -  由于信号到达不同阵元的时间不同，因此第一种方式强调信号到达不同阵元的时间延时。设 $f(t)$ 是**在坐标系原点接收到的信号**，其在变换域表示为 $F (\omega)$，则 +  由于信号到达不同阵元的时间不同，设 $f(t)$ 是**在坐标系原点接收到的信号**，其在变换域表示为 $F (\omega)$，则 $$\begin{equation} \label{DelayedSignal} \boldsymbol{f}(t, \boldsymbol{p}) = \left[ @@ -183,7 +178,7 @@ $$\begin{equation} \label{RelativeDelayWithDirectionCosine} 根据式 $\eqref{DelayedSignal}$，$\boldsymbol{F}(\omega)$ 的第 $n$ 个分量为（利用 Fourier 变换的时移性质） $$\begin{equation} - F_n(\omega) = \int_{-\infty}^{\infty} e^{j \omega t} f(t - \tau_n) \mathrm{d} t = e^{j \omega \tau_n} F (\omega) + F_n(\omega) = \int_{-\infty}^{\infty} e^{j \omega t} f_n(t - \tau_n) \mathrm{d} t = e^{j \omega \tau_n} F (\omega) \end{equation}$$ 其中 @@ -240,7 +235,7 @@ $$\begin{equation} -![图 1-1-5 延时-求和波束形成器](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-050-DelayAndSumBeamformer.png!sign){width=600px} +![图 1-1-5 延时-求和波束形成器](../images/post/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-050-DelayAndSumBeamformer.png){width=600px}   如[图 1-1-5](#fig.1-1-5) 所示，把每个阵元的输入信号进行时移、相加、归一化，使得输出为 $f(t)$，其中 @@ -264,7 +259,7 @@ $$\begin{equation} # 单位平面波模型 -  现在回更到一般的问题，要确定阵列对一个输入场 $\boldsymbol{f}(t, \boldsymbol{p})$ 的响应，可以通过之前给出的卷积求和操作来实现，但更有用的方法是首先确定阵列对单位平面波（unit plane wave）的响应，响应为单位平面波时域（弧度）频率 $\omega$ 和波数 $\boldsymbol{k}$ 的函数。（利用叠加的复指数基函数对一个线性时不变系统进行分析的系统理论方法可以扩展到空时信号的情况。） +  更一般的，要确定阵列对一个输入信号场 $\boldsymbol{f}(t, \boldsymbol{p})$ 的响应，可以通过之前给出的卷积求和操作来实现，但更有用的方法是确定阵列对单位平面波（unit plane wave）的响应，将响应表示为时域（弧度）频率 $\omega$ 和波数 $\boldsymbol{k}$ 的函数，然后将线性时不变系统中复指数基函数叠加分析的系统理论方法扩展到空时信号的情况。   取基函数 @@ -284,7 +279,7 @@ $$\begin{equation} \label{ArrayResponseToUnitPlaneWaveInTimeDomain} y \left( t, \boldsymbol{k} \right) = \boldsymbol{H}^\mathrm{T} (\omega) \boldsymbol{v}_{\boldsymbol{k}}\left(\boldsymbol{k}\right) e^{j\omega t} \end{equation}$$ -其中 $\boldsymbol{H} (\omega)$ 是式 $\eqref{ImpulseResponse}$ 中 $\boldsymbol{h}(\tau)$ 的傅里叶变换。 +其中 $\boldsymbol{H} (\omega)$ 是式 $\eqref{ImpulseResponse}$ 中 $\boldsymbol{h}(t)$ 的傅里叶变换。   这里使用 $y \left( t, \boldsymbol{k} \right)$ 来强调输出和输入波数 $\boldsymbol{k}$ 的关系。时域上的相关性体现在输出是一个复指数，和输入平面波具有相同的频率。在频域内，$\eqref{ArrayResponseToUnitPlaneWaveInTimeDomain}$ 可以写成下面的形式： @@ -384,13 +379,13 @@ $$\begin{equation} -![图 1-1-6 利用移相器实现的窄带波束形成器](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-060-NarrowbandBeamformerImplementedUsingPhaseShifters.png!sign){width=600px} +![图 1-1-6 利用移相器实现的窄带波束形成器](../images/post/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-060-NarrowbandBeamformerImplementedUsingPhaseShifters.png){width=600px}   可以发现，在很多的应用中，我们都想要调整每个传感器输出的增益和相位，以得到一个理想的波束方向图。这就产生了在[图 1-1-6(a)](#fig.1-1-6) 中给出的窄带模型。$w_n^\ast$ 是复权值，可以用一个增益和移相器的级联来实现，如[图 1-1-6(b)](#fig.1-1-6) 所示。 -![图 1-1-7 一般窄带波束形成器](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-070-GeneralNarrowbandBeamformer.png!sign){width=600px} +![图 1-1-7 一般窄带波束形成器](../images/post/2023-04-18-josh-oap-part-1-1/2023-04-18-josh-oap-part-1-1-070-GeneralNarrowbandBeamformer.png){width=600px}   另外一种实现的结构见[图 1-1-6(c)](#fig.1-1-6)。在一些情况下，我们利用正交解调，并在对基带信号进行复加权来实现波束形成器，实际是在一个正交分量上使用 $\Re[w_n^\ast]$ 进行加权，在另外一个正交分量上使用 $\Im[w_n^\ast]$ 进行加权，结果是相等的。 diff --git a/source/_posts/2023-04-20-josh-oap-part-1-2.md b/source/_posts/2023-04-20-josh-oap-part-1-2.md index cc4aaac..daa0c91 100644 --- a/source/_posts/2023-04-20-josh-oap-part-1-2.md +++ b/source/_posts/2023-04-20-josh-oap-part-1-2.md @@ -28,7 +28,7 @@ date: 2023-04-20 00:14:31 -![图 1-2-1 放置在 $z$ 轴上的线阵](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-20-josh-oap-part-1-2/2023-04-20-josh-oap-part-1-2-010-LinearArrayAlongZAaxis.png!sign){width=600px} +![图 1-2-1 放置在 $z$ 轴上的线阵](../images/post/2023-04-20-josh-oap-part-1-2/2023-04-20-josh-oap-part-1-2-010-LinearArrayAlongZAaxis.png){width=600px} diff --git a/source/_posts/2023-04-20-josh-oap-part-1-3.md b/source/_posts/2023-04-20-josh-oap-part-1-3.md index 9e20781..17e4a43 100644 --- a/source/_posts/2023-04-20-josh-oap-part-1-3.md +++ b/source/_posts/2023-04-20-josh-oap-part-1-3.md @@ -69,11 +69,11 @@ $$\begin{equation} -![图 1-3-1 $\boldsymbol{\varUpsilon}(\psi): \psi = \frac{2\pi}{\lambda} d \cos\theta, N=11$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-20-josh-oap-part-1-3/2023-04-20-josh-oap-part-1-3-010-FrequencyWavenumberResponseFunction.svg){width=1000px} +![图 1-3-1 $\boldsymbol{\varUpsilon}(\psi): \psi = \frac{2\pi}{\lambda} d \cos\theta, N=11$](../images/post/2023-04-20-josh-oap-part-1-3/2023-04-20-josh-oap-part-1-3-010-FrequencyWavenumberResponseFunction.svg){width=1000px} -![图 1-3-2 用 dB 表示 $\left|\boldsymbol{\varUpsilon}(\psi)\right|$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-20-josh-oap-part-1-3/2023-04-20-josh-oap-part-1-3-020-FrequencyWavenumberResponseFunctionInDB.svg){width=1000px} +![图 1-3-2 用 dB 表示 $\left|\boldsymbol{\varUpsilon}(\psi)\right|$](../images/post/2023-04-20-josh-oap-part-1-3/2023-04-20-josh-oap-part-1-3-020-FrequencyWavenumberResponseFunctionInDB.svg){width=1000px} {% note primary MATLAB Code %} @@ -164,7 +164,7 @@ $$\begin{equation} -![图 1-3-3 在极坐标系中画出 $B_\theta(\theta)$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-20-josh-oap-part-1-3/2023-04-20-josh-oap-part-1-3-030-PloarPlotOfBeamPatternInAngleSpace.svg){width=800px} +![图 1-3-3 在极坐标系中画出 $B_\theta(\theta)$](../images/post/2023-04-20-josh-oap-part-1-3/2023-04-20-josh-oap-part-1-3-030-PloarPlotOfBeamPatternInAngleSpace.svg){width=800px} {% note primary MATLAB Code %} @@ -200,7 +200,7 @@ h=polardb(ang,G,-40); -![图 1-3-4 $d = \lambda/2, N=10$，线阵的 $\left|\boldsymbol{\varUpsilon}_\psi(\psi)\right|$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-20-josh-oap-part-1-3/2023-04-20-josh-oap-part-1-3-040-AbsOfFWRFForALinearArray.svg){width=1000px} +![图 1-3-4 $d = \lambda/2, N=10$，线阵的 $\left|\boldsymbol{\varUpsilon}_\psi(\psi)\right|$](../images/post/2023-04-20-josh-oap-part-1-3/2023-04-20-josh-oap-part-1-3-040-AbsOfFWRFForALinearArray.svg){width=1000px} {% note primary MATLAB Code %} @@ -322,7 +322,7 @@ set(gcf,'Position',[0 0 800 800]) -![图 1-3-5 波束方向图的主波束](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-20-josh-oap-part-1-3/2023-04-20-josh-oap-part-1-3-050-MainLobeOfBeamPattern.svg){width=700px} +![图 1-3-5 波束方向图的主波束](../images/post/2023-04-20-josh-oap-part-1-3/2023-04-20-josh-oap-part-1-3-050-MainLobeOfBeamPattern.svg){width=700px} {% note primary MATLAB Code %} @@ -536,7 +536,7 @@ $$\begin{equation} -![图 1-3-6 阵元间距对波束方向图的影响：(a) $d=\lambda/4$；(b) $d=\lambda/2$；(c) $d=\lambda$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-20-josh-oap-part-1-3/2023-04-20-josh-oap-part-1-3-060-%20EffectOfElementSpacingOnBeamPattern.svg){width=1000px} +![图 1-3-6 阵元间距对波束方向图的影响：(a) $d=\lambda/4$；(b) $d=\lambda/2$；(c) $d=\lambda$](../images/post/2023-04-20-josh-oap-part-1-3/2023-04-20-josh-oap-part-1-3-060-%20EffectOfElementSpacingOnBeamPattern.svg){width=1000px} {% note primary MATLAB Code %} diff --git a/source/_posts/2023-04-22-josh-oap-part-1-4.md b/source/_posts/2023-04-22-josh-oap-part-1-4.md index 5bb9721..8aedf7c 100644 --- a/source/_posts/2023-04-22-josh-oap-part-1-4.md +++ b/source/_posts/2023-04-22-josh-oap-part-1-4.md @@ -37,7 +37,7 @@ date: 2023-04-22 18:17:52 -![图 1-4-1 利用延时实现阵列调向](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-22-josh-oap-part-1-4/2023-04-22-josh-oap-part-1-4-010-ArraySteeringWithDelays.png!sign){width=700px} +![图 1-4-1 利用延时实现阵列调向](../images/post/2023-04-22-josh-oap-part-1-4/2023-04-22-josh-oap-part-1-4-010-ArraySteeringWithDelays.png){width=700px}   [1.2 节][]开头的简单例子说明了把阵列调向某个特定方向的主要思想，调向在波数空间的影响是很直接的。考虑[图 1-4-1](#fig.1-4-1) 中的处理器，输入到调向环节的基函数为 @@ -128,7 +128,7 @@ $$\begin{equation} -![图 1-4-2 阵列调向对栅瓣的影响：$N=10$，(a) $d=2\lambda/3, \bar\theta = 30^\circ$；(b) $d=\lambda/2, \bar\theta = 90^\circ$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-22-josh-oap-part-1-4/2023-04-22-josh-oap-part-1-4-020-%20EffectOfSteeringOnTheGratingLobes.svg){width=1000px} +![图 1-4-2 阵列调向对栅瓣的影响：$N=10$，(a) $d=2\lambda/3, \bar\theta = 30^\circ$；(b) $d=\lambda/2, \bar\theta = 90^\circ$](../images/post/2023-04-22-josh-oap-part-1-4/2023-04-22-josh-oap-part-1-4-020-%20EffectOfSteeringOnTheGratingLobes.svg){width=1000px} {% note primary MATLAB Code%} @@ -201,7 +201,7 @@ $$\begin{equation} -![图 1-4-3 10 阵元均匀阵列（$d = \lambda/2$）扫描到 30°（和正侧向夹角为 60°）时的波束方向图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-22-josh-oap-part-1-4/2023-04-22-josh-oap-part-1-4-030-BeamPatternFor10ElementUniformArrayScannedTo30Degree.svg){width=800px} +![图 1-4-3 10 阵元均匀阵列（$d = \lambda/2$）扫描到 30°（和正侧向夹角为 60°）时的波束方向图](../images/post/2023-04-22-josh-oap-part-1-4/2023-04-22-josh-oap-part-1-4-030-BeamPatternFor10ElementUniformArrayScannedTo30Degree.svg){width=800px} {% note primary MATLAB Code %} @@ -268,7 +268,7 @@ $$\begin{equation} \label{HPBWOfUWLA} -![图 1-4-4 HPBW 和阵列调向角的关系：标准线阵，采用均匀加权](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-22-josh-oap-part-1-4/2023-04-22-josh-oap-part-1-4-040-HPBWVersusSteeringAngleStandardUWLA.svg){width=1000px} +![图 1-4-4 HPBW 和阵列调向角的关系：标准线阵，采用均匀加权](../images/post/2023-04-22-josh-oap-part-1-4/2023-04-22-josh-oap-part-1-4-040-HPBWVersusSteeringAngleStandardUWLA.svg){width=1000px} {% note primary MATLAB Code %} @@ -335,7 +335,7 @@ $$\begin{equation} \label{HPBWWithSmallAngle} -![图 1-4-5 长度降低了 $\cos\bar\theta_\mathrm{T}$ 倍的等效阵列](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-22-josh-oap-part-1-4/2023-04-22-josh-oap-part-1-4-050-EffectiveArrayLength.png!sign){width=600px} +![图 1-4-5 长度降低了 $\cos\bar\theta_\mathrm{T}$ 倍的等效阵列](../images/post/2023-04-22-josh-oap-part-1-4/2023-04-22-josh-oap-part-1-4-050-EffectiveArrayLength.png){width=600px}   对于 $Nd \geqslant 5\lambda$，在正侧向附近，式 $\eqref{HPBWWithSmallAngle}$ 的误差在 0.2% 以内，在扫描极限附近，误差在 4% 以内。 @@ -347,7 +347,7 @@ $$\begin{equation} \label{HPBWOfEndfireUWLA} -![图 1-4-6 一个标准 10 阵元线阵。采用均匀幅度加权时在端射时的波束方向图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-22-josh-oap-part-1-4/2023-04-22-josh-oap-part-1-4-060-BeamPatternOfStandard10ElementUWLAAtEndfire.svg){width=800px} +![图 1-4-6 一个标准 10 阵元线阵。采用均匀幅度加权时在端射时的波束方向图](../images/post/2023-04-22-josh-oap-part-1-4/2023-04-22-josh-oap-part-1-4-060-BeamPatternOfStandard10ElementUWLAAtEndfire.svg){width=800px} {% note primary MATLAB Code %} diff --git a/source/_posts/2023-04-24-josh-oap-part-1-5.md b/source/_posts/2023-04-24-josh-oap-part-1-5.md index 8d0ef89..a7fd8dd 100644 --- a/source/_posts/2023-04-24-josh-oap-part-1-5.md +++ b/source/_posts/2023-04-24-josh-oap-part-1-5.md @@ -346,7 +346,7 @@ $$ -![图 1-5-1 具有阵元位置误差的阵列](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-04-24-josh-oap-part-1-5/2023-04-24-josh-oap-part-1-5-010-ArrayWithPositionErrors.png!sign){width=700px} +![图 1-5-1 具有阵元位置误差的阵列](../images/post/2023-04-24-josh-oap-part-1-5/2023-04-24-josh-oap-part-1-5-010-ArrayWithPositionErrors.png){width=700px}   后面会分析最优处理器对于增益和相位误差、传感器定位不准确等因素的敏感度。这里总结一下[图 1-5-1](#fig.1-5-1) 中阵列的典型结果，设计的目标是使得在没有阵列扰动的情况下，从正侧向入射到阵列的信号无畸变地通过，即有 diff --git a/source/_posts/2023-06-19-josh-oap-part-2-1.md b/source/_posts/2023-06-19-josh-oap-part-2-1.md index f4d99a8..dfbe5ea 100644 --- a/source/_posts/2023-06-19-josh-oap-part-2-1.md +++ b/source/_posts/2023-06-19-josh-oap-part-2-1.md @@ -109,7 +109,7 @@ $$\begin{equation} -![图 2-1-1 均匀加权和 Cosine 加权的波束方向图: $N = 11$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-010-BeamPatternForUniformAndCosineWeighting.svg){width=700px} +![图 2-1-1 均匀加权和 Cosine 加权的波束方向图: $N = 11$](../images/post/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-010-BeamPatternForUniformAndCosineWeighting.svg){width=700px} {% note primary MATLAB Code %} @@ -181,7 +181,7 @@ $$\begin{equation} -![图 2-1-2 升 Cosine 加权的波束方向图: $N = 11$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-020-BeamPatternForRaisedCosineWeighting.svg){width=700px} +![图 2-1-2 升 Cosine 加权的波束方向图: $N = 11$](../images/post/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-020-BeamPatternForRaisedCosineWeighting.svg){width=700px} {% note primary MATLAB Code %} @@ -255,7 +255,7 @@ $$\begin{equation} -![图 2-1-3 Cosine$^m$ 加权的波束方向图: $N = 11$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-030-BeamPatternForCosineMWeighting.svg){width=700px} +![图 2-1-3 Cosine$^m$ 加权的波束方向图: $N = 11$](../images/post/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-030-BeamPatternForCosineMWeighting.svg){width=700px} {% note primary MATLAB Code %} @@ -343,7 +343,7 @@ $$\begin{equation} -![图 2-1-4 Hann 加权、Hamming 加权和 Blackman-Harris 加权的波束方向图: $N = 11$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-040-BeamPatternForHannHammingAndBlackmanHarrisWeighting.svg){width=700px} +![图 2-1-4 Hann 加权、Hamming 加权和 Blackman-Harris 加权的波束方向图: $N = 11$](../images/post/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-040-BeamPatternForHannHammingAndBlackmanHarrisWeighting.svg){width=700px} {% note primary MATLAB Code %} @@ -497,11 +497,11 @@ DPSS 加权的波束方向图参数为: -![图 2-1-5 离散长球序列: $\psi_0=0.1\pi,0.2\pi,0.4\pi$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-050-DiscreteProlateSpheroidalSequences.svg){width=700px} +![图 2-1-5 离散长球序列: $\psi_0=0.1\pi,0.2\pi,0.4\pi$](../images/post/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-050-DiscreteProlateSpheroidalSequences.svg){width=700px} -![图 2-1-6 DPSS 加权的波束方向图和 $\psi_0$ 的关系: $N = 11$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-060-BeamPatternForDPSSWeighting.svg){width=700px} +![图 2-1-6 DPSS 加权的波束方向图和 $\psi_0$ 的关系: $N = 11$](../images/post/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-060-BeamPatternForDPSSWeighting.svg){width=700px} {% note primary MATLAB Code %} @@ -650,7 +650,7 @@ $$\begin{equation} -![图 2-1-7 Kaiser 加权: (a) $\beta=3$ 和 $6$ 时的权值；(b) $\beta=3$ 和 $6$ 时的波束方向图](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-070-KaiserWeighting.svg){width=700px} +![图 2-1-7 Kaiser 加权: (a) $\beta=3$ 和 $6$ 时的权值；(b) $\beta=3$ 和 $6$ 时的波束方向图](../images/post/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-070-KaiserWeighting.svg){width=700px} {% note primary MATLAB Code %} @@ -728,7 +728,7 @@ set(gcf,'Position',[0 0 600 600]) -![图 2-1-8 Kaiser 加权的波束方向图：$\beta = 3$，$N=11,21$ 和 $41$](https://josh-blog-1257563604.cos.ap-beijing.myqcloud.com/img/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-080-BeamPatternsForKaiserWeighting.svg){width=700px} +![图 2-1-8 Kaiser 加权的波束方向图：$\beta = 3$，$N=11,21$ 和 $41$](../images/post/2023-06-19-josh-oap-part-2-1/2023-06-19-josh-oap-part-2-1-080-BeamPatternsForKaiserWeighting.svg){width=700px} {% note primary MATLAB Code %} diff --git a/source/images/post/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-010-DesignASquareRootRaisedCosineFilterExample-01.png b/source/images/post/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-010-DesignASquareRootRaisedCosineFilterExample-01.png new file mode 100644 index 0000000..db14fa1 Binary files /dev/null and b/source/images/post/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-010-DesignASquareRootRaisedCosineFilterExample-01.png differ diff --git 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b/source/images/post/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-030-ImpulseResponsesOfNormalAndSquareRootRaisedCosineFiltersExample-02.png new file mode 100644 index 0000000..3d68ecb Binary files /dev/null and b/source/images/post/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-030-ImpulseResponsesOfNormalAndSquareRootRaisedCosineFiltersExample-02.png differ diff --git a/source/images/post/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-030-ImpulseResponsesOfNormalAndSquareRootRaisedCosineFiltersExample-02.svg b/source/images/post/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-030-ImpulseResponsesOfNormalAndSquareRootRaisedCosineFiltersExample-02.svg new file mode 100644 index 0000000..4c5e67c --- /dev/null +++ b/source/images/post/2020-11-25-matlab-rcosdesign/2020-11-25-matlab-rcosdesign-030-ImpulseResponsesOfNormalAndSquareRootRaisedCosineFiltersExample-02.svg @@ -0,0 +1,281 @@ + + +024681012Samples-0.100.10.20.30.40.50.6AmplitudeImpulse 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