diff --git a/source/_posts/2020-11-27-josh-verilog-part-1.md b/source/_posts/2020-11-27-josh-verilog-part-1.md index f5f306e..efa44c5 100644 --- a/source/_posts/2020-11-27-josh-verilog-part-1.md +++ b/source/_posts/2020-11-27-josh-verilog-part-1.md @@ -1,5 +1,5 @@ --- -title: Josh 的学习笔记之 Verilog（Part 1 —— 初识 HDL 设计方法） +title: "Josh's Notes: Verilog（Part 1 — 初识 HDL 设计方法）" date: 2020-11-27 22:58:07 tags: - Verilog diff --git a/source/_posts/2020-11-28-josh-verilog-part-2.md b/source/_posts/2020-11-28-josh-verilog-part-2.md index e9cec9f..e45afd6 100644 --- a/source/_posts/2020-11-28-josh-verilog-part-2.md +++ b/source/_posts/2020-11-28-josh-verilog-part-2.md @@ -1,5 +1,5 @@ --- -title: Josh 的学习笔记之 Verilog（Part 2 —— Verilog 语言基础） +title: "Josh's Notes: Verilog（Part 2 — Verilog 语言基础）" date: 2020-11-28 11:42:50 tags: - Verilog diff --git a/source/_posts/2020-11-30-josh-verilog-part-3.md b/source/_posts/2020-11-30-josh-verilog-part-3.md index 109e696..590d25f 100644 --- a/source/_posts/2020-11-30-josh-verilog-part-3.md +++ b/source/_posts/2020-11-30-josh-verilog-part-3.md @@ -1,5 +1,5 @@ --- -title: Josh 的学习笔记之 Verilog（Part 3 —— 描述方式和设计层次） +title: "Josh's Notes: Verilog（Part 3 — 描述方式和设计层次）" date: 2020-11-30 00:57:49 tags: - Verilog diff --git a/source/_posts/2020-12-02-josh-verilog-part-4.md b/source/_posts/2020-12-02-josh-verilog-part-4.md index efa51b0..fd1aca3 100644 --- a/source/_posts/2020-12-02-josh-verilog-part-4.md +++ b/source/_posts/2020-12-02-josh-verilog-part-4.md @@ -1,5 +1,5 @@ --- -title: Josh 的学习笔记之 Verilog（Part 4 —— RTL 概念与常用 RTL 建模） +title: "Josh's Notes: Verilog（Part 4 — RTL 概念与常用 RTL 建模）" mathjax: true comments: true copyright: true diff --git a/source/_posts/2020-12-05-josh-verilog-part-5.md b/source/_posts/2020-12-05-josh-verilog-part-5.md index 8b778d3..dcb26b2 100644 --- a/source/_posts/2020-12-05-josh-verilog-part-5.md +++ b/source/_posts/2020-12-05-josh-verilog-part-5.md @@ -1,5 +1,5 @@ --- -title: Josh 的学习笔记之 Verilog（Part 5 —— RTL 设计与编码指导） +title: "Josh's Notes: Verilog（Part 5 — RTL 设计与编码指导）" mathjax: true comments: true copyright: true diff --git a/source/_posts/2021-12-08-josh-msp-part-1.md b/source/_posts/2021-12-08-josh-msp-part-1.md index 0fa9889..40a3649 100644 --- a/source/_posts/2021-12-08-josh-msp-part-1.md +++ b/source/_posts/2021-12-08-josh-msp-part-1.md @@ -1,5 +1,5 @@ --- -title: Josh 的学习笔记之多抽样率信号处理 (Part 1 —— 抽样率转换) +title: "Josh's Notes: 多抽样率信号处理 (Part 1 — 抽样率转换)" mathjax: true comments: true copyright: true diff --git a/source/_posts/2022-05-30-josh-systemverilog-1.md b/source/_posts/2022-05-30-josh-systemverilog-1.md index 36bf3ee..b51af5b 100644 --- a/source/_posts/2022-05-30-josh-systemverilog-1.md +++ b/source/_posts/2022-05-30-josh-systemverilog-1.md @@ -1,5 +1,5 @@ --- -title: 'Josh''s Notes: SystemVerilog 验证 (Part 1 — 验证导论)' +title: "Josh's Notes: SystemVerilog 验证（Part 1 — 验证导论）" mathjax: true comments: true copyright: true diff --git a/source/_posts/2022-05-31-josh-systemverilog-2.md b/source/_posts/2022-05-31-josh-systemverilog-2.md index 3707f69..ce8a90d 100644 --- a/source/_posts/2022-05-31-josh-systemverilog-2.md +++ b/source/_posts/2022-05-31-josh-systemverilog-2.md @@ -1,5 +1,5 @@ --- -title: 'Josh''s Notes: SystemVerilog 验证 (Part 2 — 数据类型)' +title: "Josh's Notes: SystemVerilog 验证（Part 2 — 数据类型）" mathjax: true comments: true copyright: true diff --git a/source/_posts/2022-06-02-josh-systemverilog-3.md b/source/_posts/2022-06-02-josh-systemverilog-3.md index bd49ac4..6e9cfcd 100644 --- a/source/_posts/2022-06-02-josh-systemverilog-3.md +++ b/source/_posts/2022-06-02-josh-systemverilog-3.md @@ -1,5 +1,5 @@ --- -title: 'Josh''s Notes: SystemVerilog 验证 (Part 3 — 过程语句和子程序)' +title: "Josh's Notes: SystemVerilog 验证（Part 3 — 过程语句和子程序）" mathjax: true comments: true copyright: true diff --git a/source/_posts/2023-04-14-josh-dsp-part-1.md b/source/_posts/2023-04-14-josh-dsp-part-1.md index aef59b5..edac5bb 100644 --- a/source/_posts/2023-04-14-josh-dsp-part-1.md +++ b/source/_posts/2023-04-14-josh-dsp-part-1.md @@ -1,5 +1,5 @@ --- -title: Josh 的学习笔记之数字信号处理（Part 1——离散时间信号和系统分析基础） +title: "Josh's Review: 数字信号处理（Part 1 — 离散时间信号和系统分析基础）" mathjax: true comments: true copyright: true @@ -8,7 +8,7 @@ toc: number: false wrap: true expand_all: false - max_depth: 3 + max_depth: 4 abbrlink: 1391fb05 date: 2023-04-14 17:24:45 tags: diff --git a/source/_posts/2023-04-14-josh-dsp-part-2.md b/source/_posts/2023-04-14-josh-dsp-part-2.md index 8617d07..6b19d33 100644 --- a/source/_posts/2023-04-14-josh-dsp-part-2.md +++ b/source/_posts/2023-04-14-josh-dsp-part-2.md @@ -1,5 +1,5 @@ --- -title: Josh 的学习笔记之数字信号处理（Part 2——离散傅里叶级数 DFS） +title: "Josh's Review: 数字信号处理（Part 2 — 离散傅里叶级数 DFS）" mathjax: true comments: true copyright: true @@ -8,7 +8,7 @@ toc: number: false wrap: true expand_all: false - max_depth: 3 + max_depth: 4 tags: - 数字信号和处理 - DSP diff --git a/source/_posts/2023-04-14-josh-dsp-part-3.md b/source/_posts/2023-04-14-josh-dsp-part-3.md index c7b224f..cc986e5 100644 --- a/source/_posts/2023-04-14-josh-dsp-part-3.md +++ b/source/_posts/2023-04-14-josh-dsp-part-3.md @@ -1,5 +1,5 @@ --- -title: Josh 的学习笔记之数字信号处理（Part 3——离散傅里叶变换 DFT） +title: "Josh's Review: 数字信号处理（Part 3 — 离散傅里叶变换 DFT）" mathjax: true comments: true copyright: true diff --git a/source/_posts/2023-04-14-josh-dsp-part-4.md b/source/_posts/2023-04-14-josh-dsp-part-4.md index 790649e..32ef184 100644 --- a/source/_posts/2023-04-14-josh-dsp-part-4.md +++ b/source/_posts/2023-04-14-josh-dsp-part-4.md @@ -1,5 +1,5 @@ --- -title: Josh 的学习笔记之数字信号处理（Part 4——快速傅里叶变换 FFT） +title: "Josh's Review: 数字信号处理（Part 4 — 快速傅里叶变换 FFT）" mathjax: true comments: true copyright: true @@ -8,7 +8,7 @@ toc: number: false wrap: true expand_all: false - max_depth: 3 + max_depth: 4 abbrlink: 7c6d68a2 date: 2023-04-14 23:11:52 tags: diff --git a/source/_posts/2023-04-15-josh-dsp-part-5.md b/source/_posts/2023-04-15-josh-dsp-part-5.md index ddf5a60..613b26d 100644 --- a/source/_posts/2023-04-15-josh-dsp-part-5.md +++ b/source/_posts/2023-04-15-josh-dsp-part-5.md @@ -1,12 +1,12 @@ --- -title: Josh 的学习笔记之数字信号处理（Part 5——部分 FFT 蝶形图） +title: "Josh's Review: 数字信号处理（Part 5 — 部分 FFT 蝶形图）" mathjax: true comments: true copyright: true toc: enable: true number: false - wrap: ture + wrap: true expand_all: false max_depth: 4 abbrlink: 14fc3f1c diff --git a/source/_posts/2023-04-15-josh-dsp-part-6.md b/source/_posts/2023-04-15-josh-dsp-part-6.md index 9c55368..1bc88c2 100644 --- a/source/_posts/2023-04-15-josh-dsp-part-6.md +++ b/source/_posts/2023-04-15-josh-dsp-part-6.md @@ -1,12 +1,12 @@ --- -title: Josh 的学习笔记之数字信号处理（Part 6——数字滤波器的基本结构） +title: "Josh's Review: 数字信号处理（Part 6 — 数字滤波器的基本结构）" mathjax: true comments: true copyright: true toc: enable: true number: false - wrap: ture + wrap: true expand_all: false max_depth: 4 abbrlink: 8df56ea6 diff --git a/source/_posts/2023-04-15-josh-dsp-part-7.md b/source/_posts/2023-04-15-josh-dsp-part-7.md index 69f5842..12fd91c 100644 --- a/source/_posts/2023-04-15-josh-dsp-part-7.md +++ b/source/_posts/2023-04-15-josh-dsp-part-7.md @@ -1,12 +1,12 @@ --- -title: Josh 的学习笔记之数字信号处理（Part 7——数字滤波器设计） +title: "Josh's Review: 数字信号处理（Part 7 — 数字滤波器设计）" mathjax: true comments: true copyright: true toc: enable: true number: false - wrap: ture + wrap: true expand_all: false max_depth: 4 tags: diff --git a/source/_posts/2023-04-16-josh-verilog-part-6.md b/source/_posts/2023-04-16-josh-verilog-part-6.md index 8c4e4f7..c9f1880 100644 --- a/source/_posts/2023-04-16-josh-verilog-part-6.md +++ b/source/_posts/2023-04-16-josh-verilog-part-6.md @@ -1,5 +1,5 @@ --- -title: Josh 的学习笔记之 Verilog（Part 6——如何写好状态机） +title: "Josh's Notes: Verilog（Part 6 —— 如何写好状态机）" mathjax: false comments: true copyright: true diff --git a/source/_posts/2023-04-16-josh-verilog-part-7.md b/source/_posts/2023-04-16-josh-verilog-part-7.md index f26237f..1feedd8 100644 --- a/source/_posts/2023-04-16-josh-verilog-part-7.md +++ b/source/_posts/2023-04-16-josh-verilog-part-7.md @@ -1,5 +1,5 @@ --- -title: Josh 的学习笔记之 Verilog（Part 7——逻辑验证与 testbench 编写） +title: "Josh's Notes: Verilog（Part 7 —— 逻辑验证与 testbench 编写）" mathjax: false comments: true copyright: true