From 5817c5f92619e3b4030983f7ea9604956a48e0d1 Mon Sep 17 00:00:00 2001 From: Josh Gao Date: Wed, 13 Nov 2024 14:10:07 +0800 Subject: [PATCH] =?UTF-8?q?feat:=20=E8=BF=81=E7=A7=BB=E4=BB=93=E5=BA=93,?= =?UTF-8?q?=E4=BD=BF=E7=94=A8vivado=202024.1.2=E5=BC=80=E5=8F=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitattributes | 23 + .gitignore | 20 + .gitmodules | 3 + dl814_k7_cal_coarse/.gitignore | 119 + .../impl_1/debug_nets.ltx | 6799 ++++++++++++ .../impl_1/system_top.bit | 3 + .../impl_1/system_top.ltx | 6799 ++++++++++++ .../new/k7401t_ad9516_2ad9361_physical.xdc | 220 + .../new/k7410t_ad9516_2ad9361_timing.xdc | 4 + .../sim_1/new/tb_accum.v | 160 + .../sim_1/new/tb_acorr.v | 105 + .../sim_1/new/tb_null_ctrl.v | 80 + .../sim_1/new/tb_rx_pre.v | 285 + .../sim_1/new/tb_rx_pre_test.v | 278 + .../sim_1/new/tb_rx_test.v | 85 + .../sim_1/new/tb_tx_pre_process.v | 93 + .../sim_1/new/tb_xpm_cdc_pulse.v | 86 + .../system_bd_axi_gpio_0_0.xci | 375 + .../system_bd_axi_spi_engine_0_0.xci | 294 + .../system_bd_clk_wiz_1_0.xci | 658 ++ .../system_bd_dlmb_bram_if_cntlr_0.xci | 363 + .../system_bd_dlmb_v10_0.xci | 163 + .../system_bd_ilmb_bram_if_cntlr_0.xci | 363 + .../system_bd_ilmb_v10_0.xci | 163 + .../system_bd_lmb_bram_0.xci | 295 + .../system_bd_mdm_riscv_0.xci | 174 + .../system_bd_microblaze_ps_axi_periph_0.xci | 353 + .../system_bd_microblaze_ps_riscv_0.xci | 654 ++ .../system_bd_rst_clk_wiz_1_100M_0.xci | 196 + .../system_bd_spi_engine_execution_0_0.xci | 176 + .../ip/system_bd_xbar_0/system_bd_xbar_0.xci | 1523 +++ .../sources_1/bd/system_bd/system_bd.bd | 1612 +++ .../sources_1/bd/system_bd/system_bd.bda | 295 + .../sources_1/bd/system_bd/ui/bd_c6d0cb12.ui | 45 + .../sources_1/bd/system_bd/ui/bd_e4e34314.ui | 30 + .../ad9361_clk_gen_cmos_2t2r.xci | 714 ++ .../sources_1/ip/ad9361_fifo/ad9361_fifo.xci | 480 + .../ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci | 653 ++ .../ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci | 714 ++ .../sources_1/ip/atan2_16b/atan2_16b.xci | 189 + .../sources_1/ip/cmpy_12x12/cmpy_12x12.xci | 213 + .../sources_1/ip/cmpy_16x12/cmpy_16x12.xci | 213 + .../ip/cmpy_18x18_mult/cmpy_18x18_mult.xci | 213 + .../sources_1/ip/cmpy_18x8/cmpy_18x8.xci | 213 + .../sources_1/ip/coe/hrc_64_12_025.coe | 771 ++ .../sources_1/ip/coe/one_hop_data.coe | 9602 +++++++++++++++++ .../sources_1/ip/coe/sweep_freq.coe | 258 + .../sources_1/ip/dds_32b_8b/dds_32b_8b.xci | 358 + .../ip/fifo_AntCtrl/fifo_AntCtrl.xci | 480 + .../ip/fifo_accor_cdc/fifo_accor_cdc.xci | 481 + .../ip/fifo_weight_cdc/fifo_weight_cdc.xci | 481 + .../sources_1/ip/hop_rom/hop_rom.xci | 254 + .../ip/hrc_64_12_025/hrc_64_12_025.xci | 350 + .../ip/ila_2x12x1024/ila_2x12x1024.xci | 6300 +++++++++++ .../ila_8x12_2x30_131072.xci | 6308 +++++++++++ .../sources_1/ip/ila_AntCtrl/ila_AntCtrl.xci | 6311 +++++++++++ .../sources_1/ip/ila_cal/ila_cal.xci | 6313 +++++++++++ .../ip/ila_rfcontrl/ila_rfcontrl.xci | 6348 +++++++++++ .../ip/ila_rx_pre_ant/ila_rx_pre_ant.xci | 6310 +++++++++++ .../ip/ila_rx_pre_sys/ila_rx_pre_sys.xci | 6307 +++++++++++ .../ip/ram_hop_data/ram_hop_data.xci | 258 + .../ip/rom_hop_data/rom_hop_data.xci | 254 + .../sources_1/ip/rotate_16b/rotate_16b.xci | 215 + .../sources_1/ip/vio_ant_rd/vio_ant_rd.xci | 1633 +++ .../ip/vio_ant_test/vio_ant_test.xci | 1631 +++ .../sources_1/ip/vio_cal/vio_cal.xci | 1630 +++ .../ip/vio_clk_ld_rd/vio_clk_ld_rd.xci | 1629 +++ .../ip/vio_manual_ctrl/vio_manual_ctrl.xci | 1633 +++ .../ip/vio_phase_comp/vio_phase_comp.xci | 1642 +++ .../sources_1/ip/vio_rf_rd/vio_rf_rd.xci | 1637 +++ .../ip/vio_rfcontrl/vio_rfcontrl.xci | 1640 +++ .../sources_1/new/ApproxModuli_26bit.v | 129 + .../sources_1/new/ad9361_rx_map_cmos_dual.v | 196 + .../sources_1/new/ad9361_tx_map_cmos_dual.v | 183 + .../sources_1/new/adder_tree_ppl.v | 246 + .../new/ant_rf/Sisyif_src/ADF4351_2.v | 188 + .../sources_1/new/ant_rf/Sisyif_src/FRAC1.v | 441 + .../new/ant_rf/Sisyif_src/INT_ROMb.v | 3569 ++++++ .../sources_1/new/ant_rf/Sisyif_src/R_CAL_1.v | 348 + .../sources_1/new/ant_rf/Sisyif_src/R_CAL_2.v | 349 + .../sources_1/new/ant_rf/Sisyif_src/R_CAL_3.v | 348 + .../sources_1/new/ant_rf/Sisyif_src/R_CAL_4.v | 349 + .../sources_1/new/ant_rf/Sisyif_src/Sisyif.v | 301 + .../sources_1/new/ant_rf/Sisyif_src/T_CAL.v | 631 ++ .../new/ant_rf/Sisyif_src/adf4371_a.v | 633 ++ .../new/ant_rf/Sisyif_src/adf4371_b.v | 622 ++ .../new/ant_rf/Sisyif_src/band_rom_a.v | 3573 ++++++ .../new/ant_rf/Sisyif_src/band_rom_b.v | 3573 ++++++ .../new/ant_rf/Sisyif_src/ds18b20_temp.v | 368 + .../new/ant_rf/Sisyif_src/frac2_rom.v | 72 + .../new/ant_rf/Sisyif_src/fre_caliatt.v | 210 + .../new/ant_rf/Sisyif_src/mgc_ctrl.v | 434 + .../new/ant_rf/Sisyif_src/mod2_rom.v | 71 + .../new/ant_rf/Sisyif_src/spi_master.v | 150 + .../new/ant_rf/Sisyif_src/spi_salve.v | 171 + .../sources_1/new/ant_rf/Sisyif_src/spi_tx.v | 118 + .../sources_1/new/ant_rf/ant_rf_ctrl.v | 515 + .../sources_1/new/hdwr/clk_dist.v | 133 + .../new/rx_pre_process/accor_mat_formatting.v | 426 + .../new/rx_pre_process/accum_cmplx_mat.v | 365 + .../new/rx_pre_process/acorr_cmplx_col_vec.v | 283 + .../rx_pre_process/ad9361_phase_cal_coarse.v | 443 + .../rx_pre_process/ad9361_phase_cal_fine.v | 1191 ++ .../sources_1/new/rx_pre_process/null_ctrl.v | 800 ++ .../sources_1/new/rx_pre_process/phase_comp.v | 130 + .../new/rx_pre_process/phase_compensate.v | 196 + .../new/rx_pre_process/rx_pre_process.v | 573 + .../new/rx_pre_process/rx_pre_test.v | 251 + .../new/rx_pre_process/spatial_filter.v | 222 + .../rx_pre_process/weight_vec_formatting.v | 410 + .../sources_1/new/system_top.v | 1114 ++ .../sources_1/new/trunc_32bit_to_12bit.v | 515 + .../sources_1/new/tx_pre_process.v | 138 + .../sources_1/new/tx_qpsk.v | 412 + .../sources_1/new/var_cal.v | 258 + .../utils_1/imports/synth_1/system_top.dcp | 3 + dl814_k7_cal_coarse/dl814_k7_cal_coarse.xpr | 2221 ++++ dl814_k7_cal_coarse/system_top.xsa | 3 + .../vitis_classic_autobuild/.gitignore | 35 + .../vitis_classic_autobuild/Makefile | 8 + .../vitis_classic_autobuild/autobuild.bat | 32 + .../vitis_classic_autobuild/config.json | 18 + .../source/adi_noos/drivers/api/gpio.c | 184 + .../source/adi_noos/drivers/api/irq.c | 153 + .../source/adi_noos/drivers/api/spi.c | 144 + .../drivers/axi_core/axi_dmac/axi_dmac.c | 328 + .../drivers/axi_core/axi_dmac/axi_dmac.h | 124 + .../drivers/axi_core/spi_engine/spi_engine.c | 978 ++ .../drivers/axi_core/spi_engine/spi_engine.h | 231 + .../axi_core/spi_engine/spi_engine_private.h | 154 + .../drivers/frequency/ad9516/ad9516.c | 129 + .../drivers/frequency/ad9516/ad9516.h | 89 + .../source/adi_noos/drivers/platform/axi_io.c | 79 + .../source/adi_noos/drivers/platform/delay.c | 77 + .../adi_noos/drivers/platform/gpio_extra.h | 95 + .../adi_noos/drivers/platform/irq_extra.h | 91 + .../adi_noos/drivers/platform/spi_extra.h | 115 + .../adi_noos/drivers/platform/uart_extra.h | 107 + .../adi_noos/drivers/platform/xilinx_gpio.c | 464 + .../adi_noos/drivers/platform/xilinx_irq.c | 384 + .../adi_noos/drivers/platform/xilinx_spi.c | 461 + .../adi_noos/drivers/platform/xilinx_spi_pl.c | 531 + .../rf-transceiver/ad9361_reg/ad9361_reg.c | 151 + .../rf-transceiver/ad9361_reg/ad9361_reg.h | 104 + .../source/adi_noos/include/axi_io.h | 59 + .../source/adi_noos/include/delay.h | 59 + .../source/adi_noos/include/error.h | 67 + .../source/adi_noos/include/gpio.h | 165 + .../source/adi_noos/include/irq.h | 188 + .../source/adi_noos/include/spi.h | 194 + .../source/adi_noos/include/util.h | 165 + .../source/adi_noos/util/util.c | 283 + .../source/app_config.h | 55 + .../source/dev_profile/ad9361_reg_profile.c | 1730 +++ .../source/dev_profile/ad9516_profile.c | 89 + .../source/dev_profile/dev_profile.h | 43 + .../vitis_classic_autobuild/source/main.c | 422 + .../source/parameters.h | 137 + scripts | 1 + 159 files changed, 134328 insertions(+) create mode 100644 .gitattributes create mode 100644 .gitignore create mode 100644 .gitmodules create mode 100644 dl814_k7_cal_coarse/.gitignore create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.runs/impl_1/debug_nets.ltx create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.runs/impl_1/system_top.bit create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.runs/impl_1/system_top.ltx create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/constrs_1/new/k7401t_ad9516_2ad9361_physical.xdc create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/constrs_1/new/k7410t_ad9516_2ad9361_timing.xdc create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_accum.v create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_acorr.v create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_null_ctrl.v create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_pre.v create mode 100644 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dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_microblaze_ps_riscv_0/system_bd_microblaze_ps_riscv_0.xci create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_rst_clk_wiz_1_100M_0/system_bd_rst_clk_wiz_1_100M_0.xci create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/system_bd.bd create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/system_bd.bda create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui create mode 100644 dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui 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merge=lfs -text +# others +*.pdf filter=lfs diff=lfs merge=lfs -text diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..41e2a60 --- /dev/null +++ b/.gitignore @@ -0,0 +1,20 @@ +# System generated files +# -- macOS +.DS_Store +.AppleDouble +.LSOverride +._* + +# -- Windows +Thumbs.db +ehthumbs.db +Desktop.ini + +# -- Linux +*~ + +# IDEs and editors' files +*.idea +*.vscode +*.sublime-workspace +*.sublime-project diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..fc2d319 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "scripts"] + path = scripts + url = https://git.gatsby.icu/gatsby/embedded-autobuild diff --git a/dl814_k7_cal_coarse/.gitignore b/dl814_k7_cal_coarse/.gitignore new file mode 100644 index 0000000..15117b5 --- /dev/null +++ b/dl814_k7_cal_coarse/.gitignore @@ -0,0 +1,119 @@ +################################################################################ +############################### Project Specific ############################### +################################################################################ +# everything +* + +# git related +!/.gitignore +!/.gitattributes + +# project documents +!/*.md +!/*.txt + +################################################################################ +############################### Vivado Specific ################################ +################################################################################ + +# xpr: needed for recreating design +!/*.xpr + +# source: include everything +!/*.srcs/ +!/*.srcs/**/* + +# runs: exclude everything but design run results +!/*.runs/ +!/*.runs/impl_*/ +!/*.runs/impl_*/*.bit +!/*.runs/impl_*/*.ltx + +# xsa (Xilinx support archive): include for ps +!/*.xsa + +################################################################################ +################################ Vitis Specific ################################ +################################################################################ + +# include sdk directory and everything in it +!/vitis*/ +!/vitis*/** +/vitis*/**.log +/vitis*/.analytics + +# exclude some obscure hidden SDK folders +/vitis*/.metadata/ +/vitis*/.sdk/ +/vitis*/RemoteSystemsTempFiles/ +/vitis*/webtalk/ + +# hw_platform: exclude the entire hw_platform folder, as everything can be +# generated from the .hdf file. Make sure to include the bitstream in the .hdf +# file when exporting from Vivado! +/vitis*/*_hw_platform_*/ + +# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and +# Makefile, ps lib files are regenerated automatically +/vitis*/*_bsp/* +!/vitis*/*_bsp/*.cproject +!/vitis*/*_bsp/*.project +!/vitis*/*_bsp/*.sdkproject +!/vitis*/*_bsp/system.mss +!/vitis*/*_bsp/Makefile + +# Application: ignored file patterns, exclude Debug & Release folders +/vitis*/**/*.o +/vitis*/**/*.d +/vitis*/**/*.a +/vitis*/*/Debug/ +/vitis*/*/Release/ + +################################################################################ +############################ Vivado & Vitis Common ############################# +################################################################################ + +# file patterns that should always be ignored (journal files, log files, dump +# files that are created upon Vivado/SDK errors) +*.jou +*.log +*.backup.jou +*.backup.log +*.upgrade_log +*.dmp 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+ }, + { + "name": "vio_PrecessTime[5]" + }, + { + "name": "vio_PrecessTime[4]" + }, + { + "name": "vio_PrecessTime[3]" + }, + { + "name": "vio_PrecessTime[2]" + }, + { + "name": "vio_PrecessTime[1]" + }, + { + "name": "vio_PrecessTime[0]" + } + ] + } + ] + } + ] + } + ], + "parent_nets": [ + { + "id": 174, + "name": "u_rx_pre_process/u_ad9361_phase_cal/curr_state[1]", + "state_reg": [ + { + "name": "u_rx_pre_process/u_ad9361_phase_cal/curr_state_reg[1]", + "states": [ + { + "name": "STATE_IDLE", + "val": "00" + }, + { + "name": "STATE_CAL_1", + "val": "01" + }, + { + "name": "STATE_CAL_2", + "val": "10" + }, + { + "name": "STATE_DONE", + "val": "11" + } + ] + } + ] + }, + { + "id": 175, + "name": "u_rx_pre_process/u_ad9361_phase_cal/curr_state[0]", + "state_reg": [ + { + "name": "u_rx_pre_process/u_ad9361_phase_cal/curr_state_reg[0]", + "states": [ + { + "name": "STATE_IDLE", + "val": "00" + }, + { + "name": "STATE_CAL_1", + "val": "01" + }, + { + "name": "STATE_CAL_2", + "val": "10" + }, + { + "name": "STATE_DONE", + "val": "11" + } + ] + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/constrs_1/new/k7401t_ad9516_2ad9361_physical.xdc b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/constrs_1/new/k7401t_ad9516_2ad9361_physical.xdc new file mode 100644 index 0000000..99382e8 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/constrs_1/new/k7401t_ad9516_2ad9361_physical.xdc @@ -0,0 +1,220 @@ +# smq7k410t_b9361 + +## Timing Assertions Section + +## Physical Constraints Section + +# Clocks +set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports clk_25m ] ;# CLK_25M +set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 } [get_ports clk_250m_p ] ;# CLK_250M_P +set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# B9361_1_CLK_OUT +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B9361_2_CLK_OUT + +# HMC7044-1 Interface +set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_clk ] ;# GM4526C_SPI_SCLK +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_csn ] ;# GM4526C_SPI_CSB +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_mosi ] ;# GM4526C_SPI_SDIO +set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_miso ] ;# GM4526C_SPI_SDO + +set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports ad9516_refmon ] ;# GM4526C_REFMON +set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS33} [get_ports ad9516_ld ] ;# GM4526C_LD +set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS33} [get_ports ad9516_status ] ;# GM4526C_STATUS +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports ad9516_pd_b ] ;# GM4526C_PDB +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports ad9516_reset_b ] ;# GM4526C_RESETB +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33} [get_ports ad9516_sync_b ] ;# GM4526C_SYNCB + +# AD9361-1 Interface +set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# B9361_1_DATA_CLK +set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# B9361_1_RX_FRAME +set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# B9361_1_P0_00_TX0_N +set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# B9361_1_P0_01_TX0_P +set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# B9361_1_P0_02_TX1_N +set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# B9361_1_P0_03_TX1_P +set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# B9361_1_P0_04_TX2_N +set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# B9361_1_P0_05_TX2_P +set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# B9361_1_P0_06_TX3_N +set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# B9361_1_P0_07_TX3_P +set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# B9361_1_P0_08_TX4_N +set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# B9361_1_P0_09_TX4_P +set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# B9361_1_P0_10_TX5_N +set_property -dict {PACKAGE_PIN G23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# B9361_1_P0_11_TX5_P + +set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# B9361_1_FB_CLK +set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# B9361_1_TX_FRAME +set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# B9361_1_P1_00_RX0_N +set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# B9361_1_P1_01_RX0_P +set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# B9361_1_P1_02_RX1_N +set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# B9361_1_P1_03_RX1_P +set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# B9361_1_P1_04_RX2_N +set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# B9361_1_P1_05_RX2_P +set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# B9361_1_P1_06_RX3_N +set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# B9361_1_P1_07_RX3_P +set_property -dict {PACKAGE_PIN F28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# B9361_1_P1_08_RX4_N +set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# B9361_1_P1_09_RX4_P +set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# B9361_1_P1_10_RX5_N +set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# B9361_1_P1_11_RX5_P + +set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# B9361_1_SPI_CLK +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# B9361_1_SPI_ENB +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# B9361_1_SPI_DI +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# B9361_1_SPI_DO + +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# B9361_1_RESETB +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# B9361_1_EN_AGC +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# B9361_1_ENABLE +set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# B9361_1_TXNRX + +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# B9361_1_CTRL_IN0 +set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# B9361_1_CTRL_IN1 +set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# B9361_1_CTRL_IN2 +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# B9361_1_CTRL_IN3 + +set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# B9361_1_CTRL_OUT0 +set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# B9361_1_CTRL_OUT1 +set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# B9361_1_CTRL_OUT2 +set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# B9361_1_CTRL_OUT3 +set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# B9361_1_CTRL_OUT4 +set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# B9361_1_CTRL_OUT5 +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# B9361_1_CTRL_OUT6 +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# B9361_1_CTRL_OUT7 +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports ad9361_sync ] ;# B9361_SYNC + +# AD9361-2 Interface +set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B9361_2_DATA_CLK +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B9361_2_RX_FRAME +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B9361_2_P0_00_TX0_N +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B9361_2_P0_01_TX0_P +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B9361_2_P0_02_TX1_N +set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B9361_2_P0_03_TX1_P +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B9361_2_P0_04_TX2_N +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B9361_2_P0_05_TX2_P +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B9361_2_P0_06_TX3_N +set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B9361_2_P0_07_TX3_P +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B9361_2_P0_08_TX4_N +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B9361_2_P0_09_TX4_P +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B9361_2_P0_10_TX5_N +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B9361_2_P0_11_TX5_P + +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B9361_2_FB_CLK +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B9361_2_TX_FRAME +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B9361_2_P1_00_RX0_N +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B9361_2_P1_01_RX0_P +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B9361_2_P1_02_RX1_N +set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B9361_2_P1_03_RX1_P +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B9361_2_P1_04_RX2_N +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B9361_2_P1_05_RX2_P +set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B9361_2_P1_06_RX3_N +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B9361_2_P1_07_RX3_P +set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B9361_2_P1_08_RX4_N +set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B9361_2_P1_09_RX4_P +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B9361_2_P1_10_RX5_N +set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B9361_2_P1_11_RX5_P + +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B9361_2_SPI_CLK +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B9361_2_SPI_ENB +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B9361_2_SPI_DI +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B9361_2_SPI_DO + +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B9361_2_RESETB +set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B9361_2_EN_AGC +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B9361_2_ENABLE +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B9361_2_TXNRX + +set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B9361_2_CTRL_IN0 +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B9361_2_CTRL_IN1 +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B9361_2_CTRL_IN2 +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B9361_2_CTRL_IN3 + +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B9361_2_CTRL_OUT0 +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B9361_2_CTRL_OUT1 +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B9361_2_CTRL_OUT2 +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B9361_2_CTRL_OUT3 +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B9361_2_CTRL_OUT4 +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B9361_2_CTRL_OUT5 +set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B9361_2_CTRL_OUT6 +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B9361_2_CTRL_OUT7 + +# Phased-Array Control +set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVTTL } [get_ports ant_cin ] ;# ANT_CIN0 +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVTTL } [get_ports ant_din0 ] ;# ANT_DIN0 +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVTTL } [get_ports ant_din1 ] ;# ANT_DIN1 +set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVTTL } [get_ports ant_cout ] ;# ANT_COUT0 +set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVTTL } [get_ports ant_dout0 ] ;# ANT_DOUT0 +set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVTTL } [get_ports ant_dout1 ] ;# ANT_DOUT1 +set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR_IN +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY_IN + +# RF Synthesizer Control +set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVTTL } [get_ports rf_standby ] ;# RF_STANDBY +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVTTL } [get_ports rf_sw_pll ] ;# RF_SW_PLL +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVTTL } [get_ports rf_t ] ;# RF_T +set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVTTL } [get_ports rf_r ] ;# RF_R +set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVTTL } [get_ports rf_sw_bpf ] ;# RF_SW_BPF +set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVTTL } [get_ports rf_sclk1 ] ;# RF_SCLK1 +set_property -dict {PACKAGE_PIN AA26 IOSTANDARD LVTTL } [get_ports rf_sdio1 ] ;# RF_SDIO1 +set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVTTL } [get_ports rf_cs1 ] ;# RF_CS1 +set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVTTL } [get_ports rf_ld1 ] ;# RF_LD1 +set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVTTL } [get_ports rf_sclk2 ] ;# RF_SCLK2 +set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVTTL } [get_ports rf_sdio2 ] ;# RF_SDIO2 +set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports rf_cs2 ] ;# RF_CS2 +set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports rf_ld2 ] ;# RF_LD2 +set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVTTL } [get_ports rf_sclk3 ] ;# RF_SCLK3 +set_property -dict {PACKAGE_PIN AE29 IOSTANDARD LVTTL } [get_ports rf_sdio3 ] ;# RF_SDIO3 +set_property -dict {PACKAGE_PIN AB28 IOSTANDARD LVTTL } [get_ports rf_cs3 ] ;# RF_CS3 +set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports rf_ld3 ] ;# RF_LD3 +set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVTTL } [get_ports rf_tmgc_16 ] ;# RF_TMGC_16 +set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVTTL } [get_ports rf_tmgc_8 ] ;# RF_TMGC_8 +set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVTTL } [get_ports rf_tmgc_4 ] ;# RF_TMGC_4 +set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVTTL } [get_ports rf_tmgc_2 ] ;# RF_TMGC_2 +set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVTTL } [get_ports rf_tmgc_1 ] ;# RF_TMGC_1 +set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVTTL } [get_ports rf_rmgc_16 ] ;# RF_RMGC_16 +set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVTTL } [get_ports rf_rmgc_8 ] ;# RF_RMGC_8 +set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVTTL } [get_ports rf_rmgc_4 ] ;# RF_RMGC_4 +set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVTTL } [get_ports rf_rmgc_2 ] ;# RF_RMGC_2 +set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVTTL } [get_ports rf_rmgc_1 ] ;# RF_RMGC_1 +set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVTTL } [get_ports rf_enable ] ;# RF_ENABLE +set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVTTL } [get_ports rf_sc ] ;# RF_SC +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVTTL } [get_ports rf_sd ] ;# RF_SD +set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVTTL } [get_ports rf_endsyn ] ;# RF_END_SYN +set_property -dict {PACKAGE_PIN W27 IOSTANDARD LVTTL } [get_ports rf_sdout ] ;# RF_SDOUT +set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVTTL } [get_ports rf_dq_wd ] ;# RF_DQ_WD +set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVTTL } [get_ports rf_sw_rx ] ;# RF_SW_RX + +# LVDS for Time Synchronization +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS33} [get_ports lvds_in_1 ] ;# LVDS_IN1 +set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports lvds_out_1 ] ;# LVDS_OUT1 + +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports lvds_in_2 ] ;# LVDS_IN2 +set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS33} [get_ports lvds_out_2 ] ;# LVDS_OUT2 + +# Debug IO +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART_1_TXD +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART_1_RXD +set_property -dict {PACKAGE_PIN U23 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART_2_TXD +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART_2_RXD +set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART_3_TXD +set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART_3_RXD + +set_property -dict {PACKAGE_PIN V25 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# DEBUG_IO_1 +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# DEBUG_IO_2 +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3 +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4 +set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5 +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6 +set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7 +set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports debug_io_8 ] ;# DEBUG_IO_8 + +set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25 } [get_ports debug_io_00_p ] ;# DEBUG_IO_00_P +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVDS_25 } [get_ports debug_io_01_p ] ;# DEBUG_IO_01_P +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25 } [get_ports debug_io_02_p ] ;# DEBUG_IO_02_P +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25 } [get_ports debug_io_03_p ] ;# DEBUG_IO_03_P +set_property -dict {PACKAGE_PIN AC20 IOSTANDARD LVDS_25 } [get_ports debug_io_04_p ] ;# DEBUG_IO_04_P +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 } [get_ports debug_io_05_p ] ;# DEBUG_IO_05_P +set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS_25 } [get_ports debug_io_06_p ] ;# DEBUG_IO_06_P +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVDS_25 } [get_ports debug_io_07_p ] ;# DEBUG_IO_07_P +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25 } [get_ports debug_io_08_p ] ;# DEBUG_IO_08_P + +# FLASH +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/constrs_1/new/k7410t_ad9516_2ad9361_timing.xdc b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/constrs_1/new/k7410t_ad9516_2ad9361_timing.xdc new file mode 100644 index 0000000..8730d14 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/constrs_1/new/k7410t_ad9516_2ad9361_timing.xdc @@ -0,0 +1,4 @@ +set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D] +set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D] +set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D] +set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_recal_d1_reg/D] diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_accum.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_accum.v new file mode 100644 index 0000000..89dd9c5 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_accum.v @@ -0,0 +1,160 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/10/30 20:46:26 +// Last Simulate Data: 2023/07/17 15:51 +// Design Name: +// Module Name: tb_accum +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Testbench for [accum_cmplx_mat] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// ------------------------------- +// MATLAB Code for data generation +// ------------------------------- +// COLUMN_NUM = 4; +// DATA_I_WIDTH = 12; +// ACC_NUM = 10; + +// rng(0); +// data = rand(4,2)*2-1; +// d_12b = round(data.*(2^(DATA_I_WIDTH-1)-1)); +// d_12b_cmplx = d_12b(:,1) + 1i*d_12b(:,2); +// d_12b_cmplx = d_12b_cmplx(end:-1:1,:); +// d_12b_acorr = d_12b_cmplx*d_12b_cmplx'; +// d_12b_acorr_real_sim = reshape(flip(reshape(real(d_12b_acorr)',1,16)),4,4); +// d_12b_acorr_imag_sim = reshape(flip(reshape(imag(d_12b_acorr)',1,16)),4,4); +// d_12b_acorr_real_sim_sum = ACC_NUM*d_12b_acorr_real_sim; +// d_12b_acorr_imag_sim_sum = ACC_NUM*d_12b_acorr_imag_sim; + + +module tb_accum; + +localparam DATA_I_WIDTH = 24; +localparam DATA_O_WIDTH = 32; +localparam ROW_NUM = 4; +localparam COL_NUM = 4; +localparam ACC_NUM = 2048; + +reg acc_rst = 1'b0; + +reg clk = 1'b1; +reg rst = 1'b1; +reg din_valid = 'b0; + +// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = { +// 24'd1952708, 24'd1246152, -24'd2458370, 24'd2283360, +// 24'd1246152, 24'd5474825, -24'd1041611, 24'd2493996, +// -24'd2458370, -24'd1041611, 24'd3154378, -24'd2757828, +// 24'd2283360, 24'd2493996, -24'd2757828, 24'd2899728 +// }; + +// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = { +// 24'd0, -24'd3022886, -24'd340582, -24'd669768, +// 24'd3022886, 24'd0, -24'd4023023, 24'd3107328, +// 24'd340582, 24'd4023023, 24'd0, 24'd1241460, +// 24'd669768, -24'd3107328, -24'd1241460, 24'd0 +// }; + + +reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = { + 24'd1952708, 24'd1246152, -24'd2458370, 24'd2283360, + 24'd1246152, 24'd5474825, -24'd1041611, 24'd2493996, + -24'd2458370, -24'd1041611, 24'd3154378, 24'h7F_FFFF, + 24'd2283360, 24'd2493996, -24'd2757828, 24'h80_0000 + }; + +reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_imag = { + 24'd0, -24'd3022886, -24'd340582, -24'd669768, + 24'd3022886, 24'd0, -24'd4023023, 24'd3107328, + 24'd340582, 24'd4023023, 24'd0, 24'd1241460, + 24'd669768, -24'd3107328, -24'd1241460, 24'd0 + }; + +wire dout_valid; +wire [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag; + +accum_cmplx_mat #( + .ROW_NUM (ROW_NUM), + .COL_NUM (COL_NUM), + .DATA_I_WIDTH (DATA_I_WIDTH), + .DATA_O_WIDTH (DATA_O_WIDTH), + .ACC_NUM (ACC_NUM) +) u_accum_cmplx_mat +( + // clock & reset + .clk (clk ), + .rst (rst ), + .acc_rst (acc_rst ), // [acc_rst] should assert before accumulation starts + + // input data + .din_valid (din_valid ), + .din_real (din_real ), + .din_imag (din_imag ), + + // output data + .dout_valid (dout_valid ), + .dout_real (dout_real ), + .dout_imag (dout_imag ) +); + + +initial begin + #102 + rst = 1'b0; + + // reset + #222 + acc_rst = 1'b1; + #20 + acc_rst = 1'b0; + + // input data valid lasts [ACC_NUM] clock cycles + #222 + @(posedge clk) + #1 + din_valid = 1'b1; + + #(20*ACC_NUM) + din_valid = 1'b0; + + // reset + #222 + acc_rst = 1'b1; + #20 + acc_rst = 1'b0; + + // input data valid lasts [ACC_NUM] clock cycles + #222 + @(posedge clk) + #1 + din_valid = 1'b1; + + #(20*ACC_NUM) + din_valid = 1'b0; + + #222 + $stop; +end + +always #10 clk = ~clk; + + +endmodule \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_acorr.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_acorr.v new file mode 100644 index 0000000..7c5276c --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_acorr.v @@ -0,0 +1,105 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/10/30 20:46:26 +// Design Name: +// Module Name: acorr_tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Testbench for [acorr_cmplx_col_vec] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_acorr; + +localparam ROW_NUM = 1; +localparam COL_NUM = 4; +localparam DATA_I_WIDTH = 12; +localparam DATA_O_WIDTH = 23; + +reg acc_rst = 1'b0; + +reg clk = 1'b1; +reg rst = 1'b1; +reg din_valid = 'b0; +reg [COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0; + +wire dout_valid; +wire [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag; + +acorr_cmplx_col_vec #( + .COL_NUM (COL_NUM), + .DATA_I_WIDTH (DATA_I_WIDTH), + .DATA_O_WIDTH (DATA_O_WIDTH) +) u_acorr_cmplx_col_vec +( + // clock & reset + .clk (clk ), + .rst (rst ), + + // input data + .din_valid (din_valid ), + .din_real (din_real ), + .din_imag (din_imag ), + + // output data + .dout_valid (dout_valid ), + .dout_real (dout_real ), + .dout_imag (dout_imag ) +); + + +initial begin + #102 rst = 1'b0; + #222; + @(posedge clk) + din_valid = 1'b1; + din_real = { + 12'd1351, + -12'd1219, + 12'd1326, + 12'd1029}; + + din_imag = { + 12'd1538, + -12'd1119, + 12'd1519, + 12'd1495}; + + @(posedge clk) + din_valid = 1'b0; + + @(posedge clk) + din_valid = 1'b1; + din_real = { + 12'd153 , + -12'd724 , + -12'd1315, + 12'd433 }; + + din_imag = { + -12'd1170, + 12'd981 , + -12'd48 , + 12'd1494}; +end + +always #10 clk = ~clk; + + +endmodule \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_null_ctrl.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_null_ctrl.v new file mode 100644 index 0000000..5ebd7b6 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_null_ctrl.v @@ -0,0 +1,80 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 07/18/2023 11:22:10 AM +// Design Name: +// Module Name: tb_null_ctrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_null_ctrl; + +localparam HOP_CNT_192 = 192*200; + +reg clk = 1'b1; +reg clk_2x = 1'b1; +reg clk_4x = 1'b1; +reg rst = 1'b1; + +reg hop_flag_in = 1'b0; +reg sync_flag_phy = 1'b0; +reg sync_null_en_phy = 1'b1; +wire hop_flag_out_phy; + +null_ctrl u_null_ctrl +( + .clk (clk ), + .clk_phy (clk_4x ), + .rst (rst ), + + .hop_flag_in_phy (hop_flag_in ), + .sync_flag_phy (sync_flag_phy ), + .sync_null_en_phy (sync_null_en_phy ), + .hop_flag_out_phy (hop_flag_out_phy ), + .adc_din_valid (1'b1 ) +); + +// clock & reset +initial begin + #102 + rst = 1'b0; +end + +always #5 clk_4x = ~clk_4x; + +always @(posedge clk_4x) begin + clk_2x = ~clk_2x; +end + +always @(posedge clk_2x) begin + clk = ~clk; +end + +// hop control +reg [$clog2(HOP_CNT_192)-1 : 0] hop_cnt = 'b0; + +always @(posedge clk_4x) begin + if (rst) begin + hop_cnt <= 'b0; + hop_flag_in <= 'b0; + end + else begin + hop_cnt <= (hop_cnt == HOP_CNT_192-1) ? 'b0 : hop_cnt + 1'b1; + hop_flag_in <= (hop_cnt == 120) ? 1'b1 : 'b0; + end +end + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_pre.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_pre.v new file mode 100644 index 0000000..fd7c67c --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_pre.v @@ -0,0 +1,285 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/09/15 11:12:45 +// Last Modified Data: 2022/11/02 +// Design Name: +// Module Name: tb_ad9361_cal +// Project Name: +// Target Devices: +// Tool Versions: +// Description: testbench for [rx_pre_process] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_rx_pre; + +localparam COL_NUM = 4; +localparam PS_PL_WIDTH = 32; +localparam OUTPUT_DATA_WIDTH = 30; + +localparam FRAME_HEAD = 32'h7E7E7E7E; +localparam FRAME_BITS = (2+COL_NUM*2)*PS_PL_WIDTH; + +reg [FRAME_BITS-1 : 0] weight_stream_buf = +{ + FRAME_HEAD, 32'd40, + -32'd1145474114, 32'd1816473250 , + 32'd2059208152, -32'd254581925 , + 32'd2062565030, 32'd244279278 , + -32'd1154406364, -32'd1806170603 +}; + +reg sys_clk = 1'b1; +reg sys_clk_4x = 1'b1; +reg sys_rst = 1'b1; +reg clk_96m = 1'b1; +reg ant_rst = 1'b1; + +reg ad9361_1_cal_start = 'b0; +wire ad9361_1_cal_done ; +reg ad9361_2_cal_start = 'b0; +wire ad9361_2_cal_done ; +wire ad9361_cal_result ; +wire ad9361_cal_valid ; +reg ad9361_recal = 'b0; + +// phase difference of 0 degree +wire [11:0] rx_ch1_i; +wire [11:0] rx_ch1_q; +wire [11:0] rx_ch2_i; +wire [11:0] rx_ch2_q; +wire [11:0] rx_ch3_q; +wire [11:0] rx_ch3_i; +wire [11:0] rx_ch4_i; +wire [11:0] rx_ch4_q; + +reg hop_start_flag = 1'b0; +wire hop_flag_out; +wire accor_stream_valid; +wire accor_stream_data; +wire weight_stream_data; +wire rx_data_valid; +wire [OUTPUT_DATA_WIDTH-1:0] rx_data_i, rx_data_q; + +rx_pre_process #( + .OUTPUT_WIDTH (OUTPUT_DATA_WIDTH ), + .SYNC_HOP_INTVL (48*200 ) +) u_rx_pre_process +( + // clock & reset + .sys_clk (sys_clk ), // input sys_clk + .sys_clk_phy (sys_clk_4x ), // input sys_clk_4x + .sys_rst (sys_rst ), // input sys_rst + .clk_96m (clk_96m ), // input clk_96m + .ant_rst (ant_rst ), // input ant_rst + // input data interface + .rx_ch1_i (rx_ch1_i ), // input [11:0] rx_ch1_i + .rx_ch1_q (rx_ch1_q ), // input [11:0] rx_ch1_q + .rx_ch2_i (-rx_ch2_i ), // input [11:0] rx_ch2_i + .rx_ch2_q (-rx_ch2_q ), // input [11:0] rx_ch2_q + .rx_ch3_i (rx_ch3_i ), // input [11:0] rx_ch3_i + .rx_ch3_q (rx_ch3_q ), // input [11:0] rx_ch3_q + .rx_ch4_i (-rx_ch4_i ), // input [11:0] rx_ch4_i + .rx_ch4_q (-rx_ch4_q ), // input [11:0] rx_ch4_q + // input channel phase + .phase_ch1 ('b0 ), + .phase_ch2 ('b0 ), + .phase_ch3 ('b0 ), + .phase_ch4 ('b0 ), + // ad9361 calibration interface + .ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start + .ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done + .ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start + .ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done + .ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result + .ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid + .ad9361_recal (ad9361_recal ), // input ad9361_recal + // nulling algotithm interface + .hop_flag_in_phy (hop_start_flag ), // input hop_start_flag + .sync_flag_phy (1'b0 ), + .lcmv_en_phy (1'b1 ), + .hop_flag_out (hop_flag_out ), + + .accor_stream_valid (accor_stream_valid ), // output accor_stream_valid + .accor_stream_data (accor_stream_data ), // output accor_stream_data + .weight_stream_data (weight_stream_data ), // input weight_stream_data + .rx_data_valid (rx_data_valid ), + .rx_data_i (rx_data_i ), + .rx_data_q (rx_data_q ) +); + +// system clock generation +always begin + #6; + sys_clk = ~sys_clk; + #14; +end + +always begin + #5 sys_clk_4x = ~sys_clk_4x; +end + +always begin + #7; + clk_96m = ~clk_96m; + #3; +end + +initial begin + #102 + sys_rst = 1'b0; + ant_rst = 1'b0; + #100 + ad9361_1_cal_start = 1'b1; +end + +always @(posedge sys_clk) begin + if (ad9361_1_cal_done) begin + ad9361_2_cal_start <= 1'b1; + end + else begin + ad9361_2_cal_start <= 1'b0; + end +end + +integer r_file_real; +integer r_file_imag; +integer w_file_real; +integer w_file_imag; + +reg signed [11:0] rx_ch1_i_data = 'b0, rx_ch1_q_data = 'b0; +reg signed [11:0] rx_ch2_i_data = 'b0, rx_ch2_q_data = 'b0; +reg signed [11:0] rx_ch3_i_data = 'b0, rx_ch3_q_data = 'b0; +reg signed [11:0] rx_ch4_i_data = 'b0, rx_ch4_q_data = 'b0; + +reg [11:0] rx_ch1_i_cal = 12'd2047; +reg [11:0] rx_ch1_q_cal = 12'd2047; +reg [11:0] rx_ch2_i_cal = -12'd2047; +reg [11:0] rx_ch2_q_cal = -12'd2047; +reg [11:0] rx_ch3_q_cal = 12'd2047; +reg [11:0] rx_ch3_i_cal = 12'd2047; +reg [11:0] rx_ch4_i_cal = -12'd2047; +reg [11:0] rx_ch4_q_cal = -12'd2047; + +assign rx_ch1_i = ad9361_cal_valid ? rx_ch1_i_data : rx_ch1_i_cal; +assign rx_ch1_q = ad9361_cal_valid ? rx_ch1_q_data : rx_ch1_q_cal; +assign rx_ch2_i = ad9361_cal_valid ? rx_ch2_i_data : rx_ch2_i_cal; +assign rx_ch2_q = ad9361_cal_valid ? rx_ch2_q_data : rx_ch2_q_cal; +assign rx_ch3_i = ad9361_cal_valid ? rx_ch3_i_data : rx_ch3_i_cal; +assign rx_ch3_q = ad9361_cal_valid ? rx_ch3_q_data : rx_ch3_q_cal; +assign rx_ch4_i = ad9361_cal_valid ? rx_ch4_i_data : rx_ch4_i_cal; +assign rx_ch4_q = ad9361_cal_valid ? rx_ch4_q_data : rx_ch4_q_cal; + +initial begin + forever begin + @(posedge sys_clk) + // æ ¡å‡†æ•°æ® + #720 + rx_ch1_i_cal = ~rx_ch1_i_cal; + rx_ch2_i_cal = ~rx_ch2_i_cal; + rx_ch3_i_cal = ~rx_ch3_i_cal; + rx_ch4_i_cal = ~rx_ch4_i_cal; + #240 + rx_ch1_q_cal = ~rx_ch1_q_cal; + rx_ch2_q_cal = ~rx_ch2_q_cal; + rx_ch3_q_cal = ~rx_ch3_q_cal; + rx_ch4_q_cal = ~rx_ch4_q_cal; + end +end + +initial begin + r_file_real = $fopen("../../../../dl814_k7_cal_coarse.srcs/sim_1/new/xs1_real.csv","r"); + r_file_imag = $fopen("../../../../dl814_k7_cal_coarse.srcs/sim_1/new/xs1_imag.csv","r"); + + w_file_real = $fopen("../../../../dl814_k7_cal_coarse.srcs/sim_1/new/out_real.csv","w"); + w_file_imag = $fopen("../../../../dl814_k7_cal_coarse.srcs/sim_1/new/out_imag.csv","w"); + + @(posedge ad9361_cal_valid) + + forever begin + @(posedge sys_clk) + $fscanf(r_file_real,"%d,%d,%d,%d", + rx_ch1_i_data, + rx_ch2_i_data, + rx_ch3_i_data, + rx_ch4_i_data); + $fscanf(r_file_imag,"%d,%d,%d,%d", + rx_ch1_q_data, + rx_ch2_q_data, + rx_ch3_q_data, + rx_ch4_q_data); + $fdisplay(w_file_real,"%d,%d,%d,%d,%d", + $signed(u_rx_pre_process.rx_comp_ch1_i), + $signed(u_rx_pre_process.rx_comp_ch2_i), + $signed(u_rx_pre_process.rx_comp_ch3_i), + $signed(u_rx_pre_process.rx_comp_ch4_i), + $signed(rx_data_i)); + $fdisplay(w_file_imag,"%d,%d,%d,%d,%d", + $signed(u_rx_pre_process.rx_comp_ch1_q), + $signed(u_rx_pre_process.rx_comp_ch2_q), + $signed(u_rx_pre_process.rx_comp_ch3_q), + $signed(u_rx_pre_process.rx_comp_ch4_q), + $signed(rx_data_q)); + end +end + +// hop flag counter +reg [$clog2(38400)-1 : 0] hop_cnt = 'b0; + +always @(posedge sys_clk_4x) begin + if (sys_rst) begin + hop_cnt <= 'b0; + hop_start_flag <= 1'b0; + end + else if (ad9361_cal_valid) begin + hop_cnt <= (hop_cnt == 200*48*4-1) ? 'b0 : hop_cnt + 1'b1; + hop_start_flag <= (hop_cnt == 127) ? 1'b1 : 1'b0; + end + else begin + hop_cnt <= hop_cnt; + hop_start_flag <= hop_start_flag; + end +end + +// +reg weight_stream_valid = 'b0; + +always @(negedge accor_stream_valid) begin + if (~sys_rst) begin + #((48*50)*40+18); // 50us of 48M clock + weight_stream_valid = 'b1; + #(FRAME_BITS*20); + weight_stream_valid = 'b0; + end +end + +reg [$clog2(FRAME_BITS)-1 : 0] weight_stream_cnt; + +always @(posedge clk_96m) begin + if (sys_rst) begin + weight_stream_cnt <= 'b0; + end + else begin + weight_stream_cnt <= (weight_stream_valid & ~(weight_stream_cnt == FRAME_BITS - 1)) ? weight_stream_cnt + 1'b1 : 'b0; + end +end + +assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt]; + +endmodule + diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_pre_test.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_pre_test.v new file mode 100644 index 0000000..2a01fc8 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_pre_test.v @@ -0,0 +1,278 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/16 15:58:28 +// Design Name: +// Module Name: tb_rx_pre_test +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Co-simulation testbench for [rx_pre_process] and [rx_pre_test] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_rx_pre_test; + +localparam COL_NUM = 4; +localparam PS_PL_WIDTH = 32; + +localparam FRAME_HEAD = 32'h7E7E7E7E; +localparam FRAME_BITS = (2+COL_NUM*2)*PS_PL_WIDTH; + +reg [FRAME_BITS-1 : 0] weight_stream_buf = +{ + FRAME_HEAD, 32'd40, + -32'd1145474114, 32'd1816473250, + 32'd2059208152, -32'd254581925 , + 32'd2062565030, 32'd244279278 , + -32'd1154406364, -32'd1806170603 +}; + +reg sys_clk = 1'b1; +reg sys_clk_2x = 1'b1; +reg sys_clk_4x = 1'b1; +reg sys_rst = 1'b1; +wire clk_96m; +wire ant_rst; + +reg ad9361_1_cal_start = 'b0; +wire ad9361_1_cal_done ; +reg ad9361_2_cal_start = 'b0; +wire ad9361_2_cal_done ; +wire ad9361_cal_result ; +wire ad9361_cal_valid ; +reg ad9361_recal = 'b0; + +// phase difference of 0 degree +reg [11:0] rx_ch1_i = 0, rx_ch1_q = 0; +reg [11:0] rx_ch2_i = 0, rx_ch2_q = 0; +reg [11:0] rx_ch3_i = 0, rx_ch3_q = 0; +reg [11:0] rx_ch4_i = 0, rx_ch4_q = 0; + +wire [11:0] rx_ch1_i_test, rx_ch1_q_test; +wire [11:0] rx_ch2_i_test, rx_ch2_q_test; +wire [11:0] rx_ch3_i_test, rx_ch3_q_test; +wire [11:0] rx_ch4_i_test, rx_ch4_q_test; + +reg [11:0] rx_ch1_i_cal = 12'd2047; +reg [11:0] rx_ch1_q_cal = 12'd2047; +reg [11:0] rx_ch2_i_cal = -12'd2047; +reg [11:0] rx_ch2_q_cal = -12'd2047; +reg [11:0] rx_ch3_q_cal = 12'd2047; +reg [11:0] rx_ch3_i_cal = 12'd2047; +reg [11:0] rx_ch4_i_cal = -12'd2047; +reg [11:0] rx_ch4_q_cal = -12'd2047; + +wire hop_start_flag; +wire hop_flag_out; +wire accor_stream_valid; +wire accor_stream_data; +wire weight_stream_data; +wire rx_data_valid; +wire [29:0] rx_data_i, rx_data_q; + +reg hop_trigger = 1'b0; + +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// Clock Generation /////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +always #5 sys_clk_4x = ~sys_clk_4x; + +always @(posedge sys_clk_4x) begin + sys_clk_2x <= ~sys_clk_2x; +end + +always @(posedge sys_clk_2x) begin + sys_clk <= ~sys_clk; +end + +assign #3 clk_96m = sys_clk_2x; +assign #3 ant_rst = sys_rst; + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////// Stimulus Generation ////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +initial begin + #102 + sys_rst = 1'b0; + #100 + ad9361_1_cal_start = 1'b1; + wait(ad9361_cal_valid); + #1000 + hop_trigger = 1'b1; + + #(192*200*10) // after 200us, trig again + hop_trigger = 1'b0; + + #(192*200*10) // after 200us, trig again + hop_trigger = 1'b1; + + #(192*200*10) // after 200us, trig again + hop_trigger = 1'b0; + + #(192*200*10) // after 200us, trig again + hop_trigger = 1'b1; + + #(192*200*10) // after 200us, trig again + hop_trigger = 1'b0; + + #(192*200*10) // after 200us, trig again + hop_trigger = 1'b1; +end + +always @(posedge sys_clk) begin + if (ad9361_1_cal_done) begin + ad9361_2_cal_start <= 1'b1; + end + else begin + ad9361_2_cal_start <= 1'b0; + end +end + +always @(posedge sys_clk) begin + if (ad9361_cal_valid) begin + rx_ch1_i <= rx_ch1_i_test; + rx_ch1_q <= rx_ch1_q_test; + rx_ch2_i <= rx_ch2_i_test; + rx_ch2_q <= rx_ch2_q_test; + rx_ch3_i <= rx_ch3_i_test; + rx_ch3_q <= rx_ch3_q_test; + rx_ch4_i <= rx_ch4_i_test; + rx_ch4_q <= rx_ch4_q_test; + end + else begin + rx_ch1_i <= rx_ch1_i_cal; + rx_ch1_q <= rx_ch1_q_cal; + rx_ch2_i <= rx_ch2_i_cal; + rx_ch2_q <= rx_ch2_q_cal; + rx_ch3_i <= rx_ch3_i_cal; + rx_ch3_q <= rx_ch3_q_cal; + rx_ch4_i <= rx_ch4_i_cal; + rx_ch4_q <= rx_ch4_q_cal; + end +end + +// æ ¡å‡†æ•°æ® +always @(posedge sys_clk) begin + rx_ch1_i_cal = ~rx_ch1_i_cal; + rx_ch1_q_cal = ~rx_ch1_q_cal; + rx_ch2_i_cal = ~rx_ch2_i_cal; + rx_ch2_q_cal = ~rx_ch2_q_cal; + rx_ch3_i_cal = ~rx_ch3_i_cal; + rx_ch3_q_cal = ~rx_ch3_q_cal; + rx_ch4_i_cal = ~rx_ch4_i_cal; + rx_ch4_q_cal = ~rx_ch4_q_cal; +end + +reg weight_stream_valid = 'b0; + +always @(negedge accor_stream_valid) begin + #((48*50)*40+18); // 50us of 48M clock + weight_stream_valid = 'b1; + #(FRAME_BITS*20); + weight_stream_valid = 'b0; +end + +reg [$clog2(FRAME_BITS)-1 : 0] weight_stream_cnt = FRAME_BITS - 1; + +always @(posedge clk_96m) begin + if (sys_rst) begin + weight_stream_cnt <= FRAME_BITS - 1; + end + else begin + weight_stream_cnt <= (weight_stream_valid & ~(weight_stream_cnt == FRAME_BITS - 1)) ? weight_stream_cnt + 1'b1 : 'b0; + end +end + +assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt]; + +//////////////////////////////////////////////////////////////////////////////// +/////////////////////// Simulation Module Instantiation //////////////////////// +//////////////////////////////////////////////////////////////////////////////// + +rx_pre_process #( + .OUTPUT_WIDTH (30 ), + .SYNC_HOP_INTVL (48*200 ) +) u_rx_pre_process +( + // clock & reset + .sys_clk (sys_clk ), // sync to adc data + .sys_clk_phy (sys_clk_4x ), // sync to physical layer + .sys_rst (sys_rst ), // sync to [sys_clk] + .clk_96m (clk_96m ), // sync to c2c data + .ant_rst (ant_rst ), // sync to [clk_96m] + // input data interface + .rx_ch1_i (rx_ch1_i ), + .rx_ch1_q (rx_ch1_q ), + .rx_ch2_i (rx_ch2_i ), + .rx_ch2_q (rx_ch2_q ), + .rx_ch3_i (rx_ch3_i ), + .rx_ch3_q (rx_ch3_q ), + .rx_ch4_i (rx_ch4_i ), + .rx_ch4_q (rx_ch4_q ), + // input channel phase + .phase_ch1 ('b0 ), + .phase_ch2 ('b0 ), + .phase_ch3 ('b0 ), + .phase_ch4 ('b0 ), + // ad9361 calibration interface + .ad9361_1_cal_start (ad9361_1_cal_start ), + .ad9361_1_cal_done (ad9361_1_cal_done ), + .ad9361_2_cal_start (ad9361_2_cal_start ), + .ad9361_2_cal_done (ad9361_2_cal_done ), + .ad9361_cal_result (ad9361_cal_result ), + .ad9361_cal_valid (ad9361_cal_valid ), + .ad9361_recal (ad9361_recal ), + // nulling algotithm interface + .hop_flag_in_phy (hop_start_flag ), // input hop_start_flag + .sync_flag_phy (1'b0 ), + .lcmv_en_phy (1'b1 ), + .hop_flag_out (hop_flag_out ), + + .accor_stream_valid (accor_stream_valid ), // output accor_stream_valid + .accor_stream_data (accor_stream_data ), // output accor_stream_data + .weight_stream_data (weight_stream_data ), // input weight_stream_data + .rx_data_valid (rx_data_valid ), + .rx_data_i (rx_data_i ), + .rx_data_q (rx_data_q ) +); + +// temporary test cases +rx_pre_test u_rx_pre_test +( + // clock & reset + .clk (sys_clk ), + .rst (sys_rst ), + .clk_phy (sys_clk_4x ), + .hop_trigger (hop_trigger ), + .hop_trigger_en (1'b1 ), + // calc result + .ad9361_cal_result (ad9361_cal_result ), + .ad9361_cal_valid (ad9361_cal_valid ), + // output test data + .rx_ch1_i (rx_ch1_i_test ), + .rx_ch1_q (rx_ch1_q_test ), + .rx_ch2_i (rx_ch2_i_test ), + .rx_ch2_q (rx_ch2_q_test ), + .rx_ch3_i (rx_ch3_i_test ), + .rx_ch3_q (rx_ch3_q_test ), + .rx_ch4_i (rx_ch4_i_test ), + .rx_ch4_q (rx_ch4_q_test ), + .hop_start_flag (hop_start_flag ) +); + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_test.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_test.v new file mode 100644 index 0000000..842b4fb --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_test.v @@ -0,0 +1,85 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/16 15:08:02 +// Design Name: +// Module Name: tb_rx_test +// Project Name: +// Target Devices: +// Tool Versions: +// Description: testbench for [rx_pre_test] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_rx_test; + +reg sys_clk = 1'b1; +reg sys_clk_4x = 1'b1; +reg sys_rst = 1'b1; +reg hop_trigger = 1'b0; + +reg ad9361_cal_result = 1'b0; +reg ad9361_cal_valid = 1'b0; + +wire [11:0] rx_ch1_i; +wire [11:0] rx_ch1_q; +wire [11:0] rx_ch2_i; +wire [11:0] rx_ch2_q; +wire [11:0] rx_ch3_i; +wire [11:0] rx_ch3_q; +wire [11:0] rx_ch4_i; +wire [11:0] rx_ch4_q; +wire hop_start_flag; + +rx_pre_test u_rx_pre_test +( + // clock & reset + .clk (sys_clk ), + .rst (sys_rst ), + .hop_trigger (hop_trigger ), + // calc result + .ad9361_cal_result (ad9361_cal_result ), + .ad9361_cal_valid (ad9361_cal_valid ), + // output test data + .rx_ch1_i (rx_ch1_i ), + .rx_ch1_q (rx_ch1_q ), + .rx_ch2_i (rx_ch2_i ), + .rx_ch2_q (rx_ch2_q ), + .rx_ch3_i (rx_ch3_i ), + .rx_ch3_q (rx_ch3_q ), + .rx_ch4_i (rx_ch4_i ), + .rx_ch4_q (rx_ch4_q ), + .hop_start_flag (hop_start_flag ) +); + +// system clock generation +always begin + #5 sys_clk = ~sys_clk; +end + +initial begin + #102 + sys_rst = 1'b0; + #100 + ad9361_cal_valid = 1'b1; + #1000 + hop_trigger = 1'b1; + #100 + hop_trigger = 1'b0; +end + +endmodule \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_tx_pre_process.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_tx_pre_process.v new file mode 100644 index 0000000..71a25b0 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_tx_pre_process.v @@ -0,0 +1,93 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2023/02/25 15:50:45 +// Design Name: +// Module Name: tb_tx_pre_process +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_tx_pre_process; + +reg clk = 1'b1; +reg rst = 1'b1; + +reg [11:0] tx_data_ch1_i = 'b0; +reg [11:0] tx_data_ch1_q = 'b0; +reg [11:0] tx_data_ch2_i = 'b0; +reg [11:0] tx_data_ch2_q = 'b0; + +reg ad9361_tx_switch = 1'b0; + +reg [3:0] bb_rshift = 4'd3; + +wire [11:0] tx_ch1_i; +wire [11:0] tx_ch1_q; +wire [11:0] tx_ch2_i; +wire [11:0] tx_ch2_q; + +tx_pre_process #( + .CAL_MOD_FINE (1 ) +) u_tx_pre_process +( + // clock & reset + .clk (clk ), + .rst (rst ), + // input data + .tx_data_ch1_i (tx_data_ch1_i ), + .tx_data_ch1_q (tx_data_ch1_q ), + .tx_data_ch2_i (tx_data_ch2_i ), + .tx_data_ch2_q (tx_data_ch2_q ), + // ad9361 calibration interface + .ad9361_tx_switch (ad9361_tx_switch ), + // + .bb_rshift (bb_rshift ), + // output data + .tx_ch1_i (tx_ch1_i ), + .tx_ch1_q (tx_ch1_q ), + .tx_ch2_i (tx_ch2_i ), + .tx_ch2_q (tx_ch2_q ) +); + +initial begin + #102 rst = 1'b0; + #100 ad9361_tx_switch = 1'b1; + #10000 ad9361_tx_switch = 1'b0; +end + +always #10 clk = ~clk; + +always @(posedge clk) begin + if (rst) begin + tx_data_ch1_i <= 'b0; + tx_data_ch1_q <= 'b0; + tx_data_ch2_i <= 'b0; + tx_data_ch2_q <= 'b0; + end + else begin + tx_data_ch1_i <= tx_data_ch1_i + 12'd1; + tx_data_ch1_q <= tx_data_ch1_q + 12'd2; + tx_data_ch2_i <= tx_data_ch2_i + 12'd3; + tx_data_ch2_q <= tx_data_ch2_q + 12'd4; + end +end + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_xpm_cdc_pulse.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_xpm_cdc_pulse.v new file mode 100644 index 0000000..576acef --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_xpm_cdc_pulse.v @@ -0,0 +1,86 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 03/29/2023 09:02:30 PM +// Design Name: +// Module Name: tb_xpm_cdc_pulse +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_xpm_cdc_pulse; + +reg sys_clk = 1'b1; +reg sys_clk_4x = 1'b1; +reg sys_rst = 1'b1; + +reg src_pulse = 1'b0; +wire dest_pulse; + +xpm_cdc_pulse #( + .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 + .INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .REG_OUTPUT (1), // DECIMAL; 0=disable registered output, 1=enable registered output + .RST_USED (1), // DECIMAL; 0=no reset, 1=implement reset + .SIM_ASSERT_CHK (1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages +) u_xpm_cdc_pulse +( + .dest_pulse (dest_pulse ), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse + // transfer is correctly initiated on src_pulse input. This output is + // combinatorial unless REG_OUTPUT is set to 1. + .dest_clk (sys_clk ), // 1-bit input: Destination clock. + .dest_rst (sys_rst ), // 1-bit input: optional; required when RST_USED = 1 + .src_clk (sys_clk_4x ), // 1-bit input: Source clock. + .src_pulse (src_pulse ), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the + // destination clock domain. The minimum gap between each pulse transfer must be + // at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured + // between the falling edge of a src_pulse to the rising edge of the next + // src_pulse. This minimum gap will guarantee that each rising edge of src_pulse + // will generate a pulse the size of one dest_clk period in the destination + // clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while + // src_rst and/or dest_rst are asserted. + .src_rst (sys_rst ) // 1-bit input: optional; required when RST_USED = 1 +); + +initial begin + #102; + sys_rst = 1'b0; +end + +always begin + #3; + sys_clk = ~sys_clk; + #37; +end + +always begin + #5; + sys_clk_4x = ~sys_clk_4x; +end + +reg [3:0] pulse_cnt = 'b0; + +always @(posedge sys_clk_4x) begin + if (sys_rst) begin + src_pulse <= 1'b0; + pulse_cnt <= 'b0; + end + else begin + pulse_cnt <= pulse_cnt + 1'b1; + src_pulse <= (pulse_cnt == 4'd15) ? 1'b1 : 1'b0; + end +end + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0.xci b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0.xci new file mode 100644 index 0000000..b8ad40e --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0.xci @@ -0,0 +1,375 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_axi_gpio_0_0", + "cell_name": "axi_gpio", + "component_reference": "xilinx.com:ip:axi_gpio:2.0", + "ip_revision": "34", + "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0", + "parameters": { + "component_parameters": { + "C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "C_GPIO_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_IS_DUAL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_ALL_INPUTS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "C_DOUT_DEFAULT": [ { "value": "0xFFFFFFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_ALL_INPUTS_2": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_INTERRUPT_PRESENT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "system_bd_axi_gpio_0_0", "resolve_type": "user", "usage": "all" } ], + "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "GPIO_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "GPIO2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "C_ALL_OUTPUTS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_ALL_OUTPUTS_2": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ] + }, + "model_parameters": { + "C_FAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ], + "C_S_AXI_ADDR_WIDTH": [ { "value": "9", "format": "long", "usage": "all" } ], + "C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ], + "C_GPIO_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ALL_INPUTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ALL_INPUTS_2": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ALL_OUTPUTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ALL_OUTPUTS_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INTERRUPT_PRESENT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DOUT_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_IS_DUAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "kintex7" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7k410t" } ], + "NEXTGEN_VERSAL": [ { "value": "0" } ], + "PACKAGE": [ { "value": "ffg900" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "34" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2024.1.2" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_aresetn": [ { "direction": "in", "driver_value": "1" } ], + "s_axi_awaddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ], + "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_awready": [ { "direction": "out" } ], + "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_wready": [ { "direction": "out" } ], + "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "s_axi_bvalid": [ { "direction": "out" } ], + "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_araddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ], + "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_arready": [ { "direction": "out" } ], + "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "s_axi_rvalid": [ { "direction": "out" } ], + "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ], + "gpio_io_o": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "gpio2_io_i": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ] + }, + "interfaces": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "slave", + "memory_map_ref": "S_AXI", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "9", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "ARADDR": [ { "physical_name": "s_axi_araddr" } ], + "ARREADY": [ { "physical_name": "s_axi_arready" } ], + "ARVALID": [ { "physical_name": "s_axi_arvalid" } ], + "AWADDR": [ { "physical_name": "s_axi_awaddr" } ], + "AWREADY": [ { "physical_name": "s_axi_awready" } ], + "AWVALID": [ { "physical_name": "s_axi_awvalid" } ], + "BREADY": [ { "physical_name": "s_axi_bready" } ], + "BRESP": [ { "physical_name": "s_axi_bresp" } ], + "BVALID": [ { "physical_name": "s_axi_bvalid" } ], + "RDATA": [ { "physical_name": "s_axi_rdata" } ], + "RREADY": [ { "physical_name": "s_axi_rready" } ], + "RRESP": [ { "physical_name": "s_axi_rresp" } ], + "RVALID": [ { "physical_name": "s_axi_rvalid" } ], + "WDATA": [ { "physical_name": "s_axi_wdata" } ], + "WREADY": [ { "physical_name": "s_axi_wready" } ], + "WSTRB": [ { "physical_name": "s_axi_wstrb" } ], + "WVALID": [ { "physical_name": "s_axi_wvalid" } ] + } + }, + "S_AXI_ACLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "s_axi_aclk" } ] + } + }, + "S_AXI_ARESETN": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + }, + "GPIO": { + "vlnv": "xilinx.com:interface:gpio:1.0", + "abstraction_type": "xilinx.com:interface:gpio_rtl:1.0", + "mode": "master", + "parameters": { + "BOARD.ASSOCIATED_PARAM": [ { "value": "GPIO_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ] + }, + "port_maps": { + "TRI_O": [ { "physical_name": "gpio_io_o" } ] + } + }, + "GPIO2": { + "vlnv": "xilinx.com:interface:gpio:1.0", + "abstraction_type": "xilinx.com:interface:gpio_rtl:1.0", + "mode": "master", + "parameters": { + "BOARD.ASSOCIATED_PARAM": [ { "value": "GPIO2_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ] + }, + "port_maps": { + "TRI_I": [ { "physical_name": "gpio2_io_i" } ] + } + } + }, + "memory_maps": { + "S_AXI": { + "display_name": "S_AXI_MEM", + "description": "Memory Map for S_AXI", + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "4096", + "display_name": "Reg", + "description": "Register Block", + "usage": "register", + "access": "read-write", + "registers": { + "GPIO_DATA": { + "address_offset": "0x0", + "size": 32, + "display_name": "Channel_1_GPIO_DATA", + "description": "Channel-1 AXI GPIO Data register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "CH1_DATA": { + "bit_offset": 0, + "bit_width": 32, + "display_name": "Channel_1_GPIO_DATA", + "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "GPIO_TRI": { + "address_offset": "0x4", + "size": 32, + "display_name": "Channel_1_GPIO_TRI", + "description": "Channel-1 AXI GPIO 3-State Control register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "CH1_TRI": { + "bit_offset": 0, + "bit_width": 32, + "display_name": "Channel_1_GPIO_DATA", + "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "GPIO2_DATA": { + "address_offset": "0x8", + "size": 32, + "display_name": "Channel_2_GPIO_DATA", + "description": "Channel-2 AXI GPIO Data register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "CH2_DATA": { + "bit_offset": 0, + "bit_width": 32, + "display_name": "Channel_2_GPIO_DATA", + "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "GPIO2_TRI": { + "address_offset": "0xC", + "size": 32, + "display_name": "Channel_2_GPIO_TRI", + "description": "Channel-2 AXI GPIO 3-State Control register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "CH2_TRI": { + "bit_offset": 0, + "bit_width": 32, + "display_name": "Channel_2_GPIO_DATA", + "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "GIER": { + "address_offset": "0x11C", + "size": 32, + "display_name": "Global_Interrupt_Enable register", + "description": "Global_Interrupt_Enable register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "INT_EN": { + "bit_offset": 31, + "bit_width": 1, + "display_name": "Global_Interrupt_Enable", + "description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "IP_IER": { + "address_offset": "0x128", + "size": 32, + "display_name": "IP Interrupt Enable register", + "description": "IP Interrupt Enable register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "CH1_INT_EN": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "Channel_1_Interrupt_Enable", + "description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n", + "is_volatile": true, + "access": "read-write" + }, + "CH2_INT_EN": { + "bit_offset": 1, + "bit_width": 1, + "display_name": "Channel_2_Interrupt_Enable", + "description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "IP_ISR": { + "address_offset": "0x120", + "size": 32, + "display_name": "IP Interrupt Status register", + "description": "IP Interrupt Status register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "CH1_INT_S": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "Channel_1_Interrupt_Status", + "description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n", + "is_volatile": true, + "access": "read-write" + }, + "CH2_INT_S": { + "bit_offset": 1, + "bit_width": 1, + "display_name": "Channel_2_Interrupt_Status", + "description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n", + "is_volatile": true, + "access": "read-write" + } + } + } + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci new file mode 100644 index 0000000..2658b76 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci @@ -0,0 +1,294 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_axi_spi_engine_0_0", + "cell_name": "axi_spi_engine", + "component_reference": "analog.com:user:axi_spi_engine:1.0", + "ip_revision": "1", + "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0", + "parameters": { + "component_parameters": { + "CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MM_IF_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OFFLOAD": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "ID": [ { "value": "0", "resolve_type": "user", "format": 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"value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "MM_IF_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "NUM_OFFLOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "CFG_INFO_0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "CFG_INFO_1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "CFG_INFO_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "CFG_INFO_3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "kintex7" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7k410t" } ], + "NEXTGEN_VERSAL": [ { "value": "0" } ], + "PACKAGE": [ { "value": "ffg900" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "1" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2024.1.2" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_aresetn": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_awaddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "s_axi_awready": [ { "direction": "out", "driver_value": "0" } ], + "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], + "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "s_axi_wready": [ { "direction": "out", "driver_value": "0" } ], + "s_axi_bvalid": [ { "direction": "out", "driver_value": "0" } ], + "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ], + "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_araddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "s_axi_arready": [ { "direction": "out", "driver_value": "0" } ], + "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], + "s_axi_rvalid": [ { "direction": "out", "driver_value": "0" } ], + "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ], + "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "irq": [ { "direction": "out" } ], + "spi_clk": [ { "direction": "in" } ], + "spi_resetn": [ { "direction": "out" } ], + "cmd_ready": [ { "direction": "in" } ], + "cmd_valid": [ { "direction": "out" } ], + "cmd_data": [ { "direction": "out", "size_left": "15", "size_right": "0" } ], + "sdo_data_ready": [ { "direction": "in", "driver_value": "0" } ], + "sdo_data_valid": [ { "direction": "out" } ], + "sdo_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], + "sdi_data_ready": [ { "direction": "out" } ], + "sdi_data_valid": [ { "direction": "in", "driver_value": "0" } ], + "sdi_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "sync_ready": [ { "direction": "out" } ], + "sync_valid": [ { "direction": "in" } ], + "sync_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ] + }, + "interfaces": { + "s_axi": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "slave", + "memory_map_ref": "s_axi", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", 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"value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "s_axi_awaddr" } ], + "AWPROT": [ { "physical_name": "s_axi_awprot" } ], + "AWVALID": [ { "physical_name": "s_axi_awvalid" } ], + "AWREADY": [ { "physical_name": "s_axi_awready" } ], + "WDATA": [ { "physical_name": "s_axi_wdata" } ], + "WSTRB": [ { "physical_name": "s_axi_wstrb" } ], + "WVALID": [ { "physical_name": "s_axi_wvalid" } ], + "WREADY": [ { "physical_name": "s_axi_wready" } ], + "BRESP": [ { "physical_name": "s_axi_bresp" } ], + "BVALID": [ { "physical_name": "s_axi_bvalid" } ], + "BREADY": [ { "physical_name": "s_axi_bready" } ], + "ARADDR": [ { "physical_name": "s_axi_araddr" } ], + "ARPROT": [ { "physical_name": "s_axi_arprot" } ], + "ARVALID": [ { "physical_name": "s_axi_arvalid" } ], + "ARREADY": [ { "physical_name": "s_axi_arready" } ], + "RDATA": [ { "physical_name": "s_axi_rdata" } ], + "RRESP": [ { "physical_name": "s_axi_rresp" } ], + "RVALID": [ { "physical_name": "s_axi_rvalid" } ], + "RREADY": [ { "physical_name": "s_axi_rready" } ] + } + }, + "s_axi_aclk": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "s_axi_aclk" } ] + } + }, + "s_axi_aresetn": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + }, + "spi_engine_ctrl": { + "vlnv": "analog.com:interface:spi_engine_ctrl:1.0", + "abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0", + "mode": "master", + "port_maps": { + "cmd_ready": [ { "physical_name": "cmd_ready" } ], + "cmd_valid": [ { "physical_name": "cmd_valid" } ], + "cmd_data": [ { "physical_name": "cmd_data" } ], + "sdo_ready": [ { "physical_name": "sdo_data_ready" } ], + "sdo_valid": [ { "physical_name": "sdo_data_valid" } ], + "sdo_data": [ { "physical_name": "sdo_data" } ], + "sdi_ready": [ { "physical_name": "sdi_data_ready" } ], + "sdi_valid": [ { "physical_name": "sdi_data_valid" } ], + "sdi_data": [ { "physical_name": "sdi_data" } ], + "sync_ready": [ { "physical_name": "sync_ready" } ], + "sync_valid": [ { "physical_name": "sync_valid" } ], + "sync_data": [ { "physical_name": "sync_data" } ] + } + }, + "spi_engine_ctrl_signal_clock": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], 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"is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "spi_resetn" } ] + } + }, + "spi_engine_offload_ctrl0_s_axi_signal_clock": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "s_axi_aclk" } ] + } + }, + "spi_engine_offload_ctrl0_s_axi_signal_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + } + }, + "memory_maps": { + "s_axi": { + "address_blocks": { + "axi_lite": { + "base_address": "0", + "range": "65536" + } + } + } + } + } + } +} \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_1_0/system_bd_clk_wiz_1_0.xci b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_1_0/system_bd_clk_wiz_1_0.xci new file mode 100644 index 0000000..6c1836b --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_1_0/system_bd_clk_wiz_1_0.xci @@ -0,0 +1,658 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_clk_wiz_1_0", + "cell_name": "clk_wiz_25M", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "14", + "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_clk_wiz_1_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "system_bd_clk_wiz_1_0", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], + "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], + "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ], + "PRIM_IN_FREQ": [ { "value": "25", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], + "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ], + "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ], + "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ], + "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SECONDARY_IN_FREQ": [ { "value": "100.000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ], + "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ], + "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN1_JITTER_PS": [ { "value": "400.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "36.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "40.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "36.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], + "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ], + "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ], + "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ], + "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", 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{ "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "peripheral_aresetn" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci new file mode 100644 index 0000000..7435229 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci @@ -0,0 +1,176 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_spi_engine_execution_0_0", + "cell_name": "spi_engine_execution", + "component_reference": "analog.com:user:spi_engine_execution:1.0", + "ip_revision": "1", + "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0", + "parameters": { + "component_parameters": { + "NUM_OF_CS": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], 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"M00_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M00_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M00_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M00_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M00_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M00_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M00_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M00_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M00_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M00_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A00_BASE_ADDR": [ { "value": "0x0000000040000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", 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"1", "physical_right": "1" } ], + "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "1", "physical_right": "1" } ], + "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "63", "physical_right": "32" } ], + "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "3", "physical_right": "2" } ], + "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "1", "physical_right": "1" } ], + "RREADY": [ { "physical_name": "m_axi_rready", "physical_left": "1", "physical_right": "1" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/system_bd.bd b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/system_bd.bd new file mode 100644 index 0000000..dacb4d2 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/system_bd.bd @@ -0,0 +1,1612 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0xBA66A8ED01512315", + "device": "xc7k410tffg900-2", + "gen_directory": "../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd", + "name": "system_bd", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2024.1.2", + "validated": "true" + }, + "design_tree": { + "microblaze_ps_local_memory": { + "dlmb_v10": "", + "ilmb_v10": "", + "dlmb_bram_if_cntlr": "", + "ilmb_bram_if_cntlr": "", + "lmb_bram": "" + }, + "clk_wiz_25M": "", + "rst_clk_wiz_25M": "", + "axi_spi_engine": { + "axi_spi_engine": "", + "spi_engine_execution": "" + }, + "microblaze_ps_axi_periph": { + "xbar": "", + "s00_couplers": {}, + "m00_couplers": {}, + "m01_couplers": {} + }, + "axi_gpio": "", + "mdm": "", + "microblaze_ps": "" + }, + "interface_ports": { + "spi": { + "mode": "Master", + "vlnv_bus_definition": "analog.com:interface:spi_engine:1.0", + "vlnv": "analog.com:interface:spi_engine_rtl:1.0", + "port_maps": { + "sclk": { + "physical_name": "spi_sclk", + "direction": "O" + }, + "sdi": { + "physical_name": "spi_sdi", + "direction": "I", + "left": "0", + "right": "0" + }, + "sdo": { + "physical_name": "spi_sdo", + "direction": "O" + }, + "sdo_t": { + "physical_name": "spi_sdo_t", + "direction": "O" + }, + "three_wire": { + "physical_name": "spi_three_wire", + "direction": "O" + }, + "cs": { + "physical_name": "spi_cs", + "direction": "O", + "left": "2", + "right": "0" + } + } + } + }, + "ports": { + "clk_25MHz": { + "type": "clk", + "direction": "I", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_clk_in1_0", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "25000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "spi_active": { + "direction": "O" + }, + "gpio_o": { + "direction": "O", + "left": "31", + "right": "0" + }, + "gpio_i": { + "direction": "I", + "left": "31", + "right": "0" + } + }, + "components": { + "microblaze_ps_local_memory": { + "interface_ports": { + "DLMB": { + "mode": "MirroredMaster", + "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0", + "vlnv": "xilinx.com:interface:lmb_rtl:1.0" + }, + "ILMB": { + "mode": "MirroredMaster", + "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0", + "vlnv": "xilinx.com:interface:lmb_rtl:1.0" + } + }, + "ports": { + "LMB_Clk": { + "type": "clk", + "direction": "I" + }, + "SYS_Rst": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "dlmb_v10": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "ip_revision": "14", + "xci_name": "system_bd_dlmb_v10_0", + "xci_path": "ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.xci", + "inst_hier_path": "microblaze_ps_local_memory/dlmb_v10", + "interface_ports": { + "LMB_M": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0" + ] + } + } + }, + "ilmb_v10": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "ip_revision": "14", + "xci_name": "system_bd_ilmb_v10_0", + "xci_path": "ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.xci", + "inst_hier_path": "microblaze_ps_local_memory/ilmb_v10", + "interface_ports": { + "LMB_M": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0" + ] + } + } + }, + "dlmb_bram_if_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "ip_revision": "24", + "xci_name": "system_bd_dlmb_bram_if_cntlr_0", + "xci_path": "ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.xci", + "inst_hier_path": "microblaze_ps_local_memory/dlmb_bram_if_cntlr", + "parameters": { + "C_ECC": { + "value": "0" + } + }, + "hdl_attributes": { + "BMM_INFO_ADDRESS_SPACE": { + "value": "byte 0x00000000 32 > system_bd microblaze_ps_local_memory/lmb_bram", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "ilmb_bram_if_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "ip_revision": "24", + "xci_name": "system_bd_ilmb_bram_if_cntlr_0", + "xci_path": "ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.xci", + "inst_hier_path": "microblaze_ps_local_memory/ilmb_bram_if_cntlr", + "parameters": { + "C_ECC": { + "value": "0" + } + } + }, + "lmb_bram": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "ip_revision": "8", + "xci_name": "system_bd_lmb_bram_0", + "xci_path": "ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.xci", + "inst_hier_path": "microblaze_ps_local_memory/lmb_bram", + "parameters": { + "Enable_B": { + "value": "Use_ENB_Pin" + }, + "Memory_Type": { + "value": "True_Dual_Port_RAM" + }, + "Port_B_Clock": { + "value": "100" + }, + "Port_B_Enable_Rate": { + "value": "100" + }, + "Port_B_Write_Rate": { + "value": "50" + }, + "Use_RSTB_Pin": { + "value": "true" + }, + "use_bram_block": { + "value": "BRAM_Controller" + } + } + } + }, + "interface_nets": { + "microblaze_ps_dlmb": { + "interface_ports": [ + "dlmb_v10/LMB_M", + "DLMB" + ] + }, + "microblaze_ps_dlmb_bus": { + "interface_ports": [ + "dlmb_v10/LMB_Sl_0", + "dlmb_bram_if_cntlr/SLMB" + ] + }, + "microblaze_ps_dlmb_cntlr": { + "interface_ports": [ + "dlmb_bram_if_cntlr/BRAM_PORT", + "lmb_bram/BRAM_PORTA" + ] + }, + "microblaze_ps_ilmb": { + "interface_ports": [ + "ilmb_v10/LMB_M", + "ILMB" + ] + }, + "microblaze_ps_ilmb_bus": { + "interface_ports": [ + "ilmb_v10/LMB_Sl_0", + "ilmb_bram_if_cntlr/SLMB" + ] + }, + "microblaze_ps_ilmb_cntlr": { + "interface_ports": [ + "ilmb_bram_if_cntlr/BRAM_PORT", + "lmb_bram/BRAM_PORTB" + ] + } + }, + "nets": { + "SYS_Rst_1": { + "ports": [ + "SYS_Rst", + "dlmb_bram_if_cntlr/LMB_Rst", + "dlmb_v10/SYS_Rst", + "ilmb_bram_if_cntlr/LMB_Rst", + "ilmb_v10/SYS_Rst" + ] + }, + "microblaze_ps_Clk": { + "ports": [ + "LMB_Clk", + "dlmb_bram_if_cntlr/LMB_Clk", + "dlmb_v10/LMB_Clk", + "ilmb_bram_if_cntlr/LMB_Clk", + "ilmb_v10/LMB_Clk" + ] + } + } + }, + "clk_wiz_25M": { + "vlnv": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "14", + "xci_name": "system_bd_clk_wiz_1_0", + "xci_path": "ip/system_bd_clk_wiz_1_0/system_bd_clk_wiz_1_0.xci", + "inst_hier_path": "clk_wiz_25M", + "parameters": { + "CLKIN1_JITTER_PS": { + "value": "400.0" + }, + "CLKOUT1_JITTER": { + "value": "401.466" + }, + "CLKOUT1_PHASE_ERROR": { + "value": "245.713" + }, + "CLKOUT1_REQUESTED_OUT_FREQ": { + "value": "25" + }, + "MMCM_CLKFBOUT_MULT_F": { + "value": "36.500" + }, + "MMCM_CLKIN1_PERIOD": { + "value": "40.000" + }, + "MMCM_CLKIN2_PERIOD": { + "value": "10.0" + }, + "MMCM_CLKOUT0_DIVIDE_F": { + "value": "36.500" + }, + "PRIM_IN_FREQ": { + "value": "25" + }, + "PRIM_SOURCE": { + "value": "Single_ended_clock_capable_pin" + }, + "USE_RESET": { + "value": "false" + } + } + }, + "rst_clk_wiz_25M": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "ip_revision": "15", + "xci_name": "system_bd_rst_clk_wiz_1_100M_0", + "xci_path": "ip/system_bd_rst_clk_wiz_1_100M_0/system_bd_rst_clk_wiz_1_100M_0.xci", + "inst_hier_path": "rst_clk_wiz_25M" + }, + "axi_spi_engine": { + "interface_ports": { + "s_axi": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "spi": { + "mode": "Master", + "vlnv_bus_definition": "analog.com:interface:spi_engine:1.0", + "vlnv": "analog.com:interface:spi_engine_rtl:1.0" + } + }, + "ports": { + "s_axi_aclk": { + "type": "clk", + "direction": "I" + }, + "s_axi_aresetn": { + "type": "rst", + "direction": "I" + }, + "spi_clk": { + "type": "clk", + "direction": "I" + }, + "active": { + "direction": "O" + }, + "irq": { + "direction": "O" + } + }, + "components": { + "axi_spi_engine": { + "vlnv": "analog.com:user:axi_spi_engine:1.0", + "ip_revision": "1", + "xci_name": "system_bd_axi_spi_engine_0_0", + "xci_path": "ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci", + "inst_hier_path": "axi_spi_engine/axi_spi_engine" + }, + "spi_engine_execution": { + "vlnv": "analog.com:user:spi_engine_execution:1.0", + "ip_revision": "1", + "xci_name": "system_bd_spi_engine_execution_0_0", + "xci_path": "ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci", + "inst_hier_path": "axi_spi_engine/spi_engine_execution", + "parameters": { + "NUM_OF_CS": { + "value": "3" + } + } + } + }, + "interface_nets": { + "Conn1": { + "interface_ports": [ + "axi_spi_engine/s_axi", + "s_axi" + ] + }, + "Conn3": { + "interface_ports": [ + "spi_engine_execution/spi", + "spi" + ] + }, + "axi_spi_engine_spi_engine_ctrl": { + "interface_ports": [ + "axi_spi_engine/spi_engine_ctrl", + "spi_engine_execution/ctrl" + ] + } + }, + "nets": { + "axi_spi_engine_irq": { + "ports": [ + "axi_spi_engine/irq", + "irq" + ] + }, + "axi_spi_engine_spi_resetn": { + "ports": [ + "axi_spi_engine/spi_resetn", + "spi_engine_execution/resetn" + ] + }, + "s_axi_aclk_0_1": { + "ports": [ + "s_axi_aclk", + "axi_spi_engine/s_axi_aclk" + ] + }, + "s_axi_aresetn_1": { + "ports": [ + "s_axi_aresetn", + "axi_spi_engine/s_axi_aresetn" + ] + }, + "spi_clk_0_1": { + "ports": [ + "spi_clk", + "axi_spi_engine/spi_clk", + "spi_engine_execution/clk" + ] + }, + "spi_engine_execution_0_active": { + "ports": [ + "spi_engine_execution/active", + "active" + ] + } + } + }, + "microblaze_ps_axi_periph": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip/system_bd_microblaze_ps_axi_periph_0/system_bd_microblaze_ps_axi_periph_0.xci", + "inst_hier_path": "microblaze_ps_axi_periph", + "xci_name": "system_bd_microblaze_ps_axi_periph_0", + "parameters": { + "NUM_MI": { + "value": "2" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M01_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M01_ARESETN" + } + } + }, + "M01_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "ip_revision": "33", + "xci_name": "system_bd_xbar_0", + "xci_path": "ip/system_bd_xbar_0/system_bd_xbar_0.xci", + "inst_hier_path": "microblaze_ps_axi_periph/xbar", + "parameters": { + "NUM_MI": { + "value": "2" + }, + "NUM_SI": { + "value": "1" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "s00_couplers_to_s00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m00_couplers_to_m00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m01_couplers_to_m01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "m00_couplers_to_microblaze_ps_axi_periph": { + "interface_ports": [ + "m00_couplers/M_AXI", + "M00_AXI" + ] + }, + "m01_couplers_to_microblaze_ps_axi_periph": { + "interface_ports": [ + "m01_couplers/M_AXI", + "M01_AXI" + ] + }, + "microblaze_ps_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "xbar_to_m01_couplers": { + "interface_ports": [ + "xbar/M01_AXI", + "m01_couplers/S_AXI" + ] + } + }, + "nets": { + "microblaze_ps_axi_periph_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/S_ACLK", + "s00_couplers/M_ACLK", + "m00_couplers/M_ACLK", + "m01_couplers/M_ACLK", + "m00_couplers/S_ACLK", + "m01_couplers/S_ACLK" + ] + }, + "microblaze_ps_axi_periph_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/S_ARESETN", + "s00_couplers/M_ARESETN", + "m00_couplers/M_ARESETN", + "m01_couplers/M_ARESETN", + "m00_couplers/S_ARESETN", + "m01_couplers/S_ARESETN" + ] + } + } + }, + "axi_gpio": { + "vlnv": "xilinx.com:ip:axi_gpio:2.0", + "ip_revision": "34", + "xci_name": "system_bd_axi_gpio_0_0", + "xci_path": "ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0.xci", + "inst_hier_path": "axi_gpio", + "parameters": { + "C_ALL_INPUTS_2": { + "value": "1" + }, + "C_ALL_OUTPUTS": { + "value": "1" + }, + "C_DOUT_DEFAULT": { + "value": "0xFFFFFFFF" + }, + "C_IS_DUAL": { + "value": "1" + } + } + }, + "mdm": { + "vlnv": "xilinx.com:ip:mdm_riscv:1.0", + "ip_revision": "2", + "xci_name": "system_bd_mdm_riscv_0", + "xci_path": "ip/system_bd_mdm_riscv_0/system_bd_mdm_riscv_0.xci", + "inst_hier_path": "mdm", + "parameters": { + "C_ADDR_SIZE": { + "value": "32" + }, + "C_AVOID_PRIMITIVES": { + "value": "0" + }, + "C_BRK": { + "value": "0" + }, + "C_BSCANID": { + "value": "76547328" + }, + "C_DATA_SIZE": { + "value": "32" + }, + "C_DBG_MEM_ACCESS": { + "value": "0" + }, + "C_DBG_REG_ACCESS": { + "value": "0" + }, + "C_DEBUG_INTERFACE": { + "value": "0" + }, + "C_INTERCONNECT": { + "value": "2" + }, + "C_JTAG_CHAIN": { + "value": "2" + }, + "C_LMB_PROTOCOL": { + "value": "0" + }, + "C_MB_DBG_PORTS": { + "value": "1" + }, + "C_M_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M_AXIS_ID_WIDTH": { + "value": "7" + }, + "C_M_AXI_ADDR_WIDTH": { + "value": "32" + }, + "C_M_AXI_DATA_WIDTH": { + "value": "32" + }, + "C_M_AXI_THREAD_ID_WIDTH": { + "value": "1" + }, + "C_S_AXI_ACLK_FREQ_HZ": { + "value": "100000000" + }, + "C_S_AXI_ADDR_WIDTH": { + "value": "9" + }, + "C_S_AXI_DATA_WIDTH": { + "value": "32" + }, + "C_USE_BSCAN": { + "value": "0" + }, + "C_USE_CONFIG_RESET": { + "value": "0" + }, + "C_XMTC": { + "value": "0" + } + } + }, + "microblaze_ps": { + "vlnv": "xilinx.com:ip:microblaze_riscv:1.0", + "ip_revision": "2", + "xci_name": "system_bd_microblaze_ps_riscv_0", + "xci_path": "ip/system_bd_microblaze_ps_riscv_0/system_bd_microblaze_ps_riscv_0.xci", + "inst_hier_path": "microblaze_ps", + "parameters": { + "C_ADDR_SIZE": { + "value": "32" + }, + "C_ASYNC_INTERRUPT": { + "value": "1" + }, + "C_ASYNC_WAKEUP": { + "value": "3" + }, + "C_AVOID_PRIMITIVES": { + "value": "0" + }, + "C_BASE_VECTORS": { + "value": "0x0000000000000000" + }, + "C_BRANCH_TARGET_CACHE_SIZE": { + "value": "0" + }, + "C_DATA_SIZE": { + "value": "32" + }, + "C_DC_AXI_MON": { + "value": "0" + }, + "C_DEBUG_COUNTER_WIDTH": { + "value": "32" + }, + "C_DEBUG_ENABLED": { + "value": "1" + }, + "C_DEBUG_EVENT_COUNTERS": { + "value": "5" + }, + "C_DEBUG_INTERFACE": { + "value": "0" + }, + "C_DEBUG_LATENCY_COUNTERS": { + "value": "1" + }, + "C_DEBUG_TRACE_ASYNC_RESET": { + "value": "0" + }, + "C_DP_AXI_MON": { + "value": "0" + }, + "C_D_AXI": { + "value": "1" + }, + "C_D_LMB": { + "value": "1" + }, + "C_D_LMB_MON": { + "value": "0" + }, + "C_D_LMB_PROTOCOL": { + "value": "0" + }, + "C_ECC_USE_CE_EXCEPTION": { + "value": "0" + }, + "C_EDGE_IS_POSITIVE": { + "value": "1" + }, + "C_ENABLE_DISCRETE_PORTS": { + "value": "0" + }, + "C_FAULT_TOLERANT": { + "value": "0" + }, + "C_FREQ": { + "value": "25000000" + }, + "C_FSL_LINKS": { + "value": "0" + }, + "C_IC_AXI_MON": { + "value": "0" + }, + "C_ILL_INSTR_EXCEPTION": { + "value": "0" + }, + "C_IMPRECISE_EXCEPTIONS": { + "value": "0" + }, + "C_INSTANCE": { + "value": "microblaze" + }, + "C_INTERCONNECT": { + "value": "2" + }, + "C_INTERRUPT_IS_EDGE": { + "value": "0" + }, + "C_INTERRUPT_MON": { + "value": "0" + }, + "C_IP_AXI_MON": { + "value": "0" + }, + "C_I_AXI": { + "value": "0" + }, + "C_I_LMB": { + "value": "1" + }, + "C_I_LMB_MON": { + "value": "0" + }, + "C_I_LMB_PROTOCOL": { + "value": "0" + }, + "C_LMB_DATA_SIZE": { + "value": "32" + }, + "C_LOCKSTEP_SELECT": { + "value": "0" + }, + "C_LOCKSTEP_SLAVE": { + "value": "0" + }, + "C_M0_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M0_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M10_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M10_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M11_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M11_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M12_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M12_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M13_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M13_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M14_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M14_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M15_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M15_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M1_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M1_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M2_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M2_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M3_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M3_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M4_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M4_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M5_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M5_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M6_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M6_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M7_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M7_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M8_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M8_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_M9_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_M9_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_MISALIGNED_EXCEPTIONS": { + "value": "0" + }, + "C_MMU_PRIVILEGED_INSTR": { + "value": "0" + }, + "C_M_AXI_DC_ADDR_WIDTH": { + "value": "32" + }, + "C_M_AXI_DC_ARUSER_WIDTH": { + "value": "5" + }, + "C_M_AXI_DC_AWUSER_WIDTH": { + "value": "5" + }, + "C_M_AXI_DC_BUSER_WIDTH": { + "value": "1" + }, + "C_M_AXI_DC_EXCLUSIVE_ACCESS": { + "value": "0" + }, + "C_M_AXI_DC_RUSER_WIDTH": { + "value": "1" + }, + "C_M_AXI_DC_THREAD_ID_WIDTH": { + "value": "1" + }, + "C_M_AXI_DC_USER_SIGNALS": { + "value": "0" + }, + "C_M_AXI_DC_USER_VALUE": { + "value": "31" + }, + "C_M_AXI_DC_WUSER_WIDTH": { + "value": "1" + }, + "C_M_AXI_DP_ADDR_WIDTH": { + "value": "32" + }, + "C_M_AXI_DP_DATA_WIDTH": { + "value": "32" + }, + "C_M_AXI_DP_EXCLUSIVE_ACCESS": { + "value": "0" + }, + "C_M_AXI_DP_THREAD_ID_WIDTH": { + "value": "1" + }, + "C_M_AXI_D_BUS_EXCEPTION": { + "value": "0" + }, + "C_M_AXI_IC_ADDR_WIDTH": { + "value": "32" + }, + "C_M_AXI_IC_ARUSER_WIDTH": { + "value": "5" + }, + "C_M_AXI_IC_AWUSER_WIDTH": { + "value": "5" + }, + "C_M_AXI_IC_BUSER_WIDTH": { + "value": "1" + }, + "C_M_AXI_IC_RUSER_WIDTH": { + "value": "1" + }, + "C_M_AXI_IC_THREAD_ID_WIDTH": { + "value": "1" + }, + "C_M_AXI_IC_USER_SIGNALS": { + "value": "0" + }, + "C_M_AXI_IC_USER_VALUE": { + "value": "31" + }, + "C_M_AXI_IC_WUSER_WIDTH": { + "value": "1" + }, + "C_M_AXI_IP_ADDR_WIDTH": { + "value": "32" + }, + "C_M_AXI_IP_DATA_WIDTH": { + "value": "32" + }, + "C_M_AXI_IP_THREAD_ID_WIDTH": { + "value": "1" + }, + "C_NUMBER_OF_PC_BRK": { + "value": "1" + }, + "C_NUMBER_OF_RD_ADDR_BRK": { + "value": "0" + }, + "C_NUMBER_OF_WR_ADDR_BRK": { + "value": "0" + }, + "C_NUM_SYNC_FF_CLK": { + "value": "2" + }, + "C_NUM_SYNC_FF_CLK_DEBUG": { + "value": "2" + }, + "C_NUM_SYNC_FF_CLK_IRQ": { + "value": "1" + }, + "C_NUM_SYNC_FF_DBG_CLK": { + "value": "1" + }, + "C_NUM_SYNC_FF_DBG_TRACE_CLK": { + "value": "2" + }, + "C_OPTIMIZATION": { + "value": "0" + }, + "C_PC_WIDTH": { + "value": "32" + }, + "C_S0_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S0_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S10_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S10_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S11_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S11_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S12_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S12_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S13_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S13_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S14_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S14_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S15_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S15_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S1_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S1_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S2_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S2_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S3_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S3_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S4_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S4_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S5_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S5_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S6_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S6_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S7_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S7_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S8_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S8_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_S9_AXIS_DATA_WIDTH": { + "value": "32" + }, + "C_S9_AXIS_PROTOCOL": { + "value": "GENERIC" + }, + "C_TEMPORAL_DEPTH": { + "value": "0" + }, + "C_TRACE": { + "value": "0" + }, + "C_USE_ATOMIC": { + "value": "0" + }, + "C_USE_BARREL": { + "value": "2" + }, + "C_USE_BRANCH_TARGET_CACHE": { + "value": "0" + }, + "C_USE_COMPRESSION": { + "value": "1" + }, + "C_USE_CONFIG_RESET": { + "value": "0" + }, + "C_USE_DCACHE": { + "value": "0" + }, + "C_USE_EXT_BRK": { + "value": "0" + }, + "C_USE_EXT_NM_BRK": { + "value": "0" + }, + "C_USE_FPU": { + "value": "0" + }, + "C_USE_ICACHE": { + "value": "0" + }, + "C_USE_INTERRUPT": { + "value": "0" + }, + "C_USE_MMU": { + "value": "0" + }, + "C_USE_MULDIV": { + "value": "0" + }, + "C_USE_NON_SECURE": { + "value": "0" + }, + "G_TEMPLATE_LIST": { + "value": "0" + } + }, + "interface_ports": { + "DLMB": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "ILMB": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "Master", + "address_space_ref": "Instruction", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "M_AXI_DP": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32" + }, + "Instruction": { + "range": "4G", + "width": "32" + } + } + }, + "hdl_attributes": { + "BMM_INFO_PROCESSOR": { + "value": "riscv > system_bd microblaze_ps_local_memory/dlmb_bram_if_cntlr", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + } + }, + "interface_nets": { + "axi_spi_engine_spi_1": { + "interface_ports": [ + "spi", + "axi_spi_engine/spi" + ] + }, + "microblaze_ps_M_AXI_DP": { + "interface_ports": [ + "microblaze_ps/M_AXI_DP", + "microblaze_ps_axi_periph/S00_AXI" + ] + }, + "microblaze_ps_axi_periph_M00_AXI": { + "interface_ports": [ + "microblaze_ps_axi_periph/M00_AXI", + "axi_spi_engine/s_axi" + ] + }, + "microblaze_ps_axi_periph_M01_AXI": { + "interface_ports": [ + "microblaze_ps_axi_periph/M01_AXI", + "axi_gpio/S_AXI" + ] + }, + "microblaze_ps_debug": { + "interface_ports": [ + "mdm/MBDEBUG_0", + "microblaze_ps/DEBUG" + ] + }, + "microblaze_ps_dlmb_1": { + "interface_ports": [ + "microblaze_ps/DLMB", + "microblaze_ps_local_memory/DLMB" + ] + }, + "microblaze_ps_ilmb_1": { + "interface_ports": [ + "microblaze_ps/ILMB", + "microblaze_ps_local_memory/ILMB" + ] + } + }, + "nets": { + "axi_gpio_gpio_io_o": { + "ports": [ + "axi_gpio/gpio_io_o", + "gpio_o" + ] + }, + "axi_spi_engine_active_0": { + "ports": [ + "axi_spi_engine/active", + "spi_active" + ] + }, + "clk_in1_0_1": { + "ports": [ + "clk_25MHz", + "clk_wiz_25M/clk_in1" + ] + }, + "clk_wiz_1_locked": { + "ports": [ + "clk_wiz_25M/locked", + "rst_clk_wiz_25M/ext_reset_in", + "rst_clk_wiz_25M/dcm_locked" + ] + }, + "gpio2_io_i_0_1": { + "ports": [ + "gpio_i", + "axi_gpio/gpio2_io_i" + ] + }, + "mdm_1_debug_sys_rst": { + "ports": [ + "mdm/Debug_SYS_Rst", + "rst_clk_wiz_25M/mb_debug_sys_rst" + ] + }, + "microblaze_ps_Clk": { + "ports": [ + "clk_wiz_25M/clk_out1", + "microblaze_ps_local_memory/LMB_Clk", + "axi_spi_engine/s_axi_aclk", + "axi_spi_engine/spi_clk", + "axi_gpio/s_axi_aclk", + "microblaze_ps_axi_periph/ACLK", + "microblaze_ps_axi_periph/S00_ACLK", + "microblaze_ps_axi_periph/M00_ACLK", + "microblaze_ps_axi_periph/M01_ACLK", + "rst_clk_wiz_25M/slowest_sync_clk", + "microblaze_ps/Clk" + ] + }, + "rst_clk_wiz_1_100M_bus_struct_reset": { + "ports": [ + "rst_clk_wiz_25M/bus_struct_reset", + "microblaze_ps_local_memory/SYS_Rst" + ] + }, + "rst_clk_wiz_1_100M_mb_reset": { + "ports": [ + "rst_clk_wiz_25M/mb_reset", + "microblaze_ps/Reset" + ] + }, + "rst_clk_wiz_25M_peripheral_aresetn": { + "ports": [ + "rst_clk_wiz_25M/peripheral_aresetn", + "axi_spi_engine/s_axi_aresetn", + "axi_gpio/s_axi_aresetn", + "microblaze_ps_axi_periph/ARESETN", + "microblaze_ps_axi_periph/S00_ARESETN", + "microblaze_ps_axi_periph/M00_ARESETN", + "microblaze_ps_axi_periph/M01_ARESETN" + ] + } + }, + "addressing": { + "/microblaze_ps": { + "address_spaces": { + "Data": { + "segments": { + "SEG_axi_gpio_Reg": { + "address_block": "/axi_gpio/S_AXI/Reg", + "offset": "0x40000000", + "range": "64K" + }, + "SEG_axi_spi_engine_axi_lite": { + "address_block": "/axi_spi_engine/axi_spi_engine/s_axi/axi_lite", + "offset": "0x44A00000", + "range": "64K" + }, + "SEG_dlmb_bram_if_cntlr_Mem": { + "address_block": "/microblaze_ps_local_memory/dlmb_bram_if_cntlr/SLMB/Mem", + "offset": "0x00000000", + "range": "256K", + "offset_high_param": "C_HIGHADDR" + } + } + }, + "Instruction": { + "segments": { + "SEG_ilmb_bram_if_cntlr_Mem": { + "address_block": "/microblaze_ps_local_memory/ilmb_bram_if_cntlr/SLMB/Mem", + "offset": "0x00000000", + "range": "256K", + "offset_high_param": "C_HIGHADDR" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/system_bd.bda b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/system_bd.bda new file mode 100644 index 0000000..06eef79 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/system_bd.bda @@ -0,0 +1,295 @@ +{ + "graphjs": { + "version": "1.0", + "keys": [ + { + "abrv": "VH", + "name": "vert_hid", + "type": "int", + "for": "node" + }, + { + "abrv": "VM", + "name": "vert_name", + "type": "string", + "for": "node" + }, + { + "abrv": "VT", + "name": "vert_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BA", + "name": "base_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "HA", + "name": "high_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "BP", + "name": "base_param", + "type": "string", + "for": "node" + }, + { + "abrv": "HP", + "name": "high_param", + "type": "string", + "for": "node" + }, + { + "abrv": "MA", + "name": "master_addrspace", + "type": "string", + "for": "node" + }, + { + "abrv": "MX", + "name": "master_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "MI", + "name": "master_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MS", + "name": "master_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "MV", + "name": "master_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "SX", + "name": "slave_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "SI", + "name": "slave_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MM", + "name": "slave_memmap", + "type": "string", + "for": "node" + }, + { + "abrv": "SS", + "name": "slave_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "SV", + "name": "slave_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "TM", + "name": "memory_type", + "type": "string", + "for": "node" + }, + { + "abrv": "TU", + "name": "usage_type", + "type": "string", + "for": "node" + }, + { + "abrv": "LT", + "name": "lock_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BT", + "name": "boot_type", + "type": "string", + "for": "node" + }, + { + "abrv": "EH", + "name": "edge_hid", + "type": "int", + "for": "edge" + } + ], + "vertice_type_order": [ + { + "abrv": "BC", + "desc": "Block Container" + }, + { + "abrv": "PR", + "desc": "Parital Reference" + }, + { + "abrv": "VR", + "desc": "Variant" + }, + { + "abrv": "PM", + "desc": "Variant Permutations" + }, + { + "abrv": "CX", + "desc": "Boundary Connection" + }, + { + "abrv": "AC", + "desc": "Assignment Coordinate" + }, + { + "abrv": "ACE", + "desc": "Excluded Assign Coordinate" + }, + { + "abrv": "APX", + "desc": "Boundary Aperture" + }, + { + "abrv": "CIP", + "desc": "High level Processing System" + } + ], + "vertices": { + "V0": { + "VM": "system_bd", + "VT": "BC" + }, + "V1": { + "VH": "2", + "VM": "system_bd", + "VT": "VR" + }, + "V2": { + "VH": "2", + "VT": "PM", + "TU": "active" + }, + "V3": { + "VT": "AC", + "BA": "0x00000000", + "HA": "0x0003FFFF", + "BP": "C_BASEADDR", + "HP": "C_HIGHADDR", + "MA": "Data", + "MX": "/microblaze_ps", + "MI": "DLMB", + "MS": "SEG_dlmb_bram_if_cntlr_Mem", + "MV": "xilinx.com:ip:microblaze_riscv:1.0", + "SX": "/microblaze_ps_local_memory/dlmb_bram_if_cntlr", + "SI": "SLMB", + "SS": "Mem", + "SV": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "TM": "both", + "TU": "memory" + }, + "V4": { + "VT": "AC", + "BA": "0x00000000", + "HA": "0x0003FFFF", + "BP": "C_BASEADDR", + "HP": "C_HIGHADDR", + "MA": "Instruction", + "MX": "/microblaze_ps", + "MI": "ILMB", + "MS": "SEG_ilmb_bram_if_cntlr_Mem", + "MV": "xilinx.com:ip:microblaze_riscv:1.0", + "SX": "/microblaze_ps_local_memory/ilmb_bram_if_cntlr", + "SI": "SLMB", + "SS": "Mem", + "SV": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "TM": "both", + "TU": "memory" + }, + "V5": { + "VT": "AC", + "BA": "0x40000000", + "HA": "0x4000FFFF", + "BP": "C_BASEADDR", + "HP": "C_HIGHADDR", + "MA": "Data", + "MX": "/microblaze_ps", + "MI": "M_AXI_DP", + "MS": "SEG_axi_gpio_Reg", + "MV": "xilinx.com:ip:microblaze_riscv:1.0", + "SX": "/axi_gpio", + "SI": "S_AXI", + "SS": "Reg", + "SV": "xilinx.com:ip:axi_gpio:2.0", + "TM": "both", + "TU": "register" + }, + "V6": { + "VT": "AC", + "BA": "0x44A00000", + "HA": "0x44A0FFFF", + "BP": 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+1,45 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-339,-74", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS +# -string -flagsOSRD +preplace port spi -pg 1 -lvl 4 -x 1140 -y 510 -defaultsOSRD +preplace port port-id_clk_25MHz -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD +preplace port port-id_spi_active -pg 1 -lvl 4 -x 1140 -y 530 -defaultsOSRD +preplace portBus gpio_o -pg 1 -lvl 4 -x 1140 -y 360 -defaultsOSRD +preplace portBus gpio_i -pg 1 -lvl 4 -x 1140 -y 400 -defaultsOSRD -right +preplace inst microblaze_ps_local_memory -pg 1 -lvl 3 -x 970 -y 100 -defaultsOSRD +preplace inst clk_wiz_25M -pg 1 -lvl 1 -x 130 -y 260 -defaultsOSRD +preplace inst rst_clk_wiz_25M -pg 1 -lvl 2 -x 540 -y 290 -defaultsOSRD +preplace inst axi_spi_engine -pg 1 -lvl 3 -x 970 -y 530 -defaultsOSRD +preplace inst microblaze_ps_axi_periph -pg 1 -lvl 2 -x 540 -y 510 -defaultsOSRD +preplace inst axi_gpio -pg 1 -lvl 3 -x 970 -y 370 -defaultsOSRD +preplace inst mdm -pg 1 -lvl 1 -x 130 -y 90 -defaultsOSRD +preplace inst microblaze_ps -pg 1 -lvl 2 -x 540 -y 90 -defaultsOSRD +preplace netloc axi_gpio_gpio_io_o 1 3 1 N 360 +preplace netloc axi_spi_engine_active_0 1 3 1 N 530 +preplace netloc clk_in1_0_1 1 0 1 N 260 +preplace netloc clk_wiz_1_locked 1 1 1 250 270n +preplace netloc gpio2_io_i_0_1 1 3 1 N 400 +preplace netloc mdm_1_debug_sys_rst 1 1 1 240 100n +preplace netloc microblaze_ps_Clk 1 1 2 260 650 820 +preplace netloc rst_clk_wiz_1_100M_bus_struct_reset 1 2 1 810J 130n +preplace netloc rst_clk_wiz_1_100M_mb_reset 1 1 2 280 190 800 +preplace netloc rst_clk_wiz_25M_peripheral_aresetn 1 1 2 280 660 800 +preplace netloc microblaze_ps_M_AXI_DP 1 1 2 270 180 800 +preplace netloc microblaze_ps_axi_periph_M00_AXI 1 2 1 N 500 +preplace netloc microblaze_ps_axi_periph_M01_AXI 1 2 1 810 350n +preplace netloc microblaze_ps_debug 1 1 1 N 80 +preplace netloc microblaze_ps_dlmb_1 1 2 1 N 70 +preplace netloc microblaze_ps_ilmb_1 1 2 1 N 90 +preplace netloc axi_spi_engine_spi_1 1 3 1 N 510 +levelinfo -pg 1 0 130 540 970 1140 +pagesize -pg 1 -db -bbox -sgen -130 0 1280 670 +" +} +{ + "da_axi4_cnt":"2", + "da_mb_cnt":"2" +} diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui new file mode 100644 index 0000000..71e9c00 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui @@ -0,0 +1,30 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-209,-166", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS +# -string -flagsOSRD +preplace port s_axi -pg 1 -lvl 0 -x 0 -y 50 -defaultsOSRD +preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD +preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y 90 -defaultsOSRD +preplace port port-id_spi_clk -pg 1 -lvl 0 -x 0 -y 110 -defaultsOSRD +preplace port port-id_active -pg 1 -lvl 3 -x 710 -y 90 -defaultsOSRD +preplace port port-id_irq -pg 1 -lvl 3 -x 710 -y 0 -defaultsOSRD +preplace port spi -pg 1 -lvl 3 -x 710 -y 70 -defaultsOSRD +preplace inst axi_spi_engine -pg 1 -lvl 1 -x 320 -y 80 -defaultsOSRD +preplace inst spi_engine_execution -pg 1 -lvl 2 -x 580 -y 80 -defaultsOSRD +preplace netloc axi_spi_engine_irq 1 1 2 460J 0 NJ +preplace netloc axi_spi_engine_spi_resetn 1 1 1 N 100 +preplace netloc s_axi_aclk_0_1 1 0 1 NJ 70 +preplace netloc s_axi_aresetn_1 1 0 1 NJ 90 +preplace netloc spi_clk_0_1 1 0 2 180 170 470J +preplace netloc spi_engine_execution_0_active 1 2 1 NJ 90 +preplace netloc Conn1 1 0 1 NJ 50 +preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N 60 +preplace netloc Conn3 1 2 1 N 70 +levelinfo -pg 1 0 320 580 710 +pagesize -pg 1 -db -bbox -sgen -150 -200 810 310 +" +} +0 diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci new file mode 100644 index 0000000..394b3a4 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci @@ -0,0 +1,714 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "ad9361_clk_gen_cmos_2t2r", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "14", + "gen_directory": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/ad9361_clk_gen_cmos_2t2r", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "ad9361_clk_gen_cmos_2t2r", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], + "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], + "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ], + "PRIM_IN_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], + "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ], + "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ], + "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ], + "USE_INCLK_SWITCHOVER": [ { "value": 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"all" } ], + "CLKIN1_JITTER_PS": [ { "value": "104.16", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "48", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "144", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "192", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "12.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "10.417", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "24.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], + "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ], + "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ], + "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ], + "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_JITTER": [ { "value": "139.139", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_PHASE_ERROR": [ { "value": "89.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_JITTER": [ { "value": "120.859", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_PHASE_ERROR": [ { "value": "89.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_JITTER": [ { "value": "112.241", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_PHASE_ERROR": [ { "value": "89.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_JITTER": [ { "value": "106.524", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_PHASE_ERROR": [ { "value": "89.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ], + "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ] + }, + "model_parameters": { + "C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", 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"resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Differential_clock_capable_pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "18.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "4.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "9.375", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], + "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ], + "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": 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b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci new file mode 100644 index 0000000..a451d75 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci @@ -0,0 +1,714 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "ant_clk_gen_stg2", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "14", + "gen_directory": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/ant_clk_gen_stg2", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "ant_clk_gen_stg2", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } 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"physical_name": "s_axis_b_tvalid" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/coe/hrc_64_12_025.coe b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/coe/hrc_64_12_025.coe new file mode 100644 index 0000000..64167ba --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/coe/hrc_64_12_025.coe @@ -0,0 +1,771 @@ +RADIX = 10; +COEFDATA = +-47, +-30, +-13, +4, +21, +38, +56, +73, +89, +106, +122, +138, +153, +168, +182, +196, +209, +221, +232, +243, +252, +261, +268, +275, +281, +285, +289, +291, +292, +292, +291, +288, +285, +280, +274, +267, +259, +249, +239, +228, +215, +202, +187, +172, +156, +139, +122, +104, +85, +66, +46, +26, +5, +-15, +-36, +-56, +-77, +-98, +-118, +-138, +-158, +-177, +-195, +-213, +-231, +-247, +-263, +-277, +-291, +-303, +-314, +-325, +-333, +-341, +-347, +-351, +-354, +-356, +-356, +-354, +-351, +-346, +-340, +-332, +-322, +-311, +-298, +-284, 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0000000..e0e08f5 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/coe/one_hop_data.coe @@ -0,0 +1,9602 @@ +MEMORY_INITIALIZATION_RADIX = 2; +MEMORY_INITIALIZATION_VECTOR = +110001101100110010100111001010100100000111001110111001011100111001111110101110100001111000111111, +000010001010000010101011010110110011000110010001101101001110110100000011000100010000000110111100, +010101001111001010011101000100111011110111101101111010101101000001001011011001010010000111001110, +001110010011111110111111101000101011110101000000010011110100001010001000001111011101110110110010, +110010000011110100011000100111000011000111010001010110100010111111010111101111101100101111000011, +100100001011111110011011000101001010010110011110111011100000110001011000100001010011000000110100, +111001000101010001001001011110110111001001011111100011010100111000111111110111111000011000001111, +011000100010001111010001010100010001101100000011101101110100010000100011011000100110010100100101, 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Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ApproxModuli_26bit( + input clk, + input din_valid, + input [25:0] din_I, + input [25:0] din_Q, + output reg dout_valid = 0, + output reg [25:0] dout = 0 + ); + +reg [25:0] din_I_D1 = 0, din_Q_D1 = 0, din_I_D2 = 0, din_Q_D2 = 0; +reg [25:0] Sub1_s = 0; +reg [25:0] Xmax = 0, Xmin = 0; +always @(posedge clk) + begin + if(din_valid) + din_I_D1[25:0] <= (din_I[25]==1'b0)? din_I[25:0]:-din_I[25:0]; + else + din_I_D1[25:0] <= 26'd0; + + din_I_D2[25:0] <= din_I_D1[25:0]; + + if(din_valid) + din_Q_D1[25:0] <= (din_Q[25]==1'b0)? din_Q[25:0]:-din_Q[25:0]; + else + din_Q_D1[25:0] <= 26'd0; + + din_Q_D2[25:0] <= din_Q_D1[25:0]; + + Sub1_s[25:0] <= din_I_D1[25:0] - din_Q_D1[25:0]; + + if(Sub1_s[25]) + Xmax[25:0] <= din_Q_D2[25:0]; + else + Xmax[25:0] <= din_I_D2[25:0]; + + if(Sub1_s[25]) + Xmin[25:0] <= din_I_D2[25:0]; + else + Xmin[25:0] <= din_Q_D2[25:0]; + end + +reg [25:0] Xmax_D1 = 0, Xmax_31by32 = 0, Xmax_13by16 = 0; +reg [25:0] Xmin_9by32 = 0, Xmin_19by32 = 0; +always @(posedge clk) + begin + Xmax_D1[25:0] <= Xmax[25:0]; + Xmax_31by32[25:0] <= Xmax[25:0] - {5'd0, Xmax[25:5]}; + Xmax_13by16[25:0] <= Xmax[25:0] - {3'd0, Xmax[25:3]} - {4'd0, Xmax[25:4]}; + + Xmin_9by32[25:0] <= {2'd0, Xmin[25:2]} + {5'd0, Xmin[25:5]}; + Xmin_19by32[25:0] <= {1'd0, Xmin[25:1]} + {4'd0, Xmin[25:4]} + {5'd0, Xmin[25:5]}; + end + +reg [25:0] t1 = 0, t2 = 0, t3 = 0; +always @(posedge clk) + begin + t1[25:0] <= Xmax_D1[25:0]; + t2[25:0] <= Xmax_31by32[25:0] + Xmin_9by32[25:0]; + t3[25:0] <= Xmax_13by16[25:0] + Xmin_19by32[25:0]; + end + +reg [25:0] sub2_s = 0; +reg [25:0] sub3_a = 0, sub3_b = 0, sub3_s = 0; +reg [25:0] sub3_a_D1 = 0, sub3_b_D1 = 0; +reg [25:0] t1_D1 = 0, t2_D1 = 0, t3_D1 = 0; +always @(posedge clk) + begin + t1_D1[25:0] <= t1[25:0]; + t2_D1[25:0] <= t2[25:0]; + t3_D1[25:0] <= t3[25:0]; + + sub2_s[25:0] <= t1[25:0] - t2[25:0]; + + if(sub2_s[25]) + sub3_a[25:0] <= t2_D1[25:0]; + else + sub3_a[25:0] <= t1_D1[25:0]; + + sub3_b[25:0] <= t3_D1[25:0]; + + sub3_a_D1[25:0] <= sub3_a[25:0]; + sub3_b_D1[25:0] <= sub3_b[25:0]; + + sub3_s[25:0] <= sub3_a[25:0] - sub3_b[25:0]; + + if(sub3_s[25]) + dout[25:0] <= sub3_b_D1[25:0]; + else + dout[25:0] <= sub3_a_D1[25:0]; + end + +reg din_valid_D1 = 0, din_valid_D2 = 0, din_valid_D3 = 0, din_valid_D4 = 0; +reg din_valid_D5 = 0, din_valid_D6 = 0, din_valid_D7 = 0, din_valid_D8 = 0; +always @(posedge clk) + begin + din_valid_D1 <= din_valid; + din_valid_D2 <= din_valid_D1; + din_valid_D3 <= din_valid_D2; + din_valid_D4 <= din_valid_D3; + din_valid_D5 <= din_valid_D4; + din_valid_D6 <= din_valid_D5; + din_valid_D7 <= din_valid_D6; + din_valid_D8 <= din_valid_D7; + + dout_valid <= din_valid_D8; + end +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v new file mode 100644 index 0000000..5e308fa --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v @@ -0,0 +1,196 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 17:37:27 +// Last Modified Date: 2023/03/06 11:26 +// Design Name: +// Module Name: ad9361_rx_map_cmos_dual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_rx_map_cmos_dual +( + input clk_2x_in , + input clk_in_rst , + + input rx_data_clk , // sync to output data + input rx_data_clk_rst , + + input rx_fifo_rst , // async fifo reset + + input rx_frame , + input [11:0] rx_data , + + output [11:0] rx_ch1_i , + output [11:0] rx_ch1_q , + output [11:0] rx_ch2_i , + output [11:0] rx_ch2_q +); + +genvar m; + +// rx data +wire [11:0] rx_data_i, rx_data_q; + +generate +for (m=0; m<12; m=m+1) begin : rx_data_iddr + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT_Q1 (1'b0 ), + .INIT_Q2 (1'b0 ), + .SRTYPE ("ASYNC" ) +) i_rx_data_iddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D (rx_data[m] ), + .Q1 (rx_data_q[m] ), + .Q2 (rx_data_i[m] ) +); + +end +endgenerate + +// rx frame +wire rx_frame_i; +wire rx_frame_q; + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT_Q1 (1'b0 ), + .INIT_Q2 (1'b0 ), + .SRTYPE ("ASYNC" ) +) i_rx_frame_iddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D (rx_frame ), + .Q1 (rx_frame_q ), + .Q2 (rx_frame_i ) +); + +// divide rx_data to dual channel +reg [11:0] rx1_data_i = 'b0; +reg [11:0] rx1_data_q = 'b0; +reg [11:0] rx2_data_i = 'b0; +reg [11:0] rx2_data_q = 'b0; + +wire rx_fifo_wr_en; +reg rx_fifo_rd_en = 'b0; + +wire rx_fifo_empty_1; +wire rx_fifo_empty_2; +wire rx_fifo_empty_3; +wire rx_fifo_empty_4; + +assign rx_fifo_wr_en = rx_frame_i; // align data & write enable + +always @ (posedge clk_2x_in) begin + if (clk_in_rst) begin + rx1_data_i <= 'b0; + rx2_data_i <= 'b0; + end + else if(rx_frame_i) begin + rx1_data_i <= rx_data_i; + end + else begin + rx2_data_i <= rx_data_i; + end +end + +always @ (posedge clk_2x_in) begin + if (clk_in_rst) begin + rx1_data_q <= 'b0; + rx2_data_q <= 'b0; + end + else if(rx_frame_q) begin + rx1_data_q <= rx_data_q; + end + else begin + rx2_data_q <= rx_data_q; + end +end + +always @(posedge rx_data_clk) begin + if (rx_data_clk_rst) begin + rx_fifo_rd_en <= 'b0; + end + else begin + rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}; + end +end + +ad9361_fifo u_rx_fifo_ch1_i +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx1_data_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_1) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch1_q +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx1_data_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_2) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch2_i +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx2_data_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_3) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch2_q +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx2_data_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_4) // output wire empty +); + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v new file mode 100644 index 0000000..7fb0b8a --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v @@ -0,0 +1,183 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 16:39:19 +// Last Modified Date: 2023/03/06 11:45 +// Design Name: +// Module Name: ad9361_tx_map_cmos_dual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_tx_map_cmos_dual +( + input clk_2x_in , + input clk_in_rst , + + input tx_data_clk , + input tx_data_clk_rst , + + input [11:0] tx_ch1_i , + input [11:0] tx_ch1_q , + input [11:0] tx_ch2_i , + input [11:0] tx_ch2_q , + + output clk_out , + output tx_frame , + output [11:0] tx_data +); + +genvar m; + +// input data fifo +reg rx_fifo_rd_en = 'b0; +wire [11:0] tx_fifo_ch1_i; +wire [11:0] tx_fifo_ch1_q; +wire [11:0] tx_fifo_ch2_i; +wire [11:0] tx_fifo_ch2_q; + +always @(posedge clk_2x_in) begin + if (clk_in_rst) begin + rx_fifo_rd_en <= 'b0; + end + else begin + rx_fifo_rd_en <= ~rx_fifo_rd_en; + end +end + +ad9361_fifo u_tx_fifo_ch1_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_ch1_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch1_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch1_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_ch1_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch1_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch2_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_ch2_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch2_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch2_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_ch2_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch2_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +// frame and data control +reg tx_frame_i = 'b0; +reg tx_frame_q = 'b0; +reg [11:0] tx_data_i = 'b0; +reg [11:0] tx_data_q = 'b0; + +always @(posedge clk_2x_in) begin + if (clk_in_rst) begin + tx_frame_i <= 'b0; + tx_frame_q <= 'b0; + tx_data_i <= 'b0; + tx_data_q <= 'b0; + end + else if (rx_fifo_rd_en == 1'b0) begin + tx_frame_i <= 1'b1; + tx_frame_q <= 1'b1; + tx_data_i <= tx_fifo_ch1_i; + tx_data_q <= tx_fifo_ch1_q; + end + else begin + tx_frame_i <= 1'b0; + tx_frame_q <= 1'b0; + tx_data_i <= tx_fifo_ch2_i; + tx_data_q <= tx_fifo_ch2_q; + end +end + +// output clock to port +assign clk_out = clk_2x_in; + +// output tx frame to port +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_frame_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D1 (tx_frame_i ), + .D2 (tx_frame_q ), + .Q (tx_frame ) +); + +// output tx data to port +generate +for (m=0; m<12; m=m+1) begin: tx_data_oddr + +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_data_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D1 (tx_data_i[m] ), + .D2 (tx_data_q[m] ), + .Q (tx_data[m] ) +); + +end +endgenerate + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/adder_tree_ppl.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/adder_tree_ppl.v new file mode 100644 index 0000000..bb4b000 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/adder_tree_ppl.v @@ -0,0 +1,246 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/13 16:05:53 +// Design Name: +// Module Name: adder_tree_ppl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// REF: https://blog.csdn.net/jiang1960034308/article/details/118078073 +// https://github.com/raiker/tarsier/tree/master/src/ +// +////////////////////////////////////////////////////////////////////////////////// + + +module adder_tree_ppl +#( + parameter DATA_I_WIDTH = 8, + parameter DATA_NUM = 5, + parameter DELAY_STAGE = $clog2(DATA_NUM), // necessary for pipeline delay stage + + localparam DATA_O_WIDTH = DATA_I_WIDTH + $clog2(DATA_NUM), + localparam DATA_NUM_A = DATA_NUM / 2, + localparam DATA_NUM_B = DATA_NUM - DATA_NUM_A, + localparam DATA_O_WIDTH_A = DATA_I_WIDTH + $clog2(DATA_NUM_A), + localparam DATA_O_WIDTH_B = DATA_I_WIDTH + $clog2(DATA_NUM_B) +) +( + // clock & reset + input clk, + input rst, + + // input data + input din_valid, + input signed [DATA_NUM*DATA_I_WIDTH-1 : 0] din_data, + + // output data + output dout_valid, + output signed [DATA_O_WIDTH-1 : 0] dout_data +); + +if (DATA_NUM == 1) begin + if (DELAY_STAGE == 1) begin + // buffer when an extra delay stage is needed + reg dout_valid_buf = 'b0; + reg signed [DATA_O_WIDTH-1 : 0] dout_data_buf = 'b0; + + always@(posedge clk) begin + dout_valid_buf <= (rst) ? 'b0 : din_valid; + dout_data_buf <= (rst) ? 'b0 : din_data; + end + + assign dout_valid = dout_valid_buf; + assign dout_data = dout_data_buf; + end + else begin + assign dout_valid = din_valid; + assign dout_data = din_data; + end +end +else begin + reg dout_valid_buf = 'b0; + reg signed [DATA_O_WIDTH-1 : 0] dout_data_buf = 'b0; + + wire din_valid_a; + wire din_valid_b; + wire signed [DATA_I_WIDTH * DATA_NUM_A - 1:0] din_data_a; + wire signed [DATA_I_WIDTH * DATA_NUM_B - 1:0] din_data_b; + + wire dout_valid_a; + wire dout_valid_b; + wire signed [DATA_O_WIDTH_A-1:0] dout_data_a; + wire signed [DATA_O_WIDTH_B-1:0] dout_data_b; + + assign din_valid_a = din_valid; + assign din_valid_b = din_valid; + assign din_data_a = din_data[DATA_I_WIDTH * DATA_NUM_A - 1: 0]; + assign din_data_b = din_data[DATA_NUM * DATA_I_WIDTH - 1: DATA_I_WIDTH * DATA_NUM_A]; + + //divide set into two chunks, conquer + adder_tree_ppl #( + .DATA_I_WIDTH (DATA_I_WIDTH ), + .DATA_NUM (DATA_NUM_A ), + .DELAY_STAGE (DELAY_STAGE - 1) + ) subtree_a ( + // clock & reset + .clk (clk ), + .rst (rst ), + + // input data + .din_valid (din_valid_a ), + .din_data (din_data_a ), + + // output data + .dout_valid (dout_valid_a ), + .dout_data (dout_data_a ) + ); + + adder_tree_ppl #( + .DATA_I_WIDTH (DATA_I_WIDTH ), + .DATA_NUM (DATA_NUM_B ), + .DELAY_STAGE (DELAY_STAGE - 1) + ) subtree_b ( + // clock & reset + .clk (clk ), + .rst (rst ), + + // input data + .din_valid (din_valid_b ), + .din_data (din_data_b ), + + // output data + .dout_valid (dout_valid_b ), + .dout_data (dout_data_b ) + ); + + always@(posedge clk) begin + if (rst) begin + dout_valid_buf <= 'b0; + dout_data_buf <= 'b0; + end + else begin + dout_valid_buf <= dout_valid_a & dout_valid_b; + dout_data_buf <= dout_data_a + dout_data_b; + end + end + + assign dout_valid = dout_valid_buf; + assign dout_data = dout_data_buf; +end + +endmodule + + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/13 16:40:15 +// Last Modified Data: 2022/11/02 +// Design Name: +// Module Name: tb_adder_tree_pip +// Project Name: +// Target Devices: +// Tool Versions: +// Description: testbench for [adder_tree_ppl] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// module tb_adder_tree_ppl; + +// localparam DATA_I_WIDTH = 16; +// localparam DATA_NUM = 9; + +// reg clk = 1'b1; +// reg rst = 1'b1; +// reg din_valid = 1'b0; +// reg [DATA_NUM*DATA_I_WIDTH-1 : 0] din_data = 'b0; +// wire dout_valid; +// wire [DATA_I_WIDTH+$clog2(DATA_NUM)-1 : 0] dout_data; + +// adder_tree_ppl #( +// .DATA_I_WIDTH (DATA_I_WIDTH ), +// .DATA_NUM (DATA_NUM ) +// ) u_adder_tree_ppl +// ( +// // clock & reset +// .clk (clk ), +// .rst (rst ), + +// // input data +// .din_valid (din_valid ), +// .din_data (din_data ), + +// // output data +// .dout_valid (dout_valid ), +// .dout_data (dout_data ) +// ); + +// initial begin +// #102 +// rst = 1'b0; +// #200 +// @(posedge clk) begin +// din_valid = 1'b1; +// din_data = { +// 16'd1, +// 16'd2, +// 16'd3, +// 16'd4, +// 16'd5, +// 16'd6, +// 16'd7, +// 16'd8, +// 16'd9 +// }; +// end + +// @(posedge clk) begin +// din_valid = 1'b1; +// din_data = { +// 16'd1230, +// 16'd1231, +// 16'd1232, +// 16'd1233, +// 16'd1234, +// 16'd1235, +// 16'd1236, +// 16'd1237, +// 16'd1238 +// }; +// end + + +// @(posedge clk) din_valid = 1'b0; +// end + +// always #5 clk = ~clk; + +// endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/ADF4351_2.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/ADF4351_2.v new file mode 100644 index 0000000..7b9ade5 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/ADF4351_2.v @@ -0,0 +1,188 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:51:06 06/08/2020 +// Design Name: +// Module Name: test_784TR_top +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// ??????9?byte? ?1-8?????????????????8???????????????????3?byte???5?don't care?? +// ?9byte??4bit??spi??4bit?????? +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +/*************?????????*******************/ +module adf4351_2( +input i_sysclk , +input i_arstn , +output o_cfgover , +output o_ADF4351_SCK , +output o_ADF4351_DATA , +output o_ADF4351_LE , +output o_ADF4351_CE , +output o_ADF4351_mutel , +input i_ADF4351_locked + ); + + +localparam DATA_WIDTH = 32; +localparam DATA_LENTH = 6; +localparam SYS_CLOCK = 10; +localparam LOCK_PIRED = SYS_CLOCK * 100000; +localparam rst_time = 16'h7fff;//16'h7fff +reg[7:0] cnt_word = 8'd0; +reg[5:0] cnt_bits = 6'd0; + +reg [DATA_WIDTH-1:0] cfgdata = 0; +wire [DATA_WIDTH-1:0] regdata; +reg cfgover = 1'b0 ; +reg pll_locked = 1'b0 ; +reg load_en = 1'b0 ; +reg [31:0] cnt_lock = 32'b0; +(* KEEP = "TRUE" *)reg[3:0] cfgstate = 4'b0000; +wire spiIdle; + +reg spi_sdi = 1'b0,spi_csb = 1'b1 ; +assign o_cfgover = cfgover ; +assign o_ADF4351_LE = load_en ; +assign o_ADF4351_mutel= 1'b1 ; +assign o_ADF4351_SCK = o_ADF4351_CE ? 1'b0 : i_sysclk ; +assign o_ADF4351_CE = spi_csb ; +assign o_ADF4351_DATA = spi_sdi ; +reg [DATA_WIDTH-1:0] CFGREG0 ; +assign regdata = CFGREG0 ; +reg cfg_start ; +reg [15:0] counter0 ; + +always@ (posedge i_sysclk) +if(~i_arstn) + CFGREG0 <= 32'b0; +else begin +//RFout = Fpfd*(INT + (Frac/Mod)) Fpfd = Refin*[(1+D)/(R*(1+T))] + case (cnt_word) + 8'h00: CFGREG0 <= {32'h580005}; //reg 5 + 8'h01: CFGREG0 <= {32'h85003C}; //reg 4 + 8'h02: CFGREG0 <= {32'h4B3}; //reg 3 + 8'h03: CFGREG0 <= {32'h28F42}; //reg 2 {5'b0,T,R,D,12'h,reg2} R = 1 D = 1 T = 1 + 8'h04: CFGREG0 <= {32'h8008011}; //reg 1 {3'd0,phase adjust,prescaler,phase value,Frac,reg1}mod = 25 + 8'h05: CFGREG0 <= {32'hC80000}; //reg 0 {1'b0,int,frac,reg0} int = 52 frac= 8 + default : CFGREG0 <= 32'b0; + endcase +end + + + + + +always@(negedge i_sysclk)begin + if(~i_arstn)begin + cfgdata <= 0; + cnt_word <= 8'd0; + cnt_bits <= 6'd0; + cfgover <= 1'b0; + cfgstate <= 4'd0; + spi_csb <= 1'b1; + load_en <= 1'b1; + spi_sdi <= 1'b0; + end + else begin + case(cfgstate) + 4'd0:begin + if(cfg_start)begin + cfgstate <= 4'd1; + end + else begin + spi_csb <= 1'b1; + load_en <= 1'b0; + spi_sdi <= 1'b0; + cfgover <= 1'b0; + cfgstate <= 4'd0; + end + end + 4'd1:begin + cfgdata <= regdata; + cnt_lock <= 32'd0; + cnt_bits <= 6'd0; + cfgstate <= cfgstate + 1'b1; + end + 4'd2:begin + spi_csb <= 1'b0; + load_en <= 1'b0; + spi_sdi <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + cfgstate <= cfgstate + 1'b1; + cnt_word <= cnt_word + 1'b1; + end + end + 4'd3:begin + spi_csb <= 1'b1; + load_en <= 1'b1; + spi_sdi <= 1'b0; + if(cnt_word == DATA_LENTH) + cfgstate <= cfgstate + 1'b1; + else + cfgstate <= 4'd0; + end + 4'd4:begin + cfgstate <= 4'd5; + spi_csb <= 1'b1; + load_en <= 1'b0; + spi_sdi <= 1'b0; + end + 4'd5:begin//ftw cfg + if(cnt_lock > LOCK_PIRED) + begin + pll_locked <= i_ADF4351_locked; + cnt_lock <= cnt_lock; + if( (pll_locked == 1'b0) && (cnt_lock > LOCK_PIRED)) + begin + cfgstate <= 4'd1; + cnt_word <= 8'd0; + end + else + begin + cfgstate <= 4'd5; + spi_csb <= 1'b1; + spi_sdi <= 1'b0; + cfgover <= 1'b1; + end + end + else + begin + cnt_lock <= cnt_lock + 1'b1; + end + end + default:cfgstate <= 4'd0; + endcase + end +end + + +always@(negedge i_sysclk)begin + if(~i_arstn)begin + counter0 <= 16'd0; + cfg_start <= 1'b0; + end + else begin + if(counter0 == rst_time)begin//16'h7fff + counter0 <= counter0; + cfg_start <= 1'b1; + end + else begin + counter0 <= counter0 + 1'b1; + cfg_start <= 1'b0; + end + end +end + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/FRAC1.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/FRAC1.v new file mode 100644 index 0000000..6cc0ff3 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/FRAC1.v @@ -0,0 +1,441 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:37:16 01/15/2022 +// Design Name: +// Module Name: FRAC1 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module FRAC1( +input clka, +input [15:0] addra, +output reg[24:0] douta + ); + + +reg[11:0] addr=0; + +always@(posedge clka)begin + addr<= (addra+375) % 400 ; +end + +always@(posedge clka)begin + case(addr) +0 : douta <= 0 ; +1 : douta <= 83886 ; +2 : douta <= 167772 ; +3 : douta <= 251658 ; +4 : douta <= 335544 ; +5 : douta <= 419430 ; +6 : douta <= 503316 ; +7 : douta <= 587202 ; +8 : douta <= 671088 ; +9 : douta <= 754974 ; +10 : douta <= 838860 ; +11 : douta <= 922746 ; +12 : douta <= 1006632 ; +13 : douta <= 1090519 ; +14 : douta <= 1174405 ; +15 : douta <= 1258291 ; +16 : douta <= 1342177 ; +17 : douta <= 1426063 ; +18 : douta <= 1509949 ; +19 : douta <= 1593835 ; +20 : douta <= 1677721 ; +21 : douta <= 1761607 ; +22 : douta <= 1845493 ; +23 : douta <= 1929379 ; +24 : douta <= 2013265 ; +25 : douta <= 2097152 ; +26 : douta <= 2181038 ; +27 : douta <= 2264924 ; +28 : douta <= 2348810 ; +29 : douta <= 2432696 ; +30 : douta <= 2516582 ; +31 : douta <= 2600468 ; +32 : douta <= 2684354 ; +33 : douta <= 2768240 ; +34 : douta <= 2852126 ; +35 : douta <= 2936012 ; +36 : douta <= 3019898 ; +37 : douta <= 3103784 ; +38 : douta <= 3187671 ; +39 : douta <= 3271557 ; +40 : douta <= 3355443 ; +41 : douta <= 3439329 ; +42 : douta <= 3523215 ; +43 : douta <= 3607101 ; +44 : douta <= 3690987 ; +45 : douta <= 3774873 ; +46 : douta <= 3858759 ; +47 : douta <= 3942645 ; +48 : douta <= 4026531 ; +49 : douta <= 4110417 ; +50 : douta <= 4194304 ; +51 : douta <= 4278190 ; +52 : douta <= 4362076 ; +53 : douta <= 4445962 ; +54 : douta <= 4529848 ; +55 : douta <= 4613734 ; +56 : douta <= 4697620 ; +57 : douta <= 4781506 ; +58 : douta <= 4865392 ; +59 : douta <= 4949278 ; +60 : douta <= 5033164 ; +61 : douta <= 5117050 ; +62 : douta <= 5200936 ; +63 : douta <= 5284823 ; +64 : douta <= 5368709 ; +65 : douta <= 5452595 ; +66 : douta <= 5536481 ; +67 : douta <= 5620367 ; +68 : douta <= 5704253 ; +69 : douta <= 5788139 ; +70 : douta <= 5872025 ; +71 : douta <= 5955911 ; +72 : douta <= 6039797 ; +73 : douta <= 6123683 ; +74 : douta <= 6207569 ; +75 : douta <= 6291456 ; +76 : douta <= 6375342 ; +77 : douta <= 6459228 ; +78 : douta <= 6543114 ; +79 : douta <= 6627000 ; +80 : douta <= 6710886 ; +81 : douta <= 6794772 ; +82 : douta <= 6878658 ; +83 : douta <= 6962544 ; +84 : douta <= 7046430 ; +85 : douta <= 7130316 ; +86 : douta <= 7214202 ; +87 : douta <= 7298088 ; +88 : douta <= 7381975 ; +89 : douta <= 7465861 ; +90 : douta <= 7549747 ; +91 : douta <= 7633633 ; +92 : douta <= 7717519 ; +93 : douta <= 7801405 ; +94 : douta <= 7885291 ; +95 : douta <= 7969177 ; +96 : douta <= 8053063 ; +97 : douta <= 8136949 ; +98 : douta <= 8220835 ; +99 : douta <= 8304721 ; +100 : douta <= 8388608 ; +101 : douta <= 8472494 ; +102 : douta <= 8556380 ; +103 : douta <= 8640266 ; +104 : douta <= 8724152 ; +105 : douta <= 8808038 ; +106 : douta <= 8891924 ; +107 : douta <= 8975810 ; +108 : douta <= 9059696 ; +109 : douta <= 9143582 ; +110 : douta <= 9227468 ; +111 : douta <= 9311354 ; +112 : douta <= 9395240 ; +113 : douta <= 9479127 ; +114 : douta <= 9563013 ; +115 : douta <= 9646899 ; +116 : douta <= 9730785 ; +117 : douta <= 9814671 ; +118 : douta <= 9898557 ; +119 : douta <= 9982443 ; +120 : douta <= 10066329 ; +121 : douta <= 10150215 ; +122 : douta <= 10234101 ; +123 : douta <= 10317987 ; +124 : douta <= 10401873 ; +125 : douta <= 10485760 ; +126 : douta <= 10569646 ; +127 : douta <= 10653532 ; +128 : douta <= 10737418 ; +129 : douta <= 10821304 ; +130 : douta <= 10905190 ; +131 : douta <= 10989076 ; +132 : douta <= 11072962 ; +133 : douta <= 11156848 ; +134 : douta <= 11240734 ; +135 : douta <= 11324620 ; +136 : douta <= 11408506 ; +137 : douta <= 11492392 ; +138 : douta <= 11576279 ; +139 : douta <= 11660165 ; +140 : douta <= 11744051 ; +141 : douta <= 11827937 ; +142 : douta <= 11911823 ; +143 : douta <= 11995709 ; +144 : douta <= 12079595 ; +145 : douta <= 12163481 ; +146 : douta <= 12247367 ; +147 : douta <= 12331253 ; +148 : douta <= 12415139 ; +149 : douta <= 12499025 ; +150 : douta <= 12582912 ; +151 : douta <= 12666798 ; +152 : douta <= 12750684 ; +153 : douta <= 12834570 ; +154 : douta <= 12918456 ; +155 : douta <= 13002342 ; +156 : douta <= 13086228 ; +157 : douta <= 13170114 ; +158 : douta <= 13254000 ; +159 : douta <= 13337886 ; +160 : douta <= 13421772 ; +161 : douta <= 13505658 ; +162 : douta <= 13589544 ; +163 : douta <= 13673431 ; +164 : douta <= 13757317 ; +165 : douta <= 13841203 ; +166 : douta <= 13925089 ; +167 : douta <= 14008975 ; +168 : douta <= 14092861 ; +169 : douta <= 14176747 ; +170 : douta <= 14260633 ; +171 : douta <= 14344519 ; +172 : douta <= 14428405 ; +173 : douta <= 14512291 ; +174 : douta <= 14596177 ; +175 : douta <= 14680064 ; +176 : douta <= 14763950 ; +177 : douta <= 14847836 ; +178 : douta <= 14931722 ; +179 : douta <= 15015608 ; +180 : douta <= 15099494 ; +181 : douta <= 15183380 ; +182 : douta <= 15267266 ; +183 : douta <= 15351152 ; +184 : douta <= 15435038 ; +185 : douta <= 15518924 ; +186 : douta <= 15602810 ; +187 : douta <= 15686696 ; +188 : douta <= 15770583 ; +189 : douta <= 15854469 ; +190 : douta <= 15938355 ; +191 : douta <= 16022241 ; +192 : douta <= 16106127 ; +193 : douta <= 16190013 ; +194 : douta <= 16273899 ; +195 : douta <= 16357785 ; +196 : douta <= 16441671 ; +197 : douta <= 16525557 ; +198 : douta <= 16609443 ; +199 : douta <= 16693329 ; +200 : douta <= 16777216 ; +201 : douta <= 16861102 ; +202 : douta <= 16944988 ; +203 : douta <= 17028874 ; +204 : douta <= 17112760 ; +205 : douta <= 17196646 ; +206 : douta <= 17280532 ; +207 : douta <= 17364418 ; +208 : douta <= 17448304 ; +209 : douta <= 17532190 ; +210 : douta <= 17616076 ; +211 : douta <= 17699962 ; +212 : douta <= 17783848 ; +213 : douta <= 17867735 ; +214 : douta <= 17951621 ; +215 : douta <= 18035507 ; +216 : douta <= 18119393 ; +217 : douta <= 18203279 ; +218 : douta <= 18287165 ; +219 : douta <= 18371051 ; +220 : douta <= 18454937 ; +221 : douta <= 18538823 ; +222 : douta <= 18622709 ; +223 : douta <= 18706595 ; +224 : douta <= 18790481 ; +225 : douta <= 18874368 ; +226 : douta <= 18958254 ; +227 : douta <= 19042140 ; +228 : douta <= 19126026 ; +229 : douta <= 19209912 ; +230 : douta <= 19293798 ; +231 : douta <= 19377684 ; +232 : douta <= 19461570 ; +233 : douta <= 19545456 ; +234 : douta <= 19629342 ; +235 : douta <= 19713228 ; +236 : douta <= 19797114 ; +237 : douta <= 19881000 ; +238 : douta <= 19964887 ; +239 : douta <= 20048773 ; +240 : douta <= 20132659 ; +241 : douta <= 20216545 ; +242 : douta <= 20300431 ; +243 : douta <= 20384317 ; +244 : douta <= 20468203 ; +245 : douta <= 20552089 ; +246 : douta <= 20635975 ; +247 : douta <= 20719861 ; +248 : douta <= 20803747 ; +249 : douta <= 20887633 ; +250 : douta <= 20971520 ; +251 : douta <= 21055406 ; +252 : douta <= 21139292 ; +253 : douta <= 21223178 ; +254 : douta <= 21307064 ; +255 : douta <= 21390950 ; +256 : douta <= 21474836 ; +257 : douta <= 21558722 ; +258 : douta <= 21642608 ; +259 : douta <= 21726494 ; +260 : douta <= 21810380 ; +261 : douta <= 21894266 ; +262 : douta <= 21978152 ; +263 : douta <= 22062039 ; +264 : douta <= 22145925 ; +265 : douta <= 22229811 ; +266 : douta <= 22313697 ; +267 : douta <= 22397583 ; +268 : douta <= 22481469 ; +269 : douta <= 22565355 ; +270 : douta <= 22649241 ; +271 : douta <= 22733127 ; +272 : douta <= 22817013 ; +273 : douta <= 22900899 ; +274 : douta <= 22984785 ; +275 : douta <= 23068672 ; +276 : douta <= 23152558 ; +277 : douta <= 23236444 ; +278 : douta <= 23320330 ; +279 : douta <= 23404216 ; +280 : douta <= 23488102 ; +281 : douta <= 23571988 ; +282 : douta <= 23655874 ; +283 : douta <= 23739760 ; +284 : douta <= 23823646 ; +285 : douta <= 23907532 ; +286 : douta <= 23991418 ; +287 : douta <= 24075304 ; +288 : douta <= 24159191 ; +289 : douta <= 24243077 ; +290 : douta <= 24326963 ; +291 : douta <= 24410849 ; +292 : douta <= 24494735 ; +293 : douta <= 24578621 ; +294 : douta <= 24662507 ; +295 : douta <= 24746393 ; +296 : douta <= 24830279 ; +297 : douta <= 24914165 ; +298 : douta <= 24998051 ; +299 : douta <= 25081937 ; +300 : douta <= 25165824 ; +301 : douta <= 25249710 ; +302 : douta <= 25333596 ; +303 : douta <= 25417482 ; +304 : douta <= 25501368 ; +305 : douta <= 25585254 ; +306 : douta <= 25669140 ; +307 : douta <= 25753026 ; +308 : douta <= 25836912 ; +309 : douta <= 25920798 ; +310 : douta <= 26004684 ; +311 : douta <= 26088570 ; +312 : douta <= 26172456 ; +313 : douta <= 26256343 ; +314 : douta <= 26340229 ; +315 : douta <= 26424115 ; +316 : douta <= 26508001 ; +317 : douta <= 26591887 ; +318 : douta <= 26675773 ; +319 : douta <= 26759659 ; +320 : douta <= 26843545 ; +321 : douta <= 26927431 ; +322 : douta <= 27011317 ; +323 : douta <= 27095203 ; +324 : douta <= 27179089 ; +325 : douta <= 27262976 ; +326 : douta <= 27346862 ; +327 : douta <= 27430748 ; +328 : douta <= 27514634 ; +329 : douta <= 27598520 ; +330 : douta <= 27682406 ; +331 : douta <= 27766292 ; +332 : douta <= 27850178 ; +333 : douta <= 27934064 ; +334 : douta <= 28017950 ; +335 : douta <= 28101836 ; +336 : douta <= 28185722 ; +337 : douta <= 28269608 ; +338 : douta <= 28353495 ; +339 : douta <= 28437381 ; +340 : douta <= 28521267 ; +341 : douta <= 28605153 ; +342 : douta <= 28689039 ; +343 : douta <= 28772925 ; +344 : douta <= 28856811 ; +345 : douta <= 28940697 ; +346 : douta <= 29024583 ; +347 : douta <= 29108469 ; +348 : douta <= 29192355 ; +349 : douta <= 29276241 ; +350 : douta <= 29360128 ; +351 : douta <= 29444014 ; +352 : douta <= 29527900 ; +353 : douta <= 29611786 ; +354 : douta <= 29695672 ; +355 : douta <= 29779558 ; +356 : douta <= 29863444 ; +357 : douta <= 29947330 ; +358 : douta <= 30031216 ; +359 : douta <= 30115102 ; +360 : douta <= 30198988 ; +361 : douta <= 30282874 ; +362 : douta <= 30366760 ; +363 : douta <= 30450647 ; +364 : douta <= 30534533 ; +365 : douta <= 30618419 ; +366 : douta <= 30702305 ; +367 : douta <= 30786191 ; +368 : douta <= 30870077 ; +369 : douta <= 30953963 ; +370 : douta <= 31037849 ; +371 : douta <= 31121735 ; +372 : douta <= 31205621 ; +373 : douta <= 31289507 ; +374 : douta <= 31373393 ; +375 : douta <= 31457280 ; +376 : douta <= 31541166 ; +377 : douta <= 31625052 ; +378 : douta <= 31708938 ; +379 : douta <= 31792824 ; +380 : douta <= 31876710 ; +381 : douta <= 31960596 ; +382 : douta <= 32044482 ; +383 : douta <= 32128368 ; +384 : douta <= 32212254 ; +385 : douta <= 32296140 ; +386 : douta <= 32380026 ; +387 : douta <= 32463912 ; +388 : douta <= 32547799 ; +389 : douta <= 32631685 ; +390 : douta <= 32715571 ; +391 : douta <= 32799457 ; +392 : douta <= 32883343 ; +393 : douta <= 32967229 ; +394 : douta <= 33051115 ; +395 : douta <= 33135001 ; +396 : douta <= 33218887 ; +397 : douta <= 33302773 ; +398 : douta <= 33386659 ; +399 : douta <= 33470545 ; + default : douta <= douta ; + endcase +end + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/INT_ROMb.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/INT_ROMb.v new file mode 100644 index 0000000..258aa3f --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/INT_ROMb.v @@ -0,0 +1,3569 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:37:56 01/26/2022 +// Design Name: +// Module Name: INT_ROMb +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module INT_ROMb( +input sysclk, +input [11 : 0] addra, + +output reg[15:0] douta +); + + +always@(posedge sysclk)begin + if(addra>=0 && addra<=24) douta<=50; + else if(addra<=424 ) douta<=51; + else if(addra<=824 ) douta<=52; + else if(addra<=1224 ) douta<=53; + else if(addra<=1624 ) douta<=54; + else if(addra<=2024 ) douta<=55; + else if(addra<=2424 ) douta<=56; + else if(addra<=2824 ) douta<=57; + else if(addra<=3224 ) douta<=58; + else if(addra<=3500 ) douta<=59; + else douta<=douta; +end +/* +always@(posedge sysclk)begin + case(addra) + +0 : douta <= 50 ; +1 : douta <= 50 ; +2 : douta <= 50 ; +3 : douta <= 50 ; +4 : douta <= 50 ; +5 : douta <= 50 ; +6 : douta <= 50 ; +7 : douta <= 50 ; +8 : douta <= 50 ; +9 : douta <= 50 ; +10 : douta <= 50 ; +11 : douta <= 50 ; +12 : douta <= 50 ; +13 : douta <= 50 ; +14 : douta <= 50 ; +15 : douta <= 50 ; +16 : douta <= 50 ; +17 : douta <= 50 ; +18 : douta <= 50 ; +19 : douta <= 50 ; +20 : douta <= 50 ; +21 : douta <= 50 ; +22 : douta <= 50 ; +23 : douta <= 50 ; +24 : douta <= 50 ; +25 : douta <= 51 ; +26 : douta <= 51 ; +27 : douta <= 51 ; +28 : douta <= 51 ; +29 : douta <= 51 ; +30 : douta <= 51 ; +31 : douta <= 51 ; +32 : douta <= 51 ; +33 : douta <= 51 ; +34 : douta <= 51 ; +35 : douta <= 51 ; +36 : douta <= 51 ; +37 : douta <= 51 ; +38 : douta <= 51 ; +39 : douta <= 51 ; +40 : douta <= 51 ; +41 : douta <= 51 ; +42 : douta <= 51 ; +43 : douta <= 51 ; +44 : douta <= 51 ; +45 : douta <= 51 ; +46 : douta <= 51 ; +47 : douta <= 51 ; +48 : douta <= 51 ; +49 : douta <= 51 ; +50 : douta <= 51 ; +51 : douta <= 51 ; +52 : douta <= 51 ; +53 : douta <= 51 ; +54 : douta <= 51 ; +55 : douta <= 51 ; +56 : douta <= 51 ; +57 : douta <= 51 ; +58 : douta <= 51 ; +59 : douta <= 51 ; +60 : douta <= 51 ; +61 : douta <= 51 ; +62 : douta <= 51 ; +63 : douta <= 51 ; +64 : douta <= 51 ; +65 : douta <= 51 ; +66 : douta <= 51 ; +67 : douta <= 51 ; +68 : douta <= 51 ; +69 : douta <= 51 ; +70 : douta <= 51 ; +71 : douta <= 51 ; +72 : douta <= 51 ; +73 : douta <= 51 ; +74 : douta <= 51 ; +75 : douta <= 51 ; +76 : douta <= 51 ; +77 : douta <= 51 ; +78 : douta <= 51 ; +79 : douta <= 51 ; +80 : douta <= 51 ; +81 : douta <= 51 ; +82 : douta <= 51 ; +83 : douta <= 51 ; +84 : douta <= 51 ; +85 : douta <= 51 ; +86 : douta <= 51 ; +87 : douta <= 51 ; +88 : douta <= 51 ; +89 : douta <= 51 ; +90 : douta <= 51 ; +91 : douta <= 51 ; +92 : douta <= 51 ; +93 : douta <= 51 ; +94 : douta <= 51 ; +95 : douta <= 51 ; +96 : douta <= 51 ; +97 : douta <= 51 ; +98 : douta <= 51 ; +99 : douta <= 51 ; +100 : douta <= 51 ; +101 : douta <= 51 ; +102 : douta <= 51 ; +103 : douta <= 51 ; +104 : douta <= 51 ; +105 : douta <= 51 ; +106 : douta <= 51 ; +107 : douta <= 51 ; +108 : douta <= 51 ; +109 : douta <= 51 ; +110 : douta <= 51 ; +111 : douta <= 51 ; +112 : douta <= 51 ; +113 : douta <= 51 ; +114 : douta <= 51 ; +115 : douta <= 51 ; +116 : douta <= 51 ; +117 : douta <= 51 ; +118 : douta <= 51 ; +119 : douta <= 51 ; +120 : douta <= 51 ; +121 : douta <= 51 ; +122 : douta <= 51 ; +123 : douta <= 51 ; +124 : douta <= 51 ; +125 : douta <= 51 ; +126 : douta <= 51 ; +127 : douta <= 51 ; +128 : douta <= 51 ; +129 : douta <= 51 ; +130 : douta <= 51 ; +131 : douta <= 51 ; +132 : douta <= 51 ; +133 : douta <= 51 ; +134 : douta <= 51 ; +135 : douta <= 51 ; +136 : douta <= 51 ; +137 : douta <= 51 ; +138 : douta <= 51 ; +139 : douta <= 51 ; +140 : douta <= 51 ; +141 : douta <= 51 ; +142 : douta <= 51 ; +143 : douta <= 51 ; +144 : douta <= 51 ; +145 : douta <= 51 ; +146 : douta <= 51 ; +147 : douta <= 51 ; +148 : douta <= 51 ; +149 : douta <= 51 ; +150 : douta <= 51 ; +151 : douta <= 51 ; +152 : douta <= 51 ; +153 : douta <= 51 ; +154 : douta <= 51 ; +155 : douta <= 51 ; +156 : douta <= 51 ; +157 : douta <= 51 ; +158 : douta <= 51 ; +159 : douta <= 51 ; +160 : douta <= 51 ; +161 : douta <= 51 ; +162 : douta <= 51 ; +163 : douta <= 51 ; +164 : douta <= 51 ; +165 : douta <= 51 ; +166 : douta <= 51 ; +167 : douta <= 51 ; +168 : douta <= 51 ; +169 : douta <= 51 ; +170 : douta <= 51 ; +171 : douta <= 51 ; +172 : douta <= 51 ; +173 : douta <= 51 ; +174 : douta <= 51 ; +175 : douta <= 51 ; +176 : douta <= 51 ; +177 : douta <= 51 ; +178 : douta <= 51 ; +179 : douta <= 51 ; +180 : douta <= 51 ; +181 : douta <= 51 ; +182 : douta <= 51 ; +183 : douta <= 51 ; +184 : douta <= 51 ; +185 : douta <= 51 ; +186 : douta <= 51 ; +187 : douta <= 51 ; +188 : douta <= 51 ; +189 : douta <= 51 ; +190 : douta <= 51 ; +191 : douta <= 51 ; +192 : douta <= 51 ; +193 : douta <= 51 ; +194 : douta <= 51 ; +195 : douta <= 51 ; +196 : douta <= 51 ; +197 : douta <= 51 ; +198 : douta <= 51 ; +199 : douta <= 51 ; +200 : douta <= 51 ; +201 : douta <= 51 ; +202 : douta <= 51 ; +203 : douta <= 51 ; +204 : douta <= 51 ; +205 : douta <= 51 ; +206 : douta <= 51 ; +207 : douta <= 51 ; +208 : douta <= 51 ; +209 : douta <= 51 ; +210 : douta <= 51 ; +211 : douta <= 51 ; +212 : douta <= 51 ; +213 : douta <= 51 ; +214 : douta <= 51 ; +215 : douta <= 51 ; +216 : douta <= 51 ; +217 : douta <= 51 ; +218 : douta <= 51 ; +219 : douta <= 51 ; +220 : douta <= 51 ; +221 : douta <= 51 ; +222 : douta <= 51 ; +223 : douta <= 51 ; +224 : douta <= 51 ; +225 : douta <= 51 ; +226 : douta <= 51 ; +227 : douta <= 51 ; +228 : douta <= 51 ; +229 : douta <= 51 ; +230 : douta <= 51 ; +231 : douta <= 51 ; +232 : douta <= 51 ; +233 : douta <= 51 ; +234 : douta <= 51 ; +235 : douta <= 51 ; +236 : douta <= 51 ; +237 : douta <= 51 ; +238 : douta <= 51 ; +239 : douta <= 51 ; +240 : douta <= 51 ; +241 : douta <= 51 ; +242 : douta <= 51 ; +243 : douta <= 51 ; +244 : douta <= 51 ; +245 : douta <= 51 ; +246 : douta <= 51 ; +247 : douta <= 51 ; +248 : douta <= 51 ; +249 : douta <= 51 ; +250 : douta <= 51 ; +251 : douta <= 51 ; +252 : douta <= 51 ; +253 : douta <= 51 ; +254 : douta <= 51 ; +255 : douta <= 51 ; +256 : douta <= 51 ; +257 : douta <= 51 ; +258 : douta <= 51 ; +259 : douta <= 51 ; +260 : douta <= 51 ; +261 : douta <= 51 ; +262 : douta <= 51 ; +263 : douta <= 51 ; +264 : douta <= 51 ; +265 : douta <= 51 ; +266 : douta <= 51 ; +267 : douta <= 51 ; +268 : douta <= 51 ; +269 : douta <= 51 ; +270 : douta <= 51 ; +271 : douta <= 51 ; +272 : douta <= 51 ; +273 : douta <= 51 ; +274 : douta <= 51 ; +275 : douta <= 51 ; +276 : douta <= 51 ; +277 : douta <= 51 ; +278 : douta <= 51 ; +279 : douta <= 51 ; +280 : douta <= 51 ; +281 : douta <= 51 ; +282 : douta <= 51 ; +283 : douta <= 51 ; +284 : douta <= 51 ; +285 : douta <= 51 ; +286 : douta <= 51 ; +287 : douta <= 51 ; +288 : douta <= 51 ; +289 : douta <= 51 ; +290 : douta <= 51 ; +291 : douta <= 51 ; +292 : douta <= 51 ; +293 : douta <= 51 ; +294 : douta <= 51 ; +295 : douta <= 51 ; +296 : douta <= 51 ; +297 : douta <= 51 ; +298 : douta <= 51 ; +299 : douta <= 51 ; +300 : douta <= 51 ; +301 : douta <= 51 ; +302 : douta <= 51 ; +303 : douta <= 51 ; +304 : douta <= 51 ; +305 : douta <= 51 ; +306 : douta <= 51 ; +307 : douta <= 51 ; +308 : douta <= 51 ; +309 : douta <= 51 ; +310 : douta <= 51 ; +311 : douta <= 51 ; +312 : douta <= 51 ; +313 : douta <= 51 ; +314 : douta <= 51 ; +315 : douta <= 51 ; +316 : douta <= 51 ; +317 : douta <= 51 ; +318 : douta <= 51 ; +319 : douta <= 51 ; +320 : douta <= 51 ; +321 : douta <= 51 ; +322 : douta <= 51 ; +323 : douta <= 51 ; +324 : douta <= 51 ; +325 : douta <= 51 ; +326 : douta <= 51 ; +327 : douta <= 51 ; +328 : douta <= 51 ; +329 : douta <= 51 ; +330 : douta <= 51 ; +331 : douta <= 51 ; +332 : douta <= 51 ; +333 : douta <= 51 ; +334 : douta <= 51 ; +335 : douta <= 51 ; +336 : douta <= 51 ; +337 : douta <= 51 ; +338 : douta <= 51 ; +339 : douta <= 51 ; +340 : douta <= 51 ; +341 : douta <= 51 ; +342 : douta <= 51 ; +343 : douta <= 51 ; +344 : douta <= 51 ; +345 : douta <= 51 ; +346 : douta <= 51 ; +347 : douta <= 51 ; +348 : douta <= 51 ; +349 : douta <= 51 ; +350 : douta <= 51 ; +351 : douta <= 51 ; +352 : douta <= 51 ; +353 : douta <= 51 ; +354 : douta <= 51 ; +355 : douta <= 51 ; +356 : douta <= 51 ; +357 : douta <= 51 ; +358 : douta <= 51 ; +359 : douta <= 51 ; +360 : douta <= 51 ; +361 : douta <= 51 ; +362 : douta <= 51 ; +363 : douta <= 51 ; +364 : douta <= 51 ; +365 : douta <= 51 ; +366 : douta <= 51 ; +367 : douta <= 51 ; +368 : douta <= 51 ; +369 : douta <= 51 ; +370 : douta <= 51 ; +371 : douta <= 51 ; +372 : douta <= 51 ; +373 : douta <= 51 ; +374 : douta <= 51 ; +375 : douta <= 51 ; +376 : douta <= 51 ; +377 : douta <= 51 ; +378 : douta <= 51 ; +379 : douta <= 51 ; +380 : douta <= 51 ; +381 : douta <= 51 ; +382 : douta <= 51 ; +383 : douta <= 51 ; +384 : douta <= 51 ; +385 : douta <= 51 ; +386 : douta <= 51 ; +387 : douta <= 51 ; +388 : douta <= 51 ; +389 : douta <= 51 ; +390 : douta <= 51 ; +391 : douta <= 51 ; +392 : douta <= 51 ; +393 : douta <= 51 ; +394 : douta <= 51 ; +395 : douta <= 51 ; +396 : douta <= 51 ; +397 : douta <= 51 ; +398 : douta <= 51 ; +399 : douta <= 51 ; +400 : douta <= 51 ; +401 : douta <= 51 ; +402 : douta <= 51 ; +403 : douta <= 51 ; +404 : douta <= 51 ; +405 : douta <= 51 ; +406 : douta <= 51 ; +407 : douta <= 51 ; +408 : douta <= 51 ; +409 : douta <= 51 ; +410 : douta <= 51 ; +411 : douta <= 51 ; +412 : douta <= 51 ; +413 : douta <= 51 ; +414 : douta <= 51 ; +415 : douta <= 51 ; +416 : douta <= 51 ; +417 : douta <= 51 ; +418 : douta <= 51 ; +419 : douta <= 51 ; +420 : douta <= 51 ; +421 : douta <= 51 ; +422 : douta <= 51 ; +423 : douta <= 51 ; +424 : douta <= 51 ; +425 : douta <= 52 ; +426 : douta <= 52 ; +427 : douta <= 52 ; +428 : douta <= 52 ; +429 : douta <= 52 ; +430 : douta <= 52 ; +431 : douta <= 52 ; +432 : douta <= 52 ; +433 : douta <= 52 ; +434 : douta <= 52 ; +435 : douta <= 52 ; +436 : douta <= 52 ; +437 : douta <= 52 ; +438 : douta <= 52 ; +439 : douta <= 52 ; +440 : douta <= 52 ; +441 : douta <= 52 ; +442 : douta <= 52 ; +443 : douta <= 52 ; +444 : douta <= 52 ; +445 : douta <= 52 ; +446 : douta <= 52 ; +447 : douta <= 52 ; +448 : douta <= 52 ; +449 : douta <= 52 ; +450 : douta <= 52 ; +451 : douta <= 52 ; +452 : douta <= 52 ; +453 : douta <= 52 ; +454 : douta <= 52 ; +455 : douta <= 52 ; +456 : douta <= 52 ; +457 : douta <= 52 ; +458 : douta <= 52 ; +459 : douta <= 52 ; +460 : douta <= 52 ; +461 : douta <= 52 ; +462 : douta <= 52 ; +463 : douta <= 52 ; +464 : douta <= 52 ; +465 : douta <= 52 ; +466 : douta <= 52 ; +467 : douta <= 52 ; +468 : douta <= 52 ; +469 : douta <= 52 ; +470 : douta <= 52 ; +471 : douta <= 52 ; +472 : douta <= 52 ; +473 : douta <= 52 ; +474 : douta <= 52 ; +475 : douta <= 52 ; +476 : douta <= 52 ; +477 : douta <= 52 ; +478 : douta <= 52 ; +479 : douta <= 52 ; +480 : douta <= 52 ; +481 : douta <= 52 ; +482 : douta <= 52 ; +483 : douta <= 52 ; +484 : douta <= 52 ; +485 : douta <= 52 ; +486 : douta <= 52 ; +487 : douta <= 52 ; +488 : douta <= 52 ; +489 : douta <= 52 ; +490 : douta <= 52 ; +491 : douta <= 52 ; +492 : douta <= 52 ; +493 : douta <= 52 ; +494 : douta <= 52 ; +495 : douta <= 52 ; +496 : douta <= 52 ; +497 : douta <= 52 ; +498 : douta <= 52 ; +499 : douta <= 52 ; +500 : douta <= 52 ; +501 : douta <= 52 ; +502 : douta <= 52 ; +503 : douta <= 52 ; +504 : douta <= 52 ; +505 : douta <= 52 ; +506 : douta <= 52 ; +507 : douta <= 52 ; +508 : douta <= 52 ; +509 : douta <= 52 ; +510 : douta <= 52 ; +511 : douta <= 52 ; +512 : douta <= 52 ; +513 : douta <= 52 ; +514 : douta <= 52 ; +515 : douta <= 52 ; +516 : douta <= 52 ; +517 : douta <= 52 ; +518 : douta <= 52 ; +519 : douta <= 52 ; +520 : douta <= 52 ; +521 : douta <= 52 ; +522 : douta <= 52 ; +523 : douta <= 52 ; +524 : douta <= 52 ; +525 : douta <= 52 ; +526 : douta <= 52 ; +527 : douta <= 52 ; +528 : douta <= 52 ; +529 : douta <= 52 ; +530 : douta <= 52 ; +531 : douta <= 52 ; +532 : douta <= 52 ; +533 : douta <= 52 ; +534 : douta <= 52 ; +535 : douta <= 52 ; +536 : douta <= 52 ; +537 : douta <= 52 ; +538 : douta <= 52 ; +539 : douta <= 52 ; +540 : douta <= 52 ; +541 : douta <= 52 ; +542 : douta <= 52 ; +543 : douta <= 52 ; +544 : douta <= 52 ; +545 : douta <= 52 ; +546 : douta <= 52 ; +547 : douta <= 52 ; +548 : douta <= 52 ; +549 : douta <= 52 ; +550 : douta <= 52 ; +551 : douta <= 52 ; +552 : douta <= 52 ; +553 : douta <= 52 ; +554 : douta <= 52 ; +555 : douta <= 52 ; +556 : douta <= 52 ; +557 : douta <= 52 ; +558 : douta <= 52 ; +559 : douta <= 52 ; +560 : douta <= 52 ; +561 : douta <= 52 ; +562 : douta <= 52 ; +563 : douta <= 52 ; +564 : douta <= 52 ; +565 : douta <= 52 ; +566 : douta <= 52 ; +567 : douta <= 52 ; +568 : douta <= 52 ; +569 : douta <= 52 ; +570 : douta <= 52 ; +571 : douta <= 52 ; +572 : douta <= 52 ; +573 : douta <= 52 ; +574 : douta <= 52 ; +575 : douta <= 52 ; +576 : douta <= 52 ; +577 : douta <= 52 ; +578 : douta <= 52 ; +579 : douta <= 52 ; +580 : douta <= 52 ; +581 : douta <= 52 ; +582 : douta <= 52 ; +583 : douta <= 52 ; +584 : douta <= 52 ; +585 : douta <= 52 ; +586 : douta <= 52 ; +587 : douta <= 52 ; +588 : douta <= 52 ; +589 : douta <= 52 ; +590 : douta <= 52 ; +591 : douta <= 52 ; +592 : douta <= 52 ; +593 : douta <= 52 ; +594 : douta <= 52 ; +595 : douta <= 52 ; +596 : douta <= 52 ; +597 : douta <= 52 ; +598 : douta <= 52 ; +599 : douta <= 52 ; +600 : douta <= 52 ; +601 : douta <= 52 ; +602 : douta <= 52 ; +603 : douta <= 52 ; +604 : douta <= 52 ; +605 : douta <= 52 ; +606 : douta <= 52 ; +607 : douta <= 52 ; +608 : douta <= 52 ; +609 : douta <= 52 ; +610 : douta <= 52 ; +611 : douta <= 52 ; +612 : douta <= 52 ; +613 : douta <= 52 ; +614 : douta <= 52 ; +615 : douta <= 52 ; +616 : douta <= 52 ; +617 : douta <= 52 ; +618 : douta <= 52 ; +619 : douta <= 52 ; +620 : douta <= 52 ; +621 : douta <= 52 ; +622 : douta <= 52 ; +623 : douta <= 52 ; +624 : douta <= 52 ; +625 : douta <= 52 ; +626 : douta <= 52 ; +627 : douta <= 52 ; +628 : douta <= 52 ; +629 : douta <= 52 ; +630 : douta <= 52 ; +631 : douta <= 52 ; +632 : douta <= 52 ; +633 : douta <= 52 ; +634 : douta <= 52 ; +635 : douta <= 52 ; +636 : douta <= 52 ; +637 : douta <= 52 ; +638 : douta <= 52 ; +639 : douta <= 52 ; +640 : douta <= 52 ; +641 : douta <= 52 ; +642 : douta <= 52 ; +643 : douta <= 52 ; +644 : douta <= 52 ; +645 : douta <= 52 ; +646 : douta <= 52 ; +647 : douta <= 52 ; +648 : douta <= 52 ; +649 : douta <= 52 ; +650 : douta <= 52 ; +651 : douta <= 52 ; +652 : douta <= 52 ; +653 : douta <= 52 ; +654 : douta <= 52 ; +655 : douta <= 52 ; +656 : douta <= 52 ; +657 : douta <= 52 ; +658 : douta <= 52 ; +659 : douta <= 52 ; +660 : douta <= 52 ; +661 : douta <= 52 ; +662 : douta <= 52 ; +663 : douta <= 52 ; +664 : douta <= 52 ; +665 : douta <= 52 ; +666 : douta <= 52 ; +667 : douta <= 52 ; +668 : douta <= 52 ; +669 : douta <= 52 ; +670 : douta <= 52 ; +671 : douta <= 52 ; +672 : douta <= 52 ; +673 : douta <= 52 ; +674 : douta <= 52 ; +675 : douta <= 52 ; +676 : douta <= 52 ; +677 : douta <= 52 ; +678 : douta <= 52 ; +679 : douta <= 52 ; +680 : douta <= 52 ; +681 : douta <= 52 ; +682 : douta <= 52 ; +683 : douta <= 52 ; +684 : douta <= 52 ; +685 : douta <= 52 ; +686 : douta <= 52 ; +687 : douta <= 52 ; +688 : douta <= 52 ; +689 : douta <= 52 ; +690 : douta <= 52 ; +691 : douta <= 52 ; +692 : douta <= 52 ; +693 : douta <= 52 ; +694 : douta <= 52 ; +695 : douta <= 52 ; +696 : douta <= 52 ; +697 : douta <= 52 ; +698 : douta <= 52 ; +699 : douta <= 52 ; +700 : douta <= 52 ; +701 : douta <= 52 ; +702 : douta <= 52 ; +703 : douta <= 52 ; +704 : douta <= 52 ; +705 : douta <= 52 ; +706 : douta <= 52 ; +707 : douta <= 52 ; +708 : douta <= 52 ; +709 : douta <= 52 ; +710 : douta <= 52 ; +711 : douta <= 52 ; +712 : douta <= 52 ; +713 : douta <= 52 ; +714 : douta <= 52 ; +715 : douta <= 52 ; +716 : douta <= 52 ; +717 : douta <= 52 ; +718 : douta <= 52 ; +719 : douta <= 52 ; +720 : douta <= 52 ; +721 : douta <= 52 ; +722 : douta <= 52 ; +723 : douta <= 52 ; +724 : douta <= 52 ; +725 : douta <= 52 ; +726 : douta <= 52 ; +727 : douta <= 52 ; +728 : douta <= 52 ; +729 : douta <= 52 ; +730 : douta <= 52 ; +731 : douta <= 52 ; +732 : douta <= 52 ; +733 : douta <= 52 ; +734 : douta <= 52 ; +735 : douta <= 52 ; +736 : douta <= 52 ; +737 : douta <= 52 ; +738 : douta <= 52 ; +739 : douta <= 52 ; +740 : douta <= 52 ; +741 : douta <= 52 ; +742 : douta <= 52 ; +743 : douta <= 52 ; +744 : douta <= 52 ; +745 : douta <= 52 ; +746 : douta <= 52 ; +747 : douta <= 52 ; +748 : douta <= 52 ; +749 : douta <= 52 ; +750 : douta <= 52 ; +751 : douta <= 52 ; +752 : douta <= 52 ; +753 : douta <= 52 ; +754 : douta <= 52 ; +755 : douta <= 52 ; +756 : douta <= 52 ; +757 : douta <= 52 ; +758 : douta <= 52 ; +759 : douta <= 52 ; +760 : douta <= 52 ; +761 : douta <= 52 ; +762 : douta <= 52 ; +763 : douta <= 52 ; +764 : douta <= 52 ; +765 : douta <= 52 ; +766 : douta <= 52 ; +767 : douta <= 52 ; +768 : douta <= 52 ; +769 : douta <= 52 ; +770 : douta <= 52 ; +771 : douta <= 52 ; +772 : douta <= 52 ; +773 : douta <= 52 ; +774 : douta <= 52 ; +775 : douta <= 52 ; +776 : douta <= 52 ; +777 : douta <= 52 ; +778 : douta <= 52 ; +779 : douta <= 52 ; +780 : douta <= 52 ; +781 : douta <= 52 ; +782 : douta <= 52 ; +783 : douta <= 52 ; +784 : douta <= 52 ; +785 : douta <= 52 ; +786 : douta <= 52 ; +787 : douta <= 52 ; +788 : douta <= 52 ; +789 : douta <= 52 ; +790 : douta <= 52 ; +791 : douta <= 52 ; +792 : douta <= 52 ; +793 : douta <= 52 ; +794 : douta <= 52 ; +795 : douta <= 52 ; +796 : douta <= 52 ; +797 : douta <= 52 ; +798 : douta <= 52 ; +799 : douta <= 52 ; +800 : douta <= 52 ; +801 : douta <= 52 ; +802 : douta <= 52 ; +803 : douta <= 52 ; +804 : douta <= 52 ; +805 : douta <= 52 ; +806 : douta <= 52 ; +807 : douta <= 52 ; +808 : douta <= 52 ; +809 : douta <= 52 ; +810 : douta <= 52 ; +811 : douta <= 52 ; +812 : douta <= 52 ; +813 : douta <= 52 ; +814 : douta <= 52 ; +815 : douta <= 52 ; +816 : douta <= 52 ; +817 : douta <= 52 ; +818 : douta <= 52 ; +819 : douta <= 52 ; +820 : douta <= 52 ; +821 : douta <= 52 ; +822 : douta <= 52 ; +823 : douta <= 52 ; +824 : douta <= 52 ; +825 : douta <= 53 ; +826 : douta <= 53 ; +827 : douta <= 53 ; +828 : douta <= 53 ; +829 : douta <= 53 ; +830 : douta <= 53 ; +831 : douta <= 53 ; +832 : douta <= 53 ; +833 : douta <= 53 ; +834 : douta <= 53 ; +835 : douta <= 53 ; +836 : douta <= 53 ; +837 : douta <= 53 ; +838 : douta <= 53 ; +839 : douta <= 53 ; +840 : douta <= 53 ; +841 : douta <= 53 ; +842 : douta <= 53 ; +843 : douta <= 53 ; +844 : douta <= 53 ; +845 : douta <= 53 ; +846 : douta <= 53 ; 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+2923 : douta <= 58 ; +2924 : douta <= 58 ; +2925 : douta <= 58 ; +2926 : douta <= 58 ; +2927 : douta <= 58 ; +2928 : douta <= 58 ; +2929 : douta <= 58 ; +2930 : douta <= 58 ; +2931 : douta <= 58 ; +2932 : douta <= 58 ; +2933 : douta <= 58 ; +2934 : douta <= 58 ; +2935 : douta <= 58 ; +2936 : douta <= 58 ; +2937 : douta <= 58 ; +2938 : douta <= 58 ; +2939 : douta <= 58 ; +2940 : douta <= 58 ; +2941 : douta <= 58 ; +2942 : douta <= 58 ; +2943 : douta <= 58 ; +2944 : douta <= 58 ; +2945 : douta <= 58 ; +2946 : douta <= 58 ; +2947 : douta <= 58 ; +2948 : douta <= 58 ; +2949 : douta <= 58 ; +2950 : douta <= 58 ; +2951 : douta <= 58 ; +2952 : douta <= 58 ; +2953 : douta <= 58 ; +2954 : douta <= 58 ; +2955 : douta <= 58 ; +2956 : douta <= 58 ; +2957 : douta <= 58 ; +2958 : douta <= 58 ; +2959 : douta <= 58 ; +2960 : douta <= 58 ; +2961 : douta <= 58 ; +2962 : douta <= 58 ; +2963 : douta <= 58 ; +2964 : douta <= 58 ; +2965 : douta <= 58 ; +2966 : douta <= 58 ; +2967 : douta <= 58 ; +2968 : douta <= 58 ; +2969 : douta <= 58 ; +2970 : douta <= 58 ; +2971 : douta <= 58 ; +2972 : douta <= 58 ; +2973 : douta <= 58 ; +2974 : douta <= 58 ; +2975 : douta <= 58 ; +2976 : douta <= 58 ; +2977 : douta <= 58 ; +2978 : douta <= 58 ; +2979 : douta <= 58 ; +2980 : douta <= 58 ; +2981 : douta <= 58 ; +2982 : douta <= 58 ; +2983 : douta <= 58 ; +2984 : douta <= 58 ; +2985 : douta <= 58 ; +2986 : douta <= 58 ; +2987 : douta <= 58 ; +2988 : douta <= 58 ; +2989 : douta <= 58 ; +2990 : douta <= 58 ; +2991 : douta <= 58 ; +2992 : douta <= 58 ; +2993 : douta <= 58 ; +2994 : douta <= 58 ; +2995 : douta <= 58 ; +2996 : douta <= 58 ; +2997 : douta <= 58 ; +2998 : douta <= 58 ; +2999 : douta <= 58 ; +3000 : douta <= 58 ; +3001 : douta <= 58 ; +3002 : douta <= 58 ; +3003 : douta <= 58 ; +3004 : douta <= 58 ; +3005 : douta <= 58 ; +3006 : douta <= 58 ; +3007 : douta <= 58 ; +3008 : douta <= 58 ; +3009 : douta <= 58 ; +3010 : douta <= 58 ; +3011 : douta <= 58 ; +3012 : douta <= 58 ; +3013 : douta <= 58 ; +3014 : douta <= 58 ; +3015 : douta <= 58 ; +3016 : douta <= 58 ; +3017 : douta <= 58 ; +3018 : douta <= 58 ; +3019 : douta <= 58 ; +3020 : douta <= 58 ; +3021 : douta <= 58 ; +3022 : douta <= 58 ; +3023 : douta <= 58 ; +3024 : douta <= 58 ; +3025 : douta <= 58 ; +3026 : douta <= 58 ; +3027 : douta <= 58 ; +3028 : douta <= 58 ; +3029 : douta <= 58 ; +3030 : douta <= 58 ; +3031 : douta <= 58 ; +3032 : douta <= 58 ; +3033 : douta <= 58 ; +3034 : douta <= 58 ; +3035 : douta <= 58 ; +3036 : douta <= 58 ; +3037 : douta <= 58 ; +3038 : douta <= 58 ; +3039 : douta <= 58 ; +3040 : douta <= 58 ; +3041 : douta <= 58 ; +3042 : douta <= 58 ; +3043 : douta <= 58 ; +3044 : douta <= 58 ; +3045 : douta <= 58 ; +3046 : douta <= 58 ; +3047 : douta <= 58 ; +3048 : douta <= 58 ; +3049 : douta <= 58 ; +3050 : douta <= 58 ; +3051 : douta <= 58 ; +3052 : douta <= 58 ; +3053 : douta <= 58 ; +3054 : douta <= 58 ; +3055 : douta <= 58 ; +3056 : douta <= 58 ; +3057 : douta <= 58 ; +3058 : douta <= 58 ; +3059 : douta <= 58 ; +3060 : douta <= 58 ; +3061 : douta <= 58 ; +3062 : douta <= 58 ; +3063 : douta <= 58 ; +3064 : douta <= 58 ; +3065 : douta <= 58 ; +3066 : douta <= 58 ; +3067 : douta <= 58 ; +3068 : douta <= 58 ; +3069 : douta <= 58 ; +3070 : douta <= 58 ; +3071 : douta <= 58 ; +3072 : douta <= 58 ; +3073 : douta <= 58 ; +3074 : douta <= 58 ; +3075 : douta <= 58 ; +3076 : douta <= 58 ; +3077 : douta <= 58 ; +3078 : douta <= 58 ; +3079 : douta <= 58 ; +3080 : douta <= 58 ; +3081 : douta <= 58 ; +3082 : douta <= 58 ; +3083 : douta <= 58 ; +3084 : douta <= 58 ; +3085 : douta <= 58 ; +3086 : douta <= 58 ; +3087 : douta <= 58 ; +3088 : douta <= 58 ; +3089 : douta <= 58 ; +3090 : douta <= 58 ; +3091 : douta <= 58 ; +3092 : douta <= 58 ; +3093 : douta <= 58 ; +3094 : douta <= 58 ; +3095 : douta <= 58 ; +3096 : douta <= 58 ; +3097 : douta <= 58 ; +3098 : douta <= 58 ; +3099 : douta <= 58 ; +3100 : douta <= 58 ; +3101 : douta <= 58 ; +3102 : douta <= 58 ; +3103 : douta <= 58 ; +3104 : douta <= 58 ; +3105 : douta <= 58 ; +3106 : douta <= 58 ; +3107 : douta <= 58 ; +3108 : douta <= 58 ; +3109 : douta <= 58 ; +3110 : douta <= 58 ; +3111 : douta <= 58 ; +3112 : douta <= 58 ; +3113 : douta <= 58 ; +3114 : douta <= 58 ; +3115 : douta <= 58 ; +3116 : douta <= 58 ; +3117 : douta <= 58 ; +3118 : douta <= 58 ; +3119 : douta <= 58 ; +3120 : douta <= 58 ; +3121 : douta <= 58 ; +3122 : douta <= 58 ; +3123 : douta <= 58 ; +3124 : douta <= 58 ; +3125 : douta <= 58 ; +3126 : douta <= 58 ; +3127 : douta <= 58 ; +3128 : douta <= 58 ; +3129 : douta <= 58 ; +3130 : douta <= 58 ; +3131 : douta <= 58 ; +3132 : douta <= 58 ; +3133 : douta <= 58 ; +3134 : douta <= 58 ; +3135 : douta <= 58 ; +3136 : douta <= 58 ; +3137 : douta <= 58 ; +3138 : douta <= 58 ; +3139 : douta <= 58 ; +3140 : douta <= 58 ; +3141 : douta <= 58 ; +3142 : douta <= 58 ; +3143 : douta <= 58 ; +3144 : douta <= 58 ; +3145 : douta <= 58 ; +3146 : douta <= 58 ; +3147 : douta <= 58 ; +3148 : douta <= 58 ; +3149 : douta <= 58 ; +3150 : douta <= 58 ; +3151 : douta <= 58 ; +3152 : douta <= 58 ; +3153 : douta <= 58 ; +3154 : douta <= 58 ; +3155 : douta <= 58 ; +3156 : douta <= 58 ; +3157 : douta <= 58 ; +3158 : douta <= 58 ; +3159 : douta <= 58 ; +3160 : douta <= 58 ; +3161 : douta <= 58 ; +3162 : douta <= 58 ; +3163 : douta <= 58 ; +3164 : douta <= 58 ; +3165 : douta <= 58 ; +3166 : douta <= 58 ; +3167 : douta <= 58 ; +3168 : douta <= 58 ; +3169 : douta <= 58 ; +3170 : douta <= 58 ; +3171 : douta <= 58 ; +3172 : douta <= 58 ; +3173 : douta <= 58 ; +3174 : douta <= 58 ; +3175 : douta <= 58 ; +3176 : douta <= 58 ; +3177 : douta <= 58 ; +3178 : douta <= 58 ; +3179 : douta <= 58 ; +3180 : douta <= 58 ; +3181 : douta <= 58 ; +3182 : douta <= 58 ; +3183 : douta <= 58 ; +3184 : douta <= 58 ; +3185 : douta <= 58 ; +3186 : douta <= 58 ; +3187 : douta <= 58 ; +3188 : douta <= 58 ; +3189 : douta <= 58 ; +3190 : douta <= 58 ; +3191 : douta <= 58 ; +3192 : douta <= 58 ; +3193 : douta <= 58 ; +3194 : douta <= 58 ; +3195 : douta <= 58 ; +3196 : douta <= 58 ; +3197 : douta <= 58 ; +3198 : douta <= 58 ; +3199 : douta <= 58 ; +3200 : douta <= 58 ; +3201 : douta <= 58 ; +3202 : douta <= 58 ; +3203 : douta <= 58 ; +3204 : douta <= 58 ; +3205 : douta <= 58 ; +3206 : douta <= 58 ; +3207 : douta <= 58 ; +3208 : douta <= 58 ; +3209 : douta <= 58 ; +3210 : douta <= 58 ; +3211 : douta <= 58 ; +3212 : douta <= 58 ; +3213 : douta <= 58 ; +3214 : douta <= 58 ; +3215 : douta <= 58 ; +3216 : douta <= 58 ; +3217 : douta <= 58 ; +3218 : douta <= 58 ; +3219 : douta <= 58 ; +3220 : douta <= 58 ; +3221 : douta <= 58 ; +3222 : douta <= 58 ; +3223 : douta <= 58 ; +3224 : douta <= 58 ; +3225 : douta <= 59 ; +3226 : douta <= 59 ; +3227 : douta <= 59 ; +3228 : douta <= 59 ; +3229 : douta <= 59 ; +3230 : douta <= 59 ; +3231 : douta <= 59 ; +3232 : douta <= 59 ; +3233 : douta <= 59 ; +3234 : douta <= 59 ; +3235 : douta <= 59 ; +3236 : douta <= 59 ; +3237 : douta <= 59 ; +3238 : douta <= 59 ; +3239 : douta <= 59 ; +3240 : douta <= 59 ; +3241 : douta <= 59 ; +3242 : douta <= 59 ; +3243 : douta <= 59 ; +3244 : douta <= 59 ; +3245 : douta <= 59 ; +3246 : douta <= 59 ; +3247 : douta <= 59 ; +3248 : douta <= 59 ; +3249 : douta <= 59 ; +3250 : douta <= 59 ; +3251 : douta <= 59 ; +3252 : douta <= 59 ; +3253 : douta <= 59 ; +3254 : douta <= 59 ; +3255 : douta <= 59 ; +3256 : douta <= 59 ; +3257 : douta <= 59 ; +3258 : douta <= 59 ; +3259 : douta <= 59 ; +3260 : douta <= 59 ; +3261 : douta <= 59 ; +3262 : douta <= 59 ; +3263 : douta <= 59 ; +3264 : douta <= 59 ; +3265 : douta <= 59 ; +3266 : douta <= 59 ; +3267 : douta <= 59 ; +3268 : douta <= 59 ; +3269 : douta <= 59 ; +3270 : douta <= 59 ; +3271 : douta <= 59 ; +3272 : douta <= 59 ; +3273 : douta <= 59 ; +3274 : douta <= 59 ; +3275 : douta <= 59 ; +3276 : douta <= 59 ; +3277 : douta <= 59 ; +3278 : douta <= 59 ; +3279 : douta <= 59 ; +3280 : douta <= 59 ; +3281 : douta <= 59 ; +3282 : douta <= 59 ; +3283 : douta <= 59 ; +3284 : douta <= 59 ; +3285 : douta <= 59 ; +3286 : douta <= 59 ; +3287 : douta <= 59 ; +3288 : douta <= 59 ; +3289 : douta <= 59 ; +3290 : douta <= 59 ; +3291 : douta <= 59 ; +3292 : douta <= 59 ; +3293 : douta <= 59 ; +3294 : douta <= 59 ; +3295 : douta <= 59 ; +3296 : douta <= 59 ; +3297 : douta <= 59 ; +3298 : douta <= 59 ; +3299 : douta <= 59 ; +3300 : douta <= 59 ; +3301 : douta <= 59 ; +3302 : douta <= 59 ; +3303 : douta <= 59 ; +3304 : douta <= 59 ; +3305 : douta <= 59 ; +3306 : douta <= 59 ; +3307 : douta <= 59 ; +3308 : douta <= 59 ; +3309 : douta <= 59 ; +3310 : douta <= 59 ; +3311 : douta <= 59 ; +3312 : douta <= 59 ; +3313 : douta <= 59 ; +3314 : douta <= 59 ; +3315 : douta <= 59 ; +3316 : douta <= 59 ; +3317 : douta <= 59 ; +3318 : douta <= 59 ; +3319 : douta <= 59 ; +3320 : douta <= 59 ; +3321 : douta <= 59 ; +3322 : douta <= 59 ; +3323 : douta <= 59 ; +3324 : douta <= 59 ; +3325 : douta <= 59 ; +3326 : douta <= 59 ; +3327 : douta <= 59 ; +3328 : douta <= 59 ; +3329 : douta <= 59 ; +3330 : douta <= 59 ; +3331 : douta <= 59 ; +3332 : douta <= 59 ; +3333 : douta <= 59 ; +3334 : douta <= 59 ; +3335 : douta <= 59 ; +3336 : douta <= 59 ; +3337 : douta <= 59 ; +3338 : douta <= 59 ; +3339 : douta <= 59 ; +3340 : douta <= 59 ; +3341 : douta <= 59 ; +3342 : douta <= 59 ; +3343 : douta <= 59 ; +3344 : douta <= 59 ; +3345 : douta <= 59 ; +3346 : douta <= 59 ; +3347 : douta <= 59 ; +3348 : douta <= 59 ; +3349 : douta <= 59 ; +3350 : douta <= 59 ; +3351 : douta <= 59 ; +3352 : douta <= 59 ; +3353 : douta <= 59 ; +3354 : douta <= 59 ; +3355 : douta <= 59 ; +3356 : douta <= 59 ; +3357 : douta <= 59 ; +3358 : douta <= 59 ; +3359 : douta <= 59 ; +3360 : douta <= 59 ; +3361 : douta <= 59 ; +3362 : douta <= 59 ; +3363 : douta <= 59 ; +3364 : douta <= 59 ; +3365 : douta <= 59 ; +3366 : douta <= 59 ; +3367 : douta <= 59 ; +3368 : douta <= 59 ; +3369 : douta <= 59 ; +3370 : douta <= 59 ; +3371 : douta <= 59 ; +3372 : douta <= 59 ; +3373 : douta <= 59 ; +3374 : douta <= 59 ; +3375 : douta <= 59 ; +3376 : douta <= 59 ; +3377 : douta <= 59 ; +3378 : douta <= 59 ; +3379 : douta <= 59 ; +3380 : douta <= 59 ; +3381 : douta <= 59 ; +3382 : douta <= 59 ; +3383 : douta <= 59 ; +3384 : douta <= 59 ; +3385 : douta <= 59 ; +3386 : douta <= 59 ; +3387 : douta <= 59 ; +3388 : douta <= 59 ; +3389 : douta <= 59 ; +3390 : douta <= 59 ; +3391 : douta <= 59 ; +3392 : douta <= 59 ; +3393 : douta <= 59 ; +3394 : douta <= 59 ; +3395 : douta <= 59 ; +3396 : douta <= 59 ; +3397 : douta <= 59 ; +3398 : douta <= 59 ; +3399 : douta <= 59 ; +3400 : douta <= 59 ; +3401 : douta <= 59 ; +3402 : douta <= 59 ; +3403 : douta <= 59 ; +3404 : douta <= 59 ; +3405 : douta <= 59 ; +3406 : douta <= 59 ; +3407 : douta <= 59 ; +3408 : douta <= 59 ; +3409 : douta <= 59 ; +3410 : douta <= 59 ; +3411 : douta <= 59 ; +3412 : douta <= 59 ; +3413 : douta <= 59 ; +3414 : douta <= 59 ; +3415 : douta <= 59 ; +3416 : douta <= 59 ; +3417 : douta <= 59 ; +3418 : douta <= 59 ; +3419 : douta <= 59 ; +3420 : douta <= 59 ; +3421 : douta <= 59 ; +3422 : douta <= 59 ; +3423 : douta <= 59 ; +3424 : douta <= 59 ; +3425 : douta <= 59 ; +3426 : douta <= 59 ; +3427 : douta <= 59 ; +3428 : douta <= 59 ; +3429 : douta <= 59 ; +3430 : douta <= 59 ; +3431 : douta <= 59 ; +3432 : douta <= 59 ; +3433 : douta <= 59 ; +3434 : douta <= 59 ; +3435 : douta <= 59 ; +3436 : douta <= 59 ; +3437 : douta <= 59 ; +3438 : douta <= 59 ; +3439 : douta <= 59 ; +3440 : douta <= 59 ; +3441 : douta <= 59 ; +3442 : douta <= 59 ; +3443 : douta <= 59 ; +3444 : douta <= 59 ; +3445 : douta <= 59 ; +3446 : douta <= 59 ; +3447 : douta <= 59 ; +3448 : douta <= 59 ; +3449 : douta <= 59 ; +3450 : douta <= 59 ; +3451 : douta <= 59 ; +3452 : douta <= 59 ; +3453 : douta <= 59 ; +3454 : douta <= 59 ; +3455 : douta <= 59 ; +3456 : douta <= 59 ; +3457 : douta <= 59 ; +3458 : douta <= 59 ; +3459 : douta <= 59 ; +3460 : douta <= 59 ; +3461 : douta <= 59 ; +3462 : douta <= 59 ; +3463 : douta <= 59 ; +3464 : douta <= 59 ; +3465 : douta <= 59 ; +3466 : douta <= 59 ; +3467 : douta <= 59 ; +3468 : douta <= 59 ; +3469 : douta <= 59 ; +3470 : douta <= 59 ; +3471 : douta <= 59 ; +3472 : douta <= 59 ; +3473 : douta <= 59 ; +3474 : douta <= 59 ; +3475 : douta <= 59 ; +3476 : douta <= 59 ; +3477 : douta <= 59 ; +3478 : douta <= 59 ; +3479 : douta <= 59 ; +3480 : douta <= 59 ; +3481 : douta <= 59 ; +3482 : douta <= 59 ; +3483 : douta <= 59 ; +3484 : douta <= 59 ; +3485 : douta <= 59 ; +3486 : douta <= 59 ; +3487 : douta <= 59 ; +3488 : douta <= 59 ; +3489 : douta <= 59 ; +3490 : douta <= 59 ; +3491 : douta <= 59 ; +3492 : douta <= 59 ; +3493 : douta <= 59 ; +3494 : douta <= 59 ; +3495 : douta <= 59 ; +3496 : douta <= 59 ; +3497 : douta <= 59 ; +3498 : douta <= 59 ; +3499 : douta <= 59 ; +3500 : douta <= 59 ; + + + +default:douta <= 59 ; +endcase + + +end + +*/ + + + + + + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_1.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_1.v new file mode 100644 index 0000000..399aa22 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_1.v @@ -0,0 +1,348 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:05:24 04/08/2022 +// Design Name: +// Module Name: R_CAL +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module R_CAL_1( +input i_clk , +input i_rstn , +input signed[7:0] i_temp , +input [15:0] fre_mode , +output reg[3:0] R_CAL + + ); + +//接收通é“1 +always@(posedge i_clk,negedge i_rstn)begin //1dB 步进 + if(!i_rstn) + R_CAL<='d0; + else if(i_temp>=8'sd70)begin//高温校准接收通é“1 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 6 ; //20495 ~ 20534 + 4 : R_CAL<= 6 ; //20535 ~ 20574 + 5 : R_CAL<= 6 ; //20575 ~ 20614 + 6 : R_CAL<= 6 ; //20615 ~ 20654 + 7 : R_CAL<= 6 ; //20655 ~ 20694 + 8 : R_CAL<= 5 ; //20695 ~ 20734 + 9 : R_CAL<= 5 ; //20735 ~ 20774 + 10: R_CAL<= 6 ; //20775 ~ 20814 + 11: R_CAL<= 6 ; //20815 ~ 20854 + 12: R_CAL<= 6 ; //20855 ~ 20894 + 13: R_CAL<= 6 ; //20895 ~ 20934 + 14: R_CAL<= 6 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 6 ; //21055 ~ 21094 + 18: R_CAL<= 6 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 7 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 8 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 7 ; //21895 ~ 21934 + 39: R_CAL<= 7 ; //21935 ~ 21974 + 40: R_CAL<= 7 ; //21975 ~ 22014 + 41: R_CAL<= 7 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 8 ; //22695 ~ 22734 + 59: R_CAL<= 8 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 8 ; //23055 ~ 23094 + 68: R_CAL<= 7 ; //23095 ~ 23134 + 69: R_CAL<= 7 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 6 ; //23255 ~ 23294 + 73: R_CAL<= 6 ; //23295 ~ 23334 + 74: R_CAL<= 6 ; //23335 ~ 23374 + 75: R_CAL<= 6 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 6 ; //23495 ~ 23534 + 79: R_CAL<= 5 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 6 ; //23615 ~ 23654 + 82: R_CAL<= 6 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 6 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + + else if(i_temp>=8'sd0)begin//常温校准接收通é“1 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 6 ; //20495 ~ 20534 + 4 : R_CAL<= 6 ; //20535 ~ 20574 + 5 : R_CAL<= 6 ; //20575 ~ 20614 + 6 : R_CAL<= 6 ; //20615 ~ 20654 + 7 : R_CAL<= 6 ; //20655 ~ 20694 + 8 : R_CAL<= 5 ; //20695 ~ 20734 + 9 : R_CAL<= 5 ; //20735 ~ 20774 + 10: R_CAL<= 6 ; //20775 ~ 20814 + 11: R_CAL<= 6 ; //20815 ~ 20854 + 12: R_CAL<= 6 ; //20855 ~ 20894 + 13: R_CAL<= 6 ; //20895 ~ 20934 + 14: R_CAL<= 6 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 6 ; //21055 ~ 21094 + 18: R_CAL<= 6 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 7 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 8 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 7 ; //21895 ~ 21934 + 39: R_CAL<= 7 ; //21935 ~ 21974 + 40: R_CAL<= 7 ; //21975 ~ 22014 + 41: R_CAL<= 7 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 8 ; //22695 ~ 22734 + 59: R_CAL<= 8 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 8 ; //23055 ~ 23094 + 68: R_CAL<= 7 ; //23095 ~ 23134 + 69: R_CAL<= 7 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 6 ; //23255 ~ 23294 + 73: R_CAL<= 6 ; //23295 ~ 23334 + 74: R_CAL<= 6 ; //23335 ~ 23374 + 75: R_CAL<= 6 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 6 ; //23495 ~ 23534 + 79: R_CAL<= 5 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 6 ; //23615 ~ 23654 + 82: R_CAL<= 6 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 6 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + else begin//低温校准接收通é“1 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 6 ; //20495 ~ 20534 + 4 : R_CAL<= 6 ; //20535 ~ 20574 + 5 : R_CAL<= 6 ; //20575 ~ 20614 + 6 : R_CAL<= 6 ; //20615 ~ 20654 + 7 : R_CAL<= 6 ; //20655 ~ 20694 + 8 : R_CAL<= 5 ; //20695 ~ 20734 + 9 : R_CAL<= 5 ; //20735 ~ 20774 + 10: R_CAL<= 6 ; //20775 ~ 20814 + 11: R_CAL<= 6 ; //20815 ~ 20854 + 12: R_CAL<= 6 ; //20855 ~ 20894 + 13: R_CAL<= 6 ; //20895 ~ 20934 + 14: R_CAL<= 6 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 6 ; //21055 ~ 21094 + 18: R_CAL<= 6 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 7 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 8 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 7 ; //21895 ~ 21934 + 39: R_CAL<= 7 ; //21935 ~ 21974 + 40: R_CAL<= 7 ; //21975 ~ 22014 + 41: R_CAL<= 7 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 8 ; //22695 ~ 22734 + 59: R_CAL<= 8 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 8 ; //23055 ~ 23094 + 68: R_CAL<= 7 ; //23095 ~ 23134 + 69: R_CAL<= 7 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 6 ; //23255 ~ 23294 + 73: R_CAL<= 6 ; //23295 ~ 23334 + 74: R_CAL<= 6 ; //23335 ~ 23374 + 75: R_CAL<= 6 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 6 ; //23495 ~ 23534 + 79: R_CAL<= 5 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 6 ; //23615 ~ 23654 + 82: R_CAL<= 6 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 6 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_2.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_2.v new file mode 100644 index 0000000..e33a079 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_2.v @@ -0,0 +1,349 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:05:24 04/08/2022 +// Design Name: +// Module Name: R_CAL +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module R_CAL_2( +input i_clk , +input i_rstn , +input signed[7:0] i_temp , +input [15:0] fre_mode , +output reg[3:0] R_CAL + + ); + + +//接收通é“2 +always@(posedge i_clk,negedge i_rstn)begin //1dB 步进 + if(!i_rstn) + R_CAL<='d0; + else if(i_temp>=8'sd70)begin//高温校准接收通é“2 + case(fre_mode) + 0 : R_CAL<= 6 ; //20375 ~ 20414 + 1 : R_CAL<= 6 ; //20415 ~ 20454 + 2 : R_CAL<= 6 ; //20455 ~ 20494 + 3 : R_CAL<= 5 ; //20495 ~ 20534 + 4 : R_CAL<= 5 ; //20535 ~ 20574 + 5 : R_CAL<= 5 ; //20575 ~ 20614 + 6 : R_CAL<= 5 ; //20615 ~ 20654 + 7 : R_CAL<= 5 ; //20655 ~ 20694 + 8 : R_CAL<= 5 ; //20695 ~ 20734 + 9 : R_CAL<= 5 ; //20735 ~ 20774 + 10: R_CAL<= 5 ; //20775 ~ 20814 + 11: R_CAL<= 5 ; //20815 ~ 20854 + 12: R_CAL<= 5 ; //20855 ~ 20894 + 13: R_CAL<= 5 ; //20895 ~ 20934 + 14: R_CAL<= 5 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 6 ; //21055 ~ 21094 + 18: R_CAL<= 6 ; //21095 ~ 21134 + 19: R_CAL<= 6 ; //21135 ~ 21174 + 20: R_CAL<= 6 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 7 ; //21255 ~ 21294 + 23: R_CAL<= 7 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 7 ; //21895 ~ 21934 + 39: R_CAL<= 7 ; //21935 ~ 21974 + 40: R_CAL<= 7 ; //21975 ~ 22014 + 41: R_CAL<= 7 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 7 ; //22695 ~ 22734 + 59: R_CAL<= 7 ; //22735 ~ 22774 + 60: R_CAL<= 7 ; //22775 ~ 22814 + 61: R_CAL<= 7 ; //22815 ~ 22854 + 62: R_CAL<= 7 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 7 ; //23055 ~ 23094 + 68: R_CAL<= 7 ; //23095 ~ 23134 + 69: R_CAL<= 7 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 7 ; //23255 ~ 23294 + 73: R_CAL<= 6 ; //23295 ~ 23334 + 74: R_CAL<= 6 ; //23335 ~ 23374 + 75: R_CAL<= 6 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 5 ; //23495 ~ 23534 + 79: R_CAL<= 5 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 5 ; //23615 ~ 23654 + 82: R_CAL<= 5 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 5 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + + else if(i_temp>=8'sd0)begin//常温校准接收通é“2 + case(fre_mode) + 0 : R_CAL<= 6 ; //20375 ~ 20414 + 1 : R_CAL<= 6 ; //20415 ~ 20454 + 2 : R_CAL<= 6 ; //20455 ~ 20494 + 3 : R_CAL<= 5 ; //20495 ~ 20534 + 4 : R_CAL<= 5 ; //20535 ~ 20574 + 5 : R_CAL<= 5 ; //20575 ~ 20614 + 6 : R_CAL<= 5 ; //20615 ~ 20654 + 7 : R_CAL<= 5 ; //20655 ~ 20694 + 8 : R_CAL<= 5 ; //20695 ~ 20734 + 9 : R_CAL<= 5 ; //20735 ~ 20774 + 10: R_CAL<= 5 ; //20775 ~ 20814 + 11: R_CAL<= 5 ; //20815 ~ 20854 + 12: R_CAL<= 5 ; //20855 ~ 20894 + 13: R_CAL<= 5 ; //20895 ~ 20934 + 14: R_CAL<= 5 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 6 ; //21055 ~ 21094 + 18: R_CAL<= 6 ; //21095 ~ 21134 + 19: R_CAL<= 6 ; //21135 ~ 21174 + 20: R_CAL<= 6 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 7 ; //21255 ~ 21294 + 23: R_CAL<= 7 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 7 ; //21895 ~ 21934 + 39: R_CAL<= 7 ; //21935 ~ 21974 + 40: R_CAL<= 7 ; //21975 ~ 22014 + 41: R_CAL<= 7 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 7 ; //22695 ~ 22734 + 59: R_CAL<= 7 ; //22735 ~ 22774 + 60: R_CAL<= 7 ; //22775 ~ 22814 + 61: R_CAL<= 7 ; //22815 ~ 22854 + 62: R_CAL<= 7 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 7 ; //23055 ~ 23094 + 68: R_CAL<= 7 ; //23095 ~ 23134 + 69: R_CAL<= 7 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 7 ; //23255 ~ 23294 + 73: R_CAL<= 6 ; //23295 ~ 23334 + 74: R_CAL<= 6 ; //23335 ~ 23374 + 75: R_CAL<= 6 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 5 ; //23495 ~ 23534 + 79: R_CAL<= 5 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 5 ; //23615 ~ 23654 + 82: R_CAL<= 5 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 5 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + else begin//低温校准接收通é“2 + case(fre_mode) + 0 : R_CAL<= 6 ; //20375 ~ 20414 + 1 : R_CAL<= 6 ; //20415 ~ 20454 + 2 : R_CAL<= 6 ; //20455 ~ 20494 + 3 : R_CAL<= 5 ; //20495 ~ 20534 + 4 : R_CAL<= 5 ; //20535 ~ 20574 + 5 : R_CAL<= 5 ; //20575 ~ 20614 + 6 : R_CAL<= 5 ; //20615 ~ 20654 + 7 : R_CAL<= 5 ; //20655 ~ 20694 + 8 : R_CAL<= 5 ; //20695 ~ 20734 + 9 : R_CAL<= 5 ; //20735 ~ 20774 + 10: R_CAL<= 5 ; //20775 ~ 20814 + 11: R_CAL<= 5 ; //20815 ~ 20854 + 12: R_CAL<= 5 ; //20855 ~ 20894 + 13: R_CAL<= 5 ; //20895 ~ 20934 + 14: R_CAL<= 5 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 6 ; //21055 ~ 21094 + 18: R_CAL<= 6 ; //21095 ~ 21134 + 19: R_CAL<= 6 ; //21135 ~ 21174 + 20: R_CAL<= 6 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 7 ; //21255 ~ 21294 + 23: R_CAL<= 7 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 7 ; //21895 ~ 21934 + 39: R_CAL<= 7 ; //21935 ~ 21974 + 40: R_CAL<= 7 ; //21975 ~ 22014 + 41: R_CAL<= 7 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 7 ; //22695 ~ 22734 + 59: R_CAL<= 7 ; //22735 ~ 22774 + 60: R_CAL<= 7 ; //22775 ~ 22814 + 61: R_CAL<= 7 ; //22815 ~ 22854 + 62: R_CAL<= 7 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 7 ; //23055 ~ 23094 + 68: R_CAL<= 7 ; //23095 ~ 23134 + 69: R_CAL<= 7 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 7 ; //23255 ~ 23294 + 73: R_CAL<= 6 ; //23295 ~ 23334 + 74: R_CAL<= 6 ; //23335 ~ 23374 + 75: R_CAL<= 6 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 5 ; //23495 ~ 23534 + 79: R_CAL<= 5 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 5 ; //23615 ~ 23654 + 82: R_CAL<= 5 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 5 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_3.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_3.v new file mode 100644 index 0000000..1c26ffe --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_3.v @@ -0,0 +1,348 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:05:24 04/08/2022 +// Design Name: +// Module Name: R_CAL +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module R_CAL_3( +input i_clk , +input i_rstn , +input signed[7:0] i_temp , +input [15:0] fre_mode , +output reg[3:0] R_CAL + + ); + +//接收通é“3 +always@(posedge i_clk,negedge i_rstn)begin //1dB 步进 + if(!i_rstn) + R_CAL<='d0; + else if(i_temp>=8'sd70)begin//高温校准接收通é“3 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 7 ; //20495 ~ 20534 + 4 : R_CAL<= 7 ; //20535 ~ 20574 + 5 : R_CAL<= 7 ; //20575 ~ 20614 + 6 : R_CAL<= 6 ; //20615 ~ 20654 + 7 : R_CAL<= 6 ; //20655 ~ 20694 + 8 : R_CAL<= 6 ; //20695 ~ 20734 + 9 : R_CAL<= 6 ; //20735 ~ 20774 + 10: R_CAL<= 6 ; //20775 ~ 20814 + 11: R_CAL<= 6 ; //20815 ~ 20854 + 12: R_CAL<= 6 ; //20855 ~ 20894 + 13: R_CAL<= 6 ; //20895 ~ 20934 + 14: R_CAL<= 6 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 7 ; //21055 ~ 21094 + 18: R_CAL<= 7 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 8 ; //21175 ~ 21214 + 21: R_CAL<= 8 ; //21215 ~ 21254 + 22: R_CAL<= 8 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 9 ; //21415 ~ 21454 + 27: R_CAL<= 9 ; //21455 ~ 21494 + 28: R_CAL<= 9 ; //21495 ~ 21534 + 29: R_CAL<= 9 ; //21535 ~ 21574 + 30: R_CAL<= 9 ; //21575 ~ 21614 + 31: R_CAL<= 9 ; //21615 ~ 21654 + 32: R_CAL<= 9 ; //21655 ~ 21694 + 33: R_CAL<= 9 ; //21695 ~ 21734 + 34: R_CAL<= 9 ; //21735 ~ 21774 + 35: R_CAL<= 9 ; //21775 ~ 21814 + 36: R_CAL<= 9 ; //21815 ~ 21854 + 37: R_CAL<= 9 ; //21855 ~ 21894 + 38: R_CAL<= 9 ; //21895 ~ 21934 + 39: R_CAL<= 9 ; //21935 ~ 21974 + 40: R_CAL<= 8 ; //21975 ~ 22014 + 41: R_CAL<= 8 ; //22015 ~ 22054 + 42: R_CAL<= 8 ; //22055 ~ 22094 + 43: R_CAL<= 8 ; //22095 ~ 22134 + 44: R_CAL<= 8 ; //22135 ~ 22174 + 45: R_CAL<= 8 ; //22175 ~ 22214 + 46: R_CAL<= 8 ; //22215 ~ 22254 + 47: R_CAL<= 8 ; //22255 ~ 22294 + 48: R_CAL<= 8 ; //22295 ~ 22334 + 49: R_CAL<= 8 ; //22335 ~ 22374 + 50: R_CAL<= 8 ; //22375 ~ 22414 + 51: R_CAL<= 8 ; //22415 ~ 22454 + 52: R_CAL<= 8 ; //22455 ~ 22494 + 53: R_CAL<= 8 ; //22495 ~ 22534 + 54: R_CAL<= 8 ; //22535 ~ 22574 + 55: R_CAL<= 8 ; //22575 ~ 22614 + 56: R_CAL<= 8 ; //22615 ~ 22654 + 57: R_CAL<= 8 ; //22655 ~ 22694 + 58: R_CAL<= 8 ; //22695 ~ 22734 + 59: R_CAL<= 8 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 9 ; //22895 ~ 22934 + 64: R_CAL<= 9 ; //22935 ~ 22974 + 65: R_CAL<= 9 ; //22975 ~ 23014 + 66: R_CAL<= 9 ; //23015 ~ 23054 + 67: R_CAL<= 9 ; //23055 ~ 23094 + 68: R_CAL<= 8 ; //23095 ~ 23134 + 69: R_CAL<= 8 ; //23135 ~ 23174 + 70: R_CAL<= 8 ; //23175 ~ 23214 + 71: R_CAL<= 8 ; //23215 ~ 23254 + 72: R_CAL<= 8 ; //23255 ~ 23294 + 73: R_CAL<= 7 ; //23295 ~ 23334 + 74: R_CAL<= 7 ; //23335 ~ 23374 + 75: R_CAL<= 7 ; //23375 ~ 23414 + 76: R_CAL<= 7 ; //23415 ~ 23454 + 77: R_CAL<= 7 ; //23455 ~ 23494 + 78: R_CAL<= 7 ; //23495 ~ 23534 + 79: R_CAL<= 7 ; //23535 ~ 23574 + 80: R_CAL<= 7 ; //23575 ~ 23614 + 81: R_CAL<= 7 ; //23615 ~ 23654 + 82: R_CAL<= 7 ; //23655 ~ 23694 + 83: R_CAL<= 7 ; //23695 ~ 23734 + 84: R_CAL<= 7 ; //23735 ~ 23774 + 85: R_CAL<= 7 ; //23775 ~ 23814 + 86: R_CAL<= 7 ; //23815 ~ 23854 + 87: R_CAL<= 7 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + + else if(i_temp>=8'sd0)begin//常温校准接收通é“3 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 7 ; //20495 ~ 20534 + 4 : R_CAL<= 7 ; //20535 ~ 20574 + 5 : R_CAL<= 7 ; //20575 ~ 20614 + 6 : R_CAL<= 6 ; //20615 ~ 20654 + 7 : R_CAL<= 6 ; //20655 ~ 20694 + 8 : R_CAL<= 6 ; //20695 ~ 20734 + 9 : R_CAL<= 6 ; //20735 ~ 20774 + 10: R_CAL<= 6 ; //20775 ~ 20814 + 11: R_CAL<= 6 ; //20815 ~ 20854 + 12: R_CAL<= 6 ; //20855 ~ 20894 + 13: R_CAL<= 6 ; //20895 ~ 20934 + 14: R_CAL<= 6 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 7 ; //21055 ~ 21094 + 18: R_CAL<= 7 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 8 ; //21175 ~ 21214 + 21: R_CAL<= 8 ; //21215 ~ 21254 + 22: R_CAL<= 8 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 9 ; //21415 ~ 21454 + 27: R_CAL<= 9 ; //21455 ~ 21494 + 28: R_CAL<= 9 ; //21495 ~ 21534 + 29: R_CAL<= 9 ; //21535 ~ 21574 + 30: R_CAL<= 9 ; //21575 ~ 21614 + 31: R_CAL<= 9 ; //21615 ~ 21654 + 32: R_CAL<= 9 ; //21655 ~ 21694 + 33: R_CAL<= 9 ; //21695 ~ 21734 + 34: R_CAL<= 9 ; //21735 ~ 21774 + 35: R_CAL<= 9 ; //21775 ~ 21814 + 36: R_CAL<= 9 ; //21815 ~ 21854 + 37: R_CAL<= 9 ; //21855 ~ 21894 + 38: R_CAL<= 9 ; //21895 ~ 21934 + 39: R_CAL<= 9 ; //21935 ~ 21974 + 40: R_CAL<= 8 ; //21975 ~ 22014 + 41: R_CAL<= 8 ; //22015 ~ 22054 + 42: R_CAL<= 8 ; //22055 ~ 22094 + 43: R_CAL<= 8 ; //22095 ~ 22134 + 44: R_CAL<= 8 ; //22135 ~ 22174 + 45: R_CAL<= 8 ; //22175 ~ 22214 + 46: R_CAL<= 8 ; //22215 ~ 22254 + 47: R_CAL<= 8 ; //22255 ~ 22294 + 48: R_CAL<= 8 ; //22295 ~ 22334 + 49: R_CAL<= 8 ; //22335 ~ 22374 + 50: R_CAL<= 8 ; //22375 ~ 22414 + 51: R_CAL<= 8 ; //22415 ~ 22454 + 52: R_CAL<= 8 ; //22455 ~ 22494 + 53: R_CAL<= 8 ; //22495 ~ 22534 + 54: R_CAL<= 8 ; //22535 ~ 22574 + 55: R_CAL<= 8 ; //22575 ~ 22614 + 56: R_CAL<= 8 ; //22615 ~ 22654 + 57: R_CAL<= 8 ; //22655 ~ 22694 + 58: R_CAL<= 8 ; //22695 ~ 22734 + 59: R_CAL<= 8 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 9 ; //22895 ~ 22934 + 64: R_CAL<= 9 ; //22935 ~ 22974 + 65: R_CAL<= 9 ; //22975 ~ 23014 + 66: R_CAL<= 9 ; //23015 ~ 23054 + 67: R_CAL<= 9 ; //23055 ~ 23094 + 68: R_CAL<= 8 ; //23095 ~ 23134 + 69: R_CAL<= 8 ; //23135 ~ 23174 + 70: R_CAL<= 8 ; //23175 ~ 23214 + 71: R_CAL<= 8 ; //23215 ~ 23254 + 72: R_CAL<= 8 ; //23255 ~ 23294 + 73: R_CAL<= 7 ; //23295 ~ 23334 + 74: R_CAL<= 7 ; //23335 ~ 23374 + 75: R_CAL<= 7 ; //23375 ~ 23414 + 76: R_CAL<= 7 ; //23415 ~ 23454 + 77: R_CAL<= 7 ; //23455 ~ 23494 + 78: R_CAL<= 7 ; //23495 ~ 23534 + 79: R_CAL<= 7 ; //23535 ~ 23574 + 80: R_CAL<= 7 ; //23575 ~ 23614 + 81: R_CAL<= 7 ; //23615 ~ 23654 + 82: R_CAL<= 7 ; //23655 ~ 23694 + 83: R_CAL<= 7 ; //23695 ~ 23734 + 84: R_CAL<= 7 ; //23735 ~ 23774 + 85: R_CAL<= 7 ; //23775 ~ 23814 + 86: R_CAL<= 7 ; //23815 ~ 23854 + 87: R_CAL<= 7 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + else begin//低温校准接收通é“3 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 7 ; //20495 ~ 20534 + 4 : R_CAL<= 7 ; //20535 ~ 20574 + 5 : R_CAL<= 7 ; //20575 ~ 20614 + 6 : R_CAL<= 6 ; //20615 ~ 20654 + 7 : R_CAL<= 6 ; //20655 ~ 20694 + 8 : R_CAL<= 6 ; //20695 ~ 20734 + 9 : R_CAL<= 6 ; //20735 ~ 20774 + 10: R_CAL<= 6 ; //20775 ~ 20814 + 11: R_CAL<= 6 ; //20815 ~ 20854 + 12: R_CAL<= 6 ; //20855 ~ 20894 + 13: R_CAL<= 6 ; //20895 ~ 20934 + 14: R_CAL<= 6 ; //20935 ~ 20974 + 15: R_CAL<= 6 ; //20975 ~ 21014 + 16: R_CAL<= 6 ; //21015 ~ 21054 + 17: R_CAL<= 7 ; //21055 ~ 21094 + 18: R_CAL<= 7 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 8 ; //21175 ~ 21214 + 21: R_CAL<= 8 ; //21215 ~ 21254 + 22: R_CAL<= 8 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 9 ; //21415 ~ 21454 + 27: R_CAL<= 9 ; //21455 ~ 21494 + 28: R_CAL<= 9 ; //21495 ~ 21534 + 29: R_CAL<= 9 ; //21535 ~ 21574 + 30: R_CAL<= 9 ; //21575 ~ 21614 + 31: R_CAL<= 9 ; //21615 ~ 21654 + 32: R_CAL<= 9 ; //21655 ~ 21694 + 33: R_CAL<= 9 ; //21695 ~ 21734 + 34: R_CAL<= 9 ; //21735 ~ 21774 + 35: R_CAL<= 9 ; //21775 ~ 21814 + 36: R_CAL<= 9 ; //21815 ~ 21854 + 37: R_CAL<= 9 ; //21855 ~ 21894 + 38: R_CAL<= 9 ; //21895 ~ 21934 + 39: R_CAL<= 9 ; //21935 ~ 21974 + 40: R_CAL<= 8 ; //21975 ~ 22014 + 41: R_CAL<= 8 ; //22015 ~ 22054 + 42: R_CAL<= 8 ; //22055 ~ 22094 + 43: R_CAL<= 8 ; //22095 ~ 22134 + 44: R_CAL<= 8 ; //22135 ~ 22174 + 45: R_CAL<= 8 ; //22175 ~ 22214 + 46: R_CAL<= 8 ; //22215 ~ 22254 + 47: R_CAL<= 8 ; //22255 ~ 22294 + 48: R_CAL<= 8 ; //22295 ~ 22334 + 49: R_CAL<= 8 ; //22335 ~ 22374 + 50: R_CAL<= 8 ; //22375 ~ 22414 + 51: R_CAL<= 8 ; //22415 ~ 22454 + 52: R_CAL<= 8 ; //22455 ~ 22494 + 53: R_CAL<= 8 ; //22495 ~ 22534 + 54: R_CAL<= 8 ; //22535 ~ 22574 + 55: R_CAL<= 8 ; //22575 ~ 22614 + 56: R_CAL<= 8 ; //22615 ~ 22654 + 57: R_CAL<= 8 ; //22655 ~ 22694 + 58: R_CAL<= 8 ; //22695 ~ 22734 + 59: R_CAL<= 8 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 9 ; //22895 ~ 22934 + 64: R_CAL<= 9 ; //22935 ~ 22974 + 65: R_CAL<= 9 ; //22975 ~ 23014 + 66: R_CAL<= 9 ; //23015 ~ 23054 + 67: R_CAL<= 9 ; //23055 ~ 23094 + 68: R_CAL<= 8 ; //23095 ~ 23134 + 69: R_CAL<= 8 ; //23135 ~ 23174 + 70: R_CAL<= 8 ; //23175 ~ 23214 + 71: R_CAL<= 8 ; //23215 ~ 23254 + 72: R_CAL<= 8 ; //23255 ~ 23294 + 73: R_CAL<= 7 ; //23295 ~ 23334 + 74: R_CAL<= 7 ; //23335 ~ 23374 + 75: R_CAL<= 7 ; //23375 ~ 23414 + 76: R_CAL<= 7 ; //23415 ~ 23454 + 77: R_CAL<= 7 ; //23455 ~ 23494 + 78: R_CAL<= 7 ; //23495 ~ 23534 + 79: R_CAL<= 7 ; //23535 ~ 23574 + 80: R_CAL<= 7 ; //23575 ~ 23614 + 81: R_CAL<= 7 ; //23615 ~ 23654 + 82: R_CAL<= 7 ; //23655 ~ 23694 + 83: R_CAL<= 7 ; //23695 ~ 23734 + 84: R_CAL<= 7 ; //23735 ~ 23774 + 85: R_CAL<= 7 ; //23775 ~ 23814 + 86: R_CAL<= 7 ; //23815 ~ 23854 + 87: R_CAL<= 7 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_4.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_4.v new file mode 100644 index 0000000..4ef0c5e --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_4.v @@ -0,0 +1,349 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:05:24 04/08/2022 +// Design Name: +// Module Name: R_CAL +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module R_CAL_4( +input i_clk , +input i_rstn , +input signed[7:0] i_temp , +input [15:0] fre_mode , +output reg[3:0] R_CAL + + ); + + +//接收通é“4 +always@(posedge i_clk,negedge i_rstn)begin //1dB 步进 + if(!i_rstn) + R_CAL<='d0; + else if(i_temp>=8'sd70)begin//高温校准接收通é“4 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 7 ; //20495 ~ 20534 + 4 : R_CAL<= 7 ; //20535 ~ 20574 + 5 : R_CAL<= 7 ; //20575 ~ 20614 + 6 : R_CAL<= 7 ; //20615 ~ 20654 + 7 : R_CAL<= 7 ; //20655 ~ 20694 + 8 : R_CAL<= 7 ; //20695 ~ 20734 + 9 : R_CAL<= 7 ; //20735 ~ 20774 + 10: R_CAL<= 7 ; //20775 ~ 20814 + 11: R_CAL<= 7 ; //20815 ~ 20854 + 12: R_CAL<= 7 ; //20855 ~ 20894 + 13: R_CAL<= 7 ; //20895 ~ 20934 + 14: R_CAL<= 7 ; //20935 ~ 20974 + 15: R_CAL<= 7 ; //20975 ~ 21014 + 16: R_CAL<= 7 ; //21015 ~ 21054 + 17: R_CAL<= 7 ; //21055 ~ 21094 + 18: R_CAL<= 7 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 7 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 7 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 8 ; //21895 ~ 21934 + 39: R_CAL<= 8 ; //21935 ~ 21974 + 40: R_CAL<= 8 ; //21975 ~ 22014 + 41: R_CAL<= 8 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 7 ; //22695 ~ 22734 + 59: R_CAL<= 7 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 8 ; //23055 ~ 23094 + 68: R_CAL<= 8 ; //23095 ~ 23134 + 69: R_CAL<= 8 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 7 ; //23255 ~ 23294 + 73: R_CAL<= 7 ; //23295 ~ 23334 + 74: R_CAL<= 7 ; //23335 ~ 23374 + 75: R_CAL<= 7 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 6 ; //23495 ~ 23534 + 79: R_CAL<= 6 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 6 ; //23615 ~ 23654 + 82: R_CAL<= 6 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 6 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + + else if(i_temp>=8'sd0)begin//常温校准接收通é“4 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 7 ; //20495 ~ 20534 + 4 : R_CAL<= 7 ; //20535 ~ 20574 + 5 : R_CAL<= 7 ; //20575 ~ 20614 + 6 : R_CAL<= 7 ; //20615 ~ 20654 + 7 : R_CAL<= 7 ; //20655 ~ 20694 + 8 : R_CAL<= 7 ; //20695 ~ 20734 + 9 : R_CAL<= 7 ; //20735 ~ 20774 + 10: R_CAL<= 7 ; //20775 ~ 20814 + 11: R_CAL<= 7 ; //20815 ~ 20854 + 12: R_CAL<= 7 ; //20855 ~ 20894 + 13: R_CAL<= 7 ; //20895 ~ 20934 + 14: R_CAL<= 7 ; //20935 ~ 20974 + 15: R_CAL<= 7 ; //20975 ~ 21014 + 16: R_CAL<= 7 ; //21015 ~ 21054 + 17: R_CAL<= 7 ; //21055 ~ 21094 + 18: R_CAL<= 7 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 7 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 7 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 8 ; //21895 ~ 21934 + 39: R_CAL<= 8 ; //21935 ~ 21974 + 40: R_CAL<= 8 ; //21975 ~ 22014 + 41: R_CAL<= 8 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 7 ; //22695 ~ 22734 + 59: R_CAL<= 7 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 8 ; //23055 ~ 23094 + 68: R_CAL<= 8 ; //23095 ~ 23134 + 69: R_CAL<= 8 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 7 ; //23255 ~ 23294 + 73: R_CAL<= 7 ; //23295 ~ 23334 + 74: R_CAL<= 7 ; //23335 ~ 23374 + 75: R_CAL<= 7 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 6 ; //23495 ~ 23534 + 79: R_CAL<= 6 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 6 ; //23615 ~ 23654 + 82: R_CAL<= 6 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 6 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end + else begin//低温校准接收通é“4 + case(fre_mode) + 0 : R_CAL<= 7 ; //20375 ~ 20414 + 1 : R_CAL<= 7 ; //20415 ~ 20454 + 2 : R_CAL<= 7 ; //20455 ~ 20494 + 3 : R_CAL<= 7 ; //20495 ~ 20534 + 4 : R_CAL<= 7 ; //20535 ~ 20574 + 5 : R_CAL<= 7 ; //20575 ~ 20614 + 6 : R_CAL<= 7 ; //20615 ~ 20654 + 7 : R_CAL<= 7 ; //20655 ~ 20694 + 8 : R_CAL<= 7 ; //20695 ~ 20734 + 9 : R_CAL<= 7 ; //20735 ~ 20774 + 10: R_CAL<= 7 ; //20775 ~ 20814 + 11: R_CAL<= 7 ; //20815 ~ 20854 + 12: R_CAL<= 7 ; //20855 ~ 20894 + 13: R_CAL<= 7 ; //20895 ~ 20934 + 14: R_CAL<= 7 ; //20935 ~ 20974 + 15: R_CAL<= 7 ; //20975 ~ 21014 + 16: R_CAL<= 7 ; //21015 ~ 21054 + 17: R_CAL<= 7 ; //21055 ~ 21094 + 18: R_CAL<= 7 ; //21095 ~ 21134 + 19: R_CAL<= 7 ; //21135 ~ 21174 + 20: R_CAL<= 7 ; //21175 ~ 21214 + 21: R_CAL<= 7 ; //21215 ~ 21254 + 22: R_CAL<= 7 ; //21255 ~ 21294 + 23: R_CAL<= 8 ; //21295 ~ 21334 + 24: R_CAL<= 8 ; //21335 ~ 21374 + 25: R_CAL<= 8 ; //21375 ~ 21414 + 26: R_CAL<= 8 ; //21415 ~ 21454 + 27: R_CAL<= 8 ; //21455 ~ 21494 + 28: R_CAL<= 8 ; //21495 ~ 21534 + 29: R_CAL<= 8 ; //21535 ~ 21574 + 30: R_CAL<= 8 ; //21575 ~ 21614 + 31: R_CAL<= 8 ; //21615 ~ 21654 + 32: R_CAL<= 8 ; //21655 ~ 21694 + 33: R_CAL<= 8 ; //21695 ~ 21734 + 34: R_CAL<= 8 ; //21735 ~ 21774 + 35: R_CAL<= 8 ; //21775 ~ 21814 + 36: R_CAL<= 8 ; //21815 ~ 21854 + 37: R_CAL<= 8 ; //21855 ~ 21894 + 38: R_CAL<= 8 ; //21895 ~ 21934 + 39: R_CAL<= 8 ; //21935 ~ 21974 + 40: R_CAL<= 8 ; //21975 ~ 22014 + 41: R_CAL<= 8 ; //22015 ~ 22054 + 42: R_CAL<= 7 ; //22055 ~ 22094 + 43: R_CAL<= 7 ; //22095 ~ 22134 + 44: R_CAL<= 7 ; //22135 ~ 22174 + 45: R_CAL<= 7 ; //22175 ~ 22214 + 46: R_CAL<= 7 ; //22215 ~ 22254 + 47: R_CAL<= 7 ; //22255 ~ 22294 + 48: R_CAL<= 7 ; //22295 ~ 22334 + 49: R_CAL<= 7 ; //22335 ~ 22374 + 50: R_CAL<= 7 ; //22375 ~ 22414 + 51: R_CAL<= 7 ; //22415 ~ 22454 + 52: R_CAL<= 7 ; //22455 ~ 22494 + 53: R_CAL<= 7 ; //22495 ~ 22534 + 54: R_CAL<= 7 ; //22535 ~ 22574 + 55: R_CAL<= 7 ; //22575 ~ 22614 + 56: R_CAL<= 7 ; //22615 ~ 22654 + 57: R_CAL<= 7 ; //22655 ~ 22694 + 58: R_CAL<= 7 ; //22695 ~ 22734 + 59: R_CAL<= 7 ; //22735 ~ 22774 + 60: R_CAL<= 8 ; //22775 ~ 22814 + 61: R_CAL<= 8 ; //22815 ~ 22854 + 62: R_CAL<= 8 ; //22855 ~ 22894 + 63: R_CAL<= 8 ; //22895 ~ 22934 + 64: R_CAL<= 8 ; //22935 ~ 22974 + 65: R_CAL<= 8 ; //22975 ~ 23014 + 66: R_CAL<= 8 ; //23015 ~ 23054 + 67: R_CAL<= 8 ; //23055 ~ 23094 + 68: R_CAL<= 8 ; //23095 ~ 23134 + 69: R_CAL<= 8 ; //23135 ~ 23174 + 70: R_CAL<= 7 ; //23175 ~ 23214 + 71: R_CAL<= 7 ; //23215 ~ 23254 + 72: R_CAL<= 7 ; //23255 ~ 23294 + 73: R_CAL<= 7 ; //23295 ~ 23334 + 74: R_CAL<= 7 ; //23335 ~ 23374 + 75: R_CAL<= 7 ; //23375 ~ 23414 + 76: R_CAL<= 6 ; //23415 ~ 23454 + 77: R_CAL<= 6 ; //23455 ~ 23494 + 78: R_CAL<= 6 ; //23495 ~ 23534 + 79: R_CAL<= 6 ; //23535 ~ 23574 + 80: R_CAL<= 6 ; //23575 ~ 23614 + 81: R_CAL<= 6 ; //23615 ~ 23654 + 82: R_CAL<= 6 ; //23655 ~ 23694 + 83: R_CAL<= 6 ; //23695 ~ 23734 + 84: R_CAL<= 6 ; //23735 ~ 23774 + 85: R_CAL<= 6 ; //23775 ~ 23814 + 86: R_CAL<= 6 ; //23815 ~ 23854 + 87: R_CAL<= 6 ; //23855 ~ 23875 + default:R_CAL<=R_CAL; + endcase + end +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/Sisyif.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/Sisyif.v new file mode 100644 index 0000000..0a0d563 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/Sisyif.v @@ -0,0 +1,301 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: Chengdu Tiger +// Engineer: Tangxy +// +// Create Date: 14:14:49 09/06/2021 +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Sisyif( +input clk_40m , +input clk_20m , +input rst_n , +//è°ƒé›¶è‡³ä¿¡å¤„æŽ¥å£ +input SPI_CLK_F ,//SPI控制，时钟暂定50MHz，用æ¥å‘é€è·³é¢‘频点ã€å‘å°„MGC值ã€æŽ¥æ”¶MGC值 +input SPI_SYN_F ,//片选 +input SPI_MOSI_F , +output SPI_MISO_F , +input TP_EN_F ,//跳频使能控制(上å‡æ²¿æ›´æ–°) +input TR_MGC_F ,//接收å‘å°„MGC使能控制(上å‡æ²¿æ›´æ–°) +input CAL_F ,//校准MGC使能(上å‡æ²¿æ›´æ–°) +input PRF ,//高å‘低收，默认接收 + +//ä¿¡å¤„è‡³å°„é¢‘æŽ¥å£ +output standby ,//高开低待机，默认待机 +output SW_PLL ,//乒乓频率æºé€‰æ‹©0：频率æºA —— 1：频率æºB +output T ,//å‘射电æºæŽ§åˆ¶ +output R ,//接收电æºæŽ§åˆ¶ +output SW_BPF ,//开关滤波器选择 +output SCLK1 ,//é”相环A控制 +output SDIO1 ,// +output CS1 ,// +input LD1 ,// +output SCLK2 ,//é”相环B控制 +output SDIO2 ,// +output CS2 ,// +input LD2 ,// +output SCLK3 ,//点频æºæŽ§åˆ¶ +output SDIO3 ,// +output CS3 ,// +input LD3 ,// +output TMGC_16db ,//å‘射通é“MGC控制,é«˜ç”µå¹³è¡°å‡ +output TMGC_8db ,// +output TMGC_4db ,// +output TMGC_2db ,// +output TMGC_1db ,// +output RMGC_16db ,//四个接收通é“MGC控制，åŒæ—¶æŽ§åˆ¶ï¼Œé«˜ç”µå¹³è¡°å‡ +output RMGC_8db ,// +output RMGC_4db ,// +output RMGC_2db ,// +output RMGC_1db ,// +output ENABLE ,//SPI控制四个接收通é“增益校准 +output SC ,// +output SD ,// +output END_SYN ,// +input SDOUT ,// +inout DQ_WD ,//温度传感器 +output SW_RX //接收监测控制 + +); + +wire vio_rstn ; +wire [9:0] SYNC_OUT ; +wire [35:0] CONTROL0 ; +wire [35:0] CONTROL1 ; +wire [150:0] TRIG0 ; + +wire[15:0] temp_data ;//LSB =0.625 C +wire[7:0] temp ;//LSB =1°C +wire[11:0] hop_fre_code; +wire adf4371_hop1 ; +wire adf4371_hop2 ; +wire [15:0] fre_code ; +wire [7:0] tx_mgc ; +wire [7:0] rx1_mgc ; +wire [7:0] rx2_mgc ; +wire [7:0] rx3_mgc ; +wire [7:0] rx4_mgc ; +wire [3:0] cal1_mgc ; +wire [3:0] cal2_mgc ; +wire [3:0] cal3_mgc ; +wire [3:0] cal4_mgc ; +wire [7:0] tx_cal_mgc ; +wire [3:0] model ; +wire [3:0] rf_en ; +wire [31:0] frame_count; +wire [3:0] ceshi_model; +wire [15:0] current_fre_code ; +wire [15:0] cal_fre_code ; +wire [7:0] R_MGC_1 ; + +wire SW_C1; +wire SW; +wire SW2; +wire SW3; + +wire [3:0] R_CAL1; +wire [3:0] R_CAL2; +wire [3:0] R_CAL3; +wire [3:0] R_CAL4; +wire [4:0] T_CAL ; + +assign temp = temp_data[11:4] ; +assign RMGC_16db = R_MGC_1[4] ; +assign RMGC_8db = R_MGC_1[3] ; +assign RMGC_4db = R_MGC_1[2] ; +assign RMGC_2db = R_MGC_1[1] ; +assign RMGC_1db = R_MGC_1[0] ; +assign standby = rf_en == 4'b0 ; +assign T = PRF ; +assign R = ~PRF ; +assign SW_BPF = SW_C1 ; +assign SW_PLL = SW ; +assign SW_RX = rx2_mgc == 8'b0 ? 1'b0 :1'b1 ; + + +spi_slave u_spi_slave ( + .i_sys_clk(clk_40m), + .i_sys_rst_n(rst_n), + .i_spi_sck(SPI_CLK_F), + .i_spi_cs(SPI_SYN_F), + .i_spi_sdi(SPI_MOSI_F), + .o_frame_count(frame_count), + .o_fre_code(fre_code), + .o_tx_mgc(tx_mgc), + .o_model(model), + .o_rf_en(rf_en), + .o_cal1_mgc(cal1_mgc), + .o_cal2_mgc(cal2_mgc), + .o_cal3_mgc(cal3_mgc), + .o_cal4_mgc(cal4_mgc), + .o_tx_cal_mgc(tx_cal_mgc), + .o_rx1_mgc(rx1_mgc), + .o_rx2_mgc(rx2_mgc), + .o_rx3_mgc(rx3_mgc), + .o_rx4_mgc(rx4_mgc), + .o_ceshi_model(ceshi_model) + ); + +spi_master u_spi_master ( +.i_sys_rst_n (rst_n) , +.i_clk (clk_40m) , +//.debug_clk (clk_80m) , +.i_spi_sck (SPI_CLK_F) , +.i_spi_cs (SPI_SYN_F) , +.o_spi_sdo (SPI_MISO_F) , +.i_spi_sdi (SPI_MOSI_F) , +.i_LD_LO3 (LD3) , +.i_LD1 (LD1) , +.i_LD2 (LD2) , +.i_cal1_mgc (R_CAL4) , +.i_cal2_mgc (R_CAL3) , +.i_cal3_mgc (R_CAL2) , +.i_cal4_mgc (R_CAL1) , +.i_temp (temp ) , +.i_frame_count (frame_count) + ); + +mgc_ctrl u_mgc_ctrl( + .i_sys_clk (clk_40m ), + .i_rst_n (rst_n ), + .i_TR_SW_F (PRF ), + .i_TP_EN_F (TP_EN_F ), + .i_T_MGC_EN_F (TR_MGC_F ), + .i_R_MGC_EN_F (TR_MGC_F ), + .i_CAL_F (CAL_F ), + .i_fre_code (fre_code ), + .i_tx_mgc (tx_mgc ), + .i_rx1_mgc (rx1_mgc ), + .i_rx2_mgc (rx2_mgc ), + .i_rx3_mgc (rx3_mgc ), + .i_rx4_mgc (rx4_mgc ), + .i_ceshi_module (ceshi_model ), + .o_current_fre_code (current_fre_code ), + .o_cal_fre_code (cal_fre_code ), + .o_hop_fre_code (hop_fre_code ), //0(20.375GHz)~3500(23.875GHz) + .o_adf4371_hop1 (adf4371_hop1 ), //high active + .o_adf4371_hop2 (adf4371_hop2 ), + .o_SW (SW ), + .o_SW2 (SW2 ), + .o_SW3 (SW3 ), + .o_SW_C1 (SW_C1 ), + .o_T_MGC_1dB (TMGC_1db ), + .o_T_MGC_2dB (TMGC_2db ), + .o_T_MGC_4dB (TMGC_4db ), + .o_T_MGC_8dB (TMGC_8db ), + .o_T_MGC_16dB (TMGC_16db ), + .o_R_MGC_1 (R_MGC_1 ) + //.o_R_MGC_2 (R_MGC_2 ), + //.o_R_MGC_3 (R_MGC_3 ), + //.o_R_MGC_4 (R_MGC_4 ) +); + +wire cfgover; +adf4371_a u_adf4371_a ( + .sysclk (clk_40m ), + .arstn (rst_n&vio_rstn ), + .cs (CS1 ), + .mux_out (LD1 ), + .sclk (SCLK1 ), + .sdio (SDIO1 ), + .rf_en (rf_en ), + .SW_PLL (SW_PLL ), + .CAL_F (CAL_F ), + .o_cfgover (cfgover ), + .ceshi_model(ceshi_model ), + .adf4371_hop(adf4371_hop1), + .fre_code (hop_fre_code) + ); + +adf4371_b u_adf4371_b ( + .sysclk (clk_40m ), + .arstn (rst_n&vio_rstn), + .cs (CS2 ), + .mux_out (LD2 ), + .sclk (SCLK2 ), + .sdio (SDIO2 ), + .rf_en (rf_en ), + .SW_PLL (SW_PLL ), + .CAL_F (CAL_F ), + .i_cfgover (cfgover ), + .ceshi_model(ceshi_model ), + .adf4371_hop(adf4371_hop2), + .fre_code (hop_fre_code) + ); + +fre_caliatt u_fre_caliatt ( + .i_clk (clk_40m ), + .i_rstn (rst_n ), + .ENABLE (ENABLE ), + .SC (SC ), + .SD (SD ), + .END_SYN (END_SYN ), + .SDOUT (SDOUT ), + .CAL_F (CAL_F ), + .i_temp (temp ), + .i_fre_mode (current_fre_code ), + .i_cal_fre_code (cal_fre_code ), + // .SYNC_OUT (SYNC_OUT ), + .SW (SW ), + .cal1_mgc (cal1_mgc ), + .cal2_mgc (cal2_mgc ), + .cal3_mgc (cal3_mgc ), + .cal4_mgc (cal4_mgc ), + .tx_cal_mgc (tx_cal_mgc ), + .tx_mgc (tx_mgc ), + .i_ceshi_module (ceshi_model ), + .R_CAL1 (R_CAL1 ), + .R_CAL2 (R_CAL2 ), + .R_CAL3 (R_CAL3 ), + .R_CAL4 (R_CAL4 ), + .T_CAL (T_CAL ) + ); + + +adf4351_2 u_adf4351 ( + .i_sysclk(clk_20m), + .i_arstn(rst_n), + .o_ADF4351_SCK(SCLK3), + .o_ADF4351_DATA(SDIO3), + .o_ADF4351_LE(CS3), + .i_ADF4351_locked(LD3) + ); + + + ds18b20_temp u_temp ( + .clk(clk_40m), + .rstn(rst_n), + .dq(DQ_WD), + .temp_data(temp_data) + ); + + + + + + +assign vio_rstn = 1'b1; + + + + + + + + + + + + endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/T_CAL.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/T_CAL.v new file mode 100644 index 0000000..20e1b52 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/T_CAL.v @@ -0,0 +1,631 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:05:24 04/08/2022 +// Design Name: +// Module Name: T_CAL_ +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module T_CAL( +input i_clk , +input i_rstn , +input SW , +input signed[7:0] i_temp , +input [31:0] hop_fre_mode , +output reg[4:0] T_CAL_ + + ); + + + +//å‘å°„é€šé“ +always@(posedge i_clk,negedge i_rstn)begin//1dB 步进 + if(!i_rstn) + T_CAL_<='d0; + else if(SW==1'b1)//B环校准值 + begin + if(i_temp>=8'sd70)//B环高温校准值 + begin + if(hop_fre_mode<=20414) T_CAL_<= 14 ; + else if(hop_fre_mode<=20454) T_CAL_<= 14 ; + else if(hop_fre_mode<=20494) T_CAL_<= 14 ; + else if(hop_fre_mode<=20534) T_CAL_<= 14 ; + else if(hop_fre_mode<=20574) T_CAL_<= 15 ; + else if(hop_fre_mode<=20614) T_CAL_<= 15 ; + else if(hop_fre_mode<=20654) T_CAL_<= 15 ; + else if(hop_fre_mode<=20694) T_CAL_<= 15 ; + else if(hop_fre_mode<=20734) T_CAL_<= 15 ; + else if(hop_fre_mode<=20774) T_CAL_<= 16 ; + else if(hop_fre_mode<=20814) T_CAL_<= 16 ; + else if(hop_fre_mode<=20854) T_CAL_<= 16 ; + else if(hop_fre_mode<=20894) T_CAL_<= 16 ; + else if(hop_fre_mode<=20934) T_CAL_<= 16 ; + else if(hop_fre_mode<=20974) T_CAL_<= 16 ; + else if(hop_fre_mode<=21014) T_CAL_<= 16 ; + else if(hop_fre_mode<=21054) T_CAL_<= 16 ; + else if(hop_fre_mode<=21094) T_CAL_<= 15 ; + else if(hop_fre_mode<=21134) T_CAL_<= 14 ; + else if(hop_fre_mode<=21174) T_CAL_<= 14 ; + else if(hop_fre_mode<=21214) T_CAL_<= 13 ; + else if(hop_fre_mode<=21254) T_CAL_<= 13 ; + else if(hop_fre_mode<=21294) T_CAL_<= 13 ; + else if(hop_fre_mode<=21334) T_CAL_<= 13 ; + else if(hop_fre_mode<=21374) T_CAL_<= 14 ; + else if(hop_fre_mode<=21414) T_CAL_<= 14 ; + else if(hop_fre_mode<=21454) T_CAL_<= 15 ; + else if(hop_fre_mode<=21494) T_CAL_<= 15 ; + else if(hop_fre_mode<=21534) T_CAL_<= 15 ; + else if(hop_fre_mode<=21574) T_CAL_<= 15 ; + else if(hop_fre_mode<=21614) T_CAL_<= 15 ; + else if(hop_fre_mode<=21654) T_CAL_<= 15 ; + else if(hop_fre_mode<=21694) T_CAL_<= 15 ; + else if(hop_fre_mode<=21734) T_CAL_<= 14 ; + else if(hop_fre_mode<=21774) T_CAL_<= 14 ; + else if(hop_fre_mode<=21814) T_CAL_<= 13 ; + else if(hop_fre_mode<=21854) T_CAL_<= 13 ; + else if(hop_fre_mode<=21875) T_CAL_<= 13 ; + else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894 + else if(hop_fre_mode<=21934) T_CAL_<= 11 ; + else if(hop_fre_mode<=21974) T_CAL_<= 11 ; + else if(hop_fre_mode<=22014) T_CAL_<= 11 ; + else if(hop_fre_mode<=22054) T_CAL_<= 11 ; + else if(hop_fre_mode<=22094) T_CAL_<= 11 ; + else if(hop_fre_mode<=22134) T_CAL_<= 11 ; + else if(hop_fre_mode<=22174) T_CAL_<= 11 ; + else if(hop_fre_mode<=22214) T_CAL_<= 11 ; + else if(hop_fre_mode<=22254) T_CAL_<= 11 ; + else if(hop_fre_mode<=22294) T_CAL_<= 11 ; + else if(hop_fre_mode<=22334) T_CAL_<= 11 ; + else if(hop_fre_mode<=22374) T_CAL_<= 11 ; + else if(hop_fre_mode<=22414) T_CAL_<= 11 ; + else if(hop_fre_mode<=22454) T_CAL_<= 11 ; + else if(hop_fre_mode<=22494) T_CAL_<= 11 ; + else if(hop_fre_mode<=22534) T_CAL_<= 11 ; + else if(hop_fre_mode<=22574) T_CAL_<= 11 ; + else if(hop_fre_mode<=22614) T_CAL_<= 11 ; + else if(hop_fre_mode<=22654) T_CAL_<= 11 ; + else if(hop_fre_mode<=22694) T_CAL_<= 11 ; + else if(hop_fre_mode<=22734) T_CAL_<= 11 ; + else if(hop_fre_mode<=22774) T_CAL_<= 11 ; + else if(hop_fre_mode<=22814) T_CAL_<= 11 ; + else if(hop_fre_mode<=22854) T_CAL_<= 11 ; + else if(hop_fre_mode<=22894) T_CAL_<= 11 ; + else if(hop_fre_mode<=22934) T_CAL_<= 11 ; + else if(hop_fre_mode<=22974) T_CAL_<= 11 ; + else if(hop_fre_mode<=23014) T_CAL_<= 11 ; + else if(hop_fre_mode<=23054) T_CAL_<= 10 ; + else if(hop_fre_mode<=23094) T_CAL_<= 10 ; + else if(hop_fre_mode<=23134) T_CAL_<= 10 ; + else if(hop_fre_mode<=23174) T_CAL_<= 10 ; + else if(hop_fre_mode<=23214) T_CAL_<= 10 ; + else if(hop_fre_mode<=23254) T_CAL_<= 10 ; + else if(hop_fre_mode<=23294) T_CAL_<= 10 ; + else if(hop_fre_mode<=23334) T_CAL_<= 10 ; + else if(hop_fre_mode<=23374) T_CAL_<= 10 ; + else if(hop_fre_mode<=23414) T_CAL_<= 10 ; + else if(hop_fre_mode<=23454) T_CAL_<= 10 ; + else if(hop_fre_mode<=23494) T_CAL_<= 10 ; + else if(hop_fre_mode<=23534) T_CAL_<= 10 ; + else if(hop_fre_mode<=23574) T_CAL_<= 10 ; + else if(hop_fre_mode<=23614) T_CAL_<= 9 ; + else if(hop_fre_mode<=23654) T_CAL_<= 9 ; + else if(hop_fre_mode<=23694) T_CAL_<= 9 ; + else if(hop_fre_mode<=23734) T_CAL_<= 9 ; + else if(hop_fre_mode<=23774) T_CAL_<= 9 ; + else if(hop_fre_mode<=23814) T_CAL_<= 9 ; + else if(hop_fre_mode<=23854) T_CAL_<= 9 ; + else if(hop_fre_mode<=23875) T_CAL_<= 9 ; + end + + else if(i_temp>=8'sd0)//B环常温校准值 + begin + if(hop_fre_mode<=20414) T_CAL_<= 14 ; + else if(hop_fre_mode<=20454) T_CAL_<= 14 ; + else if(hop_fre_mode<=20494) T_CAL_<= 14 ; + else if(hop_fre_mode<=20534) T_CAL_<= 14 ; + else if(hop_fre_mode<=20574) T_CAL_<= 15 ; + else if(hop_fre_mode<=20614) T_CAL_<= 15 ; + else if(hop_fre_mode<=20654) T_CAL_<= 15 ; + else if(hop_fre_mode<=20694) T_CAL_<= 15 ; + else if(hop_fre_mode<=20734) T_CAL_<= 15 ; + else if(hop_fre_mode<=20774) T_CAL_<= 16 ; + else if(hop_fre_mode<=20814) T_CAL_<= 16 ; + else if(hop_fre_mode<=20854) T_CAL_<= 16 ; + else if(hop_fre_mode<=20894) T_CAL_<= 16 ; + else if(hop_fre_mode<=20934) T_CAL_<= 16 ; + else if(hop_fre_mode<=20974) T_CAL_<= 16 ; + else if(hop_fre_mode<=21014) T_CAL_<= 16 ; + else if(hop_fre_mode<=21054) T_CAL_<= 16 ; + else if(hop_fre_mode<=21094) T_CAL_<= 15 ; + else if(hop_fre_mode<=21134) T_CAL_<= 14 ; + else if(hop_fre_mode<=21174) T_CAL_<= 14 ; + else if(hop_fre_mode<=21214) T_CAL_<= 13 ; + else if(hop_fre_mode<=21254) T_CAL_<= 13 ; + else if(hop_fre_mode<=21294) T_CAL_<= 13 ; + else if(hop_fre_mode<=21334) T_CAL_<= 13 ; + else if(hop_fre_mode<=21374) T_CAL_<= 14 ; + else if(hop_fre_mode<=21414) T_CAL_<= 14 ; + else if(hop_fre_mode<=21454) T_CAL_<= 15 ; + else if(hop_fre_mode<=21494) T_CAL_<= 15 ; + else if(hop_fre_mode<=21534) T_CAL_<= 15 ; + else if(hop_fre_mode<=21574) T_CAL_<= 15 ; + else if(hop_fre_mode<=21614) T_CAL_<= 15 ; + else if(hop_fre_mode<=21654) T_CAL_<= 15 ; + else if(hop_fre_mode<=21694) T_CAL_<= 15 ; + else if(hop_fre_mode<=21734) T_CAL_<= 14 ; + else if(hop_fre_mode<=21774) T_CAL_<= 14 ; + else if(hop_fre_mode<=21814) T_CAL_<= 13 ; + else if(hop_fre_mode<=21854) T_CAL_<= 13 ; + else if(hop_fre_mode<=21875) T_CAL_<= 13 ; + else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894 + else if(hop_fre_mode<=21934) T_CAL_<= 11 ; + else if(hop_fre_mode<=21974) T_CAL_<= 11 ; + else if(hop_fre_mode<=22014) T_CAL_<= 11 ; + else if(hop_fre_mode<=22054) T_CAL_<= 11 ; + else if(hop_fre_mode<=22094) T_CAL_<= 11 ; + else if(hop_fre_mode<=22134) T_CAL_<= 11 ; + else if(hop_fre_mode<=22174) T_CAL_<= 11 ; + else if(hop_fre_mode<=22214) T_CAL_<= 11 ; + else if(hop_fre_mode<=22254) T_CAL_<= 11 ; + else if(hop_fre_mode<=22294) T_CAL_<= 11 ; + else if(hop_fre_mode<=22334) T_CAL_<= 11 ; + else if(hop_fre_mode<=22374) T_CAL_<= 11 ; + else if(hop_fre_mode<=22414) T_CAL_<= 11 ; + else if(hop_fre_mode<=22454) T_CAL_<= 11 ; + else if(hop_fre_mode<=22494) T_CAL_<= 11 ; + else if(hop_fre_mode<=22534) T_CAL_<= 11 ; + else if(hop_fre_mode<=22574) T_CAL_<= 11 ; + else if(hop_fre_mode<=22614) T_CAL_<= 11 ; + else if(hop_fre_mode<=22654) T_CAL_<= 11 ; + else if(hop_fre_mode<=22694) T_CAL_<= 11 ; + else if(hop_fre_mode<=22734) T_CAL_<= 11 ; + else if(hop_fre_mode<=22774) T_CAL_<= 11 ; + else if(hop_fre_mode<=22814) T_CAL_<= 11 ; + else if(hop_fre_mode<=22854) T_CAL_<= 11 ; + else if(hop_fre_mode<=22894) T_CAL_<= 11 ; + else if(hop_fre_mode<=22934) T_CAL_<= 11 ; + else if(hop_fre_mode<=22974) T_CAL_<= 11 ; + else if(hop_fre_mode<=23014) T_CAL_<= 11 ; + else if(hop_fre_mode<=23054) T_CAL_<= 10 ; + else if(hop_fre_mode<=23094) T_CAL_<= 10 ; + else if(hop_fre_mode<=23134) T_CAL_<= 10 ; + else if(hop_fre_mode<=23174) T_CAL_<= 10 ; + else if(hop_fre_mode<=23214) T_CAL_<= 10 ; + else if(hop_fre_mode<=23254) T_CAL_<= 10 ; + else if(hop_fre_mode<=23294) T_CAL_<= 10 ; + else if(hop_fre_mode<=23334) T_CAL_<= 10 ; + else if(hop_fre_mode<=23374) T_CAL_<= 10 ; + else if(hop_fre_mode<=23414) T_CAL_<= 10 ; + else if(hop_fre_mode<=23454) T_CAL_<= 10 ; + else if(hop_fre_mode<=23494) T_CAL_<= 10 ; + else if(hop_fre_mode<=23534) T_CAL_<= 10 ; + else if(hop_fre_mode<=23574) T_CAL_<= 10 ; + else if(hop_fre_mode<=23614) T_CAL_<= 9 ; + else if(hop_fre_mode<=23654) T_CAL_<= 9 ; + else if(hop_fre_mode<=23694) T_CAL_<= 9 ; + else if(hop_fre_mode<=23734) T_CAL_<= 9 ; + else if(hop_fre_mode<=23774) T_CAL_<= 9 ; + else if(hop_fre_mode<=23814) T_CAL_<= 9 ; + else if(hop_fre_mode<=23854) T_CAL_<= 9 ; + else if(hop_fre_mode<=23875) T_CAL_<= 9 ; + end + + else //B环低温校准值 + begin + if(hop_fre_mode<=20414) T_CAL_<= 14 ; + else if(hop_fre_mode<=20454) T_CAL_<= 14 ; + else if(hop_fre_mode<=20494) T_CAL_<= 14 ; + else if(hop_fre_mode<=20534) T_CAL_<= 14 ; + else if(hop_fre_mode<=20574) T_CAL_<= 15 ; + else if(hop_fre_mode<=20614) T_CAL_<= 15 ; + else if(hop_fre_mode<=20654) T_CAL_<= 15 ; + else if(hop_fre_mode<=20694) T_CAL_<= 15 ; + else if(hop_fre_mode<=20734) T_CAL_<= 15 ; + else if(hop_fre_mode<=20774) T_CAL_<= 16 ; + else if(hop_fre_mode<=20814) T_CAL_<= 16 ; + else if(hop_fre_mode<=20854) T_CAL_<= 16 ; + else if(hop_fre_mode<=20894) T_CAL_<= 16 ; + else if(hop_fre_mode<=20934) T_CAL_<= 16 ; + else if(hop_fre_mode<=20974) T_CAL_<= 16 ; + else if(hop_fre_mode<=21014) T_CAL_<= 16 ; + else if(hop_fre_mode<=21054) T_CAL_<= 16 ; + else if(hop_fre_mode<=21094) T_CAL_<= 15 ; + else if(hop_fre_mode<=21134) T_CAL_<= 14 ; + else if(hop_fre_mode<=21174) T_CAL_<= 14 ; + else if(hop_fre_mode<=21214) T_CAL_<= 13 ; + else if(hop_fre_mode<=21254) T_CAL_<= 13 ; + else if(hop_fre_mode<=21294) T_CAL_<= 13 ; + else if(hop_fre_mode<=21334) T_CAL_<= 13 ; + else if(hop_fre_mode<=21374) T_CAL_<= 14 ; + else if(hop_fre_mode<=21414) T_CAL_<= 14 ; + else if(hop_fre_mode<=21454) T_CAL_<= 15 ; + else if(hop_fre_mode<=21494) T_CAL_<= 15 ; + else if(hop_fre_mode<=21534) T_CAL_<= 15 ; + else if(hop_fre_mode<=21574) T_CAL_<= 15 ; + else if(hop_fre_mode<=21614) T_CAL_<= 15 ; + else if(hop_fre_mode<=21654) T_CAL_<= 15 ; + else if(hop_fre_mode<=21694) T_CAL_<= 15 ; + else if(hop_fre_mode<=21734) T_CAL_<= 14 ; + else if(hop_fre_mode<=21774) T_CAL_<= 14 ; + else if(hop_fre_mode<=21814) T_CAL_<= 13 ; + else if(hop_fre_mode<=21854) T_CAL_<= 13 ; + else if(hop_fre_mode<=21875) T_CAL_<= 13 ; + else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894 + else if(hop_fre_mode<=21934) T_CAL_<= 11 ; + else if(hop_fre_mode<=21974) T_CAL_<= 11 ; + else if(hop_fre_mode<=22014) T_CAL_<= 11 ; + else if(hop_fre_mode<=22054) T_CAL_<= 11 ; + else if(hop_fre_mode<=22094) T_CAL_<= 11 ; + else if(hop_fre_mode<=22134) T_CAL_<= 11 ; + else if(hop_fre_mode<=22174) T_CAL_<= 11 ; + else if(hop_fre_mode<=22214) T_CAL_<= 11 ; + else if(hop_fre_mode<=22254) T_CAL_<= 11 ; + else if(hop_fre_mode<=22294) T_CAL_<= 11 ; + else if(hop_fre_mode<=22334) T_CAL_<= 11 ; + else if(hop_fre_mode<=22374) T_CAL_<= 11 ; + else if(hop_fre_mode<=22414) T_CAL_<= 11 ; + else if(hop_fre_mode<=22454) T_CAL_<= 11 ; + else if(hop_fre_mode<=22494) T_CAL_<= 11 ; + else if(hop_fre_mode<=22534) T_CAL_<= 11 ; + else if(hop_fre_mode<=22574) T_CAL_<= 11 ; + else if(hop_fre_mode<=22614) T_CAL_<= 11 ; + else if(hop_fre_mode<=22654) T_CAL_<= 11 ; + else if(hop_fre_mode<=22694) T_CAL_<= 11 ; + else if(hop_fre_mode<=22734) T_CAL_<= 11 ; + else if(hop_fre_mode<=22774) T_CAL_<= 11 ; + else if(hop_fre_mode<=22814) T_CAL_<= 11 ; + else if(hop_fre_mode<=22854) T_CAL_<= 11 ; + else if(hop_fre_mode<=22894) T_CAL_<= 11 ; + else if(hop_fre_mode<=22934) T_CAL_<= 11 ; + else if(hop_fre_mode<=22974) T_CAL_<= 11 ; + else if(hop_fre_mode<=23014) T_CAL_<= 11 ; + else if(hop_fre_mode<=23054) T_CAL_<= 10 ; + else if(hop_fre_mode<=23094) T_CAL_<= 10 ; + else if(hop_fre_mode<=23134) T_CAL_<= 10 ; + else if(hop_fre_mode<=23174) T_CAL_<= 10 ; + else if(hop_fre_mode<=23214) T_CAL_<= 10 ; + else if(hop_fre_mode<=23254) T_CAL_<= 10 ; + else if(hop_fre_mode<=23294) T_CAL_<= 10 ; + else if(hop_fre_mode<=23334) T_CAL_<= 10 ; + else if(hop_fre_mode<=23374) T_CAL_<= 10 ; + else if(hop_fre_mode<=23414) T_CAL_<= 10 ; + else if(hop_fre_mode<=23454) T_CAL_<= 10 ; + else if(hop_fre_mode<=23494) T_CAL_<= 10 ; + else if(hop_fre_mode<=23534) T_CAL_<= 10 ; + else if(hop_fre_mode<=23574) T_CAL_<= 10 ; + else if(hop_fre_mode<=23614) T_CAL_<= 9 ; + else if(hop_fre_mode<=23654) T_CAL_<= 9 ; + else if(hop_fre_mode<=23694) T_CAL_<= 9 ; + else if(hop_fre_mode<=23734) T_CAL_<= 9 ; + else if(hop_fre_mode<=23774) T_CAL_<= 9 ; + else if(hop_fre_mode<=23814) T_CAL_<= 9 ; + else if(hop_fre_mode<=23854) T_CAL_<= 9 ; + else if(hop_fre_mode<=23875) T_CAL_<= 9 ; + end + end + else //A环校准值 + begin + if(i_temp>=8'sd70)//A环高温校准值 + begin + if(hop_fre_mode<=20414) T_CAL_<= 14 ; + else if(hop_fre_mode<=20454) T_CAL_<= 14 ; + else if(hop_fre_mode<=20494) T_CAL_<= 14 ; + else if(hop_fre_mode<=20534) T_CAL_<= 14 ; + else if(hop_fre_mode<=20574) T_CAL_<= 15 ; + else if(hop_fre_mode<=20614) T_CAL_<= 15 ; + else if(hop_fre_mode<=20654) T_CAL_<= 15 ; + else if(hop_fre_mode<=20694) T_CAL_<= 15 ; + else if(hop_fre_mode<=20734) T_CAL_<= 15 ; + else if(hop_fre_mode<=20774) T_CAL_<= 16 ; + else if(hop_fre_mode<=20814) T_CAL_<= 16 ; + else if(hop_fre_mode<=20854) T_CAL_<= 16 ; + else if(hop_fre_mode<=20894) T_CAL_<= 16 ; + else if(hop_fre_mode<=20934) T_CAL_<= 16 ; + else if(hop_fre_mode<=20974) T_CAL_<= 16 ; + else if(hop_fre_mode<=21014) T_CAL_<= 16 ; + else if(hop_fre_mode<=21054) T_CAL_<= 16 ; + else if(hop_fre_mode<=21094) T_CAL_<= 15 ; + else if(hop_fre_mode<=21134) T_CAL_<= 14 ; + else if(hop_fre_mode<=21174) T_CAL_<= 14 ; + else if(hop_fre_mode<=21214) T_CAL_<= 13 ; + else if(hop_fre_mode<=21254) T_CAL_<= 13 ; + else if(hop_fre_mode<=21294) T_CAL_<= 13 ; + else if(hop_fre_mode<=21334) T_CAL_<= 13 ; + else if(hop_fre_mode<=21374) T_CAL_<= 14 ; + else if(hop_fre_mode<=21414) T_CAL_<= 14 ; + else if(hop_fre_mode<=21454) T_CAL_<= 15 ; + else if(hop_fre_mode<=21494) T_CAL_<= 15 ; + else if(hop_fre_mode<=21534) T_CAL_<= 15 ; + else if(hop_fre_mode<=21574) T_CAL_<= 15 ; + else if(hop_fre_mode<=21614) T_CAL_<= 15 ; + else if(hop_fre_mode<=21654) T_CAL_<= 15 ; + else if(hop_fre_mode<=21694) T_CAL_<= 15 ; + else if(hop_fre_mode<=21734) T_CAL_<= 14 ; + else if(hop_fre_mode<=21774) T_CAL_<= 14 ; + else if(hop_fre_mode<=21814) T_CAL_<= 13 ; + else if(hop_fre_mode<=21854) T_CAL_<= 13 ; + else if(hop_fre_mode<=21875) T_CAL_<= 13 ; + else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894 + else if(hop_fre_mode<=21934) T_CAL_<= 11 ; + else if(hop_fre_mode<=21974) T_CAL_<= 11 ; + else if(hop_fre_mode<=22014) T_CAL_<= 11 ; + else if(hop_fre_mode<=22054) T_CAL_<= 11 ; + else if(hop_fre_mode<=22094) T_CAL_<= 11 ; + else if(hop_fre_mode<=22134) T_CAL_<= 11 ; + else if(hop_fre_mode<=22174) T_CAL_<= 11 ; + else if(hop_fre_mode<=22214) T_CAL_<= 11 ; + else if(hop_fre_mode<=22254) T_CAL_<= 11 ; + else if(hop_fre_mode<=22294) T_CAL_<= 11 ; + else if(hop_fre_mode<=22334) T_CAL_<= 11 ; + else if(hop_fre_mode<=22374) T_CAL_<= 11 ; + else if(hop_fre_mode<=22414) T_CAL_<= 11 ; + else if(hop_fre_mode<=22454) T_CAL_<= 11 ; + else if(hop_fre_mode<=22494) T_CAL_<= 11 ; + else if(hop_fre_mode<=22534) T_CAL_<= 11 ; + else if(hop_fre_mode<=22574) T_CAL_<= 11 ; + else if(hop_fre_mode<=22614) T_CAL_<= 11 ; + else if(hop_fre_mode<=22654) T_CAL_<= 11 ; + else if(hop_fre_mode<=22694) T_CAL_<= 11 ; + else if(hop_fre_mode<=22734) T_CAL_<= 11 ; + else if(hop_fre_mode<=22774) T_CAL_<= 11 ; + else if(hop_fre_mode<=22814) T_CAL_<= 11 ; + else if(hop_fre_mode<=22854) T_CAL_<= 11 ; + else if(hop_fre_mode<=22894) T_CAL_<= 11 ; + else if(hop_fre_mode<=22934) T_CAL_<= 11 ; + else if(hop_fre_mode<=22974) T_CAL_<= 11 ; + else if(hop_fre_mode<=23014) T_CAL_<= 11 ; + else if(hop_fre_mode<=23054) T_CAL_<= 10 ; + else if(hop_fre_mode<=23094) T_CAL_<= 10 ; + else if(hop_fre_mode<=23134) T_CAL_<= 10 ; + else if(hop_fre_mode<=23174) T_CAL_<= 10 ; + else if(hop_fre_mode<=23214) T_CAL_<= 10 ; + else if(hop_fre_mode<=23254) T_CAL_<= 10 ; + else if(hop_fre_mode<=23294) T_CAL_<= 10 ; + else if(hop_fre_mode<=23334) T_CAL_<= 10 ; + else if(hop_fre_mode<=23374) T_CAL_<= 10 ; + else if(hop_fre_mode<=23414) T_CAL_<= 10 ; + else if(hop_fre_mode<=23454) T_CAL_<= 10 ; + else if(hop_fre_mode<=23494) T_CAL_<= 10 ; + else if(hop_fre_mode<=23534) T_CAL_<= 10 ; + else if(hop_fre_mode<=23574) T_CAL_<= 10 ; + else if(hop_fre_mode<=23614) T_CAL_<= 9 ; + else if(hop_fre_mode<=23654) T_CAL_<= 9 ; + else if(hop_fre_mode<=23694) T_CAL_<= 9 ; + else if(hop_fre_mode<=23734) T_CAL_<= 9 ; + else if(hop_fre_mode<=23774) T_CAL_<= 9 ; + else if(hop_fre_mode<=23814) T_CAL_<= 9 ; + else if(hop_fre_mode<=23854) T_CAL_<= 9 ; + else if(hop_fre_mode<=23875) T_CAL_<= 9 ; + end + + else if(i_temp>=8'sd0)//A环常温校准值 + begin + if(hop_fre_mode<=20414) T_CAL_<= 14 ; //20375 ~ 20414 + else if(hop_fre_mode<=20454) T_CAL_<= 14 ; //20415 ~ 20454 + else if(hop_fre_mode<=20494) T_CAL_<= 14 ; //20455 ~ 20494 + else if(hop_fre_mode<=20534) T_CAL_<= 14 ; //20495 ~ 20534 + else if(hop_fre_mode<=20574) T_CAL_<= 15 ; //20535 ~ 20574 + else if(hop_fre_mode<=20614) T_CAL_<= 15 ; //20575 ~ 20614 + else if(hop_fre_mode<=20654) T_CAL_<= 15 ; //20615 ~ 20654 + else if(hop_fre_mode<=20694) T_CAL_<= 15 ; //20655 ~ 20694 + else if(hop_fre_mode<=20734) T_CAL_<= 15 ; //20695 ~ 20734 + else if(hop_fre_mode<=20774) T_CAL_<= 16 ; //20735 ~ 20774 + else if(hop_fre_mode<=20814) T_CAL_<= 16 ; //20775 ~ 20814 + else if(hop_fre_mode<=20854) T_CAL_<= 16 ; //20815 ~ 20854 + else if(hop_fre_mode<=20894) T_CAL_<= 16 ; //20855 ~ 20894 + else if(hop_fre_mode<=20934) T_CAL_<= 16 ; //20895 ~ 20934 + else if(hop_fre_mode<=20974) T_CAL_<= 16 ; //20935 ~ 20974 + else if(hop_fre_mode<=21014) T_CAL_<= 16 ; //20975 ~ 21014 + else if(hop_fre_mode<=21054) T_CAL_<= 16 ; //21015 ~ 21054 + else if(hop_fre_mode<=21094) T_CAL_<= 15 ; //21055 ~ 21094 + else if(hop_fre_mode<=21134) T_CAL_<= 14 ; //21095 ~ 21134 + else if(hop_fre_mode<=21174) T_CAL_<= 14 ; //21135 ~ 21174 + else if(hop_fre_mode<=21214) T_CAL_<= 13 ; //21175 ~ 21214 + else if(hop_fre_mode<=21254) T_CAL_<= 13 ; //21215 ~ 21254 + else if(hop_fre_mode<=21294) T_CAL_<= 13 ; //21255 ~ 21294 + else if(hop_fre_mode<=21334) T_CAL_<= 13 ; //21295 ~ 21334 + else if(hop_fre_mode<=21374) T_CAL_<= 14 ; //21335 ~ 21374 + else if(hop_fre_mode<=21414) T_CAL_<= 14 ; //21375 ~ 21414 + else if(hop_fre_mode<=21454) T_CAL_<= 15 ; //21415 ~ 21454 + else if(hop_fre_mode<=21494) T_CAL_<= 15 ; //21455 ~ 21494 + else if(hop_fre_mode<=21534) T_CAL_<= 15 ; //21495 ~ 21534 + else if(hop_fre_mode<=21574) T_CAL_<= 15 ; //21535 ~ 21574 + else if(hop_fre_mode<=21614) T_CAL_<= 15 ; //21575 ~ 21614 + else if(hop_fre_mode<=21654) T_CAL_<= 15 ; //21615 ~ 21654 + else if(hop_fre_mode<=21694) T_CAL_<= 15 ; //21655 ~ 21694 + else if(hop_fre_mode<=21734) T_CAL_<= 14 ; //21695 ~ 21734 + else if(hop_fre_mode<=21774) T_CAL_<= 14 ; //21735 ~ 21774 + else if(hop_fre_mode<=21814) T_CAL_<= 13 ; //21775 ~ 21814 + else if(hop_fre_mode<=21854) T_CAL_<= 13 ; //21815 ~ 21854 + else if(hop_fre_mode<=21875) T_CAL_<= 13 ; //21855 ~ 21875 + else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21874 ~ 21894 + else if(hop_fre_mode<=21934) T_CAL_<= 11 ; //21895 ~ 21934 + else if(hop_fre_mode<=21974) T_CAL_<= 11 ; //21935 ~ 21974 + else if(hop_fre_mode<=22014) T_CAL_<= 11 ; //21975 ~ 22014 + else if(hop_fre_mode<=22054) T_CAL_<= 11 ; //22015 ~ 22054 + else if(hop_fre_mode<=22094) T_CAL_<= 11 ; //22055 ~ 22094 + else if(hop_fre_mode<=22134) T_CAL_<= 11 ; //22095 ~ 22134 + else if(hop_fre_mode<=22174) T_CAL_<= 11 ; //22135 ~ 22174 + else if(hop_fre_mode<=22214) T_CAL_<= 11 ; //22175 ~ 22214 + else if(hop_fre_mode<=22254) T_CAL_<= 11 ; //22215 ~ 22254 + else if(hop_fre_mode<=22294) T_CAL_<= 11 ; //22255 ~ 22294 + else if(hop_fre_mode<=22334) T_CAL_<= 11 ; //22295 ~ 22334 + else if(hop_fre_mode<=22374) T_CAL_<= 11 ; //22335 ~ 22374 + else if(hop_fre_mode<=22414) T_CAL_<= 11 ; //22375 ~ 22414 + else if(hop_fre_mode<=22454) T_CAL_<= 11 ; //22415 ~ 22454 + else if(hop_fre_mode<=22494) T_CAL_<= 11 ; //22455 ~ 22494 + else if(hop_fre_mode<=22534) T_CAL_<= 11 ; //22495 ~ 22534 + else if(hop_fre_mode<=22574) T_CAL_<= 11 ; //22535 ~ 22574 + else if(hop_fre_mode<=22614) T_CAL_<= 11 ; //22575 ~ 22614 + else if(hop_fre_mode<=22654) T_CAL_<= 11 ; //22615 ~ 22654 + else if(hop_fre_mode<=22694) T_CAL_<= 11 ; //22655 ~ 22694 + else if(hop_fre_mode<=22734) T_CAL_<= 11 ; //22695 ~ 22734 + else if(hop_fre_mode<=22774) T_CAL_<= 11 ; //22735 ~ 22774 + else if(hop_fre_mode<=22814) T_CAL_<= 11 ; //22775 ~ 22814 + else if(hop_fre_mode<=22854) T_CAL_<= 11 ; //22815 ~ 22854 + else if(hop_fre_mode<=22894) T_CAL_<= 11 ; //22855 ~ 22894 + else if(hop_fre_mode<=22934) T_CAL_<= 11 ; //22895 ~ 22934 + else if(hop_fre_mode<=22974) T_CAL_<= 11 ; //22935 ~ 22974 + else if(hop_fre_mode<=23014) T_CAL_<= 11 ; //22975 ~ 23014 + else if(hop_fre_mode<=23054) T_CAL_<= 10 ; //23015 ~ 23054 + else if(hop_fre_mode<=23094) T_CAL_<= 10 ; //23055 ~ 23094 + else if(hop_fre_mode<=23134) T_CAL_<= 10 ; //23095 ~ 23134 + else if(hop_fre_mode<=23174) T_CAL_<= 10 ; //23135 ~ 23174 + else if(hop_fre_mode<=23214) T_CAL_<= 10 ; //23175 ~ 23214 + else if(hop_fre_mode<=23254) T_CAL_<= 10 ; //23215 ~ 23254 + else if(hop_fre_mode<=23294) T_CAL_<= 10 ; //23255 ~ 23294 + else if(hop_fre_mode<=23334) T_CAL_<= 10 ; //23295 ~ 23334 + else if(hop_fre_mode<=23374) T_CAL_<= 10 ; //23335 ~ 23374 + else if(hop_fre_mode<=23414) T_CAL_<= 10 ; //23375 ~ 23414 + else if(hop_fre_mode<=23454) T_CAL_<= 10 ; //23415 ~ 23454 + else if(hop_fre_mode<=23494) T_CAL_<= 10 ; //23455 ~ 23494 + else if(hop_fre_mode<=23534) T_CAL_<= 10 ; //23495 ~ 23534 + else if(hop_fre_mode<=23574) T_CAL_<= 10 ; //23535 ~ 23574 + else if(hop_fre_mode<=23614) T_CAL_<= 9 ; //23575 ~ 23614 + else if(hop_fre_mode<=23654) T_CAL_<= 9 ; //23615 ~ 23654 + else if(hop_fre_mode<=23694) T_CAL_<= 9 ; //23655 ~ 23694 + else if(hop_fre_mode<=23734) T_CAL_<= 9 ; //23695 ~ 23734 + else if(hop_fre_mode<=23774) T_CAL_<= 9 ; //23735 ~ 23774 + else if(hop_fre_mode<=23814) T_CAL_<= 9 ; //23775 ~ 23814 + else if(hop_fre_mode<=23854) T_CAL_<= 9 ; //23815 ~ 23854 + else if(hop_fre_mode<=23875) T_CAL_<= 9 ; //23855 ~ 23875 + end + else //A环低温校准值 + begin + if(hop_fre_mode<=20414) T_CAL_<= 14 ; + else if(hop_fre_mode<=20454) T_CAL_<= 14 ; + else if(hop_fre_mode<=20494) T_CAL_<= 14 ; + else if(hop_fre_mode<=20534) T_CAL_<= 14 ; + else if(hop_fre_mode<=20574) T_CAL_<= 15 ; + else if(hop_fre_mode<=20614) T_CAL_<= 15 ; + else if(hop_fre_mode<=20654) T_CAL_<= 15 ; + else if(hop_fre_mode<=20694) T_CAL_<= 15 ; + else if(hop_fre_mode<=20734) T_CAL_<= 15 ; + else if(hop_fre_mode<=20774) T_CAL_<= 16 ; + else if(hop_fre_mode<=20814) T_CAL_<= 16 ; + else if(hop_fre_mode<=20854) T_CAL_<= 16 ; + else if(hop_fre_mode<=20894) T_CAL_<= 16 ; + else if(hop_fre_mode<=20934) T_CAL_<= 16 ; + else if(hop_fre_mode<=20974) T_CAL_<= 16 ; + else if(hop_fre_mode<=21014) T_CAL_<= 16 ; + else if(hop_fre_mode<=21054) T_CAL_<= 16 ; + else if(hop_fre_mode<=21094) T_CAL_<= 15 ; + else if(hop_fre_mode<=21134) T_CAL_<= 14 ; + else if(hop_fre_mode<=21174) T_CAL_<= 14 ; + else if(hop_fre_mode<=21214) T_CAL_<= 13 ; + else if(hop_fre_mode<=21254) T_CAL_<= 13 ; + else if(hop_fre_mode<=21294) T_CAL_<= 13 ; + else if(hop_fre_mode<=21334) T_CAL_<= 13 ; + else if(hop_fre_mode<=21374) T_CAL_<= 14 ; + else if(hop_fre_mode<=21414) T_CAL_<= 14 ; + else if(hop_fre_mode<=21454) T_CAL_<= 15 ; + else if(hop_fre_mode<=21494) T_CAL_<= 15 ; + else if(hop_fre_mode<=21534) T_CAL_<= 15 ; + else if(hop_fre_mode<=21574) T_CAL_<= 15 ; + else if(hop_fre_mode<=21614) T_CAL_<= 15 ; + else if(hop_fre_mode<=21654) T_CAL_<= 15 ; + else if(hop_fre_mode<=21694) T_CAL_<= 15 ; + else if(hop_fre_mode<=21734) T_CAL_<= 14 ; + else if(hop_fre_mode<=21774) T_CAL_<= 14 ; + else if(hop_fre_mode<=21814) T_CAL_<= 13 ; + else if(hop_fre_mode<=21854) T_CAL_<= 13 ; + else if(hop_fre_mode<=21875) T_CAL_<= 13 ; + else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894 + else if(hop_fre_mode<=21934) T_CAL_<= 11 ; + else if(hop_fre_mode<=21974) T_CAL_<= 11 ; + else if(hop_fre_mode<=22014) T_CAL_<= 11 ; + else if(hop_fre_mode<=22054) T_CAL_<= 11 ; + else if(hop_fre_mode<=22094) T_CAL_<= 11 ; + else if(hop_fre_mode<=22134) T_CAL_<= 11 ; + else if(hop_fre_mode<=22174) T_CAL_<= 11 ; + else if(hop_fre_mode<=22214) T_CAL_<= 11 ; + else if(hop_fre_mode<=22254) T_CAL_<= 11 ; + else if(hop_fre_mode<=22294) T_CAL_<= 11 ; + else if(hop_fre_mode<=22334) T_CAL_<= 11 ; + else if(hop_fre_mode<=22374) T_CAL_<= 11 ; + else if(hop_fre_mode<=22414) T_CAL_<= 11 ; + else if(hop_fre_mode<=22454) T_CAL_<= 11 ; + else if(hop_fre_mode<=22494) T_CAL_<= 11 ; + else if(hop_fre_mode<=22534) T_CAL_<= 11 ; + else if(hop_fre_mode<=22574) T_CAL_<= 11 ; + else if(hop_fre_mode<=22614) T_CAL_<= 11 ; + else if(hop_fre_mode<=22654) T_CAL_<= 11 ; + else if(hop_fre_mode<=22694) T_CAL_<= 11 ; + else if(hop_fre_mode<=22734) T_CAL_<= 11 ; + else if(hop_fre_mode<=22774) T_CAL_<= 11 ; + else if(hop_fre_mode<=22814) T_CAL_<= 11 ; + else if(hop_fre_mode<=22854) T_CAL_<= 11 ; + else if(hop_fre_mode<=22894) T_CAL_<= 11 ; + else if(hop_fre_mode<=22934) T_CAL_<= 11 ; + else if(hop_fre_mode<=22974) T_CAL_<= 11 ; + else if(hop_fre_mode<=23014) T_CAL_<= 11 ; + else if(hop_fre_mode<=23054) T_CAL_<= 10 ; + else if(hop_fre_mode<=23094) T_CAL_<= 10 ; + else if(hop_fre_mode<=23134) T_CAL_<= 10 ; + else if(hop_fre_mode<=23174) T_CAL_<= 10 ; + else if(hop_fre_mode<=23214) T_CAL_<= 10 ; + else if(hop_fre_mode<=23254) T_CAL_<= 10 ; + else if(hop_fre_mode<=23294) T_CAL_<= 10 ; + else if(hop_fre_mode<=23334) T_CAL_<= 10 ; + else if(hop_fre_mode<=23374) T_CAL_<= 10 ; + else if(hop_fre_mode<=23414) T_CAL_<= 10 ; + else if(hop_fre_mode<=23454) T_CAL_<= 10 ; + else if(hop_fre_mode<=23494) T_CAL_<= 10 ; + else if(hop_fre_mode<=23534) T_CAL_<= 10 ; + else if(hop_fre_mode<=23574) T_CAL_<= 10 ; + else if(hop_fre_mode<=23614) T_CAL_<= 9 ; + else if(hop_fre_mode<=23654) T_CAL_<= 9 ; + else if(hop_fre_mode<=23694) T_CAL_<= 9 ; + else if(hop_fre_mode<=23734) T_CAL_<= 9 ; + else if(hop_fre_mode<=23774) T_CAL_<= 9 ; + else if(hop_fre_mode<=23814) T_CAL_<= 9 ; + else if(hop_fre_mode<=23854) T_CAL_<= 9 ; + else if(hop_fre_mode<=23875) T_CAL_<= 9 ; + end + end + +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/adf4371_a.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/adf4371_a.v new file mode 100644 index 0000000..dc928a7 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/adf4371_a.v @@ -0,0 +1,633 @@ + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2021/8/13 00:24:20 +// Design Name: +// Module Name: LMX2595 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: + +// fRFOUT= (INT+ (FRAC1+FRAC2/MOD2)/MOD1)× (fPFD/R) +// fPFD = fPFD = REFIN × ((1 + D)/(R × (1 + T))) +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +////////////////////////////////////////////////////////////////////////////////// + + +module adf4371_a(//20.375Ghz ~ 23.875Ghz +input sysclk ,//40MHZ +input arstn , +output cs , +input mux_out , +output sclk , +output sdio , +input [3:0] rf_en , +input SW_PLL , +input CAL_F , +input [3:0] ceshi_model , +input adf4371_hop , +output o_cfgover , +input[11:0] fre_code + ); + +localparam DATA_WIDTH = 24 ; +localparam DATA_LENTH = 72 ; +localparam WAIT_ld = 40000 ; +//***************************************************************************** +reg[7:0] cnt_word = 8'd0 ; +reg csb_reg = 1'b1 ; +reg[5:0] cnt_bits = 6'd0 ; +reg[DATA_WIDTH-1:0] cfgdata = 0, regdata = 0 ; +reg[3:0] state = 4'b000 ; +reg spi_sdo = 1'b0, spi_csb = 1'b1; +wire pll_locked ; +reg cfgover ; +reg[31:0] cnt_lock = 32'd0 ; +reg[31:0] cnt_locked = 32'd0 ; +wire[15:0] band ; +assign o_cfgover =cfgover ; +//----------------------------------- +assign pll_locked = mux_out ; +assign sclk = spi_csb ? 1'b0 : ~sysclk ; +assign cs = spi_csb & csb_reg ; +assign sdio = spi_sdo ; +//----------------------------------- + +wire [7:0] SI_BAND_SEL ; //VCO频段 +wire [7:0] SI_VCO_SEL_BIAS_CODE ; //[7:4]=VCO内核, [3:0]=VCOåç½® +reg[13:0] MOD2 ; +reg[13:0] FRAC2 ; +reg[24:0] FRAC1 ; +reg[15:0] INT ; + +assign SI_BAND_SEL = band[15:8] ; +assign SI_VCO_SEL_BIAS_CODE = band[7:0] ; + +reg[2:0] hop_en ; +reg[15:0] code ; +reg[11:0] pre_fre_code ; +reg[3:0] rf_en_r ; +reg[2:0] CAL_F_R ; + +reg [3:0] R_DIV ; +reg [3:0] D ; +wire[13:0] douta3 ; +wire[13:0] douta4 ; +wire[24:0] douta2 ; +wire[15:0] douta1 ; +//----------------------------------- + +INT_ROMb int_rom ( + .sysclk(sysclk), + .addra(code), + .douta(douta1) + ); + +// Instantiate the module +FRAC1 frac1_rom ( + .clka(sysclk), + .addra(code), + .douta(douta2) + ); + + +// FRAC1_ROM FRAC1_ROM ( +// .clka(sysclk), // input clka +// .addra(code), // input [11 : 0] addra +// .douta(douta2) // output [24 : 0] douta +//); + +frac2_rom frac2_rom ( + .sysclk(sysclk), + .addra(code), + .douta(douta4) + ); + +mod2_rom mod2_rom ( + .sysclk(sysclk), + .addra(code), + .douta(douta3) + ); + + +band_rom_a band_rom_a ( + .sysclk(sysclk), + .addra(code), + .douta(band) // output [15 : 0] douta + ); + + +//-------------------整数边界æ‚散用66.666666Mhz鉴相---------------------------------- +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + INT<=douta1; + else if(code==24 || code==26 ) + INT<=76; + else if(code==424 ) + INT<=77; + else if(code==426 ) + INT<=78; + else if(code==824 || code==826 ) + INT<=79; + else if(code==1224) + INT<=80; + else if(code==1226 ) + INT<=81; + else if(code==1624 || code==1626 ) + INT<=82; + else if(code==2024 ) + INT<=83; + else if(code==2026 ) + INT<=84; + else if(code==2424 || code==2426 ) + INT<=85; + else if(code==2824 ) + INT<=86; + else if( code==2826 ) + INT<=87; + else + INT<=douta1; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + FRAC1<=douta2; + else if(code==24 ) + FRAC1<=16651386; + else if(code==26 ) + FRAC1<=16903045; + else if(code==424 ) + FRAC1<=33428602; + else if(code==426 ) + FRAC1<=125829; + else if(code==824 ) + FRAC1<=16651386; + else if(code==826 ) + FRAC1<=16903045; + else if(code==1224) + FRAC1<=33428602; + else if(code==1226 ) + FRAC1<=125829; + else if(code==1624) + FRAC1<=16651386; + else if(code==1626 ) + FRAC1<=16903045; + else if(code==2024 ) + FRAC1<=33428602; + else if(code==2026 ) + FRAC1<=125829; + else if(code==2424 ) + FRAC1<=16651386; + else if(code==2426 ) + FRAC1<=16903045; + else if(code==2824 ) + FRAC1<=33428602; + else if( code==2826 ) + FRAC1<=125829; + else + FRAC1<=douta2; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + MOD2<=douta3; + else if(code==24 ) + MOD2<=25; + else if(code==26 ) + MOD2<=25; + else if(code==424 ) + MOD2<=25; + else if(code==426 ) + MOD2<=25; + else if(code==824 ) + MOD2<=25; + else if(code==826 ) + MOD2<=25; + else if(code==1224) + MOD2<=25; + else if(code==1226 ) + MOD2<=25; + else if(code==1624) + MOD2<=25; + else if(code==1626 ) + MOD2<=25; + else if(code==2024 ) + MOD2<=25; + else if(code==2026 ) + MOD2<=25; + else if(code==2424 ) + MOD2<=25; + else if(code==2426 ) + MOD2<=25; + else if(code==2824 ) + MOD2<=25; + else if( code==2826 ) + MOD2<=25; + else + MOD2<=douta3; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + FRAC2<=douta4; + else if(code==24 ) + FRAC2<=22; + else if(code==26 ) + FRAC2<=3; + else if(code==424 ) + FRAC2<=22; + else if(code==426 ) + FRAC2<=3; + else if(code==824 ) + FRAC2<=22; + else if(code==826 ) + FRAC2<=3; + else if(code==1224) + FRAC2<=22; + else if(code==1226 ) + FRAC2<=3; + else if(code==1624) + FRAC2<=22; + else if(code==1626 ) + FRAC2<=3; + else if(code==2024 ) + FRAC2<=22; + else if(code==2026 ) + FRAC2<=3; + else if(code==2424 ) + FRAC2<=22; + else if(code==2426 ) + FRAC2<=3; + else if(code==2824 ) + FRAC2<=22; + else if( code==2826 ) + FRAC2<=3; + else + FRAC2<=douta4; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn)begin + R_DIV<=4'b1; + D<=4'b0; + end + else if(code==24 || code==26 || code==424 || code==426 || code==824 || code==826|| code==1224 || code==1226 || code==1624 || code==1626 ||code==2024 || code==2026 ||code==2424 || code==2426 ||code==2824 || code==2826 ) + begin + R_DIV<= 4'd3; + D<=4'd2; + end + else + begin + R_DIV<=4'b1; + D<=4'b0; + end +end + +//---------------------------------------------------------------- + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + pre_fre_code<=11'h6d6; +else if(CAL_F_R==3'b011) + pre_fre_code<=fre_code; +else + pre_fre_code<=pre_fre_code; +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + code<=16'h0; +else if(hop_en==2'b01) + code<=fre_code; +else + code<=code; +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn)begin + hop_en <= 3'b0; + rf_en_r <= 4'b0; + CAL_F_R <= 3'b0; +end +else begin + hop_en <= {hop_en[1:0],adf4371_hop}; + CAL_F_R <= {CAL_F_R[1:0],CAL_F}; + rf_en_r <= rf_en ; +end +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + csb_reg <= 1'b1; +else + csb_reg <= spi_csb; +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + cnt_locked<=32'b0; +else if(cnt_locked==WAIT_ld) + cnt_locked<=32'b0; +else if(!pll_locked) + cnt_locked<=cnt_locked+1'b1; +else + cnt_locked<=32'b0; +end + +always@(posedge sysclk,negedge arstn)begin +if(~arstn)begin + cfgdata <= 0; + cnt_word <= 7'd0; + cnt_bits <= 6'd0; + state <= 4'b0; + cnt_lock <= 32'd0; + spi_csb <= 1'b1; + cfgover <= 1'b0; + spi_sdo <= 1'b0; +end +else begin + case(state) + 4'd0:begin + cnt_word <= 7'd0; + if(rf_en==1'b1) + state <= 4'd0; + else if(cnt_lock >= 32'd4000) + state <= 4'd1; + else + state <= state; + + if(rf_en==1'b0) + cnt_lock <= cnt_lock + 1'b1; + else + cnt_lock<=32'd0; + + end + 4'd1:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + if(rf_en==1'b1) + state <= 4'd0; + else + state <= 4'd2; + end + 4'd2:begin + cfgdata <= regdata; + cnt_bits <= 6'd0; + state <= 4'd3; + end + 4'd3:begin + spi_csb <= 1'b0; + spi_sdo <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + state <= 4'd4; + cnt_word <= cnt_word + 1'b1; + end + cnt_lock <= 32'd0; + end + 4'd4:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + cnt_lock <= 32'd0; + cnt_bits <= 32'd0; + if(cnt_word == DATA_LENTH)begin + state <= 4'd5; + end + else + state <= 4'd1; + end + 4'd5:begin + if(cnt_lock>=40000 || pll_locked)begin + cnt_lock <= 32'd0 ; + state <= 4'd6 ; + end + else begin + cnt_lock <=cnt_lock+1'b1; + state <= state ; + end + end + 4'd6:begin + cnt_word <= 7'd0; + if(pll_locked) + state <= 4'd7 ; + else + state <= 4'b1 ; + end +//---------------------------------------------------------------- + 4'd7:begin//IDLE + cnt_word <= DATA_LENTH; + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + cnt_bits <= 6'd0; + cfgover <= 1'b0; + if(rf_en==4'b1) + state <= state; + else if(rf_en==4'b0 && rf_en_r==4'b1 ) + state <= 4'd0; + else if(hop_en==2'b10 || cnt_locked==WAIT_ld ) + state <= 4'd8; + else if(CAL_F_R==3'b011 && (pre_fre_code!=fre_code))//打开RF_OUT + state <= 4'd12; + else + state <= state; + end + 4'd8:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + state <= 4'd9; + end + 4'd9:begin + cfgdata <= regdata; + cnt_bits <= 6'd0; + state <= 4'd10; + end + 4'd10:begin + spi_csb <= 1'b0; + spi_sdo <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + state <= 4'd11; + cnt_word <= cnt_word + 1'b1; + end + end + 4'd11:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + cnt_lock <= 32'd0; + cnt_bits <= 32'd0; + if(cnt_word == 8'd85)begin + state <= 4'd7; + end + else + state <= 4'd8; + end + 4'd12:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + state <= 4'd13; + end + 4'd13:begin + cnt_bits <= 6'd0; + state <= 4'd14; + if(ceshi_model==4'ha) + cfgdata<={16'h0025,8'h13}; + else if(ceshi_model==4'hb) + cfgdata<={16'h0025,8'h00}; + else if(SW_PLL) + cfgdata<={16'h0025,8'h13}; + else + cfgdata<={16'h0025,8'h00}; + end + 4'd14:begin + spi_csb <= 1'b0; + spi_sdo <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + state <= 4'd7; + cfgover <= 1'b1; + cnt_word <= cnt_word ; + end + end + +//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#// + default: begin + spi_csb <= 1'b1; + state <= 4'd0; + cnt_lock <= 32'd0; + cnt_word <= 8'd0; + end + endcase +end +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + regdata <= {16'h0000,8'h18 }; + else case(cnt_word) + 8'd0 : regdata <= {16'h0000,8'h18 }; + 8'd1 : regdata <= {16'h0001,8'h00 }; + 8'd2 : regdata <= {16'h0003,8'h00 }; + 8'd3 : regdata <= {16'h0004,8'h00 }; + 8'd4 : regdata <= {16'h0005,8'h00 }; + 8'd5 : regdata <= {16'h0006,8'hFF }; + 8'd6 : regdata <= {16'h000C,8'h00 }; + 8'd7 : regdata <= {16'h000D,8'h00 }; + 8'd8 : regdata <= {16'h0010 ,INT[7:0] } ; + 8'd9 : regdata <= {16'h0011 ,INT[15:8] } ; + 8'd10 : regdata <= {16'h0012,8'h00 };//[6]No Autocalibration + //8'd10 : regdata <= {16'h0012,8'h40 };//[6]Autocalibration + 8'd11 : regdata <= {16'h0014 ,FRAC1[7:0]} ; + 8'd12 : regdata <= {16'h0015 ,FRAC1[15:8]} ; + 8'd13 : regdata <= {16'h0016 ,FRAC1[23:16]} ; + 8'd14 : regdata <= {16'h0017 ,FRAC2[6:0],FRAC1[24]} ; + 8'd15 : regdata <= {16'h0018 ,1'b0,FRAC2[13:7] } ; + 8'd16 : regdata <= {16'h0019 ,MOD2[7:0]} ; + 8'd17 : regdata <= {16'h001A ,2'b0,MOD2[13:8]} ; + 8'd18 : regdata <= {16'h001B,8'h00 }; + 8'd19 : regdata <= {16'h001C,8'h00 }; + 8'd20 : regdata <= {16'h001D,8'h00 }; + 8'd21 : regdata <= {16'h001E,8'h18 };//CP_CURRENT 电è·æ³µ + // 8'd21 : regdata <= { 16'h001E,cp,4'h8 };//CP_CURRENT 电è·æ³µ + 8'd22 : regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器 + 8'd23 : regdata <= {16'h0020,8'h1c };//digital lock detect æ•°å­—é”定ld + 8'd24 : regdata <= {16'h0021,8'h00 }; + 8'd25 : regdata <= {16'h0022,D,4'd0 };//[4]2分频 [5]double 2å€é¢‘器 + 8'd26 : regdata <= {16'h0023,8'h00 }; + 8'd27 : regdata <= {16'h0024,8'h80 };//Fout_clk DIV_SEL + 8'd28 : regdata <= {16'h0025,8'h13 };//X4_EN + 8'd29 : regdata <= {16'h0026,8'h1F }; + 8'd30 : regdata <= {16'h0027,8'hCD }; + //8'd30 : regdata <= {16'h0027,8'hCD }; + 8'd31 : regdata <= {16'h0028,8'h83 }; + 8'd32 : regdata <= {16'h002A,8'h00 }; + 8'd33 : regdata <= {16'h002B,8'h00 }; + 8'd34 : regdata <= {16'h002C,8'h44 }; + 8'd35 : regdata <= {16'h002D,8'h11 }; + 8'd36 : regdata <= {16'h002E,8'h12 }; + 8'd37 : regdata <= {16'h002F,8'h94 }; + 8'd38 : regdata <= {16'h0030,8'h2A }; + 8'd39 : regdata <= {16'h0031,8'h02 }; + 8'd40 : regdata <= {16'h0032,8'h04 }; + 8'd41 : regdata <= {16'h0033,8'h22 }; + 8'd42 : regdata <= {16'h0034,8'h25 }; + 8'd43 : regdata <= {16'h0035,8'hFA }; + 8'd44 : regdata <= {16'h0036,8'h30 }; + 8'd45 : regdata <= {16'h0037,SI_BAND_SEL} ;//VCO频段 + 8'd46 : regdata <= {16'h0038,SI_VCO_SEL_BIAS_CODE };//[7:4]=VCO内核,[3:0]VCOåç½® + 8'd47 : regdata <= {16'h0039,8'h07 }; + 8'd48 : regdata <= {16'h003A,8'h55 }; + 8'd49 : regdata <= {16'h003D,8'h00 }; + 8'd50 : regdata <= {16'h003E,8'h0C }; + 8'd51 : regdata <= {16'h003F,8'h80 }; + 8'd52 : regdata <= {16'h0040,8'h50 }; + 8'd53 : regdata <= {16'h0041,8'h28 }; + 8'd54 : regdata <= {16'h0042,8'h00 }; + 8'd55 : regdata <= {16'h0043,8'h00 }; + 8'd56 : regdata <= {16'h0044,8'h00 }; + 8'd57 : regdata <= {16'h0045,8'h00 }; + 8'd58 : regdata <= {16'h0046,8'h00 }; + 8'd59 : regdata <= {16'h0047,8'hC0 }; + 8'd60 : regdata <= {16'h0052,8'hF4 }; + 8'd61 : regdata <= {16'h006C,8'h00 }; + 8'd62 : regdata <= {16'h006E,8'h00 }; + 8'd63 : regdata <= {16'h006F,8'h00 }; + 8'd64 : regdata <= {16'h0070,8'hE3 }; + 8'd65 : regdata <= {16'h0071,8'h60 }; + 8'd66 : regdata <= {16'h0072,8'h32 }; + 8'd67 : regdata <= {16'h0073,8'h00 }; + 8'd68 : regdata <= {16'h0079,8'h00 }; + 8'd69 : regdata <= {16'h007A,8'h00 }; + 8'd70 : regdata <= {16'h007B,8'h00 }; + 8'd71 : regdata <= {16'h007C,8'h00 }; + + //跳频 + 8'd72:regdata <= { 16'h0022,D,4'd0 };//double Då€é¢‘器 + 8'd73:regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器 + 8'd74:regdata <= { 16'h001A ,2'b0,MOD2[13:8] } ; + 8'd75:regdata <= { 16'h0019 ,MOD2[7:0] } ; + 8'd76:regdata <= { 16'h0018 ,1'b0,FRAC2[13:7] } ; + 8'd77:regdata <= { 16'h0017 ,FRAC2[6:0],FRAC1[24] } ; + 8'd78:regdata <= { 16'h0016 ,FRAC1[23:16] } ; + 8'd79:regdata <= { 16'h0015 ,FRAC1[15:8] } ; + 8'd80:regdata <= { 16'h0014 ,FRAC1[7:0] } ; + 8'd81:regdata <= { 16'h0037 ,SI_BAND_SEL } ; + 8'd82:regdata <= { 16'h0038 ,SI_VCO_SEL_BIAS_CODE } ; + 8'd83:regdata <= { 16'h0011 ,INT[15:8] } ; + 8'd84:regdata <= { 16'h0010 ,INT[7:0] } ; + + default: regdata <= regdata; +endcase +end + + + + + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/adf4371_b.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/adf4371_b.v new file mode 100644 index 0000000..7708440 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/adf4371_b.v @@ -0,0 +1,622 @@ + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2021/8/13 00:24:20 +// Design Name: +// Module Name: LMX2595 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: + +// fRFOUT= (INT+ (FRAC1+FRAC2/MOD2)/MOD1)× (fPFD/R) +// fPFD = fPFD = REFIN × ((1 + D)/(R × (1 + T))) +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +////////////////////////////////////////////////////////////////////////////////// + + +module adf4371_b(//20.375Ghz ~ 23.875Ghz +input sysclk ,//40MHZ +input arstn , +output cs , +input mux_out , +output sclk , +output sdio , +input [3:0] rf_en , +input CAL_F , +input SW_PLL , +input i_cfgover , +input [3:0] ceshi_model , +input adf4371_hop , +input[11:0] fre_code + ); + +localparam DATA_WIDTH = 24 ; +localparam DATA_LENTH = 72 ; +localparam WAIT_ld = 40000 ; +//***********************************************************************************************************// +reg[7:0] cnt_word = 8'd0 ; +reg csb_reg = 1'b1 ; +reg[5:0] cnt_bits = 6'd0 ; +reg[DATA_WIDTH-1:0] cfgdata = 0, regdata = 0 ; +reg[3:0] state = 4'b000 ; +reg spi_sdo = 1'b0, spi_csb = 1'b1; +wire pll_locked ; +reg[31:0] cnt_lock = 32'd0 ; +reg[31:0] cnt_locked = 32'd0 ; +wire[15:0] band ; + +//----------------------------------- +assign pll_locked = mux_out ; +assign sclk = spi_csb ? 1'b0 : ~sysclk ; +assign cs = spi_csb & csb_reg ; +assign sdio = spi_sdo ; +//----------------------------------- + +wire [7:0] SI_BAND_SEL ; //VCO频段 +wire [7:0] SI_VCO_SEL_BIAS_CODE ; //[7:4]=VCO内核, [3:0]=VCOåç½® +reg[13:0] MOD2 ; +reg[13:0] FRAC2 ; +reg[24:0] FRAC1 ; +reg[15:0] INT ; + +assign SI_BAND_SEL = band[15:8] ; +assign SI_VCO_SEL_BIAS_CODE = band[7:0] ; + +reg[2:0] hop_en; +reg[15:0] code; +reg[11:0] pre_fre_code; +reg[3:0] cp_r; +reg[3:0] rf_en_r; +reg[2:0] CAL_F_R; + +reg [3:0] R_DIV ; +reg [3:0] D ; +wire[13:0] douta3 ; +wire[13:0] douta4 ; +wire[24:0] douta2 ; +wire[15:0] douta1 ; + +//----------------------------------- +INT_ROMb int_rom ( + .sysclk(sysclk), + .addra(code), + .douta(douta1) + ); + +FRAC1 frac1_rom ( + .clka(sysclk), + .addra(code), + .douta(douta2) + ); + +// FRAC1_ROM FRAC1_ROM ( +// .clka(sysclk), // input clka +// .addra(code), // input [11 : 0] addra +// .douta(douta2) // output [24 : 0] douta +//); + +frac2_rom frac2_rom ( + .sysclk(sysclk), + .addra(code), + .douta(douta4) + ); + +mod2_rom mod2_rom ( + .sysclk(sysclk), + .addra(code), + .douta(douta3) + ); + + +band_rom_b band_rom_b ( + .sysclk(sysclk), + .addra(code), + .douta(band) // output [15 : 0] douta + ); + +//-------------------整数边界æ‚散用66.666666Mhz鉴相---------------------------------- + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + INT<=douta1; + else if(code==24 || code==26 ) + INT<=76; + else if(code==424 ) + INT<=77; + else if(code==426 ) + INT<=78; + else if(code==824 || code==826 ) + INT<=79; + else if(code==1224) + INT<=80; + else if(code==1226 ) + INT<=81; + else if(code==1624 || code==1626 ) + INT<=82; + else if(code==2024 ) + INT<=83; + else if(code==2026 ) + INT<=84; + else if(code==2424 || code==2426 ) + INT<=85; + else if(code==2824 ) + INT<=86; + else if( code==2826 ) + INT<=87; + else + INT<=douta1; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + FRAC1<=douta2; + else if(code==24 ) + FRAC1<=16651386; + else if(code==26 ) + FRAC1<=16903045; + else if(code==424 ) + FRAC1<=33428602; + else if(code==426 ) + FRAC1<=125829; + else if(code==824 ) + FRAC1<=16651386; + else if(code==826 ) + FRAC1<=16903045; + else if(code==1224) + FRAC1<=33428602; + else if(code==1226 ) + FRAC1<=125829; + else if(code==1624) + FRAC1<=16651386; + else if(code==1626 ) + FRAC1<=16903045; + else if(code==2024 ) + FRAC1<=33428602; + else if(code==2026 ) + FRAC1<=125829; + else if(code==2424 ) + FRAC1<=16651386; + else if(code==2426 ) + FRAC1<=16903045; + else if(code==2824 ) + FRAC1<=33428602; + else if( code==2826 ) + FRAC1<=125829; + else + FRAC1<=douta2; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + MOD2<=douta3; + else if(code==24 ) + MOD2<=25; + else if(code==26 ) + MOD2<=25; + else if(code==424 ) + MOD2<=25; + else if(code==426 ) + MOD2<=25; + else if(code==824 ) + MOD2<=25; + else if(code==826 ) + MOD2<=25; + else if(code==1224) + MOD2<=25; + else if(code==1226 ) + MOD2<=25; + else if(code==1624) + MOD2<=25; + else if(code==1626 ) + MOD2<=25; + else if(code==2024 ) + MOD2<=25; + else if(code==2026 ) + MOD2<=25; + else if(code==2424 ) + MOD2<=25; + else if(code==2426 ) + MOD2<=25; + else if(code==2824 ) + MOD2<=25; + else if( code==2826 ) + MOD2<=25; + else + MOD2<=douta3; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + FRAC2<=douta4; + else if(code==24 ) + FRAC2<=22; + else if(code==26 ) + FRAC2<=3; + else if(code==424 ) + FRAC2<=22; + else if(code==426 ) + FRAC2<=3; + else if(code==824 ) + FRAC2<=22; + else if(code==826 ) + FRAC2<=3; + else if(code==1224) + FRAC2<=22; + else if(code==1226 ) + FRAC2<=3; + else if(code==1624) + FRAC2<=22; + else if(code==1626 ) + FRAC2<=3; + else if(code==2024 ) + FRAC2<=22; + else if(code==2026 ) + FRAC2<=3; + else if(code==2424 ) + FRAC2<=22; + else if(code==2426 ) + FRAC2<=3; + else if(code==2824 ) + FRAC2<=22; + else if( code==2826 ) + FRAC2<=3; + else + FRAC2<=douta4; +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn)begin + R_DIV<=4'b1; + D<=4'b0; + end + else if(code==24 || code==26 || code==424 || code==426 || code==824 || code==826|| code==1224 || code==1226 || code==1624 || code==1626 ||code==2024 || code==2026 ||code==2424 || code==2426 ||code==2824 || code==2826 ) + begin + R_DIV<= 4'd3; + D<=4'd2; + end + else + begin + R_DIV<=4'b1; + D<=4'b0; + end +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + pre_fre_code<=11'h6d6; +else if(CAL_F_R==3'b011) + pre_fre_code<=fre_code; +else + pre_fre_code<=pre_fre_code; +end + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + code<=16'h6d6; +else if(hop_en==2'b01) + code<=fre_code; +else + code<=code; +end + +always@(posedge sysclk,negedge arstn)begin +if(~arstn)begin + hop_en <= 3'b0; + CAL_F_R <= 3'b0; + rf_en_r <= 4'b0; +end +else begin + hop_en <= {hop_en[1:0],adf4371_hop}; + CAL_F_R <= {CAL_F_R[1:0],CAL_F}; + rf_en_r <= rf_en ; +end +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + csb_reg <= 1'b1; +else + csb_reg <= spi_csb; +end + + +always@(posedge sysclk,negedge arstn)begin +if(~arstn) + cnt_locked<=32'b0; +else if(cnt_locked==WAIT_ld) + cnt_locked<=32'b0; +else if(!pll_locked) + cnt_locked<=cnt_locked+1'b1; +else + cnt_locked<=32'b0; +end + +always@(posedge sysclk,negedge arstn)begin +if(~arstn)begin + cfgdata <= 0; + cnt_word <= 7'd0; + cnt_bits <= 6'd0; + state <= 4'b0; + cnt_lock <= 32'd0; + spi_csb <= 1'b1; + spi_sdo <= 1'b0; +end +else begin + case(state) + 4'd0:begin + cnt_word <= 7'd0; + if(rf_en==1'b1) + state <= 4'd0; + else if(cnt_lock >= 32'd6000) + state <= 4'd1; + else + state <= state; + + if(rf_en==1'b0) + cnt_lock <= cnt_lock + 1'b1; + else + cnt_lock<=32'd0; + + end + 4'd1:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + state <= 4'd2; + end + 4'd2:begin + cfgdata <= regdata; + cnt_bits <= 6'd0; + state <= 4'd3; + end + 4'd3:begin + spi_csb <= 1'b0; + spi_sdo <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + state <= 4'd4; + cnt_word <= cnt_word + 1'b1; + end + cnt_lock <= 32'd0; + end + 4'd4:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + cnt_lock <= 32'd0; + cnt_bits <= 32'd0; + if(cnt_word == DATA_LENTH)begin + state <= 4'd5; + end + else + state <= 4'd1; + end + 4'd5:begin + if(cnt_lock>=40000 || pll_locked)begin + cnt_lock <= 32'd0 ; + state <= 4'd6 ; + end + else begin + cnt_lock <=cnt_lock+1'b1; + state <= state ; + end + end + 4'd6:begin + cnt_word <= 7'd0; + if(pll_locked) + state <= 4'd7 ; + else + state <= 4'b1 ; + end +//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#// + 4'd7:begin//IDLE + cnt_word <= DATA_LENTH; + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + cnt_bits <= 6'd0; + if(rf_en==4'b1) + state <= state; + else if(rf_en==4'b0 && rf_en_r==4'b1 ) + state <= 4'd0; + else if(hop_en==2'b10 || cnt_locked==WAIT_ld ) + state <= 4'd8; + //else if(CAL_F_R==3'b011 && (pre_fre_code!=fre_code))//打开RF_OUT + else if(i_cfgover) + state <= 4'd12; + else + state <= state; + end + 4'd8:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + state <= 4'd9; + end + 4'd9:begin + cfgdata <= regdata; + cnt_bits <= 6'd0; + state <= 4'd10; + end + 4'd10:begin + spi_csb <= 1'b0; + spi_sdo <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + state <= 4'd11; + cnt_word <= cnt_word + 1'b1; + end + end + 4'd11:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + cnt_lock <= 32'd0; + cnt_bits <= 32'd0; + if(cnt_word == 8'd85)begin + state <= 4'd7; + end + else + state <= 4'd8; + end + 4'd12:begin + spi_csb <= 1'b1; + spi_sdo <= 1'b0; + state <= 4'd13; + end + 4'd13:begin + cnt_bits <= 6'd0; + state <= 4'd14; + if(ceshi_model==4'hb) + cfgdata <= {16'h0025,8'h13}; + else if(ceshi_model==4'ha) + cfgdata <= {16'h0025,8'h00}; + else if (SW_PLL) + cfgdata <= {16'h0025,8'h00}; + else + cfgdata <= {16'h0025,8'h13}; + end + 4'd14:begin + spi_csb <= 1'b0; + spi_sdo <= cfgdata[DATA_WIDTH-1]; + cfgdata <= cfgdata << 1'b1; + cnt_bits <= cnt_bits + 1'b1; + if(cnt_bits == DATA_WIDTH-1)begin + state <= 4'd7; + cnt_word <= cnt_word ; + end + end +//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#// + default: begin + spi_csb <= 1'b1; + state <= 4'd0; + cnt_lock <= 32'd0; + cnt_word <= 8'd0; + end + endcase +end +end + +always@(posedge sysclk,negedge arstn) +begin + if(!arstn) + regdata <= {16'h0000,8'h18 }; + else case(cnt_word) + 8'd0 : regdata <= {16'h0000,8'h18 }; + 8'd1 : regdata <= {16'h0001,8'h00 }; + 8'd2 : regdata <= {16'h0003,8'h00 }; + 8'd3 : regdata <= {16'h0004,8'h00 }; + 8'd4 : regdata <= {16'h0005,8'h00 }; + 8'd5 : regdata <= {16'h0006,8'hFF }; + 8'd6 : regdata <= {16'h000C,8'h00 }; + 8'd7 : regdata <= {16'h000D,8'h00 }; + 8'd8 : regdata <= {16'h0010 ,INT[7:0] } ; + 8'd9 : regdata <= {16'h0011 ,INT[15:8] } ; + 8'd10 : regdata <= {16'h0012,8'h00 };//[6]Autocalibration + //8'd10 : regdata <= {16'h0012,8'h40 };//[6]Autocalibration + 8'd11 : regdata <= {16'h0014 ,FRAC1[7:0]} ; + 8'd12 : regdata <= {16'h0015 ,FRAC1[15:8]} ; + 8'd13 : regdata <= {16'h0016 ,FRAC1[23:16]} ; + 8'd14 : regdata <= {16'h0017 ,FRAC2[6:0],FRAC1[24]} ; + 8'd15 : regdata <= {16'h0018 ,1'b0,FRAC2[13:7] } ; + 8'd16 : regdata <= {16'h0019 ,MOD2[7:0]} ; + 8'd17 : regdata <= {16'h001A ,2'b0,MOD2[13:8]} ; + 8'd18 : regdata <= {16'h001B,8'h00 }; + 8'd19 : regdata <= {16'h001C,8'h00 }; + 8'd20 : regdata <= {16'h001D,8'h00 }; + 8'd21 : regdata <= {16'h001E,8'h18 };//CP_CURRENT 电è·æ³µ + //8'd21 : regdata <= {16'h001E,cp,4'h8 };//CP_CURRENT 电è·æ³µ + 8'd22 : regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器 + 8'd23 : regdata <= {16'h0020,8'h1c };//digital lock detect æ•°å­—é”定ld + 8'd24 : regdata <= {16'h0021,8'h00 }; + 8'd25 : regdata <= { 16'h0022,D,4'd0 };//double Då€é¢‘器 + 8'd26 : regdata <= {16'h0023,8'h00 }; + 8'd27 : regdata <= {16'h0024,8'h80 };//DIV_SEL + 8'd28 : regdata <= {16'h0025,8'h13 };//X4_EN + 8'd29 : regdata <= {16'h0026,8'h1F }; + 8'd30 : regdata <= {16'h0027,8'hCD }; + //8'd30 : regdata <= {16'h0027,8'hCD }; + 8'd31 : regdata <= {16'h0028,8'h83 }; + 8'd32 : regdata <= {16'h002A,8'h00 }; + 8'd33 : regdata <= {16'h002B,8'h00 }; + 8'd34 : regdata <= {16'h002C,8'h44 }; + 8'd35 : regdata <= {16'h002D,8'h11 }; + 8'd36 : regdata <= {16'h002E,8'h12 }; + 8'd37 : regdata <= {16'h002F,8'h94 }; + 8'd38 : regdata <= {16'h0030,8'h2A }; + 8'd39 : regdata <= {16'h0031,8'h02 }; + 8'd40 : regdata <= {16'h0032,8'h04 }; + 8'd41 : regdata <= {16'h0033,8'h22 }; + 8'd42 : regdata <= {16'h0034,8'h25 }; + 8'd43 : regdata <= {16'h0035,8'hFA }; + 8'd44 : regdata <= {16'h0036,8'h30 }; + 8'd45 : regdata <= {16'h0037,SI_BAND_SEL} ;//VCO频段 + 8'd46 : regdata <= {16'h0038,SI_VCO_SEL_BIAS_CODE };//[7:4]=VCO内核,[3:0]VCOåç½® + 8'd47 : regdata <= {16'h0039,8'h07 }; + 8'd48 : regdata <= {16'h003A,8'h55 }; + 8'd49 : regdata <= {16'h003D,8'h00 }; + 8'd50 : regdata <= {16'h003E,8'h0C }; + 8'd51 : regdata <= {16'h003F,8'h80 }; + 8'd52 : regdata <= {16'h0040,8'h50 }; + 8'd53 : regdata <= {16'h0041,8'h28 }; + 8'd54 : regdata <= {16'h0042,8'h00 }; + 8'd55 : regdata <= {16'h0043,8'h00 }; + 8'd56 : regdata <= {16'h0044,8'h00 }; + 8'd57 : regdata <= {16'h0045,8'h00 }; + 8'd58 : regdata <= {16'h0046,8'h00 }; + 8'd59 : regdata <= {16'h0047,8'hC0 }; + 8'd60 : regdata <= {16'h0052,8'hF4 }; + 8'd61 : regdata <= {16'h006C,8'h00 }; + 8'd62 : regdata <= {16'h006E,8'h00 }; + 8'd63 : regdata <= {16'h006F,8'h00 }; + 8'd64 : regdata <= {16'h0070,8'hE3 }; + 8'd65 : regdata <= {16'h0071,8'h60 }; + 8'd66 : regdata <= {16'h0072,8'h32 }; + 8'd67 : regdata <= {16'h0073,8'h00 }; + 8'd68 : regdata <= {16'h0079,8'h00 }; + 8'd69 : regdata <= {16'h007A,8'h00 }; + 8'd70 : regdata <= {16'h007B,8'h00 }; + 8'd71 : regdata <= {16'h007C,8'h00 }; + + //跳频 + 8'd72:regdata <= { 16'h0022,D,4'd0 };//double Då€é¢‘器 + 8'd73:regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器 + 8'd74:regdata <= { 16'h001A ,2'b0,MOD2[13:8] } ; + 8'd75:regdata <= { 16'h0019 ,MOD2[7:0] } ; + 8'd76:regdata <= { 16'h0018 ,1'b0,FRAC2[13:7] } ; + 8'd77:regdata <= { 16'h0017 ,FRAC2[6:0],FRAC1[24] } ; + 8'd78:regdata <= { 16'h0016 ,FRAC1[23:16] } ; + 8'd79:regdata <= { 16'h0015 ,FRAC1[15:8] } ; + 8'd80:regdata <= { 16'h0014 ,FRAC1[7:0] } ; + 8'd81:regdata <= { 16'h0037 ,SI_BAND_SEL } ; + 8'd82:regdata <= { 16'h0038 ,SI_VCO_SEL_BIAS_CODE } ; + 8'd83:regdata <= { 16'h0011 ,INT[15:8] } ; + 8'd84:regdata <= { 16'h0010 ,INT[7:0] } ; + + default: regdata <= regdata; +endcase +end + + + + + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/band_rom_a.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/band_rom_a.v new file mode 100644 index 0000000..cf7ad8e --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/band_rom_a.v @@ -0,0 +1,3573 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 18:19:17 01/25/2022 +// Design Name: +// Module Name: band_rom +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module band_rom_a( +input sysclk, +input [11 : 0] addra, + +output reg[15:0] douta +); + +always@(posedge sysclk)begin + case(addra) + +0 : douta <= 16'h7426 ; +1 : douta <= 16'h7426 ; +2 : douta <= 16'h7426 ; +3 : douta <= 16'h7426 ; +4 : douta <= 16'h7426 ; +5 : douta <= 16'h7326 ; +6 : douta <= 16'h7326 ; +7 : douta <= 16'h7426 ; +8 : douta <= 16'h7426 ; +9 : douta <= 16'h7326 ; +10 : douta <= 16'h7326 ; +11 : douta <= 16'h7326 ; +12 : douta <= 16'h7326 ; +13 : douta <= 16'h7326 ; +14 : douta <= 16'h7326 ; +15 : douta <= 16'h7326 ; +16 : douta <= 16'h7326 ; +17 : douta <= 16'h7226 ; +18 : douta <= 16'h7326 ; +19 : douta <= 16'h7226 ; +20 : douta <= 16'h7226 ; +21 : douta <= 16'h7226 ; +22 : douta <= 16'h7226 ; +23 : douta <= 16'h7126 ; +24 : douta <= 16'h7126 ; +25 : douta <= 16'h7126 ; +26 : douta <= 16'h7226 ; +27 : douta <= 16'h7226 ; +28 : douta <= 16'h7226 ; +29 : douta <= 16'h7226 ; +30 : douta <= 16'h7226 ; +31 : douta <= 16'h7226 ; +32 : douta <= 16'h7226 ; +33 : douta <= 16'h7226 ; +34 : douta <= 16'h7226 ; +35 : douta <= 16'h7226 ; +36 : douta <= 16'h7126 ; +37 : douta <= 16'h7126 ; +38 : douta <= 16'h7126 ; +39 : douta <= 16'h7126 ; +40 : douta <= 16'h7126 ; +41 : douta <= 16'h7126 ; +42 : douta <= 16'h7126 ; +43 : douta <= 16'h7126 ; +44 : douta <= 16'h7126 ; +45 : douta <= 16'h7126 ; +46 : douta <= 16'h7126 ; +47 : douta <= 16'h7126 ; +48 : douta <= 16'h7126 ; +49 : douta <= 16'h7026 ; +50 : douta <= 16'h7026 ; +51 : douta <= 16'h7126 ; +52 : douta <= 16'h7026 ; +53 : douta <= 16'h7126 ; +54 : douta <= 16'h6F26 ; +55 : douta <= 16'h7126 ; +56 : douta <= 16'h7126 ; +57 : douta <= 16'h7126 ; +58 : douta <= 16'h7126 ; +59 : douta <= 16'h7026 ; +60 : douta <= 16'h7126 ; +61 : douta <= 16'h6E26 ; +62 : douta <= 16'h7026 ; +63 : douta <= 16'h6E26 ; +64 : douta <= 16'h7026 ; +65 : douta <= 16'h7026 ; +66 : douta <= 16'h7026 ; +67 : douta <= 16'h7026 ; +68 : douta <= 16'h7026 ; +69 : douta <= 16'h7026 ; +70 : douta <= 16'h7026 ; +71 : douta <= 16'h7026 ; +72 : douta <= 16'h7026 ; +73 : douta <= 16'h7026 ; +74 : douta <= 16'h7026 ; +75 : douta <= 16'h7026 ; +76 : douta <= 16'h7026 ; +77 : douta <= 16'h7026 ; +78 : douta <= 16'h7026 ; +79 : douta <= 16'h7026 ; +80 : douta <= 16'h7026 ; +81 : douta <= 16'h6F26 ; +82 : douta <= 16'h6F26 ; +83 : douta <= 16'h6F26 ; +84 : douta <= 16'h6F26 ; +85 : douta <= 16'h6F26 ; +86 : douta <= 16'h6E26 ; +87 : douta <= 16'h6E26 ; +88 : douta <= 16'h6E26 ; +89 : douta <= 16'h6E26 ; +90 : douta <= 16'h6E26 ; +91 : douta <= 16'h6E26 ; +92 : douta <= 16'h6E26 ; +93 : douta <= 16'h6E26 ; +94 : douta <= 16'h6E26 ; +95 : douta <= 16'h6E26 ; +96 : douta <= 16'h6E26 ; +97 : douta <= 16'h6E26 ; +98 : douta <= 16'h6E26 ; +99 : douta <= 16'h6E26 ; +100 : douta <= 16'h6E26 ; +101 : douta <= 16'h6E26 ; +102 : douta <= 16'h6E26 ; +103 : douta <= 16'h6E26 ; +104 : douta <= 16'h6E26 ; +105 : douta <= 16'h6E26 ; +106 : douta <= 16'h6E26 ; +107 : douta <= 16'h6D26 ; +108 : douta <= 16'h6E26 ; +109 : douta <= 16'h6D26 ; +110 : douta <= 16'h6D26 ; +111 : douta <= 16'h6D26 ; +112 : douta <= 16'h6D26 ; +113 : douta <= 16'h6D26 ; +114 : douta <= 16'h6D26 ; +115 : douta <= 16'h6D26 ; +116 : douta <= 16'h6D26 ; +117 : douta <= 16'h6D26 ; +118 : douta <= 16'h6D26 ; +119 : douta <= 16'h6D26 ; +120 : douta <= 16'h6D26 ; +121 : douta <= 16'h6C26 ; +122 : douta <= 16'h6D26 ; +123 : douta <= 16'h6D26 ; +124 : douta <= 16'h6C26 ; +125 : douta <= 16'h6D26 ; +126 : douta <= 16'h6D26 ; +127 : douta <= 16'h6D26 ; +128 : douta <= 16'h6D26 ; +129 : douta <= 16'h6D26 ; +130 : douta <= 16'h6D26 ; +131 : douta <= 16'h6D26 ; +132 : douta <= 16'h6D26 ; +133 : douta <= 16'h6C26 ; +134 : douta <= 16'h6C26 ; +135 : douta <= 16'h6C26 ; +136 : douta <= 16'h6C26 ; +137 : douta <= 16'h6C26 ; +138 : douta <= 16'h6C26 ; +139 : douta <= 16'h6C26 ; +140 : douta <= 16'h6C26 ; +141 : douta <= 16'h6C26 ; +142 : douta <= 16'h6C26 ; +143 : douta <= 16'h6C26 ; +144 : douta <= 16'h6C26 ; +145 : douta <= 16'h6C26 ; +146 : douta <= 16'h6C26 ; +147 : douta <= 16'h6C26 ; +148 : douta <= 16'h6C26 ; +149 : douta <= 16'h6C26 ; +150 : douta <= 16'h6C26 ; +151 : douta <= 16'h6C26 ; +152 : douta <= 16'h6C26 ; +153 : douta <= 16'h6B26 ; +154 : douta <= 16'h6B26 ; +155 : douta <= 16'h6B26 ; +156 : douta <= 16'h6B26 ; +157 : douta <= 16'h6B26 ; +158 : douta <= 16'h6B26 ; +159 : douta <= 16'h6B26 ; +160 : douta <= 16'h6B26 ; +161 : douta <= 16'h6B26 ; +162 : douta <= 16'h6A26 ; +163 : douta <= 16'h6A26 ; +164 : douta <= 16'h6A26 ; +165 : douta <= 16'h6A26 ; +166 : douta <= 16'h6A26 ; +167 : douta <= 16'h6A26 ; +168 : douta <= 16'h6926 ; +169 : douta <= 16'h6A26 ; +170 : douta <= 16'h6926 ; +171 : douta <= 16'h6A26 ; +172 : douta <= 16'h6926 ; +173 : douta <= 16'h6A26 ; +174 : douta <= 16'h6A26 ; +175 : douta <= 16'h6A26 ; +176 : douta <= 16'h6A26 ; +177 : douta <= 16'h6A26 ; +178 : douta <= 16'h6A26 ; +179 : douta <= 16'h6A26 ; +180 : douta <= 16'h6A26 ; +181 : douta <= 16'h6A26 ; +182 : douta <= 16'h6A26 ; +183 : douta <= 16'h6A26 ; +184 : douta <= 16'h6926 ; +185 : douta <= 16'h6926 ; +186 : douta <= 16'h6926 ; +187 : douta <= 16'h6926 ; +188 : douta <= 16'h6926 ; +189 : douta <= 16'h6926 ; +190 : douta <= 16'h6926 ; +191 : douta <= 16'h6926 ; +192 : douta <= 16'h6926 ; +193 : douta <= 16'h6926 ; +194 : douta <= 16'h6926 ; +195 : douta <= 16'h6826 ; +196 : douta <= 16'h6826 ; +197 : douta <= 16'h6826 ; +198 : douta <= 16'h6826 ; +199 : douta <= 16'h6826 ; +200 : douta <= 16'h6926 ; +201 : douta <= 16'h6926 ; +202 : douta <= 16'h6926 ; +203 : douta <= 16'h6926 ; +204 : douta <= 16'h6926 ; +205 : douta <= 16'h6926 ; +206 : douta <= 16'h6926 ; +207 : douta <= 16'h6926 ; +208 : douta <= 16'h6826 ; +209 : douta <= 16'h6826 ; +210 : douta <= 16'h6826 ; +211 : douta <= 16'h6826 ; +212 : douta <= 16'h6826 ; +213 : douta <= 16'h6826 ; +214 : douta <= 16'h6826 ; +215 : douta <= 16'h6826 ; +216 : douta <= 16'h6826 ; +217 : douta <= 16'h6826 ; +218 : douta <= 16'h6826 ; +219 : douta <= 16'h6726 ; +220 : douta <= 16'h6726 ; +221 : douta <= 16'h6826 ; +222 : douta <= 16'h6826 ; +223 : douta <= 16'h6826 ; +224 : douta <= 16'h6826 ; +225 : douta <= 16'h6826 ; +226 : douta <= 16'h6826 ; +227 : douta <= 16'h6826 ; +228 : douta <= 16'h6826 ; +229 : douta <= 16'h6826 ; +230 : douta <= 16'h6826 ; +231 : douta <= 16'h6826 ; +232 : douta <= 16'h6726 ; +233 : douta <= 16'h6726 ; +234 : douta <= 16'h6526 ; +235 : douta <= 16'h6526 ; +236 : douta <= 16'h6726 ; +237 : douta <= 16'h6726 ; +238 : douta <= 16'h6726 ; +239 : douta <= 16'h6726 ; +240 : douta <= 16'h6726 ; +241 : douta <= 16'h6626 ; +242 : douta <= 16'h6626 ; +243 : douta <= 16'h6626 ; +244 : douta <= 16'h6626 ; +245 : douta <= 16'h6626 ; +246 : douta <= 16'h6626 ; +247 : douta <= 16'h6626 ; +248 : douta <= 16'h6626 ; +249 : douta <= 16'h6626 ; +250 : douta <= 16'h6626 ; +251 : douta <= 16'h6626 ; +252 : douta <= 16'h6626 ; +253 : douta <= 16'h6626 ; +254 : douta <= 16'h6626 ; +255 : douta <= 16'h6626 ; +256 : douta <= 16'h6626 ; +257 : douta <= 16'h6626 ; +258 : douta <= 16'h6626 ; +259 : douta <= 16'h6626 ; +260 : douta <= 16'h6626 ; +261 : douta <= 16'h6626 ; +262 : douta <= 16'h6526 ; +263 : douta <= 16'h6626 ; +264 : douta <= 16'h6526 ; +265 : douta <= 16'h6526 ; +266 : douta <= 16'h6526 ; +267 : douta <= 16'h6526 ; +268 : douta <= 16'h6526 ; +269 : douta <= 16'h6526 ; +270 : douta <= 16'h6526 ; +271 : douta <= 16'h6526 ; +272 : douta <= 16'h6526 ; +273 : douta <= 16'h6526 ; +274 : douta <= 16'h6526 ; +275 : douta <= 16'h6526 ; +276 : douta <= 16'h6526 ; +277 : douta <= 16'h6426 ; +278 : douta <= 16'h6526 ; +279 : douta <= 16'h6526 ; +280 : douta <= 16'h6526 ; +281 : douta <= 16'h6526 ; +282 : douta <= 16'h6526 ; +283 : douta <= 16'h6526 ; +284 : douta <= 16'h6526 ; +285 : douta <= 16'h6526 ; +286 : douta <= 16'h6526 ; +287 : douta <= 16'h6526 ; +288 : douta <= 16'h6426 ; +289 : douta <= 16'h6426 ; +290 : douta <= 16'h6426 ; +291 : douta <= 16'h6426 ; +292 : douta <= 16'h6426 ; +293 : douta <= 16'h6426 ; +294 : douta <= 16'h6426 ; +295 : douta <= 16'h6426 ; +296 : douta <= 16'h6426 ; +297 : douta <= 16'h6426 ; +298 : douta <= 16'h6426 ; +299 : douta <= 16'h6426 ; +300 : douta <= 16'h6426 ; +301 : douta <= 16'h6426 ; +302 : douta <= 16'h6426 ; +303 : douta <= 16'h6426 ; +304 : douta <= 16'h6426 ; +305 : douta <= 16'h6326 ; +306 : douta <= 16'h6426 ; +307 : douta <= 16'h6326 ; +308 : douta <= 16'h6326 ; +309 : douta <= 16'h6326 ; +310 : douta <= 16'h6326 ; +311 : douta <= 16'h6426 ; +312 : douta <= 16'h6426 ; +313 : douta <= 16'h6326 ; +314 : douta <= 16'h6326 ; +315 : douta <= 16'h6326 ; +316 : douta <= 16'h6326 ; +317 : douta <= 16'h6326 ; +318 : douta <= 16'h6326 ; +319 : douta <= 16'h6226 ; +320 : douta <= 16'h6226 ; +321 : douta <= 16'h6226 ; +322 : douta <= 16'h6226 ; +323 : douta <= 16'h6226 ; +324 : douta <= 16'h6126 ; +325 : douta <= 16'h6226 ; +326 : douta <= 16'h6126 ; +327 : douta <= 16'h6126 ; +328 : douta <= 16'h6126 ; +329 : douta <= 16'h6226 ; +330 : douta <= 16'h6226 ; +331 : douta <= 16'h6226 ; +332 : douta <= 16'h6226 ; +333 : douta <= 16'h6226 ; +334 : douta <= 16'h6226 ; +335 : douta <= 16'h6226 ; +336 : douta <= 16'h6226 ; +337 : douta <= 16'h6226 ; +338 : douta <= 16'h6226 ; +339 : douta <= 16'h6226 ; +340 : douta <= 16'h6226 ; +341 : douta <= 16'h6126 ; +342 : douta <= 16'h6126 ; +343 : douta <= 16'h6126 ; +344 : douta <= 16'h6126 ; +345 : douta <= 16'h6126 ; +346 : douta <= 16'h6126 ; +347 : douta <= 16'h6126 ; +348 : douta <= 16'h6126 ; +349 : douta <= 16'h6126 ; +350 : douta <= 16'h6126 ; +351 : douta <= 16'h6126 ; +352 : douta <= 16'h6126 ; +353 : douta <= 16'h6126 ; +354 : douta <= 16'h6126 ; +355 : douta <= 16'h6026 ; +356 : douta <= 16'h6026 ; +357 : douta <= 16'h6126 ; +358 : douta <= 16'h6126 ; +359 : douta <= 16'h6126 ; +360 : douta <= 16'h6126 ; +361 : douta <= 16'h6126 ; +362 : douta <= 16'h6126 ; +363 : douta <= 16'h6126 ; +364 : douta <= 16'h6126 ; +365 : douta <= 16'h6126 ; +366 : douta <= 16'h6126 ; +367 : douta <= 16'h6126 ; +368 : douta <= 16'h6026 ; +369 : douta <= 16'h6026 ; +370 : douta <= 16'h6026 ; +371 : douta <= 16'h6026 ; +372 : douta <= 16'h6026 ; +373 : douta <= 16'h6026 ; +374 : douta <= 16'h6026 ; +375 : douta <= 16'h5F28 ; +376 : douta <= 16'h6026 ; +377 : douta <= 16'h6026 ; +378 : douta <= 16'h6026 ; +379 : douta <= 16'h5F28 ; +380 : douta <= 16'h6026 ; +381 : douta <= 16'h6026 ; +382 : douta <= 16'h6026 ; +383 : douta <= 16'h6026 ; +384 : douta <= 16'h6026 ; +385 : douta <= 16'h6026 ; +386 : douta <= 16'h5F28 ; +387 : douta <= 16'h6026 ; +388 : douta <= 16'h6026 ; +389 : douta <= 16'h6026 ; +390 : douta <= 16'h5E28 ; +391 : douta <= 16'h6026 ; +392 : douta <= 16'h6026 ; +393 : douta <= 16'h6026 ; +394 : douta <= 16'h6026 ; +395 : douta <= 16'h6026 ; +396 : douta <= 16'h6026 ; +397 : douta <= 16'h6026 ; +398 : douta <= 16'h6026 ; +399 : douta <= 16'h6026 ; +400 : douta <= 16'h5E28 ; +401 : douta <= 16'h5E28 ; +402 : douta <= 16'h5E28 ; +403 : douta <= 16'h5E28 ; +404 : douta <= 16'h5E28 ; +405 : douta <= 16'h5E28 ; +406 : douta <= 16'h5E28 ; +407 : douta <= 16'h5E28 ; +408 : douta <= 16'h5E28 ; +409 : douta <= 16'h5E28 ; +410 : douta <= 16'h5E28 ; +411 : douta <= 16'h5D28 ; +412 : douta <= 16'h5D28 ; +413 : douta <= 16'h5D28 ; +414 : douta <= 16'h5D28 ; +415 : douta <= 16'h5D28 ; +416 : douta <= 16'h5D28 ; +417 : douta <= 16'h5D28 ; +418 : douta <= 16'h5D28 ; +419 : douta <= 16'h5D28 ; +420 : douta <= 16'h5D28 ; +421 : douta <= 16'h5D28 ; +422 : douta <= 16'h5D28 ; +423 : douta <= 16'h5D28 ; +424 : douta <= 16'h5D28 ; +425 : douta <= 16'h5C28 ; +426 : douta <= 16'h5C28 ; +427 : douta <= 16'h5D28 ; +428 : douta <= 16'h5D28 ; +429 : douta <= 16'h5B28 ; +430 : douta <= 16'h5B28 ; +431 : douta <= 16'h5D28 ; +432 : douta <= 16'h5D28 ; +433 : douta <= 16'h5C28 ; +434 : douta <= 16'h5C28 ; +435 : douta <= 16'h5C28 ; +436 : douta <= 16'h5C28 ; +437 : douta <= 16'h5C28 ; +438 : douta <= 16'h5C28 ; +439 : douta <= 16'h5C28 ; +440 : douta <= 16'h5C28 ; +441 : douta <= 16'h5C28 ; +442 : douta <= 16'h5C28 ; +443 : douta <= 16'h5C28 ; +444 : douta <= 16'h5C28 ; +445 : douta <= 16'h5C28 ; +446 : douta <= 16'h5C28 ; +447 : douta <= 16'h5C28 ; +448 : douta <= 16'h5C28 ; +449 : douta <= 16'h5C28 ; +450 : douta <= 16'h5C28 ; +451 : douta <= 16'h5C28 ; +452 : douta <= 16'h5C28 ; +453 : douta <= 16'h5C28 ; +454 : douta <= 16'h5C28 ; +455 : douta <= 16'h5B28 ; +456 : douta <= 16'h5C28 ; +457 : douta <= 16'h5C28 ; +458 : douta <= 16'h5B28 ; +459 : douta <= 16'h5B28 ; +460 : douta <= 16'h5B28 ; +461 : douta <= 16'h5B28 ; +462 : douta <= 16'h5B28 ; +463 : douta <= 16'h5B28 ; +464 : douta <= 16'h5B28 ; +465 : douta <= 16'h5B28 ; +466 : douta <= 16'h5B28 ; +467 : douta <= 16'h5A28 ; +468 : douta <= 16'h5A28 ; +469 : douta <= 16'h5A28 ; +470 : douta <= 16'h5A28 ; +471 : douta <= 16'h5A28 ; +472 : douta <= 16'h5A28 ; +473 : douta <= 16'h5A28 ; +474 : douta <= 16'h5A28 ; +475 : douta <= 16'h5A28 ; +476 : douta <= 16'h5A28 ; +477 : douta <= 16'h5A28 ; +478 : douta <= 16'h5A28 ; +479 : douta <= 16'h5A28 ; +480 : douta <= 16'h5A28 ; +481 : douta <= 16'h5A28 ; +482 : douta <= 16'h5A28 ; +483 : douta <= 16'h5A28 ; +484 : douta <= 16'h5A28 ; +485 : douta <= 16'h5A28 ; +486 : douta <= 16'h5A28 ; +487 : douta <= 16'h5A28 ; +488 : douta <= 16'h5A28 ; +489 : douta <= 16'h5928 ; +490 : douta <= 16'h5928 ; +491 : douta <= 16'h5928 ; +492 : douta <= 16'h5928 ; +493 : douta <= 16'h5928 ; +494 : douta <= 16'h5928 ; +495 : douta <= 16'h5928 ; +496 : douta <= 16'h5928 ; +497 : douta <= 16'h5928 ; +498 : douta <= 16'h5928 ; +499 : douta <= 16'h5928 ; +500 : douta <= 16'h5928 ; +501 : douta <= 16'h5928 ; +502 : douta <= 16'h5828 ; +503 : douta <= 16'h5828 ; +504 : douta <= 16'h5828 ; +505 : douta <= 16'h5828 ; +506 : douta <= 16'h5828 ; +507 : douta <= 16'h5928 ; +508 : douta <= 16'h5928 ; +509 : douta <= 16'h5928 ; +510 : douta <= 16'h5928 ; +511 : douta <= 16'h5928 ; +512 : douta <= 16'h5928 ; +513 : douta <= 16'h5928 ; +514 : douta <= 16'h5828 ; +515 : douta <= 16'h5828 ; +516 : douta <= 16'h5828 ; +517 : douta <= 16'h5828 ; +518 : douta <= 16'h5828 ; +519 : douta <= 16'h5828 ; +520 : douta <= 16'h5828 ; +521 : douta <= 16'h5828 ; +522 : douta <= 16'h5828 ; +523 : douta <= 16'h5828 ; +524 : douta <= 16'h5828 ; +525 : douta <= 16'h5828 ; +526 : douta <= 16'h5828 ; +527 : douta <= 16'h5828 ; +528 : douta <= 16'h5828 ; +529 : douta <= 16'h5828 ; +530 : douta <= 16'h5828 ; +531 : douta <= 16'h5828 ; +532 : douta <= 16'h5728 ; +533 : douta <= 16'h5728 ; +534 : douta <= 16'h5728 ; +535 : douta <= 16'h5828 ; +536 : douta <= 16'h5828 ; +537 : douta <= 16'h5728 ; +538 : douta <= 16'h5728 ; +539 : douta <= 16'h5728 ; +540 : douta <= 16'h5728 ; +541 : douta <= 16'h5528 ; +542 : douta <= 16'h5728 ; +543 : douta <= 16'h5528 ; +544 : douta <= 16'h5728 ; +545 : douta <= 16'h5728 ; +546 : douta <= 16'h5728 ; +547 : douta <= 16'h5628 ; +548 : douta <= 16'h5628 ; +549 : douta <= 16'h5628 ; +550 : douta <= 16'h5628 ; +551 : douta <= 16'h5628 ; +552 : douta <= 16'h5628 ; +553 : douta <= 16'h5628 ; +554 : douta <= 16'h5628 ; +555 : douta <= 16'h5628 ; +556 : douta <= 16'h5628 ; +557 : douta <= 16'h5628 ; +558 : douta <= 16'h5628 ; +559 : douta <= 16'h5628 ; +560 : douta <= 16'h5628 ; +561 : douta <= 16'h5628 ; +562 : douta <= 16'h5628 ; +563 : douta <= 16'h5628 ; +564 : douta <= 16'h5628 ; +565 : douta <= 16'h5628 ; +566 : douta <= 16'h5628 ; +567 : douta <= 16'h5628 ; +568 : douta <= 16'h5628 ; +569 : douta <= 16'h5628 ; +570 : douta <= 16'h5628 ; +571 : douta <= 16'h5528 ; +572 : douta <= 16'h5528 ; +573 : douta <= 16'h5528 ; +574 : douta <= 16'h5528 ; +575 : douta <= 16'h5528 ; +576 : douta <= 16'h5528 ; +577 : douta <= 16'h5528 ; +578 : douta <= 16'h5528 ; +579 : douta <= 16'h5528 ; +580 : douta <= 16'h5528 ; +581 : douta <= 16'h5528 ; +582 : douta <= 16'h5528 ; +583 : douta <= 16'h5528 ; +584 : douta <= 16'h5528 ; +585 : douta <= 16'h5528 ; +586 : douta <= 16'h5428 ; +587 : douta <= 16'h5528 ; +588 : douta <= 16'h5528 ; +589 : douta <= 16'h5528 ; +590 : douta <= 16'h5528 ; +591 : douta <= 16'h5528 ; +592 : douta <= 16'h5528 ; +593 : douta <= 16'h5528 ; +594 : douta <= 16'h5528 ; +595 : douta <= 16'h5528 ; +596 : douta <= 16'h5428 ; +597 : douta <= 16'h5428 ; +598 : douta <= 16'h5428 ; +599 : douta <= 16'h5428 ; +600 : douta <= 16'h5428 ; +601 : douta <= 16'h5428 ; +602 : douta <= 16'h5428 ; +603 : douta <= 16'h5428 ; +604 : douta <= 16'h5428 ; +605 : douta <= 16'h5428 ; +606 : douta <= 16'h5428 ; +607 : douta <= 16'h5428 ; +608 : douta <= 16'h5428 ; +609 : douta <= 16'h5428 ; +610 : douta <= 16'h5428 ; +611 : douta <= 16'h5428 ; +612 : douta <= 16'h5428 ; +613 : douta <= 16'h5428 ; +614 : douta <= 16'h5428 ; +615 : douta <= 16'h5428 ; +616 : douta <= 16'h5328 ; +617 : douta <= 16'h5328 ; +618 : douta <= 16'h5328 ; +619 : douta <= 16'h5328 ; +620 : douta <= 16'h5428 ; +621 : douta <= 16'h5328 ; +622 : douta <= 16'h5328 ; +623 : douta <= 16'h5328 ; +624 : douta <= 16'h5328 ; +625 : douta <= 16'h5328 ; +626 : douta <= 16'h5328 ; +627 : douta <= 16'h5328 ; +628 : douta <= 16'h5328 ; +629 : douta <= 16'h5328 ; +630 : douta <= 16'h5328 ; +631 : douta <= 16'h5328 ; +632 : douta <= 16'h5328 ; +633 : douta <= 16'h5328 ; +634 : douta <= 16'h5228 ; +635 : douta <= 16'h5228 ; +636 : douta <= 16'h5128 ; +637 : douta <= 16'h5128 ; +638 : douta <= 16'h5128 ; +639 : douta <= 16'h5228 ; +640 : douta <= 16'h5228 ; +641 : douta <= 16'h5228 ; +642 : douta <= 16'h5228 ; +643 : douta <= 16'h5228 ; +644 : douta <= 16'h5228 ; +645 : douta <= 16'h5228 ; +646 : douta <= 16'h5228 ; +647 : douta <= 16'h5228 ; +648 : douta <= 16'h5228 ; +649 : douta <= 16'h5228 ; +650 : douta <= 16'h5228 ; +651 : douta <= 16'h5228 ; +652 : douta <= 16'h5228 ; +653 : douta <= 16'h5228 ; +654 : douta <= 16'h5228 ; +655 : douta <= 16'h5228 ; +656 : douta <= 16'h5128 ; +657 : douta <= 16'h5128 ; +658 : douta <= 16'h5128 ; +659 : douta <= 16'h5128 ; +660 : douta <= 16'h5128 ; +661 : douta <= 16'h5128 ; +662 : douta <= 16'h5128 ; +663 : douta <= 16'h5128 ; +664 : douta <= 16'h5128 ; +665 : douta <= 16'h5128 ; +666 : douta <= 16'h5128 ; +667 : douta <= 16'h5128 ; +668 : douta <= 16'h5128 ; +669 : douta <= 16'h5128 ; +670 : douta <= 16'h5128 ; +671 : douta <= 16'h5028 ; +672 : douta <= 16'h5028 ; +673 : douta <= 16'h5128 ; +674 : douta <= 16'h5128 ; +675 : douta <= 16'h5128 ; +676 : douta <= 16'h5128 ; +677 : douta <= 16'h5128 ; +678 : douta <= 16'h5128 ; +679 : douta <= 16'h5128 ; +680 : douta <= 16'h5128 ; +681 : douta <= 16'h5128 ; +682 : douta <= 16'h5028 ; +683 : douta <= 16'h5028 ; +684 : douta <= 16'h5028 ; +685 : douta <= 16'h4E28 ; +686 : douta <= 16'h5028 ; +687 : douta <= 16'h5028 ; +688 : douta <= 16'h4F28 ; +689 : douta <= 16'h5028 ; +690 : douta <= 16'h5028 ; +691 : douta <= 16'h5028 ; +692 : douta <= 16'h4F28 ; +693 : douta <= 16'h5028 ; +694 : douta <= 16'h5028 ; +695 : douta <= 16'h5028 ; +696 : douta <= 16'h5028 ; +697 : douta <= 16'h5028 ; +698 : douta <= 16'h5028 ; +699 : douta <= 16'h5028 ; +700 : douta <= 16'h5028 ; +701 : douta <= 16'h5028 ; +702 : douta <= 16'h5028 ; +703 : douta <= 16'h5028 ; +704 : douta <= 16'h5028 ; +705 : douta <= 16'h5028 ; +706 : douta <= 16'h5028 ; +707 : douta <= 16'h5028 ; +708 : douta <= 16'h4D28 ; +709 : douta <= 16'h4D28 ; +710 : douta <= 16'h4E28 ; +711 : douta <= 16'h4E28 ; +712 : douta <= 16'h4E28 ; +713 : douta <= 16'h4E28 ; +714 : douta <= 16'h4E28 ; +715 : douta <= 16'h4E28 ; +716 : douta <= 16'h4E28 ; +717 : douta <= 16'h4E28 ; +718 : douta <= 16'h4E28 ; +719 : douta <= 16'h4E28 ; +720 : douta <= 16'h4E28 ; +721 : douta <= 16'h4E28 ; +722 : douta <= 16'h4E28 ; +723 : douta <= 16'h4E28 ; +724 : douta <= 16'h4E28 ; +725 : douta <= 16'h4E28 ; +726 : douta <= 16'h4E28 ; +727 : douta <= 16'h4E28 ; +728 : douta <= 16'h4E28 ; +729 : douta <= 16'h4E28 ; +730 : douta <= 16'h4E28 ; +731 : douta <= 16'h4E28 ; +732 : douta <= 16'h4E28 ; +733 : douta <= 16'h4E28 ; +734 : douta <= 16'h4D28 ; +735 : douta <= 16'h4D28 ; +736 : douta <= 16'h4D28 ; +737 : douta <= 16'h4D28 ; +738 : douta <= 16'h4D28 ; +739 : douta <= 16'h4D28 ; +740 : douta <= 16'h4D28 ; +741 : douta <= 16'h4D28 ; +742 : douta <= 16'h4D28 ; +743 : douta <= 16'h4D28 ; +744 : douta <= 16'h4D28 ; +745 : douta <= 16'h4D28 ; +746 : douta <= 16'h4D28 ; +747 : douta <= 16'h4C28 ; +748 : douta <= 16'h4C28 ; +749 : douta <= 16'h4D28 ; +750 : douta <= 16'h4D28 ; +751 : douta <= 16'h4D28 ; +752 : douta <= 16'h4D28 ; +753 : douta <= 16'h4D28 ; +754 : douta <= 16'h4D28 ; +755 : douta <= 16'h4D28 ; +756 : douta <= 16'h4D28 ; +757 : douta <= 16'h4D28 ; +758 : douta <= 16'h4D28 ; +759 : douta <= 16'h4D28 ; +760 : douta <= 16'h4B28 ; +761 : douta <= 16'h4B28 ; +762 : douta <= 16'h4C28 ; +763 : douta <= 16'h4C28 ; +764 : douta <= 16'h4C28 ; +765 : douta <= 16'h4C28 ; +766 : douta <= 16'h4C28 ; +767 : douta <= 16'h4C28 ; +768 : douta <= 16'h4C28 ; +769 : douta <= 16'h4C28 ; +770 : douta <= 16'h4C28 ; +771 : douta <= 16'h4C28 ; +772 : douta <= 16'h4C28 ; +773 : douta <= 16'h4C28 ; +774 : douta <= 16'h4C28 ; +775 : douta <= 16'h4C28 ; +776 : douta <= 16'h4C28 ; +777 : douta <= 16'h4C28 ; +778 : douta <= 16'h4C28 ; +779 : douta <= 16'h4C28 ; +780 : douta <= 16'h4C28 ; +781 : douta <= 16'h4C28 ; +782 : douta <= 16'h4C28 ; +783 : douta <= 16'h4C28 ; +784 : douta <= 16'h4C28 ; +785 : douta <= 16'h4C28 ; +786 : douta <= 16'h4B28 ; +787 : douta <= 16'h4B28 ; +788 : douta <= 16'h4B28 ; +789 : douta <= 16'h4B28 ; +790 : douta <= 16'h4B28 ; +791 : douta <= 16'h4B28 ; +792 : douta <= 16'h4B28 ; +793 : douta <= 16'h4B28 ; +794 : douta <= 16'h4B28 ; +795 : douta <= 16'h4A28 ; +796 : douta <= 16'h4A28 ; +797 : douta <= 16'h4A28 ; +798 : douta <= 16'h4A28 ; +799 : douta <= 16'h4A28 ; +800 : douta <= 16'h4A28 ; +801 : douta <= 16'h4928 ; +802 : douta <= 16'h4A28 ; +803 : douta <= 16'h4928 ; +804 : douta <= 16'h4A28 ; +805 : douta <= 16'h4A28 ; +806 : douta <= 16'h4A28 ; +807 : douta <= 16'h4A28 ; +808 : douta <= 16'h4A28 ; +809 : douta <= 16'h4A28 ; +810 : douta <= 16'h4A28 ; +811 : douta <= 16'h4A28 ; +812 : douta <= 16'h4A28 ; +813 : douta <= 16'h4A28 ; +814 : douta <= 16'h4A28 ; +815 : douta <= 16'h4A28 ; +816 : douta <= 16'h4A28 ; +817 : douta <= 16'h4A28 ; +818 : douta <= 16'h4928 ; +819 : douta <= 16'h4928 ; +820 : douta <= 16'h4928 ; +821 : douta <= 16'h4928 ; +822 : douta <= 16'h4928 ; +823 : douta <= 16'h4928 ; +824 : douta <= 16'h4928 ; +825 : douta <= 16'h4928 ; +826 : douta <= 16'h4928 ; +827 : douta <= 16'h4928 ; +828 : douta <= 16'h4928 ; +829 : douta <= 16'h4928 ; +830 : douta <= 16'h4928 ; +831 : douta <= 16'h4828 ; +832 : douta <= 16'h4928 ; +833 : douta <= 16'h4928 ; +834 : douta <= 16'h4928 ; +835 : douta <= 16'h4928 ; +836 : douta <= 16'h4928 ; +837 : douta <= 16'h4928 ; +838 : douta <= 16'h4928 ; +839 : douta <= 16'h4928 ; +840 : douta <= 16'h4928 ; +841 : douta <= 16'h4928 ; +842 : douta <= 16'h4928 ; +843 : douta <= 16'h4928 ; +844 : douta <= 16'h4828 ; +845 : douta <= 16'h4828 ; +846 : douta <= 16'h4728 ; +847 : douta <= 16'h4728 ; +848 : douta <= 16'h4828 ; +849 : douta <= 16'h4828 ; +850 : douta <= 16'h4828 ; +851 : douta <= 16'h4828 ; +852 : douta <= 16'h4828 ; +853 : douta <= 16'h4828 ; +854 : douta <= 16'h4828 ; +855 : douta <= 16'h4828 ; +856 : douta <= 16'h4828 ; +857 : douta <= 16'h4828 ; +858 : douta <= 16'h4828 ; +859 : douta <= 16'h4828 ; +860 : douta <= 16'h4828 ; +861 : douta <= 16'h4828 ; +862 : douta <= 16'h4828 ; +863 : douta <= 16'h4828 ; +864 : douta <= 16'h4828 ; +865 : douta <= 16'h4828 ; +866 : douta <= 16'h4828 ; +867 : douta <= 16'h4828 ; +868 : douta <= 16'h4828 ; +869 : douta <= 16'h4528 ; +870 : douta <= 16'h4728 ; +871 : douta <= 16'h4528 ; +872 : douta <= 16'h4528 ; +873 : douta <= 16'h4728 ; +874 : douta <= 16'h4528 ; +875 : douta <= 16'h4728 ; +876 : douta <= 16'h4628 ; +877 : douta <= 16'h4628 ; +878 : douta <= 16'h4628 ; +879 : douta <= 16'h4628 ; +880 : douta <= 16'h4628 ; +881 : douta <= 16'h4628 ; +882 : douta <= 16'h4628 ; +883 : douta <= 16'h4628 ; +884 : douta <= 16'h4628 ; +885 : douta <= 16'h4628 ; +886 : douta <= 16'h4628 ; +887 : douta <= 16'h4628 ; +888 : douta <= 16'h4628 ; +889 : douta <= 16'h4628 ; +890 : douta <= 16'h4628 ; +891 : douta <= 16'h4628 ; +892 : douta <= 16'h4628 ; +893 : douta <= 16'h4628 ; +894 : douta <= 16'h4628 ; +895 : douta <= 16'h4628 ; +896 : douta <= 16'h4628 ; +897 : douta <= 16'h4528 ; +898 : douta <= 16'h4628 ; +899 : douta <= 16'h4528 ; +900 : douta <= 16'h4528 ; +901 : douta <= 16'h4528 ; +902 : douta <= 16'h4528 ; +903 : douta <= 16'h4528 ; +904 : douta <= 16'h4528 ; +905 : douta <= 16'h4528 ; +906 : douta <= 16'h4528 ; +907 : douta <= 16'h4528 ; +908 : douta <= 16'h4528 ; +909 : douta <= 16'h4528 ; +910 : douta <= 16'h4528 ; +911 : douta <= 16'h4528 ; +912 : douta <= 16'h4528 ; +913 : douta <= 16'h4428 ; +914 : douta <= 16'h4428 ; +915 : douta <= 16'h4528 ; +916 : douta <= 16'h4428 ; +917 : douta <= 16'h4428 ; +918 : douta <= 16'h4528 ; +919 : douta <= 16'h4528 ; +920 : douta <= 16'h4528 ; +921 : douta <= 16'h4528 ; +922 : douta <= 16'h4528 ; +923 : douta <= 16'h4528 ; +924 : douta <= 16'h4528 ; +925 : douta <= 16'h4528 ; +926 : douta <= 16'h4528 ; +927 : douta <= 16'h4428 ; +928 : douta <= 16'h4428 ; +929 : douta <= 16'h4428 ; +930 : douta <= 16'h4428 ; +931 : douta <= 16'h4428 ; +932 : douta <= 16'h4428 ; +933 : douta <= 16'h4428 ; +934 : douta <= 16'h4428 ; +935 : douta <= 16'h4428 ; +936 : douta <= 16'h4428 ; +937 : douta <= 16'h4428 ; +938 : douta <= 16'h4428 ; +939 : douta <= 16'h4428 ; +940 : douta <= 16'h4428 ; +941 : douta <= 16'h4428 ; +942 : douta <= 16'h4428 ; +943 : douta <= 16'h4428 ; +944 : douta <= 16'h4428 ; +945 : douta <= 16'h4428 ; +946 : douta <= 16'h4328 ; +947 : douta <= 16'h4328 ; +948 : douta <= 16'h4428 ; +949 : douta <= 16'h4328 ; +950 : douta <= 16'h4428 ; +951 : douta <= 16'h4428 ; +952 : douta <= 16'h4328 ; +953 : douta <= 16'h4328 ; +954 : douta <= 16'h4328 ; +955 : douta <= 16'h4328 ; +956 : douta <= 16'h4328 ; +957 : douta <= 16'h4328 ; +958 : douta <= 16'h4328 ; +959 : douta <= 16'h4328 ; +960 : douta <= 16'h4328 ; +961 : douta <= 16'h4328 ; +962 : douta <= 16'h4328 ; +963 : douta <= 16'h4228 ; +964 : douta <= 16'h4228 ; +965 : douta <= 16'h4228 ; +966 : douta <= 16'h4228 ; +967 : douta <= 16'h4228 ; +968 : douta <= 16'h4228 ; +969 : douta <= 16'h4228 ; +970 : douta <= 16'h4228 ; +971 : douta <= 16'h4228 ; +972 : douta <= 16'h4228 ; +973 : douta <= 16'h4228 ; +974 : douta <= 16'h4228 ; +975 : douta <= 16'h4228 ; +976 : douta <= 16'h4228 ; +977 : douta <= 16'h4228 ; +978 : douta <= 16'h4228 ; +979 : douta <= 16'h4228 ; +980 : douta <= 16'h4228 ; +981 : douta <= 16'h4228 ; +982 : douta <= 16'h4228 ; +983 : douta <= 16'h4228 ; +984 : douta <= 16'h4128 ; +985 : douta <= 16'h4128 ; +986 : douta <= 16'h4128 ; +987 : douta <= 16'h4128 ; +988 : douta <= 16'h4128 ; +989 : douta <= 16'h4128 ; +990 : douta <= 16'h4128 ; +991 : douta <= 16'h4128 ; +992 : douta <= 16'h4128 ; +993 : douta <= 16'h4128 ; +994 : douta <= 16'h4128 ; +995 : douta <= 16'h4128 ; +996 : douta <= 16'h4128 ; +997 : douta <= 16'h4128 ; +998 : douta <= 16'h4128 ; +999 : douta <= 16'h4128 ; +1000 : douta <= 16'h4128 ; +1001 : douta <= 16'h4128 ; +1002 : douta <= 16'h4128 ; +1003 : douta <= 16'h4128 ; +1004 : douta <= 16'h4028 ; +1005 : douta <= 16'h4128 ; +1006 : douta <= 16'h4128 ; +1007 : douta <= 16'h4128 ; +1008 : douta <= 16'h4128 ; +1009 : douta <= 16'h4128 ; +1010 : douta <= 16'h4128 ; +1011 : douta <= 16'h4128 ; +1012 : douta <= 16'h4128 ; +1013 : douta <= 16'h4128 ; +1014 : douta <= 16'h4128 ; +1015 : douta <= 16'h4028 ; +1016 : douta <= 16'h4028 ; +1017 : douta <= 16'h4028 ; +1018 : douta <= 16'h4028 ; +1019 : douta <= 16'h4028 ; +1020 : douta <= 16'h4028 ; +1021 : douta <= 16'h4028 ; +1022 : douta <= 16'h4028 ; +1023 : douta <= 16'h3F2A ; +1024 : douta <= 16'h4028 ; +1025 : douta <= 16'h4028 ; +1026 : douta <= 16'h3E2A ; +1027 : douta <= 16'h4028 ; +1028 : douta <= 16'h3F2A ; +1029 : douta <= 16'h4028 ; +1030 : douta <= 16'h4028 ; +1031 : douta <= 16'h4028 ; +1032 : douta <= 16'h4028 ; +1033 : douta <= 16'h4028 ; +1034 : douta <= 16'h4028 ; +1035 : douta <= 16'h4028 ; +1036 : douta <= 16'h4028 ; +1037 : douta <= 16'h4028 ; +1038 : douta <= 16'h4028 ; +1039 : douta <= 16'h4028 ; +1040 : douta <= 16'h4028 ; +1041 : douta <= 16'h4028 ; +1042 : douta <= 16'h4028 ; +1043 : douta <= 16'h4028 ; +1044 : douta <= 16'h4028 ; +1045 : douta <= 16'h4028 ; +1046 : douta <= 16'h4028 ; +1047 : douta <= 16'h4028 ; +1048 : douta <= 16'h4028 ; +1049 : douta <= 16'h4028 ; +1050 : douta <= 16'h3D2A ; +1051 : douta <= 16'h4028 ; +1052 : douta <= 16'h3E2A ; +1053 : douta <= 16'h3E2A ; +1054 : douta <= 16'h3E2A ; +1055 : douta <= 16'h3E2A ; +1056 : douta <= 16'h3E2A ; +1057 : douta <= 16'h3E2A ; +1058 : douta <= 16'h3E2A ; +1059 : douta <= 16'h3E2A ; +1060 : douta <= 16'h3E2A ; +1061 : douta <= 16'h3E2A ; +1062 : douta <= 16'h3E2A ; +1063 : douta <= 16'h3E2A ; +1064 : douta <= 16'h3E2A ; +1065 : douta <= 16'h3E2A ; +1066 : douta <= 16'h3E2A ; +1067 : douta <= 16'h3E2A ; +1068 : douta <= 16'h3E2A ; +1069 : douta <= 16'h3E2A ; +1070 : douta <= 16'h3E2A ; +1071 : douta <= 16'h3E2A ; +1072 : douta <= 16'h3E2A ; +1073 : douta <= 16'h3E2A ; +1074 : douta <= 16'h3E2A ; +1075 : douta <= 16'h3E2A ; +1076 : douta <= 16'h3D2A ; +1077 : douta <= 16'h3E2A ; +1078 : douta <= 16'h3D2A ; +1079 : douta <= 16'h3D2A ; +1080 : douta <= 16'h3D2A ; +1081 : douta <= 16'h3D2A ; +1082 : douta <= 16'h3D2A ; +1083 : douta <= 16'h3D2A ; +1084 : douta <= 16'h3D2A ; +1085 : douta <= 16'h3D2A ; +1086 : douta <= 16'h3D2A ; +1087 : douta <= 16'h3D2A ; +1088 : douta <= 16'h3D2A ; +1089 : douta <= 16'h3D2A ; +1090 : douta <= 16'h3D2A ; +1091 : douta <= 16'h3D2A ; +1092 : douta <= 16'h3C2A ; +1093 : douta <= 16'h3D2A ; +1094 : douta <= 16'h3D2A ; +1095 : douta <= 16'h3D2A ; +1096 : douta <= 16'h3C2A ; +1097 : douta <= 16'h3D2A ; +1098 : douta <= 16'h3D2A ; +1099 : douta <= 16'h3D2A ; +1100 : douta <= 16'h3D2A ; +1101 : douta <= 16'h3D2A ; +1102 : douta <= 16'h3C2A ; +1103 : douta <= 16'h3D2A ; +1104 : douta <= 16'h3B2A ; +1105 : douta <= 16'h3B2A ; +1106 : douta <= 16'h3B2A ; +1107 : douta <= 16'h3C2A ; +1108 : douta <= 16'h3C2A ; +1109 : douta <= 16'h3C2A ; +1110 : douta <= 16'h3C2A ; +1111 : douta <= 16'h3C2A ; +1112 : douta <= 16'h3C2A ; +1113 : douta <= 16'h3C2A ; +1114 : douta <= 16'h3C2A ; +1115 : douta <= 16'h3C2A ; +1116 : douta <= 16'h3C2A ; +1117 : douta <= 16'h3C2A ; +1118 : douta <= 16'h3C2A ; +1119 : douta <= 16'h3C2A ; +1120 : douta <= 16'h3C2A ; +1121 : douta <= 16'h3C2A ; +1122 : douta <= 16'h3C2A ; +1123 : douta <= 16'h3C2A ; +1124 : douta <= 16'h3C2A ; +1125 : douta <= 16'h3C2A ; +1126 : douta <= 16'h3C2A ; +1127 : douta <= 16'h3C2A ; +1128 : douta <= 16'h3C2A ; +1129 : douta <= 16'h3C2A ; +1130 : douta <= 16'h3C2A ; +1131 : douta <= 16'h3B2A ; +1132 : douta <= 16'h3B2A ; +1133 : douta <= 16'h3B2A ; +1134 : douta <= 16'h3B2A ; +1135 : douta <= 16'h3B2A ; +1136 : douta <= 16'h3B2A ; +1137 : douta <= 16'h3B2A ; +1138 : douta <= 16'h3A2A ; +1139 : douta <= 16'h3A2A ; +1140 : douta <= 16'h3A2A ; +1141 : douta <= 16'h3A2A ; +1142 : douta <= 16'h3A2A ; +1143 : douta <= 16'h3A2A ; +1144 : douta <= 16'h3A2A ; +1145 : douta <= 16'h3A2A ; +1146 : douta <= 16'h392A ; +1147 : douta <= 16'h392A ; +1148 : douta <= 16'h392A ; +1149 : douta <= 16'h3A2A ; +1150 : douta <= 16'h3A2A ; +1151 : douta <= 16'h3A2A ; +1152 : douta <= 16'h3A2A ; +1153 : douta <= 16'h3A2A ; +1154 : douta <= 16'h3A2A ; +1155 : douta <= 16'h3A2A ; +1156 : douta <= 16'h3A2A ; +1157 : douta <= 16'h3A2A ; +1158 : douta <= 16'h3A2A ; +1159 : douta <= 16'h3A2A ; +1160 : douta <= 16'h3A2A ; +1161 : douta <= 16'h3A2A ; +1162 : douta <= 16'h3A2A ; +1163 : douta <= 16'h392A ; +1164 : douta <= 16'h3A2A ; +1165 : douta <= 16'h392A ; +1166 : douta <= 16'h392A ; +1167 : douta <= 16'h392A ; +1168 : douta <= 16'h392A ; +1169 : douta <= 16'h392A ; +1170 : douta <= 16'h392A ; +1171 : douta <= 16'h392A ; +1172 : douta <= 16'h392A ; +1173 : douta <= 16'h392A ; +1174 : douta <= 16'h392A ; +1175 : douta <= 16'h392A ; +1176 : douta <= 16'h392A ; +1177 : douta <= 16'h392A ; +1178 : douta <= 16'h392A ; +1179 : douta <= 16'h382A ; +1180 : douta <= 16'h382A ; +1181 : douta <= 16'h392A ; +1182 : douta <= 16'h392A ; +1183 : douta <= 16'h392A ; +1184 : douta <= 16'h392A ; +1185 : douta <= 16'h392A ; +1186 : douta <= 16'h392A ; +1187 : douta <= 16'h392A ; +1188 : douta <= 16'h372A ; +1189 : douta <= 16'h372A ; +1190 : douta <= 16'h372A ; +1191 : douta <= 16'h372A ; +1192 : douta <= 16'h382A ; +1193 : douta <= 16'h382A ; +1194 : douta <= 16'h382A ; +1195 : douta <= 16'h382A ; +1196 : douta <= 16'h382A ; +1197 : douta <= 16'h382A ; +1198 : douta <= 16'h382A ; +1199 : douta <= 16'h382A ; +1200 : douta <= 16'h382A ; +1201 : douta <= 16'h382A ; +1202 : douta <= 16'h382A ; +1203 : douta <= 16'h382A ; +1204 : douta <= 16'h382A ; +1205 : douta <= 16'h382A ; +1206 : douta <= 16'h382A ; +1207 : douta <= 16'h382A ; +1208 : douta <= 16'h382A ; +1209 : douta <= 16'h382A ; +1210 : douta <= 16'h382A ; +1211 : douta <= 16'h382A ; +1212 : douta <= 16'h382A ; +1213 : douta <= 16'h382A ; +1214 : douta <= 16'h382A ; +1215 : douta <= 16'h382A ; +1216 : douta <= 16'h382A ; +1217 : douta <= 16'h372A ; +1218 : douta <= 16'h382A ; +1219 : douta <= 16'h372A ; +1220 : douta <= 16'h372A ; +1221 : douta <= 16'h372A ; +1222 : douta <= 16'h372A ; +1223 : douta <= 16'h372A ; +1224 : douta <= 16'h372A ; +1225 : douta <= 16'h372A ; +1226 : douta <= 16'h372A ; +1227 : douta <= 16'h362A ; +1228 : douta <= 16'h352A ; +1229 : douta <= 16'h362A ; +1230 : douta <= 16'h362A ; +1231 : douta <= 16'h362A ; +1232 : douta <= 16'h362A ; +1233 : douta <= 16'h362A ; +1234 : douta <= 16'h362A ; +1235 : douta <= 16'h362A ; +1236 : douta <= 16'h362A ; +1237 : douta <= 16'h362A ; +1238 : douta <= 16'h362A ; +1239 : douta <= 16'h362A ; +1240 : douta <= 16'h362A ; +1241 : douta <= 16'h362A ; +1242 : douta <= 16'h362A ; +1243 : douta <= 16'h362A ; +1244 : douta <= 16'h362A ; +1245 : douta <= 16'h362A ; +1246 : douta <= 16'h362A ; +1247 : douta <= 16'h362A ; +1248 : douta <= 16'h362A ; +1249 : douta <= 16'h362A ; +1250 : douta <= 16'h362A ; +1251 : douta <= 16'h362A ; +1252 : douta <= 16'h362A ; +1253 : douta <= 16'h352A ; +1254 : douta <= 16'h352A ; +1255 : douta <= 16'h352A ; +1256 : douta <= 16'h352A ; +1257 : douta <= 16'h352A ; +1258 : douta <= 16'h352A ; +1259 : douta <= 16'h352A ; +1260 : douta <= 16'h352A ; +1261 : douta <= 16'h352A ; +1262 : douta <= 16'h352A ; +1263 : douta <= 16'h352A ; +1264 : douta <= 16'h352A ; +1265 : douta <= 16'h352A ; +1266 : douta <= 16'h352A ; +1267 : douta <= 16'h342A ; +1268 : douta <= 16'h342A ; +1269 : douta <= 16'h352A ; +1270 : douta <= 16'h352A ; +1271 : douta <= 16'h352A ; +1272 : douta <= 16'h352A ; +1273 : douta <= 16'h352A ; +1274 : douta <= 16'h352A ; +1275 : douta <= 16'h352A ; +1276 : douta <= 16'h352A ; +1277 : douta <= 16'h352A ; +1278 : douta <= 16'h352A ; +1279 : douta <= 16'h352A ; +1280 : douta <= 16'h342A ; +1281 : douta <= 16'h342A ; +1282 : douta <= 16'h342A ; +1283 : douta <= 16'h342A ; +1284 : douta <= 16'h342A ; +1285 : douta <= 16'h342A ; +1286 : douta <= 16'h342A ; +1287 : douta <= 16'h342A ; +1288 : douta <= 16'h342A ; +1289 : douta <= 16'h342A ; +1290 : douta <= 16'h342A ; +1291 : douta <= 16'h342A ; +1292 : douta <= 16'h342A ; +1293 : douta <= 16'h342A ; +1294 : douta <= 16'h342A ; +1295 : douta <= 16'h342A ; +1296 : douta <= 16'h332A ; +1297 : douta <= 16'h332A ; +1298 : douta <= 16'h332A ; +1299 : douta <= 16'h342A ; +1300 : douta <= 16'h342A ; +1301 : douta <= 16'h342A ; +1302 : douta <= 16'h342A ; +1303 : douta <= 16'h342A ; +1304 : douta <= 16'h342A ; +1305 : douta <= 16'h332A ; +1306 : douta <= 16'h332A ; +1307 : douta <= 16'h332A ; +1308 : douta <= 16'h332A ; +1309 : douta <= 16'h332A ; +1310 : douta <= 16'h332A ; +1311 : douta <= 16'h332A ; +1312 : douta <= 16'h332A ; +1313 : douta <= 16'h332A ; +1314 : douta <= 16'h332A ; +1315 : douta <= 16'h322A ; +1316 : douta <= 16'h322A ; +1317 : douta <= 16'h322A ; +1318 : douta <= 16'h322A ; +1319 : douta <= 16'h322A ; +1320 : douta <= 16'h322A ; +1321 : douta <= 16'h312A ; +1322 : douta <= 16'h322A ; +1323 : douta <= 16'h312A ; +1324 : douta <= 16'h312A ; +1325 : douta <= 16'h322A ; +1326 : douta <= 16'h322A ; +1327 : douta <= 16'h322A ; +1328 : douta <= 16'h322A ; +1329 : douta <= 16'h322A ; +1330 : douta <= 16'h322A ; +1331 : douta <= 16'h322A ; +1332 : douta <= 16'h322A ; +1333 : douta <= 16'h322A ; +1334 : douta <= 16'h322A ; +1335 : douta <= 16'h322A ; +1336 : douta <= 16'h322A ; +1337 : douta <= 16'h322A ; +1338 : douta <= 16'h322A ; +1339 : douta <= 16'h322A ; +1340 : douta <= 16'h312A ; +1341 : douta <= 16'h312A ; +1342 : douta <= 16'h312A ; +1343 : douta <= 16'h312A ; +1344 : douta <= 16'h312A ; +1345 : douta <= 16'h312A ; +1346 : douta <= 16'h312A ; +1347 : douta <= 16'h312A ; +1348 : douta <= 16'h312A ; +1349 : douta <= 16'h312A ; +1350 : douta <= 16'h312A ; +1351 : douta <= 16'h312A ; +1352 : douta <= 16'h312A ; +1353 : douta <= 16'h312A ; +1354 : douta <= 16'h312A ; +1355 : douta <= 16'h312A ; +1356 : douta <= 16'h302A ; +1357 : douta <= 16'h312A ; +1358 : douta <= 16'h312A ; +1359 : douta <= 16'h312A ; +1360 : douta <= 16'h312A ; +1361 : douta <= 16'h312A ; +1362 : douta <= 16'h312A ; +1363 : douta <= 16'h312A ; +1364 : douta <= 16'h312A ; +1365 : douta <= 16'h312A ; +1366 : douta <= 16'h2F2A ; +1367 : douta <= 16'h302A ; +1368 : douta <= 16'h302A ; +1369 : douta <= 16'h302A ; +1370 : douta <= 16'h302A ; +1371 : douta <= 16'h302A ; +1372 : douta <= 16'h302A ; +1373 : douta <= 16'h302A ; +1374 : douta <= 16'h302A ; +1375 : douta <= 16'h302A ; +1376 : douta <= 16'h302A ; +1377 : douta <= 16'h302A ; +1378 : douta <= 16'h302A ; +1379 : douta <= 16'h302A ; +1380 : douta <= 16'h302A ; +1381 : douta <= 16'h302A ; +1382 : douta <= 16'h2F2A ; +1383 : douta <= 16'h302A ; +1384 : douta <= 16'h302A ; +1385 : douta <= 16'h302A ; +1386 : douta <= 16'h302A ; +1387 : douta <= 16'h302A ; +1388 : douta <= 16'h302A ; +1389 : douta <= 16'h302A ; +1390 : douta <= 16'h302A ; +1391 : douta <= 16'h2F2A ; +1392 : douta <= 16'h302A ; +1393 : douta <= 16'h302A ; +1394 : douta <= 16'h302A ; +1395 : douta <= 16'h2F2A ; +1396 : douta <= 16'h302A ; +1397 : douta <= 16'h2F2A ; +1398 : douta <= 16'h2F2A ; +1399 : douta <= 16'h2F2A ; +1400 : douta <= 16'h2E2A ; +1401 : douta <= 16'h2E2A ; +1402 : douta <= 16'h2D2A ; +1403 : douta <= 16'h2D2A ; +1404 : douta <= 16'h2D2A ; +1405 : douta <= 16'h2D2A ; +1406 : douta <= 16'h2E2A ; +1407 : douta <= 16'h2E2A ; +1408 : douta <= 16'h2E2A ; +1409 : douta <= 16'h2E2A ; +1410 : douta <= 16'h2E2A ; +1411 : douta <= 16'h2E2A ; +1412 : douta <= 16'h2E2A ; +1413 : douta <= 16'h2E2A ; +1414 : douta <= 16'h2E2A ; +1415 : douta <= 16'h2E2A ; +1416 : douta <= 16'h2E2A ; +1417 : douta <= 16'h2E2A ; +1418 : douta <= 16'h2E2A ; +1419 : douta <= 16'h2E2A ; +1420 : douta <= 16'h2E2A ; +1421 : douta <= 16'h2E2A ; +1422 : douta <= 16'h2E2A ; +1423 : douta <= 16'h2E2A ; +1424 : douta <= 16'h2E2A ; +1425 : douta <= 16'h2E2A ; +1426 : douta <= 16'h2E2A ; +1427 : douta <= 16'h2D2A ; +1428 : douta <= 16'h2E2A ; +1429 : douta <= 16'h2D2A ; +1430 : douta <= 16'h2D2A ; +1431 : douta <= 16'h2D2A ; +1432 : douta <= 16'h2D2A ; +1433 : douta <= 16'h2D2A ; +1434 : douta <= 16'h2D2A ; +1435 : douta <= 16'h2D2A ; +1436 : douta <= 16'h2D2A ; +1437 : douta <= 16'h2D2A ; +1438 : douta <= 16'h2D2A ; +1439 : douta <= 16'h2D2A ; +1440 : douta <= 16'h2D2A ; +1441 : douta <= 16'h2D2A ; +1442 : douta <= 16'h2D2A ; +1443 : douta <= 16'h2C2A ; +1444 : douta <= 16'h2D2A ; +1445 : douta <= 16'h2C2A ; +1446 : douta <= 16'h2D2A ; +1447 : douta <= 16'h2D2A ; +1448 : douta <= 16'h2D2A ; +1449 : douta <= 16'h2D2A ; +1450 : douta <= 16'h2D2A ; +1451 : douta <= 16'h2D2A ; +1452 : douta <= 16'h2D2A ; +1453 : douta <= 16'h2D2A ; +1454 : douta <= 16'h2D2A ; +1455 : douta <= 16'h2D2A ; +1456 : douta <= 16'h2C2A ; +1457 : douta <= 16'h2C2A ; +1458 : douta <= 16'h2C2A ; +1459 : douta <= 16'h2B2A ; +1460 : douta <= 16'h2B2A ; +1461 : douta <= 16'h2C2A ; +1462 : douta <= 16'h2C2A ; +1463 : douta <= 16'h2C2A ; +1464 : douta <= 16'h2C2A ; +1465 : douta <= 16'h2C2A ; +1466 : douta <= 16'h2C2A ; +1467 : douta <= 16'h2C2A ; +1468 : douta <= 16'h2C2A ; +1469 : douta <= 16'h2C2A ; +1470 : douta <= 16'h2C2A ; +1471 : douta <= 16'h2C2A ; +1472 : douta <= 16'h2C2A ; +1473 : douta <= 16'h2C2A ; +1474 : douta <= 16'h2C2A ; +1475 : douta <= 16'h2C2A ; +1476 : douta <= 16'h2C2A ; +1477 : douta <= 16'h2C2A ; +1478 : douta <= 16'h2C2A ; +1479 : douta <= 16'h2C2A ; +1480 : douta <= 16'h2C2A ; +1481 : douta <= 16'h2C2A ; +1482 : douta <= 16'h2C2A ; +1483 : douta <= 16'h2C2A ; +1484 : douta <= 16'h2C2A ; +1485 : douta <= 16'h2B2A ; +1486 : douta <= 16'h2B2A ; +1487 : douta <= 16'h2B2A ; +1488 : douta <= 16'h2B2A ; +1489 : douta <= 16'h2A2A ; +1490 : douta <= 16'h2B2A ; +1491 : douta <= 16'h2A2A ; +1492 : douta <= 16'h2A2A ; +1493 : douta <= 16'h2A2A ; +1494 : douta <= 16'h2A2A ; +1495 : douta <= 16'h2A2A ; +1496 : douta <= 16'h2A2A ; +1497 : douta <= 16'h2A2A ; +1498 : douta <= 16'h2A2A ; +1499 : douta <= 16'h2A2A ; +1500 : douta <= 16'h292A ; +1501 : douta <= 16'h292A ; +1502 : douta <= 16'h292A ; +1503 : douta <= 16'h2A2A ; +1504 : douta <= 16'h2A2A ; +1505 : douta <= 16'h2A2A ; +1506 : douta <= 16'h2A2A ; +1507 : douta <= 16'h2A2A ; +1508 : douta <= 16'h2A2A ; +1509 : douta <= 16'h2A2A ; +1510 : douta <= 16'h2A2A ; +1511 : douta <= 16'h2A2A ; +1512 : douta <= 16'h2A2A ; +1513 : douta <= 16'h2A2A ; +1514 : douta <= 16'h2A2A ; +1515 : douta <= 16'h292A ; +1516 : douta <= 16'h292A ; +1517 : douta <= 16'h292A ; +1518 : douta <= 16'h292A ; +1519 : douta <= 16'h292A ; +1520 : douta <= 16'h292A ; +1521 : douta <= 16'h292A ; +1522 : douta <= 16'h292A ; +1523 : douta <= 16'h292A ; +1524 : douta <= 16'h292A ; +1525 : douta <= 16'h292A ; +1526 : douta <= 16'h292A ; +1527 : douta <= 16'h292A ; +1528 : douta <= 16'h292A ; +1529 : douta <= 16'h292A ; +1530 : douta <= 16'h292A ; +1531 : douta <= 16'h292A ; +1532 : douta <= 16'h282A ; +1533 : douta <= 16'h282A ; +1534 : douta <= 16'h282A ; +1535 : douta <= 16'h292A ; +1536 : douta <= 16'h292A ; +1537 : douta <= 16'h292A ; +1538 : douta <= 16'h292A ; +1539 : douta <= 16'h292A ; +1540 : douta <= 16'h292A ; +1541 : douta <= 16'h292A ; +1542 : douta <= 16'h272A ; +1543 : douta <= 16'h292A ; +1544 : douta <= 16'h272A ; +1545 : douta <= 16'h272A ; +1546 : douta <= 16'h282A ; +1547 : douta <= 16'h282A ; +1548 : douta <= 16'h282A ; +1549 : douta <= 16'h282A ; +1550 : douta <= 16'h282A ; +1551 : douta <= 16'h282A ; +1552 : douta <= 16'h282A ; +1553 : douta <= 16'h282A ; +1554 : douta <= 16'h282A ; +1555 : douta <= 16'h282A ; +1556 : douta <= 16'h282A ; +1557 : douta <= 16'h282A ; +1558 : douta <= 16'h282A ; +1559 : douta <= 16'h282A ; +1560 : douta <= 16'h282A ; +1561 : douta <= 16'h282A ; +1562 : douta <= 16'h282A ; +1563 : douta <= 16'h282A ; +1564 : douta <= 16'h282A ; +1565 : douta <= 16'h282A ; +1566 : douta <= 16'h282A ; +1567 : douta <= 16'h282A ; +1568 : douta <= 16'h282A ; +1569 : douta <= 16'h282A ; +1570 : douta <= 16'h282A ; +1571 : douta <= 16'h282A ; +1572 : douta <= 16'h282A ; +1573 : douta <= 16'h282A ; +1574 : douta <= 16'h282A ; +1575 : douta <= 16'h272A ; +1576 : douta <= 16'h272A ; +1577 : douta <= 16'h272A ; +1578 : douta <= 16'h272A ; +1579 : douta <= 16'h272A ; +1580 : douta <= 16'h272A ; +1581 : douta <= 16'h272A ; +1582 : douta <= 16'h272A ; +1583 : douta <= 16'h262A ; +1584 : douta <= 16'h262A ; +1585 : douta <= 16'h252A ; +1586 : douta <= 16'h252A ; +1587 : douta <= 16'h262A ; +1588 : douta <= 16'h262A ; +1589 : douta <= 16'h252A ; +1590 : douta <= 16'h262A ; +1591 : douta <= 16'h262A ; +1592 : douta <= 16'h262A ; +1593 : douta <= 16'h262A ; +1594 : douta <= 16'h262A ; +1595 : douta <= 16'h262A ; +1596 : douta <= 16'h262A ; +1597 : douta <= 16'h262A ; +1598 : douta <= 16'h262A ; +1599 : douta <= 16'h262A ; +1600 : douta <= 16'h262A ; +1601 : douta <= 16'h262A ; +1602 : douta <= 16'h262A ; +1603 : douta <= 16'h262A ; +1604 : douta <= 16'h262A ; +1605 : douta <= 16'h262A ; +1606 : douta <= 16'h262A ; +1607 : douta <= 16'h262A ; +1608 : douta <= 16'h262A ; +1609 : douta <= 16'h252A ; +1610 : douta <= 16'h252A ; +1611 : douta <= 16'h252A ; +1612 : douta <= 16'h252A ; +1613 : douta <= 16'h252A ; +1614 : douta <= 16'h252A ; +1615 : douta <= 16'h252A ; +1616 : douta <= 16'h252A ; +1617 : douta <= 16'h252A ; +1618 : douta <= 16'h252A ; +1619 : douta <= 16'h252A ; +1620 : douta <= 16'h252A ; +1621 : douta <= 16'h252A ; +1622 : douta <= 16'h252A ; +1623 : douta <= 16'h252A ; +1624 : douta <= 16'h252A ; +1625 : douta <= 16'h242A ; +1626 : douta <= 16'h252A ; +1627 : douta <= 16'h252A ; +1628 : douta <= 16'h252A ; +1629 : douta <= 16'h252A ; +1630 : douta <= 16'h252A ; +1631 : douta <= 16'h252A ; +1632 : douta <= 16'h252A ; +1633 : douta <= 16'h252A ; +1634 : douta <= 16'h252A ; +1635 : douta <= 16'h252A ; +1636 : douta <= 16'h252A ; +1637 : douta <= 16'h252A ; +1638 : douta <= 16'h242A ; +1639 : douta <= 16'h242A ; +1640 : douta <= 16'h242A ; +1641 : douta <= 16'h242A ; +1642 : douta <= 16'h242A ; +1643 : douta <= 16'h242A ; +1644 : douta <= 16'h242A ; +1645 : douta <= 16'h242A ; +1646 : douta <= 16'h242A ; +1647 : douta <= 16'h242A ; +1648 : douta <= 16'h242A ; +1649 : douta <= 16'h242A ; +1650 : douta <= 16'h242A ; +1651 : douta <= 16'h242A ; +1652 : douta <= 16'h232A ; +1653 : douta <= 16'h232A ; +1654 : douta <= 16'h242A ; +1655 : douta <= 16'h242A ; +1656 : douta <= 16'h242A ; +1657 : douta <= 16'h242A ; +1658 : douta <= 16'h242A ; +1659 : douta <= 16'h242A ; +1660 : douta <= 16'h242A ; +1661 : douta <= 16'h242A ; +1662 : douta <= 16'h242A ; +1663 : douta <= 16'h242A ; +1664 : douta <= 16'h242A ; +1665 : douta <= 16'h232A ; +1666 : douta <= 16'h232A ; +1667 : douta <= 16'h232A ; +1668 : douta <= 16'h232A ; +1669 : douta <= 16'h232A ; +1670 : douta <= 16'h232A ; +1671 : douta <= 16'h232A ; +1672 : douta <= 16'h222A ; +1673 : douta <= 16'h222A ; +1674 : douta <= 16'h222A ; +1675 : douta <= 16'h222A ; +1676 : douta <= 16'h222A ; +1677 : douta <= 16'h222A ; +1678 : douta <= 16'h222A ; +1679 : douta <= 16'h222A ; +1680 : douta <= 16'h222A ; +1681 : douta <= 16'h212A ; +1682 : douta <= 16'h222A ; +1683 : douta <= 16'h212A ; +1684 : douta <= 16'h222A ; +1685 : douta <= 16'h222A ; +1686 : douta <= 16'h222A ; +1687 : douta <= 16'h222A ; +1688 : douta <= 16'h222A ; +1689 : douta <= 16'h222A ; +1690 : douta <= 16'h222A ; +1691 : douta <= 16'h222A ; +1692 : douta <= 16'h222A ; +1693 : douta <= 16'h222A ; +1694 : douta <= 16'h222A ; +1695 : douta <= 16'h222A ; +1696 : douta <= 16'h222A ; +1697 : douta <= 16'h222A ; +1698 : douta <= 16'h222A ; +1699 : douta <= 16'h212A ; +1700 : douta <= 16'h212A ; +1701 : douta <= 16'h212A ; +1702 : douta <= 16'h212A ; +1703 : douta <= 16'h212A ; +1704 : douta <= 16'h212A ; +1705 : douta <= 16'h212A ; +1706 : douta <= 16'h212A ; +1707 : douta <= 16'h212A ; +1708 : douta <= 16'h212A ; +1709 : douta <= 16'h212A ; +1710 : douta <= 16'h212A ; +1711 : douta <= 16'h212A ; +1712 : douta <= 16'h212A ; +1713 : douta <= 16'h212A ; +1714 : douta <= 16'h202A ; +1715 : douta <= 16'h202A ; +1716 : douta <= 16'h212A ; +1717 : douta <= 16'h212A ; +1718 : douta <= 16'h212A ; +1719 : douta <= 16'h212A ; +1720 : douta <= 16'h212A ; +1721 : douta <= 16'h212A ; +1722 : douta <= 16'h212A ; +1723 : douta <= 16'h212A ; +1724 : douta <= 16'h212A ; +1725 : douta <= 16'h212A ; +1726 : douta <= 16'h202A ; +1727 : douta <= 16'h212A ; +1728 : douta <= 16'h202A ; +1729 : douta <= 16'h202A ; +1730 : douta <= 16'h202A ; +1731 : douta <= 16'h202A ; +1732 : douta <= 16'h202A ; +1733 : douta <= 16'h202A ; +1734 : douta <= 16'h202A ; +1735 : douta <= 16'h202A ; +1736 : douta <= 16'h202A ; +1737 : douta <= 16'h202A ; +1738 : douta <= 16'h202A ; +1739 : douta <= 16'h202A ; +1740 : douta <= 16'h202A ; +1741 : douta <= 16'h202A ; +1742 : douta <= 16'h202A ; +1743 : douta <= 16'h202A ; +1744 : douta <= 16'h202A ; +1745 : douta <= 16'h202A ; +1746 : douta <= 16'h202A ; +1747 : douta <= 16'h202A ; +1748 : douta <= 16'h202A ; +1749 : douta <= 16'h202A ; +1750 : douta <= 16'h202A ; +1751 : douta <= 16'h1F2C ; +1752 : douta <= 16'h202A ; +1753 : douta <= 16'h202A ; +1754 : douta <= 16'h202A ; +1755 : douta <= 16'h202A ; +1756 : douta <= 16'h202A ; +1757 : douta <= 16'h1D2C ; +1758 : douta <= 16'h202A ; +1759 : douta <= 16'h202A ; +1760 : douta <= 16'h202A ; +1761 : douta <= 16'h202A ; +1762 : douta <= 16'h1E2C ; +1763 : douta <= 16'h202A ; +1764 : douta <= 16'h202A ; +1765 : douta <= 16'h202A ; +1766 : douta <= 16'h202A ; +1767 : douta <= 16'h1E2C ; +1768 : douta <= 16'h202A ; +1769 : douta <= 16'h1E2C ; +1770 : douta <= 16'h1E2C ; +1771 : douta <= 16'h1E2C ; +1772 : douta <= 16'h1E2C ; +1773 : douta <= 16'h1E2C ; +1774 : douta <= 16'h1E2C ; +1775 : douta <= 16'h1E2C ; +1776 : douta <= 16'h1E2C ; +1777 : douta <= 16'h1E2C ; +1778 : douta <= 16'h1E2C ; +1779 : douta <= 16'h1E2C ; +1780 : douta <= 16'h1E2C ; +1781 : douta <= 16'h1E2C ; +1782 : douta <= 16'h1E2C ; +1783 : douta <= 16'h1D2C ; +1784 : douta <= 16'h1D2C ; +1785 : douta <= 16'h1D2C ; +1786 : douta <= 16'h1D2C ; +1787 : douta <= 16'h1D2C ; +1788 : douta <= 16'h1D2C ; +1789 : douta <= 16'h1D2C ; +1790 : douta <= 16'h1D2C ; +1791 : douta <= 16'h1D2C ; +1792 : douta <= 16'h1D2C ; +1793 : douta <= 16'h1D2C ; +1794 : douta <= 16'h1D2C ; +1795 : douta <= 16'h1D2C ; +1796 : douta <= 16'h1D2C ; +1797 : douta <= 16'h1C2C ; +1798 : douta <= 16'h1C2C ; +1799 : douta <= 16'h1C2C ; +1800 : douta <= 16'h1C2C ; +1801 : douta <= 16'h1D2C ; +1802 : douta <= 16'h1D2C ; +1803 : douta <= 16'h1D2C ; +1804 : douta <= 16'h1D2C ; +1805 : douta <= 16'h1D2C ; +1806 : douta <= 16'h1D2C ; +1807 : douta <= 16'h1D2C ; +1808 : douta <= 16'h1D2C ; +1809 : douta <= 16'h1D2C ; +1810 : douta <= 16'h1D2C ; +1811 : douta <= 16'h1C2C ; +1812 : douta <= 16'h1C2C ; +1813 : douta <= 16'h1C2C ; +1814 : douta <= 16'h1C2C ; +1815 : douta <= 16'h1C2C ; +1816 : douta <= 16'h1C2C ; +1817 : douta <= 16'h1B2C ; +1818 : douta <= 16'h1C2C ; +1819 : douta <= 16'h1B2C ; +1820 : douta <= 16'h1B2C ; +1821 : douta <= 16'h1B2C ; +1822 : douta <= 16'h1C2C ; +1823 : douta <= 16'h1C2C ; +1824 : douta <= 16'h1C2C ; +1825 : douta <= 16'h1C2C ; +1826 : douta <= 16'h1C2C ; +1827 : douta <= 16'h1C2C ; +1828 : douta <= 16'h1C2C ; +1829 : douta <= 16'h1C2C ; +1830 : douta <= 16'h1C2C ; +1831 : douta <= 16'h1C2C ; +1832 : douta <= 16'h1C2C ; +1833 : douta <= 16'h1C2C ; +1834 : douta <= 16'h1C2C ; +1835 : douta <= 16'h1C2C ; +1836 : douta <= 16'h1C2C ; +1837 : douta <= 16'h1C2C ; +1838 : douta <= 16'h1C2C ; +1839 : douta <= 16'h1C2C ; +1840 : douta <= 16'h1B2C ; +1841 : douta <= 16'h1B2C ; +1842 : douta <= 16'h1B2C ; +1843 : douta <= 16'h1B2C ; +1844 : douta <= 16'h1B2C ; +1845 : douta <= 16'h1B2C ; +1846 : douta <= 16'h1B2C ; +1847 : douta <= 16'h1B2C ; +1848 : douta <= 16'h1B2C ; +1849 : douta <= 16'h1B2C ; +1850 : douta <= 16'h1A2C ; +1851 : douta <= 16'h1A2C ; +1852 : douta <= 16'h1A2C ; +1853 : douta <= 16'h1A2C ; +1854 : douta <= 16'h1A2C ; +1855 : douta <= 16'h1A2C ; +1856 : douta <= 16'h192C ; +1857 : douta <= 16'h192C ; +1858 : douta <= 16'h192C ; +1859 : douta <= 16'h1A2C ; +1860 : douta <= 16'h1A2C ; +1861 : douta <= 16'h1A2C ; +1862 : douta <= 16'h1A2C ; +1863 : douta <= 16'h1A2C ; +1864 : douta <= 16'h1A2C ; +1865 : douta <= 16'h1A2C ; +1866 : douta <= 16'h1A2C ; +1867 : douta <= 16'h1A2C ; +1868 : douta <= 16'h1A2C ; +1869 : douta <= 16'h1A2C ; +1870 : douta <= 16'h1A2C ; +1871 : douta <= 16'h1A2C ; +1872 : douta <= 16'h1A2C ; +1873 : douta <= 16'h1A2C ; +1874 : douta <= 16'h1A2C ; +1875 : douta <= 16'h1A2C ; +1876 : douta <= 16'h1A2C ; +1877 : douta <= 16'h1A2C ; +1878 : douta <= 16'h192C ; +1879 : douta <= 16'h192C ; +1880 : douta <= 16'h192C ; +1881 : douta <= 16'h192C ; +1882 : douta <= 16'h192C ; +1883 : douta <= 16'h192C ; +1884 : douta <= 16'h192C ; +1885 : douta <= 16'h192C ; +1886 : douta <= 16'h192C ; +1887 : douta <= 16'h192C ; +1888 : douta <= 16'h192C ; +1889 : douta <= 16'h192C ; +1890 : douta <= 16'h192C ; +1891 : douta <= 16'h192C ; +1892 : douta <= 16'h182C ; +1893 : douta <= 16'h192C ; +1894 : douta <= 16'h192C ; +1895 : douta <= 16'h192C ; +1896 : douta <= 16'h192C ; +1897 : douta <= 16'h192C ; +1898 : douta <= 16'h192C ; +1899 : douta <= 16'h192C ; +1900 : douta <= 16'h192C ; +1901 : douta <= 16'h192C ; +1902 : douta <= 16'h192C ; +1903 : douta <= 16'h192C ; +1904 : douta <= 16'h192C ; +1905 : douta <= 16'h192C ; +1906 : douta <= 16'h182C ; +1907 : douta <= 16'h182C ; +1908 : douta <= 16'h182C ; +1909 : douta <= 16'h172C ; +1910 : douta <= 16'h182C ; +1911 : douta <= 16'h172C ; +1912 : douta <= 16'h172C ; +1913 : douta <= 16'h172C ; +1914 : douta <= 16'h182C ; +1915 : douta <= 16'h182C ; +1916 : douta <= 16'h182C ; +1917 : douta <= 16'h182C ; +1918 : douta <= 16'h182C ; +1919 : douta <= 16'h182C ; +1920 : douta <= 16'h182C ; +1921 : douta <= 16'h182C ; +1922 : douta <= 16'h182C ; +1923 : douta <= 16'h182C ; +1924 : douta <= 16'h182C ; +1925 : douta <= 16'h182C ; +1926 : douta <= 16'h182C ; +1927 : douta <= 16'h182C ; +1928 : douta <= 16'h182C ; +1929 : douta <= 16'h182C ; +1930 : douta <= 16'h182C ; +1931 : douta <= 16'h182C ; +1932 : douta <= 16'h182C ; +1933 : douta <= 16'h182C ; +1934 : douta <= 16'h182C ; +1935 : douta <= 16'h172C ; +1936 : douta <= 16'h172C ; +1937 : douta <= 16'h172C ; +1938 : douta <= 16'h172C ; +1939 : douta <= 16'h172C ; +1940 : douta <= 16'h172C ; +1941 : douta <= 16'h172C ; +1942 : douta <= 16'h172C ; +1943 : douta <= 16'h152C ; +1944 : douta <= 16'h152C ; +1945 : douta <= 16'h152C ; +1946 : douta <= 16'h152C ; +1947 : douta <= 16'h152C ; +1948 : douta <= 16'h162C ; +1949 : douta <= 16'h162C ; +1950 : douta <= 16'h162C ; +1951 : douta <= 16'h162C ; +1952 : douta <= 16'h162C ; +1953 : douta <= 16'h162C ; +1954 : douta <= 16'h162C ; +1955 : douta <= 16'h162C ; +1956 : douta <= 16'h162C ; +1957 : douta <= 16'h162C ; +1958 : douta <= 16'h162C ; +1959 : douta <= 16'h162C ; +1960 : douta <= 16'h162C ; +1961 : douta <= 16'h162C ; +1962 : douta <= 16'h162C ; +1963 : douta <= 16'h162C ; +1964 : douta <= 16'h162C ; +1965 : douta <= 16'h162C ; +1966 : douta <= 16'h162C ; +1967 : douta <= 16'h162C ; +1968 : douta <= 16'h162C ; +1969 : douta <= 16'h162C ; +1970 : douta <= 16'h162C ; +1971 : douta <= 16'h162C ; +1972 : douta <= 16'h152C ; +1973 : douta <= 16'h152C ; +1974 : douta <= 16'h152C ; +1975 : douta <= 16'h152C ; +1976 : douta <= 16'h152C ; +1977 : douta <= 16'h152C ; +1978 : douta <= 16'h152C ; +1979 : douta <= 16'h152C ; +1980 : douta <= 16'h152C ; +1981 : douta <= 16'h152C ; +1982 : douta <= 16'h152C ; +1983 : douta <= 16'h152C ; +1984 : douta <= 16'h152C ; +1985 : douta <= 16'h152C ; +1986 : douta <= 16'h152C ; +1987 : douta <= 16'h142C ; +1988 : douta <= 16'h142C ; +1989 : douta <= 16'h152C ; +1990 : douta <= 16'h152C ; +1991 : douta <= 16'h152C ; +1992 : douta <= 16'h152C ; +1993 : douta <= 16'h152C ; +1994 : douta <= 16'h152C ; +1995 : douta <= 16'h152C ; +1996 : douta <= 16'h152C ; +1997 : douta <= 16'h152C ; +1998 : douta <= 16'h152C ; +1999 : douta <= 16'h152C ; +2000 : douta <= 16'h152C ; +2001 : douta <= 16'h152C ; +2002 : douta <= 16'h142C ; +2003 : douta <= 16'h142C ; +2004 : douta <= 16'h142C ; +2005 : douta <= 16'h142C ; +2006 : douta <= 16'h142C ; +2007 : douta <= 16'h142C ; +2008 : douta <= 16'h142C ; +2009 : douta <= 16'h142C ; +2010 : douta <= 16'h142C ; +2011 : douta <= 16'h142C ; +2012 : douta <= 16'h142C ; +2013 : douta <= 16'h142C ; +2014 : douta <= 16'h142C ; +2015 : douta <= 16'h142C ; +2016 : douta <= 16'h142C ; +2017 : douta <= 16'h142C ; +2018 : douta <= 16'h142C ; +2019 : douta <= 16'h122C ; +2020 : douta <= 16'h132C ; +2021 : douta <= 16'h142C ; +2022 : douta <= 16'h142C ; +2023 : douta <= 16'h142C ; +2024 : douta <= 16'h142C ; +2025 : douta <= 16'h142C ; +2026 : douta <= 16'h142C ; +2027 : douta <= 16'h132C ; +2028 : douta <= 16'h132C ; +2029 : douta <= 16'h132C ; +2030 : douta <= 16'h132C ; +2031 : douta <= 16'h132C ; +2032 : douta <= 16'h132C ; +2033 : douta <= 16'h132C ; +2034 : douta <= 16'h132C ; +2035 : douta <= 16'h132C ; +2036 : douta <= 16'h132C ; +2037 : douta <= 16'h122C ; +2038 : douta <= 16'h132C ; +2039 : douta <= 16'h122C ; +2040 : douta <= 16'h122C ; +2041 : douta <= 16'h122C ; +2042 : douta <= 16'h122C ; +2043 : douta <= 16'h112C ; +2044 : douta <= 16'h122C ; +2045 : douta <= 16'h112C ; +2046 : douta <= 16'h122C ; +2047 : douta <= 16'h122C ; +2048 : douta <= 16'h122C ; +2049 : douta <= 16'h122C ; +2050 : douta <= 16'h122C ; +2051 : douta <= 16'h122C ; +2052 : douta <= 16'h122C ; +2053 : douta <= 16'h122C ; +2054 : douta <= 16'h122C ; +2055 : douta <= 16'h122C ; +2056 : douta <= 16'h122C ; +2057 : douta <= 16'h122C ; +2058 : douta <= 16'h122C ; +2059 : douta <= 16'h122C ; +2060 : douta <= 16'h122C ; +2061 : douta <= 16'h122C ; +2062 : douta <= 16'h122C ; +2063 : douta <= 16'h122C ; +2064 : douta <= 16'h122C ; +2065 : douta <= 16'h122C ; +2066 : douta <= 16'h112C ; +2067 : douta <= 16'h112C ; +2068 : douta <= 16'h112C ; +2069 : douta <= 16'h112C ; +2070 : douta <= 16'h112C ; +2071 : douta <= 16'h112C ; +2072 : douta <= 16'h112C ; +2073 : douta <= 16'h112C ; +2074 : douta <= 16'h112C ; +2075 : douta <= 16'h112C ; +2076 : douta <= 16'h112C ; +2077 : douta <= 16'h112C ; +2078 : douta <= 16'h112C ; +2079 : douta <= 16'h112C ; +2080 : douta <= 16'h112C ; +2081 : douta <= 16'h102C ; +2082 : douta <= 16'h102C ; +2083 : douta <= 16'h102C ; +2084 : douta <= 16'h102C ; +2085 : douta <= 16'h112C ; +2086 : douta <= 16'h112C ; +2087 : douta <= 16'h112C ; +2088 : douta <= 16'h112C ; +2089 : douta <= 16'h112C ; +2090 : douta <= 16'h112C ; +2091 : douta <= 16'h0F2C ; +2092 : douta <= 16'h112C ; +2093 : douta <= 16'h112C ; +2094 : douta <= 16'h112C ; +2095 : douta <= 16'h102C ; +2096 : douta <= 16'h102C ; +2097 : douta <= 16'h102C ; +2098 : douta <= 16'h102C ; +2099 : douta <= 16'h102C ; +2100 : douta <= 16'h102C ; +2101 : douta <= 16'h102C ; +2102 : douta <= 16'h102C ; +2103 : douta <= 16'h102C ; +2104 : douta <= 16'h102C ; +2105 : douta <= 16'h102C ; +2106 : douta <= 16'h102C ; +2107 : douta <= 16'h102C ; +2108 : douta <= 16'h0E2C ; +2109 : douta <= 16'h102C ; +2110 : douta <= 16'h102C ; +2111 : douta <= 16'h102C ; +2112 : douta <= 16'h102C ; +2113 : douta <= 16'h102C ; +2114 : douta <= 16'h102C ; +2115 : douta <= 16'h102C ; +2116 : douta <= 16'h102C ; +2117 : douta <= 16'h102C ; +2118 : douta <= 16'h102C ; +2119 : douta <= 16'h102C ; +2120 : douta <= 16'h102C ; +2121 : douta <= 16'h102C ; +2122 : douta <= 16'h102C ; +2123 : douta <= 16'h102C ; +2124 : douta <= 16'h0F2C ; +2125 : douta <= 16'h0F2C ; +2126 : douta <= 16'h0F2C ; +2127 : douta <= 16'h0E2C ; +2128 : douta <= 16'h0F2C ; +2129 : douta <= 16'h0F2C ; +2130 : douta <= 16'h0F2C ; +2131 : douta <= 16'h0E2C ; +2132 : douta <= 16'h0E2C ; +2133 : douta <= 16'h0D2C ; +2134 : douta <= 16'h0D2C ; +2135 : douta <= 16'h0D2C ; +2136 : douta <= 16'h0E2C ; +2137 : douta <= 16'h0E2C ; +2138 : douta <= 16'h0E2C ; +2139 : douta <= 16'h0E2C ; +2140 : douta <= 16'h0E2C ; +2141 : douta <= 16'h0E2C ; +2142 : douta <= 16'h0E2C ; +2143 : douta <= 16'h0E2C ; +2144 : douta <= 16'h0E2C ; +2145 : douta <= 16'h0E2C ; +2146 : douta <= 16'h0E2C ; +2147 : douta <= 16'h0E2C ; +2148 : douta <= 16'h0E2C ; +2149 : douta <= 16'h0E2C ; +2150 : douta <= 16'h0E2C ; +2151 : douta <= 16'h0E2C ; +2152 : douta <= 16'h0E2C ; +2153 : douta <= 16'h0E2C ; +2154 : douta <= 16'h0E2C ; +2155 : douta <= 16'h0E2C ; +2156 : douta <= 16'h0E2C ; +2157 : douta <= 16'h0E2C ; +2158 : douta <= 16'h0D2C ; +2159 : douta <= 16'h0D2C ; +2160 : douta <= 16'h0D2C ; +2161 : douta <= 16'h0D2C ; +2162 : douta <= 16'h0D2C ; +2163 : douta <= 16'h0D2C ; +2164 : douta <= 16'h0D2C ; +2165 : douta <= 16'h0D2C ; +2166 : douta <= 16'h0D2C ; +2167 : douta <= 16'h0D2C ; +2168 : douta <= 16'h0D2C ; +2169 : douta <= 16'h0D2C ; +2170 : douta <= 16'h0D2C ; +2171 : douta <= 16'h0D2C ; +2172 : douta <= 16'h0C2C ; +2173 : douta <= 16'h0C2C ; +2174 : douta <= 16'h0C2C ; +2175 : douta <= 16'h0D2C ; +2176 : douta <= 16'h0C2C ; +2177 : douta <= 16'h0D2C ; +2178 : douta <= 16'h0D2C ; +2179 : douta <= 16'h0D2C ; +2180 : douta <= 16'h0D2C ; +2181 : douta <= 16'h0D2C ; +2182 : douta <= 16'h0D2C ; +2183 : douta <= 16'h0D2C ; +2184 : douta <= 16'h0D2C ; +2185 : douta <= 16'h0D2C ; +2186 : douta <= 16'h0D2C ; +2187 : douta <= 16'h0D2C ; +2188 : douta <= 16'h0D2C ; +2189 : douta <= 16'h0C2C ; +2190 : douta <= 16'h0C2C ; +2191 : douta <= 16'h0C2C ; +2192 : douta <= 16'h0C2C ; +2193 : douta <= 16'h0C2C ; +2194 : douta <= 16'h0C2C ; +2195 : douta <= 16'h0C2C ; +2196 : douta <= 16'h0B2C ; +2197 : douta <= 16'h0B2C ; +2198 : douta <= 16'h0B2C ; +2199 : douta <= 16'h0C2C ; +2200 : douta <= 16'h0C2C ; +2201 : douta <= 16'h0C2C ; +2202 : douta <= 16'h0C2C ; +2203 : douta <= 16'h0C2C ; +2204 : douta <= 16'h0C2C ; +2205 : douta <= 16'h0C2C ; +2206 : douta <= 16'h0C2C ; +2207 : douta <= 16'h0C2C ; +2208 : douta <= 16'h0C2C ; +2209 : douta <= 16'h0C2C ; +2210 : douta <= 16'h0C2C ; +2211 : douta <= 16'h0C2C ; +2212 : douta <= 16'h0C2C ; +2213 : douta <= 16'h0C2C ; +2214 : douta <= 16'h0C2C ; +2215 : douta <= 16'h0C2C ; +2216 : douta <= 16'h0C2C ; +2217 : douta <= 16'h0C2C ; +2218 : douta <= 16'h0C2C ; +2219 : douta <= 16'h0C2C ; +2220 : douta <= 16'h0B2C ; +2221 : douta <= 16'h0B2C ; +2222 : douta <= 16'h0B2C ; +2223 : douta <= 16'h0B2C ; +2224 : douta <= 16'h0B2C ; +2225 : douta <= 16'h0B2C ; +2226 : douta <= 16'h0A2C ; +2227 : douta <= 16'h0A2C ; +2228 : douta <= 16'h0A2C ; +2229 : douta <= 16'h0A2C ; +2230 : douta <= 16'h0A2C ; +2231 : douta <= 16'h0A2C ; +2232 : douta <= 16'h0A2C ; +2233 : douta <= 16'h0A2C ; +2234 : douta <= 16'h92C ; +2235 : douta <= 16'h0A2C ; +2236 : douta <= 16'h0A2C ; +2237 : douta <= 16'h92C ; +2238 : douta <= 16'h0A2C ; +2239 : douta <= 16'h0A2C ; +2240 : douta <= 16'h0A2C ; +2241 : douta <= 16'h0A2C ; +2242 : douta <= 16'h0A2C ; +2243 : douta <= 16'h0A2C ; +2244 : douta <= 16'h0A2C ; +2245 : douta <= 16'h0A2C ; +2246 : douta <= 16'h0A2C ; +2247 : douta <= 16'h0A2C ; +2248 : douta <= 16'h0A2C ; +2249 : douta <= 16'h0A2C ; +2250 : douta <= 16'h0A2C ; +2251 : douta <= 16'h0A2C ; +2252 : douta <= 16'h0A2C ; +2253 : douta <= 16'h92C ; +2254 : douta <= 16'h0A2C ; +2255 : douta <= 16'h92C ; +2256 : douta <= 16'h92C ; +2257 : douta <= 16'h92C ; +2258 : douta <= 16'h92C ; +2259 : douta <= 16'h92C ; +2260 : douta <= 16'h92C ; +2261 : douta <= 16'h92C ; +2262 : douta <= 16'h92C ; +2263 : douta <= 16'h92C ; +2264 : douta <= 16'h92C ; +2265 : douta <= 16'h92C ; +2266 : douta <= 16'h92C ; +2267 : douta <= 16'h92C ; +2268 : douta <= 16'h92C ; +2269 : douta <= 16'h92C ; +2270 : douta <= 16'h82C ; +2271 : douta <= 16'h82C ; +2272 : douta <= 16'h92C ; +2273 : douta <= 16'h92C ; +2274 : douta <= 16'h82C ; +2275 : douta <= 16'h92C ; +2276 : douta <= 16'h92C ; +2277 : douta <= 16'h92C ; +2278 : douta <= 16'h92C ; +2279 : douta <= 16'h92C ; +2280 : douta <= 16'h92C ; +2281 : douta <= 16'h92C ; +2282 : douta <= 16'h92C ; +2283 : douta <= 16'h92C ; +2284 : douta <= 16'h92C ; +2285 : douta <= 16'h92C ; +2286 : douta <= 16'h92C ; +2287 : douta <= 16'h82C ; +2288 : douta <= 16'h82C ; +2289 : douta <= 16'h82C ; +2290 : douta <= 16'h82C ; +2291 : douta <= 16'h82C ; +2292 : douta <= 16'h82C ; +2293 : douta <= 16'h82C ; +2294 : douta <= 16'h82C ; +2295 : douta <= 16'h82C ; +2296 : douta <= 16'h82C ; +2297 : douta <= 16'h82C ; +2298 : douta <= 16'h82C ; +2299 : douta <= 16'h82C ; +2300 : douta <= 16'h82C ; +2301 : douta <= 16'h82C ; +2302 : douta <= 16'h82C ; +2303 : douta <= 16'h82C ; +2304 : douta <= 16'h82C ; +2305 : douta <= 16'h82C ; +2306 : douta <= 16'h82C ; +2307 : douta <= 16'h82C ; +2308 : douta <= 16'h82C ; +2309 : douta <= 16'h82C ; +2310 : douta <= 16'h82C ; +2311 : douta <= 16'h82C ; +2312 : douta <= 16'h72C ; +2313 : douta <= 16'h72C ; +2314 : douta <= 16'h82C ; +2315 : douta <= 16'h82C ; +2316 : douta <= 16'h72C ; +2317 : douta <= 16'h72C ; +2318 : douta <= 16'h72C ; +2319 : douta <= 16'h72C ; +2320 : douta <= 16'h72C ; +2321 : douta <= 16'h72C ; +2322 : douta <= 16'h72C ; +2323 : douta <= 16'h72C ; +2324 : douta <= 16'h62C ; +2325 : douta <= 16'h62C ; +2326 : douta <= 16'h62C ; +2327 : douta <= 16'h52C ; +2328 : douta <= 16'h52C ; +2329 : douta <= 16'h52C ; +2330 : douta <= 16'h52C ; +2331 : douta <= 16'h62C ; +2332 : douta <= 16'h62C ; +2333 : douta <= 16'h62C ; +2334 : douta <= 16'h62C ; +2335 : douta <= 16'h62C ; +2336 : douta <= 16'h62C ; +2337 : douta <= 16'h62C ; +2338 : douta <= 16'h62C ; +2339 : douta <= 16'h62C ; +2340 : douta <= 16'h62C ; +2341 : douta <= 16'h62C ; +2342 : douta <= 16'h62C ; +2343 : douta <= 16'h62C ; +2344 : douta <= 16'h62C ; +2345 : douta <= 16'h62C ; +2346 : douta <= 16'h62C ; +2347 : douta <= 16'h62C ; +2348 : douta <= 16'h62C ; +2349 : douta <= 16'h62C ; +2350 : douta <= 16'h62C ; +2351 : douta <= 16'h62C ; +2352 : douta <= 16'h52C ; +2353 : douta <= 16'h52C ; +2354 : douta <= 16'h52C ; +2355 : douta <= 16'h52C ; +2356 : douta <= 16'h52C ; +2357 : douta <= 16'h52C ; +2358 : douta <= 16'h52C ; +2359 : douta <= 16'h52C ; +2360 : douta <= 16'h52C ; +2361 : douta <= 16'h52C ; +2362 : douta <= 16'h52C ; +2363 : douta <= 16'h52C ; +2364 : douta <= 16'h52C ; +2365 : douta <= 16'h52C ; +2366 : douta <= 16'h42C ; +2367 : douta <= 16'h42C ; +2368 : douta <= 16'h42C ; +2369 : douta <= 16'h42C ; +2370 : douta <= 16'h52C ; +2371 : douta <= 16'h52C ; +2372 : douta <= 16'h52C ; +2373 : douta <= 16'h52C ; +2374 : douta <= 16'h52C ; +2375 : douta <= 16'h52C ; +2376 : douta <= 16'h52C ; +2377 : douta <= 16'h52C ; +2378 : douta <= 16'h52C ; +2379 : douta <= 16'h52C ; +2380 : douta <= 16'h52C ; +2381 : douta <= 16'h52C ; +2382 : douta <= 16'h52C ; +2383 : douta <= 16'h42C ; +2384 : douta <= 16'h42C ; +2385 : douta <= 16'h42C ; +2386 : douta <= 16'h42C ; +2387 : douta <= 16'h42C ; +2388 : douta <= 16'h42C ; +2389 : douta <= 16'h42C ; +2390 : douta <= 16'h42C ; +2391 : douta <= 16'h42C ; +2392 : douta <= 16'h42C ; +2393 : douta <= 16'h42C ; +2394 : douta <= 16'h42C ; +2395 : douta <= 16'h42C ; +2396 : douta <= 16'h42C ; +2397 : douta <= 16'h42C ; +2398 : douta <= 16'h42C ; +2399 : douta <= 16'h42C ; +2400 : douta <= 16'h42C ; +2401 : douta <= 16'h22C ; +2402 : douta <= 16'h42C ; +2403 : douta <= 16'h42C ; +2404 : douta <= 16'h42C ; +2405 : douta <= 16'h42C ; +2406 : douta <= 16'h42C ; +2407 : douta <= 16'h42C ; +2408 : douta <= 16'h42C ; +2409 : douta <= 16'h42C ; +2410 : douta <= 16'h42C ; +2411 : douta <= 16'h42C ; +2412 : douta <= 16'h42C ; +2413 : douta <= 16'h32C ; +2414 : douta <= 16'h32C ; +2415 : douta <= 16'h32C ; +2416 : douta <= 16'h32C ; +2417 : douta <= 16'h32C ; +2418 : douta <= 16'h32C ; +2419 : douta <= 16'h32C ; +2420 : douta <= 16'h32C ; +2421 : douta <= 16'h32C ; +2422 : douta <= 16'h32C ; +2423 : douta <= 16'h22C ; +2424 : douta <= 16'h22C ; +2425 : douta <= 16'h22C ; +2426 : douta <= 16'h22C ; +2427 : douta <= 16'h22C ; +2428 : douta <= 16'h12C ; +2429 : douta <= 16'h22C ; +2430 : douta <= 16'h22C ; +2431 : douta <= 16'h22C ; +2432 : douta <= 16'h22C ; +2433 : douta <= 16'h22C ; +2434 : douta <= 16'h22C ; +2435 : douta <= 16'h22C ; +2436 : douta <= 16'h22C ; +2437 : douta <= 16'h22C ; +2438 : douta <= 16'h22C ; +2439 : douta <= 16'h22C ; +2440 : douta <= 16'h22C ; +2441 : douta <= 16'h22C ; +2442 : douta <= 16'h22C ; +2443 : douta <= 16'h22C ; +2444 : douta <= 16'h22C ; +2445 : douta <= 16'h22C ; +2446 : douta <= 16'h22C ; +2447 : douta <= 16'h22C ; +2448 : douta <= 16'h12C ; +2449 : douta <= 16'h12C ; +2450 : douta <= 16'h12C ; +2451 : douta <= 16'h12C ; +2452 : douta <= 16'h12C ; +2453 : douta <= 16'h12C ; +2454 : douta <= 16'h12C ; +2455 : douta <= 16'h12C ; +2456 : douta <= 16'h12C ; +2457 : douta <= 16'h12C ; +2458 : douta <= 16'h12C ; +2459 : douta <= 16'h12C ; +2460 : douta <= 16'h12C ; +2461 : douta <= 16'h12C ; +2462 : douta <= 16'h12C ; +2463 : douta <= 16'h02C ; +2464 : douta <= 16'h02C ; +2465 : douta <= 16'h12C ; +2466 : douta <= 16'h02C ; +2467 : douta <= 16'h12C ; +2468 : douta <= 16'h12C ; +2469 : douta <= 16'h12C ; +2470 : douta <= 16'h12C ; +2471 : douta <= 16'h12C ; +2472 : douta <= 16'h12C ; +2473 : douta <= 16'h12C ; +2474 : douta <= 16'h12C ; +2475 : douta <= 16'h12C ; +2476 : douta <= 16'h12C ; +2477 : douta <= 16'h12C ; +2478 : douta <= 16'h12C ; +2479 : douta <= 16'h02C ; +2480 : douta <= 16'h12C ; +2481 : douta <= 16'h02C ; +2482 : douta <= 16'h02C ; +2483 : douta <= 16'h02C ; +2484 : douta <= 16'hD040 ; +2485 : douta <= 16'h02C ; +2486 : douta <= 16'h02C ; +2487 : douta <= 16'h02C ; +2488 : douta <= 16'h02C ; +2489 : douta <= 16'h02C ; +2490 : douta <= 16'h02C ; +2491 : douta <= 16'h02C ; +2492 : douta <= 16'h02C ; +2493 : douta <= 16'hD040 ; +2494 : douta <= 16'h02C ; +2495 : douta <= 16'h02C ; +2496 : douta <= 16'h02C ; +2497 : douta <= 16'h02C ; +2498 : douta <= 16'h02C ; +2499 : douta <= 16'h02C ; +2500 : douta <= 16'h02C ; +2501 : douta <= 16'h02C ; +2502 : douta <= 16'h02C ; +2503 : douta <= 16'h02C ; +2504 : douta <= 16'h02C ; +2505 : douta <= 16'h02C ; +2506 : douta <= 16'h02C ; +2507 : douta <= 16'hCE40 ; +2508 : douta <= 16'h02C ; +2509 : douta <= 16'h02C ; +2510 : douta <= 16'hCE40 ; +2511 : douta <= 16'hCD40 ; +2512 : douta <= 16'hCD40 ; +2513 : douta <= 16'hCD40 ; +2514 : douta <= 16'hCD40 ; +2515 : douta <= 16'hCD40 ; +2516 : douta <= 16'hCD40 ; +2517 : douta <= 16'hCD40 ; +2518 : douta <= 16'hCD40 ; +2519 : douta <= 16'hCD40 ; +2520 : douta <= 16'hCD40 ; +2521 : douta <= 16'hCD40 ; +2522 : douta <= 16'hCC40 ; +2523 : douta <= 16'hCC40 ; +2524 : douta <= 16'hCC40 ; +2525 : douta <= 16'hCD40 ; +2526 : douta <= 16'hCD40 ; +2527 : douta <= 16'hCD40 ; +2528 : douta <= 16'hCD40 ; +2529 : douta <= 16'hCD40 ; +2530 : douta <= 16'hCC40 ; +2531 : douta <= 16'hCB40 ; +2532 : douta <= 16'hCB40 ; +2533 : douta <= 16'hCB40 ; +2534 : douta <= 16'hCB40 ; +2535 : douta <= 16'hCC40 ; +2536 : douta <= 16'hCC40 ; +2537 : douta <= 16'hCC40 ; +2538 : douta <= 16'hCC40 ; +2539 : douta <= 16'hCC40 ; +2540 : douta <= 16'hCC40 ; +2541 : douta <= 16'hCC40 ; +2542 : douta <= 16'hCC40 ; +2543 : douta <= 16'hCC40 ; +2544 : douta <= 16'hCC40 ; +2545 : douta <= 16'hCC40 ; +2546 : douta <= 16'hCC40 ; +2547 : douta <= 16'hCC40 ; +2548 : douta <= 16'hCC40 ; +2549 : douta <= 16'hCC40 ; +2550 : douta <= 16'hCB40 ; +2551 : douta <= 16'hCB40 ; +2552 : douta <= 16'hCB40 ; +2553 : douta <= 16'hCB40 ; +2554 : douta <= 16'hCB40 ; +2555 : douta <= 16'hCB40 ; +2556 : douta <= 16'hCA40 ; +2557 : douta <= 16'hCA40 ; +2558 : douta <= 16'hCA40 ; +2559 : douta <= 16'hCA40 ; +2560 : douta <= 16'hCA40 ; +2561 : douta <= 16'hCA40 ; +2562 : douta <= 16'hCA40 ; +2563 : douta <= 16'hCA40 ; +2564 : douta <= 16'hCA40 ; +2565 : douta <= 16'hCA40 ; +2566 : douta <= 16'hCA40 ; +2567 : douta <= 16'hC940 ; +2568 : douta <= 16'hCA40 ; +2569 : douta <= 16'hCA40 ; +2570 : douta <= 16'hCA40 ; +2571 : douta <= 16'hCA40 ; +2572 : douta <= 16'hCA40 ; +2573 : douta <= 16'hC940 ; +2574 : douta <= 16'hCA40 ; +2575 : douta <= 16'hC940 ; +2576 : douta <= 16'hC940 ; +2577 : douta <= 16'hC940 ; +2578 : douta <= 16'hC940 ; +2579 : douta <= 16'hC940 ; +2580 : douta <= 16'hC940 ; +2581 : douta <= 16'hC940 ; +2582 : douta <= 16'hC940 ; +2583 : douta <= 16'hC940 ; +2584 : douta <= 16'hC940 ; +2585 : douta <= 16'hC940 ; +2586 : douta <= 16'hC940 ; +2587 : douta <= 16'hC940 ; +2588 : douta <= 16'hC940 ; +2589 : douta <= 16'hC840 ; +2590 : douta <= 16'hC940 ; +2591 : douta <= 16'hC940 ; +2592 : douta <= 16'hC840 ; +2593 : douta <= 16'hC840 ; +2594 : douta <= 16'hC940 ; +2595 : douta <= 16'hC940 ; +2596 : douta <= 16'hC940 ; +2597 : douta <= 16'hC940 ; +2598 : douta <= 16'hC840 ; +2599 : douta <= 16'hC840 ; +2600 : douta <= 16'hC840 ; +2601 : douta <= 16'hC840 ; +2602 : douta <= 16'hC840 ; +2603 : douta <= 16'hC840 ; +2604 : douta <= 16'hC840 ; +2605 : douta <= 16'hC840 ; +2606 : douta <= 16'hC840 ; +2607 : douta <= 16'hC840 ; +2608 : douta <= 16'hC740 ; +2609 : douta <= 16'hC740 ; +2610 : douta <= 16'hC740 ; +2611 : douta <= 16'hC840 ; +2612 : douta <= 16'hC840 ; +2613 : douta <= 16'hC840 ; +2614 : douta <= 16'hC840 ; +2615 : douta <= 16'hC840 ; +2616 : douta <= 16'hC840 ; +2617 : douta <= 16'hC640 ; +2618 : douta <= 16'hC640 ; +2619 : douta <= 16'hC640 ; +2620 : douta <= 16'hC640 ; +2621 : douta <= 16'hC640 ; +2622 : douta <= 16'hC640 ; +2623 : douta <= 16'hC640 ; +2624 : douta <= 16'hC640 ; +2625 : douta <= 16'hC640 ; +2626 : douta <= 16'hC640 ; +2627 : douta <= 16'hC640 ; +2628 : douta <= 16'hC540 ; +2629 : douta <= 16'hC540 ; +2630 : douta <= 16'hC640 ; +2631 : douta <= 16'hC640 ; +2632 : douta <= 16'hC640 ; +2633 : douta <= 16'hC640 ; +2634 : douta <= 16'hC640 ; +2635 : douta <= 16'hC540 ; +2636 : douta <= 16'hC640 ; +2637 : douta <= 16'hC640 ; +2638 : douta <= 16'hC540 ; +2639 : douta <= 16'hC540 ; +2640 : douta <= 16'hC540 ; +2641 : douta <= 16'hC540 ; +2642 : douta <= 16'hC540 ; +2643 : douta <= 16'hC540 ; +2644 : douta <= 16'hC540 ; +2645 : douta <= 16'hC540 ; +2646 : douta <= 16'hC540 ; +2647 : douta <= 16'hC540 ; +2648 : douta <= 16'hC540 ; +2649 : douta <= 16'hC540 ; +2650 : douta <= 16'hC540 ; +2651 : douta <= 16'hC540 ; +2652 : douta <= 16'hC440 ; +2653 : douta <= 16'hC440 ; +2654 : douta <= 16'hC440 ; +2655 : douta <= 16'hC540 ; +2656 : douta <= 16'hC540 ; +2657 : douta <= 16'hC540 ; +2658 : douta <= 16'hC540 ; +2659 : douta <= 16'hC540 ; +2660 : douta <= 16'hC540 ; +2661 : douta <= 16'hC440 ; +2662 : douta <= 16'hC440 ; +2663 : douta <= 16'hC440 ; +2664 : douta <= 16'hC440 ; +2665 : douta <= 16'hC440 ; +2666 : douta <= 16'hC440 ; +2667 : douta <= 16'hC440 ; +2668 : douta <= 16'hC340 ; +2669 : douta <= 16'hC340 ; +2670 : douta <= 16'hC340 ; +2671 : douta <= 16'hC440 ; +2672 : douta <= 16'hC440 ; +2673 : douta <= 16'hC440 ; +2674 : douta <= 16'hC440 ; +2675 : douta <= 16'hC440 ; +2676 : douta <= 16'hC440 ; +2677 : douta <= 16'hC440 ; +2678 : douta <= 16'hC440 ; +2679 : douta <= 16'hC440 ; +2680 : douta <= 16'hC340 ; +2681 : douta <= 16'hC340 ; +2682 : douta <= 16'hC340 ; +2683 : douta <= 16'hC340 ; +2684 : douta <= 16'hC340 ; +2685 : douta <= 16'hC340 ; +2686 : douta <= 16'hC340 ; +2687 : douta <= 16'hC340 ; +2688 : douta <= 16'hC240 ; +2689 : douta <= 16'hC240 ; +2690 : douta <= 16'hC240 ; +2691 : douta <= 16'hC240 ; +2692 : douta <= 16'hC240 ; +2693 : douta <= 16'hC240 ; +2694 : douta <= 16'hC240 ; +2695 : douta <= 16'hC240 ; +2696 : douta <= 16'hC140 ; +2697 : douta <= 16'hC240 ; +2698 : douta <= 16'hC240 ; +2699 : douta <= 16'hC240 ; +2700 : douta <= 16'hC240 ; +2701 : douta <= 16'hC240 ; +2702 : douta <= 16'hC240 ; +2703 : douta <= 16'hC240 ; +2704 : douta <= 16'hC240 ; +2705 : douta <= 16'hC140 ; +2706 : douta <= 16'hC240 ; +2707 : douta <= 16'hC140 ; +2708 : douta <= 16'hC140 ; +2709 : douta <= 16'hC140 ; +2710 : douta <= 16'hC140 ; +2711 : douta <= 16'hC140 ; +2712 : douta <= 16'hC140 ; +2713 : douta <= 16'hC140 ; +2714 : douta <= 16'hC140 ; +2715 : douta <= 16'hC140 ; +2716 : douta <= 16'hC140 ; +2717 : douta <= 16'hC140 ; +2718 : douta <= 16'hC140 ; +2719 : douta <= 16'hC140 ; +2720 : douta <= 16'hC140 ; +2721 : douta <= 16'hC140 ; +2722 : douta <= 16'hC140 ; +2723 : douta <= 16'hC040 ; +2724 : douta <= 16'hC040 ; +2725 : douta <= 16'hC040 ; +2726 : douta <= 16'hC140 ; +2727 : douta <= 16'hC140 ; +2728 : douta <= 16'hC140 ; +2729 : douta <= 16'hC140 ; +2730 : douta <= 16'hC040 ; +2731 : douta <= 16'hC040 ; +2732 : douta <= 16'hC040 ; +2733 : douta <= 16'hC040 ; +2734 : douta <= 16'hC040 ; +2735 : douta <= 16'hC040 ; +2736 : douta <= 16'hC040 ; +2737 : douta <= 16'hC040 ; +2738 : douta <= 16'hC040 ; +2739 : douta <= 16'hC040 ; +2740 : douta <= 16'hC040 ; +2741 : douta <= 16'hC040 ; +2742 : douta <= 16'hC040 ; +2743 : douta <= 16'hC040 ; +2744 : douta <= 16'hBF40 ; +2745 : douta <= 16'hC040 ; +2746 : douta <= 16'hC040 ; +2747 : douta <= 16'hC040 ; +2748 : douta <= 16'hC040 ; +2749 : douta <= 16'hC040 ; +2750 : douta <= 16'hC040 ; +2751 : douta <= 16'hC040 ; +2752 : douta <= 16'hC040 ; +2753 : douta <= 16'hC040 ; +2754 : douta <= 16'hBE40 ; +2755 : douta <= 16'hBE40 ; +2756 : douta <= 16'hBE40 ; +2757 : douta <= 16'hBE40 ; +2758 : douta <= 16'hBE40 ; +2759 : douta <= 16'hBE40 ; +2760 : douta <= 16'hBE40 ; +2761 : douta <= 16'hBE40 ; +2762 : douta <= 16'hBE40 ; +2763 : douta <= 16'hBE40 ; +2764 : douta <= 16'hBE40 ; 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+2801 : douta <= 16'hBC40 ; +2802 : douta <= 16'hBB40 ; +2803 : douta <= 16'hBC40 ; +2804 : douta <= 16'hBC40 ; +2805 : douta <= 16'hBC40 ; +2806 : douta <= 16'hBC40 ; +2807 : douta <= 16'hBC40 ; +2808 : douta <= 16'hBC40 ; +2809 : douta <= 16'hBC40 ; +2810 : douta <= 16'hBC40 ; +2811 : douta <= 16'hBC40 ; +2812 : douta <= 16'hBC40 ; +2813 : douta <= 16'hBC40 ; +2814 : douta <= 16'hBC40 ; +2815 : douta <= 16'hBC40 ; +2816 : douta <= 16'hBC40 ; +2817 : douta <= 16'hBC40 ; +2818 : douta <= 16'hBC40 ; +2819 : douta <= 16'hBC40 ; +2820 : douta <= 16'hBB40 ; +2821 : douta <= 16'hBA40 ; +2822 : douta <= 16'hBA40 ; +2823 : douta <= 16'hBA40 ; +2824 : douta <= 16'hBA40 ; +2825 : douta <= 16'hBA40 ; +2826 : douta <= 16'hBA40 ; +2827 : douta <= 16'hBA40 ; +2828 : douta <= 16'hBA40 ; +2829 : douta <= 16'hBA40 ; +2830 : douta <= 16'hBA40 ; +2831 : douta <= 16'hBA40 ; +2832 : douta <= 16'hBA40 ; +2833 : douta <= 16'hBA40 ; +2834 : douta <= 16'hBA40 ; +2835 : douta <= 16'hB940 ; +2836 : douta <= 16'hB940 ; +2837 : douta <= 16'hBA40 ; +2838 : douta <= 16'hBA40 ; +2839 : douta <= 16'hBA40 ; +2840 : douta <= 16'hBA40 ; +2841 : douta <= 16'hB940 ; +2842 : douta <= 16'hB940 ; +2843 : douta <= 16'hB940 ; +2844 : douta <= 16'hB940 ; +2845 : douta <= 16'hB940 ; +2846 : douta <= 16'hB940 ; +2847 : douta <= 16'hB940 ; +2848 : douta <= 16'hB940 ; +2849 : douta <= 16'hB940 ; +2850 : douta <= 16'hB940 ; +2851 : douta <= 16'hB940 ; +2852 : douta <= 16'hB940 ; +2853 : douta <= 16'hB940 ; +2854 : douta <= 16'hB940 ; +2855 : douta <= 16'hB940 ; +2856 : douta <= 16'hB940 ; +2857 : douta <= 16'hB940 ; +2858 : douta <= 16'hB840 ; +2859 : douta <= 16'hB940 ; +2860 : douta <= 16'hB840 ; +2861 : douta <= 16'hB840 ; +2862 : douta <= 16'hB840 ; +2863 : douta <= 16'hB840 ; +2864 : douta <= 16'hB840 ; +2865 : douta <= 16'hB840 ; +2866 : douta <= 16'hB740 ; +2867 : douta <= 16'hB740 ; +2868 : douta <= 16'hB740 ; +2869 : douta <= 16'hB740 ; +2870 : douta <= 16'hB740 ; +2871 : douta <= 16'hB740 ; +2872 : douta <= 16'hB840 ; +2873 : douta <= 16'hB840 ; +2874 : douta <= 16'hB840 ; +2875 : douta <= 16'hB840 ; +2876 : douta <= 16'hB840 ; +2877 : douta <= 16'hB840 ; +2878 : douta <= 16'hB840 ; +2879 : douta <= 16'hB840 ; +2880 : douta <= 16'hB840 ; +2881 : douta <= 16'hB840 ; +2882 : douta <= 16'hB840 ; +2883 : douta <= 16'hB840 ; +2884 : douta <= 16'hB840 ; +2885 : douta <= 16'hB840 ; +2886 : douta <= 16'hB640 ; +2887 : douta <= 16'hB640 ; +2888 : douta <= 16'hB640 ; +2889 : douta <= 16'hB640 ; +2890 : douta <= 16'hB640 ; +2891 : douta <= 16'hB640 ; +2892 : douta <= 16'hB640 ; +2893 : douta <= 16'hB640 ; +2894 : douta <= 16'hB640 ; +2895 : douta <= 16'hB640 ; +2896 : douta <= 16'hB640 ; +2897 : douta <= 16'hB640 ; +2898 : douta <= 16'hB640 ; +2899 : douta <= 16'hB640 ; +2900 : douta <= 16'hB540 ; +2901 : douta <= 16'hB540 ; +2902 : douta <= 16'hB540 ; +2903 : douta <= 16'hB640 ; +2904 : douta <= 16'hB540 ; +2905 : douta <= 16'hB640 ; +2906 : douta <= 16'hB640 ; +2907 : douta <= 16'hB640 ; +2908 : douta <= 16'hB640 ; +2909 : douta <= 16'hB540 ; +2910 : douta <= 16'hB640 ; +2911 : douta <= 16'hB540 ; +2912 : douta <= 16'hB540 ; +2913 : douta <= 16'hB540 ; +2914 : douta <= 16'hB540 ; +2915 : douta <= 16'hB540 ; +2916 : douta <= 16'hB540 ; +2917 : douta <= 16'hB540 ; +2918 : douta <= 16'hB540 ; +2919 : douta <= 16'hB540 ; +2920 : douta <= 16'hB540 ; +2921 : douta <= 16'hB540 ; +2922 : douta <= 16'hB540 ; +2923 : douta <= 16'hB540 ; +2924 : douta <= 16'hB540 ; +2925 : douta <= 16'hB540 ; +2926 : douta <= 16'hB440 ; +2927 : douta <= 16'hB440 ; +2928 : douta <= 16'hB540 ; +2929 : douta <= 16'hB540 ; +2930 : douta <= 16'hB440 ; +2931 : douta <= 16'hB440 ; +2932 : douta <= 16'hB440 ; +2933 : douta <= 16'hB440 ; +2934 : douta <= 16'hB440 ; +2935 : douta <= 16'hB440 ; +2936 : douta <= 16'hB440 ; +2937 : douta <= 16'hB340 ; +2938 : douta <= 16'hB340 ; +2939 : douta <= 16'hB440 ; +2940 : douta <= 16'hB340 ; +2941 : douta <= 16'hB440 ; +2942 : douta <= 16'hB440 ; +2943 : douta <= 16'hB440 ; +2944 : douta <= 16'hB440 ; +2945 : douta <= 16'hB440 ; +2946 : douta <= 16'hB440 ; +2947 : douta <= 16'hB440 ; +2948 : douta <= 16'hB440 ; +2949 : douta <= 16'hB440 ; +2950 : douta <= 16'hB440 ; +2951 : douta <= 16'hB440 ; +2952 : douta <= 16'hB440 ; +2953 : douta <= 16'hB440 ; +2954 : douta <= 16'hB340 ; +2955 : douta <= 16'hB240 ; +2956 : douta <= 16'hB240 ; +2957 : douta <= 16'hB240 ; +2958 : douta <= 16'hB240 ; +2959 : douta <= 16'hB240 ; +2960 : douta <= 16'hB240 ; +2961 : douta <= 16'hB240 ; +2962 : douta <= 16'hB240 ; +2963 : douta <= 16'hB240 ; +2964 : douta <= 16'hB240 ; +2965 : douta <= 16'hB240 ; +2966 : douta <= 16'hB240 ; +2967 : douta <= 16'hB240 ; +2968 : douta <= 16'hB240 ; +2969 : douta <= 16'hB240 ; +2970 : douta <= 16'hB140 ; +2971 : douta <= 16'hB140 ; +2972 : douta <= 16'hB140 ; +2973 : douta <= 16'hB140 ; +2974 : douta <= 16'hB140 ; +2975 : douta <= 16'hB240 ; +2976 : douta <= 16'hB240 ; +2977 : douta <= 16'hB240 ; +2978 : douta <= 16'hB240 ; +2979 : douta <= 16'hB140 ; +2980 : douta <= 16'hB140 ; +2981 : douta <= 16'hB140 ; +2982 : douta <= 16'hB140 ; +2983 : douta <= 16'hB140 ; +2984 : douta <= 16'hB140 ; +2985 : douta <= 16'hB140 ; +2986 : douta <= 16'hB140 ; +2987 : douta <= 16'hB140 ; +2988 : douta <= 16'hB140 ; +2989 : douta <= 16'hB140 ; +2990 : douta <= 16'hB140 ; +2991 : douta <= 16'hB140 ; +2992 : douta <= 16'hB140 ; +2993 : douta <= 16'hB140 ; +2994 : douta <= 16'hB040 ; +2995 : douta <= 16'hB040 ; +2996 : douta <= 16'hB140 ; +2997 : douta <= 16'hB140 ; +2998 : douta <= 16'hB040 ; +2999 : douta <= 16'hB040 ; +3000 : douta <= 16'hB040 ; +3001 : douta <= 16'hB040 ; +3002 : douta <= 16'hB040 ; +3003 : douta <= 16'hB040 ; +3004 : douta <= 16'hB040 ; +3005 : douta <= 16'hB040 ; +3006 : douta <= 16'hB040 ; +3007 : douta <= 16'hB040 ; +3008 : douta <= 16'hB040 ; +3009 : douta <= 16'hB040 ; +3010 : douta <= 16'hB040 ; +3011 : douta <= 16'hB040 ; +3012 : douta <= 16'hB040 ; +3013 : douta <= 16'hB040 ; +3014 : douta <= 16'hB040 ; +3015 : douta <= 16'hB040 ; +3016 : douta <= 16'hB040 ; +3017 : douta <= 16'hB040 ; +3018 : douta <= 16'hB040 ; +3019 : douta <= 16'hB040 ; +3020 : douta <= 16'hB040 ; +3021 : douta <= 16'hB040 ; +3022 : douta <= 16'hB040 ; +3023 : douta <= 16'hB040 ; +3024 : douta <= 16'hB040 ; +3025 : douta <= 16'hAE40 ; +3026 : douta <= 16'hAE40 ; +3027 : douta <= 16'hAE40 ; +3028 : douta <= 16'hAE40 ; +3029 : douta <= 16'hAE40 ; +3030 : douta <= 16'hAE40 ; +3031 : douta <= 16'hAE40 ; +3032 : douta <= 16'hAE40 ; +3033 : douta <= 16'hAE40 ; +3034 : douta <= 16'hAE40 ; +3035 : douta <= 16'hAE40 ; +3036 : douta <= 16'hAD40 ; +3037 : douta <= 16'hAD40 ; +3038 : douta <= 16'hAD40 ; +3039 : douta <= 16'hAE40 ; +3040 : douta <= 16'hAE40 ; +3041 : douta <= 16'hAE40 ; +3042 : douta <= 16'hAE40 ; +3043 : douta <= 16'hAD40 ; +3044 : douta <= 16'hAE40 ; +3045 : douta <= 16'hAD40 ; +3046 : douta <= 16'hAD40 ; +3047 : douta <= 16'hAD40 ; +3048 : douta <= 16'hAD40 ; +3049 : douta <= 16'hAD40 ; +3050 : douta <= 16'hAD40 ; +3051 : douta <= 16'hAD40 ; +3052 : douta <= 16'hAD40 ; +3053 : douta <= 16'hAD40 ; +3054 : douta <= 16'hAD40 ; +3055 : douta <= 16'hAD40 ; +3056 : douta <= 16'hAD40 ; +3057 : douta <= 16'hAD40 ; +3058 : douta <= 16'hAD40 ; +3059 : douta <= 16'hAD40 ; +3060 : douta <= 16'hAC40 ; +3061 : douta <= 16'hAC40 ; +3062 : douta <= 16'hAC40 ; +3063 : douta <= 16'hAD40 ; +3064 : douta <= 16'hAC40 ; +3065 : douta <= 16'hAC40 ; +3066 : douta <= 16'hAC40 ; +3067 : douta <= 16'hAC40 ; +3068 : douta <= 16'hAC40 ; +3069 : douta <= 16'hAB40 ; +3070 : douta <= 16'hAB40 ; +3071 : douta <= 16'hAB40 ; +3072 : douta <= 16'hAB40 ; +3073 : douta <= 16'hAC40 ; +3074 : douta <= 16'hAB40 ; +3075 : douta <= 16'hAC40 ; +3076 : douta <= 16'hAC40 ; +3077 : douta <= 16'hAC40 ; +3078 : douta <= 16'hAC40 ; +3079 : douta <= 16'hAC40 ; +3080 : douta <= 16'hAC40 ; +3081 : douta <= 16'hAC40 ; +3082 : douta <= 16'hAC40 ; +3083 : douta <= 16'hAC40 ; +3084 : douta <= 16'hAC40 ; +3085 : douta <= 16'hAC40 ; +3086 : douta <= 16'hAC40 ; +3087 : douta <= 16'hAC40 ; +3088 : douta <= 16'hAC40 ; +3089 : douta <= 16'hAC40 ; +3090 : douta <= 16'hAA40 ; +3091 : douta <= 16'hAA40 ; +3092 : douta <= 16'hAA40 ; +3093 : douta <= 16'hAA40 ; +3094 : douta <= 16'hAA40 ; +3095 : douta <= 16'hAA40 ; +3096 : douta <= 16'hAA40 ; +3097 : douta <= 16'hAA40 ; +3098 : douta <= 16'hAA40 ; +3099 : douta <= 16'hAA40 ; +3100 : douta <= 16'hAA40 ; +3101 : douta <= 16'hAA40 ; +3102 : douta <= 16'hAA40 ; +3103 : douta <= 16'hAA40 ; +3104 : douta <= 16'hAA40 ; +3105 : douta <= 16'hAA40 ; +3106 : douta <= 16'hA940 ; +3107 : douta <= 16'hA940 ; +3108 : douta <= 16'hA940 ; +3109 : douta <= 16'hAA40 ; +3110 : douta <= 16'hAA40 ; +3111 : douta <= 16'hAA40 ; +3112 : douta <= 16'hA940 ; +3113 : douta <= 16'hA940 ; +3114 : douta <= 16'hA940 ; +3115 : douta <= 16'hA940 ; +3116 : douta <= 16'hA940 ; +3117 : douta <= 16'hA940 ; +3118 : douta <= 16'hA940 ; +3119 : douta <= 16'hA940 ; +3120 : douta <= 16'hA940 ; +3121 : douta <= 16'hA940 ; +3122 : douta <= 16'hA940 ; +3123 : douta <= 16'hA940 ; +3124 : douta <= 16'hA940 ; +3125 : douta <= 16'hA940 ; +3126 : douta <= 16'hA940 ; +3127 : douta <= 16'hA940 ; +3128 : douta <= 16'hA840 ; +3129 : douta <= 16'hA940 ; +3130 : douta <= 16'hA840 ; +3131 : douta <= 16'hA940 ; +3132 : douta <= 16'hA840 ; +3133 : douta <= 16'hA840 ; +3134 : douta <= 16'hA840 ; +3135 : douta <= 16'hA840 ; +3136 : douta <= 16'hA840 ; +3137 : douta <= 16'hA840 ; +3138 : douta <= 16'hA840 ; +3139 : douta <= 16'hA840 ; +3140 : douta <= 16'hA840 ; +3141 : douta <= 16'hA840 ; +3142 : douta <= 16'hA840 ; +3143 : douta <= 16'hA840 ; +3144 : douta <= 16'hA840 ; +3145 : douta <= 16'hA840 ; +3146 : douta <= 16'hA840 ; +3147 : douta <= 16'hA840 ; +3148 : douta <= 16'hA840 ; +3149 : douta <= 16'hA840 ; +3150 : douta <= 16'hA840 ; +3151 : douta <= 16'hA840 ; +3152 : douta <= 16'hA840 ; +3153 : douta <= 16'hA840 ; +3154 : douta <= 16'hA840 ; +3155 : douta <= 16'hA840 ; +3156 : douta <= 16'hA840 ; +3157 : douta <= 16'hA640 ; +3158 : douta <= 16'hA840 ; +3159 : douta <= 16'hA840 ; +3160 : douta <= 16'hA640 ; +3161 : douta <= 16'hA640 ; +3162 : douta <= 16'hA640 ; +3163 : douta <= 16'hA640 ; +3164 : douta <= 16'hA640 ; +3165 : douta <= 16'hA640 ; +3166 : douta <= 16'hA640 ; +3167 : douta <= 16'hA640 ; +3168 : douta <= 16'hA640 ; +3169 : douta <= 16'hA640 ; +3170 : douta <= 16'hA640 ; +3171 : douta <= 16'hA640 ; +3172 : douta <= 16'hA640 ; +3173 : douta <= 16'hA640 ; +3174 : douta <= 16'hA640 ; +3175 : douta <= 16'hA640 ; +3176 : douta <= 16'hA540 ; +3177 : douta <= 16'hA640 ; +3178 : douta <= 16'hA640 ; +3179 : douta <= 16'hA640 ; +3180 : douta <= 16'hA640 ; +3181 : douta <= 16'hA640 ; +3182 : douta <= 16'hA640 ; +3183 : douta <= 16'hA540 ; +3184 : douta <= 16'hA540 ; +3185 : douta <= 16'hA540 ; +3186 : douta <= 16'hA540 ; +3187 : douta <= 16'hA540 ; +3188 : douta <= 16'hA540 ; +3189 : douta <= 16'hA540 ; +3190 : douta <= 16'hA540 ; +3191 : douta <= 16'hA540 ; +3192 : douta <= 16'hA540 ; +3193 : douta <= 16'hA540 ; +3194 : douta <= 16'hA540 ; +3195 : douta <= 16'hA540 ; +3196 : douta <= 16'hA540 ; +3197 : douta <= 16'hA540 ; +3198 : douta <= 16'hA440 ; +3199 : douta <= 16'hA440 ; +3200 : douta <= 16'hA440 ; +3201 : douta <= 16'hA440 ; +3202 : douta <= 16'hA440 ; +3203 : douta <= 16'hA540 ; +3204 : douta <= 16'hA540 ; +3205 : douta <= 16'hA540 ; +3206 : douta <= 16'hA440 ; +3207 : douta <= 16'hA440 ; +3208 : douta <= 16'hA440 ; +3209 : douta <= 16'hA340 ; +3210 : douta <= 16'hA340 ; +3211 : douta <= 16'hA340 ; +3212 : douta <= 16'hA440 ; +3213 : douta <= 16'hA440 ; +3214 : douta <= 16'hA440 ; +3215 : douta <= 16'hA440 ; +3216 : douta <= 16'hA440 ; +3217 : douta <= 16'hA440 ; +3218 : douta <= 16'hA440 ; +3219 : douta <= 16'hA440 ; +3220 : douta <= 16'hA440 ; +3221 : douta <= 16'hA440 ; +3222 : douta <= 16'hA440 ; +3223 : douta <= 16'hA440 ; +3224 : douta <= 16'hA440 ; +3225 : douta <= 16'hA440 ; +3226 : douta <= 16'hA440 ; +3227 : douta <= 16'hA240 ; +3228 : douta <= 16'hA240 ; +3229 : douta <= 16'hA240 ; +3230 : douta <= 16'hA240 ; +3231 : douta <= 16'hA240 ; +3232 : douta <= 16'hA240 ; +3233 : douta <= 16'hA240 ; +3234 : douta <= 16'hA240 ; +3235 : douta <= 16'hA240 ; +3236 : douta <= 16'hA240 ; +3237 : douta <= 16'hA240 ; +3238 : douta <= 16'hA240 ; +3239 : douta <= 16'hA240 ; +3240 : douta <= 16'hA240 ; +3241 : douta <= 16'hA240 ; +3242 : douta <= 16'hA140 ; +3243 : douta <= 16'hA140 ; +3244 : douta <= 16'hA140 ; +3245 : douta <= 16'hA240 ; +3246 : douta <= 16'hA240 ; +3247 : douta <= 16'hA240 ; +3248 : douta <= 16'hA240 ; +3249 : douta <= 16'hA140 ; +3250 : douta <= 16'hA140 ; +3251 : douta <= 16'hA140 ; +3252 : douta <= 16'hA140 ; +3253 : douta <= 16'hA140 ; +3254 : douta <= 16'hA140 ; +3255 : douta <= 16'hA140 ; +3256 : douta <= 16'hA140 ; +3257 : douta <= 16'hA140 ; +3258 : douta <= 16'hA140 ; +3259 : douta <= 16'hA140 ; +3260 : douta <= 16'hA140 ; +3261 : douta <= 16'hA140 ; +3262 : douta <= 16'hA140 ; +3263 : douta <= 16'hA140 ; +3264 : douta <= 16'hA140 ; +3265 : douta <= 16'hA140 ; +3266 : douta <= 16'hA040 ; +3267 : douta <= 16'hA040 ; +3268 : douta <= 16'hA040 ; +3269 : douta <= 16'hA140 ; +3270 : douta <= 16'hA040 ; +3271 : douta <= 16'hA040 ; +3272 : douta <= 16'hA040 ; +3273 : douta <= 16'hA040 ; +3274 : douta <= 16'hA040 ; +3275 : douta <= 16'hA040 ; +3276 : douta <= 16'hA040 ; +3277 : douta <= 16'hA040 ; +3278 : douta <= 16'hA040 ; +3279 : douta <= 16'hA040 ; +3280 : douta <= 16'hA040 ; +3281 : douta <= 16'hA040 ; +3282 : douta <= 16'hA040 ; +3283 : douta <= 16'hA040 ; +3284 : douta <= 16'hA040 ; +3285 : douta <= 16'hA040 ; +3286 : douta <= 16'hA040 ; +3287 : douta <= 16'hA040 ; +3288 : douta <= 16'hA040 ; +3289 : douta <= 16'hA040 ; +3290 : douta <= 16'hA040 ; +3291 : douta <= 16'hA040 ; +3292 : douta <= 16'h9E42 ; +3293 : douta <= 16'hA040 ; +3294 : douta <= 16'hA040 ; +3295 : douta <= 16'hA040 ; +3296 : douta <= 16'hA040 ; +3297 : douta <= 16'hA040 ; +3298 : douta <= 16'hA040 ; +3299 : douta <= 16'hA040 ; +3300 : douta <= 16'hA040 ; +3301 : douta <= 16'hA040 ; +3302 : douta <= 16'h9F42 ; +3303 : douta <= 16'hA040 ; +3304 : douta <= 16'hA040 ; +3305 : douta <= 16'hA040 ; +3306 : douta <= 16'hA040 ; +3307 : douta <= 16'hA040 ; +3308 : douta <= 16'hA040 ; +3309 : douta <= 16'hA040 ; +3310 : douta <= 16'hA040 ; +3311 : douta <= 16'hA040 ; +3312 : douta <= 16'hA040 ; +3313 : douta <= 16'hA040 ; +3314 : douta <= 16'hA040 ; +3315 : douta <= 16'hA040 ; +3316 : douta <= 16'hA040 ; +3317 : douta <= 16'hA040 ; +3318 : douta <= 16'h9F42 ; +3319 : douta <= 16'hA040 ; +3320 : douta <= 16'hA040 ; +3321 : douta <= 16'hA040 ; +3322 : douta <= 16'hA040 ; +3323 : douta <= 16'hA040 ; +3324 : douta <= 16'h9E42 ; +3325 : douta <= 16'h9E42 ; +3326 : douta <= 16'h9E42 ; +3327 : douta <= 16'h9E42 ; +3328 : douta <= 16'h9E42 ; +3329 : douta <= 16'h9E42 ; +3330 : douta <= 16'h9E42 ; +3331 : douta <= 16'h9E42 ; +3332 : douta <= 16'h9E42 ; +3333 : douta <= 16'h9E42 ; +3334 : douta <= 16'h9E42 ; +3335 : douta <= 16'h9E42 ; +3336 : douta <= 16'h9E42 ; +3337 : douta <= 16'h9E42 ; +3338 : douta <= 16'h9E42 ; +3339 : douta <= 16'h9E42 ; +3340 : douta <= 16'h9E42 ; +3341 : douta <= 16'h9D42 ; +3342 : douta <= 16'h9E42 ; +3343 : douta <= 16'h9E42 ; +3344 : douta <= 16'h9E42 ; +3345 : douta <= 16'h9E42 ; +3346 : douta <= 16'h9E42 ; +3347 : douta <= 16'h9D42 ; +3348 : douta <= 16'h9D42 ; +3349 : douta <= 16'h9D42 ; +3350 : douta <= 16'h9D42 ; +3351 : douta <= 16'h9D42 ; +3352 : douta <= 16'h9D42 ; +3353 : douta <= 16'h9D42 ; +3354 : douta <= 16'h9D42 ; +3355 : douta <= 16'h9D42 ; +3356 : douta <= 16'h9D42 ; +3357 : douta <= 16'h9D42 ; +3358 : douta <= 16'h9D42 ; +3359 : douta <= 16'h9D42 ; +3360 : douta <= 16'h9D42 ; +3361 : douta <= 16'h9D42 ; +3362 : douta <= 16'h9D42 ; +3363 : douta <= 16'h9C42 ; +3364 : douta <= 16'h9C42 ; +3365 : douta <= 16'h9D42 ; +3366 : douta <= 16'h9C42 ; +3367 : douta <= 16'h9C42 ; +3368 : douta <= 16'h9C42 ; +3369 : douta <= 16'h9C42 ; +3370 : douta <= 16'h9C42 ; +3371 : douta <= 16'h9C42 ; +3372 : douta <= 16'h9C42 ; +3373 : douta <= 16'h9C42 ; +3374 : douta <= 16'h9C42 ; +3375 : douta <= 16'h9C42 ; +3376 : douta <= 16'h9C42 ; +3377 : douta <= 16'h9C42 ; +3378 : douta <= 16'h9C42 ; +3379 : douta <= 16'h9C42 ; +3380 : douta <= 16'h9B42 ; +3381 : douta <= 16'h9B42 ; +3382 : douta <= 16'h9C42 ; +3383 : douta <= 16'h9C42 ; +3384 : douta <= 16'h9C42 ; +3385 : douta <= 16'h9C42 ; +3386 : douta <= 16'h9C42 ; +3387 : douta <= 16'h9C42 ; +3388 : douta <= 16'h9C42 ; +3389 : douta <= 16'h9C42 ; +3390 : douta <= 16'h9C42 ; +3391 : douta <= 16'h9C42 ; +3392 : douta <= 16'h9C42 ; +3393 : douta <= 16'h9B42 ; +3394 : douta <= 16'h9B42 ; +3395 : douta <= 16'h9B42 ; +3396 : douta <= 16'h9B42 ; +3397 : douta <= 16'h9B42 ; +3398 : douta <= 16'h9A42 ; +3399 : douta <= 16'h9A42 ; +3400 : douta <= 16'h9A42 ; +3401 : douta <= 16'h9A42 ; +3402 : douta <= 16'h9A42 ; +3403 : douta <= 16'h9A42 ; +3404 : douta <= 16'h9A42 ; +3405 : douta <= 16'h9A42 ; +3406 : douta <= 16'h9A42 ; +3407 : douta <= 16'h9A42 ; +3408 : douta <= 16'h9A42 ; +3409 : douta <= 16'h9942 ; +3410 : douta <= 16'h9A42 ; +3411 : douta <= 16'h9A42 ; +3412 : douta <= 16'h9A42 ; +3413 : douta <= 16'h9A42 ; +3414 : douta <= 16'h9A42 ; +3415 : douta <= 16'h9A42 ; +3416 : douta <= 16'h9A42 ; +3417 : douta <= 16'h9A42 ; +3418 : douta <= 16'h9A42 ; +3419 : douta <= 16'h9A42 ; +3420 : douta <= 16'h9942 ; +3421 : douta <= 16'h9942 ; +3422 : douta <= 16'h9942 ; +3423 : douta <= 16'h9942 ; +3424 : douta <= 16'h9942 ; +3425 : douta <= 16'h9942 ; +3426 : douta <= 16'h9942 ; +3427 : douta <= 16'h9942 ; +3428 : douta <= 16'h9942 ; +3429 : douta <= 16'h9942 ; +3430 : douta <= 16'h9942 ; +3431 : douta <= 16'h9942 ; +3432 : douta <= 16'h9942 ; +3433 : douta <= 16'h9942 ; +3434 : douta <= 16'h9942 ; +3435 : douta <= 16'h9942 ; +3436 : douta <= 16'h9942 ; +3437 : douta <= 16'h9942 ; +3438 : douta <= 16'h9942 ; +3439 : douta <= 16'h9842 ; +3440 : douta <= 16'h9842 ; +3441 : douta <= 16'h9942 ; +3442 : douta <= 16'h9842 ; +3443 : douta <= 16'h9842 ; +3444 : douta <= 16'h9842 ; +3445 : douta <= 16'h9842 ; +3446 : douta <= 16'h9842 ; +3447 : douta <= 16'h9842 ; +3448 : douta <= 16'h9842 ; +3449 : douta <= 16'h9842 ; +3450 : douta <= 16'h9842 ; +3451 : douta <= 16'h9842 ; +3452 : douta <= 16'h9842 ; +3453 : douta <= 16'h9842 ; +3454 : douta <= 16'h9842 ; +3455 : douta <= 16'h9842 ; +3456 : douta <= 16'h9842 ; +3457 : douta <= 16'h9842 ; +3458 : douta <= 16'h9842 ; +3459 : douta <= 16'h9742 ; +3460 : douta <= 16'h9742 ; +3461 : douta <= 16'h9842 ; +3462 : douta <= 16'h9842 ; +3463 : douta <= 16'h9842 ; +3464 : douta <= 16'h9842 ; +3465 : douta <= 16'h9842 ; +3466 : douta <= 16'h9842 ; +3467 : douta <= 16'h9842 ; +3468 : douta <= 16'h9642 ; +3469 : douta <= 16'h9642 ; +3470 : douta <= 16'h9642 ; +3471 : douta <= 16'h9642 ; +3472 : douta <= 16'h9642 ; +3473 : douta <= 16'h9642 ; +3474 : douta <= 16'h9642 ; +3475 : douta <= 16'h9642 ; +3476 : douta <= 16'h9642 ; +3477 : douta <= 16'h9642 ; +3478 : douta <= 16'h9642 ; +3479 : douta <= 16'h9642 ; +3480 : douta <= 16'h9642 ; +3481 : douta <= 16'h9642 ; +3482 : douta <= 16'h9642 ; +3483 : douta <= 16'h9642 ; +3484 : douta <= 16'h9542 ; +3485 : douta <= 16'h9542 ; +3486 : douta <= 16'h9542 ; +3487 : douta <= 16'h9642 ; +3488 : douta <= 16'h9642 ; +3489 : douta <= 16'h9642 ; +3490 : douta <= 16'h9642 ; +3491 : douta <= 16'h9642 ; +3492 : douta <= 16'h9642 ; +3493 : douta <= 16'h9542 ; +3494 : douta <= 16'h9542 ; +3495 : douta <= 16'h9542 ; +3496 : douta <= 16'h9542 ; +3497 : douta <= 16'h9542 ; +3498 : douta <= 16'h9542 ; +3499 : douta <= 16'h9542 ; +3500 : douta <= 16'h9542 ; + + + +default:douta<=16'h9542; +endcase + +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/band_rom_b.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/band_rom_b.v new file mode 100644 index 0000000..80392bd --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/band_rom_b.v @@ -0,0 +1,3573 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 18:19:17 01/25/2022 +// Design Name: +// Module Name: band_rom +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module band_rom_b( +input sysclk, +input [11 : 0] addra, + +output reg[15:0] douta +); + +always@(posedge sysclk)begin + case(addra) + +0 : douta <= 16'h7426 ; +1 : douta <= 16'h7426 ; +2 : douta <= 16'h7426 ; +3 : douta <= 16'h7426 ; +4 : douta <= 16'h7426 ; +5 : douta <= 16'h7326 ; +6 : douta <= 16'h7326 ; +7 : douta <= 16'h7426 ; +8 : douta <= 16'h7426 ; +9 : douta <= 16'h7326 ; +10 : douta <= 16'h7326 ; +11 : douta <= 16'h7326 ; +12 : douta <= 16'h7326 ; +13 : douta <= 16'h7326 ; +14 : douta <= 16'h7326 ; +15 : douta <= 16'h7326 ; +16 : douta <= 16'h7326 ; +17 : douta <= 16'h7226 ; +18 : douta <= 16'h7326 ; +19 : douta <= 16'h7226 ; +20 : douta <= 16'h7226 ; +21 : douta <= 16'h7226 ; +22 : douta <= 16'h7226 ; +23 : douta <= 16'h7126 ; +24 : douta <= 16'h7126 ; +25 : douta <= 16'h7126 ; +26 : douta <= 16'h7226 ; +27 : douta <= 16'h7226 ; +28 : douta <= 16'h7226 ; +29 : douta <= 16'h7226 ; +30 : douta <= 16'h7226 ; +31 : douta <= 16'h7226 ; +32 : douta <= 16'h7226 ; +33 : douta <= 16'h7226 ; +34 : douta <= 16'h7226 ; +35 : douta <= 16'h7226 ; +36 : douta <= 16'h7126 ; +37 : douta <= 16'h7126 ; +38 : douta <= 16'h7126 ; +39 : douta <= 16'h7126 ; +40 : douta <= 16'h7126 ; +41 : douta <= 16'h7126 ; +42 : douta <= 16'h7126 ; +43 : douta <= 16'h7126 ; +44 : douta <= 16'h7126 ; +45 : douta <= 16'h7126 ; +46 : douta <= 16'h7126 ; +47 : douta <= 16'h7126 ; +48 : douta <= 16'h7126 ; +49 : douta <= 16'h7026 ; +50 : douta <= 16'h7026 ; +51 : douta <= 16'h7126 ; +52 : douta <= 16'h7026 ; +53 : douta <= 16'h7126 ; +54 : douta <= 16'h6F26 ; +55 : douta <= 16'h7126 ; +56 : douta <= 16'h7126 ; +57 : douta <= 16'h7126 ; +58 : douta <= 16'h7126 ; +59 : douta <= 16'h7026 ; +60 : douta <= 16'h7126 ; +61 : douta <= 16'h6E26 ; +62 : douta <= 16'h7026 ; +63 : douta <= 16'h6E26 ; +64 : douta <= 16'h7026 ; +65 : douta <= 16'h7026 ; +66 : douta <= 16'h7026 ; +67 : douta <= 16'h7026 ; +68 : douta <= 16'h7026 ; +69 : douta <= 16'h7026 ; +70 : douta <= 16'h7026 ; +71 : douta <= 16'h7026 ; +72 : douta <= 16'h7026 ; +73 : douta <= 16'h7026 ; +74 : douta <= 16'h7026 ; +75 : douta <= 16'h7026 ; +76 : douta <= 16'h7026 ; +77 : douta <= 16'h7026 ; +78 : douta <= 16'h7026 ; +79 : douta <= 16'h7026 ; +80 : douta <= 16'h7026 ; +81 : douta <= 16'h6F26 ; +82 : douta <= 16'h6F26 ; +83 : douta <= 16'h6F26 ; +84 : douta <= 16'h6F26 ; +85 : douta <= 16'h6F26 ; +86 : douta <= 16'h6E26 ; +87 : douta <= 16'h6E26 ; +88 : douta <= 16'h6E26 ; +89 : douta <= 16'h6E26 ; +90 : douta <= 16'h6E26 ; +91 : douta <= 16'h6E26 ; +92 : douta <= 16'h6E26 ; +93 : douta <= 16'h6E26 ; +94 : douta <= 16'h6E26 ; +95 : douta <= 16'h6E26 ; +96 : douta <= 16'h6E26 ; +97 : douta <= 16'h6E26 ; +98 : douta <= 16'h6E26 ; +99 : douta <= 16'h6E26 ; +100 : douta <= 16'h6E26 ; +101 : douta <= 16'h6E26 ; +102 : douta <= 16'h6E26 ; +103 : douta <= 16'h6E26 ; +104 : douta <= 16'h6E26 ; +105 : douta <= 16'h6E26 ; +106 : douta <= 16'h6E26 ; +107 : douta <= 16'h6D26 ; +108 : douta <= 16'h6E26 ; +109 : douta <= 16'h6D26 ; +110 : douta <= 16'h6D26 ; +111 : douta <= 16'h6D26 ; +112 : douta <= 16'h6D26 ; +113 : douta <= 16'h6D26 ; +114 : douta <= 16'h6D26 ; +115 : douta <= 16'h6D26 ; +116 : douta <= 16'h6D26 ; +117 : douta <= 16'h6D26 ; +118 : douta <= 16'h6D26 ; +119 : douta <= 16'h6D26 ; +120 : douta <= 16'h6D26 ; +121 : douta <= 16'h6C26 ; +122 : douta <= 16'h6D26 ; +123 : douta <= 16'h6D26 ; +124 : douta <= 16'h6C26 ; +125 : douta <= 16'h6D26 ; +126 : douta <= 16'h6D26 ; +127 : douta <= 16'h6D26 ; +128 : douta <= 16'h6D26 ; +129 : douta <= 16'h6D26 ; +130 : douta <= 16'h6D26 ; +131 : douta <= 16'h6D26 ; +132 : douta <= 16'h6D26 ; +133 : douta <= 16'h6C26 ; +134 : douta <= 16'h6C26 ; +135 : douta <= 16'h6C26 ; +136 : douta <= 16'h6C26 ; +137 : douta <= 16'h6C26 ; +138 : douta <= 16'h6C26 ; +139 : douta <= 16'h6C26 ; +140 : douta <= 16'h6C26 ; +141 : douta <= 16'h6C26 ; +142 : douta <= 16'h6C26 ; +143 : douta <= 16'h6C26 ; +144 : douta <= 16'h6C26 ; +145 : douta <= 16'h6C26 ; +146 : douta <= 16'h6C26 ; +147 : douta <= 16'h6C26 ; +148 : douta <= 16'h6C26 ; +149 : douta <= 16'h6C26 ; +150 : douta <= 16'h6C26 ; +151 : douta <= 16'h6C26 ; +152 : douta <= 16'h6C26 ; +153 : douta <= 16'h6B26 ; +154 : douta <= 16'h6B26 ; +155 : douta <= 16'h6B26 ; +156 : douta <= 16'h6B26 ; +157 : douta <= 16'h6B26 ; +158 : douta <= 16'h6B26 ; +159 : douta <= 16'h6B26 ; +160 : douta <= 16'h6B26 ; +161 : douta <= 16'h6B26 ; +162 : douta <= 16'h6A26 ; +163 : douta <= 16'h6A26 ; +164 : douta <= 16'h6A26 ; +165 : douta <= 16'h6A26 ; +166 : douta <= 16'h6A26 ; +167 : douta <= 16'h6A26 ; +168 : douta <= 16'h6926 ; +169 : douta <= 16'h6A26 ; +170 : douta <= 16'h6926 ; +171 : douta <= 16'h6A26 ; +172 : douta <= 16'h6926 ; +173 : douta <= 16'h6A26 ; +174 : douta <= 16'h6A26 ; +175 : douta <= 16'h6A26 ; +176 : douta <= 16'h6A26 ; +177 : douta <= 16'h6A26 ; +178 : douta <= 16'h6A26 ; +179 : douta <= 16'h6A26 ; +180 : douta <= 16'h6A26 ; +181 : douta <= 16'h6A26 ; +182 : douta <= 16'h6A26 ; +183 : douta <= 16'h6A26 ; +184 : douta <= 16'h6926 ; +185 : douta <= 16'h6926 ; +186 : douta <= 16'h6926 ; +187 : douta <= 16'h6926 ; +188 : douta <= 16'h6926 ; +189 : douta <= 16'h6926 ; +190 : douta <= 16'h6926 ; +191 : douta <= 16'h6926 ; +192 : douta <= 16'h6926 ; +193 : douta <= 16'h6926 ; +194 : douta <= 16'h6926 ; +195 : douta <= 16'h6826 ; +196 : douta <= 16'h6826 ; +197 : douta <= 16'h6826 ; +198 : douta <= 16'h6826 ; +199 : douta <= 16'h6826 ; +200 : douta <= 16'h6926 ; +201 : douta <= 16'h6926 ; +202 : douta <= 16'h6926 ; +203 : douta <= 16'h6926 ; +204 : douta <= 16'h6926 ; +205 : douta <= 16'h6926 ; +206 : douta <= 16'h6926 ; +207 : douta <= 16'h6926 ; +208 : douta <= 16'h6826 ; +209 : douta <= 16'h6826 ; +210 : douta <= 16'h6826 ; +211 : douta <= 16'h6826 ; +212 : douta <= 16'h6826 ; +213 : douta <= 16'h6826 ; +214 : douta <= 16'h6826 ; +215 : douta <= 16'h6826 ; +216 : douta <= 16'h6826 ; +217 : douta <= 16'h6826 ; +218 : douta <= 16'h6826 ; +219 : douta <= 16'h6726 ; +220 : douta <= 16'h6726 ; +221 : douta <= 16'h6826 ; +222 : douta <= 16'h6826 ; +223 : douta <= 16'h6826 ; +224 : douta <= 16'h6826 ; +225 : douta <= 16'h6826 ; +226 : douta <= 16'h6826 ; +227 : douta <= 16'h6826 ; +228 : douta <= 16'h6826 ; +229 : douta <= 16'h6826 ; +230 : douta <= 16'h6826 ; +231 : douta <= 16'h6826 ; +232 : douta <= 16'h6726 ; +233 : douta <= 16'h6726 ; +234 : douta <= 16'h6526 ; +235 : douta <= 16'h6526 ; +236 : douta <= 16'h6726 ; +237 : douta <= 16'h6726 ; +238 : douta <= 16'h6726 ; +239 : douta <= 16'h6726 ; +240 : douta <= 16'h6726 ; +241 : douta <= 16'h6626 ; +242 : douta <= 16'h6626 ; +243 : douta <= 16'h6626 ; +244 : douta <= 16'h6626 ; +245 : douta <= 16'h6626 ; +246 : douta <= 16'h6626 ; +247 : douta <= 16'h6626 ; +248 : douta <= 16'h6626 ; +249 : douta <= 16'h6626 ; +250 : douta <= 16'h6626 ; +251 : douta <= 16'h6626 ; +252 : douta <= 16'h6626 ; +253 : douta <= 16'h6626 ; +254 : douta <= 16'h6626 ; +255 : douta <= 16'h6626 ; +256 : douta <= 16'h6626 ; +257 : douta <= 16'h6626 ; +258 : douta <= 16'h6626 ; +259 : douta <= 16'h6626 ; +260 : douta <= 16'h6626 ; +261 : douta <= 16'h6626 ; +262 : douta <= 16'h6526 ; +263 : douta <= 16'h6626 ; +264 : douta <= 16'h6526 ; +265 : douta <= 16'h6526 ; +266 : douta <= 16'h6526 ; +267 : douta <= 16'h6526 ; +268 : douta <= 16'h6526 ; +269 : douta <= 16'h6526 ; +270 : douta <= 16'h6526 ; +271 : douta <= 16'h6526 ; +272 : douta <= 16'h6526 ; +273 : douta <= 16'h6526 ; +274 : douta <= 16'h6526 ; +275 : douta <= 16'h6526 ; +276 : douta <= 16'h6526 ; +277 : douta <= 16'h6426 ; +278 : douta <= 16'h6526 ; +279 : douta <= 16'h6526 ; +280 : douta <= 16'h6526 ; +281 : douta <= 16'h6526 ; +282 : douta <= 16'h6526 ; +283 : douta <= 16'h6526 ; +284 : douta <= 16'h6526 ; +285 : douta <= 16'h6526 ; +286 : douta <= 16'h6526 ; +287 : douta <= 16'h6526 ; +288 : douta <= 16'h6426 ; +289 : douta <= 16'h6426 ; +290 : douta <= 16'h6426 ; +291 : douta <= 16'h6426 ; +292 : douta <= 16'h6426 ; +293 : douta <= 16'h6426 ; +294 : douta <= 16'h6426 ; +295 : douta <= 16'h6426 ; +296 : douta <= 16'h6426 ; +297 : douta <= 16'h6426 ; +298 : douta <= 16'h6426 ; +299 : douta <= 16'h6426 ; +300 : douta <= 16'h6426 ; +301 : douta <= 16'h6426 ; +302 : douta <= 16'h6426 ; +303 : douta <= 16'h6426 ; +304 : douta <= 16'h6426 ; +305 : douta <= 16'h6326 ; +306 : douta <= 16'h6426 ; +307 : douta <= 16'h6326 ; +308 : douta <= 16'h6326 ; +309 : douta <= 16'h6326 ; +310 : douta <= 16'h6326 ; +311 : douta <= 16'h6426 ; +312 : douta <= 16'h6426 ; +313 : douta <= 16'h6326 ; +314 : douta <= 16'h6326 ; +315 : douta <= 16'h6326 ; +316 : douta <= 16'h6326 ; +317 : douta <= 16'h6326 ; +318 : douta <= 16'h6326 ; +319 : douta <= 16'h6226 ; +320 : douta <= 16'h6226 ; +321 : douta <= 16'h6226 ; +322 : douta <= 16'h6226 ; +323 : douta <= 16'h6226 ; +324 : douta <= 16'h6126 ; +325 : douta <= 16'h6226 ; +326 : douta <= 16'h6126 ; +327 : douta <= 16'h6126 ; +328 : douta <= 16'h6126 ; +329 : douta <= 16'h6226 ; +330 : douta <= 16'h6226 ; +331 : douta <= 16'h6226 ; +332 : douta <= 16'h6226 ; +333 : douta <= 16'h6226 ; +334 : douta <= 16'h6226 ; +335 : douta <= 16'h6226 ; +336 : douta <= 16'h6226 ; +337 : douta <= 16'h6226 ; +338 : douta <= 16'h6226 ; +339 : douta <= 16'h6226 ; +340 : douta <= 16'h6226 ; +341 : douta <= 16'h6126 ; +342 : douta <= 16'h6126 ; +343 : douta <= 16'h6126 ; +344 : douta <= 16'h6126 ; +345 : douta <= 16'h6126 ; +346 : douta <= 16'h6126 ; +347 : douta <= 16'h6126 ; +348 : douta <= 16'h6126 ; +349 : douta <= 16'h6126 ; +350 : douta <= 16'h6126 ; +351 : douta <= 16'h6126 ; +352 : douta <= 16'h6126 ; +353 : douta <= 16'h6126 ; +354 : douta <= 16'h6126 ; +355 : douta <= 16'h6026 ; +356 : douta <= 16'h6026 ; +357 : douta <= 16'h6126 ; +358 : douta <= 16'h6126 ; +359 : douta <= 16'h6126 ; +360 : douta <= 16'h6126 ; +361 : douta <= 16'h6126 ; +362 : douta <= 16'h6126 ; +363 : douta <= 16'h6126 ; +364 : douta <= 16'h6126 ; +365 : douta <= 16'h6126 ; +366 : douta <= 16'h6126 ; +367 : douta <= 16'h6126 ; +368 : douta <= 16'h6026 ; +369 : douta <= 16'h6026 ; +370 : douta <= 16'h6026 ; +371 : douta <= 16'h6026 ; +372 : douta <= 16'h6026 ; +373 : douta <= 16'h6026 ; +374 : douta <= 16'h6026 ; +375 : douta <= 16'h5F28 ; +376 : douta <= 16'h6026 ; +377 : douta <= 16'h6026 ; +378 : douta <= 16'h6026 ; +379 : douta <= 16'h5F28 ; +380 : douta <= 16'h6026 ; +381 : douta <= 16'h6026 ; +382 : douta <= 16'h6026 ; +383 : douta <= 16'h6026 ; +384 : douta <= 16'h6026 ; +385 : douta <= 16'h6026 ; +386 : douta <= 16'h5F28 ; +387 : douta <= 16'h6026 ; +388 : douta <= 16'h6026 ; +389 : douta <= 16'h6026 ; +390 : douta <= 16'h5E28 ; +391 : douta <= 16'h6026 ; +392 : douta <= 16'h6026 ; +393 : douta <= 16'h6026 ; +394 : douta <= 16'h6026 ; +395 : douta <= 16'h6026 ; +396 : douta <= 16'h6026 ; +397 : douta <= 16'h6026 ; +398 : douta <= 16'h6026 ; +399 : douta <= 16'h6026 ; +400 : douta <= 16'h5E28 ; +401 : douta <= 16'h5E28 ; +402 : douta <= 16'h5E28 ; +403 : douta <= 16'h5E28 ; +404 : douta <= 16'h5E28 ; +405 : douta <= 16'h5E28 ; +406 : douta <= 16'h5E28 ; +407 : douta <= 16'h5E28 ; +408 : douta <= 16'h5E28 ; +409 : douta <= 16'h5E28 ; +410 : douta <= 16'h5E28 ; +411 : douta <= 16'h5D28 ; +412 : douta <= 16'h5D28 ; +413 : douta <= 16'h5D28 ; +414 : douta <= 16'h5D28 ; +415 : douta <= 16'h5D28 ; +416 : douta <= 16'h5D28 ; +417 : douta <= 16'h5D28 ; +418 : douta <= 16'h5D28 ; +419 : douta <= 16'h5D28 ; +420 : douta <= 16'h5D28 ; +421 : douta <= 16'h5D28 ; +422 : douta <= 16'h5D28 ; +423 : douta <= 16'h5D28 ; +424 : douta <= 16'h5D28 ; +425 : douta <= 16'h5C28 ; +426 : douta <= 16'h5C28 ; +427 : douta <= 16'h5D28 ; +428 : douta <= 16'h5D28 ; +429 : douta <= 16'h5B28 ; +430 : douta <= 16'h5B28 ; +431 : douta <= 16'h5D28 ; +432 : douta <= 16'h5D28 ; +433 : douta <= 16'h5C28 ; +434 : douta <= 16'h5C28 ; +435 : douta <= 16'h5C28 ; +436 : douta <= 16'h5C28 ; +437 : douta <= 16'h5C28 ; +438 : douta <= 16'h5C28 ; +439 : douta <= 16'h5C28 ; +440 : douta <= 16'h5C28 ; +441 : douta <= 16'h5C28 ; +442 : douta <= 16'h5C28 ; +443 : douta <= 16'h5C28 ; +444 : douta <= 16'h5C28 ; +445 : douta <= 16'h5C28 ; +446 : douta <= 16'h5C28 ; +447 : douta <= 16'h5C28 ; +448 : douta <= 16'h5C28 ; +449 : douta <= 16'h5C28 ; +450 : douta <= 16'h5C28 ; +451 : douta <= 16'h5C28 ; +452 : douta <= 16'h5C28 ; +453 : douta <= 16'h5C28 ; +454 : douta <= 16'h5C28 ; +455 : douta <= 16'h5B28 ; +456 : douta <= 16'h5C28 ; +457 : douta <= 16'h5C28 ; +458 : douta <= 16'h5B28 ; +459 : douta <= 16'h5B28 ; +460 : douta <= 16'h5B28 ; +461 : douta <= 16'h5B28 ; +462 : douta <= 16'h5B28 ; +463 : douta <= 16'h5B28 ; +464 : douta <= 16'h5B28 ; +465 : douta <= 16'h5B28 ; +466 : douta <= 16'h5B28 ; +467 : douta <= 16'h5A28 ; +468 : douta <= 16'h5A28 ; +469 : douta <= 16'h5A28 ; +470 : douta <= 16'h5A28 ; +471 : douta <= 16'h5A28 ; +472 : douta <= 16'h5A28 ; +473 : douta <= 16'h5A28 ; +474 : douta <= 16'h5A28 ; +475 : douta <= 16'h5A28 ; +476 : douta <= 16'h5A28 ; +477 : douta <= 16'h5A28 ; +478 : douta <= 16'h5A28 ; +479 : douta <= 16'h5A28 ; +480 : douta <= 16'h5A28 ; +481 : douta <= 16'h5A28 ; +482 : douta <= 16'h5A28 ; +483 : douta <= 16'h5A28 ; +484 : douta <= 16'h5A28 ; +485 : douta <= 16'h5A28 ; +486 : douta <= 16'h5A28 ; +487 : douta <= 16'h5A28 ; +488 : douta <= 16'h5A28 ; +489 : douta <= 16'h5928 ; +490 : douta <= 16'h5928 ; +491 : douta <= 16'h5928 ; +492 : douta <= 16'h5928 ; +493 : douta <= 16'h5928 ; +494 : douta <= 16'h5928 ; +495 : douta <= 16'h5928 ; +496 : douta <= 16'h5928 ; +497 : douta <= 16'h5928 ; +498 : douta <= 16'h5928 ; +499 : douta <= 16'h5928 ; +500 : douta <= 16'h5928 ; +501 : douta <= 16'h5928 ; +502 : douta <= 16'h5828 ; +503 : douta <= 16'h5828 ; +504 : douta <= 16'h5828 ; +505 : douta <= 16'h5828 ; +506 : douta <= 16'h5828 ; +507 : douta <= 16'h5928 ; +508 : douta <= 16'h5928 ; +509 : douta <= 16'h5928 ; +510 : douta <= 16'h5928 ; +511 : douta <= 16'h5928 ; +512 : douta <= 16'h5928 ; +513 : douta <= 16'h5928 ; +514 : douta <= 16'h5828 ; +515 : douta <= 16'h5828 ; +516 : douta <= 16'h5828 ; +517 : douta <= 16'h5828 ; +518 : douta <= 16'h5828 ; +519 : douta <= 16'h5828 ; +520 : douta <= 16'h5828 ; +521 : douta <= 16'h5828 ; +522 : douta <= 16'h5828 ; +523 : douta <= 16'h5828 ; +524 : douta <= 16'h5828 ; +525 : douta <= 16'h5828 ; +526 : douta <= 16'h5828 ; +527 : douta <= 16'h5828 ; +528 : douta <= 16'h5828 ; +529 : douta <= 16'h5828 ; +530 : douta <= 16'h5828 ; +531 : douta <= 16'h5828 ; +532 : douta <= 16'h5728 ; +533 : douta <= 16'h5728 ; +534 : douta <= 16'h5728 ; +535 : douta <= 16'h5828 ; +536 : douta <= 16'h5828 ; +537 : douta <= 16'h5728 ; +538 : douta <= 16'h5728 ; +539 : douta <= 16'h5728 ; +540 : douta <= 16'h5728 ; +541 : douta <= 16'h5528 ; +542 : douta <= 16'h5728 ; +543 : douta <= 16'h5528 ; +544 : douta <= 16'h5728 ; +545 : douta <= 16'h5728 ; +546 : douta <= 16'h5728 ; +547 : douta <= 16'h5628 ; +548 : douta <= 16'h5628 ; +549 : douta <= 16'h5628 ; +550 : douta <= 16'h5628 ; +551 : douta <= 16'h5628 ; +552 : douta <= 16'h5628 ; +553 : douta <= 16'h5628 ; +554 : douta <= 16'h5628 ; +555 : douta <= 16'h5628 ; +556 : douta <= 16'h5628 ; +557 : douta <= 16'h5628 ; +558 : douta <= 16'h5628 ; +559 : douta <= 16'h5628 ; +560 : douta <= 16'h5628 ; +561 : douta <= 16'h5628 ; +562 : douta <= 16'h5628 ; +563 : douta <= 16'h5628 ; +564 : douta <= 16'h5628 ; +565 : douta <= 16'h5628 ; +566 : douta <= 16'h5628 ; +567 : douta <= 16'h5628 ; +568 : douta <= 16'h5628 ; +569 : douta <= 16'h5628 ; +570 : douta <= 16'h5628 ; +571 : douta <= 16'h5528 ; +572 : douta <= 16'h5528 ; +573 : douta <= 16'h5528 ; +574 : douta <= 16'h5528 ; +575 : douta <= 16'h5528 ; +576 : douta <= 16'h5528 ; +577 : douta <= 16'h5528 ; +578 : douta <= 16'h5528 ; +579 : douta <= 16'h5528 ; +580 : douta <= 16'h5528 ; +581 : douta <= 16'h5528 ; +582 : douta <= 16'h5528 ; +583 : douta <= 16'h5528 ; +584 : douta <= 16'h5528 ; +585 : douta <= 16'h5528 ; +586 : douta <= 16'h5428 ; +587 : douta <= 16'h5528 ; +588 : douta <= 16'h5528 ; +589 : douta <= 16'h5528 ; +590 : douta <= 16'h5528 ; +591 : douta <= 16'h5528 ; +592 : douta <= 16'h5528 ; +593 : douta <= 16'h5528 ; +594 : douta <= 16'h5528 ; +595 : douta <= 16'h5528 ; +596 : douta <= 16'h5428 ; +597 : douta <= 16'h5428 ; +598 : douta <= 16'h5428 ; +599 : douta <= 16'h5428 ; +600 : douta <= 16'h5428 ; +601 : douta <= 16'h5428 ; +602 : douta <= 16'h5428 ; +603 : douta <= 16'h5428 ; +604 : douta <= 16'h5428 ; +605 : douta <= 16'h5428 ; +606 : douta <= 16'h5428 ; +607 : douta <= 16'h5428 ; +608 : douta <= 16'h5428 ; +609 : douta <= 16'h5428 ; +610 : douta <= 16'h5428 ; +611 : douta <= 16'h5428 ; +612 : douta <= 16'h5428 ; +613 : douta <= 16'h5428 ; +614 : douta <= 16'h5428 ; +615 : douta <= 16'h5428 ; +616 : douta <= 16'h5328 ; +617 : douta <= 16'h5328 ; +618 : douta <= 16'h5328 ; +619 : douta <= 16'h5328 ; +620 : douta <= 16'h5428 ; +621 : douta <= 16'h5328 ; +622 : douta <= 16'h5328 ; +623 : douta <= 16'h5328 ; +624 : douta <= 16'h5328 ; +625 : douta <= 16'h5328 ; +626 : douta <= 16'h5328 ; +627 : douta <= 16'h5328 ; +628 : douta <= 16'h5328 ; +629 : douta <= 16'h5328 ; +630 : douta <= 16'h5328 ; +631 : douta <= 16'h5328 ; +632 : douta <= 16'h5328 ; +633 : douta <= 16'h5328 ; +634 : douta <= 16'h5228 ; +635 : douta <= 16'h5228 ; +636 : douta <= 16'h5128 ; +637 : douta <= 16'h5128 ; +638 : douta <= 16'h5128 ; +639 : douta <= 16'h5228 ; +640 : douta <= 16'h5228 ; +641 : douta <= 16'h5228 ; +642 : douta <= 16'h5228 ; +643 : douta <= 16'h5228 ; +644 : douta <= 16'h5228 ; +645 : douta <= 16'h5228 ; +646 : douta <= 16'h5228 ; +647 : douta <= 16'h5228 ; +648 : douta <= 16'h5228 ; +649 : douta <= 16'h5228 ; +650 : douta <= 16'h5228 ; +651 : douta <= 16'h5228 ; +652 : douta <= 16'h5228 ; +653 : douta <= 16'h5228 ; +654 : douta <= 16'h5228 ; +655 : douta <= 16'h5228 ; +656 : douta <= 16'h5128 ; +657 : douta <= 16'h5128 ; +658 : douta <= 16'h5128 ; +659 : douta <= 16'h5128 ; +660 : douta <= 16'h5128 ; +661 : douta <= 16'h5128 ; +662 : douta <= 16'h5128 ; +663 : douta <= 16'h5128 ; +664 : douta <= 16'h5128 ; +665 : douta <= 16'h5128 ; +666 : douta <= 16'h5128 ; +667 : douta <= 16'h5128 ; +668 : douta <= 16'h5128 ; +669 : douta <= 16'h5128 ; +670 : douta <= 16'h5128 ; +671 : douta <= 16'h5028 ; +672 : douta <= 16'h5028 ; +673 : douta <= 16'h5128 ; +674 : douta <= 16'h5128 ; +675 : douta <= 16'h5128 ; +676 : douta <= 16'h5128 ; +677 : douta <= 16'h5128 ; +678 : douta <= 16'h5128 ; +679 : douta <= 16'h5128 ; +680 : douta <= 16'h5128 ; +681 : douta <= 16'h5128 ; +682 : douta <= 16'h5028 ; +683 : douta <= 16'h5028 ; +684 : douta <= 16'h5028 ; +685 : douta <= 16'h4E28 ; +686 : douta <= 16'h5028 ; +687 : douta <= 16'h5028 ; +688 : douta <= 16'h4F28 ; +689 : douta <= 16'h5028 ; +690 : douta <= 16'h5028 ; +691 : douta <= 16'h5028 ; +692 : douta <= 16'h4F28 ; +693 : douta <= 16'h5028 ; +694 : douta <= 16'h5028 ; +695 : douta <= 16'h5028 ; +696 : douta <= 16'h5028 ; +697 : douta <= 16'h5028 ; +698 : douta <= 16'h5028 ; +699 : douta <= 16'h5028 ; +700 : douta <= 16'h5028 ; +701 : douta <= 16'h5028 ; +702 : douta <= 16'h5028 ; +703 : douta <= 16'h5028 ; +704 : douta <= 16'h5028 ; +705 : douta <= 16'h5028 ; +706 : douta <= 16'h5028 ; +707 : douta <= 16'h5028 ; +708 : douta <= 16'h4D28 ; +709 : douta <= 16'h4D28 ; +710 : douta <= 16'h4E28 ; +711 : douta <= 16'h4E28 ; +712 : douta <= 16'h4E28 ; +713 : douta <= 16'h4E28 ; +714 : douta <= 16'h4E28 ; +715 : douta <= 16'h4E28 ; +716 : douta <= 16'h4E28 ; +717 : douta <= 16'h4E28 ; +718 : douta <= 16'h4E28 ; +719 : douta <= 16'h4E28 ; +720 : douta <= 16'h4E28 ; +721 : douta <= 16'h4E28 ; +722 : douta <= 16'h4E28 ; +723 : douta <= 16'h4E28 ; +724 : douta <= 16'h4E28 ; +725 : douta <= 16'h4E28 ; +726 : douta <= 16'h4E28 ; +727 : douta <= 16'h4E28 ; +728 : douta <= 16'h4E28 ; +729 : douta <= 16'h4E28 ; +730 : douta <= 16'h4E28 ; +731 : douta <= 16'h4E28 ; +732 : douta <= 16'h4E28 ; +733 : douta <= 16'h4E28 ; +734 : douta <= 16'h4D28 ; +735 : douta <= 16'h4D28 ; +736 : douta <= 16'h4D28 ; +737 : douta <= 16'h4D28 ; +738 : douta <= 16'h4D28 ; +739 : douta <= 16'h4D28 ; +740 : douta <= 16'h4D28 ; +741 : douta <= 16'h4D28 ; +742 : douta <= 16'h4D28 ; +743 : douta <= 16'h4D28 ; +744 : douta <= 16'h4D28 ; +745 : douta <= 16'h4D28 ; +746 : douta <= 16'h4D28 ; +747 : douta <= 16'h4C28 ; +748 : douta <= 16'h4C28 ; +749 : douta <= 16'h4D28 ; +750 : douta <= 16'h4D28 ; +751 : douta <= 16'h4D28 ; +752 : douta <= 16'h4D28 ; +753 : douta <= 16'h4D28 ; +754 : douta <= 16'h4D28 ; +755 : douta <= 16'h4D28 ; +756 : douta <= 16'h4D28 ; +757 : douta <= 16'h4D28 ; +758 : douta <= 16'h4D28 ; +759 : douta <= 16'h4D28 ; +760 : douta <= 16'h4B28 ; +761 : douta <= 16'h4B28 ; +762 : douta <= 16'h4C28 ; +763 : douta <= 16'h4C28 ; +764 : douta <= 16'h4C28 ; +765 : douta <= 16'h4C28 ; +766 : douta <= 16'h4C28 ; +767 : douta <= 16'h4C28 ; +768 : douta <= 16'h4C28 ; +769 : douta <= 16'h4C28 ; +770 : douta <= 16'h4C28 ; +771 : douta <= 16'h4C28 ; +772 : douta <= 16'h4C28 ; +773 : douta <= 16'h4C28 ; +774 : douta <= 16'h4C28 ; +775 : douta <= 16'h4C28 ; +776 : douta <= 16'h4C28 ; +777 : douta <= 16'h4C28 ; +778 : douta <= 16'h4C28 ; +779 : douta <= 16'h4C28 ; +780 : douta <= 16'h4C28 ; +781 : douta <= 16'h4C28 ; +782 : douta <= 16'h4C28 ; +783 : douta <= 16'h4C28 ; +784 : douta <= 16'h4C28 ; +785 : douta <= 16'h4C28 ; +786 : douta <= 16'h4B28 ; +787 : douta <= 16'h4B28 ; +788 : douta <= 16'h4B28 ; +789 : douta <= 16'h4B28 ; +790 : douta <= 16'h4B28 ; +791 : douta <= 16'h4B28 ; +792 : douta <= 16'h4B28 ; +793 : douta <= 16'h4B28 ; +794 : douta <= 16'h4B28 ; +795 : douta <= 16'h4A28 ; +796 : douta <= 16'h4A28 ; +797 : douta <= 16'h4A28 ; +798 : douta <= 16'h4A28 ; +799 : douta <= 16'h4A28 ; +800 : douta <= 16'h4A28 ; +801 : douta <= 16'h4928 ; +802 : douta <= 16'h4A28 ; +803 : douta <= 16'h4928 ; +804 : douta <= 16'h4A28 ; +805 : douta <= 16'h4A28 ; +806 : douta <= 16'h4A28 ; +807 : douta <= 16'h4A28 ; +808 : douta <= 16'h4A28 ; +809 : douta <= 16'h4A28 ; +810 : douta <= 16'h4A28 ; +811 : douta <= 16'h4A28 ; +812 : douta <= 16'h4A28 ; +813 : douta <= 16'h4A28 ; +814 : douta <= 16'h4A28 ; +815 : douta <= 16'h4A28 ; +816 : douta <= 16'h4A28 ; +817 : douta <= 16'h4A28 ; +818 : douta <= 16'h4928 ; +819 : douta <= 16'h4928 ; +820 : douta <= 16'h4928 ; +821 : douta <= 16'h4928 ; +822 : douta <= 16'h4928 ; +823 : douta <= 16'h4928 ; +824 : douta <= 16'h4928 ; +825 : douta <= 16'h4928 ; +826 : douta <= 16'h4928 ; +827 : douta <= 16'h4928 ; +828 : douta <= 16'h4928 ; +829 : douta <= 16'h4928 ; +830 : douta <= 16'h4928 ; +831 : douta <= 16'h4828 ; +832 : douta <= 16'h4928 ; +833 : douta <= 16'h4928 ; +834 : douta <= 16'h4928 ; +835 : douta <= 16'h4928 ; +836 : douta <= 16'h4928 ; +837 : douta <= 16'h4928 ; +838 : douta <= 16'h4928 ; +839 : douta <= 16'h4928 ; +840 : douta <= 16'h4928 ; +841 : douta <= 16'h4928 ; +842 : douta <= 16'h4928 ; +843 : douta <= 16'h4928 ; +844 : douta <= 16'h4828 ; +845 : douta <= 16'h4828 ; +846 : douta <= 16'h4728 ; +847 : douta <= 16'h4728 ; +848 : douta <= 16'h4828 ; +849 : douta <= 16'h4828 ; +850 : douta <= 16'h4828 ; +851 : douta <= 16'h4828 ; +852 : douta <= 16'h4828 ; +853 : douta <= 16'h4828 ; +854 : douta <= 16'h4828 ; +855 : douta <= 16'h4828 ; +856 : douta <= 16'h4828 ; +857 : douta <= 16'h4828 ; +858 : douta <= 16'h4828 ; +859 : douta <= 16'h4828 ; +860 : douta <= 16'h4828 ; +861 : douta <= 16'h4828 ; +862 : douta <= 16'h4828 ; +863 : douta <= 16'h4828 ; +864 : douta <= 16'h4828 ; +865 : douta <= 16'h4828 ; +866 : douta <= 16'h4828 ; +867 : douta <= 16'h4828 ; +868 : douta <= 16'h4828 ; +869 : douta <= 16'h4528 ; +870 : douta <= 16'h4728 ; +871 : douta <= 16'h4528 ; +872 : douta <= 16'h4528 ; +873 : douta <= 16'h4728 ; +874 : douta <= 16'h4528 ; +875 : douta <= 16'h4728 ; +876 : douta <= 16'h4628 ; +877 : douta <= 16'h4628 ; +878 : douta <= 16'h4628 ; +879 : douta <= 16'h4628 ; +880 : douta <= 16'h4628 ; +881 : douta <= 16'h4628 ; +882 : douta <= 16'h4628 ; +883 : douta <= 16'h4628 ; +884 : douta <= 16'h4628 ; +885 : douta <= 16'h4628 ; +886 : douta <= 16'h4628 ; +887 : douta <= 16'h4628 ; +888 : douta <= 16'h4628 ; +889 : douta <= 16'h4628 ; +890 : douta <= 16'h4628 ; +891 : douta <= 16'h4628 ; +892 : douta <= 16'h4628 ; +893 : douta <= 16'h4628 ; +894 : douta <= 16'h4628 ; +895 : douta <= 16'h4628 ; +896 : douta <= 16'h4628 ; +897 : douta <= 16'h4528 ; +898 : douta <= 16'h4628 ; +899 : douta <= 16'h4528 ; +900 : douta <= 16'h4528 ; +901 : douta <= 16'h4528 ; +902 : douta <= 16'h4528 ; +903 : douta <= 16'h4528 ; +904 : douta <= 16'h4528 ; +905 : douta <= 16'h4528 ; +906 : douta <= 16'h4528 ; +907 : douta <= 16'h4528 ; +908 : douta <= 16'h4528 ; +909 : douta <= 16'h4528 ; +910 : douta <= 16'h4528 ; +911 : douta <= 16'h4528 ; +912 : douta <= 16'h4528 ; +913 : douta <= 16'h4428 ; +914 : douta <= 16'h4428 ; +915 : douta <= 16'h4528 ; +916 : douta <= 16'h4428 ; +917 : douta <= 16'h4428 ; +918 : douta <= 16'h4528 ; +919 : douta <= 16'h4528 ; +920 : douta <= 16'h4528 ; +921 : douta <= 16'h4528 ; +922 : douta <= 16'h4528 ; +923 : douta <= 16'h4528 ; +924 : douta <= 16'h4528 ; +925 : douta <= 16'h4528 ; +926 : douta <= 16'h4528 ; +927 : douta <= 16'h4428 ; +928 : douta <= 16'h4428 ; +929 : douta <= 16'h4428 ; +930 : douta <= 16'h4428 ; +931 : douta <= 16'h4428 ; +932 : douta <= 16'h4428 ; +933 : douta <= 16'h4428 ; +934 : douta <= 16'h4428 ; +935 : douta <= 16'h4428 ; +936 : douta <= 16'h4428 ; +937 : douta <= 16'h4428 ; +938 : douta <= 16'h4428 ; +939 : douta <= 16'h4428 ; +940 : douta <= 16'h4428 ; +941 : douta <= 16'h4428 ; +942 : douta <= 16'h4428 ; +943 : douta <= 16'h4428 ; +944 : douta <= 16'h4428 ; +945 : douta <= 16'h4428 ; +946 : douta <= 16'h4328 ; +947 : douta <= 16'h4328 ; +948 : douta <= 16'h4428 ; +949 : douta <= 16'h4328 ; +950 : douta <= 16'h4428 ; +951 : douta <= 16'h4428 ; +952 : douta <= 16'h4328 ; +953 : douta <= 16'h4328 ; +954 : douta <= 16'h4328 ; +955 : douta <= 16'h4328 ; +956 : douta <= 16'h4328 ; +957 : douta <= 16'h4328 ; +958 : douta <= 16'h4328 ; +959 : douta <= 16'h4328 ; +960 : douta <= 16'h4328 ; +961 : douta <= 16'h4328 ; +962 : douta <= 16'h4328 ; +963 : douta <= 16'h4228 ; +964 : douta <= 16'h4228 ; +965 : douta <= 16'h4228 ; +966 : douta <= 16'h4228 ; +967 : douta <= 16'h4228 ; +968 : douta <= 16'h4228 ; +969 : douta <= 16'h4228 ; +970 : douta <= 16'h4228 ; +971 : douta <= 16'h4228 ; +972 : douta <= 16'h4228 ; +973 : douta <= 16'h4228 ; +974 : douta <= 16'h4228 ; +975 : douta <= 16'h4228 ; +976 : douta <= 16'h4228 ; +977 : douta <= 16'h4228 ; +978 : douta <= 16'h4228 ; +979 : douta <= 16'h4228 ; +980 : douta <= 16'h4228 ; +981 : douta <= 16'h4228 ; +982 : douta <= 16'h4228 ; +983 : douta <= 16'h4228 ; +984 : douta <= 16'h4128 ; +985 : douta <= 16'h4128 ; +986 : douta <= 16'h4128 ; +987 : douta <= 16'h4128 ; +988 : douta <= 16'h4128 ; +989 : douta <= 16'h4128 ; +990 : douta <= 16'h4128 ; +991 : douta <= 16'h4128 ; +992 : douta <= 16'h4128 ; +993 : douta <= 16'h4128 ; +994 : douta <= 16'h4128 ; +995 : douta <= 16'h4128 ; +996 : douta <= 16'h4128 ; +997 : douta <= 16'h4128 ; +998 : douta <= 16'h4128 ; +999 : douta <= 16'h4128 ; +1000 : douta <= 16'h4128 ; +1001 : douta <= 16'h4128 ; +1002 : douta <= 16'h4128 ; +1003 : douta <= 16'h4128 ; +1004 : douta <= 16'h4028 ; +1005 : douta <= 16'h4128 ; +1006 : douta <= 16'h4128 ; +1007 : douta <= 16'h4128 ; +1008 : douta <= 16'h4128 ; +1009 : douta <= 16'h4128 ; +1010 : douta <= 16'h4128 ; +1011 : douta <= 16'h4128 ; +1012 : douta <= 16'h4128 ; +1013 : douta <= 16'h4128 ; +1014 : douta <= 16'h4128 ; +1015 : douta <= 16'h4028 ; +1016 : douta <= 16'h4028 ; +1017 : douta <= 16'h4028 ; +1018 : douta <= 16'h4028 ; +1019 : douta <= 16'h4028 ; +1020 : douta <= 16'h4028 ; +1021 : douta <= 16'h4028 ; +1022 : douta <= 16'h4028 ; +1023 : douta <= 16'h3F2A ; +1024 : douta <= 16'h4028 ; +1025 : douta <= 16'h4028 ; +1026 : douta <= 16'h3E2A ; +1027 : douta <= 16'h4028 ; +1028 : douta <= 16'h3F2A ; +1029 : douta <= 16'h4028 ; +1030 : douta <= 16'h4028 ; +1031 : douta <= 16'h4028 ; +1032 : douta <= 16'h4028 ; +1033 : douta <= 16'h4028 ; +1034 : douta <= 16'h4028 ; +1035 : douta <= 16'h4028 ; +1036 : douta <= 16'h4028 ; +1037 : douta <= 16'h4028 ; +1038 : douta <= 16'h4028 ; +1039 : douta <= 16'h4028 ; +1040 : douta <= 16'h4028 ; +1041 : douta <= 16'h4028 ; +1042 : douta <= 16'h4028 ; +1043 : douta <= 16'h4028 ; +1044 : douta <= 16'h4028 ; +1045 : douta <= 16'h4028 ; +1046 : douta <= 16'h4028 ; +1047 : douta <= 16'h4028 ; +1048 : douta <= 16'h4028 ; +1049 : douta <= 16'h4028 ; +1050 : douta <= 16'h3D2A ; +1051 : douta <= 16'h4028 ; +1052 : douta <= 16'h3E2A ; +1053 : douta <= 16'h3E2A ; +1054 : douta <= 16'h3E2A ; +1055 : douta <= 16'h3E2A ; +1056 : douta <= 16'h3E2A ; +1057 : douta <= 16'h3E2A ; +1058 : douta <= 16'h3E2A ; +1059 : douta <= 16'h3E2A ; +1060 : douta <= 16'h3E2A ; +1061 : douta <= 16'h3E2A ; +1062 : douta <= 16'h3E2A ; +1063 : douta <= 16'h3E2A ; +1064 : douta <= 16'h3E2A ; +1065 : douta <= 16'h3E2A ; +1066 : douta <= 16'h3E2A ; +1067 : douta <= 16'h3E2A ; +1068 : douta <= 16'h3E2A ; +1069 : douta <= 16'h3E2A ; +1070 : douta <= 16'h3E2A ; +1071 : douta <= 16'h3E2A ; +1072 : douta <= 16'h3E2A ; +1073 : douta <= 16'h3E2A ; +1074 : douta <= 16'h3E2A ; +1075 : douta <= 16'h3E2A ; +1076 : douta <= 16'h3D2A ; +1077 : douta <= 16'h3E2A ; +1078 : douta <= 16'h3D2A ; +1079 : douta <= 16'h3D2A ; +1080 : douta <= 16'h3D2A ; +1081 : douta <= 16'h3D2A ; +1082 : douta <= 16'h3D2A ; +1083 : douta <= 16'h3D2A ; +1084 : douta <= 16'h3D2A ; +1085 : douta <= 16'h3D2A ; +1086 : douta <= 16'h3D2A ; +1087 : douta <= 16'h3D2A ; +1088 : douta <= 16'h3D2A ; +1089 : douta <= 16'h3D2A ; +1090 : douta <= 16'h3D2A ; +1091 : douta <= 16'h3D2A ; +1092 : douta <= 16'h3C2A ; +1093 : douta <= 16'h3D2A ; +1094 : douta <= 16'h3D2A ; +1095 : douta <= 16'h3D2A ; +1096 : douta <= 16'h3C2A ; +1097 : douta <= 16'h3D2A ; +1098 : douta <= 16'h3D2A ; +1099 : douta <= 16'h3D2A ; +1100 : douta <= 16'h3D2A ; +1101 : douta <= 16'h3D2A ; +1102 : douta <= 16'h3C2A ; +1103 : douta <= 16'h3D2A ; +1104 : douta <= 16'h3B2A ; +1105 : douta <= 16'h3B2A ; +1106 : douta <= 16'h3B2A ; +1107 : douta <= 16'h3C2A ; +1108 : douta <= 16'h3C2A ; +1109 : douta <= 16'h3C2A ; +1110 : douta <= 16'h3C2A ; +1111 : douta <= 16'h3C2A ; +1112 : douta <= 16'h3C2A ; +1113 : douta <= 16'h3C2A ; +1114 : douta <= 16'h3C2A ; +1115 : douta <= 16'h3C2A ; +1116 : douta <= 16'h3C2A ; +1117 : douta <= 16'h3C2A ; +1118 : douta <= 16'h3C2A ; +1119 : douta <= 16'h3C2A ; +1120 : douta <= 16'h3C2A ; +1121 : douta <= 16'h3C2A ; +1122 : douta <= 16'h3C2A ; +1123 : douta <= 16'h3C2A ; +1124 : douta <= 16'h3C2A ; +1125 : douta <= 16'h3C2A ; +1126 : douta <= 16'h3C2A ; +1127 : douta <= 16'h3C2A ; +1128 : douta <= 16'h3C2A ; +1129 : douta <= 16'h3C2A ; +1130 : douta <= 16'h3C2A ; +1131 : douta <= 16'h3B2A ; +1132 : douta <= 16'h3B2A ; +1133 : douta <= 16'h3B2A ; +1134 : douta <= 16'h3B2A ; +1135 : douta <= 16'h3B2A ; +1136 : douta <= 16'h3B2A ; +1137 : douta <= 16'h3B2A ; +1138 : douta <= 16'h3A2A ; +1139 : douta <= 16'h3A2A ; +1140 : douta <= 16'h3A2A ; +1141 : douta <= 16'h3A2A ; +1142 : douta <= 16'h3A2A ; +1143 : douta <= 16'h3A2A ; +1144 : douta <= 16'h3A2A ; +1145 : douta <= 16'h3A2A ; +1146 : douta <= 16'h392A ; +1147 : douta <= 16'h392A ; +1148 : douta <= 16'h392A ; +1149 : douta <= 16'h3A2A ; +1150 : douta <= 16'h3A2A ; +1151 : douta <= 16'h3A2A ; +1152 : douta <= 16'h3A2A ; +1153 : douta <= 16'h3A2A ; +1154 : douta <= 16'h3A2A ; +1155 : douta <= 16'h3A2A ; +1156 : douta <= 16'h3A2A ; +1157 : douta <= 16'h3A2A ; +1158 : douta <= 16'h3A2A ; +1159 : douta <= 16'h3A2A ; +1160 : douta <= 16'h3A2A ; +1161 : douta <= 16'h3A2A ; +1162 : douta <= 16'h3A2A ; +1163 : douta <= 16'h392A ; +1164 : douta <= 16'h3A2A ; +1165 : douta <= 16'h392A ; +1166 : douta <= 16'h392A ; +1167 : douta <= 16'h392A ; +1168 : douta <= 16'h392A ; +1169 : douta <= 16'h392A ; +1170 : douta <= 16'h392A ; +1171 : douta <= 16'h392A ; +1172 : douta <= 16'h392A ; +1173 : douta <= 16'h392A ; +1174 : douta <= 16'h392A ; +1175 : douta <= 16'h392A ; +1176 : douta <= 16'h392A ; +1177 : douta <= 16'h392A ; +1178 : douta <= 16'h392A ; +1179 : douta <= 16'h382A ; +1180 : douta <= 16'h382A ; +1181 : douta <= 16'h392A ; +1182 : douta <= 16'h392A ; +1183 : douta <= 16'h392A ; +1184 : douta <= 16'h392A ; +1185 : douta <= 16'h392A ; +1186 : douta <= 16'h392A ; +1187 : douta <= 16'h392A ; +1188 : douta <= 16'h372A ; +1189 : douta <= 16'h372A ; +1190 : douta <= 16'h372A ; +1191 : douta <= 16'h372A ; +1192 : douta <= 16'h382A ; +1193 : douta <= 16'h382A ; +1194 : douta <= 16'h382A ; +1195 : douta <= 16'h382A ; +1196 : douta <= 16'h382A ; +1197 : douta <= 16'h382A ; +1198 : douta <= 16'h382A ; +1199 : douta <= 16'h382A ; +1200 : douta <= 16'h382A ; +1201 : douta <= 16'h382A ; +1202 : douta <= 16'h382A ; +1203 : douta <= 16'h382A ; +1204 : douta <= 16'h382A ; +1205 : douta <= 16'h382A ; +1206 : douta <= 16'h382A ; +1207 : douta <= 16'h382A ; +1208 : douta <= 16'h382A ; +1209 : douta <= 16'h382A ; +1210 : douta <= 16'h382A ; +1211 : douta <= 16'h382A ; +1212 : douta <= 16'h382A ; +1213 : douta <= 16'h382A ; +1214 : douta <= 16'h382A ; +1215 : douta <= 16'h382A ; +1216 : douta <= 16'h382A ; +1217 : douta <= 16'h372A ; +1218 : douta <= 16'h382A ; +1219 : douta <= 16'h372A ; +1220 : douta <= 16'h372A ; +1221 : douta <= 16'h372A ; +1222 : douta <= 16'h372A ; +1223 : douta <= 16'h372A ; +1224 : douta <= 16'h372A ; +1225 : douta <= 16'h372A ; +1226 : douta <= 16'h372A ; +1227 : douta <= 16'h362A ; +1228 : douta <= 16'h352A ; +1229 : douta <= 16'h362A ; +1230 : douta <= 16'h362A ; +1231 : douta <= 16'h362A ; +1232 : douta <= 16'h362A ; +1233 : douta <= 16'h362A ; +1234 : douta <= 16'h362A ; +1235 : douta <= 16'h362A ; +1236 : douta <= 16'h362A ; +1237 : douta <= 16'h362A ; +1238 : douta <= 16'h362A ; +1239 : douta <= 16'h362A ; +1240 : douta <= 16'h362A ; +1241 : douta <= 16'h362A ; +1242 : douta <= 16'h362A ; +1243 : douta <= 16'h362A ; +1244 : douta <= 16'h362A ; +1245 : douta <= 16'h362A ; +1246 : douta <= 16'h362A ; +1247 : douta <= 16'h362A ; +1248 : douta <= 16'h362A ; +1249 : douta <= 16'h362A ; +1250 : douta <= 16'h362A ; +1251 : douta <= 16'h362A ; +1252 : douta <= 16'h362A ; +1253 : douta <= 16'h352A ; +1254 : douta <= 16'h352A ; +1255 : douta <= 16'h352A ; +1256 : douta <= 16'h352A ; +1257 : douta <= 16'h352A ; +1258 : douta <= 16'h352A ; +1259 : douta <= 16'h352A ; +1260 : douta <= 16'h352A ; +1261 : douta <= 16'h352A ; +1262 : douta <= 16'h352A ; +1263 : douta <= 16'h352A ; +1264 : douta <= 16'h352A ; +1265 : douta <= 16'h352A ; +1266 : douta <= 16'h352A ; +1267 : douta <= 16'h342A ; +1268 : douta <= 16'h342A ; +1269 : douta <= 16'h352A ; +1270 : douta <= 16'h352A ; +1271 : douta <= 16'h352A ; +1272 : douta <= 16'h352A ; +1273 : douta <= 16'h352A ; +1274 : douta <= 16'h352A ; +1275 : douta <= 16'h352A ; +1276 : douta <= 16'h352A ; +1277 : douta <= 16'h352A ; +1278 : douta <= 16'h352A ; +1279 : douta <= 16'h352A ; +1280 : douta <= 16'h342A ; +1281 : douta <= 16'h342A ; +1282 : douta <= 16'h342A ; +1283 : douta <= 16'h342A ; +1284 : douta <= 16'h342A ; +1285 : douta <= 16'h342A ; +1286 : douta <= 16'h342A ; +1287 : douta <= 16'h342A ; +1288 : douta <= 16'h342A ; +1289 : douta <= 16'h342A ; +1290 : douta <= 16'h342A ; +1291 : douta <= 16'h342A ; +1292 : douta <= 16'h342A ; +1293 : douta <= 16'h342A ; +1294 : douta <= 16'h342A ; +1295 : douta <= 16'h342A ; +1296 : douta <= 16'h332A ; +1297 : douta <= 16'h332A ; +1298 : douta <= 16'h332A ; +1299 : douta <= 16'h342A ; +1300 : douta <= 16'h342A ; +1301 : douta <= 16'h342A ; +1302 : douta <= 16'h342A ; +1303 : douta <= 16'h342A ; +1304 : douta <= 16'h342A ; +1305 : douta <= 16'h332A ; +1306 : douta <= 16'h332A ; +1307 : douta <= 16'h332A ; +1308 : douta <= 16'h332A ; +1309 : douta <= 16'h332A ; +1310 : douta <= 16'h332A ; +1311 : douta <= 16'h332A ; +1312 : douta <= 16'h332A ; +1313 : douta <= 16'h332A ; +1314 : douta <= 16'h332A ; +1315 : douta <= 16'h322A ; +1316 : douta <= 16'h322A ; +1317 : douta <= 16'h322A ; +1318 : douta <= 16'h322A ; +1319 : douta <= 16'h322A ; +1320 : douta <= 16'h322A ; +1321 : douta <= 16'h312A ; +1322 : douta <= 16'h322A ; +1323 : douta <= 16'h312A ; +1324 : douta <= 16'h312A ; +1325 : douta <= 16'h322A ; +1326 : douta <= 16'h322A ; +1327 : douta <= 16'h322A ; +1328 : douta <= 16'h322A ; +1329 : douta <= 16'h322A ; +1330 : douta <= 16'h322A ; +1331 : douta <= 16'h322A ; +1332 : douta <= 16'h322A ; +1333 : douta <= 16'h322A ; +1334 : douta <= 16'h322A ; +1335 : douta <= 16'h322A ; +1336 : douta <= 16'h322A ; +1337 : douta <= 16'h322A ; +1338 : douta <= 16'h322A ; +1339 : douta <= 16'h322A ; +1340 : douta <= 16'h312A ; +1341 : douta <= 16'h312A ; +1342 : douta <= 16'h312A ; +1343 : douta <= 16'h312A ; +1344 : douta <= 16'h312A ; +1345 : douta <= 16'h312A ; +1346 : douta <= 16'h312A ; +1347 : douta <= 16'h312A ; +1348 : douta <= 16'h312A ; +1349 : douta <= 16'h312A ; +1350 : douta <= 16'h312A ; +1351 : douta <= 16'h312A ; +1352 : douta <= 16'h312A ; +1353 : douta <= 16'h312A ; +1354 : douta <= 16'h312A ; +1355 : douta <= 16'h312A ; +1356 : douta <= 16'h302A ; +1357 : douta <= 16'h312A ; +1358 : douta <= 16'h312A ; +1359 : douta <= 16'h312A ; +1360 : douta <= 16'h312A ; +1361 : douta <= 16'h312A ; +1362 : douta <= 16'h312A ; +1363 : douta <= 16'h312A ; +1364 : douta <= 16'h312A ; +1365 : douta <= 16'h312A ; +1366 : douta <= 16'h2F2A ; +1367 : douta <= 16'h302A ; +1368 : douta <= 16'h302A ; +1369 : douta <= 16'h302A ; +1370 : douta <= 16'h302A ; +1371 : douta <= 16'h302A ; +1372 : douta <= 16'h302A ; +1373 : douta <= 16'h302A ; +1374 : douta <= 16'h302A ; +1375 : douta <= 16'h302A ; +1376 : douta <= 16'h302A ; +1377 : douta <= 16'h302A ; +1378 : douta <= 16'h302A ; +1379 : douta <= 16'h302A ; +1380 : douta <= 16'h302A ; +1381 : douta <= 16'h302A ; +1382 : douta <= 16'h2F2A ; +1383 : douta <= 16'h302A ; +1384 : douta <= 16'h302A ; +1385 : douta <= 16'h302A ; +1386 : douta <= 16'h302A ; +1387 : douta <= 16'h302A ; +1388 : douta <= 16'h302A ; +1389 : douta <= 16'h302A ; +1390 : douta <= 16'h302A ; +1391 : douta <= 16'h2F2A ; +1392 : douta <= 16'h302A ; +1393 : douta <= 16'h302A ; +1394 : douta <= 16'h302A ; +1395 : douta <= 16'h2F2A ; +1396 : douta <= 16'h302A ; +1397 : douta <= 16'h2F2A ; +1398 : douta <= 16'h2F2A ; +1399 : douta <= 16'h2F2A ; +1400 : douta <= 16'h2E2A ; +1401 : douta <= 16'h2E2A ; +1402 : douta <= 16'h2D2A ; +1403 : douta <= 16'h2D2A ; +1404 : douta <= 16'h2D2A ; +1405 : douta <= 16'h2D2A ; +1406 : douta <= 16'h2E2A ; +1407 : douta <= 16'h2E2A ; +1408 : douta <= 16'h2E2A ; +1409 : douta <= 16'h2E2A ; +1410 : douta <= 16'h2E2A ; +1411 : douta <= 16'h2E2A ; +1412 : douta <= 16'h2E2A ; +1413 : douta <= 16'h2E2A ; +1414 : douta <= 16'h2E2A ; +1415 : douta <= 16'h2E2A ; +1416 : douta <= 16'h2E2A ; +1417 : douta <= 16'h2E2A ; +1418 : douta <= 16'h2E2A ; +1419 : douta <= 16'h2E2A ; +1420 : douta <= 16'h2E2A ; +1421 : douta <= 16'h2E2A ; +1422 : douta <= 16'h2E2A ; +1423 : douta <= 16'h2E2A ; +1424 : douta <= 16'h2E2A ; +1425 : douta <= 16'h2E2A ; +1426 : douta <= 16'h2E2A ; +1427 : douta <= 16'h2D2A ; +1428 : douta <= 16'h2E2A ; +1429 : douta <= 16'h2D2A ; +1430 : douta <= 16'h2D2A ; +1431 : douta <= 16'h2D2A ; +1432 : douta <= 16'h2D2A ; +1433 : douta <= 16'h2D2A ; +1434 : douta <= 16'h2D2A ; +1435 : douta <= 16'h2D2A ; +1436 : douta <= 16'h2D2A ; +1437 : douta <= 16'h2D2A ; +1438 : douta <= 16'h2D2A ; +1439 : douta <= 16'h2D2A ; +1440 : douta <= 16'h2D2A ; +1441 : douta <= 16'h2D2A ; +1442 : douta <= 16'h2D2A ; +1443 : douta <= 16'h2C2A ; +1444 : douta <= 16'h2D2A ; +1445 : douta <= 16'h2C2A ; +1446 : douta <= 16'h2D2A ; +1447 : douta <= 16'h2D2A ; +1448 : douta <= 16'h2D2A ; +1449 : douta <= 16'h2D2A ; +1450 : douta <= 16'h2D2A ; +1451 : douta <= 16'h2D2A ; +1452 : douta <= 16'h2D2A ; +1453 : douta <= 16'h2D2A ; +1454 : douta <= 16'h2D2A ; +1455 : douta <= 16'h2D2A ; +1456 : douta <= 16'h2C2A ; +1457 : douta <= 16'h2C2A ; +1458 : douta <= 16'h2C2A ; +1459 : douta <= 16'h2B2A ; +1460 : douta <= 16'h2B2A ; +1461 : douta <= 16'h2C2A ; +1462 : douta <= 16'h2C2A ; +1463 : douta <= 16'h2C2A ; +1464 : douta <= 16'h2C2A ; +1465 : douta <= 16'h2C2A ; +1466 : douta <= 16'h2C2A ; +1467 : douta <= 16'h2C2A ; +1468 : douta <= 16'h2C2A ; +1469 : douta <= 16'h2C2A ; +1470 : douta <= 16'h2C2A ; +1471 : douta <= 16'h2C2A ; +1472 : douta <= 16'h2C2A ; +1473 : douta <= 16'h2C2A ; +1474 : douta <= 16'h2C2A ; +1475 : douta <= 16'h2C2A ; +1476 : douta <= 16'h2C2A ; +1477 : douta <= 16'h2C2A ; +1478 : douta <= 16'h2C2A ; +1479 : douta <= 16'h2C2A ; +1480 : douta <= 16'h2C2A ; +1481 : douta <= 16'h2C2A ; +1482 : douta <= 16'h2C2A ; +1483 : douta <= 16'h2C2A ; +1484 : douta <= 16'h2C2A ; +1485 : douta <= 16'h2B2A ; +1486 : douta <= 16'h2B2A ; +1487 : douta <= 16'h2B2A ; +1488 : douta <= 16'h2B2A ; +1489 : douta <= 16'h2A2A ; +1490 : douta <= 16'h2B2A ; +1491 : douta <= 16'h2A2A ; +1492 : douta <= 16'h2A2A ; +1493 : douta <= 16'h2A2A ; +1494 : douta <= 16'h2A2A ; +1495 : douta <= 16'h2A2A ; +1496 : douta <= 16'h2A2A ; +1497 : douta <= 16'h2A2A ; +1498 : douta <= 16'h2A2A ; +1499 : douta <= 16'h2A2A ; +1500 : douta <= 16'h292A ; +1501 : douta <= 16'h292A ; +1502 : douta <= 16'h292A ; +1503 : douta <= 16'h2A2A ; +1504 : douta <= 16'h2A2A ; +1505 : douta <= 16'h2A2A ; +1506 : douta <= 16'h2A2A ; +1507 : douta <= 16'h2A2A ; +1508 : douta <= 16'h2A2A ; +1509 : douta <= 16'h2A2A ; +1510 : douta <= 16'h2A2A ; +1511 : douta <= 16'h2A2A ; +1512 : douta <= 16'h2A2A ; +1513 : douta <= 16'h2A2A ; +1514 : douta <= 16'h2A2A ; +1515 : douta <= 16'h292A ; +1516 : douta <= 16'h292A ; +1517 : douta <= 16'h292A ; +1518 : douta <= 16'h292A ; +1519 : douta <= 16'h292A ; +1520 : douta <= 16'h292A ; +1521 : douta <= 16'h292A ; +1522 : douta <= 16'h292A ; +1523 : douta <= 16'h292A ; +1524 : douta <= 16'h292A ; +1525 : douta <= 16'h292A ; +1526 : douta <= 16'h292A ; +1527 : douta <= 16'h292A ; +1528 : douta <= 16'h292A ; +1529 : douta <= 16'h292A ; +1530 : douta <= 16'h292A ; +1531 : douta <= 16'h292A ; +1532 : douta <= 16'h282A ; +1533 : douta <= 16'h282A ; +1534 : douta <= 16'h282A ; +1535 : douta <= 16'h292A ; +1536 : douta <= 16'h292A ; +1537 : douta <= 16'h292A ; +1538 : douta <= 16'h292A ; +1539 : douta <= 16'h292A ; +1540 : douta <= 16'h292A ; +1541 : douta <= 16'h292A ; +1542 : douta <= 16'h272A ; +1543 : douta <= 16'h292A ; +1544 : douta <= 16'h272A ; +1545 : douta <= 16'h272A ; +1546 : douta <= 16'h282A ; +1547 : douta <= 16'h282A ; +1548 : douta <= 16'h282A ; +1549 : douta <= 16'h282A ; +1550 : douta <= 16'h282A ; +1551 : douta <= 16'h282A ; +1552 : douta <= 16'h282A ; +1553 : douta <= 16'h282A ; +1554 : douta <= 16'h282A ; +1555 : douta <= 16'h282A ; +1556 : douta <= 16'h282A ; +1557 : douta <= 16'h282A ; +1558 : douta <= 16'h282A ; +1559 : douta <= 16'h282A ; +1560 : douta <= 16'h282A ; +1561 : douta <= 16'h282A ; +1562 : douta <= 16'h282A ; +1563 : douta <= 16'h282A ; +1564 : douta <= 16'h282A ; +1565 : douta <= 16'h282A ; +1566 : douta <= 16'h282A ; +1567 : douta <= 16'h282A ; +1568 : douta <= 16'h282A ; +1569 : douta <= 16'h282A ; +1570 : douta <= 16'h282A ; +1571 : douta <= 16'h282A ; +1572 : douta <= 16'h282A ; +1573 : douta <= 16'h282A ; +1574 : douta <= 16'h282A ; +1575 : douta <= 16'h272A ; +1576 : douta <= 16'h272A ; +1577 : douta <= 16'h272A ; +1578 : douta <= 16'h272A ; +1579 : douta <= 16'h272A ; +1580 : douta <= 16'h272A ; +1581 : douta <= 16'h272A ; +1582 : douta <= 16'h272A ; +1583 : douta <= 16'h262A ; +1584 : douta <= 16'h262A ; +1585 : douta <= 16'h252A ; +1586 : douta <= 16'h252A ; +1587 : douta <= 16'h262A ; +1588 : douta <= 16'h262A ; +1589 : douta <= 16'h252A ; +1590 : douta <= 16'h262A ; +1591 : douta <= 16'h262A ; +1592 : douta <= 16'h262A ; +1593 : douta <= 16'h262A ; +1594 : douta <= 16'h262A ; +1595 : douta <= 16'h262A ; +1596 : douta <= 16'h262A ; +1597 : douta <= 16'h262A ; +1598 : douta <= 16'h262A ; +1599 : douta <= 16'h262A ; +1600 : douta <= 16'h262A ; +1601 : douta <= 16'h262A ; +1602 : douta <= 16'h262A ; +1603 : douta <= 16'h262A ; +1604 : douta <= 16'h262A ; +1605 : douta <= 16'h262A ; +1606 : douta <= 16'h262A ; +1607 : douta <= 16'h262A ; +1608 : douta <= 16'h262A ; +1609 : douta <= 16'h252A ; +1610 : douta <= 16'h252A ; +1611 : douta <= 16'h252A ; +1612 : douta <= 16'h252A ; +1613 : douta <= 16'h252A ; +1614 : douta <= 16'h252A ; +1615 : douta <= 16'h252A ; +1616 : douta <= 16'h252A ; +1617 : douta <= 16'h252A ; +1618 : douta <= 16'h252A ; +1619 : douta <= 16'h252A ; +1620 : douta <= 16'h252A ; +1621 : douta <= 16'h252A ; +1622 : douta <= 16'h252A ; +1623 : douta <= 16'h252A ; +1624 : douta <= 16'h252A ; +1625 : douta <= 16'h242A ; +1626 : douta <= 16'h252A ; +1627 : douta <= 16'h252A ; +1628 : douta <= 16'h252A ; +1629 : douta <= 16'h252A ; +1630 : douta <= 16'h252A ; +1631 : douta <= 16'h252A ; +1632 : douta <= 16'h252A ; +1633 : douta <= 16'h252A ; +1634 : douta <= 16'h252A ; +1635 : douta <= 16'h252A ; +1636 : douta <= 16'h252A ; +1637 : douta <= 16'h252A ; +1638 : douta <= 16'h242A ; +1639 : douta <= 16'h242A ; +1640 : douta <= 16'h242A ; +1641 : douta <= 16'h242A ; +1642 : douta <= 16'h242A ; +1643 : douta <= 16'h242A ; +1644 : douta <= 16'h242A ; +1645 : douta <= 16'h242A ; +1646 : douta <= 16'h242A ; +1647 : douta <= 16'h242A ; +1648 : douta <= 16'h242A ; +1649 : douta <= 16'h242A ; +1650 : douta <= 16'h242A ; +1651 : douta <= 16'h242A ; +1652 : douta <= 16'h232A ; +1653 : douta <= 16'h232A ; +1654 : douta <= 16'h242A ; +1655 : douta <= 16'h242A ; +1656 : douta <= 16'h242A ; +1657 : douta <= 16'h242A ; +1658 : douta <= 16'h242A ; +1659 : douta <= 16'h242A ; +1660 : douta <= 16'h242A ; +1661 : douta <= 16'h242A ; +1662 : douta <= 16'h242A ; +1663 : douta <= 16'h242A ; +1664 : douta <= 16'h242A ; +1665 : douta <= 16'h232A ; +1666 : douta <= 16'h232A ; +1667 : douta <= 16'h232A ; +1668 : douta <= 16'h232A ; +1669 : douta <= 16'h232A ; +1670 : douta <= 16'h232A ; +1671 : douta <= 16'h232A ; +1672 : douta <= 16'h222A ; +1673 : douta <= 16'h222A ; +1674 : douta <= 16'h222A ; +1675 : douta <= 16'h222A ; +1676 : douta <= 16'h222A ; +1677 : douta <= 16'h222A ; +1678 : douta <= 16'h222A ; +1679 : douta <= 16'h222A ; +1680 : douta <= 16'h222A ; +1681 : douta <= 16'h212A ; +1682 : douta <= 16'h222A ; +1683 : douta <= 16'h212A ; +1684 : douta <= 16'h222A ; +1685 : douta <= 16'h222A ; +1686 : douta <= 16'h222A ; +1687 : douta <= 16'h222A ; +1688 : douta <= 16'h222A ; +1689 : douta <= 16'h222A ; +1690 : douta <= 16'h222A ; +1691 : douta <= 16'h222A ; +1692 : douta <= 16'h222A ; +1693 : douta <= 16'h222A ; +1694 : douta <= 16'h222A ; +1695 : douta <= 16'h222A ; +1696 : douta <= 16'h222A ; +1697 : douta <= 16'h222A ; +1698 : douta <= 16'h222A ; +1699 : douta <= 16'h212A ; +1700 : douta <= 16'h212A ; +1701 : douta <= 16'h212A ; +1702 : douta <= 16'h212A ; +1703 : douta <= 16'h212A ; +1704 : douta <= 16'h212A ; +1705 : douta <= 16'h212A ; +1706 : douta <= 16'h212A ; +1707 : douta <= 16'h212A ; +1708 : douta <= 16'h212A ; +1709 : douta <= 16'h212A ; +1710 : douta <= 16'h212A ; +1711 : douta <= 16'h212A ; +1712 : douta <= 16'h212A ; +1713 : douta <= 16'h212A ; +1714 : douta <= 16'h202A ; +1715 : douta <= 16'h202A ; +1716 : douta <= 16'h212A ; +1717 : douta <= 16'h212A ; +1718 : douta <= 16'h212A ; +1719 : douta <= 16'h212A ; +1720 : douta <= 16'h212A ; +1721 : douta <= 16'h212A ; +1722 : douta <= 16'h212A ; +1723 : douta <= 16'h212A ; +1724 : douta <= 16'h212A ; +1725 : douta <= 16'h212A ; +1726 : douta <= 16'h202A ; +1727 : douta <= 16'h212A ; +1728 : douta <= 16'h202A ; +1729 : douta <= 16'h202A ; +1730 : douta <= 16'h202A ; +1731 : douta <= 16'h202A ; +1732 : douta <= 16'h202A ; +1733 : douta <= 16'h202A ; +1734 : douta <= 16'h202A ; +1735 : douta <= 16'h202A ; +1736 : douta <= 16'h202A ; +1737 : douta <= 16'h202A ; +1738 : douta <= 16'h202A ; +1739 : douta <= 16'h202A ; +1740 : douta <= 16'h202A ; +1741 : douta <= 16'h202A ; +1742 : douta <= 16'h202A ; +1743 : douta <= 16'h202A ; +1744 : douta <= 16'h202A ; +1745 : douta <= 16'h202A ; +1746 : douta <= 16'h202A ; +1747 : douta <= 16'h202A ; +1748 : douta <= 16'h202A ; +1749 : douta <= 16'h202A ; +1750 : douta <= 16'h202A ; +1751 : douta <= 16'h1F2C ; +1752 : douta <= 16'h202A ; +1753 : douta <= 16'h202A ; +1754 : douta <= 16'h202A ; +1755 : douta <= 16'h202A ; +1756 : douta <= 16'h202A ; +1757 : douta <= 16'h1D2C ; +1758 : douta <= 16'h202A ; +1759 : douta <= 16'h202A ; +1760 : douta <= 16'h202A ; +1761 : douta <= 16'h202A ; +1762 : douta <= 16'h1E2C ; +1763 : douta <= 16'h202A ; +1764 : douta <= 16'h202A ; +1765 : douta <= 16'h202A ; +1766 : douta <= 16'h202A ; +1767 : douta <= 16'h1E2C ; +1768 : douta <= 16'h202A ; +1769 : douta <= 16'h1E2C ; +1770 : douta <= 16'h1E2C ; +1771 : douta <= 16'h1E2C ; +1772 : douta <= 16'h1E2C ; +1773 : douta <= 16'h1E2C ; +1774 : douta <= 16'h1E2C ; +1775 : douta <= 16'h1E2C ; +1776 : douta <= 16'h1E2C ; +1777 : douta <= 16'h1E2C ; +1778 : douta <= 16'h1E2C ; +1779 : douta <= 16'h1E2C ; +1780 : douta <= 16'h1E2C ; +1781 : douta <= 16'h1E2C ; +1782 : douta <= 16'h1E2C ; +1783 : douta <= 16'h1D2C ; +1784 : douta <= 16'h1D2C ; +1785 : douta <= 16'h1D2C ; +1786 : douta <= 16'h1D2C ; +1787 : douta <= 16'h1D2C ; +1788 : douta <= 16'h1D2C ; +1789 : douta <= 16'h1D2C ; +1790 : douta <= 16'h1D2C ; +1791 : douta <= 16'h1D2C ; +1792 : douta <= 16'h1D2C ; +1793 : douta <= 16'h1D2C ; +1794 : douta <= 16'h1D2C ; +1795 : douta <= 16'h1D2C ; +1796 : douta <= 16'h1D2C ; +1797 : douta <= 16'h1C2C ; +1798 : douta <= 16'h1C2C ; +1799 : douta <= 16'h1C2C ; +1800 : douta <= 16'h1C2C ; +1801 : douta <= 16'h1D2C ; +1802 : douta <= 16'h1D2C ; +1803 : douta <= 16'h1D2C ; +1804 : douta <= 16'h1D2C ; +1805 : douta <= 16'h1D2C ; +1806 : douta <= 16'h1D2C ; +1807 : douta <= 16'h1D2C ; +1808 : douta <= 16'h1D2C ; +1809 : douta <= 16'h1D2C ; +1810 : douta <= 16'h1D2C ; +1811 : douta <= 16'h1C2C ; +1812 : douta <= 16'h1C2C ; +1813 : douta <= 16'h1C2C ; +1814 : douta <= 16'h1C2C ; +1815 : douta <= 16'h1C2C ; +1816 : douta <= 16'h1C2C ; +1817 : douta <= 16'h1B2C ; +1818 : douta <= 16'h1C2C ; +1819 : douta <= 16'h1B2C ; +1820 : douta <= 16'h1B2C ; +1821 : douta <= 16'h1B2C ; +1822 : douta <= 16'h1C2C ; +1823 : douta <= 16'h1C2C ; +1824 : douta <= 16'h1C2C ; +1825 : douta <= 16'h1C2C ; +1826 : douta <= 16'h1C2C ; +1827 : douta <= 16'h1C2C ; +1828 : douta <= 16'h1C2C ; +1829 : douta <= 16'h1C2C ; +1830 : douta <= 16'h1C2C ; +1831 : douta <= 16'h1C2C ; +1832 : douta <= 16'h1C2C ; +1833 : douta <= 16'h1C2C ; +1834 : douta <= 16'h1C2C ; +1835 : douta <= 16'h1C2C ; +1836 : douta <= 16'h1C2C ; +1837 : douta <= 16'h1C2C ; +1838 : douta <= 16'h1C2C ; +1839 : douta <= 16'h1C2C ; +1840 : douta <= 16'h1B2C ; +1841 : douta <= 16'h1B2C ; +1842 : douta <= 16'h1B2C ; +1843 : douta <= 16'h1B2C ; +1844 : douta <= 16'h1B2C ; +1845 : douta <= 16'h1B2C ; +1846 : douta <= 16'h1B2C ; +1847 : douta <= 16'h1B2C ; +1848 : douta <= 16'h1B2C ; +1849 : douta <= 16'h1B2C ; +1850 : douta <= 16'h1A2C ; +1851 : douta <= 16'h1A2C ; +1852 : douta <= 16'h1A2C ; +1853 : douta <= 16'h1A2C ; +1854 : douta <= 16'h1A2C ; +1855 : douta <= 16'h1A2C ; +1856 : douta <= 16'h192C ; +1857 : douta <= 16'h192C ; +1858 : douta <= 16'h192C ; +1859 : douta <= 16'h1A2C ; +1860 : douta <= 16'h1A2C ; +1861 : douta <= 16'h1A2C ; +1862 : douta <= 16'h1A2C ; +1863 : douta <= 16'h1A2C ; +1864 : douta <= 16'h1A2C ; +1865 : douta <= 16'h1A2C ; +1866 : douta <= 16'h1A2C ; +1867 : douta <= 16'h1A2C ; +1868 : douta <= 16'h1A2C ; +1869 : douta <= 16'h1A2C ; +1870 : douta <= 16'h1A2C ; +1871 : douta <= 16'h1A2C ; +1872 : douta <= 16'h1A2C ; +1873 : douta <= 16'h1A2C ; +1874 : douta <= 16'h1A2C ; +1875 : douta <= 16'h1A2C ; +1876 : douta <= 16'h1A2C ; +1877 : douta <= 16'h1A2C ; +1878 : douta <= 16'h192C ; +1879 : douta <= 16'h192C ; +1880 : douta <= 16'h192C ; +1881 : douta <= 16'h192C ; +1882 : douta <= 16'h192C ; +1883 : douta <= 16'h192C ; +1884 : douta <= 16'h192C ; +1885 : douta <= 16'h192C ; +1886 : douta <= 16'h192C ; +1887 : douta <= 16'h192C ; +1888 : douta <= 16'h192C ; +1889 : douta <= 16'h192C ; +1890 : douta <= 16'h192C ; +1891 : douta <= 16'h192C ; +1892 : douta <= 16'h182C ; +1893 : douta <= 16'h192C ; +1894 : douta <= 16'h192C ; +1895 : douta <= 16'h192C ; +1896 : douta <= 16'h192C ; +1897 : douta <= 16'h192C ; +1898 : douta <= 16'h192C ; +1899 : douta <= 16'h192C ; +1900 : douta <= 16'h192C ; +1901 : douta <= 16'h192C ; +1902 : douta <= 16'h192C ; +1903 : douta <= 16'h192C ; +1904 : douta <= 16'h192C ; +1905 : douta <= 16'h192C ; +1906 : douta <= 16'h182C ; +1907 : douta <= 16'h182C ; +1908 : douta <= 16'h182C ; +1909 : douta <= 16'h172C ; +1910 : douta <= 16'h182C ; +1911 : douta <= 16'h172C ; +1912 : douta <= 16'h172C ; +1913 : douta <= 16'h172C ; +1914 : douta <= 16'h182C ; +1915 : douta <= 16'h182C ; +1916 : douta <= 16'h182C ; +1917 : douta <= 16'h182C ; +1918 : douta <= 16'h182C ; +1919 : douta <= 16'h182C ; +1920 : douta <= 16'h182C ; +1921 : douta <= 16'h182C ; +1922 : douta <= 16'h182C ; +1923 : douta <= 16'h182C ; +1924 : douta <= 16'h182C ; +1925 : douta <= 16'h182C ; +1926 : douta <= 16'h182C ; +1927 : douta <= 16'h182C ; +1928 : douta <= 16'h182C ; +1929 : douta <= 16'h182C ; +1930 : douta <= 16'h182C ; +1931 : douta <= 16'h182C ; +1932 : douta <= 16'h182C ; +1933 : douta <= 16'h182C ; +1934 : douta <= 16'h182C ; +1935 : douta <= 16'h172C ; +1936 : douta <= 16'h172C ; +1937 : douta <= 16'h172C ; +1938 : douta <= 16'h172C ; +1939 : douta <= 16'h172C ; +1940 : douta <= 16'h172C ; +1941 : douta <= 16'h172C ; +1942 : douta <= 16'h172C ; +1943 : douta <= 16'h152C ; +1944 : douta <= 16'h152C ; +1945 : douta <= 16'h152C ; +1946 : douta <= 16'h152C ; +1947 : douta <= 16'h152C ; +1948 : douta <= 16'h162C ; +1949 : douta <= 16'h162C ; +1950 : douta <= 16'h162C ; +1951 : douta <= 16'h162C ; +1952 : douta <= 16'h162C ; +1953 : douta <= 16'h162C ; +1954 : douta <= 16'h162C ; +1955 : douta <= 16'h162C ; +1956 : douta <= 16'h162C ; +1957 : douta <= 16'h162C ; +1958 : douta <= 16'h162C ; +1959 : douta <= 16'h162C ; +1960 : douta <= 16'h162C ; +1961 : douta <= 16'h162C ; +1962 : douta <= 16'h162C ; +1963 : douta <= 16'h162C ; +1964 : douta <= 16'h162C ; +1965 : douta <= 16'h162C ; +1966 : douta <= 16'h162C ; +1967 : douta <= 16'h162C ; +1968 : douta <= 16'h162C ; +1969 : douta <= 16'h162C ; +1970 : douta <= 16'h162C ; +1971 : douta <= 16'h162C ; +1972 : douta <= 16'h152C ; +1973 : douta <= 16'h152C ; +1974 : douta <= 16'h152C ; +1975 : douta <= 16'h152C ; +1976 : douta <= 16'h152C ; +1977 : douta <= 16'h152C ; +1978 : douta <= 16'h152C ; +1979 : douta <= 16'h152C ; +1980 : douta <= 16'h152C ; +1981 : douta <= 16'h152C ; +1982 : douta <= 16'h152C ; +1983 : douta <= 16'h152C ; +1984 : douta <= 16'h152C ; +1985 : douta <= 16'h152C ; +1986 : douta <= 16'h152C ; +1987 : douta <= 16'h142C ; +1988 : douta <= 16'h142C ; +1989 : douta <= 16'h152C ; +1990 : douta <= 16'h152C ; +1991 : douta <= 16'h152C ; +1992 : douta <= 16'h152C ; +1993 : douta <= 16'h152C ; +1994 : douta <= 16'h152C ; +1995 : douta <= 16'h152C ; +1996 : douta <= 16'h152C ; +1997 : douta <= 16'h152C ; +1998 : douta <= 16'h152C ; +1999 : douta <= 16'h152C ; +2000 : douta <= 16'h152C ; +2001 : douta <= 16'h152C ; +2002 : douta <= 16'h142C ; +2003 : douta <= 16'h142C ; +2004 : douta <= 16'h142C ; +2005 : douta <= 16'h142C ; +2006 : douta <= 16'h142C ; +2007 : douta <= 16'h142C ; +2008 : douta <= 16'h142C ; +2009 : douta <= 16'h142C ; +2010 : douta <= 16'h142C ; +2011 : douta <= 16'h142C ; +2012 : douta <= 16'h142C ; +2013 : douta <= 16'h142C ; +2014 : douta <= 16'h142C ; +2015 : douta <= 16'h142C ; +2016 : douta <= 16'h142C ; +2017 : douta <= 16'h142C ; +2018 : douta <= 16'h142C ; +2019 : douta <= 16'h122C ; +2020 : douta <= 16'h132C ; +2021 : douta <= 16'h142C ; +2022 : douta <= 16'h142C ; +2023 : douta <= 16'h142C ; +2024 : douta <= 16'h142C ; +2025 : douta <= 16'h142C ; +2026 : douta <= 16'h142C ; +2027 : douta <= 16'h132C ; +2028 : douta <= 16'h132C ; +2029 : douta <= 16'h132C ; +2030 : douta <= 16'h132C ; +2031 : douta <= 16'h132C ; +2032 : douta <= 16'h132C ; +2033 : douta <= 16'h132C ; +2034 : douta <= 16'h132C ; +2035 : douta <= 16'h132C ; +2036 : douta <= 16'h132C ; +2037 : douta <= 16'h122C ; +2038 : douta <= 16'h132C ; +2039 : douta <= 16'h122C ; +2040 : douta <= 16'h122C ; +2041 : douta <= 16'h122C ; +2042 : douta <= 16'h122C ; +2043 : douta <= 16'h112C ; +2044 : douta <= 16'h122C ; +2045 : douta <= 16'h112C ; +2046 : douta <= 16'h122C ; +2047 : douta <= 16'h122C ; +2048 : douta <= 16'h122C ; +2049 : douta <= 16'h122C ; +2050 : douta <= 16'h122C ; +2051 : douta <= 16'h122C ; +2052 : douta <= 16'h122C ; +2053 : douta <= 16'h122C ; +2054 : douta <= 16'h122C ; +2055 : douta <= 16'h122C ; +2056 : douta <= 16'h122C ; +2057 : douta <= 16'h122C ; +2058 : douta <= 16'h122C ; +2059 : douta <= 16'h122C ; +2060 : douta <= 16'h122C ; +2061 : douta <= 16'h122C ; +2062 : douta <= 16'h122C ; +2063 : douta <= 16'h122C ; +2064 : douta <= 16'h122C ; +2065 : douta <= 16'h122C ; +2066 : douta <= 16'h112C ; +2067 : douta <= 16'h112C ; +2068 : douta <= 16'h112C ; +2069 : douta <= 16'h112C ; +2070 : douta <= 16'h112C ; +2071 : douta <= 16'h112C ; +2072 : douta <= 16'h112C ; +2073 : douta <= 16'h112C ; +2074 : douta <= 16'h112C ; +2075 : douta <= 16'h112C ; +2076 : douta <= 16'h112C ; +2077 : douta <= 16'h112C ; +2078 : douta <= 16'h112C ; +2079 : douta <= 16'h112C ; +2080 : douta <= 16'h112C ; +2081 : douta <= 16'h102C ; +2082 : douta <= 16'h102C ; +2083 : douta <= 16'h102C ; +2084 : douta <= 16'h102C ; +2085 : douta <= 16'h112C ; +2086 : douta <= 16'h112C ; +2087 : douta <= 16'h112C ; +2088 : douta <= 16'h112C ; +2089 : douta <= 16'h112C ; +2090 : douta <= 16'h112C ; +2091 : douta <= 16'h0F2C ; +2092 : douta <= 16'h112C ; +2093 : douta <= 16'h112C ; +2094 : douta <= 16'h112C ; +2095 : douta <= 16'h102C ; +2096 : douta <= 16'h102C ; +2097 : douta <= 16'h102C ; +2098 : douta <= 16'h102C ; +2099 : douta <= 16'h102C ; +2100 : douta <= 16'h102C ; +2101 : douta <= 16'h102C ; +2102 : douta <= 16'h102C ; +2103 : douta <= 16'h102C ; +2104 : douta <= 16'h102C ; +2105 : douta <= 16'h102C ; +2106 : douta <= 16'h102C ; +2107 : douta <= 16'h102C ; +2108 : douta <= 16'h0E2C ; +2109 : douta <= 16'h102C ; +2110 : douta <= 16'h102C ; +2111 : douta <= 16'h102C ; +2112 : douta <= 16'h102C ; +2113 : douta <= 16'h102C ; +2114 : douta <= 16'h102C ; +2115 : douta <= 16'h102C ; +2116 : douta <= 16'h102C ; +2117 : douta <= 16'h102C ; +2118 : douta <= 16'h102C ; +2119 : douta <= 16'h102C ; +2120 : douta <= 16'h102C ; +2121 : douta <= 16'h102C ; +2122 : douta <= 16'h102C ; +2123 : douta <= 16'h102C ; +2124 : douta <= 16'h0F2C ; +2125 : douta <= 16'h0F2C ; +2126 : douta <= 16'h0F2C ; +2127 : douta <= 16'h0E2C ; +2128 : douta <= 16'h0F2C ; +2129 : douta <= 16'h0F2C ; +2130 : douta <= 16'h0F2C ; +2131 : douta <= 16'h0E2C ; +2132 : douta <= 16'h0E2C ; +2133 : douta <= 16'h0D2C ; +2134 : douta <= 16'h0D2C ; +2135 : douta <= 16'h0D2C ; +2136 : douta <= 16'h0E2C ; +2137 : douta <= 16'h0E2C ; +2138 : douta <= 16'h0E2C ; +2139 : douta <= 16'h0E2C ; +2140 : douta <= 16'h0E2C ; +2141 : douta <= 16'h0E2C ; +2142 : douta <= 16'h0E2C ; +2143 : douta <= 16'h0E2C ; +2144 : douta <= 16'h0E2C ; +2145 : douta <= 16'h0E2C ; +2146 : douta <= 16'h0E2C ; +2147 : douta <= 16'h0E2C ; +2148 : douta <= 16'h0E2C ; +2149 : douta <= 16'h0E2C ; +2150 : douta <= 16'h0E2C ; +2151 : douta <= 16'h0E2C ; +2152 : douta <= 16'h0E2C ; +2153 : douta <= 16'h0E2C ; +2154 : douta <= 16'h0E2C ; +2155 : douta <= 16'h0E2C ; +2156 : douta <= 16'h0E2C ; +2157 : douta <= 16'h0E2C ; +2158 : douta <= 16'h0D2C ; +2159 : douta <= 16'h0D2C ; +2160 : douta <= 16'h0D2C ; +2161 : douta <= 16'h0D2C ; +2162 : douta <= 16'h0D2C ; +2163 : douta <= 16'h0D2C ; +2164 : douta <= 16'h0D2C ; +2165 : douta <= 16'h0D2C ; +2166 : douta <= 16'h0D2C ; +2167 : douta <= 16'h0D2C ; +2168 : douta <= 16'h0D2C ; +2169 : douta <= 16'h0D2C ; +2170 : douta <= 16'h0D2C ; +2171 : douta <= 16'h0D2C ; +2172 : douta <= 16'h0C2C ; +2173 : douta <= 16'h0C2C ; +2174 : douta <= 16'h0C2C ; +2175 : douta <= 16'h0D2C ; +2176 : douta <= 16'h0C2C ; +2177 : douta <= 16'h0D2C ; +2178 : douta <= 16'h0D2C ; +2179 : douta <= 16'h0D2C ; +2180 : douta <= 16'h0D2C ; +2181 : douta <= 16'h0D2C ; +2182 : douta <= 16'h0D2C ; +2183 : douta <= 16'h0D2C ; +2184 : douta <= 16'h0D2C ; +2185 : douta <= 16'h0D2C ; +2186 : douta <= 16'h0D2C ; +2187 : douta <= 16'h0D2C ; +2188 : douta <= 16'h0D2C ; +2189 : douta <= 16'h0C2C ; +2190 : douta <= 16'h0C2C ; +2191 : douta <= 16'h0C2C ; +2192 : douta <= 16'h0C2C ; +2193 : douta <= 16'h0C2C ; +2194 : douta <= 16'h0C2C ; +2195 : douta <= 16'h0C2C ; +2196 : douta <= 16'h0B2C ; +2197 : douta <= 16'h0B2C ; +2198 : douta <= 16'h0B2C ; +2199 : douta <= 16'h0C2C ; +2200 : douta <= 16'h0C2C ; +2201 : douta <= 16'h0C2C ; +2202 : douta <= 16'h0C2C ; +2203 : douta <= 16'h0C2C ; +2204 : douta <= 16'h0C2C ; +2205 : douta <= 16'h0C2C ; +2206 : douta <= 16'h0C2C ; +2207 : douta <= 16'h0C2C ; +2208 : douta <= 16'h0C2C ; +2209 : douta <= 16'h0C2C ; +2210 : douta <= 16'h0C2C ; +2211 : douta <= 16'h0C2C ; +2212 : douta <= 16'h0C2C ; +2213 : douta <= 16'h0C2C ; +2214 : douta <= 16'h0C2C ; +2215 : douta <= 16'h0C2C ; +2216 : douta <= 16'h0C2C ; +2217 : douta <= 16'h0C2C ; +2218 : douta <= 16'h0C2C ; +2219 : douta <= 16'h0C2C ; +2220 : douta <= 16'h0B2C ; +2221 : douta <= 16'h0B2C ; +2222 : douta <= 16'h0B2C ; +2223 : douta <= 16'h0B2C ; +2224 : douta <= 16'h0B2C ; +2225 : douta <= 16'h0B2C ; +2226 : douta <= 16'h0A2C ; +2227 : douta <= 16'h0A2C ; +2228 : douta <= 16'h0A2C ; +2229 : douta <= 16'h0A2C ; +2230 : douta <= 16'h0A2C ; +2231 : douta <= 16'h0A2C ; +2232 : douta <= 16'h0A2C ; +2233 : douta <= 16'h0A2C ; +2234 : douta <= 16'h92C ; +2235 : douta <= 16'h0A2C ; +2236 : douta <= 16'h0A2C ; +2237 : douta <= 16'h92C ; +2238 : douta <= 16'h0A2C ; +2239 : douta <= 16'h0A2C ; +2240 : douta <= 16'h0A2C ; +2241 : douta <= 16'h0A2C ; +2242 : douta <= 16'h0A2C ; +2243 : douta <= 16'h0A2C ; +2244 : douta <= 16'h0A2C ; +2245 : douta <= 16'h0A2C ; +2246 : douta <= 16'h0A2C ; +2247 : douta <= 16'h0A2C ; +2248 : douta <= 16'h0A2C ; +2249 : douta <= 16'h0A2C ; +2250 : douta <= 16'h0A2C ; +2251 : douta <= 16'h0A2C ; +2252 : douta <= 16'h0A2C ; +2253 : douta <= 16'h92C ; +2254 : douta <= 16'h0A2C ; +2255 : douta <= 16'h92C ; +2256 : douta <= 16'h92C ; +2257 : douta <= 16'h92C ; +2258 : douta <= 16'h92C ; +2259 : douta <= 16'h92C ; +2260 : douta <= 16'h92C ; +2261 : douta <= 16'h92C ; +2262 : douta <= 16'h92C ; +2263 : douta <= 16'h92C ; +2264 : douta <= 16'h92C ; +2265 : douta <= 16'h92C ; +2266 : douta <= 16'h92C ; +2267 : douta <= 16'h92C ; +2268 : douta <= 16'h92C ; +2269 : douta <= 16'h92C ; +2270 : douta <= 16'h82C ; +2271 : douta <= 16'h82C ; +2272 : douta <= 16'h92C ; +2273 : douta <= 16'h92C ; +2274 : douta <= 16'h82C ; +2275 : douta <= 16'h92C ; +2276 : douta <= 16'h92C ; +2277 : douta <= 16'h92C ; +2278 : douta <= 16'h92C ; +2279 : douta <= 16'h92C ; +2280 : douta <= 16'h92C ; +2281 : douta <= 16'h92C ; +2282 : douta <= 16'h92C ; +2283 : douta <= 16'h92C ; +2284 : douta <= 16'h92C ; +2285 : douta <= 16'h92C ; +2286 : douta <= 16'h92C ; +2287 : douta <= 16'h82C ; +2288 : douta <= 16'h82C ; +2289 : douta <= 16'h82C ; +2290 : douta <= 16'h82C ; +2291 : douta <= 16'h82C ; +2292 : douta <= 16'h82C ; +2293 : douta <= 16'h82C ; +2294 : douta <= 16'h82C ; +2295 : douta <= 16'h82C ; +2296 : douta <= 16'h82C ; +2297 : douta <= 16'h82C ; +2298 : douta <= 16'h82C ; +2299 : douta <= 16'h82C ; +2300 : douta <= 16'h82C ; +2301 : douta <= 16'h82C ; +2302 : douta <= 16'h82C ; +2303 : douta <= 16'h82C ; +2304 : douta <= 16'h82C ; +2305 : douta <= 16'h82C ; +2306 : douta <= 16'h82C ; +2307 : douta <= 16'h82C ; +2308 : douta <= 16'h82C ; +2309 : douta <= 16'h82C ; +2310 : douta <= 16'h82C ; +2311 : douta <= 16'h82C ; +2312 : douta <= 16'h72C ; +2313 : douta <= 16'h72C ; +2314 : douta <= 16'h82C ; +2315 : douta <= 16'h82C ; +2316 : douta <= 16'h72C ; +2317 : douta <= 16'h72C ; +2318 : douta <= 16'h72C ; +2319 : douta <= 16'h72C ; +2320 : douta <= 16'h72C ; +2321 : douta <= 16'h72C ; +2322 : douta <= 16'h72C ; +2323 : douta <= 16'h72C ; +2324 : douta <= 16'h62C ; +2325 : douta <= 16'h62C ; +2326 : douta <= 16'h62C ; +2327 : douta <= 16'h52C ; +2328 : douta <= 16'h52C ; +2329 : douta <= 16'h52C ; +2330 : douta <= 16'h52C ; +2331 : douta <= 16'h62C ; +2332 : douta <= 16'h62C ; +2333 : douta <= 16'h62C ; +2334 : douta <= 16'h62C ; +2335 : douta <= 16'h62C ; +2336 : douta <= 16'h62C ; +2337 : douta <= 16'h62C ; +2338 : douta <= 16'h62C ; +2339 : douta <= 16'h62C ; +2340 : douta <= 16'h62C ; +2341 : douta <= 16'h62C ; +2342 : douta <= 16'h62C ; +2343 : douta <= 16'h62C ; +2344 : douta <= 16'h62C ; +2345 : douta <= 16'h62C ; +2346 : douta <= 16'h62C ; +2347 : douta <= 16'h62C ; +2348 : douta <= 16'h62C ; +2349 : douta <= 16'h62C ; +2350 : douta <= 16'h62C ; +2351 : douta <= 16'h62C ; +2352 : douta <= 16'h52C ; +2353 : douta <= 16'h52C ; +2354 : douta <= 16'h52C ; +2355 : douta <= 16'h52C ; +2356 : douta <= 16'h52C ; +2357 : douta <= 16'h52C ; +2358 : douta <= 16'h52C ; +2359 : douta <= 16'h52C ; +2360 : douta <= 16'h52C ; +2361 : douta <= 16'h52C ; +2362 : douta <= 16'h52C ; +2363 : douta <= 16'h52C ; +2364 : douta <= 16'h52C ; +2365 : douta <= 16'h52C ; +2366 : douta <= 16'h42C ; +2367 : douta <= 16'h42C ; +2368 : douta <= 16'h42C ; +2369 : douta <= 16'h42C ; +2370 : douta <= 16'h52C ; +2371 : douta <= 16'h52C ; +2372 : douta <= 16'h52C ; +2373 : douta <= 16'h52C ; +2374 : douta <= 16'h52C ; +2375 : douta <= 16'h52C ; +2376 : douta <= 16'h52C ; +2377 : douta <= 16'h52C ; +2378 : douta <= 16'h52C ; +2379 : douta <= 16'h52C ; +2380 : douta <= 16'h52C ; +2381 : douta <= 16'h52C ; +2382 : douta <= 16'h52C ; +2383 : douta <= 16'h42C ; +2384 : douta <= 16'h42C ; +2385 : douta <= 16'h42C ; +2386 : douta <= 16'h42C ; +2387 : douta <= 16'h42C ; +2388 : douta <= 16'h42C ; +2389 : douta <= 16'h42C ; +2390 : douta <= 16'h42C ; +2391 : douta <= 16'h42C ; +2392 : douta <= 16'h42C ; +2393 : douta <= 16'h42C ; +2394 : douta <= 16'h42C ; +2395 : douta <= 16'h42C ; +2396 : douta <= 16'h42C ; +2397 : douta <= 16'h42C ; +2398 : douta <= 16'h42C ; +2399 : douta <= 16'h42C ; +2400 : douta <= 16'h42C ; +2401 : douta <= 16'h22C ; +2402 : douta <= 16'h42C ; +2403 : douta <= 16'h42C ; +2404 : douta <= 16'h42C ; +2405 : douta <= 16'h42C ; +2406 : douta <= 16'h42C ; +2407 : douta <= 16'h42C ; +2408 : douta <= 16'h42C ; +2409 : douta <= 16'h42C ; +2410 : douta <= 16'h42C ; +2411 : douta <= 16'h42C ; +2412 : douta <= 16'h42C ; +2413 : douta <= 16'h32C ; +2414 : douta <= 16'h32C ; +2415 : douta <= 16'h32C ; +2416 : douta <= 16'h32C ; +2417 : douta <= 16'h32C ; +2418 : douta <= 16'h32C ; +2419 : douta <= 16'h32C ; +2420 : douta <= 16'h32C ; +2421 : douta <= 16'h32C ; +2422 : douta <= 16'h32C ; +2423 : douta <= 16'h22C ; +2424 : douta <= 16'h22C ; +2425 : douta <= 16'h22C ; +2426 : douta <= 16'h22C ; +2427 : douta <= 16'h22C ; +2428 : douta <= 16'h12C ; +2429 : douta <= 16'h22C ; +2430 : douta <= 16'h22C ; +2431 : douta <= 16'h22C ; +2432 : douta <= 16'h22C ; +2433 : douta <= 16'h22C ; +2434 : douta <= 16'h22C ; +2435 : douta <= 16'h22C ; +2436 : douta <= 16'h22C ; +2437 : douta <= 16'h22C ; +2438 : douta <= 16'h22C ; +2439 : douta <= 16'h22C ; +2440 : douta <= 16'h22C ; +2441 : douta <= 16'h22C ; +2442 : douta <= 16'h22C ; +2443 : douta <= 16'h22C ; +2444 : douta <= 16'h22C ; +2445 : douta <= 16'h22C ; +2446 : douta <= 16'h22C ; +2447 : douta <= 16'h22C ; +2448 : douta <= 16'h12C ; +2449 : douta <= 16'h12C ; +2450 : douta <= 16'h12C ; +2451 : douta <= 16'h12C ; +2452 : douta <= 16'h12C ; +2453 : douta <= 16'h12C ; +2454 : douta <= 16'h12C ; +2455 : douta <= 16'h12C ; +2456 : douta <= 16'h12C ; +2457 : douta <= 16'h12C ; +2458 : douta <= 16'h12C ; +2459 : douta <= 16'h12C ; +2460 : douta <= 16'h12C ; +2461 : douta <= 16'h12C ; +2462 : douta <= 16'h12C ; +2463 : douta <= 16'h02C ; +2464 : douta <= 16'h02C ; +2465 : douta <= 16'h12C ; +2466 : douta <= 16'h02C ; +2467 : douta <= 16'h12C ; +2468 : douta <= 16'h12C ; +2469 : douta <= 16'h12C ; +2470 : douta <= 16'h12C ; +2471 : douta <= 16'h12C ; +2472 : douta <= 16'h12C ; +2473 : douta <= 16'h12C ; +2474 : douta <= 16'h12C ; +2475 : douta <= 16'h12C ; +2476 : douta <= 16'h12C ; +2477 : douta <= 16'h12C ; +2478 : douta <= 16'h12C ; +2479 : douta <= 16'h02C ; +2480 : douta <= 16'h12C ; +2481 : douta <= 16'h02C ; +2482 : douta <= 16'h02C ; +2483 : douta <= 16'h02C ; +2484 : douta <= 16'hD040 ; +2485 : douta <= 16'h02C ; +2486 : douta <= 16'h02C ; +2487 : douta <= 16'h02C ; +2488 : douta <= 16'h02C ; +2489 : douta <= 16'h02C ; +2490 : douta <= 16'h02C ; +2491 : douta <= 16'h02C ; +2492 : douta <= 16'h02C ; +2493 : douta <= 16'hD040 ; +2494 : douta <= 16'h02C ; +2495 : douta <= 16'h02C ; +2496 : douta <= 16'h02C ; +2497 : douta <= 16'h02C ; +2498 : douta <= 16'h02C ; +2499 : douta <= 16'h02C ; +2500 : douta <= 16'h02C ; +2501 : douta <= 16'h02C ; +2502 : douta <= 16'h02C ; +2503 : douta <= 16'h02C ; +2504 : douta <= 16'h02C ; +2505 : douta <= 16'h02C ; +2506 : douta <= 16'h02C ; +2507 : douta <= 16'hCE40 ; +2508 : douta <= 16'h02C ; +2509 : douta <= 16'h02C ; +2510 : douta <= 16'hCE40 ; +2511 : douta <= 16'hCD40 ; +2512 : douta <= 16'hCD40 ; +2513 : douta <= 16'hCD40 ; +2514 : douta <= 16'hCD40 ; +2515 : douta <= 16'hCD40 ; +2516 : douta <= 16'hCD40 ; +2517 : douta <= 16'hCD40 ; +2518 : douta <= 16'hCD40 ; +2519 : douta <= 16'hCD40 ; +2520 : douta <= 16'hCD40 ; +2521 : douta <= 16'hCD40 ; +2522 : douta <= 16'hCC40 ; +2523 : douta <= 16'hCC40 ; +2524 : douta <= 16'hCC40 ; +2525 : douta <= 16'hCD40 ; +2526 : douta <= 16'hCD40 ; +2527 : douta <= 16'hCD40 ; +2528 : douta <= 16'hCD40 ; +2529 : douta <= 16'hCD40 ; +2530 : douta <= 16'hCC40 ; +2531 : douta <= 16'hCB40 ; +2532 : douta <= 16'hCB40 ; +2533 : douta <= 16'hCB40 ; +2534 : douta <= 16'hCB40 ; +2535 : douta <= 16'hCC40 ; +2536 : douta <= 16'hCC40 ; +2537 : douta <= 16'hCC40 ; +2538 : douta <= 16'hCC40 ; +2539 : douta <= 16'hCC40 ; +2540 : douta <= 16'hCC40 ; +2541 : douta <= 16'hCC40 ; +2542 : douta <= 16'hCC40 ; +2543 : douta <= 16'hCC40 ; +2544 : douta <= 16'hCC40 ; +2545 : douta <= 16'hCC40 ; +2546 : douta <= 16'hCC40 ; +2547 : douta <= 16'hCC40 ; +2548 : douta <= 16'hCC40 ; +2549 : douta <= 16'hCC40 ; +2550 : douta <= 16'hCB40 ; +2551 : douta <= 16'hCB40 ; +2552 : douta <= 16'hCB40 ; +2553 : douta <= 16'hCB40 ; +2554 : douta <= 16'hCB40 ; +2555 : douta <= 16'hCB40 ; +2556 : douta <= 16'hCA40 ; +2557 : douta <= 16'hCA40 ; +2558 : douta <= 16'hCA40 ; +2559 : douta <= 16'hCA40 ; +2560 : douta <= 16'hCA40 ; +2561 : douta <= 16'hCA40 ; +2562 : douta <= 16'hCA40 ; +2563 : douta <= 16'hCA40 ; +2564 : douta <= 16'hCA40 ; +2565 : douta <= 16'hCA40 ; +2566 : douta <= 16'hCA40 ; +2567 : douta <= 16'hC940 ; +2568 : douta <= 16'hCA40 ; +2569 : douta <= 16'hCA40 ; +2570 : douta <= 16'hCA40 ; +2571 : douta <= 16'hCA40 ; +2572 : douta <= 16'hCA40 ; +2573 : douta <= 16'hC940 ; +2574 : douta <= 16'hCA40 ; +2575 : douta <= 16'hC940 ; +2576 : douta <= 16'hC940 ; +2577 : douta <= 16'hC940 ; +2578 : douta <= 16'hC940 ; +2579 : douta <= 16'hC940 ; +2580 : douta <= 16'hC940 ; +2581 : douta <= 16'hC940 ; +2582 : douta <= 16'hC940 ; +2583 : douta <= 16'hC940 ; +2584 : douta <= 16'hC940 ; +2585 : douta <= 16'hC940 ; +2586 : douta <= 16'hC940 ; +2587 : douta <= 16'hC940 ; +2588 : douta <= 16'hC940 ; +2589 : douta <= 16'hC840 ; +2590 : douta <= 16'hC940 ; +2591 : douta <= 16'hC940 ; +2592 : douta <= 16'hC840 ; +2593 : douta <= 16'hC840 ; +2594 : douta <= 16'hC940 ; +2595 : douta <= 16'hC940 ; +2596 : douta <= 16'hC940 ; +2597 : douta <= 16'hC940 ; +2598 : douta <= 16'hC840 ; +2599 : douta <= 16'hC840 ; +2600 : douta <= 16'hC840 ; +2601 : douta <= 16'hC840 ; +2602 : douta <= 16'hC840 ; +2603 : douta <= 16'hC840 ; +2604 : douta <= 16'hC840 ; +2605 : douta <= 16'hC840 ; +2606 : douta <= 16'hC840 ; +2607 : douta <= 16'hC840 ; +2608 : douta <= 16'hC740 ; +2609 : douta <= 16'hC740 ; +2610 : douta <= 16'hC740 ; +2611 : douta <= 16'hC840 ; +2612 : douta <= 16'hC840 ; +2613 : douta <= 16'hC840 ; +2614 : douta <= 16'hC840 ; +2615 : douta <= 16'hC840 ; +2616 : douta <= 16'hC840 ; +2617 : douta <= 16'hC640 ; +2618 : douta <= 16'hC640 ; +2619 : douta <= 16'hC640 ; +2620 : douta <= 16'hC640 ; +2621 : douta <= 16'hC640 ; +2622 : douta <= 16'hC640 ; +2623 : douta <= 16'hC640 ; +2624 : douta <= 16'hC640 ; +2625 : douta <= 16'hC640 ; +2626 : douta <= 16'hC640 ; +2627 : douta <= 16'hC640 ; +2628 : douta <= 16'hC540 ; +2629 : douta <= 16'hC540 ; +2630 : douta <= 16'hC640 ; +2631 : douta <= 16'hC640 ; +2632 : douta <= 16'hC640 ; +2633 : douta <= 16'hC640 ; +2634 : douta <= 16'hC640 ; +2635 : douta <= 16'hC540 ; +2636 : douta <= 16'hC640 ; +2637 : douta <= 16'hC640 ; +2638 : douta <= 16'hC540 ; +2639 : douta <= 16'hC540 ; +2640 : douta <= 16'hC540 ; +2641 : douta <= 16'hC540 ; +2642 : douta <= 16'hC540 ; +2643 : douta <= 16'hC540 ; +2644 : douta <= 16'hC540 ; +2645 : douta <= 16'hC540 ; +2646 : douta <= 16'hC540 ; +2647 : douta <= 16'hC540 ; +2648 : douta <= 16'hC540 ; +2649 : douta <= 16'hC540 ; +2650 : douta <= 16'hC540 ; +2651 : douta <= 16'hC540 ; +2652 : douta <= 16'hC440 ; +2653 : douta <= 16'hC440 ; +2654 : douta <= 16'hC440 ; +2655 : douta <= 16'hC540 ; +2656 : douta <= 16'hC540 ; +2657 : douta <= 16'hC540 ; +2658 : douta <= 16'hC540 ; +2659 : douta <= 16'hC540 ; +2660 : douta <= 16'hC540 ; +2661 : douta <= 16'hC440 ; +2662 : douta <= 16'hC440 ; +2663 : douta <= 16'hC440 ; +2664 : douta <= 16'hC440 ; +2665 : douta <= 16'hC440 ; +2666 : douta <= 16'hC440 ; +2667 : douta <= 16'hC440 ; +2668 : douta <= 16'hC340 ; +2669 : douta <= 16'hC340 ; +2670 : douta <= 16'hC340 ; +2671 : douta <= 16'hC440 ; +2672 : douta <= 16'hC440 ; +2673 : douta <= 16'hC440 ; +2674 : douta <= 16'hC440 ; +2675 : douta <= 16'hC440 ; +2676 : douta <= 16'hC440 ; +2677 : douta <= 16'hC440 ; +2678 : douta <= 16'hC440 ; +2679 : douta <= 16'hC440 ; +2680 : douta <= 16'hC340 ; +2681 : douta <= 16'hC340 ; +2682 : douta <= 16'hC340 ; +2683 : douta <= 16'hC340 ; +2684 : douta <= 16'hC340 ; +2685 : douta <= 16'hC340 ; +2686 : douta <= 16'hC340 ; +2687 : douta <= 16'hC340 ; +2688 : douta <= 16'hC240 ; +2689 : douta <= 16'hC240 ; +2690 : douta <= 16'hC240 ; +2691 : douta <= 16'hC240 ; +2692 : douta <= 16'hC240 ; +2693 : douta <= 16'hC240 ; +2694 : douta <= 16'hC240 ; +2695 : douta <= 16'hC240 ; +2696 : douta <= 16'hC140 ; +2697 : douta <= 16'hC240 ; +2698 : douta <= 16'hC240 ; +2699 : douta <= 16'hC240 ; +2700 : douta <= 16'hC240 ; +2701 : douta <= 16'hC240 ; +2702 : douta <= 16'hC240 ; +2703 : douta <= 16'hC240 ; +2704 : douta <= 16'hC240 ; +2705 : douta <= 16'hC140 ; +2706 : douta <= 16'hC240 ; +2707 : douta <= 16'hC140 ; +2708 : douta <= 16'hC140 ; +2709 : douta <= 16'hC140 ; +2710 : douta <= 16'hC140 ; +2711 : douta <= 16'hC140 ; +2712 : douta <= 16'hC140 ; +2713 : douta <= 16'hC140 ; +2714 : douta <= 16'hC140 ; +2715 : douta <= 16'hC140 ; +2716 : douta <= 16'hC140 ; +2717 : douta <= 16'hC140 ; +2718 : douta <= 16'hC140 ; +2719 : douta <= 16'hC140 ; +2720 : douta <= 16'hC140 ; +2721 : douta <= 16'hC140 ; +2722 : douta <= 16'hC140 ; +2723 : douta <= 16'hC040 ; +2724 : douta <= 16'hC040 ; +2725 : douta <= 16'hC040 ; +2726 : douta <= 16'hC140 ; +2727 : douta <= 16'hC140 ; +2728 : douta <= 16'hC140 ; +2729 : douta <= 16'hC140 ; +2730 : douta <= 16'hC040 ; +2731 : douta <= 16'hC040 ; +2732 : douta <= 16'hC040 ; +2733 : douta <= 16'hC040 ; +2734 : douta <= 16'hC040 ; +2735 : douta <= 16'hC040 ; +2736 : douta <= 16'hC040 ; +2737 : douta <= 16'hC040 ; +2738 : douta <= 16'hC040 ; +2739 : douta <= 16'hC040 ; +2740 : douta <= 16'hC040 ; +2741 : douta <= 16'hC040 ; +2742 : douta <= 16'hC040 ; +2743 : douta <= 16'hC040 ; +2744 : douta <= 16'hBF40 ; +2745 : douta <= 16'hC040 ; +2746 : douta <= 16'hC040 ; +2747 : douta <= 16'hC040 ; +2748 : douta <= 16'hC040 ; +2749 : douta <= 16'hC040 ; +2750 : douta <= 16'hC040 ; +2751 : douta <= 16'hC040 ; +2752 : douta <= 16'hC040 ; +2753 : douta <= 16'hC040 ; +2754 : douta <= 16'hBE40 ; +2755 : douta <= 16'hBE40 ; +2756 : douta <= 16'hBE40 ; +2757 : douta <= 16'hBE40 ; +2758 : douta <= 16'hBE40 ; +2759 : douta <= 16'hBE40 ; +2760 : douta <= 16'hBE40 ; +2761 : douta <= 16'hBE40 ; +2762 : douta <= 16'hBE40 ; +2763 : douta <= 16'hBE40 ; +2764 : douta <= 16'hBE40 ; +2765 : douta <= 16'hBE40 ; +2766 : douta <= 16'hBE40 ; +2767 : douta <= 16'hBE40 ; +2768 : douta <= 16'hBD40 ; +2769 : douta <= 16'hBD40 ; +2770 : douta <= 16'hBE40 ; +2771 : douta <= 16'hBE40 ; +2772 : douta <= 16'hBE40 ; +2773 : douta <= 16'hBE40 ; +2774 : douta <= 16'hBE40 ; +2775 : douta <= 16'hBE40 ; +2776 : douta <= 16'hBE40 ; +2777 : douta <= 16'hBE40 ; +2778 : douta <= 16'hBD40 ; +2779 : douta <= 16'hBD40 ; +2780 : douta <= 16'hBD40 ; +2781 : douta <= 16'hBD40 ; +2782 : douta <= 16'hBD40 ; +2783 : douta <= 16'hBD40 ; +2784 : douta <= 16'hBD40 ; +2785 : douta <= 16'hBD40 ; +2786 : douta <= 16'hBD40 ; +2787 : douta <= 16'hBD40 ; +2788 : douta <= 16'hBD40 ; +2789 : douta <= 16'hBD40 ; +2790 : douta <= 16'hBD40 ; +2791 : douta <= 16'hBD40 ; +2792 : douta <= 16'hBC40 ; +2793 : douta <= 16'hBC40 ; +2794 : douta <= 16'hBC40 ; +2795 : douta <= 16'hBD40 ; +2796 : douta <= 16'hBC40 ; +2797 : douta <= 16'hBC40 ; +2798 : douta <= 16'hBC40 ; +2799 : douta <= 16'hBC40 ; +2800 : douta <= 16'hBB40 ; +2801 : douta <= 16'hBC40 ; +2802 : douta <= 16'hBB40 ; +2803 : douta <= 16'hBC40 ; +2804 : douta <= 16'hBC40 ; +2805 : douta <= 16'hBC40 ; +2806 : douta <= 16'hBC40 ; +2807 : douta <= 16'hBC40 ; +2808 : douta <= 16'hBC40 ; +2809 : douta <= 16'hBC40 ; +2810 : douta <= 16'hBC40 ; +2811 : douta <= 16'hBC40 ; +2812 : douta <= 16'hBC40 ; +2813 : douta <= 16'hBC40 ; +2814 : douta <= 16'hBC40 ; +2815 : douta <= 16'hBC40 ; +2816 : douta <= 16'hBC40 ; +2817 : douta <= 16'hBC40 ; +2818 : douta <= 16'hBC40 ; +2819 : douta <= 16'hBC40 ; +2820 : douta <= 16'hBB40 ; +2821 : douta <= 16'hBA40 ; +2822 : douta <= 16'hBA40 ; +2823 : douta <= 16'hBA40 ; +2824 : douta <= 16'hBA40 ; +2825 : douta <= 16'hBA40 ; +2826 : douta <= 16'hBA40 ; +2827 : douta <= 16'hBA40 ; +2828 : douta <= 16'hBA40 ; +2829 : douta <= 16'hBA40 ; +2830 : douta <= 16'hBA40 ; +2831 : douta <= 16'hBA40 ; +2832 : douta <= 16'hBA40 ; +2833 : douta <= 16'hBA40 ; +2834 : douta <= 16'hBA40 ; +2835 : douta <= 16'hB940 ; +2836 : douta <= 16'hB940 ; +2837 : douta <= 16'hBA40 ; +2838 : douta <= 16'hBA40 ; +2839 : douta <= 16'hBA40 ; +2840 : douta <= 16'hBA40 ; +2841 : douta <= 16'hB940 ; +2842 : douta <= 16'hB940 ; +2843 : douta <= 16'hB940 ; +2844 : douta <= 16'hB940 ; +2845 : douta <= 16'hB940 ; +2846 : douta <= 16'hB940 ; +2847 : douta <= 16'hB940 ; +2848 : douta <= 16'hB940 ; +2849 : douta <= 16'hB940 ; +2850 : douta <= 16'hB940 ; +2851 : douta <= 16'hB940 ; +2852 : douta <= 16'hB940 ; +2853 : douta <= 16'hB940 ; +2854 : douta <= 16'hB940 ; +2855 : douta <= 16'hB940 ; +2856 : douta <= 16'hB940 ; +2857 : douta <= 16'hB940 ; +2858 : douta <= 16'hB840 ; +2859 : douta <= 16'hB940 ; +2860 : douta <= 16'hB840 ; +2861 : douta <= 16'hB840 ; +2862 : douta <= 16'hB840 ; +2863 : douta <= 16'hB840 ; +2864 : douta <= 16'hB840 ; +2865 : douta <= 16'hB840 ; +2866 : douta <= 16'hB740 ; +2867 : douta <= 16'hB740 ; +2868 : douta <= 16'hB740 ; +2869 : douta <= 16'hB740 ; +2870 : douta <= 16'hB740 ; +2871 : douta <= 16'hB740 ; +2872 : douta <= 16'hB840 ; +2873 : douta <= 16'hB840 ; +2874 : douta <= 16'hB840 ; +2875 : douta <= 16'hB840 ; +2876 : douta <= 16'hB840 ; +2877 : douta <= 16'hB840 ; +2878 : douta <= 16'hB840 ; +2879 : douta <= 16'hB840 ; +2880 : douta <= 16'hB840 ; +2881 : douta <= 16'hB840 ; +2882 : douta <= 16'hB840 ; +2883 : douta <= 16'hB840 ; +2884 : douta <= 16'hB840 ; +2885 : douta <= 16'hB840 ; +2886 : douta <= 16'hB640 ; +2887 : douta <= 16'hB640 ; +2888 : douta <= 16'hB640 ; +2889 : douta <= 16'hB640 ; +2890 : douta <= 16'hB640 ; +2891 : douta <= 16'hB640 ; +2892 : douta <= 16'hB640 ; +2893 : douta <= 16'hB640 ; +2894 : douta <= 16'hB640 ; +2895 : douta <= 16'hB640 ; +2896 : douta <= 16'hB640 ; +2897 : douta <= 16'hB640 ; +2898 : douta <= 16'hB640 ; +2899 : douta <= 16'hB640 ; +2900 : douta <= 16'hB540 ; +2901 : douta <= 16'hB540 ; +2902 : douta <= 16'hB540 ; +2903 : douta <= 16'hB640 ; +2904 : douta <= 16'hB540 ; +2905 : douta <= 16'hB640 ; +2906 : douta <= 16'hB640 ; +2907 : douta <= 16'hB640 ; +2908 : douta <= 16'hB640 ; +2909 : douta <= 16'hB540 ; +2910 : douta <= 16'hB640 ; +2911 : douta <= 16'hB540 ; +2912 : douta <= 16'hB540 ; +2913 : douta <= 16'hB540 ; +2914 : douta <= 16'hB540 ; +2915 : douta <= 16'hB540 ; +2916 : douta <= 16'hB540 ; +2917 : douta <= 16'hB540 ; +2918 : douta <= 16'hB540 ; +2919 : douta <= 16'hB540 ; +2920 : douta <= 16'hB540 ; +2921 : douta <= 16'hB540 ; +2922 : douta <= 16'hB540 ; +2923 : douta <= 16'hB540 ; +2924 : douta <= 16'hB540 ; +2925 : douta <= 16'hB540 ; +2926 : douta <= 16'hB440 ; +2927 : douta <= 16'hB440 ; +2928 : douta <= 16'hB540 ; +2929 : douta <= 16'hB540 ; +2930 : douta <= 16'hB440 ; +2931 : douta <= 16'hB440 ; +2932 : douta <= 16'hB440 ; +2933 : douta <= 16'hB440 ; +2934 : douta <= 16'hB440 ; +2935 : douta <= 16'hB440 ; +2936 : douta <= 16'hB440 ; +2937 : douta <= 16'hB340 ; +2938 : douta <= 16'hB340 ; +2939 : douta <= 16'hB440 ; +2940 : douta <= 16'hB340 ; +2941 : douta <= 16'hB440 ; +2942 : douta <= 16'hB440 ; +2943 : douta <= 16'hB440 ; +2944 : douta <= 16'hB440 ; +2945 : douta <= 16'hB440 ; +2946 : douta <= 16'hB440 ; +2947 : douta <= 16'hB440 ; +2948 : douta <= 16'hB440 ; +2949 : douta <= 16'hB440 ; +2950 : douta <= 16'hB440 ; +2951 : douta <= 16'hB440 ; +2952 : douta <= 16'hB440 ; +2953 : douta <= 16'hB440 ; +2954 : douta <= 16'hB340 ; +2955 : douta <= 16'hB240 ; +2956 : douta <= 16'hB240 ; +2957 : douta <= 16'hB240 ; +2958 : douta <= 16'hB240 ; +2959 : douta <= 16'hB240 ; +2960 : douta <= 16'hB240 ; +2961 : douta <= 16'hB240 ; +2962 : douta <= 16'hB240 ; +2963 : douta <= 16'hB240 ; +2964 : douta <= 16'hB240 ; +2965 : douta <= 16'hB240 ; +2966 : douta <= 16'hB240 ; +2967 : douta <= 16'hB240 ; +2968 : douta <= 16'hB240 ; +2969 : douta <= 16'hB240 ; +2970 : douta <= 16'hB140 ; +2971 : douta <= 16'hB140 ; +2972 : douta <= 16'hB140 ; +2973 : douta <= 16'hB140 ; +2974 : douta <= 16'hB140 ; +2975 : douta <= 16'hB240 ; +2976 : douta <= 16'hB240 ; +2977 : douta <= 16'hB240 ; +2978 : douta <= 16'hB240 ; +2979 : douta <= 16'hB140 ; +2980 : douta <= 16'hB140 ; +2981 : douta <= 16'hB140 ; +2982 : douta <= 16'hB140 ; +2983 : douta <= 16'hB140 ; +2984 : douta <= 16'hB140 ; +2985 : douta <= 16'hB140 ; +2986 : douta <= 16'hB140 ; +2987 : douta <= 16'hB140 ; +2988 : douta <= 16'hB140 ; +2989 : douta <= 16'hB140 ; +2990 : douta <= 16'hB140 ; +2991 : douta <= 16'hB140 ; +2992 : douta <= 16'hB140 ; +2993 : douta <= 16'hB140 ; +2994 : douta <= 16'hB040 ; +2995 : douta <= 16'hB040 ; +2996 : douta <= 16'hB140 ; +2997 : douta <= 16'hB140 ; +2998 : douta <= 16'hB040 ; +2999 : douta <= 16'hB040 ; +3000 : douta <= 16'hB040 ; +3001 : douta <= 16'hB040 ; +3002 : douta <= 16'hB040 ; +3003 : douta <= 16'hB040 ; +3004 : douta <= 16'hB040 ; +3005 : douta <= 16'hB040 ; +3006 : douta <= 16'hB040 ; +3007 : douta <= 16'hB040 ; +3008 : douta <= 16'hB040 ; +3009 : douta <= 16'hB040 ; +3010 : douta <= 16'hB040 ; +3011 : douta <= 16'hB040 ; +3012 : douta <= 16'hB040 ; +3013 : douta <= 16'hB040 ; +3014 : douta <= 16'hB040 ; +3015 : douta <= 16'hB040 ; +3016 : douta <= 16'hB040 ; +3017 : douta <= 16'hB040 ; +3018 : douta <= 16'hB040 ; +3019 : douta <= 16'hB040 ; +3020 : douta <= 16'hB040 ; +3021 : douta <= 16'hB040 ; +3022 : douta <= 16'hB040 ; +3023 : douta <= 16'hB040 ; +3024 : douta <= 16'hB040 ; +3025 : douta <= 16'hAE40 ; +3026 : douta <= 16'hAE40 ; +3027 : douta <= 16'hAE40 ; +3028 : douta <= 16'hAE40 ; +3029 : douta <= 16'hAE40 ; +3030 : douta <= 16'hAE40 ; +3031 : douta <= 16'hAE40 ; +3032 : douta <= 16'hAE40 ; +3033 : douta <= 16'hAE40 ; +3034 : douta <= 16'hAE40 ; +3035 : douta <= 16'hAE40 ; +3036 : douta <= 16'hAD40 ; +3037 : douta <= 16'hAD40 ; +3038 : douta <= 16'hAD40 ; +3039 : douta <= 16'hAE40 ; +3040 : douta <= 16'hAE40 ; +3041 : douta <= 16'hAE40 ; +3042 : douta <= 16'hAE40 ; +3043 : douta <= 16'hAD40 ; +3044 : douta <= 16'hAE40 ; +3045 : douta <= 16'hAD40 ; +3046 : douta <= 16'hAD40 ; +3047 : douta <= 16'hAD40 ; +3048 : douta <= 16'hAD40 ; +3049 : douta <= 16'hAD40 ; +3050 : douta <= 16'hAD40 ; +3051 : douta <= 16'hAD40 ; +3052 : douta <= 16'hAD40 ; +3053 : douta <= 16'hAD40 ; +3054 : douta <= 16'hAD40 ; +3055 : douta <= 16'hAD40 ; +3056 : douta <= 16'hAD40 ; +3057 : douta <= 16'hAD40 ; +3058 : douta <= 16'hAD40 ; +3059 : douta <= 16'hAD40 ; +3060 : douta <= 16'hAC40 ; +3061 : douta <= 16'hAC40 ; +3062 : douta <= 16'hAC40 ; +3063 : douta <= 16'hAD40 ; +3064 : douta <= 16'hAC40 ; +3065 : douta <= 16'hAC40 ; +3066 : douta <= 16'hAC40 ; +3067 : douta <= 16'hAC40 ; +3068 : douta <= 16'hAC40 ; +3069 : douta <= 16'hAB40 ; +3070 : douta <= 16'hAB40 ; +3071 : douta <= 16'hAB40 ; +3072 : douta <= 16'hAB40 ; +3073 : douta <= 16'hAC40 ; +3074 : douta <= 16'hAB40 ; +3075 : douta <= 16'hAC40 ; +3076 : douta <= 16'hAC40 ; +3077 : douta <= 16'hAC40 ; +3078 : douta <= 16'hAC40 ; +3079 : douta <= 16'hAC40 ; +3080 : douta <= 16'hAC40 ; +3081 : douta <= 16'hAC40 ; +3082 : douta <= 16'hAC40 ; +3083 : douta <= 16'hAC40 ; +3084 : douta <= 16'hAC40 ; +3085 : douta <= 16'hAC40 ; +3086 : douta <= 16'hAC40 ; +3087 : douta <= 16'hAC40 ; +3088 : douta <= 16'hAC40 ; +3089 : douta <= 16'hAC40 ; +3090 : douta <= 16'hAA40 ; +3091 : douta <= 16'hAA40 ; +3092 : douta <= 16'hAA40 ; +3093 : douta <= 16'hAA40 ; +3094 : douta <= 16'hAA40 ; +3095 : douta <= 16'hAA40 ; +3096 : douta <= 16'hAA40 ; +3097 : douta <= 16'hAA40 ; +3098 : douta <= 16'hAA40 ; +3099 : douta <= 16'hAA40 ; +3100 : douta <= 16'hAA40 ; +3101 : douta <= 16'hAA40 ; +3102 : douta <= 16'hAA40 ; +3103 : douta <= 16'hAA40 ; +3104 : douta <= 16'hAA40 ; +3105 : douta <= 16'hAA40 ; +3106 : douta <= 16'hA940 ; +3107 : douta <= 16'hA940 ; +3108 : douta <= 16'hA940 ; +3109 : douta <= 16'hAA40 ; +3110 : douta <= 16'hAA40 ; +3111 : douta <= 16'hAA40 ; +3112 : douta <= 16'hA940 ; +3113 : douta <= 16'hA940 ; +3114 : douta <= 16'hA940 ; +3115 : douta <= 16'hA940 ; +3116 : douta <= 16'hA940 ; +3117 : douta <= 16'hA940 ; +3118 : douta <= 16'hA940 ; +3119 : douta <= 16'hA940 ; +3120 : douta <= 16'hA940 ; +3121 : douta <= 16'hA940 ; +3122 : douta <= 16'hA940 ; +3123 : douta <= 16'hA940 ; +3124 : douta <= 16'hA940 ; +3125 : douta <= 16'hA940 ; +3126 : douta <= 16'hA940 ; +3127 : douta <= 16'hA940 ; +3128 : douta <= 16'hA840 ; +3129 : douta <= 16'hA940 ; +3130 : douta <= 16'hA840 ; +3131 : douta <= 16'hA940 ; +3132 : douta <= 16'hA840 ; +3133 : douta <= 16'hA840 ; +3134 : douta <= 16'hA840 ; +3135 : douta <= 16'hA840 ; +3136 : douta <= 16'hA840 ; +3137 : douta <= 16'hA840 ; +3138 : douta <= 16'hA840 ; +3139 : douta <= 16'hA840 ; +3140 : douta <= 16'hA840 ; +3141 : douta <= 16'hA840 ; +3142 : douta <= 16'hA840 ; +3143 : douta <= 16'hA840 ; +3144 : douta <= 16'hA840 ; +3145 : douta <= 16'hA840 ; +3146 : douta <= 16'hA840 ; +3147 : douta <= 16'hA840 ; +3148 : douta <= 16'hA840 ; +3149 : douta <= 16'hA840 ; +3150 : douta <= 16'hA840 ; +3151 : douta <= 16'hA840 ; +3152 : douta <= 16'hA840 ; +3153 : douta <= 16'hA840 ; +3154 : douta <= 16'hA840 ; +3155 : douta <= 16'hA840 ; +3156 : douta <= 16'hA840 ; +3157 : douta <= 16'hA640 ; +3158 : douta <= 16'hA840 ; +3159 : douta <= 16'hA840 ; +3160 : douta <= 16'hA640 ; +3161 : douta <= 16'hA640 ; +3162 : douta <= 16'hA640 ; +3163 : douta <= 16'hA640 ; +3164 : douta <= 16'hA640 ; +3165 : douta <= 16'hA640 ; +3166 : douta <= 16'hA640 ; +3167 : douta <= 16'hA640 ; +3168 : douta <= 16'hA640 ; +3169 : douta <= 16'hA640 ; +3170 : douta <= 16'hA640 ; +3171 : douta <= 16'hA640 ; +3172 : douta <= 16'hA640 ; +3173 : douta <= 16'hA640 ; +3174 : douta <= 16'hA640 ; +3175 : douta <= 16'hA640 ; +3176 : douta <= 16'hA540 ; +3177 : douta <= 16'hA640 ; +3178 : douta <= 16'hA640 ; +3179 : douta <= 16'hA640 ; +3180 : douta <= 16'hA640 ; +3181 : douta <= 16'hA640 ; +3182 : douta <= 16'hA640 ; +3183 : douta <= 16'hA540 ; +3184 : douta <= 16'hA540 ; +3185 : douta <= 16'hA540 ; +3186 : douta <= 16'hA540 ; +3187 : douta <= 16'hA540 ; +3188 : douta <= 16'hA540 ; +3189 : douta <= 16'hA540 ; +3190 : douta <= 16'hA540 ; +3191 : douta <= 16'hA540 ; +3192 : douta <= 16'hA540 ; +3193 : douta <= 16'hA540 ; +3194 : douta <= 16'hA540 ; +3195 : douta <= 16'hA540 ; +3196 : douta <= 16'hA540 ; +3197 : douta <= 16'hA540 ; +3198 : douta <= 16'hA440 ; +3199 : douta <= 16'hA440 ; +3200 : douta <= 16'hA440 ; +3201 : douta <= 16'hA440 ; +3202 : douta <= 16'hA440 ; +3203 : douta <= 16'hA540 ; +3204 : douta <= 16'hA540 ; +3205 : douta <= 16'hA540 ; +3206 : douta <= 16'hA440 ; +3207 : douta <= 16'hA440 ; +3208 : douta <= 16'hA440 ; +3209 : douta <= 16'hA340 ; +3210 : douta <= 16'hA340 ; +3211 : douta <= 16'hA340 ; +3212 : douta <= 16'hA440 ; +3213 : douta <= 16'hA440 ; +3214 : douta <= 16'hA440 ; +3215 : douta <= 16'hA440 ; +3216 : douta <= 16'hA440 ; +3217 : douta <= 16'hA440 ; +3218 : douta <= 16'hA440 ; +3219 : douta <= 16'hA440 ; +3220 : douta <= 16'hA440 ; +3221 : douta <= 16'hA440 ; +3222 : douta <= 16'hA440 ; +3223 : douta <= 16'hA440 ; +3224 : douta <= 16'hA440 ; +3225 : douta <= 16'hA440 ; +3226 : douta <= 16'hA440 ; +3227 : douta <= 16'hA240 ; +3228 : douta <= 16'hA240 ; +3229 : douta <= 16'hA240 ; +3230 : douta <= 16'hA240 ; +3231 : douta <= 16'hA240 ; +3232 : douta <= 16'hA240 ; +3233 : douta <= 16'hA240 ; +3234 : douta <= 16'hA240 ; +3235 : douta <= 16'hA240 ; +3236 : douta <= 16'hA240 ; +3237 : douta <= 16'hA240 ; +3238 : douta <= 16'hA240 ; +3239 : douta <= 16'hA240 ; +3240 : douta <= 16'hA240 ; +3241 : douta <= 16'hA240 ; +3242 : douta <= 16'hA140 ; +3243 : douta <= 16'hA140 ; +3244 : douta <= 16'hA140 ; +3245 : douta <= 16'hA240 ; +3246 : douta <= 16'hA240 ; +3247 : douta <= 16'hA240 ; +3248 : douta <= 16'hA240 ; +3249 : douta <= 16'hA140 ; +3250 : douta <= 16'hA140 ; +3251 : douta <= 16'hA140 ; +3252 : douta <= 16'hA140 ; +3253 : douta <= 16'hA140 ; +3254 : douta <= 16'hA140 ; +3255 : douta <= 16'hA140 ; +3256 : douta <= 16'hA140 ; +3257 : douta <= 16'hA140 ; +3258 : douta <= 16'hA140 ; +3259 : douta <= 16'hA140 ; +3260 : douta <= 16'hA140 ; +3261 : douta <= 16'hA140 ; +3262 : douta <= 16'hA140 ; +3263 : douta <= 16'hA140 ; +3264 : douta <= 16'hA140 ; +3265 : douta <= 16'hA140 ; +3266 : douta <= 16'hA040 ; +3267 : douta <= 16'hA040 ; +3268 : douta <= 16'hA040 ; +3269 : douta <= 16'hA140 ; +3270 : douta <= 16'hA040 ; +3271 : douta <= 16'hA040 ; +3272 : douta <= 16'hA040 ; +3273 : douta <= 16'hA040 ; +3274 : douta <= 16'hA040 ; +3275 : douta <= 16'hA040 ; +3276 : douta <= 16'hA040 ; +3277 : douta <= 16'hA040 ; +3278 : douta <= 16'hA040 ; +3279 : douta <= 16'hA040 ; +3280 : douta <= 16'hA040 ; +3281 : douta <= 16'hA040 ; +3282 : douta <= 16'hA040 ; +3283 : douta <= 16'hA040 ; +3284 : douta <= 16'hA040 ; +3285 : douta <= 16'hA040 ; +3286 : douta <= 16'hA040 ; +3287 : douta <= 16'hA040 ; +3288 : douta <= 16'hA040 ; +3289 : douta <= 16'hA040 ; +3290 : douta <= 16'hA040 ; +3291 : douta <= 16'hA040 ; +3292 : douta <= 16'h9E42 ; +3293 : douta <= 16'hA040 ; +3294 : douta <= 16'hA040 ; +3295 : douta <= 16'hA040 ; +3296 : douta <= 16'hA040 ; +3297 : douta <= 16'hA040 ; +3298 : douta <= 16'hA040 ; +3299 : douta <= 16'hA040 ; +3300 : douta <= 16'hA040 ; +3301 : douta <= 16'hA040 ; +3302 : douta <= 16'h9F42 ; +3303 : douta <= 16'hA040 ; +3304 : douta <= 16'hA040 ; +3305 : douta <= 16'hA040 ; +3306 : douta <= 16'hA040 ; +3307 : douta <= 16'hA040 ; +3308 : douta <= 16'hA040 ; +3309 : douta <= 16'hA040 ; +3310 : douta <= 16'hA040 ; +3311 : douta <= 16'hA040 ; +3312 : douta <= 16'hA040 ; +3313 : douta <= 16'hA040 ; +3314 : douta <= 16'hA040 ; +3315 : douta <= 16'hA040 ; +3316 : douta <= 16'hA040 ; +3317 : douta <= 16'hA040 ; +3318 : douta <= 16'h9F42 ; +3319 : douta <= 16'hA040 ; +3320 : douta <= 16'hA040 ; +3321 : douta <= 16'hA040 ; +3322 : douta <= 16'hA040 ; +3323 : douta <= 16'hA040 ; +3324 : douta <= 16'h9E42 ; +3325 : douta <= 16'h9E42 ; +3326 : douta <= 16'h9E42 ; +3327 : douta <= 16'h9E42 ; +3328 : douta <= 16'h9E42 ; +3329 : douta <= 16'h9E42 ; +3330 : douta <= 16'h9E42 ; +3331 : douta <= 16'h9E42 ; +3332 : douta <= 16'h9E42 ; +3333 : douta <= 16'h9E42 ; +3334 : douta <= 16'h9E42 ; +3335 : douta <= 16'h9E42 ; +3336 : douta <= 16'h9E42 ; +3337 : douta <= 16'h9E42 ; +3338 : douta <= 16'h9E42 ; +3339 : douta <= 16'h9E42 ; +3340 : douta <= 16'h9E42 ; +3341 : douta <= 16'h9D42 ; +3342 : douta <= 16'h9E42 ; +3343 : douta <= 16'h9E42 ; +3344 : douta <= 16'h9E42 ; +3345 : douta <= 16'h9E42 ; +3346 : douta <= 16'h9E42 ; +3347 : douta <= 16'h9D42 ; +3348 : douta <= 16'h9D42 ; +3349 : douta <= 16'h9D42 ; +3350 : douta <= 16'h9D42 ; +3351 : douta <= 16'h9D42 ; +3352 : douta <= 16'h9D42 ; +3353 : douta <= 16'h9D42 ; +3354 : douta <= 16'h9D42 ; +3355 : douta <= 16'h9D42 ; +3356 : douta <= 16'h9D42 ; +3357 : douta <= 16'h9D42 ; +3358 : douta <= 16'h9D42 ; +3359 : douta <= 16'h9D42 ; +3360 : douta <= 16'h9D42 ; +3361 : douta <= 16'h9D42 ; +3362 : douta <= 16'h9D42 ; +3363 : douta <= 16'h9C42 ; +3364 : douta <= 16'h9C42 ; +3365 : douta <= 16'h9D42 ; +3366 : douta <= 16'h9C42 ; +3367 : douta <= 16'h9C42 ; +3368 : douta <= 16'h9C42 ; +3369 : douta <= 16'h9C42 ; +3370 : douta <= 16'h9C42 ; +3371 : douta <= 16'h9C42 ; +3372 : douta <= 16'h9C42 ; +3373 : douta <= 16'h9C42 ; +3374 : douta <= 16'h9C42 ; +3375 : douta <= 16'h9C42 ; +3376 : douta <= 16'h9C42 ; +3377 : douta <= 16'h9C42 ; +3378 : douta <= 16'h9C42 ; +3379 : douta <= 16'h9C42 ; +3380 : douta <= 16'h9B42 ; +3381 : douta <= 16'h9B42 ; +3382 : douta <= 16'h9C42 ; +3383 : douta <= 16'h9C42 ; +3384 : douta <= 16'h9C42 ; +3385 : douta <= 16'h9C42 ; +3386 : douta <= 16'h9C42 ; +3387 : douta <= 16'h9C42 ; +3388 : douta <= 16'h9C42 ; +3389 : douta <= 16'h9C42 ; +3390 : douta <= 16'h9C42 ; +3391 : douta <= 16'h9C42 ; +3392 : douta <= 16'h9C42 ; +3393 : douta <= 16'h9B42 ; +3394 : douta <= 16'h9B42 ; +3395 : douta <= 16'h9B42 ; +3396 : douta <= 16'h9B42 ; +3397 : douta <= 16'h9B42 ; +3398 : douta <= 16'h9A42 ; +3399 : douta <= 16'h9A42 ; +3400 : douta <= 16'h9A42 ; +3401 : douta <= 16'h9A42 ; +3402 : douta <= 16'h9A42 ; +3403 : douta <= 16'h9A42 ; +3404 : douta <= 16'h9A42 ; +3405 : douta <= 16'h9A42 ; +3406 : douta <= 16'h9A42 ; +3407 : douta <= 16'h9A42 ; +3408 : douta <= 16'h9A42 ; +3409 : douta <= 16'h9942 ; +3410 : douta <= 16'h9A42 ; +3411 : douta <= 16'h9A42 ; +3412 : douta <= 16'h9A42 ; +3413 : douta <= 16'h9A42 ; +3414 : douta <= 16'h9A42 ; +3415 : douta <= 16'h9A42 ; +3416 : douta <= 16'h9A42 ; +3417 : douta <= 16'h9A42 ; +3418 : douta <= 16'h9A42 ; +3419 : douta <= 16'h9A42 ; +3420 : douta <= 16'h9942 ; +3421 : douta <= 16'h9942 ; +3422 : douta <= 16'h9942 ; +3423 : douta <= 16'h9942 ; +3424 : douta <= 16'h9942 ; +3425 : douta <= 16'h9942 ; +3426 : douta <= 16'h9942 ; +3427 : douta <= 16'h9942 ; +3428 : douta <= 16'h9942 ; +3429 : douta <= 16'h9942 ; +3430 : douta <= 16'h9942 ; +3431 : douta <= 16'h9942 ; +3432 : douta <= 16'h9942 ; +3433 : douta <= 16'h9942 ; +3434 : douta <= 16'h9942 ; +3435 : douta <= 16'h9942 ; +3436 : douta <= 16'h9942 ; +3437 : douta <= 16'h9942 ; +3438 : douta <= 16'h9942 ; +3439 : douta <= 16'h9842 ; +3440 : douta <= 16'h9842 ; +3441 : douta <= 16'h9942 ; +3442 : douta <= 16'h9842 ; +3443 : douta <= 16'h9842 ; +3444 : douta <= 16'h9842 ; +3445 : douta <= 16'h9842 ; +3446 : douta <= 16'h9842 ; +3447 : douta <= 16'h9842 ; +3448 : douta <= 16'h9842 ; +3449 : douta <= 16'h9842 ; +3450 : douta <= 16'h9842 ; +3451 : douta <= 16'h9842 ; +3452 : douta <= 16'h9842 ; +3453 : douta <= 16'h9842 ; +3454 : douta <= 16'h9842 ; +3455 : douta <= 16'h9842 ; +3456 : douta <= 16'h9842 ; +3457 : douta <= 16'h9842 ; +3458 : douta <= 16'h9842 ; +3459 : douta <= 16'h9742 ; +3460 : douta <= 16'h9742 ; +3461 : douta <= 16'h9842 ; +3462 : douta <= 16'h9842 ; +3463 : douta <= 16'h9842 ; +3464 : douta <= 16'h9842 ; +3465 : douta <= 16'h9842 ; +3466 : douta <= 16'h9842 ; +3467 : douta <= 16'h9842 ; +3468 : douta <= 16'h9642 ; +3469 : douta <= 16'h9642 ; +3470 : douta <= 16'h9642 ; +3471 : douta <= 16'h9642 ; +3472 : douta <= 16'h9642 ; +3473 : douta <= 16'h9642 ; +3474 : douta <= 16'h9642 ; +3475 : douta <= 16'h9642 ; +3476 : douta <= 16'h9642 ; +3477 : douta <= 16'h9642 ; +3478 : douta <= 16'h9642 ; +3479 : douta <= 16'h9642 ; +3480 : douta <= 16'h9642 ; +3481 : douta <= 16'h9642 ; +3482 : douta <= 16'h9642 ; +3483 : douta <= 16'h9642 ; +3484 : douta <= 16'h9542 ; +3485 : douta <= 16'h9542 ; +3486 : douta <= 16'h9542 ; +3487 : douta <= 16'h9642 ; +3488 : douta <= 16'h9642 ; +3489 : douta <= 16'h9642 ; +3490 : douta <= 16'h9642 ; +3491 : douta <= 16'h9642 ; +3492 : douta <= 16'h9642 ; +3493 : douta <= 16'h9542 ; +3494 : douta <= 16'h9542 ; +3495 : douta <= 16'h9542 ; +3496 : douta <= 16'h9542 ; +3497 : douta <= 16'h9542 ; +3498 : douta <= 16'h9542 ; +3499 : douta <= 16'h9542 ; +3500 : douta <= 16'h9542 ; + + + +default:douta<=16'h9542; +endcase + +end + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/ds18b20_temp.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/ds18b20_temp.v new file mode 100644 index 0000000..d7a8471 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/ds18b20_temp.v @@ -0,0 +1,368 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:59:21 10/19/2020 +// Design Name: +// Module Name: DS18B20 +// Project Name: +// Target Devices: +// Tool versions: +// Description: + +//+125 0000 0111 1101 0000 07D0h +//+85* 0000 0101 0101 0000 0550h +//+25.0625 0000 0001 1001 0001 0191h +//+10.125 0000 0000 1010 0010 00A2h +//+0.5 0000 0000 0000 1000 0008h +//0 0000 0000 0000 0000 0000h +//-0.5 1111 1111 1111 1000 FFF8h +//-10.125 1111 1111 0101 1110 FF5Eh +//-25.0625 1111 1110 0110 1111 FE6Fh +//-55 1111 1100 1001 0000 FC90h +////////////////////////////////////////////////////////////////////////////////// +module ds18b20_temp( + input clk , //40_000_000 + input rstn , + inout dq , + output reg signed[15:0] temp_data //LSB =0.625 C +); + +parameter FRE = 40 ;// //clk为40M时钟，若clk为50M，则 FRE=50ï¼› + +parameter INIT = 3'b000 , //Gray code + WR_CMD = 3'b001 , + WAIT = 3'b011 , + INIT_AGAIN = 3'b010 , + RD_CMD = 3'b110 , + RD_TEMP = 3'b111 ; + +localparam WR_CC_44 = 16'h44cc ; +localparam WR_CC_BE = 16'hbecc ; +localparam cnt_max = FRE[31:1]-1 ; +localparam WAIT_TEMP_CNT = 20'd750_000 ;//750ms + +reg flag ; +reg [15:0] data_reg ; +reg [2:0] state ; +reg clk_1us ; +reg [31:0] cnt_1us ; +reg dq_en ; +reg dq_reg ; +reg [19:0] cnt ; +reg [3:0] bit_cnt ; + +assign dq = dq_en ? dq_reg : 1'bz; + +always@(posedge clk,negedge rstn) + if(!rstn) + cnt_1us<=32'b0; + else if(cnt_1us==cnt_max) + cnt_1us<=32'b0; + else + cnt_1us<=cnt_1us+1'b1; + +always@(posedge clk,negedge rstn) + if(!rstn) + clk_1us<=1'b0; + else if(cnt_1us==cnt_max) + clk_1us<=~clk_1us; + else + clk_1us<=clk_1us; + +always@(posedge clk_1us,negedge rstn) + if(!rstn) + begin + dq_en <=1'b1; + dq_reg <=1'b0; + state <=INIT; + cnt <=20'd0; + flag <=1'b0; + bit_cnt <=4'b0; + data_reg <=16'd0; + temp_data<=12'b0; + end + else case(state) + INIT :begin + //if(cnt==16'd999)begin //for sim + if(cnt==16'd9999) + cnt <=20'd0; + else if(cnt==16'd999&&flag)begin + cnt <=20'd0; + state<=WR_CMD; + end + else begin + cnt <=cnt+1'd1; + state<=INIT; + end + //------------------ + if(cnt==16'd9999)begin + dq_en <=1'b1; + dq_reg<=1'b0; + end + //else if(cnt==16'd499)begin + else if(cnt==16'd599)begin + dq_en <=1'b0; + dq_reg<=1'b0; + end + else begin + dq_en <=dq_en; + dq_reg<=dq_reg; + end + //------------------ + // if(cnt==20'd570)//&&dq==1'b0) + if(cnt==20'd670)//&&dq==1'b0) + flag<= ~dq; + else if(cnt==20'd999) + flag<=1'b0; + else + flag<=flag; + end + /* INIT :begin + //if(cnt==16'd999)begin //for sim + if(cnt==16'd999&&flag)begin + cnt <=20'd0; + state<=WR_CMD; + end + else begin + cnt <=cnt+1'd1; + state<=INIT; + end + //------------------ + if(cnt==16'd499)begin + dq_en <=1'b0; + dq_reg<=1'b0; + end + else begin + dq_en <=dq_en; + dq_reg<=dq_reg; + end + //------------------ + if(cnt==20'd570)//&&dq==1'b0) + flag<= ~dq; + else if(cnt==20'd999) + flag<=1'b0; + else + flag<=flag; + end */ + WR_CMD :begin + if(cnt==20'd64 && bit_cnt==4'd15) + begin + bit_cnt<=4'd0; + state<=WAIT; + end + else if(cnt==20'd64) + begin + bit_cnt<=bit_cnt+1'd1; + state<=WR_CMD; + end + else + begin + bit_cnt<=bit_cnt; + state<=WR_CMD; + end + //------------------ + if(cnt==20'd64 && bit_cnt==4'd15) + cnt<=20'd0; + else if(cnt==20'd64) + cnt<=20'd0; + else + cnt<=cnt+1'd1; + //------------------ + if(WR_CC_44[bit_cnt]==1'b0 && cnt<=20'd62) + begin + dq_en <=1'b1; + dq_reg<=1'b0; + end + else if(WR_CC_44[bit_cnt]==1'b1 && cnt<=20'd1) + begin + dq_en <=1'b1; + dq_reg<=1'b0; + end + else + begin + dq_en <=1'b0; + dq_reg<=1'b0; + end + end + WAIT : if(cnt==WAIT_TEMP_CNT) + begin + dq_en <=1'b1; + dq_reg<=1'b0; + cnt<=20'd0; + state<=INIT_AGAIN; + end + else + begin + dq_en <=1'b1; + dq_reg<=1'b1; + cnt<=cnt+1'd1; + state<=WAIT; + end + INIT_AGAIN :begin + if(cnt==16'd999&&flag) + //if(cnt==16'd999) //for sim + begin + cnt <=20'd0; + state<=RD_CMD; + end + else + begin + cnt <=cnt+1'd1; + state<=INIT_AGAIN; + end + //------------------ + if(cnt==16'd499) + begin + dq_en <=1'b0; + dq_reg<=1'b0; + end + else + begin + dq_en <=dq_en; + dq_reg<=dq_reg; + end + //------------------ + if(cnt==20'd570)//&&dq==1'b0) + flag<=~dq; + else if(cnt==20'd999) + flag<=1'b0; + else + flag<=flag; + end + RD_CMD :begin + if(cnt==20'd64 && bit_cnt==4'd15) + begin + bit_cnt<=4'd0; + state<=RD_TEMP; + end + else if(cnt==20'd64) + begin + bit_cnt<=bit_cnt+1'd1; + state<=RD_CMD; + end + else + begin + bit_cnt<=bit_cnt; + state<=RD_CMD; + end + //------------------ + if(cnt==20'd64 && bit_cnt==4'd15) + cnt<=20'd0; + else if(cnt==20'd64) + cnt<=20'd0; + else + cnt<=cnt+1'd1; + //------------------ + if(WR_CC_BE[bit_cnt]==1'b0 && cnt<=20'd62) + begin + dq_en <=1'b1; + dq_reg<=1'b0; + end + else if(WR_CC_BE[bit_cnt]==1'b1 && cnt<=20'd1) + begin + dq_en <=1'b1; + dq_reg<=1'b0; + end + else + begin + dq_en <=1'b0; + dq_reg<=1'b0; + end + end + RD_TEMP :begin + if(cnt==20'd64 && bit_cnt==4'd15) + cnt <=20'd0; + else if(cnt==20'd64) + cnt<=20'd0; + else + cnt<=cnt+1'd1; + //------------------ + if(cnt<=20'd1|| (cnt==20'd64 && bit_cnt==4'd15)) + begin + dq_en <=1'b1; + dq_reg<=1'b0; + end + else + begin + dq_en <=1'b0; + dq_reg<=1'b0; + end + //------------------ + if(cnt==20'd64 && bit_cnt==4'd15) + begin + bit_cnt<=4'd0; + state<=INIT; + end + else if(cnt==20'd64) + begin + bit_cnt<=bit_cnt+1'd1; + state<=RD_TEMP; + end + else + begin + bit_cnt<=bit_cnt; + state<=RD_TEMP; + end + //------------------ + if(cnt==20'd8) + data_reg<={dq,data_reg[15:1]}; + else + data_reg<=data_reg; + //------------------ + if(cnt==20'd64 && bit_cnt==4'd15) + temp_data<=data_reg; + else + temp_data<=temp_data; + end + default: state<=INIT; + endcase + + +/* wire[33:0]SYNC_OUT; +wire[35:0]CONTROL0; +wire[35:0]CONTROL1; +wire[149:0]TRIG0; + + vio u_vio ( + .CONTROL (CONTROL0), // INOUT BUS [35:0] + .CLK (clk), // IN + .SYNC_OUT (SYNC_OUT) // OUT BUS [33:0] +); + + +icon u_icon ( + .CONTROL0 (CONTROL0), // INOUT BUS [35:0] + .CONTROL1 (CONTROL1) // INOUT BUS [35:0] +); + + +ila u_ila ( + .CONTROL (CONTROL1), // INOUT BUS [35:0] + .CLK (clk), // IN + .TRIG0 (TRIG0) // IN BUS [39:0] +); + + +assign TRIG0[2:0] = state ; +assign TRIG0[21:3] = cnt ; +assign TRIG0[22] = dq ; + */ + + + + + + + + + + + + + + + + +endmodule \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/frac2_rom.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/frac2_rom.v new file mode 100644 index 0000000..286a0a3 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/frac2_rom.v @@ -0,0 +1,72 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:35:03 01/27/2022 +// Design Name: +// Module Name: mod2_rom +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module frac2_rom( +input sysclk, +input [11 : 0] addra, +output reg[13:0] douta +); + + +reg[11:0] addr=0; + +always@(posedge sysclk)begin + addr<=addra%25; +end + +always@(posedge sysclk)begin + case(addr) +0 : douta <= 0; +1 : douta <= 2; +2 : douta <= 4; +3 : douta <= 6; +4 : douta <= 8; +5 : douta <= 2; +6 : douta <= 12; +7 : douta <= 14; +8 : douta <= 16; +9 : douta <= 18; +10 : douta <= 4; +11 : douta <= 22; +12 : douta <= 24; +13 : douta <= 1; +14 : douta <= 3; +15 : douta <= 1; +16 : douta <= 7; +17 : douta <= 9; +18 : douta <= 11; +19 : douta <= 13; +20 : douta <= 3; +21 : douta <= 17; +22 : douta <= 19; +23 : douta <= 21; +24 : douta <= 23; +default:douta <= douta ; +endcase + +end + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/fre_caliatt.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/fre_caliatt.v new file mode 100644 index 0000000..a8e733e --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/fre_caliatt.v @@ -0,0 +1,210 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 10:03:33 09/24/2021 +// Design Name: +// Module Name: fre_caliatt +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module fre_caliatt( +input i_clk , +input i_rstn , +output ENABLE , +output SC , +output SD , +output END_SYN , +input SDOUT , +input CAL_F , +input signed[7:0] i_temp , +input[15:0] i_fre_mode , +input[15:0] i_cal_fre_code , +input [3:0] cal1_mgc , +input [3:0] cal2_mgc , +input [3:0] cal3_mgc , +input [3:0] cal4_mgc , +input [3:0] i_ceshi_module , +input [40:0] SYNC_OUT , +input SW , +output [3:0] R_CAL1 , +output [3:0] R_CAL2 , +output [3:0] R_CAL3 , +output [3:0] R_CAL4 , +input [4:0] tx_mgc , +input [4:0] tx_cal_mgc , +output [4:0] T_CAL + ); + + +wire[15:0] fre_mode ; +wire[31:0] hop_fre_mode ; +assign fre_mode = i_cal_fre_code/40 ;//20.375Ghz~23.875Ghz +assign hop_fre_mode = i_cal_fre_code+20375 ;//20.375Ghz~23.875Ghz + + +wire [3:0] R_CAL4_r ; +wire [3:0] R_CAL3_r ; +wire [3:0] R_CAL2_r ; +wire [3:0] R_CAL1_r ; +wire [4:0] T_CAL_r ; +wire [31:0] data_in ; +reg [31:0] data_in_r ; +reg R_CAL_F ; +wire[15:0] cal_mgc_r ; +reg [15:0] cal_mgc_rr ; +reg tx_en ; +reg vio_en ; + + + + +always@(posedge i_clk) +begin + cal_mgc_rr <= cal_mgc_r; +end +//------------------vio_debug------------------------// +/* always@(posedge i_clk) +begin + vio_R_CAL_4 <= SYNC_OUT[4:0]; + vio_R_CAL_3 <= SYNC_OUT[9:5]; + vio_R_CAL_2 <= SYNC_OUT[14:10]; + vio_R_CAL_1 <= SYNC_OUT[19:15]; + vio_T_CAL <= SYNC_OUT[24:20]; + vio_en <= SYNC_OUT[25]; +end */ + +//------------------vio_debug------------------------// +assign R_CAL1 = R_CAL1_r + cal1_mgc ;//通é“1 +assign R_CAL2 = R_CAL2_r + cal2_mgc ;//通é“2 +assign R_CAL3 = R_CAL3_r + cal3_mgc ;//通é“3 +assign R_CAL4 = R_CAL4_r + cal4_mgc ;//通é“4 +assign T_CAL = ( i_ceshi_module==4'ha || i_ceshi_module==4'hb) ? (tx_mgc[4:0] + tx_cal_mgc) : (T_CAL_r + tx_cal_mgc) ;//å‘射通é“ï¼Œä½Žè¡°å‡ + +assign cal_mgc_r = {cal1_mgc,cal2_mgc,cal3_mgc,cal4_mgc}; +assign data_in = { 4'h0,3'b0, + T_CAL , //å‘å°„é€šé“ + R_CAL1[0], //接收通é“1_1dB + R_CAL1[1], //接收通é“1_2dB + R_CAL1[2], //接收通é“1_4dB + R_CAL1[3], //接收通é“1_8dB + R_CAL2[0], //接收通é“2_1dB + R_CAL2[1], //接收通é“2_2dB + R_CAL2[2], //接收通é“2_4dB + R_CAL2[3], //接收通é“2_8dB + R_CAL3[0], //接收通é“3_1dB + R_CAL3[1], //接收通é“3_2dB + R_CAL3[2], //接收通é“3_4dB + R_CAL3[3], //接收通é“3_8dB + R_CAL4 , // + 4'b0 }; +reg [31:0] cnt5us=0; + +always@(posedge i_clk)begin + if(cnt5us==2000) + cnt5us<=2000; + else + cnt5us<=cnt5us+1'b1; +end + +always@(posedge i_clk or negedge i_rstn)begin +if(!i_rstn) + R_CAL_F <= 1'b0; +else + R_CAL_F <= CAL_F; +end + +always@(posedge i_clk or negedge i_rstn)begin + if(!i_rstn) + tx_en<=1'b0; + else if(cnt5us==1999) + tx_en<=1'b1; + else if({R_CAL_F,CAL_F}==2'b01 || cal_mgc_rr!=cal_mgc_r) + tx_en<=1'b1; + else + tx_en<=1'b0; +end + + + +R_CAL_1 R_CAL_1 ( + .i_clk(i_clk), + .i_rstn(i_rstn), + .i_temp(i_temp), + .fre_mode(fre_mode), + .R_CAL(R_CAL1_r) + ); + +R_CAL_2 R_CAL_2 ( + .i_clk(i_clk), + .i_rstn(i_rstn), + .i_temp(i_temp), + .fre_mode(fre_mode), + .R_CAL(R_CAL2_r) + ); + +R_CAL_3 R_CAL_3 ( + .i_clk(i_clk), + .i_rstn(i_rstn), + .i_temp(i_temp), + .fre_mode(fre_mode), + .R_CAL(R_CAL3_r) + ); + +R_CAL_4 R_CAL_4 ( + .i_clk(i_clk), + .i_rstn(i_rstn), + .i_temp(i_temp), + .fre_mode(fre_mode), + .R_CAL(R_CAL4_r) + ); + + +T_CAL T_CAL__ ( + .i_clk(i_clk), + .i_rstn(i_rstn), + .SW(SW), + .i_temp(i_temp), + .hop_fre_mode(hop_fre_mode), + .T_CAL_(T_CAL_r) + ); + + +spi_tx SPI_TX ( + .clk (i_clk ) , + .rstn (i_rstn ) , + .tx_en (tx_en ) , + .data_in (data_in ) , + .spi_cs (ENABLE ) , + .spi_sclk (SC ) , + .spi_sdo (SD ) , + .DARY (END_SYN ) + ); + + + + + + + + + + + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/mgc_ctrl.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/mgc_ctrl.v new file mode 100644 index 0000000..a537295 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/mgc_ctrl.v @@ -0,0 +1,434 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 19:54:29 09/06/2021 +// Design Name: +// Module Name: mgc_ctrl +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mgc_ctrl( +input i_sys_clk , +input i_rst_n , +input i_TR_SW_F , +input i_TP_EN_F , +input i_CAL_F , +input i_T_MGC_EN_F , +input i_R_MGC_EN_F , + +input [15:0] i_fre_code , +input [7:0] i_tx_mgc , +input [7:0] i_rx1_mgc , +input [7:0] i_rx2_mgc , +input [7:0] i_rx3_mgc , +input [7:0] i_rx4_mgc , +input [3:0] i_ceshi_module, +output [15:0] o_current_fre_code, +output [15:0] o_cal_fre_code, +output [15:0] o_hop_fre_code, +output o_adf4371_hop1, +output o_adf4371_hop2, + +output o_SW, +output o_SW2, +output o_SW3, +output o_SW_C1, + +//·¢ÉäͨµÀMGC¿ØÖÆ£¬¸ßË¥¡£31dB£¬²½½ø1dB¡£³õʼֱ̬ͨ£¨È«ÖÃ1£© +output o_T_MGC_1dB, +output o_T_MGC_2dB, +output o_T_MGC_4dB, +output o_T_MGC_8dB, +output o_T_MGC_16dB, +//½ÓÊÕͨµÀ1MGC¿ØÖÆ£¬¸ßË¥¡£31dB£¬²½½ø1dB¡£³õʼֱ̬ͨ£¨È«ÖÃ1£© +output reg[7:0] o_R_MGC_1, + +//½ÓÊÕͨµÀ2MGC¿ØÖÆ£¬¸ßË¥¡£31dB£¬²½½ø1dB¡£³õʼֱ̬ͨ£¨È«ÖÃ1£© +output reg[7:0] o_R_MGC_2, + +//½ÓÊÕͨµÀ3MGC¿ØÖÆ£¬¸ßË¥¡£31dB£¬²½½ø1dB¡£³õʼֱ̬ͨ£¨È«ÖÃ1£© +output reg[7:0] o_R_MGC_3, +//½ÓÊÕͨµÀ4MGC¿ØÖÆ£¬¸ßË¥¡£31dB£¬²½½ø1dB¡£³õʼֱ̬ͨ£¨È«ÖÃ1£© +output reg[7:0] o_R_MGC_4 + +); + + +reg TR_SW_F; +reg [2:0] TP_EN_r; +reg [2:0] T_MGC_EN_r; +reg [2:0] R_MGC_EN_r; +reg [2:0] R_CAL_F; +reg [15:0] hop_fre_code; +reg [15:0] current_fre_code; +wire [15:0] cal_fre_code; +reg [47:0] fre_code_a_b; +reg hop_en; +reg hop_en_r; +reg hop_en_rr; +reg cfg_en; +reg cfg_en_r; +reg cfg_en_rr; +reg hmc704_1_hop; +reg hmc704_2_hop; +reg [1:0] cnt_cfg; +reg [1:0] cnt_hop; + + +reg sw1; +reg sw2; +reg sw3; +reg SW_C1; + +reg T_MGC_1dB_r ; +reg T_MGC_2dB_r ; +reg T_MGC_4dB_r ; +reg T_MGC_8dB_r ; +reg T_MGC_16dB_r; + +assign o_SW = sw1; +assign o_SW2 = sw2; +assign o_SW3 = sw3; +assign o_SW_C1 = SW_C1; + +assign o_current_fre_code= current_fre_code; +assign o_cal_fre_code = cal_fre_code; +assign o_hop_fre_code = hop_fre_code; +assign o_adf4371_hop1 = hmc704_1_hop; +assign o_adf4371_hop2 = hmc704_2_hop; + +assign o_T_MGC_1dB = T_MGC_1dB_r ; +assign o_T_MGC_2dB = T_MGC_2dB_r ; +assign o_T_MGC_4dB = T_MGC_4dB_r ; +assign o_T_MGC_8dB = T_MGC_8dB_r ; +assign o_T_MGC_16dB = T_MGC_16dB_r ; + + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + TR_SW_F <= 1'b0; + TP_EN_r <= 3'b0; + T_MGC_EN_r <= 3'b0; + R_MGC_EN_r <= 3'b0; + R_CAL_F <= 3'b0; +end +else begin + TR_SW_F <= i_TR_SW_F; + TP_EN_r <= {TP_EN_r[1:0] ,i_TP_EN_F}; + T_MGC_EN_r <= {T_MGC_EN_r[1:0] ,i_T_MGC_EN_F}; + R_MGC_EN_r <= {R_MGC_EN_r[1:0] ,i_R_MGC_EN_F}; + R_CAL_F <= {R_CAL_F[1:0] ,i_CAL_F}; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + SW_C1 <= 1'b0; + current_fre_code <= 16'h6d6 ; +end +else begin + current_fre_code <= hop_en ? hop_fre_code : current_fre_code ; + if(TR_SW_F==1'b1)begin + if(current_fre_code<=1500)//20.375Ghz~21.875Ghz + SW_C1 <= 1'b1; + else //21.875Ghz~23.875Ghz + SW_C1 <= 1'b0; + end + else begin + SW_C1 <= SW_C1; + end +end +end + + +assign cal_fre_code = R_CAL_F==3'b001 ? hop_fre_code : cal_fre_code ; + + + + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + fre_code_a_b <= 48'h0000000006d6; +end +else if(cfg_en)begin + fre_code_a_b <= {fre_code_a_b[31:0],i_fre_code}; +end +else begin + fre_code_a_b <= fre_code_a_b; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + hop_en <= 1'b0; +end +else if(TP_EN_r==3'b011)begin + hop_en <= 1'b1; +end +else begin + hop_en <= 1'b0; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + hop_fre_code <= 16'h6d6; +end +else begin + hop_fre_code <= i_fre_code; +end +end + + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + cfg_en <= 1'b0; +end +else if(hop_fre_code != i_fre_code)begin + cfg_en <= 1'b1; +end +else begin + cfg_en <= 1'b0; +end +end + + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + hop_en_r <= 1'b0; + hop_en_rr <= 1'b0; +end +else begin + hop_en_r <= hop_en; + hop_en_rr <= hop_en_r; +end +end + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + cfg_en_r <= 1'b0; + cfg_en_rr <= 1'b0; +end +else begin + cfg_en_r <= cfg_en; + cfg_en_rr <= cfg_en_r; +end +end + +reg [15:0] pre_hop_fre_code; +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + cnt_hop <= 2'b00; +end +else if(cnt_hop == 2'b10)begin + cnt_hop <= 2'b00; +end +else if(~hop_en_r & hop_en && (pre_hop_fre_code!=hop_fre_code ))begin + cnt_hop <= cnt_hop + 1'b1; +end +else begin + cnt_hop <= cnt_hop; +end +end + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + cnt_cfg <= 2'b00; +end +else if(cnt_cfg == 2'b10)begin + cnt_cfg <= 2'b00; +end +else if(~cfg_en_r&cfg_en)begin + cnt_cfg <= cnt_cfg + 1'b1; +end +else begin + cnt_cfg <= cnt_cfg; +end +end + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n) + pre_hop_fre_code<=16'h6d6; +else if(hop_en_rr) + pre_hop_fre_code<=hop_fre_code; +else + pre_hop_fre_code<=pre_hop_fre_code; +end + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + sw1 <= 1'b1; + sw2 <= 1'b1; + sw3 <= 1'b0; +end +else if(i_ceshi_module==4'ha)//×Ô¶¯Ð£×¼¿ª¹Øµ½a +begin + sw1 <= 1'b0; + sw2 <= 1'b0; + sw3 <= 1'b1; +end +else if(i_ceshi_module==4'hb)//×Ô¶¯Ð£×¼¿ª¹Øµ½b +begin + sw1 <= 1'b1; + sw2 <= 1'b1; + sw3 <= 1'b0; +end +else if(hop_en_rr && pre_hop_fre_code != hop_fre_code)begin + if(cnt_hop == 2'b01)begin + sw1 <= 1'b0; + sw2 <= 1'b0; + sw3 <= 1'b1; + end + else begin + sw1 <= 1'b1; + sw2 <= 1'b1; + sw3 <= 1'b0; + end +end +else begin + sw1 <= sw1; + sw2 <= sw2; + sw3 <= sw3; +end +end + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b0; +end +else if(i_ceshi_module==4'ha&&cfg_en_rr)begin + hmc704_1_hop <= 1'b1; + hmc704_2_hop <= 1'b0; +end +else if(i_ceshi_module==4'hb&&cfg_en_rr)begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b1; +end +else if(cfg_en_rr)begin + if(fre_code_a_b[47:32]==fre_code_a_b[15:0])begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b0; + end + else if(cnt_cfg == 2'b01)begin + hmc704_1_hop <= 1'b1; + hmc704_2_hop <= 1'b0; + end + else begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b1; + end +end +else begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b0; +end +end + +/* always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + sw1 <= 1'b1; + sw2 <= 1'b1; + sw3 <= 1'b0; +end +end + +always @ (posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b0; +end +else if(cfg_en_rr)begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b1; +end +else begin + hmc704_1_hop <= 1'b0; + hmc704_2_hop <= 1'b0; +end +end */ + + + + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + T_MGC_1dB_r <= 1'b0; + T_MGC_2dB_r <= 1'b0; + T_MGC_4dB_r <= 1'b0; + T_MGC_8dB_r <= 1'b0; + T_MGC_16dB_r <= 1'b0; +end +else if(i_ceshi_module==4'ha || i_ceshi_module==4'hb )begin + T_MGC_1dB_r <= 1'b0; + T_MGC_2dB_r <= 1'b0; + T_MGC_4dB_r <= 1'b0; + T_MGC_8dB_r <= 1'b0; + T_MGC_16dB_r <= 1'b0; +end +else if(T_MGC_EN_r==3'b011)begin + T_MGC_1dB_r <= i_tx_mgc[0]; + T_MGC_2dB_r <= i_tx_mgc[1]; + T_MGC_4dB_r <= i_tx_mgc[2]; + T_MGC_8dB_r <= i_tx_mgc[3]; + T_MGC_16dB_r <= i_tx_mgc[4]; +end +else begin + T_MGC_1dB_r <= T_MGC_1dB_r ; + T_MGC_2dB_r <= T_MGC_2dB_r ; + T_MGC_4dB_r <= T_MGC_4dB_r ; + T_MGC_8dB_r <= T_MGC_8dB_r ; + T_MGC_16dB_r <= T_MGC_16dB_r ; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + o_R_MGC_1 <= 1'b0; +end +else if(R_MGC_EN_r==3'b011)begin + o_R_MGC_1 <= i_rx1_mgc; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + o_R_MGC_2 <= 1'b0; +end +else if(R_MGC_EN_r==3'b011)begin + o_R_MGC_2 <= i_rx2_mgc; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + o_R_MGC_3 <= 1'b0; +end +else if(R_MGC_EN_r==3'b011)begin + o_R_MGC_3 <= i_rx3_mgc; +end +end + +always@(posedge i_sys_clk or negedge i_rst_n)begin +if(!i_rst_n)begin + o_R_MGC_4 <= 1'b0; +end +else if(R_MGC_EN_r==3'b011)begin + o_R_MGC_4 <= i_rx4_mgc; + +end +end + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/mod2_rom.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/mod2_rom.v new file mode 100644 index 0000000..b119dea --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/mod2_rom.v @@ -0,0 +1,71 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:35:03 01/27/2022 +// Design Name: +// Module Name: mod2_rom +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mod2_rom( +input sysclk, +input [11 : 0] addra, + +output reg[13:0] douta +); + +reg[11:0] addr=0; +always@(posedge sysclk)begin + addr<=addra%25; +end + +always@(posedge sysclk)begin + case(addr) +0 : douta <= 1 ; +1 : douta <= 25 ; +2 : douta <= 25 ; +3 : douta <= 25 ; +4 : douta <= 25 ; +5 : douta <= 5 ; +6 : douta <= 25 ; +7 : douta <= 25 ; +8 : douta <= 25 ; +9 : douta <= 25 ; +10 : douta <= 5 ; +11 : douta <= 25 ; +12 : douta <= 25 ; +13 : douta <= 25 ; +14 : douta <= 25 ; +15 : douta <= 5 ; +16 : douta <= 25 ; +17 : douta <= 25 ; +18 : douta <= 25 ; +19 : douta <= 25 ; +20 : douta <= 5 ; +21 : douta <= 25 ; +22 : douta <= 25 ; +23 : douta <= 25 ; +24 : douta <= 25 ; +default:douta <= douta ; +endcase + +end + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/spi_master.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/spi_master.v new file mode 100644 index 0000000..2aa6f7e --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/spi_master.v @@ -0,0 +1,150 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 20:42:39 09/29/2021 +// Design Name: +// Module Name: spi_master +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module spi_master #(parameter BIT_NUM = 95 )( + input i_clk , + input debug_clk , + input i_sys_rst_n , + input i_spi_sck , + input i_spi_cs , + output o_spi_sdo , + input i_spi_sdi , + input i_LD_LO3 , + input i_LD1 , + input i_LD2 , + input[3:0] i_cal1_mgc , + input[3:0] i_cal2_mgc , + input[3:0] i_cal3_mgc , + input[3:0] i_cal4_mgc , + input[7:0] i_temp , + input[31:0] i_frame_count + +); + +wire [BIT_NUM:0] data ; +reg [BIT_NUM:0] data_r ; +reg [BIT_NUM:0] data_reg ; +assign data={ 8'hAA , + i_temp , + 7'b0,i_LD_LO3 , + 7'b0,i_LD1 , + 7'b0,i_LD2 , + i_cal1_mgc,i_cal2_mgc , + i_cal3_mgc,i_cal4_mgc , + i_frame_count , + 8'hCC } ; + +wire spi_sck ; +wire spi_cs ; +reg spi_sdo ; +reg [2:0] reg_cs ; +reg [31:0] cnt ; + +assign spi_sck = i_spi_sck; +assign spi_cs = i_spi_cs; +assign o_spi_sdo = spi_sdo; + +always@(negedge spi_sck,negedge i_sys_rst_n)begin + if(!i_sys_rst_n) + reg_cs<=3'b111; + else + reg_cs<={reg_cs[1:0],i_spi_cs}; +end + +always@(negedge spi_sck,negedge i_sys_rst_n)begin + if(!i_sys_rst_n) + data_r<={8'hAA,80'b0,8'hCC}; + else if(reg_cs[2:1]==2'b10) + data_r<={8'hAA,data[87:8],8'hCC}; +end + +always@(negedge spi_sck,negedge i_sys_rst_n)begin + if(!i_sys_rst_n) + spi_sdo <= 1'b0 ; + else if(!spi_cs) + spi_sdo <= data_r[cnt]; + else + spi_sdo <= 1'b0 ; +end + +always@(posedge spi_sck,negedge i_sys_rst_n)begin + if(!i_sys_rst_n) + cnt<=BIT_NUM; + else if(spi_cs==1 | cnt==0) + cnt<=BIT_NUM; + else + cnt<=cnt-1; +end + +//------------debug------------ +always@(posedge spi_sck,negedge i_sys_rst_n)begin + if(!i_sys_rst_n) + data_reg <= 0 ; + else if(!spi_cs) + data_reg <= {data_reg,spi_sdo} ; + else + data_reg <= data_reg ; +end +//------------debug------------ + +/* +wire [40:0] SYNC_OUT ; +wire [35:0] CONTROL0 ; +wire [35:0] CONTROL1 ; +wire [150:0] TRIG0 ; + +vio u_vio ( + .CONTROL (CONTROL0), // INOUT BUS [35:0] + .CLK (i_clk), // IN + .SYNC_OUT (SYNC_OUT) // OUT BUS [33:0] +); + + +icon u_icon ( + .CONTROL0 (CONTROL0), // INOUT BUS [35:0] + .CONTROL1 (CONTROL1) // INOUT BUS [35:0] +); + + +ila u_ila ( + .CONTROL (CONTROL1), // INOUT BUS [35:0] + .CLK (debug_clk), // IN + .TRIG0 (TRIG0) // IN BUS [39:0] +); + + +assign TRIG0[0] = i_LD_LO3; +assign TRIG0[1] = i_LD1 ; +assign TRIG0[2] = i_LD2 ; +assign TRIG0[98:3] = data_r ; +assign TRIG0[101:99] = reg_cs ; +assign TRIG0[132:102] = cnt ; +assign TRIG0[133] = i_spi_sck ; +assign TRIG0[134] = i_spi_cs ; +assign TRIG0[135] = o_spi_sdo ; +assign TRIG0[136] = i_spi_sdi ; + + */ + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/spi_salve.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/spi_salve.v new file mode 100644 index 0000000..c358aaf --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/spi_salve.v @@ -0,0 +1,171 @@ + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2020/09/02 10:48:55 +// Design Name: +// Module Name: d +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// SPI时钟频率50MHz。æ¯ä¸€å¸§æ•°æ®12个字节，共96bitæ•°æ®ã€‚ +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module spi_slave#( + parameter BIT_NUM = 96 +) +( +input i_sys_clk, +input i_sys_rst_n, + +input i_spi_sck, //从机在时钟下é™æ²¿é‡‡æ ·æ•°æ® +input i_spi_cs, //低电平时从机接收数æ®æŒ‡ä»¤ +input i_spi_sdi, +output [31:0] o_frame_count, //帧计数 +output [15:0] o_fre_code , //天线频率 +output [7:0] o_tx_mgc, //å‘å°„MGC +output [3:0] o_model, //模å¼å­— +output [3:0] o_rf_en, //射频使能 +output [3:0] o_cal1_mgc, //接收校准1mgc +output [3:0] o_cal2_mgc, //接收校准2mgc +output [3:0] o_cal3_mgc, //接收校准3mgc +output [3:0] o_cal4_mgc, //接收校准4mgc +output [7:0] o_tx_cal_mgc, //å‘射校准mgc +output [7:0] o_rx1_mgc, //接收1mgc +output [7:0] o_rx2_mgc, //接收2mgc +output [7:0] o_rx3_mgc, //接收3mgc +output [7:0] o_rx4_mgc , //接收4mgc + +output [3:0] o_ceshi_model +); + +reg [BIT_NUM -1:0] receive_data; +reg [3:0] rf_en ; +reg [3:0] model; +reg [31:0] frame_count; +reg [11:0] fre_code; +reg [7:0] tx_mgc; +reg [7:0] rx1_mgc; +reg [7:0] rx2_mgc; +reg [7:0] rx3_mgc; +reg [7:0] rx4_mgc; +reg [3:0] cal1_mgc; +reg [3:0] cal2_mgc; +reg [3:0] cal3_mgc; +reg [3:0] cal4_mgc; +reg [7:0] tx_cal_mgc; +reg [3:0] ceshi_module; + + +assign o_frame_count= frame_count; +assign o_fre_code = {4'b0,fre_code}; +assign o_rf_en = rf_en; +assign o_model = model; +assign o_tx_mgc = tx_mgc; +assign o_cal1_mgc = cal1_mgc; +assign o_cal2_mgc = cal2_mgc; +assign o_cal3_mgc = cal3_mgc; +assign o_cal4_mgc = cal4_mgc; +assign o_tx_cal_mgc = tx_cal_mgc; +assign o_rx1_mgc = rx1_mgc; +assign o_rx2_mgc = rx2_mgc; +assign o_rx3_mgc = rx3_mgc; +assign o_rx4_mgc = rx4_mgc; +assign o_ceshi_model = ceshi_module; + +always @ ( negedge i_spi_sck or negedge i_sys_rst_n)begin +if( !i_sys_rst_n ) + receive_data <= 'b0; +else if(i_spi_cs == 1'b0) + receive_data <= {receive_data,i_spi_sdi}; +else + receive_data <= receive_data; +end + + +reg [2:0] cs_reg; + +always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin +if( !i_sys_rst_n ) + cs_reg <= 3'b111; +else + cs_reg <= {cs_reg[1:0],i_spi_cs}; +end + + + +always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin +if(!i_sys_rst_n)begin + tx_cal_mgc<=8'h0; +end +else if(cs_reg[2:1]==2'b01 && (receive_data[95:88] == 8'hbb) && (receive_data[7:0] == 8'hdd))begin + tx_cal_mgc<=receive_data[15:8]; +end +else begin + tx_cal_mgc<=tx_cal_mgc; +end +end + +always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin +if(!i_sys_rst_n)begin + fre_code <= 12'h6d6; + tx_mgc <= 8'h00; + rf_en <= 4'b1; + model <= 4'b0; + frame_count <= 32'd1; + rx1_mgc <= 4'h0; + rx2_mgc <= 4'h0; + rx3_mgc <= 4'h0; + rx4_mgc <= 4'h0; + cal1_mgc <= 4'h0; + cal2_mgc <= 4'h0; + cal3_mgc <= 4'h0; + cal4_mgc <= 4'h0; + ceshi_module <= 4'h0; +end +else if(cs_reg[2:1]==2'b01 && (receive_data[95:88] == 8'haa) && (receive_data[7:0] == 8'hcc))begin + frame_count <= frame_count+1'b1; + rf_en <= receive_data[87:84]; + model <= receive_data[83:80]; + ceshi_module<= receive_data[79:76]; + fre_code <= receive_data[75:64]; + tx_mgc <= receive_data[63:56]; + cal1_mgc <= receive_data[55:52]; + cal2_mgc <= receive_data[51:48]; + cal3_mgc <= receive_data[47:44]; + cal4_mgc <= receive_data[43:40]; + rx1_mgc <= receive_data[39:32]; + rx2_mgc <= receive_data[31:24]; + rx3_mgc <= receive_data[23:16]; + rx4_mgc <= receive_data[15:8]; +end +else begin + frame_count <= frame_count ; + rf_en <= rf_en ; + model <= model ; + fre_code <= fre_code ; + tx_mgc <= tx_mgc ; + cal1_mgc <= cal1_mgc ; + cal2_mgc <= cal2_mgc ; + cal3_mgc <= cal3_mgc ; + cal4_mgc <= cal4_mgc ; + rx1_mgc <= rx1_mgc ; + rx2_mgc <= rx2_mgc ; + rx3_mgc <= rx3_mgc ; + rx4_mgc <= rx4_mgc ; +end +end + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/spi_tx.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/spi_tx.v new file mode 100644 index 0000000..486071f --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/spi_tx.v @@ -0,0 +1,118 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:23:58 10/12/2020 +// Design Name: spi·¢ËÍÄ£¿é +// Module Name: spi +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module spi_tx #(parameter WHITH=32)( +input clk,//ϵͳʱÖÓ +input rstn,//Òì²½¸´Î» +input tx_en,//·¢ËÍʹÄÜ +input [WHITH-1:0] data_in,//´ý·¢ËÍÊý¾Ý +output reg spi_cs, //Ƭѡ +output reg spi_sclk, //ͬ²½Ê±ÖÓ£¬µÈÓÚclk/2 +output reg spi_sdo, //·¢ËÍÊý¾ÝµÄÏß +output reg DARY +); + +//localparam [1:0] polaeity = 2'b10;//negedge Êý¾ÝϽµÑر£³Ö +localparam [1:0] polaeity = 2'b01;//posedge Êý¾ÝÉϽµÑر£³Ö +reg [2:0] state ; //״̬»ú +reg [WHITH-1:0] reg_data;//ÒÆλ¼Ä´æÆ÷ +reg [5:0] cnt;//¼ÆÊýÆ÷£¬±ØÐë´óÓÚÊý¾Ýλ¿í + +wire CPOL ; //ʱÖÓ¿ÕÏÐʱµçƽ +wire CPHA ; //¼«ÐÔ +assign CPOL = polaeity[0] ; +assign CPHA = polaeity[1] ; + +always @(posedge clk,negedge rstn)begin +if(!rstn)begin + state <= 3'd0; + spi_cs <= 1'b1; + spi_sclk <= CPOL; + reg_data <= 1'd0; + cnt <= 5'b0; + spi_sdo <= 1'b0; + DARY <= 1'b1; +end +else begin + case(state) + 3'd0:begin//¿ÕÏÐ̬ + spi_sclk <= CPOL ; + spi_cs <= 1'b1 ; + spi_sdo <= 1'b0 ; + DARY <= 1'b1 ; + cnt <= 5'b0 ; + reg_data <= data_in ; + if(tx_en)//·¢ËÍʹÄÜÌøÏÂÒ»¸ö״̬ + state <= 3'd1 ; + else + state <= state ; + end + 3'd1:begin + spi_cs <= 1'b0 ; + state <= 3'd2 ; + reg_data <= data_in ; + end + 3'd2:begin//Êý¾ÝÒÆλ̬ + spi_cs <= 1'b0 ; + reg_data <= reg_data<<1'b1 ; + spi_sdo <= reg_data[WHITH-1] ; + spi_sclk <= CPHA ; + state <= (cnt >= WHITH-1) ? 3'd4:3'd3; + end + 3'd3:begin//ʱÖÓ·­×ª + cnt <= cnt+1'b1 ; + spi_sclk <= ~CPHA ; + state <= 3'd2 ; + end + 3'd4:begin//½áÊø̬ + state <= 3'd5; + spi_sclk <= ~CPHA; + end + 3'd5:begin//½áÊø̬ + state <= 3'd6; + DARY <= 0; + spi_sdo <= 1'b0 ; + spi_cs <= 1'b1 ; + end + 3'd6:begin//½áÊø̬ + state <= 3'd7; + DARY <= 1; + spi_cs <= 1'b1 ; + end + 3'd7:begin//½áÊø̬ + state <= 3'd8; + DARY <= 0; + end + 3'd8:begin//½áÊø̬ + state <= 3'd0; + DARY <= 1; + end + default :state<=3'd0; + endcase +end +end + + + + + + + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/ant_rf_ctrl.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/ant_rf_ctrl.v new file mode 100644 index 0000000..a9bfe7b --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/ant_rf_ctrl.v @@ -0,0 +1,515 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2022/07/13 14:20:24 +// Design Name: +// Module Name: ant_rf_ctrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ant_rf_ctrl +( + input clk_48m , + input clk_96m , + input clk_32m , + input clk_19p2m , + input sys_rst , + + output ant_clk , + output ant_en , + output ant_data , + output ant_tr , + output ant_dary , + input ant_dout , + + output rf_standby , + output rf_sw_pll , + output rf_t , + output rf_r , + output rf_sw_bpf , + output rf_sclk1 , + output rf_sdio1 , + output rf_cs1 , + input rf_ld1 , + output rf_sclk2 , + output rf_sdio2 , + output rf_cs2 , + input rf_ld2 , + output rf_sclk3 , + output rf_sdio3 , + output rf_cs3 , + input rf_ld3 , + output rf_tmgc_16 , + output rf_tmgc_8 , + output rf_tmgc_4 , + output rf_tmgc_2 , + output rf_tmgc_1 , + output rf_rmgc_16 , + output rf_rmgc_8 , + output rf_rmgc_4 , + output rf_rmgc_2 , + output rf_rmgc_1 , + output rf_enable , + output rf_sc , + output rf_sd , + output rf_endsyn , + input rf_sdout , + inout rf_dq_wd , + output rf_sw_rx +); + + +(*dont_touch = "true"*) wire vio_switch ; // 键控开关，沿有效 +(*dont_touch = "true"*) wire vio_trdirection ; // 收å‘æ–¹å‘ +(*dont_touch = "true"*) wire [15:0] vio_frequency ; // 收å‘频率 +(*dont_touch = "true"*) wire [ 7:0] vio_emitMGC ; // å‘é€MGC +(*dont_touch = "true"*) wire [ 3:0] vio_ch01MGC ; // 1通é“校准MGC +(*dont_touch = "true"*) wire [ 3:0] vio_ch02MGC ; // 2通é“校准MGC +(*dont_touch = "true"*) wire [ 3:0] vio_ch03MGC ; // 3通é“校准MGC +(*dont_touch = "true"*) wire [ 3:0] vio_ch04MGC ; // 4通é“校准MGC +(*dont_touch = "true"*) wire [ 7:0] vio_recvMGC ; // 接收MGC +(*dont_touch = "true"*) wire [ 7:0] vio_AntMod ; // å¤©çº¿å·¥ä½œæ¨¡å¼ +(*dont_touch = "true"*) wire [15:0] vio_AntOffAxis ; // 天线离轴角 +(*dont_touch = "true"*) wire [15:0] vio_AntYaw ; // 天线å航角 +(*dont_touch = "true"*) wire [15:0] vio_PrecessTime ; // 处ç†æ—¶é—´ï¼Œä»ŽEN拉低到DARY拉低 + +(*dont_touch = "true"*)wire vio_mode_ant ; // 0定频手动，1æ‰«é¢‘æ¨¡å¼ +(*dont_touch = "true"*)wire vio_hop_start ; // 0跳频终止，1é‡æ–°è·³é¢‘ +(*dont_touch = "true"*)wire vio_standby ; // 1待机模å¼ï¼Œ0å·¥ä½œæ¨¡å¼ +(*dont_touch = "true"*)wire [15:0] vio_hoptime ; // å•è·³æ—¶é—´è®¡æ•°å™¨ + +reg Ant_switch_D1 = 0; +reg data_valid = 0; +reg switch_valid = 0; +reg [95:0] RF_CtrlWord = 0; +reg [127:0] Ant_CtrlWord = 0; +reg [15:0] data_valid_countdown = 0; +reg [15:0] rst_countdown = 100; +reg [95:0] RF_CtrlWord_running = 0; +reg [127:0] Ant_CtrlWord_running = 0; +reg rst_n = 0; +reg SPI_SYN_F = 1; +reg SPI_MOSI_F = 1; +reg TP_EN_F = 0; +reg TR_MGC_F = 0; +reg CAL_F = 0; +reg PRF = 0; +wire SPI_MISO_F; +reg Ant_DATA = 0; +reg Ant_EN = 0; +reg Ant_DARY = 0; +reg Ant_TR = 0; + + + +//ç›¸æŽ§é˜µæµ‹è¯•ç¨‹åº +reg [15:0] cnt_freq_change = 16'd0; + +reg Ant_switch ; // 键控开关，沿有效 +reg [15:0] Ant_frequency; // 收å‘频率 +reg [ 7:0] Ant_mode ; // ç›¸æŽ§é˜µæ¨¡å¼ +reg [ 7:0] RF_mode ; // å°„é¢‘æ¨¡å¼ + +always @ (posedge clk_48m) begin + if(sys_rst) begin + Ant_switch <= 1'b0; + cnt_freq_change[15:0] <= 16'd0; + Ant_frequency[15:0] <= 16'd0; + RF_mode[7:0] <= 8'h10; + Ant_mode[7:0] <= 8'h0f; + end + else begin + if(vio_mode_ant) begin + if(vio_hop_start) begin + if(cnt_freq_change[15:0] == (vio_hoptime[15:0] - 16'd1)) begin + Ant_switch <= ~Ant_switch; + if(Ant_frequency[15:0] == 16'd3500) begin + Ant_frequency[15:0] <= 16'd0; + end + else begin + Ant_frequency[15:0] <= Ant_frequency[15:0] + 16'd1; + end + cnt_freq_change[15:0] <= 16'd0; + end + else begin + Ant_switch <= Ant_switch; + Ant_frequency[15:0] <= Ant_frequency[15:0]; + cnt_freq_change[15:0] <= cnt_freq_change[15:0] + 16'd1; + end + end + else begin + Ant_switch <= Ant_switch; + Ant_frequency[15:0] <= 16'd0; + cnt_freq_change[15:0] <= 16'd0; + end + end + else begin + Ant_switch <= vio_switch; + Ant_frequency[15:0] <= vio_frequency[15:0]; + cnt_freq_change[15:0] <= 16'd0; + end + + if(vio_standby) begin + RF_mode[7:0] <= 8'h10; + Ant_mode[7:0] <= 8'h0f; + end + else begin + RF_mode[7:0] <= 8'h00; + Ant_mode[7:0] <= vio_AntMod[7:0]; + end + end + +end + +always @(posedge clk_48m) + begin + Ant_switch_D1 <= Ant_switch; + if(Ant_switch_D1 != Ant_switch) + switch_valid <= 1'b1; + else + switch_valid <= 1'b0; + + if(switch_valid) + begin + RF_CtrlWord[95:88] <= 8'hAA; + RF_CtrlWord[87:80] <= RF_mode[7:0]; + RF_CtrlWord[79:64] <= Ant_frequency[15:0]; + RF_CtrlWord[63:56] <= vio_emitMGC[7:0]; + RF_CtrlWord[55:52] <= vio_ch01MGC[3:0]; + RF_CtrlWord[51:48] <= vio_ch02MGC[3:0]; + RF_CtrlWord[47:44] <= vio_ch03MGC[3:0]; + RF_CtrlWord[43:40] <= vio_ch04MGC[3:0]; + RF_CtrlWord[39:32] <= vio_recvMGC[7:0]; + RF_CtrlWord[31:8] <= 24'h00_0000; + RF_CtrlWord[7:0] <= 8'hCC; + + Ant_CtrlWord[127:120] <= 8'hAA; + Ant_CtrlWord[119:112] <= 8'h00; + Ant_CtrlWord[111:104] <= Ant_mode[7:0]; + Ant_CtrlWord[103: 88] <= vio_AntOffAxis[15:0]; + Ant_CtrlWord[ 87: 72] <= vio_AntYaw[15:0]; + Ant_CtrlWord[ 71: 56] <= Ant_frequency[15:0]; + Ant_CtrlWord[ 55: 8] <= 48'h00_00_00_00_00_00; + Ant_CtrlWord[ 7: 0] <= 8'hCC; + end + else + begin + RF_CtrlWord[95:0] <= RF_CtrlWord[95:0]; + // Ant_CtrlWord[127:0] <= Ant_CtrlWord[127:0]; + end + + if(switch_valid) + data_valid_countdown[15:0] <= vio_PrecessTime[15:0]; + else if(data_valid_countdown[15:0] != 16'd0) + data_valid_countdown[15:0] <= data_valid_countdown[15:0] - 16'd1; + + + // RF控制 + if(data_valid_countdown[15:0] == vio_PrecessTime[15:0]) + RF_CtrlWord_running[95:0] <= RF_CtrlWord[95:0]; + else + RF_CtrlWord_running[95:0] <= {RF_CtrlWord_running[94:0],1'b0}; + + if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd96 && data_valid_countdown[15:0] < vio_PrecessTime[15:0]) + begin + SPI_SYN_F <= 1'b0; + SPI_MOSI_F <= RF_CtrlWord_running[95]; + end + else + begin + SPI_SYN_F <= 1'b1; + SPI_MOSI_F <= 1'b0; + end + + + if(data_valid_countdown[15:0] <= 16'd128 && data_valid_countdown[15:0] > 16'd80) + CAL_F <= 1'b1; + else + CAL_F <= 1'b0; + + if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0) + begin + TP_EN_F <= 1'b1; + TR_MGC_F <= 1'b1; + end + else + begin + TP_EN_F <= 1'b0; + TR_MGC_F <= 1'b0; + end + + if(data_valid_countdown[15:0] == 16'd48) + PRF <= vio_trdirection; + else + PRF <= PRF; + + if(sys_rst) + rst_countdown[15:0] <= 16'd100; + else if(rst_countdown[15:0] != 0) + begin + rst_countdown[15:0] <= rst_countdown[15:0] - 16'd1; + rst_n <= 1'b0; + end + else + begin + rst_countdown[15:0] <= rst_countdown[15:0]; + rst_n <= 1'b1; + end + + // 天线控制 + if(data_valid_countdown[15:0] == vio_PrecessTime[15:0]) + Ant_CtrlWord_running[127:0] <= Ant_CtrlWord[127:0]; + else + Ant_CtrlWord_running[127:0] <= {Ant_CtrlWord_running[126:0],1'b0}; + + if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd128 && data_valid_countdown[15:0] < vio_PrecessTime[15:0]) + begin + Ant_EN <= 1'b0; + Ant_DATA <= Ant_CtrlWord_running[127]; + end + else + begin + Ant_EN <= 1'b1; + Ant_DATA <= 1'b0; + end + + if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0) + Ant_DARY <= 1'b0; + else + Ant_DARY <= 1'b1; + + if(data_valid_countdown[15:0] == 16'd48) + Ant_TR <= vio_trdirection; + else + Ant_TR <= Ant_TR; + end + + +//RF recv_data +reg [1:0] state_rfdata; +reg SPI_SYN_F_d1 = 1'b0; +reg [15:0] cnt_rfdata = 16'd0; +reg [95:0] RF_RecvWord = 96'd0; +reg [95:0] RF_RecvWord_last = 96'd0; + +reg [7:0] RF_temperature = 8'd0 ; +reg [7:0] RF_IFlocked = 8'd0 ; +reg [7:0] RF_RFAlocked = 8'd0 ; +reg [7:0] RF_RFBlocked = 8'd0 ; +reg [3:0] RF_ch1mgc = 4'd0 ; +reg [3:0] RF_ch2mgc = 4'd0 ; +reg [3:0] RF_ch3mgc = 4'd0 ; +reg [3:0] RF_ch4mgc = 4'd0 ; +reg [31:0] RF_Framecount = 32'd0 ; + +always @ (posedge clk_48m) begin + if(sys_rst) begin + state_rfdata[1:0] <= 2'd0; + SPI_SYN_F_d1 <= 1'b0; + RF_RecvWord[95:0] <= 96'd0; + cnt_rfdata[15:0] <= 16'd0; + RF_temperature[7:0] <= 8'd0 ; + RF_IFlocked[7:0] <= 8'd0 ; + RF_RFAlocked[7:0] <= 8'd0 ; + RF_RFBlocked[7:0] <= 8'd0 ; + RF_ch1mgc[3:0] <= 4'd0 ; + RF_ch2mgc[3:0] <= 4'd0 ; + RF_ch3mgc[3:0] <= 4'd0 ; + RF_ch4mgc[3:0] <= 4'd0 ; + RF_Framecount[31:0] <= 32'd0; + end + else begin + RF_RecvWord[95:0] <= {RF_RecvWord[94:0],SPI_MISO_F}; + + if (RF_RecvWord[95:88] == 8'hAA && RF_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾 + RF_temperature[7:0] <= RF_RecvWord[87:80]; + RF_IFlocked[7:0] <= RF_RecvWord[79:72]; + RF_RFAlocked[7:0] <= RF_RecvWord[71:64]; + RF_RFBlocked[7:0] <= RF_RecvWord[63:56]; + RF_ch1mgc[3:0] <= RF_RecvWord[55:52]; + RF_ch2mgc[3:0] <= RF_RecvWord[51:48]; + RF_ch3mgc[3:0] <= RF_RecvWord[47:44]; + RF_ch4mgc[3:0] <= RF_RecvWord[43:40]; + RF_Framecount[31:0] <= RF_RecvWord[39:8]; + RF_RecvWord_last <= RF_RecvWord; + end + else begin // hold otherwise + RF_temperature[7:0] <= RF_temperature[7:0]; + RF_IFlocked[7:0] <= RF_IFlocked[7:0] ; + RF_RFAlocked[7:0] <= RF_RFAlocked[7:0] ; + RF_RFBlocked[7:0] <= RF_RFBlocked[7:0] ; + RF_ch1mgc[3:0] <= RF_ch1mgc[3:0] ; + RF_ch2mgc[3:0] <= RF_ch2mgc[3:0] ; + RF_ch3mgc[3:0] <= RF_ch3mgc[3:0] ; + RF_ch4mgc[3:0] <= RF_ch4mgc[3:0] ; + RF_Framecount[31:0] <= RF_Framecount[31:0]; + RF_RecvWord_last <= RF_RecvWord_last; + end + end +end +// å¤©çº¿çš„è¾“å‡ºæ—¶é’Ÿè½¬æ¢ +reg Ant_dclk_96m = 1; +wire [3:0] fifo_wr_din, fifo_rd_dout; +wire fifo_full, fifo_empty; +reg Ant_EN_96m = 0; +reg Ant_DATA_96m = 0; +reg Ant_DARY_96m = 1; +reg Ant_TR_96m = 0; +assign fifo_wr_din[3] = Ant_EN; +assign fifo_wr_din[2] = Ant_DATA; +assign fifo_wr_din[1] = Ant_DARY; +assign fifo_wr_din[0] = Ant_TR; +reg fifo_rd_en = 0; +reg fifo_rst = 0; +reg [8:0] Ant_clk_countdown = 0; +always @(posedge clk_96m) + begin + fifo_rst <= sys_rst; + + fifo_rd_en <= (fifo_rst == 1'b1)? 1'b0:!fifo_rd_en; + + if(fifo_rd_en) + {Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= fifo_rd_dout[3:0]; + else + {Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= {Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m}; + + if(fifo_rd_en && Ant_EN_96m && !fifo_rd_dout[3]) + Ant_clk_countdown[8:0] <= 9'd276; + else if(Ant_clk_countdown[8:0] != 9'd0) + Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0] - 9'd1; + else + Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0]; + end +assign ant_clk = !Ant_clk_countdown[0]; +assign ant_en = Ant_EN_96m; +assign ant_data = Ant_DATA_96m; +assign ant_tr = Ant_TR_96m; +assign ant_dary = Ant_DARY_96m; + +fifo_AntCtrl fifo_AntCtrl +( + .rst (fifo_rst ), // input wire rst + .wr_clk (clk_48m ), // input wire wr_clk + .rd_clk (clk_96m ), // input wire rd_clk + .din (fifo_wr_din[3:0] ), // input wire [3 : 0] din + .wr_en (!fifo_rst ), // input wire wr_en + .rd_en (fifo_rd_en ), // input wire rd_en + .dout (fifo_rd_dout[3:0] ), // output wire [3 : 0] dout + .full (fifo_full ), // output wire full + .empty (fifo_empty ) // output wire empty +); +//Ant recv_data +reg [1:0] state_antdata; +reg Ant_EN_96m_d1 = 1'b0; +reg [15:0] cnt_antdata = 16'd0; +reg [127:0] Ant_RecvWord = 128'b0; +reg [127:0] Ant_RecvWord_last = 128'b0; + +reg [7:0] Ant_Ant_Volt = 8'd0 ; +reg [7:0] Ant_RF_Volt = 8'd0 ; +reg [7:0] Ant_IF_Volt = 8'd0 ; +reg [7:0] Ant_state = 8'd0 ; +reg [31:0] Ant_Framecount = 32'd0 ; + +always @ (posedge clk_96m) begin + if(sys_rst) begin + state_antdata[1:0] <= 2'd0; + Ant_EN_96m_d1 <= 1'b0; + Ant_RecvWord[127:0] <= 128'd0; + cnt_antdata[15:0] <= 16'd0; + Ant_Ant_Volt[7:0] <= 8'd0 ; + Ant_RF_Volt[7:0] <= 8'd0 ; + Ant_IF_Volt[7:0] <= 8'd0 ; + Ant_state[7:0] <= 8'd0 ; + Ant_Framecount[31:0] <= 32'd0; + Ant_RecvWord_last[127:0] <= 128'd0; + end + else begin + if(!ant_clk) begin + Ant_RecvWord[127:0] <= {Ant_RecvWord[126:0],ant_dout}; + end + else begin + Ant_RecvWord[127:0] <= Ant_RecvWord[127:0]; + end + + if(Ant_RecvWord[127:120] == 8'hAA && Ant_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾 + Ant_Ant_Volt[7:0] <= Ant_RecvWord[119:112]; + Ant_RF_Volt[7:0] <= Ant_RecvWord[111:104]; + Ant_IF_Volt[7:0] <= Ant_RecvWord[103:96]; + Ant_state[7:0] <= Ant_RecvWord[47:40]; + Ant_Framecount[31:0] <= Ant_RecvWord[39:8] ; + Ant_RecvWord_last[127:0] <= Ant_RecvWord[127:0]; + end + else begin // hold otherwise + Ant_Ant_Volt[7:0] <= Ant_Ant_Volt[7:0] ; + Ant_RF_Volt[7:0] <= Ant_RF_Volt[7:0] ; + Ant_IF_Volt[7:0] <= Ant_IF_Volt[7:0] ; + Ant_state[7:0] <= Ant_state[7:0] ; + Ant_Framecount[31:0] <= Ant_Framecount[31:0] ; + Ant_RecvWord_last[127:0] <= Ant_RecvWord_last[127:0]; + end + end + +end +Sisyif uut( + .clk_40m(clk_32m), + .clk_20m(clk_19p2m), + .SPI_CLK_F(clk_48m), + .rst_n(rst_n), + .SPI_SYN_F(SPI_SYN_F), + .SPI_MOSI_F(SPI_MOSI_F), + .SPI_MISO_F(SPI_MISO_F), + .TP_EN_F(TP_EN_F), + .TR_MGC_F(TR_MGC_F), + .CAL_F(CAL_F), + .PRF(PRF), + .standby(rf_standby), + .SW_PLL(rf_sw_pll), + .T(rf_t), + .R(rf_r), + .SW_BPF(rf_sw_bpf), + .SCLK1(rf_sclk1), + .SDIO1(rf_sdio1), + .CS1(rf_cs1), + .LD1(rf_ld1), + .SCLK2(rf_sclk2), + .SDIO2(rf_sdio2), + .CS2(rf_cs2), + .LD2(rf_ld2), + .SCLK3(rf_sclk3), + .SDIO3(rf_sdio3), + .CS3(rf_cs3), + .LD3(rf_ld3), + .TMGC_16db(rf_tmgc_16), + .TMGC_8db(rf_tmgc_8), + .TMGC_4db(rf_tmgc_4), + .TMGC_2db(rf_tmgc_2), + .TMGC_1db(rf_tmgc_1), + .RMGC_16db(rf_rmgc_16), + .RMGC_8db(rf_rmgc_8), + .RMGC_4db(rf_rmgc_4), + .RMGC_2db(rf_rmgc_2), + .RMGC_1db(rf_rmgc_1), + .ENABLE(rf_enable), + .SC(rf_sc), + .SD(rf_sd), + .END_SYN(rf_endsyn), + .SDOUT(rf_sdout), + .DQ_WD(rf_dq_wd), + .SW_RX(rf_sw_rx) + ); + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/hdwr/clk_dist.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/hdwr/clk_dist.v new file mode 100644 index 0000000..8dfb48e --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/hdwr/clk_dist.v @@ -0,0 +1,133 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/01 11:15:25 +// Design Name: +// Module Name: clk_dist +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Clock distribution module +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module clk_dist +( + // input clocks + input clk_250m_p , // generated by ad9516, 250mhz + input clk_250m_n , + input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz + input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz + + // output clocks & reset + // global reset + output sys_rst , // global reset signal, active high + output ant_rst , // phased-array & rf control reset signal, active high + + // pl signal processing clock + output sys_clk , // 41.6667mhz + output sys_clk_2x , // 83.3333mhz + output sys_clk_3x , // 125mhz + output sys_clk_4x , // 166.6667mhz + output sys_clk_ld , // system main clock locked indicator + + // ad9361-1 clocks + output ad9361_1_clk , // 41.6667mhz + output ad9361_1_clk_2x , // 83.3333mhz + output ad9361_1_clk_3x , // 125mhz + output ad9361_1_clk_4x , // 166.6667mhz + output ad9361_1_clk_ld , // ad9361-1 clock group locked indicator + + // ad9361-2 clocks + output ad9361_2_clk , // 41.6667mhz + output ad9361_2_clk_2x , // 83.3333mhz + output ad9361_2_clk_3x , // 125mhz + output ad9361_2_clk_4x , // 166.6667mhz + output ad9361_2_clk_ld , // ad9361-2 clock group locked indicator + + // phased-array & rf control clocks + output clk_96m , + output clk_48m , + output clk_32m , + output clk_19p2m +); + +assign sys_clk = ad9361_1_clk ; +assign sys_clk_2x = ad9361_1_clk_2x; +assign sys_clk_3x = ad9361_1_clk_3x; +assign sys_clk_4x = ad9361_1_clk_4x; +assign sys_clk_ld = ad9361_1_clk_ld; + +assign sys_rst = ~sys_clk_ld; + +ad9361_clk_gen_cmos_2t2r u_ad9361_1_clk_gen +( + // Clock out ports + .clk_out1 (ad9361_1_clk ), // output clk_out1 + .clk_out2 (ad9361_1_clk_2x ), // output clk_out2 + .clk_out3 (ad9361_1_clk_3x ), // output clk_out3 + .clk_out4 (ad9361_1_clk_4x ), // output clk_out4 + // Status and control signals + .locked (ad9361_1_clk_ld ), // output locked + // Clock in ports + .clk_in1 (ad9361_1_rx_data_clk ) // input clk_in1 +); + +ad9361_clk_gen_cmos_2t2r u_ad9361_2_clk_gen +( + // Clock out ports + .clk_out1 (ad9361_2_clk ), // output clk_out1 + .clk_out2 (ad9361_2_clk_2x ), // output clk_out2 + .clk_out3 (ad9361_2_clk_3x ), // output clk_out3 + .clk_out4 (ad9361_2_clk_4x ), // output clk_out4 + // Status and control signals + .locked (ad9361_2_clk_ld ), // output locked + // Clock in ports + .clk_in1 (ad9361_2_rx_data_clk ) // input clk_in1 +); + +wire ant_clk_stg1_96m; +wire ant_clk_stg1_ld; +wire ant_clk_stg2_ld; + +assign ant_rst = ~ant_clk_stg2_ld; + +ant_clk_gen_stg1 u_ant_clk_gen_stg1 +( + // Clock out ports + .clk_out1 (ant_clk_stg1_96m ), // output clk_out1 + // Status and control signals + .locked (ant_clk_stg1_ld ), // output locked + // Clock in ports + .clk_in1_p (clk_250m_p ), // input clk_in1_p + .clk_in1_n (clk_250m_n ) // input clk_in1_n +); + +ant_clk_gen_stg2 u_ant_clk_gen_stg2 +( + // Clock out ports + .clk_out1 (clk_96m ), // output clk_out1 + .clk_out2 (clk_48m ), // output clk_out2 + .clk_out3 (clk_32m ), // output clk_out3 + .clk_out4 (clk_19p2m ), // output clk_out4 + // Status and control signals + .locked (ant_clk_stg2_ld ), // output locked + // Clock in ports + .clk_in1 (ant_clk_stg1_96m ) // input clk_in1 +); + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/accor_mat_formatting.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/accor_mat_formatting.v new file mode 100644 index 0000000..661cee0 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/accor_mat_formatting.v @@ -0,0 +1,426 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/06 15:24:48 +// Design Name: +// Module Name: accor_mat_formatting +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Formmat the input complex matrix to 1-bit stream. +// Parameter: +// ROW_NUM: Row number of input matrix. +// COL_NUM: Column number of input matrix. +// DATA_I_WIDTH: Bit width of input matrix element. +// FRAME_HEAD: Frame head indicate autocorrelation matrix frame. +// Data format: +// din_valid: Indicate [din_real/imag] data are valid. +// din_real/imag: Suppose the input matrix x = [x11 x12; x21 x22], then +// din_real = {Re{x22}, Re{x21}, Re{x12}, Re{x11}} +// din_imag = {Im{x22}, Im{x21}, Im{x12}, Im{x11}} +// dout_valid: Indicate [dout_data] is valid. The latency is set to 2 clock +// cycles by default. +// dout_data: +// dout_data = {FRAME_HEAD[msb], ..., FRAME_HEAD[lsb], FRAME_LEN[msb], +// ..., FRAME_LEN[lsb], Re{x11}[msb], ..., Re{x11}[lsb], Im{x11}[msb], ..., +// Im{x11}[lsb], ..., Re{x12}[msb], ......, Im{x22}[lsb]} +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module accor_mat_formatting +#( + parameter ROW_NUM = 4, + parameter COL_NUM = 4, + parameter DATA_I_WIDTH = 32, + parameter FRAME_HEAD = 32'h7E7E7E7E +) +( + // clock & reset + input sys_clk, + input sys_rst, + input clk_96m, + input ant_rst, + + // input data + input din_valid, + input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1 : 0] din_real, + input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1 : 0] din_imag, + input fifo_cdc_rst, + + // output data + output dout_valid, + output dout_data +); + +localparam CMPLX_DIM = 2; +localparam FRAME_LEN = ROW_NUM*COL_NUM*CMPLX_DIM; // 32-bit data number per frame +localparam BYTE_LEN = 4 * (ROW_NUM*COL_NUM*CMPLX_DIM + 2); // byte number per frame, plus frame head and frame length + +// available state +localparam STATE_NUM = 4; +localparam STATE_IDLE = 0; +localparam STATE_HEAD = 1; +localparam STATE_LEN = 2; +localparam STATE_DATA = 3; + +genvar i; +integer m; + +// format input data to array +wire [DATA_I_WIDTH-1 : 0] din_array [0 : ROW_NUM*COL_NUM*CMPLX_DIM-1]; +reg [DATA_I_WIDTH-1 : 0] din_array_cdc [0 : ROW_NUM*COL_NUM*CMPLX_DIM-1]; + +generate +for (i = 0; i < ROW_NUM*COL_NUM; i = i + 1) begin: input_mat_reshape + assign din_array[i*2] = din_real[i*DATA_I_WIDTH +: DATA_I_WIDTH]; + assign din_array[i*2+1] = din_imag[i*DATA_I_WIDTH +: DATA_I_WIDTH]; +end +endgenerate + +// clock domain crossing fifo, write channel +reg fifo_wr_start = 'b0; +reg fifo_wr_en = 'b0; +reg [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_wr_cnt = 'b0; +reg [DATA_I_WIDTH-1 : 0] fifo_din = 'b0; + +always @(posedge sys_clk) begin + if (sys_rst) begin + fifo_wr_start <= 'b0; + end + else if (din_valid) begin + fifo_wr_start <= 1'b1; + end + else if (fifo_wr_cnt == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin + fifo_wr_start <= 1'b0; + end + else begin + fifo_wr_start <= fifo_wr_start; + end +end + +always @(posedge sys_clk) begin + if (sys_rst) begin + fifo_wr_en <= 'b0; + fifo_wr_cnt <= 'b0; + fifo_din <= 'b0; + end + else if (fifo_wr_start) begin + fifo_wr_en <= 1'b1; + fifo_wr_cnt <= fifo_wr_cnt + 1'b1; + fifo_din <= din_array[fifo_wr_cnt]; + end + else begin + fifo_wr_en <= 'b0; + fifo_wr_cnt <= 'b0; + fifo_din <= 'b0; + end +end + +// clock domain crossing fifo, read channel +reg fifo_rd_en = 'b0; +reg fifo_rd_en_d1 = 'b0; +reg [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt = 'b0; +reg [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt_d1 = 'b0; // read data latency +reg fifo_rd_valid = 'b0; +wire [DATA_I_WIDTH-1 : 0] fifo_dout; +wire [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM*2)-1 : 0] fifo_rd_num; +wire fifo_full; +wire fifo_empty; + +always @(posedge clk_96m) begin + if (ant_rst) begin + fifo_rd_en <= 'b0; + end + else if (fifo_rd_num == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin + fifo_rd_en <= 1'b1; + end + else if (fifo_rd_cnt == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin + fifo_rd_en <= 'b0; + end + else begin + fifo_rd_en <= fifo_rd_en; + end +end + +always @(posedge clk_96m) begin + if (ant_rst) begin + fifo_rd_en_d1 <= 'b0; + end + else begin + fifo_rd_en_d1 <= fifo_rd_en; + end +end + +always @(posedge clk_96m) begin + if (ant_rst) begin + fifo_rd_cnt <= 'b0; + end + else if (fifo_rd_en) begin + fifo_rd_cnt <= fifo_rd_cnt + 1'b1; + end + else begin + fifo_rd_cnt <= 'b0; + end +end + +always @(posedge clk_96m) begin + if (ant_rst) begin + fifo_rd_cnt_d1 <= 'b0; + end + else begin + fifo_rd_cnt_d1 <= fifo_rd_cnt; + end +end + +always @(posedge clk_96m) begin + if (ant_rst) begin + fifo_rd_valid <= 'b0; + end + else if (fifo_rd_cnt_d1 == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin + fifo_rd_valid <= 1'b1; + end + else begin + fifo_rd_valid <= 'b0; + end +end + +always @(posedge clk_96m) begin + if (ant_rst) begin + for (m = 0; m < ROW_NUM*COL_NUM*CMPLX_DIM; m = m + 1) begin + din_array_cdc[m] <= 'b0; + end + end + else if (fifo_rd_en_d1) begin + din_array_cdc[fifo_rd_cnt_d1] <= fifo_dout; + end + else begin + for (m = 0; m < ROW_NUM*COL_NUM*CMPLX_DIM; m = m + 1) begin + din_array_cdc[m] <= din_array_cdc[m]; + end + end +end + +// clock domain crossing fifo, interface +fifo_accor_cdc u_fifo_accor_cdc +( + .rst (fifo_cdc_rst ), // input wire wr_rst + .wr_clk (sys_clk ), // input wire wr_clk + .rd_clk (clk_96m ), // input wire rd_clk + .din (fifo_din ), // input wire [31 : 0] din + .wr_en (fifo_wr_en ), // input wire wr_en + .rd_en (fifo_rd_en ), // input wire rd_en + .dout (fifo_dout ), // output wire [31 : 0] dout + .full (fifo_full ), // output wire full + .empty (fifo_empty ), // output wire empty + .rd_data_count (fifo_rd_num ) // output wire [5 : 0] rd_data_count +); + +// center state machine & counter +reg [$clog2(STATE_NUM)-1 : 0] state = STATE_IDLE; +reg [$clog2(DATA_I_WIDTH)-1 : 0] bit_cnt = 'b0; // bit counter within one frame +reg [$clog2(FRAME_LEN)-1 : 0] frame_cnt = 'b0; // frame counter + +always @(posedge clk_96m) begin + if (ant_rst) begin + state <= STATE_IDLE; + end + else begin + case (state) + STATE_IDLE: state <= fifo_rd_valid ? STATE_HEAD : STATE_IDLE; + STATE_HEAD: state <= (bit_cnt == DATA_I_WIDTH-1) ? STATE_LEN : STATE_HEAD; + STATE_LEN : state <= (bit_cnt == DATA_I_WIDTH-1) ? STATE_DATA : STATE_LEN; + STATE_DATA: state <= (frame_cnt == FRAME_LEN-1 && bit_cnt == DATA_I_WIDTH-1) ? STATE_IDLE : STATE_DATA; + default: state <= STATE_IDLE; + endcase + end +end + +always @(posedge clk_96m) begin + if (ant_rst) begin + bit_cnt <= 'b0; + end + else if (state == STATE_IDLE) begin + bit_cnt <= 'b0; + end + else begin + bit_cnt <= (bit_cnt == DATA_I_WIDTH-1) ? 'b0 : bit_cnt + 1'b1; + end +end + +always @(posedge clk_96m) begin + if (ant_rst) begin + frame_cnt <= 'b0; + end + else if (state == STATE_IDLE) begin + frame_cnt <= 'b0; + end + else if (state == STATE_DATA && bit_cnt == DATA_I_WIDTH-1) begin + frame_cnt <= frame_cnt + 1'b1; + end + else begin + frame_cnt <= frame_cnt; + end +end + + +// output data +reg dout_valid_buf = 'b0; +reg dout_data_buf = 'b0; + +assign dout_valid = dout_valid_buf; +assign dout_data = dout_data_buf; + +always @(posedge clk_96m) begin + if (ant_rst) begin + dout_valid_buf <= 'b0; + dout_data_buf <= 'b0; + end + else case (state) + STATE_IDLE: begin dout_valid_buf <= 'b0 ; dout_data_buf <= 'b0; end + STATE_HEAD: begin dout_valid_buf <= 1'b1; dout_data_buf <= FRAME_HEAD[DATA_I_WIDTH-1 - bit_cnt]; end + STATE_LEN : begin dout_valid_buf <= 1'b1; dout_data_buf <= BYTE_LEN[DATA_I_WIDTH-1 - bit_cnt]; end + STATE_DATA: begin dout_valid_buf <= 1'b1; dout_data_buf <= din_array_cdc[frame_cnt][DATA_I_WIDTH-1 - bit_cnt]; end + default: begin dout_valid_buf <= 'b0 ; dout_data_buf <= 'b0; end + endcase +end + +endmodule + + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/10/30 20:46:26 +// Design Name: +// Module Name: tb_accum +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Testbench for [accor_mat_formatting] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// ------------------------------- +// MATLAB Code for data generation +// ------------------------------- +// COLUMN_NUM = 4; +// DATA_I_WIDTH = 12; +// ACC_NUM = 10; + +// rng(0); +// data = rand(4,2)*2-1; +// d_12b = round(data.*(2^(DATA_I_WIDTH-1)-1)); +// d_12b_cmplx = d_12b(:,1) + 1i*d_12b(:,2); +// d_12b_cmplx = d_12b_cmplx(end:-1:1,:); +// d_12b_acorr = d_12b_cmplx*d_12b_cmplx'; +// d_12b_acorr_real_sim = reshape(flip(reshape(real(d_12b_acorr)',1,16)),4,4); +// d_12b_acorr_imag_sim = reshape(flip(reshape(imag(d_12b_acorr)',1,16)),4,4); +// d_12b_acorr_real_sim_sum = ACC_NUM*d_12b_acorr_real_sim; +// d_12b_acorr_imag_sim_sum = ACC_NUM*d_12b_acorr_imag_sim; + + +// module tb_accor_format; + +// localparam DATA_I_WIDTH = 32; +// localparam ROW_NUM = 4; +// localparam COL_NUM = 4; + +// reg sys_clk = 1'b1; +// reg sys_rst = 1'b1; +// reg clk_96m = 1'b1; +// reg ant_rst = 1'b1; +// reg din_valid = 'b0; +// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0; + +// wire dout_valid; +// wire dout_data; + +// accor_mat_formatting #( +// .ROW_NUM (ROW_NUM), +// .COL_NUM (COL_NUM), +// .DATA_I_WIDTH (DATA_I_WIDTH) +// ) u_accor_mat_formatting +// ( +// // clock & reset +// .sys_clk (sys_clk ), // input sys_clk +// .sys_rst (sys_rst ), // input sys_rst +// .clk_96m (clk_96m ), // input clk_96m +// .ant_rst (ant_rst ), // input ant_rst + +// // input data +// .din_valid (din_valid ), +// .din_real (din_real ), +// .din_imag (din_imag ), + +// // output data +// .dout_valid (dout_valid ), +// .dout_data (dout_data ) +// ); + + +// initial begin +// #102 +// sys_rst = 1'b0; +// ant_rst = 1'b0; + +// #222; +// @(posedge sys_clk) +// din_valid = 1'b1; +// din_real = { +// 32'd1952708, 32'd1246152, -32'd2458370, 32'd2283360, +// 32'd1246152, 32'd5474825, -32'd1041611, 32'd2493996, +// -32'd2458370, -32'd1041611, 32'd3154378, -32'd2757828, +// 32'd2283360, 32'd2493996, -32'd2757828, 32'd2899728 +// }; + +// din_imag = { +// 32'd1, -32'd3022886, -32'd340582, -32'd669768, +// 32'd3022886, 32'd2, -32'd4023023, 32'd3107328, +// 32'd340582, 32'd4023023, 32'd3, 32'd1241460, +// 32'd669768, -32'd3107328, -32'd1241460, 32'd4 +// }; + +// @(posedge sys_clk) +// din_valid = 1'b0; + +// end + +// always begin +// #20 sys_clk = ~sys_clk; +// end + +// always begin +// #7; +// clk_96m = ~clk_96m; +// #3; +// end + + +// endmodule \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/accum_cmplx_mat.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/accum_cmplx_mat.v new file mode 100644 index 0000000..7cb0fff --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/accum_cmplx_mat.v @@ -0,0 +1,365 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/02 11:06:43 +// Design Name: +// Module Name: accum_cmplx_mat +// Project Name: +// Target Devices: +// Tool Versions: 2019.1.3 +// Description: Compute the accumulation of complex matrices. The parameters are +// fully adjustable. +// Parameter: +// ROW_NUM: Row number of input matrix. +// COL_NUM: Column number of input matrix. +// ACC_NUM: Accumulation number of input matrix. +// DATA_I_WIDTH: Bit width of input matrix element. +// DATA_O_WIDTH: Bit width of output matrix element. If [DATA_O_WIDTH] <= +// [ACC_WIDTH], MSB of accumulation result will be truncated, or zeros will +// be appended. +// ACC_WIDTH (local): Accumulation adder output data width, determined by +// [DATA_I_WIDTH] and [ACC_NUM]. +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// 20230717-1552 - 修改程åºä½¿å¾—å¿«æ‹æ•°å¯ä»¥å¤§äºŽ 256，具体修改有：1. 将累加ä½å®½ +// 改为内部å‚æ•°ï¼›2. 移除加法器，å˜ä¸ºæ‰‹å†™åŠ æ³•ï¼›3. 修改 Generate 结构，always +// å—中ä¸åº”出现 generate å—。 +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module accum_cmplx_mat +#( + parameter ROW_NUM = 4, + parameter COL_NUM = 4, + parameter ACC_NUM = 256, + parameter DATA_I_WIDTH = 24, + parameter DATA_O_WIDTH = 32 +) +( + // clock & reset + input clk, + input rst, + input acc_rst, // [acc_rst] should assert before accumulation starts + + // input data + input din_valid, + input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real, + input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_imag, + + // output data + output dout_valid, + output [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, + output [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_imag +); + +localparam ACC_WIDTH = $clog2(ACC_NUM) + DATA_I_WIDTH; + +integer i; +genvar m; + +// prepare adder input & output data +wire signed [DATA_I_WIDTH-1:0] din_real_array [0:ROW_NUM*COL_NUM-1]; +wire signed [DATA_I_WIDTH-1:0] din_imag_array [0:ROW_NUM*COL_NUM-1]; + +for (m = 0; m < ROW_NUM*COL_NUM; m = m + 1) begin: array_conversion + // Array split + assign din_real_array[m] = din_real[m*DATA_I_WIDTH +: DATA_I_WIDTH]; + assign din_imag_array[m] = din_imag[m*DATA_I_WIDTH +: DATA_I_WIDTH]; +end + +// accumulation counter +reg [$clog2(ACC_NUM)-1:0] accum_cnt = 'b0; +reg accum_full_flag = 'b0; +reg accum_full_flag_d = 'b0; + +// accumulation +reg signed [ACC_WIDTH-1:0] acc_real_array [0:ROW_NUM*COL_NUM-1]; +reg signed [ACC_WIDTH-1:0] acc_imag_array [0:ROW_NUM*COL_NUM-1]; + +if (ACC_NUM > 1) begin + // accumulation counter + always @(posedge clk) begin + if (rst || acc_rst) begin + accum_cnt <= 'b0; + end + else if (din_valid) begin + accum_cnt <= accum_cnt + 1'b1; + end + else begin + accum_cnt <= accum_cnt; + end + end + + always @(posedge clk) begin + if (rst || acc_rst) begin + accum_full_flag <= 'b0; + end + else begin + accum_full_flag <= (accum_cnt == ACC_NUM - 1) ? 1'b1 : accum_full_flag; + end + + accum_full_flag_d <= accum_full_flag; + end + + // accumulation + for (m = 0; m < ROW_NUM*COL_NUM; m = m + 1) begin: accumulation + always @(posedge clk) begin + if (rst || acc_rst) begin + acc_real_array[m] <= 'b0; + acc_imag_array[m] <= 'b0; + end + else if (din_valid && ~accum_full_flag) begin + acc_real_array[m] <= acc_real_array[m] + din_real_array[m]; + acc_imag_array[m] <= acc_imag_array[m] + din_imag_array[m]; + end + else begin + acc_real_array[m] <= acc_real_array[m]; + acc_imag_array[m] <= acc_imag_array[m]; + end + end + end +end + +// output control +reg dout_valid_buf; +reg [DATA_O_WIDTH-1:0] dout_real_array [0:ROW_NUM*COL_NUM-1]; +reg [DATA_O_WIDTH-1:0] dout_imag_array [0:ROW_NUM*COL_NUM-1]; + +assign dout_valid = dout_valid_buf; + +if (ACC_NUM > 1) begin + always @(posedge clk) begin + if (rst || acc_rst) begin + dout_valid_buf <= 'b0; + end + else begin + dout_valid_buf <= ~accum_full_flag_d & accum_full_flag; + end + end +end +else begin + always @(posedge clk) begin + if (rst || acc_rst) begin + dout_valid_buf <= 'b0; + end + else begin + dout_valid_buf <= din_valid; + end + end +end + +for (m = 0; m < ROW_NUM*COL_NUM; m = m + 1) begin: output_data + if (ACC_NUM > 1) begin + if (DATA_O_WIDTH <= ACC_WIDTH) begin + // truncate msb + always @(posedge clk) begin + if (rst || acc_rst) begin + dout_real_array[m] <= 'b0; + dout_imag_array[m] <= 'b0; + end + else if (~accum_full_flag_d & accum_full_flag) begin + dout_real_array[m] <= acc_real_array[m][ACC_WIDTH-1 -: DATA_O_WIDTH]; + dout_imag_array[m] <= acc_imag_array[m][ACC_WIDTH-1 -: DATA_O_WIDTH]; + end + else begin + dout_real_array[m] <= dout_real_array[m]; + dout_imag_array[m] <= dout_imag_array[m]; + end + end + end + else begin // if (DATA_O_WIDTH > ACC_WIDTH) + // append zeros to fit output data width + always @(posedge clk) begin + if (rst || acc_rst) begin + dout_real_array[m] <= 'b0; + dout_imag_array[m] <= 'b0; + end + else if (~accum_full_flag_d & accum_full_flag) begin + dout_real_array[m] <= {acc_real_array[m],{(DATA_O_WIDTH-ACC_WIDTH){1'b0}}}; + dout_imag_array[m] <= {acc_imag_array[m],{(DATA_O_WIDTH-ACC_WIDTH){1'b0}}}; + end + else begin + dout_real_array[m] <= dout_real_array[m]; + dout_imag_array[m] <= dout_imag_array[m]; + end + end + end + end + else begin + if (DATA_O_WIDTH <= DATA_I_WIDTH) begin + // truncate msb + always @(posedge clk) begin + if (rst || acc_rst) begin + dout_real_array[m] <= 'b0; + dout_imag_array[m] <= 'b0; + end + else if (din_valid) begin + dout_real_array[m] <= din_real_array[m][DATA_I_WIDTH-1 -: DATA_O_WIDTH]; + dout_imag_array[m] <= din_imag_array[m][DATA_I_WIDTH-1 -: DATA_O_WIDTH]; + end + else begin + dout_real_array[m] <= dout_real_array[m]; + dout_imag_array[m] <= dout_imag_array[m]; + end + end + end + else begin // if (DATA_O_WIDTH > DATA_I_WIDTH) + // append zeros to fit output data width + always @(posedge clk) begin + if (rst || acc_rst) begin + dout_real_array[m] <= 'b0; + dout_imag_array[m] <= 'b0; + end + else if (din_valid) begin + dout_real_array[m] <= {din_real_array[m],{(DATA_O_WIDTH-DATA_I_WIDTH){1'b0}}}; + dout_imag_array[m] <= {din_imag_array[m],{(DATA_O_WIDTH-DATA_I_WIDTH){1'b0}}}; + end + else begin + dout_real_array[m] <= dout_real_array[m]; + dout_imag_array[m] <= dout_imag_array[m]; + end + end + end + end +end + +// output mapping +for (m = 0; m < ROW_NUM*COL_NUM; m = m + 1) begin: output_mapping + assign dout_real[m*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_real_array[m]; + assign dout_imag[m*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_imag_array[m]; +end + +endmodule + + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/10/30 20:46:26 +// Design Name: +// Module Name: tb_accum +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Testbench for [accum_cmplx_mat] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// ------------------------------- +// MATLAB Code for data generation +// ------------------------------- +// COLUMN_NUM = 4; +// DATA_I_WIDTH = 12; +// ACC_NUM = 10; + +// rng(0); +// data = rand(4,2)*2-1; +// d_12b = round(data.*(2^(DATA_I_WIDTH-1)-1)); +// d_12b_cmplx = d_12b(:,1) + 1i*d_12b(:,2); +// d_12b_cmplx = d_12b_cmplx(end:-1:1,:); +// d_12b_acorr = d_12b_cmplx*d_12b_cmplx'; +// d_12b_acorr_real_sim = reshape(flip(reshape(real(d_12b_acorr)',1,16)),4,4); +// d_12b_acorr_imag_sim = reshape(flip(reshape(imag(d_12b_acorr)',1,16)),4,4); +// d_12b_acorr_real_sim_sum = ACC_NUM*d_12b_acorr_real_sim; +// d_12b_acorr_imag_sim_sum = ACC_NUM*d_12b_acorr_imag_sim; + + +// module tb_accum; + +// localparam DATA_I_WIDTH = 24; +// localparam ACC_WIDTH = 32; +// localparam DATA_O_WIDTH = 35; +// localparam ROW_NUM = 4; +// localparam COL_NUM = 4; + +// reg acc_rst = 1'b0; + +// reg clk = 1'b1; +// reg rst = 1'b1; +// reg din_valid = 'b0; +// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0; + +// wire dout_valid; +// wire [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag; + +// accum_cmplx_mat #( +// .ROW_NUM (ROW_NUM), +// .COL_NUM (COL_NUM), +// .DATA_I_WIDTH (DATA_I_WIDTH), +// .ACC_WIDTH (ACC_WIDTH), +// .DATA_O_WIDTH (DATA_O_WIDTH), +// .ACC_NUM (1) +// ) u_accum_cmplx_mat +// ( +// // clock & reset +// .clk (clk ), +// .rst (rst ), +// .acc_rst (acc_rst ), // [acc_rst] should assert before accumulation starts + +// // input data +// .din_valid (din_valid ), +// .din_real (din_real ), +// .din_imag (din_imag ), + +// // output data +// .dout_valid (dout_valid ), +// .dout_real (dout_real ), +// .dout_imag (dout_imag ) +// ); + + +// initial begin +// #102 rst = 1'b0; +// #222; +// @(posedge clk) +// din_valid = 1'b1; +// din_real = { +// 24'd1952708, 24'd1246152, -24'd2458370, 24'd2283360, +// 24'd1246152, 24'd5474825, -24'd1041611, 24'd2493996, +// -24'd2458370, -24'd1041611, 24'd3154378, -24'd2757828, +// 24'd2283360, 24'd2493996, -24'd2757828, 24'd2899728 +// }; + +// din_imag = { +// 24'd0, -24'd3022886, -24'd340582, -24'd669768, +// 24'd3022886, 24'd0, -24'd4023023, 24'd3107328, +// 24'd340582, 24'd4023023, 24'd0, 24'd1241460, +// 24'd669768, -24'd3107328, -24'd1241460, 24'd0 +// }; + +// #1002 +// acc_rst = 1'b1; +// #20 +// acc_rst = 1'b0; + +// end + +// always #10 clk = ~clk; + + +// endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/acorr_cmplx_col_vec.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/acorr_cmplx_col_vec.v new file mode 100644 index 0000000..e611222 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/acorr_cmplx_col_vec.v @@ -0,0 +1,283 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/10/30 19:27:01 +// Design Name: +// Module Name: acorr_cmplx_col_vec +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Compute the autocorrelation of a complex column vector. The +// computation is conducted in fully parallel style. +// Parameter: +// DATA_I_WIDTH: Width of input vector element, the same as of complex +// multiplication input data. +// CMPY_P_FULL_WIDTH (local): Width of unsigned complex multiplication +// output data (The cmpy LogiCore IP does not care whether the input data +// are signed or unsigned), which equals to (2*[DATA_MULT_WIDTH]+1). +// CMPY_P_VALID_WIDTH (local): Width of signed complex multiplication, which +// equals to 2*[DATA_MULT_WIDTH]. +// DATA_O_WIDTH: Width of output matrix element. If [DATA_O_WIDTH] <= +// [DATA_MULT_WIDTH], MSB of valid complex multiplication output will be +// truncated; or zeros will be appended. +// Data format: +// din_valid: Indicate [din_real/imag] data are valid. +// din_real/imag: Suppose the input column vector x = [x1 x2 x3 x4]^T, then +// din_real = {Re{x4}, Re{x3}, Re{x2}, Re{x1}} +// din_imag = {Im{x4}, Im{x3}, Im{x2}, Im{x1}} +// dout_valid: Indicate [dout_real/imag] data are valid. The latency is +// determined by the configuration of the cmpy ip core, which is set to 5 +// clock cycles by default. +// dout_real/imag: +// dout_real = {Re{x4*x4^H}, Re{x4*x3^H}, ..., Re{x1*x2^H}, Re{x1*x1^H}} +// dout_imag = {Im{x4*x4^H}, Im{x4*x3^H}, ..., Im{x1*x2^H}, Im{x1*x1^H}} +// +// Latency: 5 clock cycles for CMPY using LUTs, 6 for DSPs. +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// 20230713-1557 - 1. 增加 AXIS æ ¼å¼è½¬æ¢å‰åŽä¸­é—´å˜é‡ï¼Œä¾¿äºŽè§‚察中间结果；2. 输 +// 出ä½å®½å¤§äºŽè®¡ç®—ä½å®½æ—¶ä»Žç¬¦å·ä¸ºæ‰©å±•å˜ä¸ºæœ«å°¾è¡¥é›¶ï¼›3. 修改部分å˜é‡å称，æå‡ +// å¯è¯»æ€§ã€‚ +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module acorr_cmplx_col_vec +#( + parameter DATA_I_WIDTH = 12, + parameter DATA_O_WIDTH = 24, + parameter COL_NUM = 4 +) +( + // clock & reset + input clk, + input rst, + + // input data + input din_valid, + input [COL_NUM*DATA_I_WIDTH-1:0] din_real, + input [COL_NUM*DATA_I_WIDTH-1:0] din_imag, + + // output data + output dout_valid, + output [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, + output [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_imag +); + +// local parameters +localparam CMPY_P_FULL_WIDTH = 2*DATA_I_WIDTH+1; +localparam CMPY_P_VALID_WIDTH = 2*DATA_I_WIDTH; +localparam AXIS_CMPY_I_WIDTH = 8*((DATA_I_WIDTH-1)/8+1) ; // axis data width of input real/image data +localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_FULL_WIDTH-1)/8+1); // axis data width of cmpy output real/image data + +genvar i,j; + + +// prepare cmpy input data +wire [DATA_I_WIDTH-1:0] din_real_array [0:COL_NUM-1]; +wire [DATA_I_WIDTH-1:0] din_imag_array [0:COL_NUM-1]; + +wire [AXIS_CMPY_I_WIDTH-1:0] din_real_array_axis [0:COL_NUM-1]; +wire [AXIS_CMPY_I_WIDTH-1:0] din_imag_array_axis [0:COL_NUM-1]; + +for(i = 0; i < COL_NUM; i = i + 1) begin: array_conversion + // Array split + assign din_real_array[i] = din_real[i*DATA_I_WIDTH +: DATA_I_WIDTH]; + assign din_imag_array[i] = din_imag[i*DATA_I_WIDTH +: DATA_I_WIDTH]; + + // Sign extension to fit 8-bit axis data format + assign din_real_array_axis[i] = {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real_array[i][DATA_I_WIDTH-1]}},din_real[i*DATA_I_WIDTH +: DATA_I_WIDTH]}; + assign din_imag_array_axis[i] = {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag_array[i][DATA_I_WIDTH-1]}},din_imag[i*DATA_I_WIDTH +: DATA_I_WIDTH]}; +end + + +// complex multiplication +wire [AXIS_CMPY_P_WIDTH-1:0] cmpy_real_array_axis [0:COL_NUM*COL_NUM-1]; +wire [AXIS_CMPY_P_WIDTH-1:0] cmpy_imag_array_axis [0:COL_NUM*COL_NUM-1]; + +wire [CMPY_P_VALID_WIDTH-1:0] cmpy_real_array [0:COL_NUM*COL_NUM-1]; +wire [CMPY_P_VALID_WIDTH-1:0] cmpy_imag_array [0:COL_NUM*COL_NUM-1]; + +wire [DATA_O_WIDTH-1:0] dout_real_array [0:COL_NUM*COL_NUM-1]; +wire [DATA_O_WIDTH-1:0] dout_imag_array [0:COL_NUM*COL_NUM-1]; + +for(i = 0; i < COL_NUM; i = i + 1) begin: acorr_cmpy_col + for(j = 0; j < COL_NUM; j = j + 1) begin: acorr_cmpy_row + // cmpy interface + wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_a; + wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_b; + wire [2*AXIS_CMPY_P_WIDTH-1:0] cmpy_p; + wire cmpy_p_vld; + + assign cmpy_a = {din_imag_array_axis[i],din_real_array_axis[i]}; + assign cmpy_b = {-din_imag_array_axis[j],din_real_array_axis[j]}; + assign {cmpy_imag_array_axis[i*COL_NUM+j],cmpy_real_array_axis[i*COL_NUM+j]} = cmpy_p; + + assign cmpy_real_array[i*COL_NUM+j] = cmpy_real_array_axis[i*COL_NUM+j][0 +: CMPY_P_VALID_WIDTH]; + assign cmpy_imag_array[i*COL_NUM+j] = cmpy_imag_array_axis[i*COL_NUM+j][0 +: CMPY_P_VALID_WIDTH]; + + cmpy_12x12 u_cmpy_12x12 + ( + .aclk (clk ), // input wire aclk + .s_axis_a_tvalid (din_valid ), // input wire s_axis_a_tvalid + .s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid (din_valid ), // input wire s_axis_b_tvalid + .s_axis_b_tdata (cmpy_b ), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata + ); + + + // output data interface + if (DATA_O_WIDTH <= CMPY_P_VALID_WIDTH) begin + // truncate msb of the valid part + assign dout_real_array[i*COL_NUM+j] = cmpy_real_array[i*COL_NUM+j][CMPY_P_VALID_WIDTH-1 -: DATA_O_WIDTH]; + assign dout_imag_array[i*COL_NUM+j] = cmpy_imag_array[i*COL_NUM+j][CMPY_P_VALID_WIDTH-1 -: DATA_O_WIDTH]; + end + else begin + // append zeros to fit output data width + assign dout_real_array[i*COL_NUM+j] = {cmpy_real_array[i*COL_NUM+j],{(DATA_O_WIDTH-CMPY_P_VALID_WIDTH){1'b0}}}; + assign dout_imag_array[i*COL_NUM+j] = {cmpy_imag_array[i*COL_NUM+j],{(DATA_O_WIDTH-CMPY_P_VALID_WIDTH){1'b0}}}; + end + + assign dout_real[(i*COL_NUM+j)*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_real_array[i*COL_NUM+j]; + assign dout_imag[(i*COL_NUM+j)*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_imag_array[i*COL_NUM+j]; + end +end + +// output mapping +assign dout_valid = acorr_cmpy_col[0].acorr_cmpy_row[0].cmpy_p_vld; + +endmodule + + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/10/30 20:46:26 +// Design Name: +// Module Name: acorr_tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Testbench for [acorr_cmplx_col_vec] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// ------------------------------- +// MATLAB Code for data generation +// ------------------------------- +// COLUMN_NUM = 4; +// DATA_I_WIDTH = 12; + +// rng(0); +// data = (rand(4,2)*2-1) + 1i*(rand(4,2)*2-1); +// d_12b = round(data/max(max(abs(data)))*(2^11-1)); +// d_12b_real = real(d_12b(end:-1:1,:)); +// d_12b_imag = imag(d_12b(end:-1:1,:)); +// d_12b_acorr(:,:,1) = d_12b(:,1)*d_12b(:,1)'; +// d_12b_acorr(:,:,2) = d_12b(:,2)*d_12b(:,2)'; + + +// module tb_acorr; + +// localparam ROW_NUM = 1; +// localparam COL_NUM = 4; +// localparam DATA_I_WIDTH = 12; +// localparam DATA_O_WIDTH = 23; + +// reg acc_rst = 1'b0; + +// reg clk = 1'b1; +// reg rst = 1'b1; +// reg din_valid = 'b0; +// reg [COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0; + +// wire dout_valid; +// wire [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag; + +// acorr_cmplx_col_vec #( +// .COL_NUM (COL_NUM), +// .DATA_I_WIDTH (DATA_I_WIDTH), +// .DATA_O_WIDTH (DATA_O_WIDTH) +// ) u_acorr_cmplx_col_vec +// ( +// // clock & reset +// .clk (clk ), +// .rst (rst ), + +// // input data +// .din_valid (din_valid ), +// .din_real (din_real ), +// .din_imag (din_imag ), + +// // output data +// .dout_valid (dout_valid ), +// .dout_real (dout_real ), +// .dout_imag (dout_imag ) +// ); + + +// initial begin +// #102 rst = 1'b0; +// #222; +// @(posedge clk) +// din_valid = 1'b1; +// din_real = { +// 12'd1351, +// -12'd1219, +// 12'd1326, +// 12'd1029}; + +// din_imag = { +// 12'd1538, +// -12'd1119, +// 12'd1519, +// 12'd1495}; + +// @(posedge clk) +// din_valid = 1'b0; + +// @(posedge clk) +// din_valid = 1'b1; +// din_real = { +// 12'd153 , +// -12'd724 , +// -12'd1315, +// 12'd433 }; + +// din_imag = { +// -12'd1170, +// 12'd981 , +// -12'd48 , +// 12'd1494}; +// end + +// always #10 clk = ~clk; + + +// endmodule \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/ad9361_phase_cal_coarse.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/ad9361_phase_cal_coarse.v new file mode 100644 index 0000000..7e4b6de --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/ad9361_phase_cal_coarse.v @@ -0,0 +1,443 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/09/14 16:45:10 +// Last Modified Data: 2023/02/12 17:10 +// Design Name: +// Module Name: ad9361_phase_cal_coarse +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// 2022/09/14 16:45:10 - File Created +// 2023/02/12 17:10 - 修改：校准未完æˆæ—¶ï¼Œå°†è¾“入信å·å¯„存输出。 +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_phase_cal_coarse +#( + parameter COUNTER_MOD = 48, + parameter PEAK_POS = 12, + parameter ADC_DATA_WIDTH = 12 +) +( + // clock & reset + input clk , + input rst , + // control interface + input ad9361_1_cal_start , + output ad9361_1_cal_done , + input ad9361_2_cal_start , + output ad9361_2_cal_done , + output ad9361_cal_result , + output ad9361_cal_valid , + input ad9361_recal , + // input data interface + input [ADC_DATA_WIDTH-1:0] rx_ch1_i , + input [ADC_DATA_WIDTH-1:0] rx_ch1_q , + input [ADC_DATA_WIDTH-1:0] rx_ch2_i , + input [ADC_DATA_WIDTH-1:0] rx_ch2_q , + input [ADC_DATA_WIDTH-1:0] rx_ch3_i , + input [ADC_DATA_WIDTH-1:0] rx_ch3_q , + input [ADC_DATA_WIDTH-1:0] rx_ch4_i , + input [ADC_DATA_WIDTH-1:0] rx_ch4_q , + // output data interface + output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i, + output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q +); + +localparam STATE_IDLE = 2'd0; +localparam STATE_CAL_1 = 2'd1; +localparam STATE_CAL_2 = 2'd2; +localparam STATE_DONE = 2'd3; + +// buffer input control signals +reg ad9361_1_cal_start_d1 = 'b0; +reg ad9361_1_cal_start_d2 = 'b0; +reg ad9361_2_cal_start_d1 = 'b0; +reg ad9361_2_cal_start_d2 = 'b0; +reg ad9361_recal_d1 = 'b0; +reg ad9361_recal_d2 = 'b0; + +always @(posedge clk) begin + ad9361_1_cal_start_d1 <= ad9361_1_cal_start; + ad9361_1_cal_start_d2 <= ad9361_1_cal_start_d1; + + ad9361_2_cal_start_d1 <= ad9361_2_cal_start; + ad9361_2_cal_start_d2 <= ad9361_2_cal_start_d1; + + ad9361_recal_d1 <= ad9361_recal; + ad9361_recal_d2 <= ad9361_recal_d1; +end + +// center state machine +reg [ 1:0] curr_state = STATE_IDLE; + +always @(posedge clk) begin + if (rst) begin + curr_state <= STATE_IDLE; + end + else begin + case (curr_state) + STATE_IDLE: begin + // move to next state when [ad9361_1_cal_start] asserts + curr_state <= ad9361_1_cal_start_d2 ? STATE_CAL_1 : STATE_IDLE; + end + STATE_CAL_1: begin + // move to next state when 1st cal finishes [ad9361_2_cal_start] asserts + curr_state <= (ad9361_1_cal_done && ad9361_2_cal_start_d2) ? STATE_CAL_2 : STATE_CAL_1; + end + STATE_CAL_2: begin + // move to next state when 2nd cal finishes + curr_state <= ad9361_2_cal_done ? STATE_DONE : STATE_CAL_2; + end + STATE_DONE: begin + // move to ILDA state when it needs to recal + curr_state <= (ad9361_recal_d2) ? STATE_IDLE : STATE_DONE; + end + default: begin + curr_state <= STATE_IDLE; + end + endcase + end +end + +// +reg rx_ch2_i_msb_d1 = 'b0; +reg cnt_start = 'b0; +reg cnt_start_flag = 'b0; +reg [$clog2(COUNTER_MOD)-1:0] cnt = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_ch2_i_rec = 'b0; +reg rx_ch2_i_rec_flag = 'b0; + +assign ad9361_1_cal_done = rx_ch2_i_rec_flag; + +always @(posedge clk) begin + if (rst) begin + rx_ch2_i_msb_d1 <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + rx_ch2_i_msb_d1 <= 'b0; + end + else if (curr_state == STATE_CAL_1) begin + rx_ch2_i_msb_d1 <= rx_ch2_i[ADC_DATA_WIDTH-1]; + end + else begin + rx_ch2_i_msb_d1 <= rx_ch2_i_msb_d1; + end +end + +always @(posedge clk) begin + if (rst) begin + cnt_start <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + cnt_start <= 'b0; + end + else if (curr_state == STATE_CAL_1 && ~cnt_start) begin + // assert when the 1st falling edge of msb of rx_ch2_i is detected + cnt_start <= (rx_ch2_i_msb_d1 & ~rx_ch2_i[ADC_DATA_WIDTH-1]) ? 1'b1 : 1'b0; + end + else begin + cnt_start <= cnt_start; + end +end + +always @(posedge clk) begin + if (rst) begin + cnt <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + cnt <= 'b0; + end + else if (cnt_start) begin + cnt <= (cnt == COUNTER_MOD - 1) ? 'b0 : cnt + 1'b1; + end + else begin + cnt <= cnt; + end +end + +always @(posedge clk) begin + if (rst) begin + rx_ch2_i_rec <= 'b0; + rx_ch2_i_rec_flag <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + rx_ch2_i_rec <= 'b0; + rx_ch2_i_rec_flag <= 'b0; + end + else if (curr_state == STATE_CAL_1 && cnt == PEAK_POS && ~rx_ch2_i_rec_flag) begin + rx_ch2_i_rec <= rx_ch2_i; + rx_ch2_i_rec_flag <= 1'b1; + end + else begin + rx_ch2_i_rec <= rx_ch2_i_rec; + rx_ch2_i_rec_flag <= rx_ch2_i_rec_flag; + end +end + +// +reg [ADC_DATA_WIDTH-1:0] rx_ch4_i_rec = 'b0; +reg rx_ch4_i_rec_flag = 'b0; + +assign ad9361_2_cal_done = rx_ch4_i_rec_flag; + +always @(posedge clk) begin + if (rst) begin + rx_ch4_i_rec <= 'b0; + rx_ch4_i_rec_flag <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + rx_ch4_i_rec <= 'b0; + rx_ch4_i_rec_flag <= 'b0; + end + else if (curr_state == STATE_CAL_2 && cnt == COUNTER_MOD/4 && ~rx_ch4_i_rec_flag) begin + rx_ch4_i_rec <= rx_ch4_i; + rx_ch4_i_rec_flag <= 1'b1; + end + else begin + rx_ch4_i_rec <= rx_ch4_i_rec; + rx_ch4_i_rec_flag <= rx_ch4_i_rec_flag; + end +end + + +reg ad9361_cal_valid_buf = 'b0; +reg ad9361_cal_result_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q_buf = 'b0; +reg [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q_buf = 'b0; + +assign ad9361_cal_valid = ad9361_cal_valid_buf; +assign ad9361_cal_result = ad9361_cal_result_buf; +assign rx_cal_ch1_i = rx_cal_ch1_i_buf; +assign rx_cal_ch2_i = rx_cal_ch2_i_buf; +assign rx_cal_ch3_i = rx_cal_ch3_i_buf; +assign rx_cal_ch4_i = rx_cal_ch4_i_buf; +assign rx_cal_ch1_q = rx_cal_ch1_q_buf; +assign rx_cal_ch2_q = rx_cal_ch2_q_buf; +assign rx_cal_ch3_q = rx_cal_ch3_q_buf; +assign rx_cal_ch4_q = rx_cal_ch4_q_buf; + +always @(posedge clk) begin + if (rst) begin + ad9361_cal_valid_buf <= 'b0; + ad9361_cal_result_buf <= 'b0; + rx_cal_ch1_i_buf <= 'b0; + rx_cal_ch2_i_buf <= 'b0; + rx_cal_ch3_i_buf <= 'b0; + rx_cal_ch4_i_buf <= 'b0; + rx_cal_ch1_q_buf <= 'b0; + rx_cal_ch2_q_buf <= 'b0; + rx_cal_ch3_q_buf <= 'b0; + rx_cal_ch4_q_buf <= 'b0; + end + else if (curr_state == STATE_DONE) begin + ad9361_cal_valid_buf <= 1'b1; + + if (rx_ch2_i_rec[ADC_DATA_WIDTH-1] == rx_ch4_i_rec[ADC_DATA_WIDTH-1]) begin + ad9361_cal_result_buf <= 'b0; + rx_cal_ch1_i_buf <= rx_ch1_i; + rx_cal_ch1_q_buf <= rx_ch1_q; + rx_cal_ch2_i_buf <= -rx_ch2_i; + rx_cal_ch2_q_buf <= -rx_ch2_q; + rx_cal_ch3_i_buf <= rx_ch3_i; + rx_cal_ch3_q_buf <= rx_ch3_q; + rx_cal_ch4_i_buf <= -rx_ch4_i; + rx_cal_ch4_q_buf <= -rx_ch4_q; + end + else begin + ad9361_cal_result_buf <= 'b1; + rx_cal_ch1_i_buf <= rx_ch1_i; + rx_cal_ch1_q_buf <= rx_ch1_q; + rx_cal_ch2_i_buf <= -rx_ch2_i; + rx_cal_ch2_q_buf <= -rx_ch2_q; + rx_cal_ch3_i_buf <= -rx_ch3_i; + rx_cal_ch3_q_buf <= -rx_ch3_q; + rx_cal_ch4_i_buf <= rx_ch4_i; + rx_cal_ch4_q_buf <= rx_ch4_q; + end + end + else begin + ad9361_cal_valid_buf <= 1'b0; + ad9361_cal_result_buf <= ad9361_cal_result_buf; + rx_cal_ch1_i_buf <= rx_ch1_i; + rx_cal_ch2_i_buf <= rx_ch2_i; + rx_cal_ch3_i_buf <= rx_ch3_i; + rx_cal_ch4_i_buf <= rx_ch4_i; + rx_cal_ch1_q_buf <= rx_ch1_q; + rx_cal_ch2_q_buf <= rx_ch2_q; + rx_cal_ch3_q_buf <= rx_ch3_q; + rx_cal_ch4_q_buf <= rx_ch4_q; + end +end + +endmodule + + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/09/15 11:12:45 +// Last Modified Data: 2022/11/02 +// Design Name: +// Module Name: tb_ad9361_cal_coarse +// Project Name: +// Target Devices: +// Tool Versions: +// Description: testbench for [ad9361_phase_cal_coarse] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// module tb_ad9361_cal_coarse; + +// reg clk = 'b0; +// reg rst = 1'b1; + +// reg ad9361_1_cal_start = 'b0; +// wire ad9361_1_cal_done ; +// reg ad9361_2_cal_start = 'b0; +// wire ad9361_2_cal_done ; +// wire ad9361_cal_result ; +// wire ad9361_cal_valid; +// reg ad9361_recal = 'b0; + +// // phase difference of 180 degree +// reg [11:0] rx_ch1_i = 12'd2047; +// reg [11:0] rx_ch1_q = 12'd2047; +// reg [11:0] rx_ch2_i = -12'd2047; +// reg [11:0] rx_ch2_q = -12'd2047; +// reg [11:0] rx_ch3_q = -12'd2047; +// reg [11:0] rx_ch3_i = -12'd2047; +// reg [11:0] rx_ch4_i = 12'd2047; +// reg [11:0] rx_ch4_q = 12'd2047; + +// wire [11:0] rx_cal_ch1_i; +// wire [11:0] rx_cal_ch2_i; +// wire [11:0] rx_cal_ch3_i; +// wire [11:0] rx_cal_ch4_i; +// wire [11:0] rx_cal_ch1_q; +// wire [11:0] rx_cal_ch2_q; +// wire [11:0] rx_cal_ch3_q; +// wire [11:0] rx_cal_ch4_q; + +// ad9361_phase_cal #( +// .COUNTER_MOD (48), +// .PEAK_POS (12) +// ) u_ad9361_phase_cal +// ( +// // clock & reset +// .clk (clk ), // input clk +// .rst (rst ), // input rst +// // control interface +// .ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start +// .ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done +// .ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start +// .ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done +// .ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result +// .ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid +// .ad9361_recal (ad9361_recal ), // input ad9361_recal +// // input data interface +// .rx_ch1_i (rx_ch1_i ), // input [11:0] rx_ch1_i +// .rx_ch2_i (rx_ch2_i ), // input [11:0] rx_ch2_i +// .rx_ch3_i (rx_ch3_i ), // input [11:0] rx_ch3_i +// .rx_ch4_i (rx_ch4_i ), // input [11:0] rx_ch4_i +// .rx_ch1_q (rx_ch1_q ), // input [11:0] rx_ch1_q +// .rx_ch2_q (rx_ch2_q ), // input [11:0] rx_ch2_q +// .rx_ch3_q (rx_ch3_q ), // input [11:0] rx_ch3_q +// .rx_ch4_q (rx_ch4_q ), // input [11:0] rx_ch4_q +// // output data interface +// .rx_cal_ch1_i (rx_cal_ch1_i ), // output [11:0] rx_cal_ch1_i +// .rx_cal_ch2_i (rx_cal_ch2_i ), // output [11:0] rx_cal_ch2_i +// .rx_cal_ch3_i (rx_cal_ch3_i ), // output [11:0] rx_cal_ch3_i +// .rx_cal_ch4_i (rx_cal_ch4_i ), // output [11:0] rx_cal_ch4_i +// .rx_cal_ch1_q (rx_cal_ch1_q ), // output [11:0] rx_cal_ch1_q +// .rx_cal_ch2_q (rx_cal_ch2_q ), // output [11:0] rx_cal_ch2_q +// .rx_cal_ch3_q (rx_cal_ch3_q ), // output [11:0] rx_cal_ch3_q +// .rx_cal_ch4_q (rx_cal_ch4_q ) // output [11:0] rx_cal_ch4_q +// ); + +// initial begin +// #102 +// rst = 1'b0; +// #100 +// ad9361_1_cal_start = 1'b1; +// end + +// initial begin +// #10000 +// ad9361_recal = 1'b1; +// #20 +// ad9361_recal = 1'b0; +// end + +// always begin +// #2 clk = ~clk; +// end + +// always begin +// #72 +// rx_ch1_i = ~rx_ch1_i; +// rx_ch2_i = ~rx_ch2_i; +// rx_ch3_i = ~rx_ch3_i; +// rx_ch4_i = ~rx_ch4_i; +// #24 +// rx_ch1_q = ~rx_ch1_q; +// rx_ch2_q = ~rx_ch2_q; +// rx_ch3_q = ~rx_ch3_q; +// rx_ch4_q = ~rx_ch4_q; +// end + +// always @(posedge clk) begin +// if (ad9361_1_cal_done) begin +// ad9361_2_cal_start <= 1'b1; +// end +// else begin +// ad9361_2_cal_start <= 1'b0; +// end +// end + +// endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/ad9361_phase_cal_fine.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/ad9361_phase_cal_fine.v new file mode 100644 index 0000000..0d9a373 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/ad9361_phase_cal_fine.v @@ -0,0 +1,1191 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2023/02/15 17:47:17 +// Last Modified Date: 2023/03/04 12:30:00 +// Design Name: +// Module Name: ad9361_phase_cal_fine +// Project Name: +// Target Devices: +// Tool Versions: +// Description: 本程åºç”¨äºŽ +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// 20230304-1230 +// 1. 修改相ä½å·®è®¡ç®—结果，原计算结果å¯èƒ½è¶…出 [-pi,pi] 范围，现在会进行修正； +// 2. 修改 CORDIC IP 核相ä½è¾“入输出为 Scaled Radians 模å¼ï¼› +// 3. 修改 [cnt_decim] 在校准完æˆçŠ¶æ€ä¸‹çš„值为 0ï¼› +// 4. 通é“间相对延迟计算ä¸æ­£ç¡®ï¼Œä¿®æ”¹ [peak_index_num] 为无符å·æ•°å³å¯ï¼› +// 5. 修改 [atan2_data_xxxx] 在累积结果长度å°äºŽ CORDIC AXIS ä½å®½æ—¶çš„符å·ä½æ‰©å±•æ–¹æ³•ã€‚ +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_phase_cal_fine +#( + parameter ADC_DATA_WIDTH = 12, + parameter PRBS = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)] + parameter PRBS_LEN = 128, // length of pseudorandom bit sequence + parameter INTERP_FACTOR = 8, // interpolation factor, max inter-channel delay ranges in [-INTERP_FACTOR+1,INTERP_FACTOR-1] + parameter ACCUM_SYMBOL_NUM = 16, + parameter CORDIC_WIDTH = 16, // input and output data width of cordic-ip-based atan2 and rotation operation + parameter CHANNEL_NUM = 2 // the channel number of current algorithm is LIMITED to 2 +) +( + // clock & reset + input clk , + input rst , + // control interface + input ad9361_1_cal_start , + output ad9361_1_cal_done , + input ad9361_2_cal_start , + output ad9361_2_cal_done , + output ad9361_cal_result , + output ad9361_cal_valid , + input ad9361_recal , + // input data interface + input [ADC_DATA_WIDTH-1 : 0] rx_ch1_i , + input [ADC_DATA_WIDTH-1 : 0] rx_ch1_q , + input [ADC_DATA_WIDTH-1 : 0] rx_ch2_i , + input [ADC_DATA_WIDTH-1 : 0] rx_ch2_q , + input [ADC_DATA_WIDTH-1 : 0] rx_ch3_i , + input [ADC_DATA_WIDTH-1 : 0] rx_ch3_q , + input [ADC_DATA_WIDTH-1 : 0] rx_ch4_i , + input [ADC_DATA_WIDTH-1 : 0] rx_ch4_q , + // output data interface + output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch1_i , + output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch1_q , + output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch2_i , + output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch2_q , + output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch3_i , + output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch3_q , + output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch4_i , + output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch4_q +); + +localparam STATE_IDLE = 2'd0; // idle state +localparam STATE_CAL_1 = 2'd1; // correlation, accumulation and peak finding +localparam STATE_CAL_2 = 2'd2; // phase calculation, rotation and delay compansation +localparam STATE_DONE = 2'd3; // done state + +localparam signed POS_PI_2Q13_SCALED = 16'b001_00000_00000_000; +localparam signed NEG_PI_2Q13_SCALED = 16'b111_00000_00000_000; + +integer i, j; +genvar m, n; + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////// Center State Machine ///////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// buffer input control signals (clock domain crossing from ps to pl clock domain) +reg ad9361_1_cal_start_d1 = 'b0; +reg ad9361_1_cal_start_d2 = 'b0; +reg ad9361_2_cal_start_d1 = 'b0; +reg ad9361_2_cal_start_d2 = 'b0; +reg ad9361_recal_d1 = 'b0; +reg ad9361_recal_d2 = 'b0; + +always @(posedge clk) begin + ad9361_1_cal_start_d1 <= ad9361_1_cal_start; + ad9361_1_cal_start_d2 <= ad9361_1_cal_start_d1; + + ad9361_2_cal_start_d1 <= ad9361_2_cal_start; + ad9361_2_cal_start_d2 <= ad9361_2_cal_start_d1; + + ad9361_recal_d1 <= ad9361_recal; + ad9361_recal_d2 <= ad9361_recal_d1; +end + +// center state machine +reg [ 1:0] curr_state = STATE_IDLE; + +always @(posedge clk) begin + if (rst) begin + curr_state <= STATE_IDLE; + end + else begin + case (curr_state) + STATE_IDLE: begin + // move to next state when [ad9361_1_cal_start] asserts + curr_state <= ad9361_1_cal_start_d2 ? STATE_CAL_1 : STATE_IDLE; + end + STATE_CAL_1: begin + // move to next state when 1st cal finishes and [ad9361_2_cal_start] asserts + curr_state <= ad9361_1_cal_done ? STATE_CAL_2 : STATE_CAL_1; + end + STATE_CAL_2: begin + // move to next state when 2nd cal finishes + curr_state <= ad9361_2_cal_done ? STATE_DONE : STATE_CAL_2; + end + STATE_DONE: begin + // move to IDLE state when it needs to recal + curr_state <= (ad9361_recal_d2) ? STATE_IDLE : STATE_DONE; + end + default: begin + curr_state <= STATE_IDLE; + end + endcase + end +end + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////////// Accumulation ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// state counter +reg [$clog2(INTERP_FACTOR)-1 : 0] cnt_decim = 'b0; // downsample counter, mod [INTERP_FACTOR] +reg [$clog2(PRBS_LEN)-1 : 0] cnt_chip_in = 'b0; // input chip counter, mod [PRBS_LEN] +reg [$clog2(PRBS_LEN)-1 : 0] pn_curr_addr = 'b0; // current local pn address, mod [PRBS_LEN] +reg [$clog2(ACCUM_SYMBOL_NUM)-1 : 0] cnt_symbol = 'b0; // accumulation symbol counter, mod [ACCUM_SYMBOL_NUM] +reg [$clog2(PRBS_LEN)-1 : 0] cnt_accum = 'b0; // accumulation result index indicator, mod [PRBS_LEN] + +always @(posedge clk) begin + // downsample counter, each clock cycles increase by 1 during calibration state + if (rst) begin + cnt_decim <= 'b0; + end + else begin + case (curr_state) + STATE_IDLE : cnt_decim <= 'b0; + STATE_CAL_1: cnt_decim <= cnt_decim + 1'b1; + STATE_CAL_2: cnt_decim <= cnt_decim + 1'b1; + STATE_DONE : cnt_decim <= 'b0; + default : cnt_decim <= 'b0; + endcase + end +end + +always @(posedge clk) begin + if (rst) begin + cnt_chip_in <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + cnt_chip_in <= 'b0; + end + else if (cnt_decim == INTERP_FACTOR-1) begin + // each time the number of samples received is [INTERP_FACTOR], increase the counter by 1, + // indicating a new chip is received + cnt_chip_in <= cnt_chip_in + 1'b1; + end + else begin + cnt_chip_in <= cnt_chip_in; + end +end + +always @(posedge clk) begin + if (rst) begin + pn_curr_addr <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + pn_curr_addr <= 'b0; + end + else if (cnt_decim == INTERP_FACTOR-1) begin + // each time the number of samples received is [INTERP_FACTOR], if the number of complete symbols + // accumulated is [ACCUM_SYMBOL_NUM], increase the address by 2; otherwise by 1. The increasing-by-2 + // behaviour is analogous to `circshift` operation in MATLAB. + pn_curr_addr <= (cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1) ? pn_curr_addr + 2'd2 : pn_curr_addr + 2'd1; + end + else begin + pn_curr_addr <= pn_curr_addr; + end +end + +always @(posedge clk) begin + if (rst) begin + cnt_symbol <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + cnt_symbol <= 'b0; + end + else if (cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin + // each time the number of complete chips received is [PRBS_LEN], increase the counter by 1, + // indicating a complete symbol is received + cnt_symbol <= cnt_symbol + 1'b1; + end + else begin + cnt_symbol <= cnt_symbol; + end +end + +always @(posedge clk) begin + if (rst) begin + cnt_accum <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + cnt_accum <= 'b0; + end + else if (cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin + // each time the number of complete symbols received is [ACCUM_SYMBOL_NUM], increase the counter by 1, + // indicating the accumulation of current pn code phased is finished + cnt_accum <= cnt_accum + 1'b1; + end + else begin + cnt_accum <= cnt_accum; + end +end + +// accumulate the msb of input data at different sample position +localparam MSB_ACCUM_LEN = $clog2(PRBS_LEN*ACCUM_SYMBOL_NUM)+2; // extra 2 bits to ensure signed operation and to prevent overflow + +reg signed [MSB_ACCUM_LEN-1 : 0] msb_accum_i [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1]; +reg signed [MSB_ACCUM_LEN-1 : 0] msb_accum_q [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1]; + +always @(posedge clk) begin + if (rst) begin + for (i = 0; i < CHANNEL_NUM; i = i + 1) begin + for (j = 0; j < INTERP_FACTOR; j = j + 1) begin + msb_accum_i[i][j] <= 'b0; + msb_accum_q[i][j] <= 'b0; + end + end + end + else if (curr_state == STATE_CAL_1) begin + if (cnt_symbol == 'b0 && cnt_chip_in == 'b0) begin + // set the initial value to 1 when msb equals current pn code, otherwise set to -1 + msb_accum_i[0][cnt_decim] <= (rx_ch2_i[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? 1'b1 : -1'b1; + msb_accum_q[0][cnt_decim] <= (rx_ch2_q[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? 1'b1 : -1'b1; + msb_accum_i[1][cnt_decim] <= (rx_ch4_i[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? 1'b1 : -1'b1; + msb_accum_q[1][cnt_decim] <= (rx_ch4_q[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? 1'b1 : -1'b1; + end + else begin + // increase when msb equals current pn code, otherwise decrease + msb_accum_i[0][cnt_decim] <= (rx_ch2_i[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? (msb_accum_i[0][cnt_decim] + 1'b1) : (msb_accum_i[0][cnt_decim] - 1'b1); + msb_accum_q[0][cnt_decim] <= (rx_ch2_q[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? (msb_accum_q[0][cnt_decim] + 1'b1) : (msb_accum_q[0][cnt_decim] - 1'b1); + msb_accum_i[1][cnt_decim] <= (rx_ch4_i[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? (msb_accum_i[1][cnt_decim] + 1'b1) : (msb_accum_i[1][cnt_decim] - 1'b1); + msb_accum_q[1][cnt_decim] <= (rx_ch4_q[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? (msb_accum_q[1][cnt_decim] + 1'b1) : (msb_accum_q[1][cnt_decim] - 1'b1); + end + end + else begin + for (i = 0; i < CHANNEL_NUM; i = i + 1) begin + for (j = 0; j < INTERP_FACTOR; j = j + 1) begin + msb_accum_i[i][j] <= 'b0; + msb_accum_q[i][j] <= 'b0; + end + end + end +end + +// flag signal indicating the accumulation within one symbol (i.e. one kind of pn phase) is finished +reg symbol_msb_accum_valid = 'b0; +// preserve pn phase index for approximate moduli module +reg [$clog2(PRBS_LEN)-1 : 0] symbol_msb_accum_index = 'b0; + +always @(posedge clk) begin + if (rst) begin + symbol_msb_accum_valid <= 'b0; + end + else if (cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin + symbol_msb_accum_valid <= 1'b1; + end + else begin + symbol_msb_accum_valid <= 'b0; + end +end + +always @(posedge clk) begin + if (rst) begin + symbol_msb_accum_index <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + symbol_msb_accum_index <= 'b0; + end + else if (cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin + symbol_msb_accum_index <= cnt_accum; + end + else begin + symbol_msb_accum_index <= symbol_msb_accum_index; + end +end + +// truncate or shift to fit in 26-bit data format & get the absolute value +wire [25 : 0] msb_accum_i_26b [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1]; +wire [25 : 0] msb_accum_q_26b [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1]; +wire [25 : 0] msb_accum_abs [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1]; +wire msb_accum_abs_valid [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1]; + +generate +for (m = 0; m < CHANNEL_NUM; m = m + 1) begin +for (n = 0; n < INTERP_FACTOR; n = n + 1) begin + +assign msb_accum_i_26b[m][n] = (MSB_ACCUM_LEN > 26) ? msb_accum_i[m][n][MSB_ACCUM_LEN-1 -: 26] : {{(26-MSB_ACCUM_LEN){msb_accum_i[m][n][MSB_ACCUM_LEN-1]}},msb_accum_i[m][n]}; +assign msb_accum_q_26b[m][n] = (MSB_ACCUM_LEN > 26) ? msb_accum_q[m][n][MSB_ACCUM_LEN-1 -: 26] : {{(26-MSB_ACCUM_LEN){msb_accum_q[m][n][MSB_ACCUM_LEN-1]}},msb_accum_q[m][n]}; + +ApproxModuli_26bit u_msb_accum_abs +( + .clk (clk ), + .din_valid (symbol_msb_accum_valid ), + .din_I (msb_accum_i_26b[m][n] ), + .din_Q (msb_accum_q_26b[m][n] ), + .dout_valid (msb_accum_abs_valid[m][n] ), + .dout (msb_accum_abs[m][n] ) +); + +end +end +endgenerate + + +// record the peak index and corresponding value +reg [25 : 0] msb_accum_abs_peak [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1]; +reg [$clog2(PRBS_LEN)-1 : 0] msb_accum_abs_peak_index [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1]; + +generate +for (m = 0; m < CHANNEL_NUM; m = m + 1) begin +for (n = 0; n < INTERP_FACTOR; n = n + 1) begin + +always @(posedge clk) begin + if (rst) begin + msb_accum_abs_peak[m][n] <= 'b0; + msb_accum_abs_peak_index[m][n] <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + msb_accum_abs_peak[m][n] <= 'b0; + msb_accum_abs_peak_index[m][n] <= 'b0; + end + else if (msb_accum_abs_valid[m][n]) begin + msb_accum_abs_peak[m][n] <= (msb_accum_abs_peak[m][n] >= msb_accum_abs[m][n]) ? msb_accum_abs_peak[m][n] : msb_accum_abs[m][n]; + msb_accum_abs_peak_index[m][n] <= (msb_accum_abs_peak[m][n] >= msb_accum_abs[m][n]) ? msb_accum_abs_peak_index[m][n] : symbol_msb_accum_index; + end +end + +end +end +endgenerate + + +// accumulate input data at the 1st sample position and the 1st and 2nd chip position +// during the last msb accumulation cycle +localparam DATA_ACCUM_LEN = $clog2(ACCUM_SYMBOL_NUM)+ADC_DATA_WIDTH; + +reg signed [DATA_ACCUM_LEN-1 : 0] rx_i_accum [0 : CHANNEL_NUM-1][0 : 1]; +reg signed [DATA_ACCUM_LEN-1 : 0] rx_q_accum [0 : CHANNEL_NUM-1][0 : 1]; + +always @(posedge clk) begin + if (rst) begin + for(i = 0; i < CHANNEL_NUM; i = i + 1) begin + for(j = 0; j < 2; j = j + 1) begin + rx_i_accum[i][j] <= 'b0; + rx_q_accum[i][j] <= 'b0; + end + end + end + else if (curr_state == STATE_IDLE) begin + for(i = 0; i < CHANNEL_NUM; i = i + 1) begin + for(j = 0; j < 2; j = j + 1) begin + // reset at IDLE state + rx_i_accum[i][j] <= 'b0; + rx_q_accum[i][j] <= 'b0; + end + end + end + else if (cnt_accum == PRBS_LEN-1 && cnt_decim == 'b0) begin + case (cnt_chip_in) + 1'b0: begin + rx_i_accum[0][0] <= rx_i_accum[0][0] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch2_i[ADC_DATA_WIDTH-1]}},rx_ch2_i}; + rx_q_accum[0][0] <= rx_q_accum[0][0] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch2_q[ADC_DATA_WIDTH-1]}},rx_ch2_q}; + rx_i_accum[1][0] <= rx_i_accum[1][0] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch4_i[ADC_DATA_WIDTH-1]}},rx_ch4_i}; + rx_q_accum[1][0] <= rx_q_accum[1][0] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch4_q[ADC_DATA_WIDTH-1]}},rx_ch4_q}; + end + 1'b1: begin + rx_i_accum[0][1] <= rx_i_accum[0][1] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch2_i[ADC_DATA_WIDTH-1]}},rx_ch2_i}; + rx_q_accum[0][1] <= rx_q_accum[0][1] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch2_q[ADC_DATA_WIDTH-1]}},rx_ch2_q}; + rx_i_accum[1][1] <= rx_i_accum[1][1] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch4_i[ADC_DATA_WIDTH-1]}},rx_ch4_i}; + rx_q_accum[1][1] <= rx_q_accum[1][1] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch4_q[ADC_DATA_WIDTH-1]}},rx_ch4_q}; + end + default: begin + for(i = 0; i < CHANNEL_NUM; i = i + 1) begin + for(j = 0; j < 2; j = j + 1) begin + rx_i_accum[i][j] <= rx_i_accum[i][j]; + rx_q_accum[i][j] <= rx_q_accum[i][j]; + end + end + end + endcase + end + else begin + for(i = 0; i < CHANNEL_NUM; i = i + 1) begin + for(j = 0; j < 2; j = j + 1) begin + rx_i_accum[i][j] <= rx_i_accum[i][j]; + rx_q_accum[i][j] <= rx_q_accum[i][j]; + end + end + end +end + +// flag signal indicating the accumulation stage of calculation is finished +reg ad9361_1_cal_done_buf = 'b0; + +assign ad9361_1_cal_done = ad9361_1_cal_done_buf; + +always @(posedge clk) begin + if (rst) begin + ad9361_1_cal_done_buf <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + // reset at IDLE state + ad9361_1_cal_done_buf <= 'b0; + end + else if (cnt_accum == PRBS_LEN-1 && cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin + ad9361_1_cal_done_buf <= 1'b1; + end + else begin + ad9361_1_cal_done_buf <= ad9361_1_cal_done_buf; + end +end + + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////////// Accumulation ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// indicating the peak finding process is finished +reg peak_index_valid = 'b0; + +always @(posedge clk) begin + if (rst) begin + peak_index_valid <= 'b0; + end + else if (curr_state == STATE_CAL_2) begin + peak_index_valid <= msb_accum_abs_valid[0][0] ? 1'b1 : peak_index_valid; + end + else begin + peak_index_valid <= 'b0; + end +end + +// count the number of same peak index +reg [$clog2(INTERP_FACTOR)-1 : 0] peak_index_num [0 : CHANNEL_NUM-1]; +reg peak_index_num_valid = 'b0; + +reg signed [$clog2(INTERP_FACTOR) : 0] peak_index_num_diff = 'b0; // currently limit channel number to 2 +reg peak_index_num_diff_valid = 'b0; + +always @(posedge clk) begin + if (rst) begin + for (i = 0; i < CHANNEL_NUM; i = i + 1) begin + peak_index_num[i] <= 'b0; + end + end + else if (curr_state == STATE_CAL_2 && cnt_chip_in == 2'd2) begin + for (i = 0; i < CHANNEL_NUM; i = i + 1) begin + if (msb_accum_abs_peak_index[i][cnt_decim] == msb_accum_abs_peak_index[i][0]) begin + peak_index_num[i] <= cnt_decim; + end + else begin + peak_index_num[i] <= peak_index_num[i]; + end + end + end +end + +always @(posedge clk) begin + if (rst) begin + peak_index_num_valid <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + peak_index_num_valid <= 'b0; + end + else if (curr_state == STATE_CAL_2 && cnt_chip_in == 2'd2 && cnt_decim == INTERP_FACTOR-1) begin + peak_index_num_valid <= 1'b1; + end + else begin + peak_index_num_valid <= 'b0; + end +end + +always @(posedge clk) begin + if (rst) begin + peak_index_num_diff <= 'b0; + end + else if (peak_index_num_valid) begin + peak_index_num_diff <= peak_index_num[1] - peak_index_num[0]; + end +end + +always @(posedge clk) begin + if (rst) begin + peak_index_num_diff_valid <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + peak_index_num_diff_valid <= 'b0; + end + else begin + peak_index_num_diff_valid <= peak_index_num_valid; + end +end + +// +reg [$clog2(PRBS_LEN)-1 : 0] peak_index_plus_minus [0 : 2]; + +always @(posedge clk) begin + if (rst) begin + for (i = 0; i < 3; i = i + 1) begin + peak_index_plus_minus[i] <= 'b0; + end + end + else if (curr_state == STATE_CAL_2) begin + peak_index_plus_minus[0] <= msb_accum_abs_peak_index[0][0]; + peak_index_plus_minus[1] <= msb_accum_abs_peak_index[0][0] - 1'b1; + peak_index_plus_minus[2] <= msb_accum_abs_peak_index[0][0] + 1'b1; + end +end + +// get target downsample position +localparam CORDIC_LATENCY = 20; + +reg target_accum_index [0 : CHANNEL_NUM-1]; +reg target_accum_index_valid = 'b0; +reg [$clog2(INTERP_FACTOR+CORDIC_LATENCY)-1 : 0] relative_delay = 'b0; // compasate cordic delay +reg ad9361_cal_result_buf = 'b0; + +assign ad9361_cal_result = ad9361_cal_result_buf; + +always @(posedge clk) begin + if (rst) begin + for (i = 0; i < CHANNEL_NUM; i = i + 1) begin + target_accum_index[i] <= 'b0; + end + end + else if (peak_index_num_diff_valid) begin + if (msb_accum_abs_peak_index[1][0] == peak_index_plus_minus[0]) begin + target_accum_index[0] <= 1'b0; + target_accum_index[1] <= 1'b0; + relative_delay <= peak_index_num_diff + (CORDIC_LATENCY-1); + ad9361_cal_result_buf <= 1'b1; + end + else if (msb_accum_abs_peak_index[1][0] == peak_index_plus_minus[1]) begin + target_accum_index[0] <= 1'b0; + target_accum_index[1] <= 1'b1; + relative_delay <= peak_index_num_diff + INTERP_FACTOR + (CORDIC_LATENCY-1); + ad9361_cal_result_buf <= 1'b1; + end + else if (msb_accum_abs_peak_index[1][0] == peak_index_plus_minus[2]) begin + target_accum_index[0] <= 1'b1; + target_accum_index[1] <= 1'b0; + relative_delay <= peak_index_num_diff - INTERP_FACTOR + (CORDIC_LATENCY-1); + ad9361_cal_result_buf <= 1'b1; + end + else begin + target_accum_index[0] <= 1'b0; + target_accum_index[1] <= 1'b0; + relative_delay <= peak_index_num_diff + (CORDIC_LATENCY-1); + ad9361_cal_result_buf <= 1'b0; + end + end + else begin + for (i = 0; i < CHANNEL_NUM; i = i + 1) begin + target_accum_index[i] <= target_accum_index[i]; + end + relative_delay <= relative_delay; + end +end + +always @(posedge clk) begin + if (rst) begin + target_accum_index_valid <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + target_accum_index_valid <= 'b0; + end + else begin + target_accum_index_valid <= peak_index_num_diff_valid; + end +end + + +// get target data +reg [DATA_ACCUM_LEN-1 : 0] rx_i_accum_target [0 : CHANNEL_NUM-1]; +reg [DATA_ACCUM_LEN-1 : 0] rx_q_accum_target [0 : CHANNEL_NUM-1]; +reg rx_accum_target_valid = 'b0; + +always @(posedge clk) begin + if (rst) begin + for (i = 0; i < CHANNEL_NUM; i = i + 1) begin + rx_i_accum_target[i] <= 'b0; + rx_q_accum_target[i] <= 'b0; + end + end + else if (target_accum_index_valid) begin + for (i = 0; i < CHANNEL_NUM; i = i + 1) begin + rx_i_accum_target[i] <= rx_i_accum[i][target_accum_index[i]]; + rx_q_accum_target[i] <= rx_q_accum[i][target_accum_index[i]]; + end + end +end + +always @(posedge clk) begin + if (rst) begin + rx_accum_target_valid <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + rx_accum_target_valid <= 'b0; + end + else begin + rx_accum_target_valid <= target_accum_index_valid; + end +end + +// calculate phase difference +localparam AXIS_CORDIC_WIDTH = 8*((CORDIC_WIDTH-1)/8+1); + +wire [AXIS_CORDIC_WIDTH-1 : 0] atan2_data_real [0 : CHANNEL_NUM-1]; +wire [AXIS_CORDIC_WIDTH-1 : 0] atan2_data_imag [0 : CHANNEL_NUM-1]; + +wire [2*AXIS_CORDIC_WIDTH-1:0] atan2_data [0 : CHANNEL_NUM-1]; +wire atan2_valid_i [0 : CHANNEL_NUM-1]; + +wire signed [AXIS_CORDIC_WIDTH-1:0] atan2_phase [0 : CHANNEL_NUM-1]; +wire atan2_valid_o [0 : CHANNEL_NUM-1]; + +generate +for (m = 0; m < CHANNEL_NUM; m = m + 1) begin + +assign atan2_data_real[m] = (DATA_ACCUM_LEN > AXIS_CORDIC_WIDTH) ? rx_i_accum_target[m][DATA_ACCUM_LEN-1 -: AXIS_CORDIC_WIDTH] : {{(AXIS_CORDIC_WIDTH-DATA_ACCUM_LEN){rx_i_accum_target[m][DATA_ACCUM_LEN-1]}},rx_i_accum_target[m]}; +assign atan2_data_imag[m] = (DATA_ACCUM_LEN > AXIS_CORDIC_WIDTH) ? rx_q_accum_target[m][DATA_ACCUM_LEN-1 -: AXIS_CORDIC_WIDTH] : {{(AXIS_CORDIC_WIDTH-DATA_ACCUM_LEN){rx_q_accum_target[m][DATA_ACCUM_LEN-1]}},rx_q_accum_target[m]}; + +assign atan2_data[m] = {atan2_data_imag[m],atan2_data_real[m]}; +assign atan2_valid_i[m] = rx_accum_target_valid; + +atan2_16b u_atan2 +( + .aclk (clk ), // input wire aclk + .s_axis_cartesian_tvalid(atan2_valid_i[m] ), // input wire s_axis_cartesian_tvalid + .s_axis_cartesian_tdata (atan2_data[m] ), // input wire [31 : 0] s_axis_cartesian_tdata + .m_axis_dout_tvalid (atan2_valid_o[m] ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (atan2_phase[m] ) // output wire [15 : 0] m_axis_dout_tdata +); + +end +endgenerate + +reg signed [AXIS_CORDIC_WIDTH-1:0] phase_diff_raw = 'b0; +reg phase_diff_raw_valid = 'b0; + +reg signed [AXIS_CORDIC_WIDTH-1:0] phase_diff = 'b0; +reg phase_diff_valid = 'b0; + +always @(posedge clk) begin + if (rst) begin + phase_diff_raw <= 'b0; + end + else if (atan2_valid_o[0]) begin + // here calculate the phase difference from target channel to another channel, + // then rotate another channel to target channel + phase_diff_raw <= atan2_phase[0] - atan2_phase[1]; + end + else begin + phase_diff_raw <= phase_diff_raw; + end +end + +always @(posedge clk) begin + if (rst) begin + phase_diff_raw_valid <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + phase_diff_raw_valid <= 'b0; + end + else if (atan2_valid_o[0]) begin + phase_diff_raw_valid <= 1'b1; + end + else begin + phase_diff_raw_valid <= phase_diff_raw_valid; + end +end + +always @(posedge clk) begin + if (rst) begin + phase_diff <= 'b0; + end + else if (phase_diff_raw_valid) begin + if (phase_diff_raw > POS_PI_2Q13_SCALED) begin + phase_diff <= phase_diff_raw - (2*POS_PI_2Q13_SCALED); + end + else if (phase_diff_raw < NEG_PI_2Q13_SCALED) begin + phase_diff <= phase_diff_raw + (2*POS_PI_2Q13_SCALED); + end + else begin + phase_diff <= phase_diff_raw; + end + end +end + +always @(posedge clk) begin + if (rst) begin + phase_diff_valid <= 'b0; + end + else if (curr_state == STATE_IDLE) begin + phase_diff_valid <= 'b0; + end + else begin + phase_diff_valid <= phase_diff_raw_valid; + end +end + +// rotate the 3rd and 4th channel +wire rotate_phase_valid; +wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_phase_data; + +wire rotate_cart_valid; +wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch3_data_real; +wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch3_data_imag; +wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch4_data_real; +wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch4_data_imag; +wire [2*AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch3_data; +wire [2*AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch4_data; + +wire rotate_dout_ch3_valid; +wire rotate_dout_ch4_valid; +wire [2*AXIS_CORDIC_WIDTH-1 : 0] rotate_dout_ch3_data; +wire [2*AXIS_CORDIC_WIDTH-1 : 0] rotate_dout_ch4_data; +wire [AXIS_CORDIC_WIDTH-1 : 0] rx_ch3_rotate_i; +wire [AXIS_CORDIC_WIDTH-1 : 0] rx_ch3_rotate_q; +wire [AXIS_CORDIC_WIDTH-1 : 0] rx_ch4_rotate_i; +wire [AXIS_CORDIC_WIDTH-1 : 0] rx_ch4_rotate_q; + +assign rotate_phase_valid = phase_diff_valid; +assign rotate_phase_data = phase_diff; + +assign rotate_cart_valid = 1'b1; +assign rotate_cart_ch3_data_real = (ADC_DATA_WIDTH > AXIS_CORDIC_WIDTH) ? rx_ch3_i[ADC_DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH] : {rx_ch3_i,{(AXIS_CORDIC_WIDTH-ADC_DATA_WIDTH){1'b0}}}; +assign rotate_cart_ch3_data_imag = (ADC_DATA_WIDTH > AXIS_CORDIC_WIDTH) ? rx_ch3_q[ADC_DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH] : {rx_ch3_q,{(AXIS_CORDIC_WIDTH-ADC_DATA_WIDTH){1'b0}}}; +assign rotate_cart_ch4_data_real = (ADC_DATA_WIDTH > AXIS_CORDIC_WIDTH) ? rx_ch4_i[ADC_DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH] : {rx_ch4_i,{(AXIS_CORDIC_WIDTH-ADC_DATA_WIDTH){1'b0}}}; +assign rotate_cart_ch4_data_imag = (ADC_DATA_WIDTH > AXIS_CORDIC_WIDTH) ? rx_ch4_q[ADC_DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH] : {rx_ch4_q,{(AXIS_CORDIC_WIDTH-ADC_DATA_WIDTH){1'b0}}}; + +assign rotate_cart_ch3_data = {rotate_cart_ch3_data_imag,rotate_cart_ch3_data_real}; +assign rotate_cart_ch4_data = {rotate_cart_ch4_data_imag,rotate_cart_ch4_data_real}; + +assign {rx_ch3_rotate_q,rx_ch3_rotate_i} = rotate_dout_ch3_data; +assign {rx_ch4_rotate_q,rx_ch4_rotate_i} = rotate_dout_ch4_data; + +rotate_16b u_rotate_16b_ch3 +( + .aclk (clk ), // input wire aclk + .s_axis_phase_tvalid (rotate_phase_valid ), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata (rotate_phase_data ), // input wire [15 : 0] s_axis_phase_tdata + .s_axis_cartesian_tvalid(rotate_cart_valid ), // input wire s_axis_cartesian_tvalid + .s_axis_cartesian_tdata (rotate_cart_ch3_data ), // input wire [31 : 0] s_axis_cartesian_tdata + .m_axis_dout_tvalid (rotate_dout_ch3_valid ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (rotate_dout_ch3_data ) // output wire [31 : 0] m_axis_dout_tdata +); + +rotate_16b u_rotate_16b_ch4 +( + .aclk (clk ), // input wire aclk + .s_axis_phase_tvalid (rotate_phase_valid ), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata (rotate_phase_data ), // input wire [15 : 0] s_axis_phase_tdata + .s_axis_cartesian_tvalid(rotate_cart_valid ), // input wire s_axis_cartesian_tvalid + .s_axis_cartesian_tdata (rotate_cart_ch4_data ), // input wire [31 : 0] s_axis_cartesian_tdata + .m_axis_dout_tvalid (rotate_dout_ch4_valid ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (rotate_dout_ch4_data ) // output wire [31 : 0] m_axis_dout_tdata +); + + +localparam TOTAL_LATENCY = CORDIC_LATENCY+INTERP_FACTOR-1; + +reg [ADC_DATA_WIDTH-1 : 0] rx_ch1_i_delay [0 : TOTAL_LATENCY-1]; +reg [ADC_DATA_WIDTH-1 : 0] rx_ch1_q_delay [0 : TOTAL_LATENCY-1]; +reg [ADC_DATA_WIDTH-1 : 0] rx_ch2_i_delay [0 : TOTAL_LATENCY-1]; +reg [ADC_DATA_WIDTH-1 : 0] rx_ch2_q_delay [0 : TOTAL_LATENCY-1]; + +always @(posedge clk) begin + if (rst) begin + for (i = 0; i < TOTAL_LATENCY; i = i + 1) begin + rx_ch1_i_delay[i] <= 'b0; + rx_ch1_q_delay[i] <= 'b0; + rx_ch2_i_delay[i] <= 'b0; + rx_ch2_q_delay[i] <= 'b0; + end + end + else begin + for (i = 1; i < TOTAL_LATENCY; i = i + 1) begin + rx_ch1_i_delay[i] <= rx_ch1_i_delay[i-1]; + rx_ch1_q_delay[i] <= rx_ch1_q_delay[i-1]; + rx_ch2_i_delay[i] <= rx_ch2_i_delay[i-1]; + rx_ch2_q_delay[i] <= rx_ch2_q_delay[i-1]; + end + rx_ch1_i_delay[0] <= rx_ch1_i; + rx_ch1_q_delay[0] <= rx_ch1_q; + rx_ch2_i_delay[0] <= rx_ch2_i; + rx_ch2_q_delay[0] <= rx_ch2_q; + end +end + +reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch1_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch1_q_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch2_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch2_q_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch3_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch3_q_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch4_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch4_q_buf = 'b0; + +assign rx_cal_ch1_i = rx_cal_ch1_i_buf; +assign rx_cal_ch1_q = rx_cal_ch1_q_buf; +assign rx_cal_ch2_i = rx_cal_ch2_i_buf; +assign rx_cal_ch2_q = rx_cal_ch2_q_buf; +assign rx_cal_ch3_i = rx_cal_ch3_i_buf; +assign rx_cal_ch3_q = rx_cal_ch3_q_buf; +assign rx_cal_ch4_i = rx_cal_ch4_i_buf; +assign rx_cal_ch4_q = rx_cal_ch4_q_buf; + +always @(posedge clk) begin + if (rst) begin + rx_cal_ch1_i_buf <= 'b0; + rx_cal_ch1_q_buf <= 'b0; + rx_cal_ch2_i_buf <= 'b0; + rx_cal_ch2_q_buf <= 'b0; + rx_cal_ch3_i_buf <= 'b0; + rx_cal_ch3_q_buf <= 'b0; + rx_cal_ch4_i_buf <= 'b0; + rx_cal_ch4_q_buf <= 'b0; + end + else if (rotate_dout_ch3_valid) begin + rx_cal_ch1_i_buf <= rx_ch1_i_delay[relative_delay]; + rx_cal_ch1_q_buf <= rx_ch1_q_delay[relative_delay]; + rx_cal_ch2_i_buf <= -rx_ch2_i_delay[relative_delay]; + rx_cal_ch2_q_buf <= -rx_ch2_q_delay[relative_delay]; + rx_cal_ch3_i_buf <= rx_ch3_rotate_i[AXIS_CORDIC_WIDTH-1 -: ADC_DATA_WIDTH]; + rx_cal_ch3_q_buf <= rx_ch3_rotate_q[AXIS_CORDIC_WIDTH-1 -: ADC_DATA_WIDTH]; + rx_cal_ch4_i_buf <= -rx_ch4_rotate_i[AXIS_CORDIC_WIDTH-1 -: ADC_DATA_WIDTH]; + rx_cal_ch4_q_buf <= -rx_ch4_rotate_q[AXIS_CORDIC_WIDTH-1 -: ADC_DATA_WIDTH]; + end + else begin + rx_cal_ch1_i_buf <= rx_ch1_i; + rx_cal_ch1_q_buf <= rx_ch1_q; + rx_cal_ch2_i_buf <= rx_ch2_i; + rx_cal_ch2_q_buf <= rx_ch2_q; + rx_cal_ch3_i_buf <= rx_ch3_i; + rx_cal_ch3_q_buf <= rx_ch3_q; + rx_cal_ch4_i_buf <= rx_ch4_i; + rx_cal_ch4_q_buf <= rx_ch4_q; + end +end + +// +reg ad9361_2_cal_done_buf = 'b0; + +assign ad9361_2_cal_done = ad9361_2_cal_done_buf; +assign ad9361_cal_valid = ad9361_2_cal_done_buf; + +always @(posedge clk) begin + if (rst) begin + ad9361_2_cal_done_buf <= 'b0; + end + else begin + ad9361_2_cal_done_buf <= rotate_dout_ch3_valid; + end +end + +endmodule + + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2023/02/17 16:51:52 +// Design Name: +// Module Name: tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: testbench for [ad9361_phase_cal_fine] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +// ----------------------------------------------------------------------------- +// ----------------------- MATLAB Code for data generation --------------------- +// ----------------------------------------------------------------------------- +// %% File Header/文件说明 +// % +// % 调零算法对幅相一致性的è¦æ±‚较高，且 AD9361 多片åŒæ­¥çš„精度éšæœºæ€§è¾ƒå¤§ï¼Œå› æ­¤éœ€è¦å¯¹ +// % AD9361 多片åŒæ­¥è¯¯å·®è¿›è¡Œç²¾ç»†æ ¡å‡†ã€‚采用收å‘扩频ç çš„æ–¹å¼åœ¨æ ¡å‡†è¿‡ç¨‹ä¸­å¯¹ä¸¤ç‰‡ AD9361 +// % 的两个接收通é“进行幅相测é‡ï¼Œåœ¨æŽ¥æ”¶ç«¯ä½¿ç”¨åŠ æ³•å™¨è¿›è¡Œéžç›¸å¹²ç›¸å…³å³°ç´¯ç§¯ï¼Œç´¯ç§¯ N 个 +// % 符å·åŽå‡ºå³°ï¼Œæ ¹æ®ç›¸å…³å³°çš„高度差和相ä½å·®ï¼Œåœ¨æŽ¥æ”¶ç«¯å¯¹ä¿¡å·çš„幅度和相ä½è¿›è¡Œè¡¥å¿ã€‚ +// % +// clc; clear; close all; +// %% initial system parameters/åˆå§‹ç³»ç»Ÿå‚æ•° +// rng(0); +// Eb_N0 = 30; % energy per bit to noise power spectral density ratio +// interp = 8; % interpolation factor +// SNR = 10*log10(2/interp) + Eb_N0; % signal-to-noise power ration +// channelNum = 2; +// deltaAmp = 1-(2*rand-1)*0.05; % random amplitude error, range: [0.95,1.05] +// deltaAngRad = (2*rand-1)*pi; % random phase error, range: [-pi,pi] +// deltaAngDeg = deltaAngRad/pi*180; +// angleInit = 20/pi*180; + +// % standard pn sequence +// pnSequence = comm.PNSequence('Polynomial','x^7+x^6+1', ... +// 'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1); +// PRBS7 = pnSequence(); +// PRBS7_polar = 1-2*[PRBS7;0]; + +// chipLen = length(PRBS7_polar); % pn chip length +// accumSymbolNum = 16; +// totalSymbolNum = accumSymbolNum+1; + +// randomChipIndex_ch1 = randi(chipLen*interp*2-1)-chipLen*interp; % random rx chip index +// randomChipIndex_ch2 = randomChipIndex_ch1 + (randi(2*interp-1)-interp); % random rx chip index +// % randomChipIndex_ch1 = -2; % random rx chip index +// % randomChipIndex_ch2 = 5; % random rx chip index + +// %% +// % å‘é€ä¿¡å·ï¼šæ–¹æ³¢æˆåž‹ +// seqTx = kron(repmat(PRBS7_polar,totalSymbolNum,1),ones(interp,1)); + +// % 接收信å·ï¼šéšæœºåˆå§‹ç›¸ä½ï¼ŒåŠ å™ªï¼Œéšæœºå¹…度误差，éšæœºç›¸ä½è¯¯å·® +// seqRx = awgn(seqTx,SNR,'measured').*[1,deltaAmp].*[exp(1i*angleInit),... +// exp(1i*(angleInit+deltaAngRad))]; +// seqRx(:,1) = circshift(seqRx(:,1),randomChipIndex_ch1); +// seqRx(:,2) = circshift(seqRx(:,2),randomChipIndex_ch2); + +// rxdata = readmatrix("iladata_pn_trx_1.csv"); +// seqRx(:,1) = rxdata(1:chipLen*interp*totalSymbolNum,8) + 1i*rxdata(1:chipLen*interp*totalSymbolNum,9); +// seqRx(:,2) = rxdata(1:chipLen*interp*totalSymbolNum,12) + 1i*rxdata(1:chipLen*interp*totalSymbolNum,13); + +// % é™é‡‡æ ·ï¼Œä¸Ž Verilog 实现一样在ç ç‰‡ä¸­å¿ƒé‡‡æ · +// seqRxDown = zeros(chipLen*accumSymbolNum,channelNum,interp); + +// for i = 0:interp-1 +// % è¡¥å¿ Verilog 模å—的读数延迟 +// seqRxDown(:,:,i+1) = downsample(seqRx((1:accumSymbolNum*chipLen*interp)+2,:),interp,i); +// end + +// % å–符å·ä½ +// seqRxMsbReal = zeros(size(seqRxDown)); +// seqRxMsbImag = zeros(size(seqRxDown)); +// seqRxMsbReal(real(seqRxDown)>0) = 1; +// seqRxMsbReal(real(seqRxDown)<0) = -1; +// seqRxMsbImag(imag(seqRxDown)>0) = 1; +// seqRxMsbImag(imag(seqRxDown)<0) = -1; + +// % 符å·ä½ç´¯ç§¯ +// seqRxMsbRealAccum = zeros(chipLen,channelNum,interp); +// seqRxMsbImagAccum = zeros(chipLen,channelNum,interp); + +// for i = 0:chipLen-1 +// % PN ç åœ†å‘¨ç§»ä½ï¼Œé历所有 PN ç ç›¸ä½ +// PRBS7_cshift = circshift(repmat(PRBS7_polar,accumSymbolNum,1),-i); % è´Ÿå·ä¸ºäº†å’Œ Verilog 程åºå¯¹åº” +// % 累积，若当å‰æ¯”特与 PN ç ç›¸åŒï¼Œç»“æžœ +1ï¼›å¦åˆ™ç»“æžœ -1 +// seqRxMsbRealAccum(i+1,:,:) = sum(PRBS7_cshift==seqRxMsbReal)-... +// sum(PRBS7_cshift~=seqRxMsbReal); +// seqRxMsbImagAccum(i+1,:,:) = sum(PRBS7_cshift==seqRxMsbImag)-... +// sum(PRBS7_cshift~=seqRxMsbImag); +// end + +// seqRxMsbAccum = seqRxMsbRealAccum+1i*seqRxMsbImagAccum; + +// % 通过相关峰ä½ç½®åˆ¤æ–­ç›®æ ‡ä¿¡å·ä½ç½® +// maxPeakIndex = zeros(2,interp); + +// for i = 1:2 +// for j = 1:interp +// maxPeakIndex(i,j) = find(abs(seqRxMsbAccum(:,i,j))==max(abs(seqRxMsbAccum(:,i,j))),1); % PN ç ç›¸ä½ +// end +// end + +// maxPeakIndexDiff = zeros(channelNum,1); % 相ä½å·® + +// for i = 1:channelNum +// for j = 1:interp +// if (maxPeakIndex(i,j)==maxPeakIndex(i,1)) +// maxPeakIndexDiff(i) = j; +// end +// end +// end + +// % 以下æ¡ä»¶ä»…对åŒé€šé“有效 +// if (maxPeakIndex(1,1) == maxPeakIndex(2,1)) +// relativeDelay = maxPeakIndexDiff(2) - maxPeakIndexDiff(1); +// desiredPointIndex = [1,1]+[0,chipLen]; +// elseif (mod(maxPeakIndex(1,1)-1,chipLen) == mod(maxPeakIndex(2,1),chipLen)) +// relativeDelay = maxPeakIndexDiff(2) - maxPeakIndexDiff(1) + interp; +// desiredPointIndex = [1,2]+[0,chipLen]; +// elseif (mod(maxPeakIndex(1,1)+1,chipLen) == mod(maxPeakIndex(2,1),chipLen)) +// relativeDelay = maxPeakIndexDiff(2) - maxPeakIndexDiff(1) - interp; +// desiredPointIndex = [2,1]+[0,chipLen]; +// end + +// % 输入信å·ç´¯åŠ  +// seqRxDownAccum = squeeze(sum(reshape(seqRxDown(:,:,1),128,[],2),2)); +// % å–目标ä½ç½®ä¿¡å· +// desiredPoint = seqRxDownAccum(desiredPointIndex); + +// ampEst = abs(desiredPoint)./abs(desiredPoint(1)); +// angleEst = (angle(desiredPoint) - angle(desiredPoint(1)))/pi*180; + +// seqRxExport = round([real(seqRx(:,1)),imag(seqRx(:,1)),real(seqRx(:,2)),... +// imag(seqRx(:,2))]/max(abs(seqRx),[],'all')*(2^11-1)); +// writematrix(seqRxExport,'D:\fine_cal_data.txt'); + + +// ----------------------------------------------------------------------------- +// --------------------------------- Testbench --------------------------------- +// ----------------------------------------------------------------------------- +// module tb_ad9361_cal_fine; + +// localparam DATA_FILE_PATH = "D:\\fine_cal_data.txt"; +// localparam DATA_LEN = 16384; +// localparam DATA_WIDTH = 12; +// localparam ACCUM_SYMBOL_NUM = 4; + +// // localparam DATA_FILE_PATH = "D:\\iladata_pn_trx_4.csv"; +// // localparam DATA_LEN = 131072; +// // localparam DATA_WIDTH = 12; + +// reg clk = 'b0; +// reg rst = 1'b1; + +// reg ad9361_1_cal_start = 'b0; +// wire ad9361_1_cal_done ; +// reg ad9361_2_cal_start = 'b0; +// wire ad9361_2_cal_done ; +// wire ad9361_cal_result ; +// wire ad9361_cal_valid; +// reg ad9361_recal = 'b0; + +// // phase difference of 180 degree +// reg signed [11:0] rx_ch1_i = 'b0; +// reg signed [11:0] rx_ch1_q = 'b0; +// reg signed [11:0] rx_ch2_i = 'b0; +// reg signed [11:0] rx_ch2_q = 'b0; +// reg signed [11:0] rx_ch3_q = 'b0; +// reg signed [11:0] rx_ch3_i = 'b0; +// reg signed [11:0] rx_ch4_i = 'b0; +// reg signed [11:0] rx_ch4_q = 'b0; + +// wire [11:0] rx_cal_ch1_i; +// wire [11:0] rx_cal_ch2_i; +// wire [11:0] rx_cal_ch3_i; +// wire [11:0] rx_cal_ch4_i; +// wire [11:0] rx_cal_ch1_q; +// wire [11:0] rx_cal_ch2_q; +// wire [11:0] rx_cal_ch3_q; +// wire [11:0] rx_cal_ch4_q; + +// integer i = 0; +// integer r_file; + +// ad9361_phase_cal_fine #( +// .ACCUM_SYMBOL_NUM (ACCUM_SYMBOL_NUM ) +// ) u_ad9361_phase_cal +// ( +// // clock & reset +// .clk (clk ), // input clk +// .rst (rst ), // input rst +// // control interface +// .ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start +// .ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done +// .ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start +// .ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done +// .ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result +// .ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid +// .ad9361_recal (ad9361_recal ), // input ad9361_recal +// // input data interface +// .rx_ch1_i (rx_ch1_i ), // input [11:0] rx_ch1_i +// .rx_ch2_i (rx_ch2_i ), // input [11:0] rx_ch2_i +// .rx_ch3_i (rx_ch3_i ), // input [11:0] rx_ch3_i +// .rx_ch4_i (rx_ch4_i ), // input [11:0] rx_ch4_i +// .rx_ch1_q (rx_ch1_q ), // input [11:0] rx_ch1_q +// .rx_ch2_q (rx_ch2_q ), // input [11:0] rx_ch2_q +// .rx_ch3_q (rx_ch3_q ), // input [11:0] rx_ch3_q +// .rx_ch4_q (rx_ch4_q ), // input [11:0] rx_ch4_q +// // output data interface +// .rx_cal_ch1_i (rx_cal_ch1_i ), // output [11:0] rx_cal_ch1_i +// .rx_cal_ch2_i (rx_cal_ch2_i ), // output [11:0] rx_cal_ch2_i +// .rx_cal_ch3_i (rx_cal_ch3_i ), // output [11:0] rx_cal_ch3_i +// .rx_cal_ch4_i (rx_cal_ch4_i ), // output [11:0] rx_cal_ch4_i +// .rx_cal_ch1_q (rx_cal_ch1_q ), // output [11:0] rx_cal_ch1_q +// .rx_cal_ch2_q (rx_cal_ch2_q ), // output [11:0] rx_cal_ch2_q +// .rx_cal_ch3_q (rx_cal_ch3_q ), // output [11:0] rx_cal_ch3_q +// .rx_cal_ch4_q (rx_cal_ch4_q ) // output [11:0] rx_cal_ch4_q +// ); + +// initial begin +// r_file = $fopen(DATA_FILE_PATH,"r"); +// #102 +// rst = 1'b0; +// #100 +// ad9361_1_cal_start = 1'b1; +// end + +// always @(posedge clk) begin +// if (ad9361_1_cal_start) begin +// if (i == DATA_LEN-1) begin +// $fscanf(r_file,"%d,%d,%d,%d", +// rx_ch2_i, +// rx_ch2_q, +// rx_ch4_i, +// rx_ch4_q); +// $fclose(r_file); +// r_file = $fopen(DATA_FILE_PATH,"r"); +// i <= 0; +// end +// else begin +// $fscanf(r_file,"%d,%d,%d,%d", +// rx_ch2_i, +// rx_ch2_q, +// rx_ch4_i, +// rx_ch4_q); +// i <= i + 1; +// end +// end +// end + +// always begin +// #10 clk = ~clk; +// end + +// // initial begin +// // #10000 +// // ad9361_recal = 1'b1; +// // #20 +// // ad9361_recal = 1'b0; +// // end + +// always @(posedge clk) begin +// if (ad9361_1_cal_done) begin +// ad9361_2_cal_start <= 1'b1; +// end +// else begin +// ad9361_2_cal_start <= 1'b0; +// end +// end + +// always @(posedge clk) begin +// if (ad9361_2_cal_done) begin +// #2000 +// ad9361_recal <= 1'b1; +// end +// else begin +// ad9361_recal <= 1'b0; +// end +// end + +// endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/null_ctrl.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/null_ctrl.v new file mode 100644 index 0000000..a6de9f5 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/null_ctrl.v @@ -0,0 +1,800 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 07/17/2023 05:26:54 PM +// Design Name: +// Module Name: null_ctrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module null_ctrl +#( + parameter ADC_WIDTH = 12 , + parameter CH_NUM = 4 , + parameter SYNC_HOP_INTVL = 48*1000 , // 1 ms of 48M clock, must > 48*200 + parameter STABLE_CNT_MOD = 48*5 , // 5 us of 48M clock + parameter SNAPSHOT_NUM = 2048 , + parameter GUARD_CNT_MOD = 48*50 , // 50 us of 48M clock + parameter ACCUM_WIDTH = 32 , + parameter ACORR_WIDTH = 2*ADC_WIDTH, + parameter WEIGHT_WIDTH = 16 , + parameter OUTPUT_WIDTH = ADC_WIDTH, + parameter LCMV_WIDTH = ADC_WIDTH + WEIGHT_WIDTH + $clog2(CH_NUM) +) +( + // *************************************************************************** + // ***************************** clock & reset ******************************* + // *************************************************************************** + input clk , + input clk_phy , + input rst , + + // + input hop_flag_in_phy , + input sync_flag_phy , + input lcmv_en_phy , + output hop_flag_out , + // *************************************************************************** + // **************************** ADC Input Data ******************************* + // *************************************************************************** + input adc_din_valid , + input [CH_NUM*ADC_WIDTH-1 : 0] adc_din_real , + input [CH_NUM*ADC_WIDTH-1 : 0] adc_din_imag , + + // *************************************************************************** + // **************************** Autocorrelation ****************************** + // *************************************************************************** + output acorr_din_valid , + output [CH_NUM*ADC_WIDTH-1 : 0] acorr_din_real , + output [CH_NUM*ADC_WIDTH-1 : 0] acorr_din_imag , + + input acorr_dout_valid , + input [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] acorr_dout_real , + input [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] acorr_dout_imag , + + // *************************************************************************** + // **************************** Accumulation ********************************* + // *************************************************************************** + output accum_rst , + + output accum_din_valid , + output [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] accum_din_real , + output [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] accum_din_imag , + + input accum_dout_valid , + input [CH_NUM*CH_NUM*ACCUM_WIDTH-1:0] accum_dout_real , + input [CH_NUM*CH_NUM*ACCUM_WIDTH-1:0] accum_dout_imag , + + // *************************************************************************** + // ************************* Parallel to Serial ****************************** + // *************************************************************************** + output stream_fifo_rst , + + output stream_din_valid , + output [CH_NUM*CH_NUM*ACCUM_WIDTH-1 : 0] stream_din_real , + output [CH_NUM*CH_NUM*ACCUM_WIDTH-1 : 0] stream_din_imag , + + // *************************************************************************** + // ************************* Serial to Parallel ****************************** + // *************************************************************************** + output weight_fifo_rst , + + input weight_dout_valid , + input [CH_NUM*WEIGHT_WIDTH-1 : 0] weight_dout_real , + input [CH_NUM*WEIGHT_WIDTH-1 : 0] weight_dout_imag , + + // *************************************************************************** + // **************************** Spatial Filter ******************************* + // *************************************************************************** + // input weight vector + output filter_weight_valid , + output [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_real , + output [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_imag , + + // input adc data + output filter_din_valid , + output [CH_NUM*ADC_WIDTH-1 : 0] filter_din_real , + output [CH_NUM*ADC_WIDTH-1 : 0] filter_din_imag , + + // output data + input filter_dout_valid , + input [LCMV_WIDTH-1 : 0] filter_dout_real , + input [LCMV_WIDTH-1 : 0] filter_dout_imag , + + // *************************************************************************** + // *************************** Output Data Port ****************************** + // *************************************************************************** + output null_dout_valid , + output [OUTPUT_WIDTH-1 : 0] null_dout_real , + output [OUTPUT_WIDTH-1 : 0] null_dout_imag +); + +localparam RAM_HOP_DEPTH = 9600; + +// hop flag delay of data segment when lcmv is enabled +// 1 for rom addr reset +// 1 for rom read data +// 7 for spatial filter +// 1 for buffering spatial filter input data - whether last or current hop +// 1 for buffering spatial filter output data - whether lcmv or das +localparam LCMV_DELAY = RAM_HOP_DEPTH + 11; + +// hop flag delay of data segment when lcmv is enabled +// 2 for multi-channel addition +// 1 for buffering output data +localparam DAS_DELAY = 3; + +localparam CMPLX_DIM = 2; +localparam NULL_DELAY = RAM_HOP_DEPTH + 6; +localparam DAS_WIDTH = ADC_WIDTH + $clog2(CH_NUM); +// autocorrelation state machine +localparam ACORR_STATE_NUM = 4; +localparam ACORR_STATE_IDLE = 0; +localparam ACORR_STATE_STABLE = 1; // wait until rf is stable +localparam ACORR_STATE_CALC = 2; // autocorrelation calculation and formatting +localparam ACORR_STATE_GUARD = 3; // guard for data transmission and inverse calculation + +integer i; + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Clock Domain Crossing ///////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +wire hop_flag_in ; // input hop flag, pulse, level detection +wire sync_flag ; // input sync segment indicator, 1 for sync segment, 0 for + // data segment, level, level detection +wire lcmv_en ; // input nulling algorithm enable control, 1 for enable, 2 + // for disable, level, level detection. If frequency + // hopping is enabled in sync segment, nulling should be + // turned off, because spatial anti-jamming cannot work + // properly in this scenario. +// wire hop_flag_out; // output hop flag, pulse + +// hop_flag_in, input +xpm_cdc_pulse #( + .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 + .INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .REG_OUTPUT (1), // DECIMAL; 0=disable registered output, 1=enable registered output + .RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset + .SIM_ASSERT_CHK (1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages +) u_hop_flag_in +( + .dest_pulse (hop_flag_in ), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse + // transfer is correctly initiated on src_pulse input. This output is + // combinatorial unless REG_OUTPUT is set to 1. + .dest_clk (clk ), // 1-bit input: Destination clock. + .dest_rst (1'b1 ), // 1-bit input: optional; required when RST_USED = 1 + .src_clk (clk_phy ), // 1-bit input: Source clock. + .src_pulse (hop_flag_in_phy), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the + // destination clock domain. The minimum gap between each pulse transfer must be + // at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured + // between the falling edge of a src_pulse to the rising edge of the next + // src_pulse. This minimum gap will guarantee that each rising edge of src_pulse + // will generate a pulse the size of one dest_clk period in the destination + // clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while + // src_rst and/or dest_rst are asserted. + .src_rst (1'b1 ) // 1-bit input: optional; required when RST_USED = 1 +); + +// sync_flag, input +xpm_cdc_single #( + .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 + .INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages + .SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input +) +u_sync_flag ( + .dest_out (sync_flag ), // 1-bit output: src_in synchronized to the destination clock domain. This output is + // registered. + .dest_clk (clk ), // 1-bit input: Clock signal for the destination clock domain. + .src_clk (clk_phy ), // 1-bit input: optional; required when SRC_INPUT_REG = 1 + .src_in (sync_flag_phy ) // 1-bit input: Input signal to be synchronized to dest_clk domain. +); + +// lcmv_en, input +xpm_cdc_single #( + .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 + .INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages + .SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input +) +u_lcmv_en ( + .dest_out (lcmv_en ), // 1-bit output: src_in synchronized to the destination clock domain. This output is + // registered. + .dest_clk (clk ), // 1-bit input: Clock signal for the destination clock domain. + .src_clk (clk_phy ), // 1-bit input: optional; required when SRC_INPUT_REG = 1 + .src_in (lcmv_en_phy ) // 1-bit input: Input signal to be synchronized to dest_clk domain. +); + +// hop_flag_out, output +// xpm_cdc_pulse #( +// .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 +// .INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values +// .REG_OUTPUT (1), // DECIMAL; 0=disable registered output, 1=enable registered output +// .RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset +// .SIM_ASSERT_CHK (1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages +// ) u_hop_flag_out +// ( +// .dest_pulse (hop_flag_out_phy ), +// .dest_clk (clk_phy ), +// .dest_rst (1'b1 ), +// .src_clk (clk ), +// .src_pulse (hop_flag_out ), +// .src_rst (1'b1 ) +// ); + + +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////// Autocorrelation Control //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + +// <---------------------------------------------------------------------------> +// <-------------------- sync segment hop flag generation ---------------------> +// <---------------------------------------------------------------------------> +reg [$clog2(SYNC_HOP_INTVL)-1 : 0] sync_hop_cnt = 'b0; +reg sync_hop_flag = 'b0; + +always @(posedge clk) begin + if (rst) begin + sync_hop_cnt <= 'b0; + sync_hop_flag <= 'b0; + end + else if (sync_flag && lcmv_en) begin + // During sync segment and when nulling algorithm is enabled + + // Counter period is controlled by [SYNC_HOP_INTVL] + sync_hop_cnt <= (sync_hop_cnt == SYNC_HOP_INTVL - 1) ? 'b0 : sync_hop_cnt + 1'b1; + // For protection, assert 10 us after entering sync segment + sync_hop_flag <= (sync_hop_cnt == 48*10 - 1) ? 1'b1 : 'b0; + end + else begin + sync_hop_cnt <= 'b0; + sync_hop_flag <= 'b0; + end +end + +// <---------------------------------------------------------------------------> +// <---------------------- autocorrelation state machine ----------------------> +// <---------------------------------------------------------------------------> +reg [$clog2(ACORR_STATE_NUM)-1 : 0] acorr_curr_state = ACORR_STATE_IDLE; +reg [$clog2(ACORR_STATE_NUM)-1 : 0] acorr_next_state = ACORR_STATE_IDLE; +reg [$clog2(STABLE_CNT_MOD)-1 : 0] stable_cnt = 'b0; +reg [$clog2(SNAPSHOT_NUM)-1 : 0] snapshot_cnt = 'b0; +reg [$clog2(GUARD_CNT_MOD)-1 : 0] guard_cnt = 'b0; +reg snapshot_valid = 'b0; +reg accum_rst_buf = 'b0; +reg fifo_cdc_rst_buf = 'b0; + +// 1st always block, sequential state transition +always @(posedge clk) begin + if (rst) begin + acorr_curr_state <= ACORR_STATE_IDLE; + end + else begin + acorr_curr_state <= acorr_next_state; + end +end + +// 2nd always block, combinational condition judgment +always @(*) begin + case (acorr_curr_state) + ACORR_STATE_IDLE: begin + if (adc_din_valid && lcmv_en) begin + // if adc data is valid & lcmv is enabled + if ((sync_flag && sync_hop_flag) || (~sync_flag && hop_flag_in)) begin + acorr_next_state = ACORR_STATE_STABLE; + end + else begin + acorr_next_state = ACORR_STATE_IDLE; + end + end + else begin + acorr_next_state = ACORR_STATE_IDLE; + end + end + ACORR_STATE_STABLE: begin + if (stable_cnt == STABLE_CNT_MOD-1) begin + acorr_next_state = ACORR_STATE_CALC; + end + else begin + acorr_next_state = ACORR_STATE_STABLE; + end + end + ACORR_STATE_CALC: begin + if (snapshot_cnt == SNAPSHOT_NUM-1) begin + acorr_next_state = ACORR_STATE_GUARD; + end + else begin + acorr_next_state = ACORR_STATE_CALC; + end + end + ACORR_STATE_GUARD: begin + if (guard_cnt == GUARD_CNT_MOD-1) begin + acorr_next_state = ACORR_STATE_IDLE; + end + else begin + acorr_next_state = ACORR_STATE_GUARD; + end + end + default: begin + acorr_next_state = ACORR_STATE_IDLE; + end + endcase +end + +// 3rd always block, the sequential FSM output +always @(posedge clk) begin + if (rst) begin + stable_cnt <= 'b0; + snapshot_cnt <= 'b0; + guard_cnt <= 'b0; + snapshot_valid <= 'b0; + accum_rst_buf <= 'b0; + end + else begin + case (acorr_curr_state) + ACORR_STATE_STABLE: begin + stable_cnt <= stable_cnt + 1'b1; + snapshot_cnt <= 'b0; + guard_cnt <= 'b0; + end + ACORR_STATE_CALC: begin + stable_cnt <= stable_cnt; + snapshot_cnt <= snapshot_cnt + 1'b1; + guard_cnt <= 'b0; + end + ACORR_STATE_GUARD: begin + stable_cnt <= stable_cnt; + snapshot_cnt <= snapshot_cnt; + guard_cnt <= guard_cnt + 1'b1; + end + default: begin + stable_cnt <= 'b0; + snapshot_cnt <= 'b0; + guard_cnt <= 'b0; + end + endcase + + case (acorr_next_state) + ACORR_STATE_CALC: begin + snapshot_valid <= 1'b1; + end + default: begin + snapshot_valid <= 'b0; + end + endcase + + case (acorr_curr_state) + ACORR_STATE_STABLE: begin + accum_rst_buf <= 1'b1; + fifo_cdc_rst_buf <= 1'b1; + end + default: begin + accum_rst_buf <= 'b0; + fifo_cdc_rst_buf <= 'b0; + end + endcase + end +end + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Data Buffering Control //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + +// <---------------------------------------------------------------------------> +// <--------------- store current hop & restore last hop weight ---------------> +// <---------------------------------------------------------------------------> +reg sync_hop_flag_d = 'b0; // wait for ram data +reg hop_flag_in_d = 'b0; // wait for ram data +reg curr_weight_valid = 'b0; +reg [CH_NUM*WEIGHT_WIDTH-1 : 0] curr_weight_real = 'b0; +reg [CH_NUM*WEIGHT_WIDTH-1 : 0] curr_weight_imag = 'b0; +reg last_weight_valid = 'b0; +reg [CH_NUM*WEIGHT_WIDTH-1 : 0] last_weight_real = 'b0; +reg [CH_NUM*WEIGHT_WIDTH-1 : 0] last_weight_imag = 'b0; + +always @(posedge clk) begin + if (rst) begin + sync_hop_flag_d <= 'b0; + hop_flag_in_d <= 'b0; + + curr_weight_valid <= 'b0; + curr_weight_real <= 'b0; + curr_weight_imag <= 'b0; + + last_weight_valid <= 'b0; + last_weight_real <= 'b0; + last_weight_imag <= 'b0; + end + else if (lcmv_en) begin + // If lcmv is enabled + + // Delay 1 clock cycle for adc data read + sync_hop_flag_d <= sync_hop_flag; + hop_flag_in_d <= hop_flag_in; + + curr_weight_valid <= (weight_dout_valid) ? 1'b1 : 'b0; + curr_weight_real <= (weight_dout_valid) ? weight_dout_real : curr_weight_real; + curr_weight_imag <= (weight_dout_valid) ? weight_dout_imag : curr_weight_imag; + + if ((sync_flag && sync_hop_flag_d) || (~sync_flag && hop_flag_in_d)) begin + last_weight_valid <= 1'b1; + last_weight_real <= curr_weight_real; + last_weight_imag <= curr_weight_imag; + end + else begin + last_weight_valid <= last_weight_valid; + last_weight_real <= last_weight_real; + last_weight_imag <= last_weight_imag; + end + + end + else begin + sync_hop_flag_d <= 'b0; + hop_flag_in_d <= 'b0; + + curr_weight_valid <= 'b0; + curr_weight_real <= 'b0; + curr_weight_imag <= 'b0; + + last_weight_valid <= 'b0; + last_weight_real <= 'b0; + last_weight_imag <= 'b0; + end +end + +// <---------------------------------------------------------------------------> +// <---------------- store current hop & restore last hop data ----------------> +// <---------------------------------------------------------------------------> +// address counter +reg [$clog2(RAM_HOP_DEPTH)-1 : 0] hop_data_cnt = 'b0; + +always @(posedge clk) begin + if (rst) begin + hop_data_cnt <= 'b0; + end + else if(adc_din_valid && lcmv_en && ~sync_flag) begin + // if adc data is valid & lcmv is enabled & during data segment + if (hop_flag_in) begin + hop_data_cnt <= 'b0; + end + else begin + hop_data_cnt <= (hop_data_cnt == RAM_HOP_DEPTH-1) ? 'b0 : hop_data_cnt + 1'b1; + end + end + else begin + hop_data_cnt <= 'b0; + end +end + +// data interface +wire [CMPLX_DIM*CH_NUM*ADC_WIDTH-1 : 0] curr_hop_data; +wire [CMPLX_DIM*CH_NUM*ADC_WIDTH-1 : 0] last_hop_data; +reg last_hop_valid = 'b0; + +wire [CH_NUM*ADC_WIDTH-1 : 0] last_data_real; +wire [CH_NUM*ADC_WIDTH-1 : 0] last_data_imag; + +assign curr_hop_data = {adc_din_imag,adc_din_real}; +assign {last_data_imag,last_data_real} = last_hop_data; + +always @(posedge clk) begin + if (rst) begin + last_hop_valid <= 'b0; + end + else if(adc_din_valid && lcmv_en && ~sync_flag) begin + // if adc data is valid & lcmv is enabled & during data segment + last_hop_valid <= adc_din_valid; + end + else begin + last_hop_valid <= 'b0; + end +end + +ram_hop_data u_ram_hop_data +( + .clka (clk ), // input wire clka + .wea (adc_din_valid ), // input wire [0 : 0] wea + .addra(hop_data_cnt ), // input wire [13 : 0] addra + .dina (curr_hop_data ), // input wire [95 : 0] dina + .douta(last_hop_data ) // output wire [95 : 0] douta +); + +// <---------------------------------------------------------------------------> +// <----------------- hop flag buffering when lcmv is enabled -----------------> +// <---------------------------------------------------------------------------> +reg [$clog2(LCMV_DELAY)-1 : 0] lcmv_hop_cnt_1 = 'b0; +reg [$clog2(LCMV_DELAY)-1 : 0] lcmv_hop_cnt_2 = 'b0; + +always @(posedge clk) begin + if (rst) begin + lcmv_hop_cnt_1 <= 'b0; + lcmv_hop_cnt_2 <= 'b0; + end + else if (lcmv_en && ~sync_flag) begin + if (hop_flag_in) begin + if (lcmv_hop_cnt_1 == 'b0 && lcmv_hop_cnt_2 == 'b0) begin + lcmv_hop_cnt_1 <= 1'b1; + lcmv_hop_cnt_2 <= 'b0; + end + else if (lcmv_hop_cnt_1 != 'b0 && lcmv_hop_cnt_2 == 'b0) begin + lcmv_hop_cnt_1 <= (lcmv_hop_cnt_1 == LCMV_DELAY-1) ? 'b0 : lcmv_hop_cnt_1 + 1'b1; + lcmv_hop_cnt_2 <= 1'b1; + end + else if (lcmv_hop_cnt_1 == 'b0 && lcmv_hop_cnt_2 != 'b0) begin + lcmv_hop_cnt_1 <= 1'b1; + lcmv_hop_cnt_2 <= (lcmv_hop_cnt_2 == LCMV_DELAY-1) ? 'b0 : lcmv_hop_cnt_2 + 1'b1; + end + else begin + lcmv_hop_cnt_1 <= (lcmv_hop_cnt_1 == LCMV_DELAY-1) ? 'b0 : lcmv_hop_cnt_1 + 1'b1; + lcmv_hop_cnt_2 <= (lcmv_hop_cnt_2 == LCMV_DELAY-1) ? 'b0 : lcmv_hop_cnt_2 + 1'b1; + end + end + else begin + // behaviour of [lcmv_hop_cnt_1] when [hop_flag_in] does not assert + if (lcmv_hop_cnt_1 != 'b0) begin + lcmv_hop_cnt_1 <= (lcmv_hop_cnt_1 == LCMV_DELAY-1) ? 'b0 : lcmv_hop_cnt_1 + 1'b1; + end + else begin + lcmv_hop_cnt_1 <= 'b0; + end + // behaviour of [lcmv_hop_cnt_2] when [hop_flag_in] does not assert + if (lcmv_hop_cnt_2 != 'b0) begin + lcmv_hop_cnt_2 <= (lcmv_hop_cnt_2 == LCMV_DELAY-1) ? 'b0 : lcmv_hop_cnt_2 + 1'b1; + end + else begin + lcmv_hop_cnt_2 <= 'b0; + end + + end + end + else begin + lcmv_hop_cnt_1 <= 'b0; + lcmv_hop_cnt_2 <= 'b0; + end +end + +// <---------------------------------------------------------------------------> +// <----------------- hop flag buffering when das is enabled ------------------> +// <---------------------------------------------------------------------------> +reg [$clog2(DAS_DELAY)-1 : 0] das_hop_cnt = 'b0; + +always @(posedge clk) begin + if (rst) begin + das_hop_cnt <= 'b0; + end + else if (~lcmv_en && ~sync_flag) begin + if (hop_flag_in) begin + das_hop_cnt <= 1'b1; + end + else if (das_hop_cnt != 0) begin + das_hop_cnt <= (das_hop_cnt == DAS_DELAY-1) ? 'b0 : das_hop_cnt + 1'b1; + end + else begin + das_hop_cnt <= 'b0; + end + end + else begin + das_hop_cnt <= 'b0; + end +end + +reg hop_flag_out_buf = 'b0; + +assign hop_flag_out = hop_flag_out_buf; + +always @(posedge clk) begin + if (rst) begin + hop_flag_out_buf <= 'b0; + end + else if (lcmv_hop_cnt_1 == LCMV_DELAY-1 || lcmv_hop_cnt_2 == LCMV_DELAY-1 || das_hop_cnt == DAS_DELAY-1) begin + hop_flag_out_buf <= 1'b1; + end + else begin + hop_flag_out_buf <= 'b0; + end +end + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////// Delay and Sum ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +wire das_valid; +wire [DAS_WIDTH-1 : 0] das_real; +wire [DAS_WIDTH-1 : 0] das_imag; + +wire [LCMV_WIDTH-1 : 0] das_real_ext; +wire [LCMV_WIDTH-1 : 0] das_imag_ext; + +assign das_real_ext = {das_real,{(LCMV_WIDTH-DAS_WIDTH){1'b0}}}; +assign das_imag_ext = {das_imag,{(LCMV_WIDTH-DAS_WIDTH){1'b0}}}; + +adder_tree_ppl #( + .DATA_I_WIDTH (ADC_WIDTH ), + .DATA_NUM (CH_NUM ) +) u_das_add_ppl_real ( + // clock & reset + .clk (clk ), + .rst (rst ), + + // input data + .din_valid (adc_din_valid ), + .din_data (adc_din_real ), + + // output data + .dout_valid (das_valid ), + .dout_data (das_real ) +); + +adder_tree_ppl #( + .DATA_I_WIDTH (ADC_WIDTH ), + .DATA_NUM (CH_NUM ) +) u_das_add_ppl_imag ( + // clock & reset + .clk (clk ), + .rst (rst ), + + // input data + .din_valid (adc_din_valid ), + .din_data (adc_din_imag ), + + // output data + .dout_valid ( ), + .dout_data (das_imag ) +); + + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////// Output Data Control ////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +reg null_dout_valid_buf = 'b0; +reg [OUTPUT_WIDTH-1 : 0] null_dout_real_buf = 'b0; +reg [OUTPUT_WIDTH-1 : 0] null_dout_imag_buf = 'b0; + +assign null_dout_valid = null_dout_valid_buf; +assign null_dout_real = null_dout_real_buf ; +assign null_dout_imag = null_dout_imag_buf ; + +if (OUTPUT_WIDTH <= LCMV_WIDTH) begin + // truncate msb + always @(posedge clk) begin + if (rst) begin + null_dout_valid_buf <= 'b0; + null_dout_real_buf <= 'b0; + null_dout_imag_buf <= 'b0; + end + else if (lcmv_en) begin + null_dout_valid_buf <= filter_dout_valid; + null_dout_real_buf <= filter_dout_real[LCMV_WIDTH-1 -: OUTPUT_WIDTH]; + null_dout_imag_buf <= filter_dout_imag[LCMV_WIDTH-1 -: OUTPUT_WIDTH]; + end + else begin + null_dout_valid_buf <= das_valid; + null_dout_real_buf <= das_real_ext[LCMV_WIDTH-1 -: OUTPUT_WIDTH]; + null_dout_imag_buf <= das_imag_ext[LCMV_WIDTH-1 -: OUTPUT_WIDTH]; + end + end +end +else begin // if (OUTPUT_WIDTH > LCMV_WIDTH) + // append zeros to fit output data width + always @(posedge clk) begin + if (rst) begin + null_dout_valid_buf <= 'b0; + null_dout_real_buf <= 'b0; + null_dout_imag_buf <= 'b0; + end + else if (lcmv_en) begin + null_dout_valid_buf <= filter_dout_valid; + null_dout_real_buf <= {filter_dout_real,{(OUTPUT_WIDTH-LCMV_WIDTH){1'b0}}}; + null_dout_imag_buf <= {filter_dout_imag,{(OUTPUT_WIDTH-LCMV_WIDTH){1'b0}}}; + end + else begin + null_dout_valid_buf <= das_valid; + null_dout_real_buf <= {das_real_ext,{(OUTPUT_WIDTH-LCMV_WIDTH){1'b0}}}; + null_dout_imag_buf <= {das_imag_ext,{(OUTPUT_WIDTH-LCMV_WIDTH){1'b0}}}; + end + end +end + + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////// Submodule Interface ////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + +// ADC Input Data -> Autocorrelation +assign acorr_din_valid = snapshot_valid; +assign acorr_din_real = adc_din_real; +assign acorr_din_imag = adc_din_imag; + +// Autocorrelation -> Accumulation +assign accum_rst = accum_rst_buf; +assign accum_din_valid = acorr_dout_valid; +assign accum_din_real = acorr_dout_real; +assign accum_din_imag = acorr_dout_imag; + +// Accumulation -> Parallel to Serial +assign stream_fifo_rst = fifo_cdc_rst_buf; +assign stream_din_valid = accum_dout_valid; +assign stream_din_real = accum_dout_real; +assign stream_din_imag = accum_dout_imag; + +// Serial to Parallel +assign weight_fifo_rst = fifo_cdc_rst_buf; + +// Spatial Filter +reg filter_weight_valid_buf = 'b0; +reg [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_real_buf = 'b0; +reg [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_imag_buf = 'b0; + +reg filter_din_valid_buf = 'b0; +reg [CH_NUM*ADC_WIDTH-1 : 0] filter_din_real_buf = 'b0; +reg [CH_NUM*ADC_WIDTH-1 : 0] filter_din_imag_buf = 'b0; + +assign filter_weight_valid = filter_weight_valid_buf; +assign filter_weight_real = filter_weight_real_buf ; +assign filter_weight_imag = filter_weight_imag_buf ; + +assign filter_din_valid = filter_din_valid_buf; +assign filter_din_real = filter_din_real_buf ; +assign filter_din_imag = filter_din_imag_buf ; + +always @(posedge clk) begin + if (rst) begin + filter_weight_valid_buf <= 'b0; + filter_weight_real_buf <= 'b0; + filter_weight_imag_buf <= 'b0; + + filter_din_valid_buf <= 'b0; + filter_din_real_buf <= 'b0; + filter_din_imag_buf <= 'b0; + end + else if (lcmv_en) begin + if (sync_flag) begin + filter_weight_valid_buf <= curr_weight_valid; + filter_weight_real_buf <= curr_weight_real ; + filter_weight_imag_buf <= curr_weight_imag ; + + filter_din_valid_buf <= adc_din_valid ; + filter_din_real_buf <= adc_din_real ; + filter_din_imag_buf <= adc_din_imag ; + end + else begin + filter_weight_valid_buf <= last_weight_valid; + filter_weight_real_buf <= last_weight_real ; + filter_weight_imag_buf <= last_weight_imag ; + + filter_din_valid_buf <= last_hop_valid; + filter_din_real_buf <= last_data_real ; + filter_din_imag_buf <= last_data_imag ; + end + end + else begin + filter_weight_valid_buf <= 'b0; + filter_weight_real_buf <= 'b0; + filter_weight_imag_buf <= 'b0; + + filter_din_valid_buf <= 'b0; + filter_din_real_buf <= 'b0; + filter_din_imag_buf <= 'b0; + end +end + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/phase_comp.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/phase_comp.v new file mode 100644 index 0000000..617439e --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/phase_comp.v @@ -0,0 +1,130 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/17/2023 03:30:04 PM +// Design Name: +// Module Name: phase_comp +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// 20230713-1529 - 由于 Cordic IP 核会将输入信å·è¿›è¡Œç¼©æ”¾ï¼Œä¸ºé¿å…缩放åŽæº¢å‡ºï¼Œå°† +// Cordic 的输入改为至少两个符å·ä½ã€‚ +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module phase_comp +#( + parameter DATA_WIDTH = 12, + parameter CORDIC_WIDTH = 16, + parameter CH_NUM = 4 +) +( + // clock & reset + input clk , + input rst , + + // input data + input din_valid , + input [CH_NUM*CORDIC_WIDTH-1:0] phase , + input [CH_NUM*DATA_WIDTH-1:0] din_real , + input [CH_NUM*DATA_WIDTH-1:0] din_imag , + + // output data + output dout_valid , + output [CH_NUM*DATA_WIDTH-1:0] dout_real, + output [CH_NUM*DATA_WIDTH-1:0] dout_imag +); + +genvar m; + +localparam AXIS_CORDIC_WIDTH = 8*((CORDIC_WIDTH-1)/8+1); + +// prepare cordic input data +wire [AXIS_CORDIC_WIDTH-1:0] din_real_array [0:CH_NUM-1]; +wire [AXIS_CORDIC_WIDTH-1:0] din_imag_array [0:CH_NUM-1]; +wire [AXIS_CORDIC_WIDTH-1:0] phase_array [0:CH_NUM-1]; + +for(m = 0; m < CH_NUM; m = m + 1) begin: array_convert + if (CORDIC_WIDTH > DATA_WIDTH+1) begin + // append zeros to fit cordic input with, sign-bit extension to fit 8 bit axis format, keep at least 2 sign-bits for cordic scaling + assign din_real_array[m] = {{(AXIS_CORDIC_WIDTH-CORDIC_WIDTH+1){din_real[(m+1)*DATA_WIDTH-1]}},din_real[m*DATA_WIDTH +: DATA_WIDTH],{(CORDIC_WIDTH-DATA_WIDTH-1){1'b0}}}; + assign din_imag_array[m] = {{(AXIS_CORDIC_WIDTH-CORDIC_WIDTH+1){din_imag[(m+1)*DATA_WIDTH-1]}},din_imag[m*DATA_WIDTH +: DATA_WIDTH],{(CORDIC_WIDTH-DATA_WIDTH-1){1'b0}}}; + end + else begin + // truncate msb, keep at least 2 sign-bits for cordic scaling + assign din_real_array[m] = {din_real[(m+1)*DATA_WIDTH-1],din_real[(m+1)*DATA_WIDTH-1 -: (AXIS_CORDIC_WIDTH-1)]}; + assign din_imag_array[m] = {din_imag[(m+1)*DATA_WIDTH-1],din_imag[(m+1)*DATA_WIDTH-1 -: (AXIS_CORDIC_WIDTH-1)]}; + end + + if (AXIS_CORDIC_WIDTH > CORDIC_WIDTH) begin + // sign-bit extension to fit 8 bit axis format + assign phase_array[m] = {{(AXIS_CORDIC_WIDTH-CORDIC_WIDTH){phase[(m+1)*CORDIC_WIDTH-1]}},phase[m*CORDIC_WIDTH +: CORDIC_WIDTH]}; + end + else begin + // truncate msb + assign phase_array[m] = phase[(m+1)*CORDIC_WIDTH-1 -: AXIS_CORDIC_WIDTH]; + end +end + +// output data & cordic interface +wire [AXIS_CORDIC_WIDTH-1:0] rotate_real_array [0:CH_NUM-1]; +wire [AXIS_CORDIC_WIDTH-1:0] rotate_imag_array [0:CH_NUM-1]; + +wire [DATA_WIDTH-1:0] dout_real_array [0:CH_NUM-1]; +wire [DATA_WIDTH-1:0] dout_imag_array [0:CH_NUM-1]; + +for(m = 0; m < CH_NUM; m = m + 1) begin: cordic + + wire rotate_phase_valid; + wire [15:0] rotate_phase_data ; + wire rotate_cart_valid ; + wire [31:0] rotate_cart_data ; + wire rotate_dout_valid ; + wire [31:0] rotate_dout_data ; + + assign rotate_phase_valid = din_valid; + assign rotate_phase_data = phase_array[m]; + assign rotate_cart_valid = din_valid; + assign rotate_cart_data = {din_imag_array[m],din_real_array[m]}; + assign {rotate_imag_array[m],rotate_real_array[m]} = rotate_dout_data; + + if (DATA_WIDTH > AXIS_CORDIC_WIDTH) begin + // append zeros + assign dout_real_array[m] = {rotate_real_array[m],{(DATA_WIDTH-AXIS_CORDIC_WIDTH){1'b0}}}; + assign dout_imag_array[m] = {rotate_imag_array[m],{(DATA_WIDTH-AXIS_CORDIC_WIDTH){1'b0}}}; + end + else begin + // truncate msb + assign dout_real_array[m] = rotate_real_array[m][AXIS_CORDIC_WIDTH-1 -: DATA_WIDTH]; + assign dout_imag_array[m] = rotate_imag_array[m][AXIS_CORDIC_WIDTH-1 -: DATA_WIDTH]; + end + + assign dout_real[m*DATA_WIDTH +: DATA_WIDTH] = dout_real_array[m]; + assign dout_imag[m*DATA_WIDTH +: DATA_WIDTH] = dout_imag_array[m]; + + rotate_16b u_rotate_16b + ( + .aclk (clk ), // input wire aclk + .s_axis_phase_tvalid (rotate_phase_valid ), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata (rotate_phase_data ), // input wire [15 : 0] s_axis_phase_tdata + .s_axis_cartesian_tvalid(rotate_cart_valid ), // input wire s_axis_cartesian_tvalid + .s_axis_cartesian_tdata (rotate_cart_data ), // input wire [31 : 0] s_axis_cartesian_tdata + .m_axis_dout_tvalid (rotate_dout_valid ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (rotate_dout_data ) // output wire [31 : 0] m_axis_dout_tdata + ); + + end + +assign dout_valid = cordic[0].rotate_dout_valid; + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/phase_compensate.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/phase_compensate.v new file mode 100644 index 0000000..90c386d --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/phase_compensate.v @@ -0,0 +1,196 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/05/16 02:00:43 +// Design Name: +// Module Name: phase_compensate +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module phase_compensate( + input clk , + input rst , + input [11:0] vio_sin_0 , + input [11:0] vio_sin_1 , + input [11:0] vio_sin_2 , + input [11:0] vio_sin_3 , + input [11:0] vio_cos_0 , + input [11:0] vio_cos_1 , + input [11:0] vio_cos_2 , + input [11:0] vio_cos_3 , + input [11:0] din_i_0 , + input [11:0] din_i_1 , + input [11:0] din_i_2 , + input [11:0] din_i_3 , + input [11:0] din_q_0 , + input [11:0] din_q_1 , + input [11:0] din_q_2 , + input [11:0] din_q_3 , + input [4:0] vio_trunc , + + output [11:0] dout_0_i , + output [11:0] dout_1_i , + output [11:0] dout_2_i , + output [11:0] dout_3_i , + output [11:0] dout_0_q , + output [11:0] dout_1_q , + output [11:0] dout_2_q , + output [11:0] dout_3_q , + output trunc_overflow +); + + wire [63:0] dout_comp_0; + wire [63:0] dout_comp_1; + wire [63:0] dout_comp_2; + wire [63:0] dout_comp_3; + cmpy_12x12 cmpy_12x12_0 ( + .aclk(clk), // input wire aclk + .s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid + .s_axis_a_tdata({{4{vio_sin_0[11]}},vio_sin_0[11:0],{4{vio_cos_0[11]}},vio_cos_0[11:0]}), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid + .s_axis_b_tdata({{4{din_q_0[11]}},din_q_0[11:0],{4{din_i_0[11]}},din_i_0[11:0]}), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata(dout_comp_0) // output wire [63 : 0] m_axis_dout_tdata + ); + + cmpy_12x12 cmpy_12x12_1 ( + .aclk(clk), // input wire aclk + .s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid + .s_axis_a_tdata({{4{vio_sin_1[11]}},vio_sin_1[11:0],{4{vio_cos_1[11]}},vio_cos_1[11:0]}), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid + .s_axis_b_tdata({{4{din_q_1[11]}},din_q_1[11:0],{4{din_i_1[11]}},din_i_1[11:0]}), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata(dout_comp_1) // output wire [63 : 0] m_axis_dout_tdata + ); + + cmpy_12x12 cmpy_12x12_2 ( + .aclk(clk), // input wire aclk + .s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid + .s_axis_a_tdata({{4{vio_sin_2[11]}},vio_sin_2[11:0],{4{vio_cos_2[11]}},vio_cos_2[11:0]}), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid + .s_axis_b_tdata({{4{din_q_2[11]}},din_q_2[11:0],{4{din_i_2[11]}},din_i_2[11:0]}), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata(dout_comp_2) // output wire [63 : 0] m_axis_dout_tdata + ); + + cmpy_12x12 cmpy_12x12_3 ( + .aclk(clk), // input wire aclk + .s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid + .s_axis_a_tdata({{4{vio_sin_3[11]}},vio_sin_3[11:0],{4{vio_cos_3[11]}},vio_cos_3[11:0]}), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid + .s_axis_b_tdata({{4{din_q_3[11]}},din_q_3[11:0],{4{din_i_3[11]}},din_i_3[11:0]}), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata(dout_comp_3) // output wire [63 : 0] m_axis_dout_tdata + ); + wire [11:0] dout_trunc_0i, dout_trunc_0q; + wire [11:0] dout_trunc_1i, dout_trunc_1q; + wire [11:0] dout_trunc_2i, dout_trunc_2q; + wire [11:0] dout_trunc_3i, dout_trunc_3q; + wire [11:0] trunc_overflow_0i, trunc_overflow_0q; + wire [11:0] trunc_overflow_1i, trunc_overflow_1q; + wire [11:0] trunc_overflow_2i, trunc_overflow_2q; + wire [11:0] trunc_overflow_3i, trunc_overflow_3q; + trunc_32bit_to_12bit trunc_32bit_to_12bit_0i( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_0[24]}},dout_comp_0[24:0]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_0i), + .trunc_overflow(trunc_overflow_0i) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_0q( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_0[56]}},dout_comp_0[56:32]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_0q), + .trunc_overflow(trunc_overflow_0q) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_1i( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_1[24]}},dout_comp_1[24:0]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_1i), + .trunc_overflow(trunc_overflow_1i) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_1q( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_1[56]}},dout_comp_1[56:32]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_1q), + .trunc_overflow(trunc_overflow_1q) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_2i( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_2[24]}},dout_comp_2[24:0]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_2i), + .trunc_overflow(trunc_overflow_2i) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_2q( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_2[56]}},dout_comp_2[56:32]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_2q), + .trunc_overflow(trunc_overflow_2q) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_3i( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_3[24]}},dout_comp_3[24:0]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_3i), + .trunc_overflow(trunc_overflow_3i) + ); + + trunc_32bit_to_12bit trunc_32bit_to_12bit_3q( + .clk(clk), + .rst(rst), + .trunc_32bit_in({{7{dout_comp_3[56]}},dout_comp_3[56:32]}), + .vio_trunc(vio_trunc), + + .trunc_12bit_out(dout_trunc_3q), + .trunc_overflow(trunc_overflow_3q) + ); + + assign dout_0_i = dout_trunc_0i; + assign dout_1_i = dout_trunc_1i; + assign dout_2_i = dout_trunc_2i; + assign dout_3_i = dout_trunc_3i; + assign dout_0_q = dout_trunc_0q; + assign dout_1_q = dout_trunc_1q; + assign dout_2_q = dout_trunc_2q; + assign dout_3_q = dout_trunc_3q; + + assign trunc_overflow = trunc_overflow_3q || trunc_overflow_2q || trunc_overflow_1q || trunc_overflow_0q || trunc_overflow_3i || trunc_overflow_2i || trunc_overflow_1i || trunc_overflow_0i; +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/rx_pre_process.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/rx_pre_process.v new file mode 100644 index 0000000..2fa8c77 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/rx_pre_process.v @@ -0,0 +1,573 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/10/30 18:09:20 +// Design Name: +// Module Name: rx_pre_process +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Pre-process rx data, including ad9361 mcs & implementing nulling +// algorithm on rx data. The latency of autocorrelation is consisted of 2 +// parts: 1. [STABLE_CNT_MOD] + [SNAPSHOT_NUM] + several intermediate delay +// of [sys_clk] clock cycles; 2. ([CH_NUM]*[CH_NUM]*[CMPLX_DIM] + +// 1 frame head + 1 frame length)*[ACCUM_WIDTH] of [clk_96m] clock cycles. +// The simulation result shows delay of about 30us when [sys_clk] is 48m. +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +/******************************************************************************* + * Contents + * 01. AD9361 Rx Multi-Channel Calibration + * 02. Autocorrelation of Snapshot Vector + * 03. Accumulation of Snapshot Autocorrelation Matrices + * 04. 32-bit Matrix Element to 1-bit Stream Conversion + * 05. 1-bit Stream to 32-bit Vector Element Conversion + * 06. RF Synthesizer Control + * 07. Debug IO + * 08. DDR and Fixed-io (Do NOT Modify) +*******************************************************************************/ + +module rx_pre_process +#( + parameter CAL_CNT_MOD = 48 , + parameter CAL_PEAK_POS = 12 , + parameter STABLE_CNT_MOD = 96 , + parameter ADC_WIDTH = 12 , + parameter CH_NUM = 4 , + parameter PHASE_WIDTH = 16 , + parameter SYNC_HOP_INTVL = 48*1000, // 1 ms of 48M clock, must > 48*200 + parameter SNAPSHOT_NUM = 2048, + parameter PS_PL_WIDTH = 32 , + parameter WEIGHT_WIDTH = 16 , + parameter OUTPUT_WIDTH = ADC_WIDTH, + parameter ACCOR_FRAME_HEAD = 32'h7E7E7E7E, + parameter WEIGHT_FRAME_HEAD = ACCOR_FRAME_HEAD // Same head is required by [c2c_bridge] module +) +( + // clock & reset + input sys_clk , // sync to adc data + input sys_clk_phy , // sync to adc data + input sys_rst , // sync to [sys_clk] + input clk_96m , // sync to c2c data + input ant_rst , // sync to [clk_96m] + + // input un-calibrated data + input [ADC_WIDTH-1:0] rx_ch1_i , + input [ADC_WIDTH-1:0] rx_ch1_q , + input [ADC_WIDTH-1:0] rx_ch2_i , + input [ADC_WIDTH-1:0] rx_ch2_q , + input [ADC_WIDTH-1:0] rx_ch3_i , + input [ADC_WIDTH-1:0] rx_ch3_q , + input [ADC_WIDTH-1:0] rx_ch4_i , + input [ADC_WIDTH-1:0] rx_ch4_q , + + // input channel phase + input [PHASE_WIDTH-1:0] phase_ch1 , // sync to [sys_clk] + input [PHASE_WIDTH-1:0] phase_ch2 , // sync to [sys_clk] + input [PHASE_WIDTH-1:0] phase_ch3 , // sync to [sys_clk] + input [PHASE_WIDTH-1:0] phase_ch4 , // sync to [sys_clk] + + // ad9361 calibration interface + input ad9361_1_cal_start , + output ad9361_1_cal_done , + input ad9361_2_cal_start , + output ad9361_2_cal_done , + output ad9361_cal_result , + output ad9361_cal_valid , + input ad9361_recal , + + // nulling algorithm interface + input hop_flag_in_phy , // sync to [sys_clk_phy], hop flag that drives lcmv algorithm and hop data buffering + input sync_flag_phy , // sync to [sys_clk_phy], 1: sync segment; 0: guard/data segment + input lcmv_en_phy , // sync to [sys_clk_phy], 1: lcmv; 0: das (delay and sum) + output hop_flag_out , // sync to [sys_clk], hop flag that drives physical receiver + + output accor_stream_valid , // sync to [clk_96m] + output accor_stream_data , // sync to [clk_96m] + input weight_stream_data , // sync to [clk_96m] + output rx_data_valid , // sync to [sys_clk] + output [OUTPUT_WIDTH-1:0] rx_data_i , // sync to [sys_clk] + output [OUTPUT_WIDTH-1:0] rx_data_q // sync to [sys_clk] +); + +localparam CMPLX_DIM = 2; +localparam ACORR_WIDTH = 2*ADC_WIDTH; +localparam ACCUM_WIDTH = PS_PL_WIDTH; +localparam LCMV_WIDTH = ADC_WIDTH + WEIGHT_WIDTH + $clog2(CH_NUM); + +//////////////////////////////////////////////////////////////////////////////// +///////////////////// AD9361 Rx Multi-Channel Calibration ////////////////////// +//////////////////////////////////////////////////////////////////////////////// +wire [11:0] rx_cal_ch1_i, rx_cal_ch1_q; +wire [11:0] rx_cal_ch2_i, rx_cal_ch2_q; +wire [11:0] rx_cal_ch3_i, rx_cal_ch3_q; +wire [11:0] rx_cal_ch4_i, rx_cal_ch4_q; + +ad9361_phase_cal_coarse u_ad9361_phase_cal +( + // clock & reset + .clk (sys_clk ), // input clk + .rst (sys_rst ), // input rst + // control interface + .ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start + .ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done + .ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start + .ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done + .ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result + .ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid + .ad9361_recal (ad9361_recal ), // input ad9361_recal + // input data interface + .rx_ch1_i (rx_ch1_i ), // input [ADC_WIDTH-1:0] rx_ch1_i + .rx_ch1_q (rx_ch1_q ), // input [ADC_WIDTH-1:0] rx_ch1_q + .rx_ch2_i (rx_ch2_i ), // input [ADC_WIDTH-1:0] rx_ch2_i + .rx_ch2_q (rx_ch2_q ), // input [ADC_WIDTH-1:0] rx_ch2_q + .rx_ch3_i (rx_ch3_i ), // input [ADC_WIDTH-1:0] rx_ch3_i + .rx_ch3_q (rx_ch3_q ), // input [ADC_WIDTH-1:0] rx_ch3_q + .rx_ch4_i (rx_ch4_i ), // input [ADC_WIDTH-1:0] rx_ch4_i + .rx_ch4_q (rx_ch4_q ), // input [ADC_WIDTH-1:0] rx_ch4_q + // output data interface + .rx_cal_ch1_i (rx_cal_ch1_i ), // output [ADC_WIDTH-1:0] rx_cal_ch1_i + .rx_cal_ch1_q (rx_cal_ch1_q ), // output [ADC_WIDTH-1:0] rx_cal_ch1_q + .rx_cal_ch2_i (rx_cal_ch2_i ), // output [ADC_WIDTH-1:0] rx_cal_ch2_i + .rx_cal_ch2_q (rx_cal_ch2_q ), // output [ADC_WIDTH-1:0] rx_cal_ch2_q + .rx_cal_ch3_i (rx_cal_ch3_i ), // output [ADC_WIDTH-1:0] rx_cal_ch3_i + .rx_cal_ch3_q (rx_cal_ch3_q ), // output [ADC_WIDTH-1:0] rx_cal_ch3_q + .rx_cal_ch4_i (rx_cal_ch4_i ), // output [ADC_WIDTH-1:0] rx_cal_ch4_i + .rx_cal_ch4_q (rx_cal_ch4_q ) // output [ADC_WIDTH-1:0] rx_cal_ch4_q +); + + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////// Phase Compensation ////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// input data +wire phase_comp_din_valid; +wire [CH_NUM*PHASE_WIDTH-1 : 0] phase_comp_phase; +wire [CH_NUM*ADC_WIDTH-1 : 0] phase_comp_din_real; +wire [CH_NUM*ADC_WIDTH-1 : 0] phase_comp_din_imag; + +assign phase_comp_din_valid = ad9361_cal_valid; +assign phase_comp_phase = {phase_ch4, phase_ch3, phase_ch2, phase_ch1}; +assign phase_comp_din_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i}; +assign phase_comp_din_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q}; + +// output data +(*dont_touch = "true"*) wire [11:0] rx_comp_ch1_i; +(*dont_touch = "true"*) wire [11:0] rx_comp_ch1_q; +(*dont_touch = "true"*) wire [11:0] rx_comp_ch2_i; +(*dont_touch = "true"*) wire [11:0] rx_comp_ch2_q; +(*dont_touch = "true"*) wire [11:0] rx_comp_ch3_i; +(*dont_touch = "true"*) wire [11:0] rx_comp_ch3_q; +(*dont_touch = "true"*) wire [11:0] rx_comp_ch4_i; +(*dont_touch = "true"*) wire [11:0] rx_comp_ch4_q; + +wire phase_comp_dout_valid; +wire [CH_NUM*ADC_WIDTH-1:0] phase_comp_dout_real; +wire [CH_NUM*ADC_WIDTH-1:0] phase_comp_dout_imag; + +// assign phase_comp_dout_valid = ad9361_cal_valid; +assign {rx_comp_ch4_i, rx_comp_ch3_i, rx_comp_ch2_i, rx_comp_ch1_i} = phase_comp_dout_real; +assign {rx_comp_ch4_q, rx_comp_ch3_q, rx_comp_ch2_q, rx_comp_ch1_q} = phase_comp_dout_imag; + +phase_comp #( + .DATA_WIDTH (ADC_WIDTH ), + .CORDIC_WIDTH (PHASE_WIDTH ), + .CH_NUM (CH_NUM ) +) u_phase_comp +( + // clock & reset + .clk (sys_clk ), + .rst (sys_rst ), + + // input data + .din_valid (phase_comp_din_valid ), + .phase (phase_comp_phase ), + .din_real (phase_comp_din_real ), + .din_imag (phase_comp_din_imag ), + + // output data + .dout_valid (phase_comp_dout_valid ), + .dout_real (phase_comp_dout_real ), + .dout_imag (phase_comp_dout_imag ) +); + + +// (*dont_touch = "true"*) wire [11:0] vio_sin_0; +// (*dont_touch = "true"*) wire [11:0] vio_sin_1; +// (*dont_touch = "true"*) wire [11:0] vio_sin_2; +// (*dont_touch = "true"*) wire [11:0] vio_sin_3; +// (*dont_touch = "true"*) wire [11:0] vio_cos_0; +// (*dont_touch = "true"*) wire [11:0] vio_cos_1; +// (*dont_touch = "true"*) wire [11:0] vio_cos_2; +// (*dont_touch = "true"*) wire [11:0] vio_cos_3; +// (*dont_touch = "true"*) wire [ 4:0] vio_trunc; +// (*dont_touch = "true"*) wire trunc_overflow; + +// phase_compensate u_phase_compensate +// ( +// .clk (sys_clk ), +// .rst (sys_rst ), + +// .vio_sin_0 (vio_sin_0 ), +// .vio_sin_1 (vio_sin_1 ), +// .vio_sin_2 (vio_sin_2 ), +// .vio_sin_3 (vio_sin_3 ), +// .vio_cos_0 (vio_cos_0 ), +// .vio_cos_1 (vio_cos_1 ), +// .vio_cos_2 (vio_cos_2 ), +// .vio_cos_3 (vio_cos_3 ), + +// .din_i_0 (rx_cal_ch1_i ), +// .din_i_1 (rx_cal_ch2_i ), +// .din_i_2 (rx_cal_ch3_i ), +// .din_i_3 (rx_cal_ch4_i ), +// .din_q_0 (rx_cal_ch1_q ), +// .din_q_1 (rx_cal_ch2_q ), +// .din_q_2 (rx_cal_ch3_q ), +// .din_q_3 (rx_cal_ch4_q ), +// .vio_trunc (vio_trunc ), + +// .dout_0_i (rx_comp_ch1_i ), +// .dout_1_i (rx_comp_ch2_i ), +// .dout_2_i (rx_comp_ch3_i ), +// .dout_3_i (rx_comp_ch4_i ), +// .dout_0_q (rx_comp_ch1_q ), +// .dout_1_q (rx_comp_ch2_q ), +// .dout_2_q (rx_comp_ch3_q ), +// .dout_3_q (rx_comp_ch4_q ), +// .trunc_overflow (trunc_overflow ) +// ); + +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// Nulling Control //////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// adc input +wire adc_din_valid ; +wire [CH_NUM*ADC_WIDTH-1 : 0] adc_din_real; +wire [CH_NUM*ADC_WIDTH-1 : 0] adc_din_imag; + +assign adc_din_valid = phase_comp_dout_valid; +assign adc_din_real = phase_comp_dout_real ; +assign adc_din_imag = phase_comp_dout_imag ; + +// autocorrelation +wire acorr_din_valid ; +wire [CH_NUM*ADC_WIDTH-1 : 0] acorr_din_real; +wire [CH_NUM*ADC_WIDTH-1 : 0] acorr_din_imag; + +wire acorr_dout_valid ; +wire [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] acorr_dout_real; +wire [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] acorr_dout_imag; + +// accumulation +wire accum_rst ; + +wire accum_din_valid ; +wire [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] accum_din_real; +wire [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] accum_din_imag; + +wire accum_dout_valid ; +wire [CH_NUM*CH_NUM*ACCUM_WIDTH-1:0] accum_dout_real; +wire [CH_NUM*CH_NUM*ACCUM_WIDTH-1:0] accum_dout_imag; + +// Parallel to Serial +wire stream_fifo_rst ; + +wire stream_din_valid ; +wire [CH_NUM*CH_NUM*ACCUM_WIDTH-1 : 0] stream_din_real; +wire [CH_NUM*CH_NUM*ACCUM_WIDTH-1 : 0] stream_din_imag; + +// Serial to Parallel +wire weight_fifo_rst ; + +wire weight_dout_valid ; +wire [CH_NUM*WEIGHT_WIDTH-1 : 0] weight_dout_real; +wire [CH_NUM*WEIGHT_WIDTH-1 : 0] weight_dout_imag; + +// spatial filter +wire filter_weight_valid ; +wire [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_real; +wire [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_imag; + +wire filter_din_valid ; +wire [CH_NUM*ADC_WIDTH-1 : 0] filter_din_real; +wire [CH_NUM*ADC_WIDTH-1 : 0] filter_din_imag; + +wire filter_dout_valid ; +wire [LCMV_WIDTH-1 : 0] filter_dout_real; +wire [LCMV_WIDTH-1 : 0] filter_dout_imag; + +// output data port +wire null_dout_valid ; +wire [OUTPUT_WIDTH-1 : 0] null_dout_real; +wire [OUTPUT_WIDTH-1 : 0] null_dout_imag; + +assign rx_data_valid = null_dout_valid; +assign rx_data_i = null_dout_real; +assign rx_data_q = null_dout_imag; + +null_ctrl #( + .ADC_WIDTH (ADC_WIDTH ), + .CH_NUM (CH_NUM ), + .STABLE_CNT_MOD (STABLE_CNT_MOD ), + .SYNC_HOP_INTVL (SYNC_HOP_INTVL ), + .SNAPSHOT_NUM (SNAPSHOT_NUM ), + .ACCUM_WIDTH (ACCUM_WIDTH ), + .ACORR_WIDTH (ACORR_WIDTH ), + .WEIGHT_WIDTH (WEIGHT_WIDTH ), + .OUTPUT_WIDTH (OUTPUT_WIDTH ) +) u_null_ctrl ( + // ************************************************************************* + // ***************************** clock & reset ***************************** + // ************************************************************************* + .clk (sys_clk ), // input clk + .clk_phy (sys_clk_phy ), // input clk_phy + .rst (sys_rst ), // input rst + + // + .hop_flag_in_phy (hop_flag_in_phy ), // input hop_flag_in_phy + .sync_flag_phy (sync_flag_phy ), // input sync_flag_phy + .lcmv_en_phy (lcmv_en_phy ), // input lcmv_en_phy + .hop_flag_out (hop_flag_out ), // output hop_flag_out + // ************************************************************************* + // **************************** ADC Input Data ***************************** + // ************************************************************************* + .adc_din_valid (adc_din_valid ), // input adc_din_valid + .adc_din_real (adc_din_real ), // input [CH_NUM*ADC_WIDTH-1 : 0] adc_din_real + .adc_din_imag (adc_din_imag ), // input [CH_NUM*ADC_WIDTH-1 : 0] adc_din_imag + + // ************************************************************************* + // **************************** Autocorrelation **************************** + // ************************************************************************* + .acorr_din_valid (acorr_din_valid ), // output acorr_din_valid + .acorr_din_real (acorr_din_real ), // output [CH_NUM*ADC_WIDTH-1 : 0] acorr_din_real + .acorr_din_imag (acorr_din_imag ), // output [CH_NUM*ADC_WIDTH-1 : 0] acorr_din_imag + + .acorr_dout_valid (acorr_dout_valid ), // input acorr_dout_valid + .acorr_dout_real (acorr_dout_real ), // input [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] acorr_dout_real + .acorr_dout_imag (acorr_dout_imag ), // input [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] acorr_dout_imag + + // ************************************************************************* + // **************************** Accumulation ******************************* + // ************************************************************************* + .accum_rst (accum_rst ), // output accum_rst + + .accum_din_valid (accum_din_valid ), // output accum_din_valid + .accum_din_real (accum_din_real ), // output [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] accum_din_real + .accum_din_imag (accum_din_imag ), // output [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] accum_din_imag + + .accum_dout_valid (accum_dout_valid ), // input accum_dout_valid + .accum_dout_real (accum_dout_real ), // input [CH_NUM*CH_NUM*ACCUM_WIDTH-1:0] accum_dout_real + .accum_dout_imag (accum_dout_imag ), // input [CH_NUM*CH_NUM*ACCUM_WIDTH-1:0] accum_dout_imag + + // ************************************************************************* + // ************************* Parallel to Serial **************************** + // ************************************************************************* + .stream_fifo_rst (stream_fifo_rst ), // output stream_fifo_rst + + .stream_din_valid (stream_din_valid ), // output stream_din_valid + .stream_din_real (stream_din_real ), // output [CH_NUM*CH_NUM*ACCUM_WIDTH-1 : 0] stream_din_real + .stream_din_imag (stream_din_imag ), // output [CH_NUM*CH_NUM*ACCUM_WIDTH-1 : 0] stream_din_imag + + // ************************************************************************* + // ************************* Serial to Parallel **************************** + // ************************************************************************* + .weight_fifo_rst (weight_fifo_rst ), // output weight_fifo_rst + + .weight_dout_valid (weight_dout_valid ), // input weight_dout_valid + .weight_dout_real (weight_dout_real ), // input [CH_NUM*WEIGHT_WIDTH-1 : 0] weight_dout_real + .weight_dout_imag (weight_dout_imag ), // input [CH_NUM*WEIGHT_WIDTH-1 : 0] weight_dout_imag + + // ************************************************************************* + // **************************** Spatial Filter ***************************** + // ************************************************************************* + // input weight vector + .filter_weight_valid (filter_weight_valid ), // output filter_weight_valid + .filter_weight_real (filter_weight_real ), // output [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_real + .filter_weight_imag (filter_weight_imag ), // output [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_imag + + // input adc data + .filter_din_valid (filter_din_valid ), // output filter_din_valid + .filter_din_real (filter_din_real ), // output [CH_NUM*ADC_WIDTH-1 : 0] filter_din_real + .filter_din_imag (filter_din_imag ), // output [CH_NUM*ADC_WIDTH-1 : 0] filter_din_imag + + // output data + .filter_dout_valid (filter_dout_valid ), // input filter_dout_valid + .filter_dout_real (filter_dout_real ), // input [LCMV_WIDTH-1 : 0] filter_dout_real + .filter_dout_imag (filter_dout_imag ), // input [LCMV_WIDTH-1 : 0] filter_dout_imag + + // ************************************************************************* + // *************************** Output Data Port **************************** + // ************************************************************************* + .null_dout_valid (null_dout_valid ), // output null_dout_valid + .null_dout_real (null_dout_real ), // output [OUTPUT_WIDTH-1 : 0] null_dout_real + .null_dout_imag (null_dout_imag ) // output [OUTPUT_WIDTH-1 : 0] null_dout_imag +); + + +//////////////////////////////////////////////////////////////////////////////// +////////////////////// Autocorrelation of Snapshot Vector ////////////////////// +//////////////////////////////////////////////////////////////////////////////// +acorr_cmplx_col_vec #( + .DATA_I_WIDTH (ADC_WIDTH ), + .DATA_O_WIDTH (ACORR_WIDTH ), + .COL_NUM (CH_NUM ) +) u_acorr ( + // clock & reset + .clk (sys_clk ), + .rst (sys_rst ), + + // input data + .din_valid (acorr_din_valid ), + .din_real (acorr_din_real ), + .din_imag (acorr_din_imag ), + + // output data + .dout_valid (acorr_dout_valid ), + .dout_real (acorr_dout_real ), + .dout_imag (acorr_dout_imag ) +); + + +//////////////////////////////////////////////////////////////////////////////// +////////////// Accumulation of Snapshot Autocorrelation Matrices /////////////// +//////////////////////////////////////////////////////////////////////////////// +accum_cmplx_mat #( + .ROW_NUM (CH_NUM ), + .COL_NUM (CH_NUM ), + .ACC_NUM (SNAPSHOT_NUM ), + .DATA_I_WIDTH (ACORR_WIDTH ), + .DATA_O_WIDTH (PS_PL_WIDTH ) +) u_accum_cmplx_mat +( + // clock & reset + .clk (sys_clk ), + .rst (sys_rst ), + .acc_rst (accum_rst ), // [accum_rst] should assert before accumulation starts + + // input data + .din_valid (accum_din_valid ), + .din_real (accum_din_real ), + .din_imag (accum_din_imag ), + + // output data + .dout_valid (accum_dout_valid ), + .dout_real (accum_dout_real ), + .dout_imag (accum_dout_imag ) +); + + +//////////////////////////////////////////////////////////////////////////////// +/////////////// 32-bit Matrix Element to 1-bit Stream Conversion /////////////// +//////////////////////////////////////////////////////////////////////////////// +// output data +wire stream_dout_valid; +wire stream_dout_data; + +assign accor_stream_valid = stream_dout_valid; // to module port +assign accor_stream_data = stream_dout_data; // to module port + +accor_mat_formatting #( + .ROW_NUM (CH_NUM ), + .COL_NUM (CH_NUM ), + .DATA_I_WIDTH (PS_PL_WIDTH ), + .FRAME_HEAD (ACCOR_FRAME_HEAD ) +) u_accor_mat_stream +( + // clock & reset + .sys_clk (sys_clk ), + .sys_rst (sys_rst ), + .clk_96m (clk_96m ), + .ant_rst (ant_rst ), + + // input data, sync to [sys_clk] + .din_valid (stream_din_valid ), + .din_real (stream_din_real ), + .din_imag (stream_din_imag ), + .fifo_cdc_rst (stream_fifo_rst ), + + // output data, sync to [clk_96m] + .dout_valid (stream_dout_valid ), + .dout_data (stream_dout_data ) +); + + +//////////////////////////////////////////////////////////////////////////////// +/////////////// 1-bit Stream to 32-bit Vector Element Conversion /////////////// +//////////////////////////////////////////////////////////////////////////////// +// input data +wire weight_din_data; + +assign weight_din_data = weight_stream_data; + +weight_vec_formatting #( + .COL_NUM (CH_NUM ), + .WEIGHT_WIDTH (PS_PL_WIDTH ), + .DATA_O_WIDTH (WEIGHT_WIDTH ), + .FRAME_HEAD (WEIGHT_FRAME_HEAD ) +) u_weight_vec_formatting +( + // clock & reset + .sys_clk (sys_clk ), + .sys_rst (sys_rst ), + .clk_96m (clk_96m ), + .ant_rst (ant_rst ), + + // input data, sync to [clk_96m] + .din_data (weight_din_data ), + + // sync to [sys_clk] + .fifo_cdc_rst (weight_fifo_rst ), + + // output data, sync to [sys_clk] + .dout_valid (weight_dout_valid ), + .dout_real (weight_dout_real ), + .dout_imag (weight_dout_imag ) +); + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////// Spatial Filter //////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +spatial_filter #( + .CH_NUM (CH_NUM ), + .WEIGHT_WIDTH (WEIGHT_WIDTH ), + .ADC_WIDTH (ADC_WIDTH ), + .FILTER_O_WIDTH (OUTPUT_WIDTH ) +) u_spatial_filter +( + // clock & reset + .clk (sys_clk ), + .rst (sys_rst ), + + // input weight vector + .din_weight_valid (filter_weight_valid), + .din_weight_real (filter_weight_real ), + .din_weight_imag (filter_weight_imag ), + + // input adc data + .din_adc_valid (filter_din_valid ), + .din_adc_real (filter_din_real ), + .din_adc_imag (filter_din_imag ), + + // output data + .dout_valid (filter_dout_valid ), + .dout_real (filter_dout_real ), + .dout_imag (filter_dout_imag ) +); + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/rx_pre_test.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/rx_pre_test.v new file mode 100644 index 0000000..07a54aa --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/rx_pre_test.v @@ -0,0 +1,251 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/16 11:18:28 +// Design Name: +// Module Name: rx_pre_test +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module rx_pre_test +#( + parameter ADC_DATA_WIDTH = 12, + parameter BYPASS_CAL = 0 , + parameter PHY_CLK_MULT = 3 +) +( + // clock & reset + input clk , + input clk_phy , + input rst , + // calc result + input ad9361_cal_result , + input ad9361_cal_valid , + // + input hop_trigger , + input hop_trigger_en , + // output test data + output [ADC_DATA_WIDTH-1:0] rx_ch1_i , + output [ADC_DATA_WIDTH-1:0] rx_ch1_q , + output [ADC_DATA_WIDTH-1:0] rx_ch2_i , + output [ADC_DATA_WIDTH-1:0] rx_ch2_q , + output [ADC_DATA_WIDTH-1:0] rx_ch3_i , + output [ADC_DATA_WIDTH-1:0] rx_ch3_q , + output [ADC_DATA_WIDTH-1:0] rx_ch4_i , + output [ADC_DATA_WIDTH-1:0] rx_ch4_q , + output hop_start_flag +); + +localparam HOP_CNT_MOD_PHY = 48*200*PHY_CLK_MULT; +localparam HOP_CNT_MOD_48M = 48*200; + +// data valid cdc +wire ad9361_cal_valid_cdc; + +xpm_cdc_single #( + .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 + .INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages + .SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input +) u_ad9361_cal_valid_cdc +( + .dest_out (ad9361_cal_valid_cdc ), // 1-bit output: src_in synchronized to the destination clock domain. This output is + // registered. + .dest_clk (clk_phy ), // 1-bit input: Clock signal for the destination clock domain. + .src_clk (clk ), // 1-bit input: optional; required when SRC_INPUT_REG = 1 + .src_in (ad9361_cal_valid ) // 1-bit input: Input signal to be synchronized to dest_clk domain. +); + +// auto hop flag generation +reg [$clog2(HOP_CNT_MOD_PHY)-1 : 0] hop_cnt_phy = 'b0; +reg hop_flag_auto = 'b0; + +always @(posedge clk_phy) begin + if (rst) begin + hop_cnt_phy = 'b0; + hop_flag_auto = 'b0; + end + else if (ad9361_cal_valid_cdc) begin + hop_cnt_phy <= (hop_cnt_phy == HOP_CNT_MOD_PHY-1) ? 'b0 : hop_cnt_phy + 1'b1; + hop_flag_auto <= (hop_cnt_phy == 20) ? 1'b1 : 1'b0; + end + else begin + hop_cnt_phy <= 'b0; + hop_flag_auto = 'b0; + end +end + +// manual hop flag generation +reg hop_flag_manual = 'b0; +reg hop_trigger_d1 = 'b0; + +always @(posedge clk_phy) begin + hop_trigger_d1 <= hop_trigger; +end + +always @(posedge clk_phy) begin + if (rst) begin + hop_flag_manual <= 'b0; + end + else if (ad9361_cal_valid_cdc) begin + if (hop_trigger_d1 ^ hop_trigger) begin + hop_flag_manual <= 1'b1; + end + else begin + hop_flag_manual <= 1'b0; + end + end + else begin + hop_flag_manual <= 'b0; + end +end + +// output hop flag +reg hop_start_flag_buf = 'b0; + +assign hop_start_flag = hop_start_flag_buf; + +always @(posedge clk_phy) begin + if (rst) begin + hop_start_flag_buf <= 'b0; + end + else begin + if (hop_trigger_en) begin + hop_start_flag_buf <= hop_flag_manual; + end + else begin + hop_start_flag_buf <= hop_flag_auto; + end + end +end + +// hop flag cdc +wire hop_flag_cdc; + +xpm_cdc_pulse #( + .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 + .INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .REG_OUTPUT (0), // DECIMAL; 0=disable registered output, 1=enable registered output + .RST_USED (1), // DECIMAL; 0=no reset, 1=implement reset + .SIM_ASSERT_CHK (0) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages +) u_hop_flag_cdc +( + .dest_pulse (hop_flag_cdc ), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse + // transfer is correctly initiated on src_pulse input. This output is + // combinatorial unless REG_OUTPUT is set to 1. + .dest_clk (clk ), // 1-bit input: Destination clock. + .dest_rst (rst ), // 1-bit input: optional; required when RST_USED = 1 + .src_clk (clk_phy ), // 1-bit input: Source clock. + .src_pulse (hop_start_flag_buf ), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the + // destination clock domain. The minimum gap between each pulse transfer must be + // at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured + // between the falling edge of a src_pulse to the rising edge of the next + // src_pulse. This minimum gap will guarantee that each rising edge of src_pulse + // will generate a pulse the size of one dest_clk period in the destination + // clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while + // src_rst and/or dest_rst are asserted. + .src_rst (rst ) // 1-bit input: optional; required when RST_USED = 1 +); + +// data rom address counter +reg [$clog2(HOP_CNT_MOD_48M)-1 : 0] hop_cnt_48m = 'b0; + +always @(posedge clk) begin + if (rst) begin + hop_cnt_48m <= 2'd2; + end + else if (ad9361_cal_valid) begin + if (hop_flag_cdc) begin + hop_cnt_48m = 2'd2; + end + else begin + hop_cnt_48m <= (hop_cnt_48m == HOP_CNT_MOD_48M-1 || hop_flag_cdc) ? 'b0 : hop_cnt_48m + 1'b1; + end + end + else begin + hop_cnt_48m <= 2'd2; + end +end + +// rom interface +wire [95:0] hop_data; + +wire [11:0] rom_ch1_i,rom_ch2_i,rom_ch3_i,rom_ch4_i; +wire [11:0] rom_ch1_q,rom_ch2_q,rom_ch3_q,rom_ch4_q; + +assign {rom_ch1_i,rom_ch2_i,rom_ch3_i,rom_ch4_i, + rom_ch1_q,rom_ch2_q,rom_ch3_q,rom_ch4_q} = hop_data; + +rom_hop_data u_rom_hop_data +( + .clka (clk ), // input wire clka + .addra (hop_cnt_48m), // input wire [13 : 0] addra + .douta (hop_data ) // output wire [95 : 0] douta +); + +reg [11:0] rom_ch1_i_buf,rom_ch2_i_buf,rom_ch3_i_buf,rom_ch4_i_buf; +reg [11:0] rom_ch1_q_buf,rom_ch2_q_buf,rom_ch3_q_buf,rom_ch4_q_buf; + +assign rx_ch1_i = rom_ch1_i_buf; +assign rx_ch1_q = rom_ch1_q_buf; +assign rx_ch2_i = rom_ch2_i_buf; +assign rx_ch2_q = rom_ch2_q_buf; +assign rx_ch3_i = rom_ch3_i_buf; +assign rx_ch3_q = rom_ch3_q_buf; +assign rx_ch4_i = rom_ch4_i_buf; +assign rx_ch4_q = rom_ch4_q_buf; + +always @(posedge clk) begin +if (BYPASS_CAL) begin + rom_ch1_i_buf <= rom_ch1_i; + rom_ch1_q_buf <= rom_ch1_q; + rom_ch2_i_buf <= rom_ch2_i; + rom_ch2_q_buf <= rom_ch2_q; + rom_ch3_i_buf <= rom_ch3_i; + rom_ch3_q_buf <= rom_ch3_q; + rom_ch4_i_buf <= rom_ch4_i; + rom_ch4_q_buf <= rom_ch4_q; +end +else begin + if (ad9361_cal_result) begin + rom_ch1_i_buf <= rom_ch1_i; + rom_ch1_q_buf <= rom_ch1_q; + rom_ch2_i_buf <= -rom_ch2_i; + rom_ch2_q_buf <= -rom_ch2_q; + rom_ch3_i_buf <= -rom_ch3_i; + rom_ch3_q_buf <= -rom_ch3_q; + rom_ch4_i_buf <= rom_ch4_i; + rom_ch4_q_buf <= rom_ch4_q; + end + else begin + rom_ch1_i_buf <= rom_ch1_i; + rom_ch1_q_buf <= rom_ch1_q; + rom_ch2_i_buf <= -rom_ch2_i; + rom_ch2_q_buf <= -rom_ch2_q; + rom_ch3_i_buf <= rom_ch3_i; + rom_ch3_q_buf <= rom_ch3_q; + rom_ch4_i_buf <= -rom_ch4_i; + rom_ch4_q_buf <= -rom_ch4_q; + end +end +end + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/spatial_filter.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/spatial_filter.v new file mode 100644 index 0000000..d3a0110 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/spatial_filter.v @@ -0,0 +1,222 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/11 17:05:31 +// Design Name: +// Module Name: spatial_filter +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Perform vector multiplication of data vector and weight vector, +// to get spatial filtered output. +// Parameters: +// CH_NUM: Number of signal channels, i.e. the row number of signal vector and +// the column number of weight vector. +// WEIGHT_WIDTH: Bit width of input weight vector element. +// ADC_WIDTH: Bit width of input signal vector element. +// FILTER_O_WIDTH: Bit width of spatial filter output signal. +// Data format: +// din_weight_valid: Indicate [din_weight_real/imag] data are valid. +// din_weight_real/imag: Suppose the input weight vector is w = [w1, w2, w3, +// w4]^T, then +// din_weight_real = {Re{w4}, Re{w3}, Re{w2}, Re{w1}} +// din_weight_imag = {Im{w4}, Im{w3}, Im{w2}, Im{w1}} +// din_adc_valid: Indicate [din_adc_real/imag] data are valid. +// din_adc_real/imag: Suppose the input signal vector is x = [x1, x2, x3, x4], +// then +// din_adc_real = {Re{x4}, Re{x3}, Re{x2}, Re{x1}} +// din_adc_imag = {Im{x4}, Im{x3}, Im{x2}, Im{x1}} +// dout_valid: Indicate [dout_real/imag] data are valid. +// dout_real/imag: Output spatial filtered signal. +// +// Latency: 7 clock cycles for CMPY using LUTs, 8 for DSPs, including 5/6 clock +// cycles for complex multiplication and floor(log2(CH_NUM))=2 clock cycles +// for addition. +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// 20230404-1037 - å°†æƒçŸ¢é‡å’Œæ•°æ®å¯¹é½ï¼Œå¢žåŠ  [last_hop_weight_d1] è¡¥å¿ RAM 读数 +// 的延迟。 +// 20230723-0947 - 大修模å—，将缓存数æ®ç¼“存移至 [null_ctrl] 模å—，本模å—åªè´Ÿè´£ +// ä¿¡å·åŠ æƒå’Œæ±‚和。 +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module spatial_filter +#( + parameter CH_NUM = 4, + parameter WEIGHT_WIDTH = 16, + parameter ADC_WIDTH = 12, + parameter FILTER_O_WIDTH = ADC_WIDTH +) +( + // clock & reset + input clk, + input rst, + + // input weight vector + input din_weight_valid, + input [CH_NUM*WEIGHT_WIDTH-1 : 0] din_weight_real, + input [CH_NUM*WEIGHT_WIDTH-1 : 0] din_weight_imag, + + // input adc data + input din_adc_valid, + input [CH_NUM*ADC_WIDTH-1 : 0] din_adc_real, + input [CH_NUM*ADC_WIDTH-1 : 0] din_adc_imag, + + // output data + output dout_valid, + output [FILTER_O_WIDTH-1 : 0] dout_real, + output [FILTER_O_WIDTH-1 : 0] dout_imag +); + +localparam RAM_HOP_DEPTH = 9728; +localparam CMPLX_DIM = 2; + +localparam CMPY_P_FULL_WIDTH = WEIGHT_WIDTH+ADC_WIDTH+1; +localparam CMPY_P_VALID_WIDTH = WEIGHT_WIDTH+ADC_WIDTH; +localparam FILTER_SUM_WIDTH = CMPY_P_VALID_WIDTH+$clog2(CH_NUM); +localparam AXIS_WEIGHT_WIDTH = 8*((WEIGHT_WIDTH-1)/8+1); // axis data width of input weight vector real/image data +localparam AXIS_ADC_WIDTH = 8*((ADC_WIDTH-1)/8+1); // axis data width of input adc real/image data +localparam AXIS_FILTER_WIDTH = 8*((CMPY_P_FULL_WIDTH-1)/8+1) ; // axis data width of cmpy output real/image data + +genvar m; + +// prepare cmpy input data +wire [WEIGHT_WIDTH-1:0] din_weight_real_array [0:CH_NUM-1]; +wire [WEIGHT_WIDTH-1:0] din_weight_imag_array [0:CH_NUM-1]; + +wire [ADC_WIDTH-1:0] din_adc_real_array [0:CH_NUM-1]; +wire [ADC_WIDTH-1:0] din_adc_imag_array [0:CH_NUM-1]; + +wire [AXIS_WEIGHT_WIDTH-1:0] din_weight_real_array_axis [0:CH_NUM-1]; +wire [AXIS_WEIGHT_WIDTH-1:0] din_weight_imag_array_axis [0:CH_NUM-1]; + +wire [AXIS_ADC_WIDTH-1:0] din_adc_real_array_axis [0:CH_NUM-1]; +wire [AXIS_ADC_WIDTH-1:0] din_adc_imag_array_axis [0:CH_NUM-1]; + +for(m = 0; m < CH_NUM; m = m + 1) begin: array_conversion + // Array split + assign din_weight_real_array[m] = din_weight_real[m*WEIGHT_WIDTH +: WEIGHT_WIDTH]; + assign din_weight_imag_array[m] = din_weight_imag[m*WEIGHT_WIDTH +: WEIGHT_WIDTH]; + + assign din_adc_real_array[m] = din_adc_real[m*ADC_WIDTH +: ADC_WIDTH]; + assign din_adc_imag_array[m] = din_adc_imag[m*ADC_WIDTH +: ADC_WIDTH]; + + // Sign extension to fit 8-bit axis data format + assign din_weight_real_array_axis[m] = {{(AXIS_WEIGHT_WIDTH-WEIGHT_WIDTH){din_weight_real_array[m][WEIGHT_WIDTH-1]}},din_weight_real_array[m]}; + assign din_weight_imag_array_axis[m] = {{(AXIS_WEIGHT_WIDTH-WEIGHT_WIDTH){din_weight_imag_array[m][WEIGHT_WIDTH-1]}},din_weight_imag_array[m]}; + + assign din_adc_real_array_axis[m] = {{(AXIS_ADC_WIDTH-ADC_WIDTH){din_adc_real_array[m][ADC_WIDTH-1]}},din_adc_real_array[m]}; + assign din_adc_imag_array_axis[m] = {{(AXIS_ADC_WIDTH-ADC_WIDTH){din_adc_imag_array[m][ADC_WIDTH-1]}},din_adc_imag_array[m]}; +end + +// complex multiplication, spatial filtering +wire [AXIS_FILTER_WIDTH-1:0] cmpy_real_array [0:CH_NUM-1]; +wire [AXIS_FILTER_WIDTH-1:0] cmpy_imag_array [0:CH_NUM-1]; + +wire [CMPY_P_VALID_WIDTH-1:0] weight_adc_real_array [0:CH_NUM-1]; +wire [CMPY_P_VALID_WIDTH-1:0] weight_adc_imag_array [0:CH_NUM-1]; + +wire weight_adc_valid; +wire [CH_NUM*CMPY_P_VALID_WIDTH-1:0] weight_adc_real; +wire [CH_NUM*CMPY_P_VALID_WIDTH-1:0] weight_adc_imag; + +for(m = 0; m < CH_NUM; m = m + 1) begin: spatial_filter_cmpy + wire [2*AXIS_WEIGHT_WIDTH-1:0] cmpy_a; + wire [2*AXIS_ADC_WIDTH-1:0] cmpy_b; + wire [2*AXIS_FILTER_WIDTH-1:0] cmpy_p; + wire cmpy_p_vld; + + assign cmpy_a = {-din_weight_imag_array_axis[m],din_weight_real_array_axis[m]}; + assign cmpy_b = {din_adc_imag_array_axis[m],din_adc_real_array_axis[m]}; + assign {cmpy_imag_array[m],cmpy_real_array[m]} = cmpy_p; + + assign weight_adc_real_array[m] = cmpy_real_array[m][0 +: CMPY_P_VALID_WIDTH]; + assign weight_adc_imag_array[m] = cmpy_imag_array[m][0 +: CMPY_P_VALID_WIDTH]; + + assign weight_adc_real[m*CMPY_P_VALID_WIDTH +: CMPY_P_VALID_WIDTH] = weight_adc_real_array[m]; + assign weight_adc_imag[m*CMPY_P_VALID_WIDTH +: CMPY_P_VALID_WIDTH] = weight_adc_imag_array[m]; + + cmpy_16x12 u_cmpy_16x12 + ( + .aclk (clk ), // input wire aclk + .s_axis_a_tvalid (din_weight_valid ), // input wire s_axis_a_tvalid + .s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid (din_adc_valid ), // input wire s_axis_b_tvalid + .s_axis_b_tdata (cmpy_b ), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata + ); +end + +assign weight_adc_valid = spatial_filter_cmpy[0].cmpy_p_vld; + +// multi-channel sum +wire weight_adc_sum_valid; +wire [FILTER_SUM_WIDTH-1 : 0] weight_adc_sum_real; +wire [FILTER_SUM_WIDTH-1 : 0] weight_adc_sum_imag; + +adder_tree_ppl #( + .DATA_I_WIDTH (CMPY_P_VALID_WIDTH), + .DATA_NUM (CH_NUM ) +) u_multi_ch_add_ppl_i ( + // clock & reset + .clk (clk ), + .rst (rst ), + + // input data + .din_valid (weight_adc_valid ), + .din_data (weight_adc_real ), + + // output data + .dout_valid (weight_adc_sum_valid ), + .dout_data (weight_adc_sum_real ) +); + +adder_tree_ppl #( + .DATA_I_WIDTH (CMPY_P_VALID_WIDTH), + .DATA_NUM (CH_NUM ) +) u_multi_ch_add_ppl_q ( + // clock & reset + .clk (clk ), + .rst (rst ), + + // input data + .din_valid (weight_adc_valid ), + .din_data (weight_adc_imag ), + + // output data + .dout_valid ( ), + .dout_data (weight_adc_sum_imag ) +); + +// output filtered signal +assign dout_valid = weight_adc_sum_valid; + +if (FILTER_O_WIDTH <= FILTER_SUM_WIDTH) begin + // truncate msb + assign dout_real = weight_adc_sum_real[FILTER_SUM_WIDTH-1 -: FILTER_O_WIDTH]; + assign dout_imag = weight_adc_sum_imag[FILTER_SUM_WIDTH-1 -: FILTER_O_WIDTH]; +end +else begin + // append zeros to fit output data width + assign dout_real = {weight_adc_sum_real,{(FILTER_O_WIDTH-FILTER_SUM_WIDTH){1'b0}}}; + assign dout_imag = {weight_adc_sum_imag,{(FILTER_O_WIDTH-FILTER_SUM_WIDTH){1'b0}}}; +end + + +endmodule + +// This module has been tested during the simulation of [rx_pre_process] \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/weight_vec_formatting.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/weight_vec_formatting.v new file mode 100644 index 0000000..d099869 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/weight_vec_formatting.v @@ -0,0 +1,410 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/10 11:48:23 +// Design Name: +// Module Name: weight_vec_formatting +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Format the input 1-bit stream to weight vector. +// Parameter: +// COL_NUM: Column number of output vector. +// WEIGHT_WIDTH: Bit width of input weight vector element (retrieve from +// stream data). +// DATA_O_WIDTH: Bit width of output vector element, and bit width of +// FRAME_HEAD: Frame head indicate weight vector frame. +// FIFO_CDC_DEPTH: Depth of [clk_96m] to [sys_clk] cdc fifo. +// Data format: +// din_data: Suppose the output vector x = [x11 x21 x31 x41]^T, then +// din_data = {FRAME_HEAD[msb], ..., FRAME_HEAD[lsb], FRAME_LEN[msb], +// ..., FRAME_LEN[lsb], Re{x11}[msb], ..., Re{x11}[lsb], Im{x11}[msb], ..., +// Im{x11}[lsb], ..., Re{x41}[msb], ......, Im{x41}[lsb]} +// dout_valid: Indicate [dout_data] is valid. +// dout_real/imag: +// dout_real = {Re{x41}, Re{x31}, Re{x21}, Re{x11}} +// dout_imag = {Im{x41}, Im{x31}, Im{x21}, Im{x11}} +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module weight_vec_formatting +#( + parameter COL_NUM = 4, + parameter WEIGHT_WIDTH = 32, + parameter DATA_O_WIDTH = 16, + parameter FRAME_HEAD = 32'h7E7E7E7E, + parameter FIFO_CDC_DEPTH = 32 +) +( + // clock & reset + input sys_clk, + input sys_rst, + input clk_96m, + input ant_rst, + + // input data + input din_data, + + input fifo_cdc_rst, + + // output data + output dout_valid, + output [COL_NUM*DATA_O_WIDTH-1 : 0] dout_real, + output [COL_NUM*DATA_O_WIDTH-1 : 0] dout_imag +); + +localparam CMPLX_DIM = 2; +localparam FRAME_LEN = COL_NUM*CMPLX_DIM; +localparam BYTE_LEN = 4 * (COL_NUM*CMPLX_DIM + 2); + +// available state +localparam STATE_NUM_DIN = 3; +localparam STATE_IDLE_DIN = 0; +localparam STATE_LEN_DIN = 1; +localparam STATE_DATA_DIN = 2; + +localparam STATE_NUM_DOUT = 2; +localparam STATE_IDLE_DOUT = 0; +localparam STATE_READ_DOUT = 1; + +genvar i; +integer m; + +// input data shift register +reg [WEIGHT_WIDTH-1 : 0] din_shift = 'b0; + +always @(posedge clk_96m) begin + if (ant_rst) begin + din_shift <= 'b0; + end + else begin + din_shift <= {din_shift[WEIGHT_WIDTH-2 : 0],din_data}; + end +end + +// input data center state machine & counter +reg [$clog2(STATE_NUM_DIN)-1 : 0] state_din = STATE_IDLE_DIN; +reg [$clog2(WEIGHT_WIDTH)-1 : 0] bit_cnt = 'b0; // bit counter within one frame +reg [$clog2(FRAME_LEN)-1 : 0] frame_cnt = 'b0; // frame counter + +always @(posedge clk_96m) begin + if (ant_rst) begin + state_din <= STATE_IDLE_DIN; + end + else begin + case (state_din) + STATE_IDLE_DIN: state_din <= (din_shift == FRAME_HEAD) ? STATE_LEN_DIN : STATE_IDLE_DIN; + STATE_LEN_DIN : begin + if (bit_cnt == WEIGHT_WIDTH-1) begin + state_din <= (din_shift == BYTE_LEN) ? STATE_DATA_DIN : STATE_IDLE_DIN; + end + else begin + state_din <= STATE_LEN_DIN; + end + end + STATE_DATA_DIN: state_din <= (frame_cnt == FRAME_LEN-1 && bit_cnt == WEIGHT_WIDTH-1) ? STATE_IDLE_DIN : STATE_DATA_DIN; + default: state_din <= STATE_IDLE_DIN; + endcase + end +end + +always @(posedge clk_96m) begin + if (ant_rst) begin + bit_cnt <= 'b0; + end + else if (state_din == STATE_IDLE_DIN) begin + bit_cnt <= 'b0; + end + else begin + bit_cnt <= (bit_cnt == WEIGHT_WIDTH-1) ? 'b0 : bit_cnt + 1'b1; + end +end + +always @(posedge clk_96m) begin + if (ant_rst) begin + frame_cnt <= 'b0; + end + else if (state_din == STATE_IDLE_DIN) begin + frame_cnt <= 'b0; + end + else if (state_din == STATE_DATA_DIN && bit_cnt == WEIGHT_WIDTH-1) begin + frame_cnt <= frame_cnt + 1'b1; + end + else begin + frame_cnt <= frame_cnt; + end +end + +// clock domain crossing fifo, write channel +reg [DATA_O_WIDTH-1 : 0] fifo_din = 'b0; +reg fifo_wr_en = 'b0; + +always @(posedge clk_96m) begin + if (ant_rst) begin + fifo_din <= 'b0; + fifo_wr_en <= 'b0; + end + else if (state_din == STATE_DATA_DIN && bit_cnt == DATA_O_WIDTH-1) begin + fifo_din <= din_shift[DATA_O_WIDTH-1 -: DATA_O_WIDTH]; + fifo_wr_en <= 1'b1; + end + else begin + fifo_din <= fifo_din; + fifo_wr_en <= 'b0; + end +end + +// clock domain crossing fifo, read channel +reg fifo_rd_en = 'b0; +reg fifo_rd_en_d1 = 'b0; +reg [$clog2(COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt = 'b0; +reg [$clog2(COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt_d1 = 'b0; // read data latency +reg fifo_rd_valid = 'b0; +wire [DATA_O_WIDTH-1 : 0] fifo_dout; +wire [$clog2(COL_NUM*CMPLX_DIM*2)-1 : 0] fifo_rd_num; +wire fifo_full; +wire fifo_empty; +reg [DATA_O_WIDTH-1 : 0] dout_array_cdc [0 : COL_NUM*CMPLX_DIM-1]; + +always @(posedge sys_clk) begin + if (sys_rst) begin + fifo_rd_en <= 'b0; + end + else if (fifo_rd_num == COL_NUM*CMPLX_DIM) begin + fifo_rd_en <= 1'b1; + end + else if (fifo_rd_cnt == COL_NUM*CMPLX_DIM-1) begin + fifo_rd_en <= 'b0; + end + else begin + fifo_rd_en <= fifo_rd_en; + end +end + +always @(posedge sys_clk) begin + if (sys_rst) begin + fifo_rd_en_d1 <= 'b0; + end + else begin + fifo_rd_en_d1 <= fifo_rd_en; + end +end + +always @(posedge sys_clk) begin + if (sys_rst) begin + fifo_rd_cnt <= 'b0; + end + else if (fifo_rd_en) begin + fifo_rd_cnt <= fifo_rd_cnt + 1'b1; + end + else begin + fifo_rd_cnt <= 'b0; + end +end + +always @(posedge sys_clk) begin + if (sys_rst) begin + fifo_rd_cnt_d1 <= 'b0; + end + else begin + fifo_rd_cnt_d1 <= fifo_rd_cnt; + end +end + +always @(posedge sys_clk) begin + if (sys_rst) begin + fifo_rd_valid <= 'b0; + end + else if (fifo_rd_cnt_d1 == COL_NUM*CMPLX_DIM-1) begin + fifo_rd_valid <= 1'b1; + end + else begin + fifo_rd_valid <= 'b0; + end +end + +always @(posedge sys_clk) begin + if (sys_rst) begin + for (m = 0; m < COL_NUM*CMPLX_DIM; m = m + 1) begin + dout_array_cdc[m] <= 'b0; + end + end + else if (fifo_rd_en_d1) begin + dout_array_cdc[fifo_rd_cnt_d1] <= fifo_dout; + end + else begin + for (m = 0; m < COL_NUM*CMPLX_DIM; m = m + 1) begin + dout_array_cdc[m] <= dout_array_cdc[m]; + end + end +end + +fifo_weight_cdc u_fifo_weight_cdc +( + .rst (fifo_cdc_rst ), // input wire rd_rst + .wr_clk (clk_96m ), // input wire wr_clk + .rd_clk (sys_clk ), // input wire rd_clk + .din (fifo_din ), // input wire [15 : 0] din + .wr_en (fifo_wr_en ), // input wire wr_en + .rd_en (fifo_rd_en ), // input wire rd_en + .dout (fifo_dout ), // output wire [15 : 0] dout + .full (fifo_full ), // output wire full + .empty (fifo_empty ), // output wire empty + .rd_data_count (fifo_rd_num ) // output wire [3 : 0] rd_data_count +); + +// format output data array +wire [DATA_O_WIDTH-1 : 0] dout_real_array [0 : COL_NUM-1]; +wire [DATA_O_WIDTH-1 : 0] dout_imag_array [0 : COL_NUM-1]; + +generate +for(i = 0; i < COL_NUM; i = i + 1) begin: array_convert_stg1 + assign dout_real_array[i] = dout_array_cdc[2*i]; + assign dout_imag_array[i] = dout_array_cdc[2*i+1]; +end +endgenerate + +generate +for(i = 0; i < COL_NUM; i = i + 1) begin: array_convert_stg2 + assign dout_real[i*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_real_array[i]; + assign dout_imag[i*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_imag_array[i]; +end +endgenerate + +assign dout_valid = fifo_rd_valid; + +endmodule + + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/10/30 20:46:26 +// Design Name: +// Module Name: tb_wvec_format +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Testbench for [weight_vec_formatting] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// ------------------------------- +// MATLAB Code for data generation +// ------------------------------- +// COLUMN_NUM = 4; +// DATA_O_WIDTH = 32; + +// rng(0); +// data = rand(4,2)*2-1; +// d_32b = round(data.*(2^(DATA_O_WIDTH-1)-1)); +// d_32b_cmplx = d_32b(:,1) + 1i*d_32b(:,2); + + +// module tb_wvec_format; + +// localparam ROW_NUM = 1; +// localparam COL_NUM = 4; +// localparam WEIGHT_WIDTH = 32; +// localparam DATA_O_WIDTH = 16; +// localparam FRAME_HEAD = 32'b10110011100011110000111000110010; +// localparam FRAME_BITS = (2+COL_NUM*2)*WEIGHT_WIDTH + 1024; + +// reg sys_clk = 1'b1; +// reg sys_rst = 1'b1; +// reg clk_96m = 1'b1; +// reg ant_rst = 1'b1; +// wire din_data; +// reg [FRAME_BITS-1 : 0] din_buf = +// { +// FRAME_HEAD, 32'd40, +// 32'd1351727940, 32'd568478634, +// 32'd1742863098, -32'd1728550798, +// -32'd1602079424, -32'd951342906, +// 32'd1775435782, 32'd201354592, +// 1024'd0 +// }; + + +// wire dout_valid; +// wire [COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag; + +// weight_vec_formatting #( +// .COL_NUM (COL_NUM), +// .DATA_O_WIDTH (DATA_O_WIDTH), +// .WEIGHT_WIDTH (WEIGHT_WIDTH), +// .FRAME_HEAD (FRAME_HEAD ) +// ) u_weight_vec_formatting +// ( +// // clock & reset +// .sys_clk (sys_clk ), // input sys_clk +// .sys_rst (sys_rst ), // input sys_rst +// .clk_96m (clk_96m ), // input clk_96m +// .ant_rst (ant_rst ), // input ant_rst + +// // input data +// .din_data (din_data ), + +// // output data +// .dout_valid (dout_valid ), +// .dout_real (dout_real ), +// .dout_imag (dout_imag ) +// ); + +// always begin +// #20 sys_clk = ~sys_clk; +// end + +// always begin +// #7; +// clk_96m = ~clk_96m; +// #3; +// end + +// initial begin +// #102 +// sys_rst = 1'b0; +// ant_rst = 1'b0; +// end + +// reg [$clog2(FRAME_BITS)-1 : 0] din_cnt; + +// always @(posedge clk_96m) begin +// if (sys_rst) begin +// din_cnt <= 'b0; +// end +// else begin +// din_cnt <= (din_cnt == FRAME_BITS-1) ? 'b0 : din_cnt + 1'b1; +// end +// end + +// assign din_data = din_buf[FRAME_BITS-1-din_cnt]; + +// endmodule \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/system_top.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/system_top.v new file mode 100644 index 0000000..19d0ca0 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/system_top.v @@ -0,0 +1,1114 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2021/12/14 15:54:11 +// Design Name: +// Module Name: system_top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module system_top +( + /*************************************************************************** + * Contents + * 01. Clocks + * 02. AD9516 Interface + * 03. AD9361-1 Interface + * 04. AD9361-2 Interface + * 05. Phased-Array Control + * 06. RF Synthesizer Control + * 07. LVDS for Time Synchronization + * 08. Debug IO + **************************************************************************/ + + // ************************************************************************* + // ******************************** Clocks ********************************* + // ************************************************************************* + // power-up configure clock + input clk_25m , + // 250mhz backup clock + input clk_250m_p , // generated by ad9516, 250mhz + input clk_250m_n , + // ad9361 buffered clock + input ad9361_1_buffer_clk , // derived from ad9361 input clock + input ad9361_2_buffer_clk , // derived from ad9361 input clock + // ************************************************************************* + // *************************** AD9516 Interface **************************** + // ************************************************************************* + // spi interface + output ad9516_spi_clk , + output ad9516_spi_csn , + inout ad9516_spi_mosi , + input ad9516_spi_miso , + // control signals + input ad9516_refmon , // ad9516 reference clock monitor + input ad9516_ld , // ad9516 lock detect + input ad9516_status , // ad9516 multiple selectable status output + output ad9516_pd_b , // ad9516 active-low power down control + output ad9516_reset_b , // ad9516 active-low reset control + output ad9516_sync_b , // ad9516 active-low manual synchronization control + // ************************************************************************* + // ************************** AD9361-1 Interface *************************** + // ************************************************************************* + // rx data (rx channels are tied to ground physically) + input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz + input ad9361_1_rx_frame , + input [11:0] ad9361_1_rx_data , + // tx data + output ad9361_1_tx_fb_clk , + output ad9361_1_tx_frame , + output [11:0] ad9361_1_tx_data , + // spi interface + output ad9361_1_spi_clk , + output ad9361_1_spi_csn , + inout ad9361_1_spi_mosi , + input ad9361_1_spi_miso , + // control signals + output ad9361_1_reset_b , // ad9361 active-low reset control + output ad9361_1_en_agc , // ad9361 manual agc control + output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed) + output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed) + output [ 3:0] ad9361_1_ctrl_in , + input [ 7:0] ad9361_1_ctrl_out , + output ad9361_sync , + // ************************************************************************* + // ************************** AD9361-2 Interface *************************** + // ************************************************************************* + // rx data (rx channels are tied to ground physically) + input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz + input ad9361_2_rx_frame , + input [11:0] ad9361_2_rx_data , + // tx data + output ad9361_2_tx_fb_clk , + output ad9361_2_tx_frame , + output [11:0] ad9361_2_tx_data , + // spi interface + output ad9361_2_spi_clk , + output ad9361_2_spi_csn , + inout ad9361_2_spi_mosi , + input ad9361_2_spi_miso , + // control signals + output ad9361_2_reset_b , // ad9361 active-low reset control + output ad9361_2_en_agc , // ad9361 manual agc control + output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed) + output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed) + output [ 3:0] ad9361_2_ctrl_in , + input [ 7:0] ad9361_2_ctrl_out , + // ************************************************************************* + // ************************* Phased-Array Control ************************** + // ************************************************************************* + output ant_cin , + output ant_din0 , + output ant_din1 , + input ant_cout , + input ant_dout0 , + input ant_dout1 , + output ant_tr , + output ant_dary , + // ************************************************************************* + // ************************ RF Synthesizer Control ************************* + // ************************************************************************* + output rf_standby , + output rf_sw_pll , + output rf_t , + output rf_r , + output rf_sw_bpf , + output rf_sclk1 , + output rf_sdio1 , + output rf_cs1 , + input rf_ld1 , + output rf_sclk2 , + output rf_sdio2 , + output rf_cs2 , + input rf_ld2 , + output rf_sclk3 , + output rf_sdio3 , + output rf_cs3 , + input rf_ld3 , + output rf_tmgc_16 , + output rf_tmgc_8 , + output rf_tmgc_4 , + output rf_tmgc_2 , + output rf_tmgc_1 , + output rf_rmgc_16 , + output rf_rmgc_8 , + output rf_rmgc_4 , + output rf_rmgc_2 , + output rf_rmgc_1 , + output rf_enable , + output rf_sc , + output rf_sd , + output rf_endsyn , + input rf_sdout , + inout rf_dq_wd , + output rf_sw_rx , + // ************************************************************************* + // ********************* LVDS for Time Synchronization ********************* + // ************************************************************************* + // 1st group + input lvds_in_1 , + output lvds_out_1 , + // 2nd group (these pins can be disconnected physically) + input lvds_in_2 , + output lvds_out_2 , + // ************************************************************************* + // ******************************* Debug IO ******************************** + // ************************************************************************* + // 3.3v ports + output uart1_txd , + input uart1_rxd , + output uart2_txd , + input uart2_rxd , + output uart3_txd , + input uart3_rxd , + inout debug_io_1 , + inout debug_io_2 , + inout debug_io_3 , + inout debug_io_4 , + inout debug_io_5 , + inout debug_io_6 , + inout debug_io_7 , + inout debug_io_8 , + // 1.8v ports + inout debug_io_00_p , + inout debug_io_01_p , + inout debug_io_02_p , + inout debug_io_03_p , + inout debug_io_04_p , + inout debug_io_05_p , + inout debug_io_06_p , + inout debug_io_07_p , + inout debug_io_08_p +); + +/******************************************************************************* + * Contents + * 01. Input/Output Buffer + * 02. System Clock Generation + * 03. Block Design Interface + * 04. Phased-Array Control + * 05. RF Synthesizer Control + * 06. LVDS for Time Synchronization + * 07. Tx Signals + * 08. Rx Signals + * 09. ILAs and VIOs + ******************************************************************************/ + +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////// System Clock Generation //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// global reset +wire sys_rst ; // global reset signal, active high +wire ant_rst ; // phased-array & rf control reset signal, active high + +// pl signal processing clock +wire sys_clk ; // 48MHz 41.6667MHz +wire sys_clk_2x ; // 96MHz 83.3333MHz +wire sys_clk_3x ; // 144MHz 125MHz +wire sys_clk_4x ; // 192MHz 166.6667MHz +wire sys_clk_ld ; // system main clock locked indicator + +// ad9361-1 clocks +wire ad9361_1_clk ; // 48MHz 41.6667MHz +wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz +wire ad9361_1_clk_3x ; // 144MHz 125MHz +wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz +wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator + +// ad9361-2 clocks +wire ad9361_2_clk ; // 48MHz 41.6667MHz +wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz +wire ad9361_2_clk_3x ; // 144MHz 125MHz +wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz +wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator + +// phased-array & rf control clocks +wire clk_96m ; +wire clk_48m ; +wire clk_32m ; +wire clk_19p2m ; + +clk_dist u_clk_dist +( + // input clocks + .clk_250m_p (clk_250m_p ), // generated by ad9516, 250mhz + .clk_250m_n (clk_250m_n ), + .ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz + .ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz + + // output clocks & reset + // global reset + .sys_rst (sys_rst ), // global reset signal, active high + .ant_rst (ant_rst ), // phased-array & rf control reset signal, active high + + // pl signal processing clock + .sys_clk (sys_clk ), // 48MHz 41.6667MHz + .sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz + .sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz + .sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz + .sys_clk_ld (sys_clk_ld ), // system main clock locked indicator + + // ad9361-1 clocks + .ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz + .ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz + .ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz + .ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz + .ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator + + // ad9361-2 clocks + .ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz + .ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz + .ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz + .ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz + .ad9361_2_clk_ld (ad9361_2_clk_ld ), // ad9361-2 clock group locked indicator + + // phased-array & rf control clocks + .clk_96m (clk_96m ), + .clk_48m (clk_48m ), + .clk_32m (clk_32m ), + .clk_19p2m (clk_19p2m ) +); + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Block Design Interface //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// gpio +wire [31:0] gpio_i; +wire [31:0] gpio_o; +wire ad9361_rx_fifo_rst; +wire ad9361_1_cal_start; +wire ad9361_1_cal_done; +wire ad9361_2_cal_start; +wire ad9361_2_cal_done; +wire ad9361_cal_result; +wire ad9361_recal; + +assign ad9516_pd_b = gpio_o[ 0]; +assign ad9516_reset_b = gpio_o[ 1]; +assign ad9516_sync_b = gpio_o[ 2]; +assign ad9361_1_txnrx = gpio_o[ 3]; // ad9361 enable state machine control +assign ad9361_1_enable = gpio_o[ 4]; // ad9361 enable state machine control +assign ad9361_1_en_agc = gpio_o[ 5]; // ad9361 agc control +assign ad9361_1_reset_b = gpio_o[ 6]; // ad9361 reset +assign ad9361_1_ctrl_in = gpio_o[10:7]; +assign ad9361_2_txnrx = gpio_o[11]; // ad9361 enable state machine control +assign ad9361_2_enable = gpio_o[12]; // ad9361 enable state machine control +assign ad9361_2_en_agc = gpio_o[13]; // ad9361 agc control +assign ad9361_2_reset_b = gpio_o[14]; // ad9361 reset +assign ad9361_2_ctrl_in = gpio_o[18:15]; +assign ad9361_sync = gpio_o[19]; +assign ad9361_rx_fifo_rst = gpio_o[20]; +assign ad9361_1_cal_start = gpio_o[21]; +assign ad9361_2_cal_start = gpio_o[22]; +assign ad9361_recal = gpio_o[23]; +assign ad9361_tx_switch = gpio_o[24]; + +assign gpio_i[ 7:0] = ad9361_1_ctrl_out; +assign gpio_i[15:8] = ad9361_2_ctrl_out; +assign gpio_i[16] = ad9516_refmon; +assign gpio_i[17] = ad9516_ld; +assign gpio_i[18] = ad9516_status; +assign gpio_i[19] = ad9361_1_cal_done; +assign gpio_i[20] = ad9361_2_cal_done; +assign gpio_i[21] = ad9361_cal_result; + +// spi interface +wire spi_sclk ; +wire [ 2:0] spi_cs ; +reg spi_sdi ; +wire spi_sdo ; +wire spi_sdo_t ; +wire spi_three_wire; +wire spi_active ; + +// ad9516 - three-wire spi or four-wire spi +assign ad9516_spi_clk = spi_sclk; +assign ad9516_spi_csn = spi_cs[0]; +assign ad9516_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; +// ad9361-1 - three-wire spi or four-wire spi +assign ad9361_1_spi_clk = spi_sclk; +assign ad9361_1_spi_csn = spi_cs[1]; +assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; +// ad9361-2 - three-wire spi or four-wire spi +assign ad9361_2_spi_clk = spi_sclk; +assign ad9361_2_spi_csn = spi_cs[2]; +assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; +// select sdi signal +always @(*) begin + if (~ad9516_spi_csn) + spi_sdi = spi_three_wire ? ad9516_spi_mosi : ad9516_spi_miso; + else if (~ad9361_1_spi_csn) + spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso; + else if (~ad9361_2_spi_csn) + spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso; + else + spi_sdi = 1'bz; +end + +system_bd_wrapper u_system_bd_wrapper +( + // ps system clock input + .clk_25MHz (clk_25m ), // input clk_25MHz + + // gpio, for control signals + .gpio_i (gpio_i ), // input [31:0]gpio_i + .gpio_o (gpio_o ), // output [31:0]gpio_o + + // spi interface + .spi_sclk (spi_sclk ), // output spi_sclk + .spi_cs (spi_cs ), // output [2:0]spi_cs + .spi_sdi (spi_sdi ), // input [0:0]spi_sdi + .spi_sdo (spi_sdo ), // output spi_sdo + .spi_sdo_t (spi_sdo_t ), // output spi_sdo_t + .spi_three_wire (spi_three_wire ), // output spi_three_wire + .spi_active (spi_active ) // output spi_active +); + + +//////////////////////////////////////////////////////////////////////////////// +///////////////// Phased-Array & RF Synthesizer Control & C2C ////////////////// +//////////////////////////////////////////////////////////////////////////////// +// antenna & rf interface +wire rf_clk ; +wire rf_en ; +wire rf_data; +wire rf_tr ; +wire rf_dary; +wire rf_dout; + +// nulling algorithm +wire accor_stream_valid; +wire accor_stream_data; +reg weight_stream_data = 'b0 ; + +// buffer output data +reg ant_din1_buf = 'b0; +reg ant_tr_buf = 'b0; +reg ant_dary_buf = 'b0; + +assign ant_cin = clk_96m ; +assign ant_din1 = ant_din1_buf; +assign ant_tr = ant_tr_buf ; +assign ant_dary = ant_dary_buf; + +always @(posedge clk_96m) begin + if (ant_rst) begin + ant_din1_buf <= 'b0; + ant_tr_buf <= 'b0; + ant_dary_buf <= 'b0; + end + else begin + ant_din1_buf <= (accor_stream_valid) ? accor_stream_data : rf_data; + ant_tr_buf <= rf_tr; + ant_dary_buf <= rf_dary; + end +end + +// input data +reg ant_dout1_d1 = 'b0; +reg ant_dout1_d2 = 'b0; + +always @(posedge clk_96m) begin + if (ant_rst) begin + ant_dout1_d1 <= 'b0; + ant_dout1_d2 <= 'b0; + weight_stream_data <= 'b0; + end + else begin + ant_dout1_d1 <= ant_dout1; + ant_dout1_d2 <= ant_dout1_d1; + weight_stream_data <= ant_dout1_d2; + end +end + +ant_rf_ctrl u_ant_rf_ctrl +( + .clk_48m (clk_48m ), // input clk_48m + .clk_96m (clk_96m ), // input clk_96m + .clk_32m (clk_32m ), // input clk_32m + .clk_19p2m (clk_19p2m ), // input clk_19p2m + .sys_rst (ant_rst ), // input sys_rst + + .ant_clk (rf_clk ), // output ant_clk + .ant_en (rf_en ), // output ant_en + .ant_data (rf_data ), // output ant_data + .ant_tr (rf_tr ), // output ant_tr + .ant_dary (rf_dary ), // output ant_dary + .ant_dout (ant_dout1_d2), // input ant_dout + + .rf_standby (rf_standby ), // output rf_standby + .rf_sw_pll (rf_sw_pll ), // output rf_sw_pll + .rf_t (rf_t ), // output rf_t + .rf_r (rf_r ), // output rf_r + .rf_sw_bpf (rf_sw_bpf ), // output rf_sw_bpf + .rf_sclk1 (rf_sclk1 ), // output rf_sclk1 + .rf_sdio1 (rf_sdio1 ), // output rf_sdio1 + .rf_cs1 (rf_cs1 ), // output rf_cs1 + .rf_ld1 (rf_ld1 ), // input rf_ld1 + .rf_sclk2 (rf_sclk2 ), // output rf_sclk2 + .rf_sdio2 (rf_sdio2 ), // output rf_sdio2 + .rf_cs2 (rf_cs2 ), // output rf_cs2 + .rf_ld2 (rf_ld2 ), // input rf_ld2 + .rf_sclk3 (rf_sclk3 ), // output rf_sclk3 + .rf_sdio3 (rf_sdio3 ), // output rf_sdio3 + .rf_cs3 (rf_cs3 ), // output rf_cs3 + .rf_ld3 (rf_ld3 ), // input rf_ld3 + .rf_tmgc_16 (rf_tmgc_16 ), // output rf_tmgc_16 + .rf_tmgc_8 (rf_tmgc_8 ), // output rf_tmgc_8 + .rf_tmgc_4 (rf_tmgc_4 ), // output rf_tmgc_4 + .rf_tmgc_2 (rf_tmgc_2 ), // output rf_tmgc_2 + .rf_tmgc_1 (rf_tmgc_1 ), // output rf_tmgc_1 + .rf_rmgc_16 (rf_rmgc_16 ), // output rf_rmgc_16 + .rf_rmgc_8 (rf_rmgc_8 ), // output rf_rmgc_8 + .rf_rmgc_4 (rf_rmgc_4 ), // output rf_rmgc_4 + .rf_rmgc_2 (rf_rmgc_2 ), // output rf_rmgc_2 + .rf_rmgc_1 (rf_rmgc_1 ), // output rf_rmgc_1 + .rf_enable (rf_enable ), // output rf_enable + .rf_sc (rf_sc ), // output rf_sc + .rf_sd (rf_sd ), // output rf_sd + .rf_endsyn (rf_endsyn ), // output rf_endsyn + .rf_sdout (rf_sdout ), // input rf_sdout + .rf_dq_wd (rf_dq_wd ), // inout rf_dq_wd + .rf_sw_rx (rf_sw_rx ) // output rf_sw_rx +); + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////// LVDS for Time Synchronization ///////////////////////// +//////////////////////////////////////////////////////////////////////////////// + + + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////////// Tx Signals ////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// baseband signal +wire [11:0] tx_data_i; +wire [11:0] tx_data_q; +wire [11:0] tx_ch1_i; +wire [11:0] tx_ch1_q; +wire [11:0] tx_ch2_i; +wire [11:0] tx_ch2_q; + +ad9361_tx_map_cmos_dual u_ad9361_tx_map +( + .clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in + .clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst + + .tx_data_clk (sys_clk ), // input tx_data_clk + .tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst + + .tx_ch1_i (tx_ch1_i ), // input [11:0] tx_ch1_i + .tx_ch1_q (tx_ch1_q ), // input [11:0] tx_ch1_q + .tx_ch2_i (tx_ch2_i ), // input [11:0] tx_ch2_i + .tx_ch2_q (tx_ch2_q ), // input [11:0] tx_ch2_q + .clk_out (ad9361_1_tx_fb_clk ), // output clk_out + .tx_frame (ad9361_1_tx_frame ), // output tx_frame + .tx_data (ad9361_1_tx_data ) // output [11:0] tx_data +); + +assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk; +// assign ad9361_2_tx_frame = ad9361_1_tx_frame ; +// assign ad9361_2_tx_data = ad9361_1_tx_data ; + +tx_pre_process #( + .CAL_MOD_FINE (0) +) u_tx_pre_process +( + // clock & reset + .clk (sys_clk ), + .rst (sys_rst ), + // input data + .tx_data_ch1_i (tx_data_i ), + .tx_data_ch1_q (tx_data_q ), + .tx_data_ch2_i (tx_data_i ), + .tx_data_ch2_q (tx_data_q ), + // ad9361 calibration interface + .ad9361_tx_switch (ad9361_tx_switch ), + // + .bb_rshift (1'b0 ), + // output data + .tx_ch1_i (tx_ch1_i ), + .tx_ch1_q (tx_ch1_q ), + .tx_ch2_i (tx_ch2_i ), + .tx_ch2_q (tx_ch2_q ) +); + +// <---------------------------------------------------------------------------> +// <--------------------- insert transmitter logic below ----------------------> +// <---------------------------------------------------------------------------> +wire [ 1:0] waveform_sel; +wire sweep_on ; +wire [31:0] freq_set ; +wire [ 1:0] iq_sel ; +wire [ 3:0] bb_rshift ; + +tx_qpsk #( + .BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001), + .BIT_DATA_LEN (1024), + .CLK_FREQ (48000000) +) u_tx_qpsk +( + .clk (sys_clk ), // input clk + .rst (sys_rst ), // input rst + .tx_data_i (tx_data_i ), // output [11:0] tx_data_i + .tx_data_q (tx_data_q ), // output [11:0] tx_data_q + // debug ports + .waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel + .sweep_on (sweep_on ), // input sweep_on + .freq_set (freq_set ), // input [31:0] freq_set + .iq_sel (iq_sel ), // input [ 1:0] iq_sel + .bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift +); + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////////// Rx Signals ////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +reg [11:0] rx_ch1_i, rx_ch1_q; +reg [11:0] rx_ch2_i, rx_ch2_q; +reg [11:0] rx_ch3_i, rx_ch3_q; +reg [11:0] rx_ch4_i, rx_ch4_q; + +wire [11:0] rx_ch1_i_9361, rx_ch1_q_9361; +wire [11:0] rx_ch2_i_9361, rx_ch2_q_9361; +wire [11:0] rx_ch3_i_9361, rx_ch3_q_9361; +wire [11:0] rx_ch4_i_9361, rx_ch4_q_9361; + +wire [11:0] rx_ch1_i_test, rx_ch1_q_test; +wire [11:0] rx_ch2_i_test, rx_ch2_q_test; +wire [11:0] rx_ch3_i_test, rx_ch3_q_test; +wire [11:0] rx_ch4_i_test, rx_ch4_q_test; + +wire [15:0] phase_ch1; +wire [15:0] phase_ch2; +wire [15:0] phase_ch3; +wire [15:0] phase_ch4; + +wire rx_data_valid; +wire [29:0] rx_data_i, rx_data_q; + +wire hop_trigger; +wire hop_trigger_en; +wire rx_test_en; +wire lcmv_en; + +wire hop_start_flag ; +// wire accor_stream_valid ; +// wire accor_stream_data ; +// wire weight_stream_data ; + +always @(posedge sys_clk) begin + if (sys_rst) begin + rx_ch1_i <= 'b0; + rx_ch2_i <= 'b0; + rx_ch3_i <= 'b0; + rx_ch4_i <= 'b0; + rx_ch1_q <= 'b0; + rx_ch2_q <= 'b0; + rx_ch3_q <= 'b0; + rx_ch4_q <= 'b0; + end + else if (rx_test_en && ad9361_cal_valid) begin + rx_ch1_i <= rx_ch1_i_test; + rx_ch2_i <= rx_ch2_i_test; + rx_ch3_i <= rx_ch3_i_test; + rx_ch4_i <= rx_ch4_i_test; + rx_ch1_q <= rx_ch1_q_test; + rx_ch2_q <= rx_ch2_q_test; + rx_ch3_q <= rx_ch3_q_test; + rx_ch4_q <= rx_ch4_q_test; + end + else begin + rx_ch1_i <= rx_ch1_i_9361; + rx_ch2_i <= rx_ch2_i_9361; + rx_ch3_i <= rx_ch3_i_9361; + rx_ch4_i <= rx_ch4_i_9361; + rx_ch1_q <= rx_ch1_q_9361; + rx_ch2_q <= rx_ch2_q_9361; + rx_ch3_q <= rx_ch3_q_9361; + rx_ch4_q <= rx_ch4_q_9361; + end +end + +ad9361_rx_map_cmos_dual u_ad9361_1_rx_map +( + .clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in + .clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst + + .rx_data_clk (sys_clk ), // input rx_data_clk + .rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst + + .rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst + + .rx_frame (ad9361_1_rx_frame ), // input rx_frame + .rx_data (ad9361_1_rx_data ), // input [11:0] rx_data + .rx_ch1_i (rx_ch1_i_9361 ), // output [11:0] rx_ch1_i + .rx_ch1_q (rx_ch1_q_9361 ), // output [11:0] rx_ch1_q + .rx_ch2_i (rx_ch2_i_9361 ), // output [11:0] rx_ch2_i + .rx_ch2_q (rx_ch2_q_9361 ) // output [11:0] rx_ch2_q +); + +ad9361_rx_map_cmos_dual u_ad9361_2_rx_map +( + .clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in + .clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst + + .rx_data_clk (sys_clk ), // input rx_data_clk + .rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst + + .rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst + + .rx_frame (ad9361_2_rx_frame ), // input rx_frame + .rx_data (ad9361_2_rx_data ), // input [11:0] rx_data + .rx_ch1_i (rx_ch3_i_9361 ), // output [11:0] rx_ch1_i + .rx_ch1_q (rx_ch3_q_9361 ), // output [11:0] rx_ch1_q + .rx_ch2_i (rx_ch4_i_9361 ), // output [11:0] rx_ch2_i + .rx_ch2_q (rx_ch4_q_9361 ) // output [11:0] rx_ch2_q +); + +rx_pre_process #( + .OUTPUT_WIDTH (30 ) +) u_rx_pre_process +( + // clock & reset + .sys_clk (sys_clk ), // sync to adc data + .sys_clk_phy (sys_clk_3x ), // sync to physical layer + .sys_rst (sys_rst ), // sync to [sys_clk] + .clk_96m (clk_96m ), // sync to c2c data + .ant_rst (ant_rst ), // sync to [clk_96m] + // input data interface + .rx_ch1_i (rx_ch1_i ), + .rx_ch1_q (rx_ch1_q ), + .rx_ch2_i (rx_ch2_i ), + .rx_ch2_q (rx_ch2_q ), + .rx_ch3_i (rx_ch3_i ), + .rx_ch3_q (rx_ch3_q ), + .rx_ch4_i (rx_ch4_i ), + .rx_ch4_q (rx_ch4_q ), + // input channel phase + .phase_ch1 (phase_ch1 ), + .phase_ch2 (phase_ch2 ), + .phase_ch3 (phase_ch3 ), + .phase_ch4 (phase_ch4 ), + // ad9361 calibration interface + .ad9361_1_cal_start (ad9361_1_cal_start ), + .ad9361_1_cal_done (ad9361_1_cal_done ), + .ad9361_2_cal_start (ad9361_2_cal_start ), + .ad9361_2_cal_done (ad9361_2_cal_done ), + .ad9361_cal_result (ad9361_cal_result ), + .ad9361_cal_valid (ad9361_cal_valid ), + .ad9361_recal (ad9361_recal ), + // nulling algotithm interface + .hop_flag_in_phy (hop_start_flag ), // sync to [sys_clk_3x] + .sync_flag_phy (1'b0 ), // sync to [sys_clk_3x] + .lcmv_en_phy (lcmv_en ), // sync to [sys_clk_3x] + .hop_flag_out ( ), // sync to [sys_clk] + + .accor_stream_valid (accor_stream_valid ), // sync to [clk_96m] + .accor_stream_data (accor_stream_data ), // sync to [clk_96m] + .weight_stream_data (weight_stream_data ), // sync to [clk_96m] + .rx_data_valid (rx_data_valid ), // sync to [sys_clk] + .rx_data_i (rx_data_i ), // sync to [sys_clk] + .rx_data_q (rx_data_q ) // sync to [sys_clk] +); + +// temporary test cases +rx_pre_test u_rx_pre_test +( + // clock & reset + .clk (sys_clk ), + .clk_phy (sys_clk_3x ), + .rst (sys_rst ), + .hop_trigger (hop_trigger ), + .hop_trigger_en (hop_trigger_en ), + // calc result + .ad9361_cal_result (ad9361_cal_result ), + .ad9361_cal_valid (ad9361_cal_valid ), + // output test data + .rx_ch1_i (rx_ch1_i_test ), + .rx_ch1_q (rx_ch1_q_test ), + .rx_ch2_i (rx_ch2_i_test ), + .rx_ch2_q (rx_ch2_q_test ), + .rx_ch3_i (rx_ch3_i_test ), + .rx_ch3_q (rx_ch3_q_test ), + .rx_ch4_i (rx_ch4_i_test ), + .rx_ch4_q (rx_ch4_q_test ), + .hop_start_flag (hop_start_flag ) +); + +// <---------------------------------------------------------------------------> +// <----------------------- insert receiver logic below -----------------------> +// <---------------------------------------------------------------------------> +wire var_cal_start; +wire var_cal_auto_en; +wire var_cal_busy; +wire var_valid; +wire [31:0] var; +wire [31:0] var_ch1; +wire [31:0] var_ch2; +wire [31:0] var_ch3; +wire [31:0] var_ch4; + +var_cal #( + .ACCUM_NUM (16384 ), + .DATA_I_WIDTH (30 ), + .DATA_O_WIDTH (32 ) +) u_var_cal +( + .clk (sys_clk ), + .rst (sys_rst ), + + .cal_start (var_cal_start ), + .cal_auto_en(var_cal_auto_en), + .cal_busy (var_cal_busy ), + + .din_valid (rx_data_valid ), + .din_real (rx_data_i ), + .din_imag (rx_data_q ), + + .var_valid (var_valid ), + .var (var ) +); + +var_cal #( + .ACCUM_NUM (16384 ), + .DATA_I_WIDTH (12 ), + .DATA_O_WIDTH (32 ) +) u_var_cal_ch1 +( + .clk (sys_clk ), + .rst (sys_rst ), + + .cal_start (var_cal_start ), + .cal_auto_en(var_cal_auto_en), + .cal_busy ( ), + + .din_valid (rx_data_valid ), + .din_real (rx_ch1_i ), + .din_imag (rx_ch1_q ), + + .var_valid ( ), + .var (var_ch1 ) +); + +var_cal #( + .ACCUM_NUM (16384 ), + .DATA_I_WIDTH (12 ), + .DATA_O_WIDTH (32 ) +) u_var_cal_ch2 +( + .clk (sys_clk ), + .rst (sys_rst ), + + .cal_start (var_cal_start ), + .cal_auto_en(var_cal_auto_en), + .cal_busy ( ), + + .din_valid (rx_data_valid ), + .din_real (rx_ch2_i ), + .din_imag (rx_ch2_q ), + + .var_valid ( ), + .var (var_ch2 ) +); + +var_cal #( + .ACCUM_NUM (16384 ), + .DATA_I_WIDTH (12 ), + .DATA_O_WIDTH (32 ) +) u_var_cal_ch3 +( + .clk (sys_clk ), + .rst (sys_rst ), + + .cal_start (var_cal_start ), + .cal_auto_en(var_cal_auto_en), + .cal_busy ( ), + + .din_valid (rx_data_valid ), + .din_real (rx_ch3_i ), + .din_imag (rx_ch3_q ), + + .var_valid ( ), + .var (var_ch3 ) +); + +var_cal #( + .ACCUM_NUM (16384 ), + .DATA_I_WIDTH (12 ), + .DATA_O_WIDTH (32 ) +) u_var_cal_ch4 +( + .clk (sys_clk ), + .rst (sys_rst ), + + .cal_start (var_cal_start ), + .cal_auto_en(var_cal_auto_en), + .cal_busy ( ), + + .din_valid (rx_data_valid ), + .din_real (rx_ch4_i ), + .din_imag (rx_ch4_q ), + + .var_valid ( ), + .var (var_ch4 ) +); + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////// ILAs and VIOs ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// vio_clk_ld_rd u_vio_clk_ld_rd +// ( +// .clk (sys_clk ), +// .probe_in0 (ad9361_1_clk_ld), +// .probe_in1 (ad9361_2_clk_ld) +// ); + +vio_rfcontrl u_vio_rfcontrl +( + .clk (clk_48m ), // input wire clk + .probe_out0 (u_ant_rf_ctrl.vio_switch ), // output wire [0 : 0] probe_out0 + .probe_out1 (u_ant_rf_ctrl.vio_trdirection ), // output wire [0 : 0] probe_out1 + .probe_out2 (u_ant_rf_ctrl.vio_frequency[15:0] ), // output wire [15 : 0] probe_out2 + .probe_out3 (u_ant_rf_ctrl.vio_emitMGC[7:0] ), // output wire [7 : 0] probe_out3 + .probe_out4 (u_ant_rf_ctrl.vio_ch01MGC[3:0] ), // output wire [3 : 0] probe_out4 + .probe_out5 (u_ant_rf_ctrl.vio_ch02MGC[3:0] ), // output wire [3 : 0] probe_out5 + .probe_out6 (u_ant_rf_ctrl.vio_ch03MGC[3:0] ), // output wire [3 : 0] probe_out6 + .probe_out7 (u_ant_rf_ctrl.vio_ch04MGC[3:0] ), // output wire [3 : 0] probe_out7 + .probe_out8 (u_ant_rf_ctrl.vio_recvMGC[7:0] ), // output wire [7 : 0] probe_out8 + .probe_out9 (u_ant_rf_ctrl.vio_AntMod[7:0] ), // output wire [7 : 0] probe_out9 + .probe_out10(u_ant_rf_ctrl.vio_AntOffAxis[15:0] ), // output wire [15 : 0] probe_out10 + .probe_out11(u_ant_rf_ctrl.vio_AntYaw[15:0] ), // output wire [15 : 0] probe_out11 + .probe_out12(u_ant_rf_ctrl.vio_PrecessTime[15:0] ) // output wire [15 : 0] probe_out12 +); + +vio_ant_test u_vio_ant_test +( + .clk (clk_48m ), + .probe_out0 (u_ant_rf_ctrl.vio_mode_ant ), + .probe_out1 (u_ant_rf_ctrl.vio_hop_start ), + .probe_out2 (u_ant_rf_ctrl.vio_standby ), + .probe_out3 (u_ant_rf_ctrl.vio_hoptime[15:0] ) +); + +ila_rfcontrl u_ila_rfcontrl +( + .clk (clk_48m ), // input wire clk + .probe0 (u_ant_rf_ctrl.SPI_MOSI_F ), // input wire [0:0] + .probe1 (u_ant_rf_ctrl.SPI_MISO_F ), // input wire [0:0] + .probe2 (u_ant_rf_ctrl.SPI_SYN_F ), // input wire [0:0] + .probe3 (u_ant_rf_ctrl.TP_EN_F ), // input wire [0:0] + .probe4 (u_ant_rf_ctrl.TR_MGC_F ), // input wire [0:0] + .probe5 (u_ant_rf_ctrl.CAL_F ), // input wire [0:0] + .probe6 (u_ant_rf_ctrl.PRF ), // input wire [0:0] + .probe7 (u_ant_rf_ctrl.rf_standby ), // input wire [0:0] + .probe8 (u_ant_rf_ctrl.rf_sw_pll ), // input wire [0:0] + .probe9 (u_ant_rf_ctrl.rf_t ), // input wire [0:0] + .probe10(u_ant_rf_ctrl.rf_r ), // input wire [0:0] + .probe11(u_ant_rf_ctrl.rf_sw_bpf ), // input wire [0:0] + .probe12(u_ant_rf_ctrl.rf_sclk1 ), // input wire [0:0] + .probe13(u_ant_rf_ctrl.rf_sdio1 ), // input wire [0:0] + .probe14(u_ant_rf_ctrl.rf_cs1 ), // input wire [0:0] + .probe15(u_ant_rf_ctrl.rf_ld1 ), // input wire [0:0] + .probe16(u_ant_rf_ctrl.rf_sclk2 ), // input wire [0:0] + .probe17(u_ant_rf_ctrl.rf_sdio2 ), // input wire [0:0] + .probe18(u_ant_rf_ctrl.rf_cs2 ), // input wire [0:0] + .probe19(u_ant_rf_ctrl.rf_ld2 ), // input wire [0:0] + .probe20(u_ant_rf_ctrl.rf_sclk3 ), // input wire [0:0] + .probe21(u_ant_rf_ctrl.rf_sdio3 ), // input wire [0:0] + .probe22(u_ant_rf_ctrl.rf_cs3 ), // input wire [0:0] + .probe23(u_ant_rf_ctrl.rf_ld3 ), // input wire [0:0] + .probe24(u_ant_rf_ctrl.rf_tmgc_16 ), // input wire [0:0] + .probe25(u_ant_rf_ctrl.rf_tmgc_8 ), // input wire [0:0] + .probe26(u_ant_rf_ctrl.rf_tmgc_4 ), // input wire [0:0] + .probe27(u_ant_rf_ctrl.rf_tmgc_2 ), // input wire [0:0] + .probe28(u_ant_rf_ctrl.rf_tmgc_1 ), // input wire [0:0] + .probe29(u_ant_rf_ctrl.rf_rmgc_16 ), // input wire [0:0] + .probe30(u_ant_rf_ctrl.rf_rmgc_8 ), // input wire [0:0] + .probe31(u_ant_rf_ctrl.rf_rmgc_4 ), // input wire [0:0] + .probe32(u_ant_rf_ctrl.rf_rmgc_2 ), // input wire [0:0] + .probe33(u_ant_rf_ctrl.rf_rmgc_1 ), // input wire [0:0] + .probe34(u_ant_rf_ctrl.rf_enable ), // input wire [0:0] + .probe35(u_ant_rf_ctrl.rf_sc ), // input wire [0:0] + .probe36(u_ant_rf_ctrl.rf_sd ), // input wire [0:0] + .probe37(u_ant_rf_ctrl.rf_endsyn ), // input wire [0:0] + .probe38(u_ant_rf_ctrl.rf_sdout ), // input wire [0:0] + .probe39(u_ant_rf_ctrl.state_rfdata[1:0] ), // input wire [0:0] + .probe40(u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [0:0] + .probe41(u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [0:0] + .probe42(u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [0:0] + .probe43(u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [0:0] + .probe44(u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [0:0] + .probe45(u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [0:0] + .probe46(u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [0:0] + .probe47(u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [0:0] + .probe48(u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [0:0] + .probe49(u_ant_rf_ctrl.RF_RecvWord[95:0] ) // input wire [0:0] +); + +ila_AntCtrl u_ila_AntCtrl +( + .clk (clk_96m ), // input wire clk + .probe0 (u_ant_rf_ctrl.ant_clk ), // input wire [0:0] probe0 + .probe1 (u_ant_rf_ctrl.ant_en ), // input wire [0:0] probe1 + .probe2 (u_ant_rf_ctrl.ant_data ), // input wire [0:0] probe2 + .probe3 (u_ant_rf_ctrl.ant_tr ), // input wire [0:0] probe3 + .probe4 (u_ant_rf_ctrl.ant_dary ), // input wire [0:0] probe4 + .probe5 (u_ant_rf_ctrl.ant_dout ), // input wire [0:0] probe5 + .probe6 (u_ant_rf_ctrl.state_antdata[1:0] ), // input wire [0:0] probe5 + .probe7 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [0:0] probe5 + .probe8 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [0:0] probe5 + .probe9 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [0:0] probe5 + .probe10(u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [0:0] probe5 + .probe11(u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [0:0] probe5 + .probe12(u_ant_rf_ctrl.Ant_RecvWord[95:0] ) // input wire [0:0] probe5 +); + +vio_rf_rd u_vio_rf_rd ( + .clk (clk_96m ), // input wire clk + .probe_in0 (u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [7 : 0] probe_in0 + .probe_in1 (u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [7 : 0] probe_in1 + .probe_in2 (u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [7 : 0] probe_in2 + .probe_in3 (u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [7 : 0] probe_in3 + .probe_in4 (u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [3 : 0] probe_in4 + .probe_in5 (u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [3 : 0] probe_in5 + .probe_in6 (u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [3 : 0] probe_in6 + .probe_in7 (u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [3 : 0] probe_in7 + .probe_in8 (u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [31 : 0] probe_in8 + .probe_in9 (u_ant_rf_ctrl.RF_RecvWord_last ) // input wire [95 : 0] probe_in9 +); + +// vio_ant_rd u_vio_ant_rd ( +// .clk (clk_96m ), // input wire clk +// .probe_in0 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [7 : 0] probe_in0 +// .probe_in1 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [7 : 0] probe_in1 +// .probe_in2 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [7 : 0] probe_in2 +// .probe_in3 (u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [7 : 0] probe_in3 +// .probe_in4 (u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [31 : 0] probe_in4 +// .probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [127 : 0] probe_in5 +// ); + +ila_2x12x1024 u_ila_tx +( + .clk (sys_clk ), // input wire clk + .probe0 (tx_ch1_i ), // input wire [11:0] probe0 + .probe1 (tx_ch1_q ) // input wire [11:0] probe1 +); + +ila_8x12_2x30_131072 u_ila_rx +( + .clk (sys_clk ), // input wire clk + .probe0 (u_rx_pre_process.rx_comp_ch1_i ), // input wire [11:0] probe0 + .probe1 (u_rx_pre_process.rx_comp_ch1_q ), // input wire [11:0] probe1 + .probe2 (u_rx_pre_process.rx_comp_ch2_i ), // input wire [11:0] probe2 + .probe3 (u_rx_pre_process.rx_comp_ch2_q ), // input wire [11:0] probe3 + .probe4 (u_rx_pre_process.rx_comp_ch3_i ), // input wire [11:0] probe4 + .probe5 (u_rx_pre_process.rx_comp_ch3_q ), // input wire [11:0] probe5 + .probe6 (u_rx_pre_process.rx_comp_ch4_i ), // input wire [11:0] probe6 + .probe7 (u_rx_pre_process.rx_comp_ch4_q ), // input wire [11:0] probe7 + .probe8 (rx_data_i ), // input wire [29:0] probe8 + .probe9 (rx_data_q ) // input wire [29:0] probe9 +); + +ila_cal u_ila_cal +( + .clk (sys_clk ), // input wire clk + .probe0 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_start_d2 ), // input wire [0:0] probe0 + .probe1 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_done ), // input wire [0:0] probe1 + .probe2 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_start_d2 ), // input wire [0:0] probe2 + .probe3 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_done ), // input wire [0:0] probe3 + .probe4 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_cal_result ), // input wire [0:0] probe4 + .probe5 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_recal_d2 ), // input wire [0:0] probe5 + .probe6 (u_rx_pre_process.u_ad9361_phase_cal.curr_state ), // input wire [1:0] probe6 + .probe7 (rx_ch2_i ), // input wire [11:0] probe7 + .probe8 (rx_ch2_q ), // input wire [11:0] probe8 + .probe9 (rx_ch4_i ), // input wire [11:0] probe9 + .probe10(rx_ch4_q ), // input wire [11:0] probe10 + .probe11(u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe11 + .probe12(u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe12 + .probe13(u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe13 + .probe14(u_rx_pre_process.rx_cal_ch4_q ) // input wire [11:0] probe14 +); + +ila_rx_pre_sys u_ila_rx_pre_sys +( + .clk (sys_clk ), // input wire clk + .probe0 (u_rx_pre_process.u_null_ctrl.hop_flag_in ), // input wire [0:0] probe0 + .probe1 (u_rx_pre_process.stream_fifo_rst ), // input wire [0:0] probe1 + .probe2 (u_rx_pre_process.u_accor_mat_stream.fifo_wr_en ), // input wire [0:0] probe2 + .probe3 (u_rx_pre_process.u_accor_mat_stream.fifo_din ), // input wire [31:0] probe3 + .probe4 (u_rx_pre_process.u_accor_mat_stream.fifo_full ), // input wire [0:0] probe4 + .probe5 (u_rx_pre_process.u_weight_vec_formatting.fifo_rd_en ), // input wire [0:0] probe5 + .probe6 (u_rx_pre_process.u_weight_vec_formatting.fifo_dout ), // input wire [15:0] probe6 + .probe7 (u_rx_pre_process.u_weight_vec_formatting.fifo_empty ), // input wire [0:0] probe7 + .probe8 (u_rx_pre_process.u_weight_vec_formatting.fifo_rd_num ) // input wire [3:0] probe8 +); + +ila_rx_pre_ant u_ila_rx_pre_ant +( + .clk (clk_96m ), // input wire clk + .probe0 (u_rx_pre_process.u_null_ctrl.hop_flag_in ), // input wire [0:0] probe0 + .probe1 (accor_stream_valid ), // input wire [0:0] probe1 + .probe2 (accor_stream_data ), // input wire [0:0] probe2 + .probe3 (weight_stream_data ), // input wire [0:0] probe3 + .probe4 (u_rx_pre_process.weight_fifo_rst ), // input wire [0:0] probe4 + .probe5 (u_rx_pre_process.u_accor_mat_stream.fifo_rd_en ), // input wire [0:0] probe5 + .probe6 (u_rx_pre_process.u_accor_mat_stream.fifo_dout ), // input wire [31:0] probe6 + .probe7 (u_rx_pre_process.u_accor_mat_stream.fifo_empty ), // input wire [0:0] probe7 + .probe8 (u_rx_pre_process.u_accor_mat_stream.fifo_rd_num ), // input wire [4:0] probe8 + .probe9 (u_rx_pre_process.u_weight_vec_formatting.fifo_wr_en), // input wire [0:0] probe9 + .probe10(u_rx_pre_process.u_weight_vec_formatting.fifo_din ), // input wire [15:0] probe10 + .probe11(u_rx_pre_process.u_weight_vec_formatting.fifo_full ) // input wire [0:0] probe11 +); + +vio_manual_ctrl u_vio_manual_ctrl +( + .clk (sys_clk ), // input wire clk + .probe_out0 (waveform_sel[1:0] ), // output wire [1 : 0] probe_out0 + .probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1 + .probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2 + .probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3 + .probe_out4 (bb_rshift[3:0] ), // output wire [3 : 0] probe_out4 + .probe_out5 (rx_test_en ) // output wire [0 : 0] probe_out5 +); + +vio_phase_comp u_vio_phase_comp +( + .clk (sys_clk ), // input wire clk + .probe_in0 (var_cal_busy ), // output wire [0 : 0] probe_in0 + .probe_in1 (var ), // output wire [31 : 0] probe_in1 + .probe_in2 (var_ch1 ), // output wire [31 : 0] probe_in2 + .probe_in3 (var_ch2 ), // output wire [31 : 0] probe_in3 + .probe_in4 (var_ch3 ), // output wire [31 : 0] probe_in4 + .probe_in5 (var_ch4 ), // output wire [31 : 0] probe_in5 + .probe_out0 (phase_ch1 ), // output wire [15 : 0] probe_out0 + .probe_out1 (phase_ch2 ), // output wire [15 : 0] probe_out1 + .probe_out2 (phase_ch3 ), // output wire [15 : 0] probe_out2 + .probe_out3 (phase_ch4 ), // output wire [15 : 0] probe_out3 + .probe_out4 (var_cal_start ), // output wire [0 : 0] probe_out4 + .probe_out5 (var_cal_auto_en), // output wire [0 : 0] probe_out5 + .probe_out6 (hop_trigger_en ), // output wire [0 : 0] probe_out6 + .probe_out7 (hop_trigger ), // output wire [0 : 0] probe_out7 + .probe_out8 (lcmv_en ) // output wire [0 : 0] probe_out8 +); + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/trunc_32bit_to_12bit.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/trunc_32bit_to_12bit.v new file mode 100644 index 0000000..797642f --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/trunc_32bit_to_12bit.v @@ -0,0 +1,515 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/03/01 10:44:50 +// Design Name: +// Module Name: trunc_32bit_to_12bit +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module trunc_32bit_to_12bit( + input clk, + input rst, + input [31:0] trunc_32bit_in, + input [4:0] vio_trunc, + + output reg [11:0] trunc_12bit_out = 12'd0, + output reg trunc_overflow = 1'd0 + ); + + always @ (posedge clk) begin + if(rst) begin + trunc_12bit_out[11:0] <= 12'd0; + trunc_overflow <= 1'd0; + end else begin + case(vio_trunc[4:0]) + 5'd0:begin + if(trunc_32bit_in[31:31] == 1'd1 || trunc_32bit_in[31:31] == 1'd0) begin + if(trunc_32bit_in[31:31] == 1'd0 &&trunc_32bit_in[19] == 1'd1 && trunc_32bit_in[31:20] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[31:20] + 12'd1; + end + else begin + if(trunc_32bit_in[31:31] == 1'd1 && trunc_32bit_in[19:0] > 20'd524288) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[31:20] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[31:20]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd1:begin + if(trunc_32bit_in[31:30] == 2'd3 || trunc_32bit_in[31:30] == 2'd0) begin + if(trunc_32bit_in[31:30] == 2'd0 &&trunc_32bit_in[18] == 1'd1 && trunc_32bit_in[30:19] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[30:19] + 12'd1; + end + else begin + if(trunc_32bit_in[31:30] == 2'd3 && trunc_32bit_in[18:0] > 19'd262144) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[30:19] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[30:19]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd2:begin + if(trunc_32bit_in[31:29] == 3'd7 || trunc_32bit_in[31:29] == 3'd0) begin + if(trunc_32bit_in[31:29] == 3'd0 &&trunc_32bit_in[17] == 1'd1 && trunc_32bit_in[29:18] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[29:18] + 12'd1; + end + else begin + if(trunc_32bit_in[31:29] == 3'd7 && trunc_32bit_in[17:0] > 18'd131072) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[29:18] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[29:18]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd3:begin + if(trunc_32bit_in[31:28] == 4'd15 || trunc_32bit_in[31:28] == 4'd0) begin + if(trunc_32bit_in[31:28] == 4'd0 &&trunc_32bit_in[16] == 1'd1 && trunc_32bit_in[28:17] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[28:17] + 12'd1; + end + else begin + if(trunc_32bit_in[31:28] == 4'd15 && trunc_32bit_in[16:0] > 17'd65536) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[28:17] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[28:17]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd4:begin + if(trunc_32bit_in[31:27] == 5'd31 || trunc_32bit_in[31:27] == 5'd0) begin + if(trunc_32bit_in[31:27] == 5'd0 &&trunc_32bit_in[15] == 1'd1 && trunc_32bit_in[27:16] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[27:16] + 12'd1; + end + else begin + if(trunc_32bit_in[31:27] == 5'd31 && trunc_32bit_in[15:0] > 16'd32768) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[27:16] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[27:16]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd5:begin + if(trunc_32bit_in[31:26] == 6'd63 || trunc_32bit_in[31:26] == 6'd0) begin + if(trunc_32bit_in[31:26] == 6'd0 &&trunc_32bit_in[14] == 1'd1 && trunc_32bit_in[26:15] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[26:15] + 12'd1; + end + else begin + if(trunc_32bit_in[31:26] == 6'd63 && trunc_32bit_in[14:0] > 15'd16384) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[26:15] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[26:15]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd6:begin + if(trunc_32bit_in[31:25] == 7'd127 || trunc_32bit_in[31:25] == 7'd0) begin + if(trunc_32bit_in[31:25] == 7'd0 &&trunc_32bit_in[13] == 1'd1 && trunc_32bit_in[25:14] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[25:14] + 12'd1; + end + else begin + if(trunc_32bit_in[31:25] == 7'd127 && trunc_32bit_in[13:0] > 14'd8192) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[25:14] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[25:14]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd7:begin + if(trunc_32bit_in[31:24] == 8'd255 || trunc_32bit_in[31:24] == 8'd0) begin + if(trunc_32bit_in[31:24] == 8'd0 &&trunc_32bit_in[12] == 1'd1 && trunc_32bit_in[24:13] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[24:13] + 12'd1; + end + else begin + if(trunc_32bit_in[31:24] == 8'd255 && trunc_32bit_in[12:0] > 13'd4096) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[24:13] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[24:13]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd8:begin + if(trunc_32bit_in[31:23] == 9'd511 || trunc_32bit_in[31:23] == 9'd0) begin + if(trunc_32bit_in[31:23] == 9'd0 &&trunc_32bit_in[11] == 1'd1 && trunc_32bit_in[23:12] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[23:12] + 12'd1; + end + else begin + if(trunc_32bit_in[31:23] == 9'd511 && trunc_32bit_in[11:0] > 12'd2048) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[23:12] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[23:12]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd9:begin + if(trunc_32bit_in[31:22] == 10'd1023 || trunc_32bit_in[31:22] == 10'd0) begin + if(trunc_32bit_in[31:22] == 10'd0 &&trunc_32bit_in[10] == 1'd1 && trunc_32bit_in[22:11] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[22:11] + 12'd1; + end + else begin + if(trunc_32bit_in[31:22] == 10'd1023 && trunc_32bit_in[10:0] > 11'd1024) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[22:11] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[22:11]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd10:begin + if(trunc_32bit_in[31:21] == 11'd2047 || trunc_32bit_in[31:21] == 11'd0) begin + if(trunc_32bit_in[31:21] == 11'd0 &&trunc_32bit_in[9] == 1'd1 && trunc_32bit_in[21:10] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[21:10] + 12'd1; + end + else begin + if(trunc_32bit_in[31:21] == 11'd2047 && trunc_32bit_in[9:0] > 10'd512) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[21:10] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[21:10]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd11:begin + if(trunc_32bit_in[31:20] == 12'd4095 || trunc_32bit_in[31:20] == 12'd0) begin + if(trunc_32bit_in[31:20] == 12'd0 &&trunc_32bit_in[8] == 1'd1 && trunc_32bit_in[20:9] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[20:9] + 12'd1; + end + else begin + if(trunc_32bit_in[31:20] == 12'd4095 && trunc_32bit_in[8:0] > 9'd256) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[20:9] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[20:9]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd12:begin + if(trunc_32bit_in[31:19] == 13'd8191 || trunc_32bit_in[31:19] == 13'd0) begin + if(trunc_32bit_in[31:19] == 13'd0 &&trunc_32bit_in[7] == 1'd1 && trunc_32bit_in[19:8] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[19:8] + 12'd1; + end + else begin + if(trunc_32bit_in[31:19] == 13'd8191 && trunc_32bit_in[7:0] > 8'd128) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[19:8] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[19:8]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd13:begin + if(trunc_32bit_in[31:18] == 14'd16383 || trunc_32bit_in[31:18] == 14'd0) begin + if(trunc_32bit_in[31:18] == 14'd0 &&trunc_32bit_in[6] == 1'd1 && trunc_32bit_in[18:7] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[18:7] + 12'd1; + end + else begin + if(trunc_32bit_in[31:18] == 14'd16383 && trunc_32bit_in[6:0] > 7'd64) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[18:7] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[18:7]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd14:begin + if(trunc_32bit_in[31:17] == 15'd32767 || trunc_32bit_in[31:17] == 15'd0) begin + if(trunc_32bit_in[31:17] == 15'd0 &&trunc_32bit_in[5] == 1'd1 && trunc_32bit_in[17:6] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[17:6] + 12'd1; + end + else begin + if(trunc_32bit_in[31:17] == 15'd32767 && trunc_32bit_in[5:0] > 6'd32) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[17:6] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[17:6]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd15:begin + if(trunc_32bit_in[31:16] == 16'd65535 || trunc_32bit_in[31:16] == 16'd0) begin + if(trunc_32bit_in[31:16] == 16'd0 &&trunc_32bit_in[4] == 1'd1 && trunc_32bit_in[16:5] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[16:5] + 12'd1; + end + else begin + if(trunc_32bit_in[31:16] == 16'd65535 && trunc_32bit_in[4:0] > 5'd16) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[16:5] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[16:5]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd16:begin + if(trunc_32bit_in[31:15] == 17'd131071 || trunc_32bit_in[31:15] == 17'd0) begin + if(trunc_32bit_in[31:15] == 17'd0 &&trunc_32bit_in[3] == 1'd1 && trunc_32bit_in[15:4] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[15:4] + 12'd1; + end + else begin + if(trunc_32bit_in[31:15] == 17'd131071 && trunc_32bit_in[3:0] > 4'd8) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[15:4] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[15:4]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd17:begin + if(trunc_32bit_in[31:14] == 18'd262143 || trunc_32bit_in[31:14] == 18'd0) begin + if(trunc_32bit_in[31:14] == 18'd0 &&trunc_32bit_in[2] == 1'd1 && trunc_32bit_in[14:3] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[14:3] + 12'd1; + end + else begin + if(trunc_32bit_in[31:14] == 18'd262143 && trunc_32bit_in[2:0] > 3'd4) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[14:3] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[14:3]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd18:begin + if(trunc_32bit_in[31:13] == 19'd524287 || trunc_32bit_in[31:13] == 19'd0) begin + if(trunc_32bit_in[31:13] == 19'd0 &&trunc_32bit_in[1] == 1'd1 && trunc_32bit_in[13:2] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[13:2] + 12'd1; + end + else begin + if(trunc_32bit_in[31:13] == 19'd524287 && trunc_32bit_in[1:0] > 2'd2) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[13:2] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[13:2]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd19:begin + if(trunc_32bit_in[31:12] == 20'd1048575 || trunc_32bit_in[31:12] == 20'd0) begin + if(trunc_32bit_in[31:12] == 20'd0 &&trunc_32bit_in[0] == 1'd1 && trunc_32bit_in[12:1] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[12:1] + 12'd1; + end + else begin + if(trunc_32bit_in[31:12] == 20'd1048575 && trunc_32bit_in[0:0] > 1'd1) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[12:1] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[12:1]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + default:begin + if(trunc_32bit_in[31:11] == 21'd2097151 || trunc_32bit_in[31:11] == 21'd0) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[11:0]; + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + endcase + end + end +endmodule \ No newline at end of file diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/tx_pre_process.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/tx_pre_process.v new file mode 100644 index 0000000..7b0b7e1 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/tx_pre_process.v @@ -0,0 +1,138 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2023/02/25 15:20:22 +// Design Name: +// Module Name: tx_pre_process +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tx_pre_process +#( + parameter ADC_DATA_WIDTH = 12, + parameter PRBS = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)] + parameter PRBS_LEN = 128, // length of pseudorandom bit sequence + parameter INTERP_FACTOR = 8, // interpolation factor, max inter-channel delay ranges in [-INTERP_FACTOR+1,INTERP_FACTOR-1] + parameter CAL_MOD_FINE = 1 +) +( + // clock & reset + input clk , + input rst , + // input data + input [ADC_DATA_WIDTH-1:0] tx_data_ch1_i , + input [ADC_DATA_WIDTH-1:0] tx_data_ch1_q , + input [ADC_DATA_WIDTH-1:0] tx_data_ch2_i , + input [ADC_DATA_WIDTH-1:0] tx_data_ch2_q , + // ad9361 calibration interface + input ad9361_tx_switch , + // + input [$clog2(ADC_DATA_WIDTH)-1:0] bb_rshift, + // output data + output [ADC_DATA_WIDTH-1:0] tx_ch1_i , + output [ADC_DATA_WIDTH-1:0] tx_ch1_q , + output [ADC_DATA_WIDTH-1:0] tx_ch2_i , + output [ADC_DATA_WIDTH-1:0] tx_ch2_q +); + +integer i; + +// square shaped bpsk signal +reg [$clog2(PRBS_LEN*INTERP_FACTOR)-1 : 0] chip_interp_cnt = 'b0; +reg signed [ADC_DATA_WIDTH-1:0] tx_pn_i = 'b0; +reg signed [ADC_DATA_WIDTH-1:0] tx_pn_q = 'b0; + +if (CAL_MOD_FINE == 1) begin + +always @(posedge clk) begin + if (rst) begin + chip_interp_cnt <= 'b0; + end + else begin + chip_interp_cnt <= chip_interp_cnt + 1'b1; + end +end + +always @(posedge clk) begin + if (rst) begin + tx_pn_i <= 'b0; + tx_pn_q <= 'b0; + end + else begin + tx_pn_i <= PRBS[chip_interp_cnt[$clog2(PRBS_LEN*INTERP_FACTOR)-1 -: $clog2(PRBS_LEN)]] ? {1'b0,{(ADC_DATA_WIDTH-1){1'b1}}} : {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1}; // (1 or 0) ? 4'b0111 : 4'b1001 + tx_pn_q <= PRBS[chip_interp_cnt[$clog2(PRBS_LEN*INTERP_FACTOR)-1 -: $clog2(PRBS_LEN)]] ? {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1} : {1'b0,{(ADC_DATA_WIDTH-1){1'b1}}}; // (1 or 0) ? 4'b1001 : 4'b0111 + end +end + +end // if (CAL_MOD_FINE == 1) + +// buffer input control signals (clock domain crossing from ps to pl clock domain) +reg ad9361_tx_switch_d1 = 'b0; +reg ad9361_tx_switch_d2 = 'b0; + +wire signed [ADC_DATA_WIDTH-1:0] tx_dc_i = {1'b0,{(ADC_DATA_WIDTH-2){1'b1}},1'b1}; +wire signed [ADC_DATA_WIDTH-1:0] tx_dc_q = {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1}; + +always @(posedge clk) begin + ad9361_tx_switch_d1 <= ad9361_tx_switch; + ad9361_tx_switch_d2 <= ad9361_tx_switch_d1; +end + +reg [ADC_DATA_WIDTH-1 : 0] tx_ch1_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] tx_ch1_q_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] tx_ch2_i_buf = 'b0; +reg [ADC_DATA_WIDTH-1 : 0] tx_ch2_q_buf = 'b0; + +assign tx_ch1_i = tx_ch1_i_buf; +assign tx_ch1_q = tx_ch1_q_buf; +assign tx_ch2_i = tx_ch2_i_buf; +assign tx_ch2_q = tx_ch2_q_buf; + +always @(posedge clk) begin + if (rst) begin + tx_ch1_i_buf <= 'b0; + tx_ch1_q_buf <= 'b0; + tx_ch2_i_buf <= 'b0; + tx_ch2_q_buf <= 'b0; + end + else if (ad9361_tx_switch_d2) begin +if (CAL_MOD_FINE == 1) begin + tx_ch1_i_buf <= tx_pn_i >>> bb_rshift; + tx_ch1_q_buf <= tx_pn_q >>> bb_rshift; + tx_ch2_i_buf <= tx_pn_i >>> bb_rshift; + tx_ch2_q_buf <= tx_pn_q >>> bb_rshift; +end // CAL_MOD_FINE == 1 +else begin + tx_ch1_i_buf <= tx_dc_i >>> bb_rshift; + tx_ch1_q_buf <= tx_dc_q >>> bb_rshift; + tx_ch2_i_buf <= tx_dc_i >>> bb_rshift; + tx_ch2_q_buf <= tx_dc_q >>> bb_rshift; +end // CAL_MOD_FINE != 1 + end + else begin + tx_ch1_i_buf <= tx_data_ch1_i; + tx_ch1_q_buf <= tx_data_ch1_q; + tx_ch2_i_buf <= tx_data_ch2_i; + tx_ch2_q_buf <= tx_data_ch2_q; + end +end + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/tx_qpsk.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/tx_qpsk.v new file mode 100644 index 0000000..9ab3a0a --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/tx_qpsk.v @@ -0,0 +1,412 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/03/23 20:17:56 +// Last Modified Date: 2023/03/10 15:41 +// Design Name: +// Module Name: tx_qpsk +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// 20230228-1541 - 修改ä¸æ‰«é¢‘ã€æ— åŸºå¸¦é¢‘åæ—¶ [baseband_i/q] çš„æ•°æ®è¾“出，原æ¥ä»Ž +// 乘法器引出，会导致频率为 0 时输出数æ®é”™è¯¯ï¼ŒçŽ°åœ¨ç›´æŽ¥ä»ŽåŸºå¸¦æ•°æ®å¼•å‡ºã€‚ +// 20230310-1542 - 增加输入å‚数，å‘é€æ•°æ®æ›´æ”¹ä¸ºç›´æŽ¥ç”±å‚数输入，å‘é€æ–¹æ³¢æ”¹ä¸º 8 +// å€è¿‡é‡‡æ ·ï¼Œå‘é€åŒéŸ³ä¿¡å·ä¸­ 1MHz ä¿¡å·çš„频率控制字å¯ä»¥æ ¹æ®å‚数中的时钟频率计 +// 算得出。 +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tx_qpsk +#( + parameter DATA_WIDTH = 12, // need to be <= 16 + parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)] + parameter BIT_DATA_LEN = 128, + parameter SQUARE_INTERP = 8, + parameter CLK_FREQ = 245760000 // in Hertz +) +( + input clk , + input rst , + output [DATA_WIDTH-1:0] tx_data_i , + output [DATA_WIDTH-1:0] tx_data_q , + // debug ports + input [ 1:0] waveform_sel , + input sweep_on , + input [31:0] freq_set , + input [ 1:0] iq_sel , + input [ 3:0] bb_rshift +); + +localparam RCOS_INTERP = 64; +localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP; +localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ; + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////////// Data Counter ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// symbol & interpolation counter +reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0; + +always @(posedge clk) begin + if (rst) begin + cnt <= 'b0; + end + else begin + cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1; + end +end + +//////////////////////////////////////////////////////////////////////////////// +////////////////////// Root-Rasied Cosine Shaping Filter /////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// address +reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0; +reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1; + +always @(posedge clk) begin + if (rst) begin + hrc_data_addr_i <= 'b0; + hrc_data_addr_q <= 'b1; + end + else begin + hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0}; + hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1}; + end +end + +// bit data +reg hrc_data_i = 'b0; +reg hrc_data_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + hrc_data_i <= 'b0; + hrc_data_q <= 'b0; + end + else begin + hrc_data_i <= BIT_DATA[hrc_data_addr_i]; + hrc_data_q <= BIT_DATA[hrc_data_addr_q]; + end +end + +// polarization +wire [ 7:0] hrc_data_polar_i; +wire [ 7:0] hrc_data_polar_q; + +assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1}; +assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1}; + +// root raised cosine shaping-filter +wire [23:0] hrc_wave_i; +wire [23:0] hrc_wave_q; + +hrc_64_12_025 u_hrc_i ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata +); + +hrc_64_12_025 u_hrc_q ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata +); + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Square Shaping Filter ///////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// address +reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0; + +always @(posedge clk) begin + if (rst) begin + hsq_data_addr <= 'b0; + end + else + hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]}; +end + +// bit data +reg hsq_data = 'b0; + +always @(posedge clk) begin + if (rst) begin + hsq_data <= 'b0; + end + else begin + hsq_data <= BIT_DATA[hsq_data_addr]; + end +end + +// square shaping-filter +reg [17:0] hsq_wave_i ='b0; +reg [17:0] hsq_wave_q ='b0; + +always @(posedge clk) begin + if (rst) begin + hsq_wave_i <= 'b0; + hsq_wave_q <= 'b0; + end + else begin + hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001; + hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111; + end +end + + +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// Two Tone Siganl //////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// cosine wave with freq of 1 MHz +wire signed [7:0] cos_1m; +wire signed [7:0] sin_1m; + +dds_32b_8b u_dds_1m +( + .aclk (clk ), // input wire aclk + .s_axis_config_tvalid (1'b1 ), // input wire s_axis_config_tvalid + .s_axis_config_tdata (FREQ_WORD_1M[31:0] ), // input wire [31 : 0] s_axis_config_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata ({sin_1m,cos_1m} ) // output wire [15 : 0] m_axis_data_tdata +); + +// two-tone signal +reg signed [16:0] two_tone_wave_i = 'b0; +reg signed [16:0] two_tone_wave_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + two_tone_wave_i <= 'b0; + two_tone_wave_q <= 'b0; + end + else begin + two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0}; + two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0}; + end +end + + +//////////////////////////////////////////////////////////////////////////////// +///////////////////// Waveform Selection & Hopping Control ///////////////////// +//////////////////////////////////////////////////////////////////////////////// +// baseband signal select +reg [17:0] baseband_sel_i = 'b0; +reg [17:0] baseband_sel_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + baseband_sel_i <= 'b0; + baseband_sel_q <= 'b0; + end + else begin + case (waveform_sel[1:0]) + 2'd0: begin + baseband_sel_i <= {hrc_wave_i[16:0],1'b0}; + baseband_sel_q <= {hrc_wave_q[16:0],1'b0}; + end + 2'd1: begin + baseband_sel_i <= hsq_wave_i[17:0]; + baseband_sel_q <= hsq_wave_q[17:0]; + end + 2'd2: begin + baseband_sel_i <= 18'b01_1111_1111_1111_1111; + baseband_sel_q <= 18'b0; + end + 2'd3: begin + baseband_sel_i <= {two_tone_wave_i[16:0],1'b0}; + baseband_sel_q <= {two_tone_wave_q[16:0],1'b0}; + end + default: begin + baseband_sel_i <= {hrc_wave_i[16:0],1'b0}; + baseband_sel_q <= {hrc_wave_q[16:0],1'b0}; + end + endcase + end +end + +// hopping control, 3750hop/s +reg [23:0] sweep_rom_addr = 'b0; +wire [31:0] freq_sweep; + +always @(posedge clk) begin + if (rst) begin + sweep_rom_addr <= 'b0; + end + else if (sweep_on) begin + sweep_rom_addr <= sweep_rom_addr + 24'b1; + end + else begin + sweep_rom_addr <= 'b0; + end +end + +hop_rom u_sweep_rom +( + .clka (clk ), // input wire clka + .addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra + .douta (freq_sweep ) // output wire [31 : 0] douta +); + +// choose the actual frequency word +reg [31:0] freq_word = 'b0; + +always @(posedge clk) begin + if (rst) begin + freq_word <= 'b0; + end + else if (sweep_on) begin + // frequency sweep + freq_word <= freq_sweep; + end + else begin + // normal operation + freq_word <= freq_set; + end +end + +// baseband frequency shift carrier generation +wire [ 7:0] cos_dds; +wire [ 7:0] sin_dds; +reg [ 7:0] cos = 'b0; +reg [ 7:0] sin = 'b0; + +dds_32b_8b u_dds_bb_shift ( + .aclk (clk ), // input wire aclk + .s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid + .s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata +); + +always @(posedge clk) begin + if (rst) begin + cos <= 'b0; + sin <= 'b0; + end + else if (freq_word == 'b0) begin + // to make sure the carriers stay at the right position when freq = 0 + cos <= 8'b0111_1111; + sin <= 8'b0111_1111; + end + else begin + cos <= cos_dds; + sin <= sin_dds; + end +end + +// baseband frequency shift modulation +wire [47:0] mod_cmpy_a; +wire [15:0] mod_cmpy_b; +wire [63:0] mod_cmpy_out; + +wire [26:0] baseband_mult_i; +wire [26:0] baseband_mult_q; + +assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i}; +assign mod_cmpy_b = {-sin,cos}; + +assign baseband_mult_i = mod_cmpy_out[58:32]; +assign baseband_mult_q = mod_cmpy_out[26: 0]; + +cmpy_18x8 u_cmpy_18x8 +( + .aclk (clk ), // input wire aclk + .s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid + .s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata + .s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid + .s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata + .m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata +); + +// truncate to 16-bit +reg signed [15:0] baseband_i = 'b0; +reg signed [15:0] baseband_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + baseband_i <= 'b0; + baseband_q <= 'b0; + end + else begin + case (waveform_sel[1:0]) + 2'd0: begin + // scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625 + baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]}); + baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]}); + end + 2'd1: begin + baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]}); + baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]}); + end + 2'd2: begin + baseband_i <= baseband_mult_i[24:9]; + baseband_q <= baseband_mult_q[24:9]; + end + 2'd3: begin + baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9]; + baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9]; + end + default: begin + // scale rasied-cosine-shaped bpsk signal by 1.125 + baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]}; + baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]}; + end + endcase + end +end + +// iq selection & baseband right shift +reg signed [15:0] baseband_data_i = 'b0; +reg signed [15:0] baseband_data_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + baseband_data_i <= 'b0; + baseband_data_q <= 'b0; + end + else begin + // inphase selection + if (iq_sel[1]) begin + baseband_data_i <= baseband_i >>> bb_rshift; + end + else begin + baseband_data_i <= 'b0; + end + // quadrature selection + if (iq_sel[0]) begin + baseband_data_q <= baseband_q >>> bb_rshift; + end + else begin + baseband_data_q <= 'b0; + end + end +end + +// output data to ports +assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH]; +assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH]; + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/var_cal.v b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/var_cal.v new file mode 100644 index 0000000..0b67fa4 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/var_cal.v @@ -0,0 +1,258 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 06/11/2023 02:41:47 PM +// Design Name: +// Module Name: var_cal +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// 20230730-1427 - 修改输入ä½å®½å°äºŽä¹˜æ³•å™¨ä½å®½æ—¶çš„处ç†ï¼Œç”±è¡¥é›¶å˜ä¸ºç¬¦å·ä½æ‰©å±•ï¼› +// 修改；修改累加和输出截ä½æ–¹å¼ï¼Œä¾æ‰˜åŽŸå§‹æ•°æ®ä½å®½è¿›è¡Œå¤„ç†ã€‚ +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module var_cal +#( + parameter ACCUM_NUM = 16384, + parameter DATA_I_WIDTH = 30, + parameter DATA_O_WIDTH = 32, + parameter CMPY_I_WIDTH = 18 +) +( + input clk , + input rst , + + input cal_start , + input cal_auto_en , + output cal_busy , + + input din_valid , + input [DATA_I_WIDTH-1 : 0] din_real , + input [DATA_I_WIDTH-1 : 0] din_imag , + + output var_valid , + output [DATA_O_WIDTH-1 : 0] var +); + +integer i; + +localparam CMPY_P_WIDTH = 2*CMPY_I_WIDTH+1; +localparam AXIS_CMPY_I_WIDTH = 8*((CMPY_I_WIDTH-1)/8+1) ; // axis data width of input real/image data +localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_WIDTH-1)/8+1); // axis data width of cmpy output real/image data +localparam CMPY_P_VALID_WIDTH = (DATA_I_WIDTH > CMPY_I_WIDTH) ? 2*CMPY_I_WIDTH : 2*DATA_I_WIDTH; + + +localparam ACCUM_WIDTH = CMPY_P_VALID_WIDTH + $clog2(ACCUM_NUM); + +// status control +reg cal_start_auto = 'b0; +reg cal_start_d1 = 'b0; +reg cal_start_d2 = 'b0; +reg cal_busy_buf = 'b0; +reg [$clog2(ACCUM_NUM)-1 : 0] cnt_accum = 'b0; +reg last_data = 'b0; +reg [6:0] last_data_d = 'b0; // 1 for register input, 6 for cmpy, 1 for register output + +assign cal_busy = cal_busy_buf; +assign var_valid = last_data_d[6]; + +always @(posedge clk) begin + if (rst) begin + cal_start_auto <= 'b0; + end + else begin + if (cal_auto_en) begin + if (~cal_busy_buf) begin + cal_start_auto <= ~cal_start_auto; + end + else begin + cal_start_auto <= cal_start_auto; + end + end + else begin + cal_start_auto <= 'b0; + end + end +end + +always @(posedge clk) begin + cal_start_d1 <= cal_auto_en ? cal_start_auto : cal_start; + cal_start_d2 <= cal_start_d1; +end + +always @(posedge clk) begin + if (rst) begin + cal_busy_buf <= 'b0; + end + else begin + if ((cal_start_d1 ^ cal_start_d2) && din_valid) begin + cal_busy_buf <= 1'b1; + end + else if (cnt_accum == ACCUM_NUM-1) begin + cal_busy_buf <= 'b0; + end + else begin + cal_busy_buf <= cal_busy_buf; + end + end +end + +always @(posedge clk) begin + if (rst) begin + cnt_accum <= 'b0; + end + else begin + cnt_accum <= cal_busy ? (cnt_accum + 1'b1) : 'b0; + end +end + +always @(posedge clk) begin + if (rst) begin + last_data <= 'b0; + end + else begin + last_data <= (cnt_accum == ACCUM_NUM-1) ? 1'b1 : 1'b0; + end +end + +always @(posedge clk) begin + if (rst) begin + last_data_d[6:0] <= 'b0; + end + else begin + last_data_d[6:0] <= {last_data_d[5:0],last_data}; + end +end + + +// cmpy +reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_real = 'b0; +reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_imag = 'b0; +reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_real = 'b0; +reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_imag = 'b0; +wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_real; +wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_imag; +wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_real; +wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_imag; + +if (CMPY_I_WIDTH > DATA_I_WIDTH) begin + // sign-bit extension to fit cmpy input data width + always @(posedge clk) begin + if (rst) begin + cmpy_a_real <= 'b0; + cmpy_a_imag <= 'b0; + cmpy_b_real <= 'b0; + cmpy_b_imag <= 'b0; + end + else begin + cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real}; + cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag}; + cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real}; + cmpy_b_imag <= (din_imag == {1'b1,{(DATA_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH+1){1'b0}},{(DATA_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag}; + end + end +end +else begin + // truncate msb + always @(posedge clk) begin + if (rst) begin + cmpy_a_real <= 'b0; + cmpy_a_imag <= 'b0; + cmpy_b_real <= 'b0; + cmpy_b_imag <= 'b0; + end + else begin + cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]}; + cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]}; + cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]}; + cmpy_b_imag <= (din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH] == {1'b1,{(CMPY_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH+1){1'b0}},{(CMPY_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]}; + end + end +end + +// truncate valid bits +assign cmpy_p_real = cmpy_p_raw_real[0 +: CMPY_P_VALID_WIDTH]; +assign cmpy_p_imag = cmpy_p_raw_imag[0 +: CMPY_P_VALID_WIDTH]; + + +wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_a; +wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_b; +wire [2*AXIS_CMPY_P_WIDTH-1:0] cmpy_p; +wire cmpy_p_vld; + +assign cmpy_a = {cmpy_a_imag,cmpy_a_real}; +assign cmpy_b = {cmpy_b_imag,cmpy_b_real}; +assign {cmpy_p_raw_imag,cmpy_p_raw_real} = cmpy_p; + +cmpy_18x18_mult u_cmpy_18x18 +( + .aclk (clk ), // input wire aclk + .s_axis_a_tvalid (cal_busy ), // input wire s_axis_a_tvalid + .s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata + .s_axis_b_tvalid (cal_busy ), // input wire s_axis_b_tvalid + .s_axis_b_tdata (cmpy_b ), // input wire [31 : 0] s_axis_b_tdata + .m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata +); + + +// accumulation +reg [ACCUM_WIDTH-1 : 0] accum = 'b0; +reg [DATA_O_WIDTH-1 : 0] var_buf = 'b0; + +assign var = var_buf; + +always @(posedge clk) begin + if (rst) begin + accum <= 'b0; + end + else begin + if (cmpy_p_vld) begin + accum <= accum + cmpy_p_real; + end + else begin + accum <= 'b0; + end + end +end + +if (DATA_O_WIDTH > ACCUM_WIDTH) begin + // sign-bit extension to fit output data width + always @(posedge clk) begin + if (rst) begin + var_buf <= 'b0; + end + else if (last_data_d[5]) begin + var_buf <= {{(DATA_O_WIDTH-ACCUM_WIDTH){accum[ACCUM_WIDTH-1]}},accum}; + end + end +end +else begin + // truncate msb + always @(posedge clk) begin + if (rst) begin + var_buf <= 'b0; + end + else if (last_data_d[5]) begin + var_buf <= accum[ACCUM_WIDTH-1 -: DATA_O_WIDTH]; + end + end +end + +endmodule diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/utils_1/imports/synth_1/system_top.dcp b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/utils_1/imports/synth_1/system_top.dcp new file mode 100644 index 0000000..f6e1939 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/utils_1/imports/synth_1/system_top.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:aa0dafa7f67db8118cf941e6a832097656b94ba621c2cca6487e1f42d6fdcf29 +size 1802716 diff --git a/dl814_k7_cal_coarse/dl814_k7_cal_coarse.xpr b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.xpr new file mode 100644 index 0000000..25e7931 --- /dev/null +++ b/dl814_k7_cal_coarse/dl814_k7_cal_coarse.xpr @@ -0,0 +1,2221 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/dl814_k7_cal_coarse/system_top.xsa b/dl814_k7_cal_coarse/system_top.xsa new file mode 100644 index 0000000..730c7c1 --- /dev/null +++ b/dl814_k7_cal_coarse/system_top.xsa @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:856f388e1c7ab289cc85078b76867b067db8aa1498361b659a3a034002c82c1e +size 2329281 diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/.gitignore b/dl814_k7_cal_coarse/vitis_classic_autobuild/.gitignore new file mode 100644 index 0000000..3ce08f3 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/.gitignore @@ -0,0 +1,35 @@ +# keep compiled libs +!*.a + +# Buid folder +build/ + +# Xilinx tools generated files +.metadata/ +.settings/ +.wsdata/ +.Xil/ +logs/ +Packages/ +*.log* + +# System generated files +# -- macOS +.DS_Store +.AppleDouble +.LSOverride +._* + +# -- Windows +Thumbs.db +ehthumbs.db +Desktop.ini + +# -- Linux +*~ + +# IDEs and editors' files +*.idea +*.vscode +*.sublime-workspace +*.sublime-project diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/Makefile b/dl814_k7_cal_coarse/vitis_classic_autobuild/Makefile new file mode 100644 index 0000000..e7b8a91 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/Makefile @@ -0,0 +1,8 @@ +include ../../scripts/generic_variables.mk + +PLATFORM := xilinx +CONFIG_FILE := $(PROJECT)/config.json +XILINX_VITIS_CLASSIC = y +SCRIPT_DIR = ../../scripts + +include ../../scripts/generic.mk \ No newline at end of file diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/autobuild.bat b/dl814_k7_cal_coarse/vitis_classic_autobuild/autobuild.bat new file mode 100644 index 0000000..cf85261 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/autobuild.bat @@ -0,0 +1,32 @@ +@echo off +set "platform=xilinx" +set "pltform_ver=2024.1" +set "work_dir=%~dp0build" +set "config=%~dp0config.json" +set "tools_dir=%~dp0..\..\scripts\platform\%platform%" + +REM Set up enviroment +call "%tools_dir%\setenv.bat" "%pltform_ver%" +if "%ERRORLEVEL%" neq "0" ( + echo Error: Failed to installize enviroment. + pause >nul + exit /b 1 +) + +REM Build project +call "%tools_dir%\build.bat" "%config%" "%work_dir%" +if "%ERRORLEVEL%" neq "0" ( + echo Error: Failed to build project. + pause >nul + exit /b 1 +) + +REM Lauch SDK +call "%tools_dir%\launch.bat" "%pltform_ver%" "%work_dir%" +if "%ERRORLEVEL%" neq "0" ( + echo Error: Failed to launch SDK. + pause >nul + exit /b 1 +) + +exit /b 0 \ No newline at end of file diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/config.json b/dl814_k7_cal_coarse/vitis_classic_autobuild/config.json new file mode 100644 index 0000000..7de20ff --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/config.json @@ -0,0 +1,18 @@ +{ + "project_name": "dl814_cal", + "version": "0.0.1", + "hw_design": "../system_top.xsa", + "hw_version": "dl814_cal-HW-0.0.1", + "apps": { + "app_dl814_k7_48m": { + "sources": ["source/"], + "target_cpu": "microblaze_ps", + "os": "standalone", + "language": "C", + "mem_layout" : { + "heap_size": "0x8000", + "stack_size": "0x4000" + } + } + } +} diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/api/gpio.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/api/gpio.c new file mode 100644 index 0000000..9742613 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/api/gpio.c @@ -0,0 +1,184 @@ +/***************************************************************************//** + * @file gpio.c + * @brief Implementation of the GPIO Interface + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2020(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#include +#include +#include "../../include/gpio.h" +#include "../../include/error.h" + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Obtain the GPIO decriptor. + * @param desc - The GPIO descriptor. + * @param param - GPIO Initialization parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get(struct gpio_desc **desc, + const struct gpio_init_param *param) +{ + if (!param) + return FAILURE; + + if ((param->platform_ops->gpio_ops_get(desc, param))) + return FAILURE; + + (*desc)->platform_ops = param->platform_ops; + + return SUCCESS; +} + +/** + * @brief Get the value of an optional GPIO. + * @param desc - The GPIO descriptor. + * @param param - GPIO Initialization parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get_optional(struct gpio_desc **desc, + const struct gpio_init_param *param) +{ + if (!param || (param->number == -1)) { + *desc = NULL; + return SUCCESS; + } + + if ((param->platform_ops->gpio_ops_get_optional(desc, param))) + return FAILURE; + + (*desc)->platform_ops = param->platform_ops; + + return SUCCESS; +} +/** + * @brief Free the resources allocated by gpio_get(). + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_remove(struct gpio_desc *desc) +{ + if (desc) + return desc->platform_ops->gpio_ops_remove(desc); + else + return SUCCESS; +} + +/** + * @brief Enable the input direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_direction_input(struct gpio_desc *desc) +{ + if (desc) + return desc->platform_ops->gpio_ops_direction_input(desc); + else + return SUCCESS; +} + +/** + * @brief Enable the output direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_direction_output(struct gpio_desc *desc, + uint8_t value) +{ + if (desc) + return desc->platform_ops-> + gpio_ops_direction_output(desc, value); + else + return SUCCESS; +} + +/** + * @brief Get the direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param direction - The direction. + * Example: GPIO_OUT + * GPIO_IN + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get_direction(struct gpio_desc *desc, + uint8_t *direction) +{ + if (desc) + return desc->platform_ops-> + gpio_ops_get_direction(desc, direction); + else + return SUCCESS; +} + +/** + * @brief Set the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_set_value(struct gpio_desc *desc, + uint8_t value) +{ + if (desc) + return desc->platform_ops->gpio_ops_set_value(desc, value); + else + return SUCCESS; +} + +/** + * @brief Get the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get_value(struct gpio_desc *desc, + uint8_t *value) +{ + if (desc) + return desc->platform_ops->gpio_ops_get_value(desc, value); + else + return SUCCESS; +} diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/api/irq.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/api/irq.c new file mode 100644 index 0000000..937c57f --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/api/irq.c @@ -0,0 +1,153 @@ +/***************************************************************************//** + * @file irq.c + * @brief Implementation of the IRQ Interface + * @author Andrei Porumb (andrei.porumb@analog.com) +******************************************************************************** + * Copyright 2021(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#include +#include +#include "../../include/irq.h" +#include "../../include/error.h" + +/** + * @brief Initialize the IRQ interrupts. + * @param desc - The IRQ descriptor. + * @param param - The structure that contains the IRQ parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_ctrl_init(struct irq_ctrl_desc **desc, + const struct irq_init_param *param) +{ + if (!param) + return FAILURE; + + if ((param->platform_ops->init(desc, param))) + return FAILURE; + + (*desc)->platform_ops = param->platform_ops; + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by irq_ctrl_init(). + * @param desc - The SPI descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc) +{ + return desc->platform_ops->remove(desc); +} + +/** + * @brief Register a callback to handle the irq events. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @param callback_desc - Callback descriptor + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id, + struct callback_desc *callback_desc) +{ + return desc->platform_ops->register_callback(desc, irq_id, callback_desc); +} + +/** + * @brief Unregisters a generic IRQ handling function. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + return desc->platform_ops->unregister(desc, irq_id); +} + +/** + * @brief Enable global interrupts. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_global_enable(struct irq_ctrl_desc *desc) +{ + return desc->platform_ops->global_enable(desc); +} + +/** + * @brief Disable global interrupts. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_global_disable(struct irq_ctrl_desc *desc) +{ + return desc->platform_ops->global_disable(desc); +} + +/** + * @brief Set interrupt trigger level. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @param trig - New trigger level for the interrupt. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id, + enum irq_trig_level trig) +{ + if(desc->platform_ops->trigger_level_set) + return desc->platform_ops->trigger_level_set(desc, irq_id, trig); + else + return ENOSYS; +} + +/** + * @brief Enable specific interrupt. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + return desc->platform_ops->enable(desc, irq_id); +} + +/** + * @brief Disable specific interrupt. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + return desc->platform_ops->disable(desc, irq_id); +} diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/api/spi.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/api/spi.c new file mode 100644 index 0000000..c114eda --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/api/spi.c @@ -0,0 +1,144 @@ +/***************************************************************************//** + * @file spi.c + * @brief Implementation of the SPI Interface + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2020(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#include +#include +#include +#include "../../include/spi.h" +#include "../../include/error.h" + +/** + * @brief Initialize the SPI communication peripheral. + * @param desc - The SPI descriptor. + * @param param - The structure that contains the SPI parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_init(struct spi_desc **desc, + const struct spi_init_param *param) +{ + if (!param) + return FAILURE; + + if ((param->platform_ops->init(desc, param))) + return FAILURE; + + (*desc)->platform_ops = param->platform_ops; + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by spi_init(). + * @param desc - The SPI descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_remove(struct spi_desc *desc) +{ + return desc->platform_ops->remove(desc); +} + +/** + * @brief Write and read data to/from SPI. + * @param desc - The SPI descriptor. + * @param data - The buffer with the transmitted/received data. + * @param bytes_number - Number of bytes to write/read. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number) +{ + return desc->platform_ops->write_and_read(desc, data, bytes_number); +} + +/** + * @brief Write and read data to/from SPI in 3 wire mode. + * @param desc - The SPI descriptor. + * @param write_data - The buffer with the transmitted data. + * @param read_data - The buffer with the received data. + * @param write_bytes_number - Number of bytes to write. + * @param read_bytes_number - Number of bytes to read. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_write_and_read_3wire(struct spi_desc *desc, + uint8_t *write_data, + uint8_t *read_data, + uint16_t write_bytes_number, + uint16_t read_bytes_number) +{ + int ret; + if(desc->platform_ops->write_and_read_3wire != NULL){ + return desc->platform_ops->write_and_read_3wire(desc, write_data, read_data, + write_bytes_number, read_bytes_number); + } + else{ + return FAILURE; + } +} + + +/** + * @brief Iterate over head list and send all spi messages + * @param desc - The SPI descriptor. + * @param msgs - Array of messages. + * @param len - Number of messages in the array. + * @return SUCCESS in case of success, negativ error code otherwise. + */ +int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len) +{ + int32_t ret; + uint32_t i; + + if (!desc || !desc->platform_ops) + return -EINVAL; + + if (desc->platform_ops->transfer) + return desc->platform_ops->transfer(desc, msgs, len); + + for (i = 0; i < len; i++) { + if (msgs[i].rx_buff != msgs[i].tx_buff || !msgs[i].tx_buff) + return -EINVAL; + ret = spi_write_and_read(desc, msgs[i].rx_buff, + msgs[i].bytes_number); + if (IS_ERR_VALUE(ret)) + return ret; + } + + return SUCCESS; +} diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c new file mode 100644 index 0000000..7964fbf --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c @@ -0,0 +1,328 @@ +/***************************************************************************//** + * @file axi_dmac.c + * @brief Driver for the Analog Devices AXI-DMAC core. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include +#include +#include "../../../include/axi_io.h" +#include "../../../include/error.h" +#include "../axi_dmac/axi_dmac.h" + +/***************************************************************************//** + * @brief dma_isr +*******************************************************************************/ +void axi_dmac_default_isr(void *instance) +{ + struct axi_dmac *dmac = (struct axi_dmac *)instance; + uint32_t remaining_size, burst_size; + uint32_t reg_val; + + /* Get interrupt sources and clear interrupts. */ + axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val); + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val); + + if ((reg_val & AXI_DMAC_IRQ_SOT) && (dmac->big_transfer.size != 0)) { + remaining_size = dmac->big_transfer.size - + dmac->big_transfer.size_done; + burst_size = (remaining_size <= dmac->transfer_max_size) ? + remaining_size : dmac->transfer_max_size; + + dmac->big_transfer.size_done += burst_size; + dmac->big_transfer.address += burst_size; + switch (dmac->direction) { + case DMA_DEV_TO_MEM: + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, + dmac->big_transfer.address); + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0); + break; + case DMA_MEM_TO_DEV: + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, + dmac->big_transfer.address); + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0); + break; + default: + return; // Other directions are not supported yet + } + /* The current transfer was started and a new one is queued. */ + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, + burst_size); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + } + if (reg_val & AXI_DMAC_IRQ_EOT) { + dmac->big_transfer.transfer_done = true; + dmac->big_transfer.address = 0; + dmac->big_transfer.size = 0; + dmac->big_transfer.size_done = 0; + } +} + +/***************************************************************************//** + * @brief axi_dmac_read + *******************************************************************************/ +int32_t axi_dmac_read(struct axi_dmac *dmac, + uint32_t reg_addr, + uint32_t *reg_data) +{ + axi_io_read(dmac->base, reg_addr, reg_data); + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_write + *******************************************************************************/ +int32_t axi_dmac_write(struct axi_dmac *dmac, + uint32_t reg_addr, + uint32_t reg_data) +{ + axi_io_write(dmac->base, reg_addr, reg_data); + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_transfer_nonblock + *******************************************************************************/ +int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac, + uint32_t address, uint32_t size) +{ + uint32_t reg_val; + + if (size == 0) + return SUCCESS; /* nothing to do */ + + axi_dmac_read(dmac, AXI_DMAC_REG_CTRL, ®_val); + if (!(reg_val & AXI_DMAC_CTRL_ENABLE)) { + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0); + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE); + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0); + } + + axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, ®_val); + if (!(reg_val & 1)) { + switch (dmac->direction) { + case DMA_DEV_TO_MEM: + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address); + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0); + break; + case DMA_MEM_TO_DEV: + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address); + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0); + break; + default: + return FAILURE; // Other directions are not supported yet + } + if ((size - 1) > dmac->transfer_max_size) { + dmac->big_transfer.address = address; + dmac->big_transfer.size = size - 1; + dmac->big_transfer.size_done = dmac->transfer_max_size; + + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, + dmac->transfer_max_size); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + } else { + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, + size - 1); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + } + } else { + return FAILURE; + } + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_is_transfer_ready + *******************************************************************************/ +int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy) +{ + *rdy = dmac->big_transfer.transfer_done; + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_transfer + *******************************************************************************/ +int32_t axi_dmac_transfer(struct axi_dmac *dmac, + uint32_t address, uint32_t size) +{ + uint32_t transfer_id; + uint32_t reg_val; + uint32_t timeout = 0; + + if (size == 0) + return SUCCESS; /* nothing to do */ + + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0); + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE); + + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0); + + axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID, &transfer_id); + axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val); + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val); + + switch (dmac->direction) { + case DMA_DEV_TO_MEM: + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address); + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0); + break; + case DMA_MEM_TO_DEV: + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address); + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0); + break; + default: + return FAILURE; // Other directions are not supported yet + } + + if ((size - 1) > dmac->transfer_max_size) { + dmac->big_transfer.address = address; + dmac->big_transfer.size = size - 1; + dmac->big_transfer.size_done = dmac->transfer_max_size; + + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, + dmac->transfer_max_size); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + + while(!dmac->big_transfer.transfer_done) { + timeout++; + if (timeout == UINT32_MAX) + return FAILURE; + } + + dmac->big_transfer.address = 0; + dmac->big_transfer.size = 0; + dmac->big_transfer.size_done = 0; + + return SUCCESS; + } + + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, size - 1); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + + if (dmac->flags & DMA_CYCLIC) + return SUCCESS; + + /* Wait until the new transfer is queued. */ + do { + axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, ®_val); + } while(reg_val == 1); + + /* Wait until the current transfer is completed. */ + do { + axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val); + if (reg_val == (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT)) + break; + } while(!dmac->big_transfer.transfer_done); + if (reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT)) + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val); + + /* Wait until the transfer with the ID transfer_id is completed. */ + do { + axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE, ®_val); + } while((reg_val & (1u << transfer_id)) != (1u << transfer_id)); + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_init + *******************************************************************************/ +int32_t axi_dmac_init(struct axi_dmac **dmac_core, + const struct axi_dmac_init *init) +{ + struct axi_dmac *dmac; + + dmac = (struct axi_dmac *)malloc(sizeof(*dmac)); + if (!dmac) + return FAILURE; + + dmac->name = init->name; + dmac->base = init->base; + dmac->direction = init->direction; + dmac->flags = init->flags; + dmac->transfer_max_size = -1; + dmac->big_transfer.address = 0; + dmac->big_transfer.size = 0; + dmac->big_transfer.size_done = 0; + + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, dmac->transfer_max_size); + axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH, &dmac->transfer_max_size); + + *dmac_core = dmac; + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_remove + *******************************************************************************/ +int32_t axi_dmac_remove(struct axi_dmac *dmac) +{ + if(!dmac) + return FAILURE; + + free(dmac); + + return SUCCESS; +} diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h new file mode 100644 index 0000000..d7a1085 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h @@ -0,0 +1,124 @@ +/***************************************************************************//** + * @file axi_dmac.h + * @brief Driver for the Analog Devices AXI-DMAC core. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef AXI_DMAC_H_ +#define AXI_DMAC_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "../../../include/util.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#define AXI_DMAC_REG_IRQ_MASK 0x80 +#define AXI_DMAC_REG_IRQ_PENDING 0x84 +#define AXI_DMAC_IRQ_SOT BIT(0) +#define AXI_DMAC_IRQ_EOT BIT(1) + +#define AXI_DMAC_REG_CTRL 0x400 +#define AXI_DMAC_CTRL_ENABLE BIT(0) +#define AXI_DMAC_CTRL_PAUSE BIT(1) + +#define AXI_DMAC_REG_TRANSFER_ID 0x404 +#define AXI_DMAC_REG_START_TRANSFER 0x408 +#define AXI_DMAC_REG_FLAGS 0x40c +#define AXI_DMAC_REG_DEST_ADDRESS 0x410 +#define AXI_DMAC_REG_SRC_ADDRESS 0x414 +#define AXI_DMAC_REG_X_LENGTH 0x418 +#define AXI_DMAC_REG_Y_LENGTH 0x41c +#define AXI_DMAC_REG_DEST_STRIDE 0x420 +#define AXI_DMAC_REG_SRC_STRIDE 0x424 +#define AXI_DMAC_REG_TRANSFER_DONE 0x428 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ +enum dma_direction { + DMA_DEV_TO_MEM, + DMA_MEM_TO_DEV +}; + +enum dma_flags { + DMA_CYCLIC = 1, + DMA_LAST = 2 +}; + +struct axi_dma_transfer { + uint32_t size; + uint32_t address; + uint32_t size_done; + volatile bool transfer_done; +}; + +struct axi_dmac { + const char *name; + uint32_t base; + enum dma_direction direction; + uint32_t flags; + uint32_t transfer_max_size; + volatile struct axi_dma_transfer big_transfer; +}; + +struct axi_dmac_init { + const char *name; + uint32_t base; + enum dma_direction direction; + uint32_t flags; +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ +void axi_dmac_default_isr(void *instance); +int32_t axi_dmac_read(struct axi_dmac *dmac, uint32_t reg_addr, + uint32_t *reg_data); +int32_t axi_dmac_write(struct axi_dmac *dmac, uint32_t reg_addr, + uint32_t reg_data); +int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac, + uint32_t address, uint32_t size); +int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy); +int32_t axi_dmac_transfer(struct axi_dmac *dmac, + uint32_t address, uint32_t size); +int32_t axi_dmac_init(struct axi_dmac **adc_core, + const struct axi_dmac_init *init); +int32_t axi_dmac_remove(struct axi_dmac *dmac); + +#endif diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/spi_engine/spi_engine.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/spi_engine/spi_engine.c new file mode 100644 index 0000000..702d97d --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/spi_engine/spi_engine.c @@ -0,0 +1,978 @@ +/******************************************************************************* + * @file spi_engine.c + * @brief Core implementation of the SPI Engine Driver. + * @author Sergiu Cuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +/* In debug mode the printf function used in displaying the messages is causing +significant delays */ +//#define DEBUG_LEVEL 2 + +#include +#include +#include +#include +#include +#include + +#include "spi_engine.h" +#include "../axi_dmac/axi_dmac.h" +#include "../../../include/axi_io.h" +#include "../../../include/error.h" + +/** + * @brief Spi engine platform specific SPI platform ops structure + */ +const struct spi_platform_ops spi_eng_platform_ops = { + .init = &spi_engine_init, + .write_and_read = &spi_engine_spi_write_and_read, + .write_and_read_3wire = &spi_engine_spi_write_and_read_3wire, + .remove = &spi_engine_remove +}; + +/******************************************************************************/ +/***************************** Static variables *******************************/ +/******************************************************************************/ + +/** + * @brief Static variable used to sync transfers + * + */ +static uint8_t _sync_id = 0x01; + +/******************************************************************************/ +/************************** Functions Implementation **************************/ +/******************************************************************************/ + +/** + * @brief Write SPI Engine's axi registers + * + * @param desc Decriptor containing SPI Engine's parameters + * @param reg_addr The address of the SPI Engine's axi register where the data + * will be written + * @param reg_data Data that will be written + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_write(struct spi_engine_desc *desc, + uint32_t reg_addr, + uint32_t reg_data) +{ + axi_io_write(desc->spi_engine_baseaddr, reg_addr, reg_data); + + return SUCCESS; +} + +/** + * @brief Read SPI Engine's axi registers + * + * @param desc Decriptor containing SPI Engine's parameters + * @param reg_addr The address of the SPI Engine's axi register from where the + * data where the data will be read + * @param reg_data Pointer where the read that will be stored + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_read(struct spi_engine_desc *desc, + uint32_t reg_addr, + uint32_t *reg_data) +{ + axi_io_read(desc->spi_engine_baseaddr, reg_addr, reg_data); + return SUCCESS; +} + +/** + * @brief Set width of the transferred word over SPI + * + * @param desc Decriptor containing SPI interface parameters + * @param data_width The desired data width + * The supported values are: + * - 8 + * - 16 + * - 24 + * - 32 + */ +int32_t spi_engine_set_transfer_width(struct spi_desc *desc, + uint8_t data_width) +{ + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + if (data_width > desc_extra->max_data_width) + desc_extra->data_width = desc_extra->max_data_width; + else + desc_extra->data_width = data_width; + + return SUCCESS; +} + +/** + * @brief Set SPI engine clock frequency + * + * @param desc Decriptor containing SPI Engine's parameters + * @param speed_hz SPI engine transfer speed + */ +void spi_engine_set_speed(struct spi_desc *desc, + uint32_t speed_hz) +{ + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + desc_extra->clk_div = desc_extra->ref_clk_hz / + (2 * speed_hz) - 1; +} + +/** + * @brief Set the number of words transferred in a single transaction + * + * @param desc Decriptor containing SPI Engine's parameters + * @param bytes_number The number of bytes to be converted + * @return uint8_t A number of words in which bytes_number can be grouped + */ +static uint8_t spi_get_words_number(struct spi_engine_desc *desc, + uint8_t bytes_number) +{ + uint8_t xfer_word_len; + uint8_t words_number; + + xfer_word_len = desc->data_width / 8; + words_number = bytes_number / xfer_word_len; + + if ((bytes_number % xfer_word_len) != 0) + words_number++; + + return words_number; +} + +/** + * @brief Get the word length in bytes + * + * @param desc Decriptor containing SPI Engine's parameters + * @return uint8_t Number of bytes that fit in one word + */ +static uint8_t spi_get_word_length(struct spi_engine_desc *desc) +{ + uint8_t word_length; + + word_length = desc->data_width / 8; + + return word_length; +} + +/** + * @brief Compute the prescaler used to set the sleep period. + * + * @param desc Decriptor containing SPI interface parameters + * @param sleep_time_ns The amount of time where the transfer hangs + * @param sleep_div Clock prescaler + * @return int32_t This function allways returns SUCCESS + */ +static int32_t spi_get_sleep_div(struct spi_desc *desc, + uint32_t sleep_time_ns, + uint32_t *sleep_div) +{ + struct spi_engine_desc *eng_desc; + + eng_desc = desc->extra; + + /* + * Engine Wiki: + * + * The frequency of the SCLK signal is derived from the + * module clock frequency using the following formula: + * f_sclk = f_clk / ((div + 1) * 2) + */ + + *sleep_div = (desc->max_speed_hz / 1000000 * sleep_time_ns / 1000) / + ((eng_desc->clk_div + 1) * 2) - 1; + + return SUCCESS; +} + +/** + * @brief Create a new commands queue used in a spi transfer + * + * @param fifo Command buffer, usually used in fifo mode + * @param cmd Command with witch the buffer will be initiated + * @return int32_t Failure if the memory allocation failed + */ +static int32_t spi_engine_queue_new_cmd(struct spi_engine_cmd_queue **fifo, + uint32_t cmd) +{ + struct spi_engine_cmd_queue *local_fifo; + + local_fifo = (spi_engine_cmd_queue*)malloc(sizeof(*local_fifo)); + + if(!local_fifo) + return FAILURE; + + local_fifo->cmd = cmd; + local_fifo->next = NULL; + *fifo = local_fifo; + + return SUCCESS; +} + +/** + * @brief Add a command at the end of an existing queue + * + * @param fifo Command buffer, usually used in fifo mode + * @param cmd Command to be added + */ +static void spi_engine_queue_add_cmd(struct spi_engine_cmd_queue **fifo, + uint32_t cmd) +{ + struct spi_engine_cmd_queue *to_add = NULL; + struct spi_engine_cmd_queue *local_fifo; + + local_fifo = *fifo; + while (local_fifo->next != NULL) { + // Get the last element + local_fifo = local_fifo->next; + } + + // Create a new element + spi_engine_queue_new_cmd(&to_add, cmd); + // Add as the next element + local_fifo->next = to_add; +} + +/** + * @brief Add a command at the beginning of an existing queue + * + * @param fifo Command buffer, usually used in fifo mode + * @param cmd Command to be added + */ +static void spi_engine_queue_append_cmd(struct spi_engine_cmd_queue **fifo, + uint32_t cmd) +{ + struct spi_engine_cmd_queue *to_add = NULL; + + // Create a new element + spi_engine_queue_new_cmd(&to_add, cmd); + // Interchange the addresses + to_add->next = *fifo; + *fifo = to_add; +} + + +/** + * @brief Get the command from the beginning of the queue + * + * @param fifo Command buffer, usually used in fifo mode + * @param cmd Value of the command that was extracted + * @return int32_t Return FAILURE if the queue is empty + */ +static int32_t spi_engine_queue_get_cmd(struct spi_engine_cmd_queue **fifo, + uint32_t *cmd) +{ + struct spi_engine_cmd_queue *local_fifo; + + if (!*fifo) + return FAILURE; + + local_fifo = *fifo; + *cmd = local_fifo->cmd; + if ((*fifo)->next) { + *fifo = local_fifo->next; + free(local_fifo); + } else { + free(*fifo); + *fifo = NULL; + } + + return SUCCESS; +} + +/** + * @brief Free the memory allocated by a queue + * + * @param fifo The queue that needs it's memory freed + * @return int32_t This function allways return SUCCESS + */ +static int32_t spi_engine_queue_free(struct spi_engine_cmd_queue **fifo) +{ + if(*fifo && (*fifo)->next) + spi_engine_queue_free(&(*fifo)->next); + if((*fifo) != NULL) { + free(*fifo); + *fifo = NULL; + } + + return SUCCESS; +} + +/** + * @brief Write the SPI engine's command fifo + * + * @param desc Decriptor containing SPI Engine's parameters + * @param cmd The command that will be written + * @return int32_t Returns FAILURE if the the axi transfer failed + */ +static int32_t spi_engine_write_cmd_reg(struct spi_engine_desc *desc, + uint32_t cmd) +{ + int32_t ret; + + /* Check if offload is enabled */ + if(desc->offload_config & (OFFLOAD_TX_EN | OFFLOAD_RX_EN)) { + ret = spi_engine_write(desc, + SPI_ENGINE_REG_OFFLOAD_CMD_MEM(0), + cmd); + + } else { + ret = spi_engine_write(desc, + SPI_ENGINE_REG_CMD_FIFO, + cmd); + } + + return ret; +} + +/** + * @brief Write a transfer command to the SPI engine's command fifo + * + * @param desc Decriptor containing SPI Engine's parameters + * @param read_write Read/Write operation flag + * @param bytes_number Number of bytes to transfer + * @return int32_t This function allways returns SUCCESS + */ +static int32_t spi_engine_transfer(struct spi_engine_desc *desc, + uint8_t read_write, + uint8_t bytes_number) +{ + uint8_t words_number; + + words_number = spi_get_words_number(desc, bytes_number); + + desc->offload_tx_len += words_number; + + /* + * Engine Wiki: + * + * https://wiki.analog.com/resources/fpga/peripherals/spi_engine + * + * The words number is zero based + */ + + spi_engine_write_cmd_reg(desc, + SPI_ENGINE_CMD_TRANSFER(read_write, + words_number - 1)); + + return SUCCESS; +} + +/** + * @brief Change the state of the chip select port + * + * @param desc Decriptor containing SPI interface parameters + * @param assert Chip select state. + * The supported values are : + * -true (HIGH) + * -false (LOW) + */ +static void spi_engine_set_cs(struct spi_desc *desc, + bool assert) +{ + uint8_t mask; + struct spi_engine_desc *eng_desc; + + eng_desc = desc->extra; + + mask = 0xFF; + /* Switch the state only of the selected chip select */ + if (!assert) + mask ^= BIT(desc->chip_select); + + spi_engine_write_cmd_reg(eng_desc, + SPI_ENGINE_CMD_ASSERT(eng_desc->cs_delay, + mask)); +} + +/** + * @brief Add a delay between the engine commands + * + * @param desc Decriptor containing SPI interface parameters + * @param sleep_time_ns Number of nanoseconds to sleep between commands + */ +static void spi_gen_sleep_ns(struct spi_desc *desc, + uint32_t sleep_time_ns) +{ + uint32_t sleep_div; + struct spi_engine_desc *eng_desc; + + eng_desc = desc->extra; + + spi_get_sleep_div(desc, sleep_time_ns, &sleep_div); + + spi_engine_write_cmd_reg(eng_desc, SPI_ENGINE_CMD_SLEEP(sleep_div)); +} + +/** + * @brief Spi engine command interpreter + * + * @param desc Decriptor containing SPI interface parameters + * @param cmd Command to send to the engine + * @return int32_t - SUCCESS if the command is transferred + * - FAILURE if the command format is invalid + */ +static int32_t spi_engine_write_cmd(struct spi_desc *desc, + uint32_t cmd) +{ + uint8_t engine_command; + uint8_t parameter; + uint8_t modifier; + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + engine_command = (cmd >> 12) & 0x0F; + modifier = (cmd >> 8) & 0x0F; + parameter = cmd & 0xFF; + + switch(engine_command) { + case SPI_ENGINE_INST_TRANSFER: + spi_engine_transfer(desc_extra, modifier, parameter); + break; + + case SPI_ENGINE_INST_ASSERT: + if(parameter == 0xFF) { + /* Set the CS HIGH */ + spi_engine_set_cs(desc, true); + } else if(parameter == 0x00) { + /* Set the CS LOW */ + spi_engine_set_cs(desc, false); + } + break; + + /* The SYNC and SLEEP commands got the same value but different + modifier */ + case SPI_ENGINE_INST_SYNC_SLEEP: + /* SYNC instruction */ + if(modifier == 0x00) { + spi_engine_write_cmd_reg(desc_extra, cmd); + } else if(modifier == 0x01) { + spi_gen_sleep_ns(desc, parameter); + } + break; + case SPI_ENGINE_INST_CONFIG: + spi_engine_write_cmd_reg(desc_extra, cmd); + + break; + + default: + + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Prepare the command queue before sending it to the engine + * + * @param desc Decriptor containing SPI interface parameters + * @param msg Structure used to store the transfer messages + * @return int32_t This function allways returns SUCCESS + */ +static int32_t spi_engine_compile_message(struct spi_desc *desc, + struct spi_engine_msg *msg) +{ + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + /* Configure the prescaler */ + spi_engine_queue_append_cmd(&msg->cmds, + SPI_ENGINE_CMD_CONFIG( + SPI_ENGINE_CMD_REG_CLK_DIV, + desc_extra->clk_div)); + + /* Set the data transfer length */ + spi_engine_queue_append_cmd(&msg->cmds, + SPI_ENGINE_CMD_CONFIG( + SPI_ENGINE_CMD_DATA_TRANSFER_LEN, + desc_extra->data_width)); + /* + * Configure the spi mode : + * - 3 wire + * - CPOL + * - CPHA + */ + spi_engine_queue_append_cmd(&msg->cmds, + SPI_ENGINE_CMD_CONFIG( + SPI_ENGINE_CMD_REG_CONFIG, + desc->mode)); + + /* Add a sync command to signal that the transfer has finished */ + spi_engine_queue_add_cmd(&msg->cmds, SPI_ENGINE_CMD_SYNC(_sync_id)); + + return SUCCESS; +} + +/** + * @brief Initiate a spi transfer (Blocking) + * + * @param desc Decriptor containing SPI interface parameters + * @param msg Structure used to store the transfer messages + * @return int32_t - SUCCESS if the transfer finished + * - FAILURE if the memory allocation failed + */ +static int32_t spi_engine_transfer_message(struct spi_desc *desc, + struct spi_engine_msg *msg) +{ + uint32_t i; + uint32_t data; + uint32_t sync_id; + bool offload_en; + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + spi_engine_compile_message(desc, msg); + + offload_en = (desc_extra->offload_config & OFFLOAD_TX_EN) | + (desc_extra->offload_config & OFFLOAD_RX_EN); + + /* Write the command fifo buffer */ + while(msg->cmds != NULL) { + spi_engine_queue_get_cmd(&msg->cmds, &data); + spi_engine_write_cmd(desc, data); + } + + /* Write a number of tx_length WORDS on the SDO line */ + if(offload_en) { + for(i = 0; i < desc_extra->offload_tx_len; i++) + spi_engine_write(desc_extra, + SPI_ENGINE_REG_OFFLOAD_SDO_MEM(0), + msg->tx_buf[i]); + + } else { + if(msg->tx_buf != NULL){ + for(i = 0; i < msg->tx_length; i++) + spi_engine_write(desc_extra, + SPI_ENGINE_REG_SDO_DATA_FIFO, + msg->tx_buf[i]); + } + do { + spi_engine_read(desc_extra, + SPI_ENGINE_REG_SYNC_ID, + &sync_id); + } + /* Wait for the end sync signal */ + while(sync_id != _sync_id); + _sync_id++; + + /* Read a number of rx_length WORDS from the SDI line and store + them */ + for(i = 0; i < msg->rx_length; i++) { + spi_engine_read(desc_extra, + SPI_ENGINE_REG_SDI_DATA_FIFO, + &data); + /* Store the rx data if rx buffer valid, flush sdi_fifo if + rx buffer is invalid.*/ + if(msg->rx_buf != NULL){ + msg->rx_buf[i] = data; + } + } + } + + return SUCCESS; +} + +/** + * @brief Initialize the spi engine + * + * @param desc Decriptor containing SPI interface parameters + * @param param Structure containing the spi init parameters + * @return int32_t - SUCCESS if the transfer finished + * - FAILURE if the memory allocation failed + */ +int32_t spi_engine_init(struct spi_desc **desc, + const struct spi_init_param *param) +{ + uint32_t data_width = 0; + uint32_t spi_engine_version = 0; + struct spi_engine_desc *eng_desc; + struct spi_engine_init_param *spi_engine_init; + + if (!param) { + return FAILURE; + } + + *desc = malloc(sizeof(**desc)); + if(! *desc) { + free(*desc); + return FAILURE; + } + + eng_desc = (struct spi_engine_desc*)malloc(sizeof(*eng_desc)); + + if (!eng_desc) + return FAILURE; + + spi_engine_init = param->extra; + + (*desc)->max_speed_hz = param->max_speed_hz; + (*desc)->chip_select = param->chip_select; + (*desc)->mode = param->mode; + (*desc)->extra = eng_desc; + + eng_desc->offload_config = OFFLOAD_DISABLED; + eng_desc->spi_engine_baseaddr = spi_engine_init->spi_engine_baseaddr; + eng_desc->type = spi_engine_init->type; + eng_desc->cs_delay = spi_engine_init->cs_delay; + eng_desc->ref_clk_hz = spi_engine_init->ref_clk_hz; + eng_desc->clk_div = eng_desc->ref_clk_hz / + (2 * param->max_speed_hz) - 1; + + /* Perform a reset */ + spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x01); + usleep(1000); + spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x00); + + /* Get current data width */ + spi_engine_read(eng_desc, SPI_ENGINE_REG_DATA_WIDTH, &data_width); + eng_desc->max_data_width = data_width; + + spi_engine_set_transfer_width(*desc, spi_engine_init->data_width); + + /* Get spi engine version */ + spi_engine_read(eng_desc, SPI_ENGINE_REG_VERSION, &spi_engine_version); + + printf("Spi engine v%"PRIu32".%"PRIu32".%"PRIu32" successfully initialized.\n", + (spi_engine_version >> 16), + ((spi_engine_version >> 8) & 0xFF), + (spi_engine_version & 0xFF)); + + return SUCCESS; +} + +/** + * @brief Write and read on the spi interface in 4-wire mode (full-duplex) + * + * @param desc Decriptor containing SPI interface parameters + * @param data Pointer to data buffer + * @param bytes_number Number of bytes to transfer + * @return int32_t - SUCCESS if the transfer finished + * - FAILURE if the memory allocation or transfer failed + */ +int32_t spi_engine_spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number) +{ + uint8_t word_len; + uint8_t words_number; + int32_t ret; + struct spi_engine_msg msg; + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + /* If we want to access SPI interface and SPI engine offload module was + * activated, we need to disable it + * This is set in spi_engine_offload_init() */ + desc_extra->offload_config = OFFLOAD_DISABLED; + /* This is set in spi_engine_offload_transfer() */ + spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0); + + words_number = spi_get_words_number(desc_extra, bytes_number); + + msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds)); + if (!msg.cmds) + return FAILURE; + + msg.tx_buf =(uint32_t*)calloc(words_number, sizeof(msg.tx_buf[0])); + msg.rx_buf =(uint32_t*)calloc(words_number, sizeof(msg.rx_buf[0])); + msg.tx_length = words_number; + msg.rx_length = words_number; + + /* Get the length of transferred word */ + word_len = spi_get_word_length(desc_extra); + + /* Make sure the CS is HIGH before starting a transaction */ + msg.cmds->next = NULL; + msg.cmds->cmd = CS_HIGH; + // Assert select. + spi_engine_queue_add_cmd(&msg.cmds, CS_LOW); + // add read/write command + spi_engine_queue_add_cmd(&msg.cmds, WRITE_READ(bytes_number)); + // Disable select. + spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH); + + /* Pack the bytes into engine WORDS */ + for (int i = 0; i < bytes_number; i++) + msg.tx_buf[i / word_len] |= data[i] << (desc_extra->data_width- + (i % word_len + 1) * 8); + + ret = spi_engine_transfer_message(desc, &msg); + + for (int i = 0; i < bytes_number; i++) + data[i] = msg.rx_buf[(i) / word_len] >> + (desc_extra->data_width - + ((i) % word_len + 1) * 8); + + spi_engine_queue_free(&msg.cmds); + free(msg.tx_buf); + free(msg.rx_buf); + + return ret; +} + +/** + * @brief Write and read on the spi interface in 3-wire mode (half-duplex) + * + * @param desc Decriptor containing SPI interface parameters + * @param data Pointer to data buffer + * @param bytes_number Number of bytes to transfer + * @return int32_t - SUCCESS if the transfer finished + * - FAILURE if the memory allocation or transfer failed + */ +int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc, + uint8_t *write_data, + uint8_t *read_data, + uint16_t write_bytes_number, + uint16_t read_bytes_number) +{ + uint8_t word_len; + uint8_t wr_words_number; + uint8_t rd_words_number; + int32_t ret; + struct spi_engine_msg msg; + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + /* If we want to access SPI interface and SPI engine offload module was + * activated, we need to disable it + * This is set in spi_engine_offload_init() */ + desc_extra->offload_config = OFFLOAD_DISABLED; + /* This is set in spi_engine_offload_transfer() */ + spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0); + + wr_words_number = spi_get_words_number(desc_extra, write_bytes_number); + rd_words_number = spi_get_words_number(desc_extra, read_bytes_number); + + msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds)); + if (!msg.cmds) + return FAILURE; + + msg.tx_buf =(wr_words_number>0)?(uint32_t*)calloc(wr_words_number, sizeof(msg.tx_buf[0])):NULL; + msg.rx_buf =(rd_words_number>0)?(uint32_t*)calloc(rd_words_number, sizeof(msg.rx_buf[0])):NULL; + msg.tx_length = wr_words_number; + msg.rx_length = rd_words_number; + + /* Get the length of transferred word */ + word_len = spi_get_word_length(desc_extra); + + /* Make sure the CS is HIGH before starting a transaction */ + msg.cmds->next = NULL; + msg.cmds->cmd = CS_HIGH; + + // Assert select. + spi_engine_queue_add_cmd(&msg.cmds, CS_LOW); + + // add read/write command + if(write_bytes_number > 0) + spi_engine_queue_add_cmd(&msg.cmds, WRITE(write_bytes_number)); + if(read_bytes_number > 0) + spi_engine_queue_add_cmd(&msg.cmds, READ(read_bytes_number)); + + // Disable select. + spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH); + + /* Pack the bytes into engine WORDS */ + for (int i = 0; i < write_bytes_number; i++) + msg.tx_buf[i / word_len] |= write_data[i] << (desc_extra->data_width- + (i % word_len + 1) * 8); + + ret = spi_engine_transfer_message(desc, &msg); + + for (int i = 0; i < read_bytes_number; i++) + read_data[i] = msg.rx_buf[(i) / word_len] >> + (desc_extra->data_width - + ((i) % word_len + 1) * 8); + + spi_engine_queue_free(&msg.cmds); + free(msg.tx_buf); + free(msg.rx_buf); + + return ret; +} + +/** + * @brief Initialize the SPI engine's offload module + * + * @param desc Decriptor containing SPI interface parameters + * @param param Structure containing the offload init parameters + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_offload_init(struct spi_desc *desc, + const struct spi_engine_offload_init_param *param) +{ + struct spi_engine_desc *eng_desc; + struct axi_dmac_init dmac_init; + uint32_t dma_flags; + + eng_desc = desc->extra; + + eng_desc->offload_config = param->offload_config; + + if(!(param->dma_flags)) + dma_flags = DMA_CYCLIC; + else + dma_flags = *(param->dma_flags); + + if(param->offload_config & OFFLOAD_TX_EN) { + dmac_init.name = "DAC DMAC"; + dmac_init.base = param->tx_dma_baseaddr; + dmac_init.direction = DMA_MEM_TO_DEV; + dmac_init.flags = dma_flags; + axi_dmac_init(&eng_desc->offload_tx_dma, &dmac_init); + if(!eng_desc->offload_tx_dma) + return FAILURE; + } + if(param->offload_config & OFFLOAD_RX_EN) { + dmac_init.name = "ADC DMAC"; + dmac_init.base = param->rx_dma_baseaddr; + dmac_init.direction = DMA_DEV_TO_MEM; + dmac_init.flags = dma_flags; + axi_dmac_init(&eng_desc->offload_rx_dma, &dmac_init); + if(!eng_desc->offload_rx_dma) + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Initiate a SPI transfer in offload mode + * + * @param desc Decriptor containing SPI interface parameters + * @param msg Offload message that get's to be transferred + * @param no_samples Number of time the messages will be transferred + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_offload_transfer(struct spi_desc *desc, + struct spi_engine_offload_message msg, + uint32_t no_samples) +{ + struct spi_engine_msg transfer; + struct spi_engine_desc *eng_desc; + uint32_t i; + uint8_t word_length; + + eng_desc = desc->extra; + + /* Check if offload is disabled */ + if(!((eng_desc->offload_config & OFFLOAD_TX_EN) | + (eng_desc->offload_config & OFFLOAD_RX_EN))) + return FAILURE; + + spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 1); + spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 0); + + eng_desc->offload_tx_len = 0; + eng_desc->offload_rx_len = 0; + + transfer.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*transfer.cmds)); + + if (!transfer.cmds) + return FAILURE; + + transfer.tx_buf = msg.commands_data; + + /* Load the commands into the message */ + transfer.cmds->next = NULL; + transfer.cmds->cmd = msg.commands[0]; + i = 1; + while(i < msg.no_commands) { + spi_engine_queue_add_cmd(&transfer.cmds, msg.commands[i++]); + + } + + spi_engine_transfer_message(desc, &transfer); + + /* Start transfer */ + spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0x0001); + + word_length = spi_get_word_length(eng_desc); + if(eng_desc->offload_config & OFFLOAD_TX_EN) { + axi_dmac_transfer(eng_desc->offload_tx_dma, + msg.tx_addr, + word_length * eng_desc->offload_tx_len * + no_samples); + } + + if(eng_desc->offload_config & OFFLOAD_RX_EN) { + axi_dmac_transfer(eng_desc->offload_rx_dma, + msg.rx_addr, + word_length * eng_desc->offload_tx_len * + no_samples); + } + + usleep(1000); + + spi_engine_queue_free(&transfer.cmds); + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by spi_init(). + * + * @param desc Decriptor containing SPI interface parameters + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_remove(struct spi_desc *desc) +{ + struct spi_engine_desc *eng_desc; + + eng_desc = desc->extra; + + if(eng_desc->offload_config & OFFLOAD_TX_EN) + axi_dmac_remove(eng_desc->offload_tx_dma); + if(eng_desc->offload_config & OFFLOAD_RX_EN) + axi_dmac_remove(eng_desc->offload_rx_dma); + free(desc->extra); + free(desc); + + return SUCCESS; +} diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/spi_engine/spi_engine.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/spi_engine/spi_engine.h new file mode 100644 index 0000000..90dd18e --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/spi_engine/spi_engine.h @@ -0,0 +1,231 @@ +/******************************************************************************* + * @file spi_engine.h + * @brief Header file of SPI Engine core features. + * @author Sergiu Cuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef SPI_ENGINE_H +#define SPI_ENGINE_H + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +#include "spi_engine_private.h" +#include "../../platform/spi_extra.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define OFFLOAD_DISABLED 0x00 +#define OFFLOAD_TX_EN BIT(0) +#define OFFLOAD_RX_EN BIT(1) +#define OFFLOAD_TX_RX_EN OFFLOAD_TX_EN | OFFLOAD_RX_EN + +#define SPI_ENGINE_MSG_QUEUE_END 0xFFFFFFFF + +/* Spi engine commands */ +#define WRITE_OR_READ(mode, no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\ +((mode) << 8) | (no_bytes)) + +#define WRITE(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\ + (SPI_ENGINE_INSTRUCTION_TRANSFER_W << 8) | (no_bytes)) + +#define READ(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\ + (SPI_ENGINE_INSTRUCTION_TRANSFER_R << 8) | (no_bytes)) + +#define WRITE_READ(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\ + (SPI_ENGINE_INSTRUCTION_TRANSFER_RW << 8) | (no_bytes)) + + + +#define SLEEP(time) SPI_ENGINE_CMD_SLEEP(time & 0xF) + +/* The delay and chip select parmeters are passed over the engine descriptor +and will be used inside the function call */ +#define CS_HIGH SPI_ENGINE_CMD_ASSERT(0x00, 0xFF) +#define CS_LOW SPI_ENGINE_CMD_ASSERT(0x00, 0x00) + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @struct spi_engine_init_param + * @brief Structure containing the init parameters needed by the SPI engine + */ +struct spi_engine_init_param { + /** SPI engine reference clock */ + uint32_t ref_clk_hz; + /** Type of implementation */ + enum xil_spi_type type; + /** Base address where the HDL core is situated */ + uint32_t spi_engine_baseaddr; + /** Delay between the CS toggle and the start of SCLK */ + uint32_t cs_delay; + /** Data with of one SPI transfer ( in bits ) */ + uint8_t data_width; +}; + + +/** + * @struct spi_engine_desc + * @brief Structure representing an SPI engine device + */ +struct spi_engine_desc { + /** SPI engine reference clock */ + uint32_t ref_clk_hz; + /** Type of implementation */ + enum xil_spi_type type; + /** Pointer to a DMAC used in transmission */ + struct axi_dmac *offload_tx_dma; + /** Pointer to a DMAC used in reception */ + struct axi_dmac *offload_rx_dma; + /** Offload's module transfer direction : TX, RX or both */ + uint8_t offload_config; + /** Number of words that the module has to send */ + uint8_t offload_tx_len; + /** Number of words that the module has to receive */ + uint8_t offload_rx_len; + /** Base address where the HDL core is situated */ + uint32_t spi_engine_baseaddr; + /** Base address where the RX DMAC core is situated */ + uint32_t rx_dma_baseaddr; + /** Base address where the TX DMAC core is situated */ + uint32_t tx_dma_baseaddr; + /** Delay between the CS toggle and the start of SCLK */ + uint8_t cs_delay; + /** Clock divider used in transmission delays */ + uint32_t clk_div; + /** Data with of one SPI transfer ( in bits ) */ + uint8_t data_width; + /** The maximum data width supported by the engine */ + uint8_t max_data_width; +}; + + +/** + * @struct spi_engine_offload_init_param + * @brief Structure containing the init parameters needed by the offload module + */ +struct spi_engine_offload_init_param { + /** Base address where the RX DMAC core is situated */ + uint32_t rx_dma_baseaddr; + /** Base address where the TX DMAC core is situated */ + uint32_t tx_dma_baseaddr; + /** DMAC flags - if not initialized, the default value is DMA_CYCLIC */ + uint32_t *dma_flags; + /** Offload's module transfer direction : TX, RX or both */ + uint8_t offload_config; +}; + +/** + * @struct spi_engine_offload_message + * @brief Structure representing an offload message + */ +struct spi_engine_offload_message { + /** Pointer to the SPI engine commands buffer that will be sent. + * The available commands can be found at: + * https://wiki.analog.com/resources/fpga/peripherals/spi_engine/ + */ + uint32_t *commands; + /** Length of the SPI engine commands buffer */ + uint32_t no_commands; + /** Pointer of the data that will be sent over spi */ + uint32_t *commands_data; + /** The address where the data that will be transmitted is situated */ + uint32_t tx_addr; + /** The address where the data that will be received is situated */ + uint32_t rx_addr; +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/** + * @brief Spi engine platform specific SPI platform ops structure + */ +extern const struct spi_platform_ops xil_spi_ops; + +/* Write SPI Engine's axi registers */ +int32_t spi_engine_write(struct spi_engine_desc *desc, + uint32_t reg_addr, + uint32_t reg_data); + +/* Read SPI Engine's axi registers */ +int32_t spi_engine_read(struct spi_engine_desc *desc, + uint32_t reg_addr, + uint32_t *reg_data); +/* Initialize the SPI engine device */ +int32_t spi_engine_init(struct spi_desc **desc, + const struct spi_init_param *param); + +/* Write and read data over SPI using the SPI engine */ +int32_t spi_engine_spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number); + +/* Write and read data over SPI using the SPI engine in 3-wire mode */ +int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc, + uint8_t *write_data, + uint8_t *read_data, + uint16_t write_bytes_number, + uint16_t read_bytes_number); +/* Free the resources used by the SPI engine device */ +int32_t spi_engine_remove(struct spi_desc *desc); + +/* Initialize the SPI engine offload module */ +int32_t spi_engine_offload_init(struct spi_desc *desc, + const struct spi_engine_offload_init_param *param); + +/* Write and read data over SPI using the offload module */ +int32_t spi_engine_offload_transfer(struct spi_desc *desc, + struct spi_engine_offload_message msg, + uint32_t no_samples); + +/* Set SPI transfer width */ +int32_t spi_engine_set_transfer_width(struct spi_desc *desc, + uint8_t data_wdith); + +/* Set SPI transfer speed */ +void spi_engine_set_speed(struct spi_desc *desc, + uint32_t speed_hz); + +#endif // SPI_ENGINE_H diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h new file mode 100644 index 0000000..2c71ebf --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h @@ -0,0 +1,154 @@ +/******************************************************************************* + * @file spi_engine_private.h + * @brief Private definitions of the SPI Engine + * @author Sergiu Cuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef SPI_ENGINE_PRIVATE_H +#define SPI_ENGINE_PRIVATE_H + +#include +#include + +#include "../../../include/spi.h" +#include "../../../include/util.h" + +/******************************************************************************/ +/*************************** Spi Engine registers *****************************/ +/******************************************************************************/ + +#define SPI_ENGINE_REG_VERSION 0x00 +#define SPI_ENGINE_REG_DATA_WIDTH 0x0C +#define SPI_ENGINE_REG_RESET 0x40 +#define SPI_ENGINE_REG_INT_ENABLE 0x80 +#define SPI_ENGINE_REG_INT_PENDING 0x84 +#define SPI_ENGINE_REG_INT_SOURCE 0x88 +#define SPI_ENGINE_REG_SYNC_ID 0xC0 +#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xD0 +#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xD4 +#define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xD8 +#define SPI_ENGINE_REG_CMD_FIFO 0xE0 +#define SPI_ENGINE_REG_SDO_DATA_FIFO 0xE4 +#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xE8 +#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xEC + +/******************************************************************************/ +/************************ Spi Engine register parameters **********************/ +/******************************************************************************/ + +#define SPI_ENGINE_INST_TRANSFER 0x00 +#define SPI_ENGINE_INST_ASSERT 0x01 +#define SPI_ENGINE_INST_CONFIG 0x02 +#define SPI_ENGINE_INST_SYNC_SLEEP 0x03 +#define SPI_ENGINE_INST_MISC 0x03 +#define SPI_ENGINE_CMD_REG_CLK_DIV 0x00 +#define SPI_ENGINE_CMD_REG_CONFIG 0x01 +#define SPI_ENGINE_CMD_DATA_TRANSFER_LEN 0x02 +#define SPI_ENGINE_MISC_SYNC 0x00 +#define SPI_ENGINE_MISC_SLEEP 0x01 +#define SPI_ENGINE_SYNC_TRANSFER_BEGIN BIT(1) +#define SPI_ENGINE_SYNC_TRANSFER_END BIT(2) +#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0) +#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1) +#define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2) +#define SPI_ENGINE_INT_SYNC BIT(3) +#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE BIT(0) +#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED BIT(0) +#define SPI_ENGINE_CONFIG_CPHA BIT(0) +#define SPI_ENGINE_CONFIG_CPOL BIT(1) +#define SPI_ENGINE_CONFIG_3WIRE BIT(2) +#define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff) +#define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff) +#define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff) + +/******************************************************************************/ +/**************************** Spi Engine commands *****************************/ +/******************************************************************************/ + +#define SPI_ENGINE_INSTRUCTION_TRANSFER_W 0x01 +#define SPI_ENGINE_INSTRUCTION_TRANSFER_R 0x02 +#define SPI_ENGINE_INSTRUCTION_TRANSFER_RW 0x03 + +#define SPI_ENGINE_REG_OFFLOAD_CTRL(x) (0x100 + (0x20 * x)) +#define SPI_ENGINE_REG_OFFLOAD_STATUS(x) (0x104 + (0x20 * x)) +#define SPI_ENGINE_REG_OFFLOAD_RESET(x) (0x108 + (0x20 * x)) +#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM(x) (0x110 + (0x20 * x)) +#define SPI_ENGINE_REG_OFFLOAD_SDO_MEM(x) (0x114 + (0x20 * x)) + +#define SPI_ENGINE_CMD(inst, arg1, arg2) \ + (((inst & 0x03) << 12) | \ + ((arg1 & 0x03) << 8) | arg2 ) + +#define SPI_ENGINE_CMD_TRANSFER(readwrite, n) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, \ + (readwrite), (n)) + +#define SPI_ENGINE_CMD_ASSERT(delay, cs) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, \ + (delay), (cs)) + +#define SPI_ENGINE_CMD_CONFIG(reg, val) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_CONFIG, \ + (reg), (val)) + +#define SPI_ENGINE_CMD_SLEEP(delay) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \ + SPI_ENGINE_MISC_SLEEP, \ + (delay)) + +#define SPI_ENGINE_CMD_SYNC(id) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \ + SPI_ENGINE_MISC_SYNC, \ + (id)) + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +typedef struct spi_engine_cmd_queue { + uint32_t cmd; + struct spi_engine_cmd_queue *next; +} spi_engine_cmd_queue; + +typedef struct spi_engine_msg { + uint32_t *tx_buf; + uint32_t *rx_buf; + uint32_t tx_length; + uint32_t rx_length; + struct spi_engine_cmd_queue *cmds; +} spi_engine_msg; + +#endif // SPI_ENGINE_PRIVATE_H diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/frequency/ad9516/ad9516.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/frequency/ad9516/ad9516.c new file mode 100644 index 0000000..c47524d --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/frequency/ad9516/ad9516.c @@ -0,0 +1,129 @@ +/***************************************************************************//** + * @file ad9516.c + * @brief Implementation of AD9680 Driver. + * @author DBogdan (dragos.bogdan@analog.com) + ******************************************************************************** + * Copyright 2014-2016(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include "ad9516.h" + +#include +#include +#include "../../../include/error.h" + +/***************************************************************************//** + * @brief ad9516_read + *******************************************************************************/ +int32_t ad9516_read(struct ad9516_dev *dev, + uint16_t reg_addr, + uint8_t *reg_data) +{ + uint8_t tx_buf[2]; + uint8_t rx_buf[1]; + int32_t ret; + + tx_buf[0] = 0x80 | (reg_addr >> 8); + tx_buf[1] = reg_addr & 0xFF; + + + ret = spi_write_and_read_3wire(dev->spi_desc, + tx_buf, rx_buf, 2, 1); + + *reg_data = rx_buf[0]; + + return ret; +} + +/***************************************************************************//** + * @brief ad9516_write + *******************************************************************************/ +int32_t ad9516_write(struct ad9516_dev *dev, + uint16_t reg_addr, + uint8_t reg_data) +{ + uint8_t buf[3]; + + int32_t ret; + + buf[0] = reg_addr >> 8; + buf[1] = reg_addr & 0xFF; + buf[2] = reg_data; + + ret = spi_write_and_read_3wire(dev->spi_desc, + buf, NULL, 3, 0); + return ret; +} + +/***************************************************************************//** + * @brief ad9516_init + *******************************************************************************/ +int32_t ad9516_init(struct ad9516_dev **device, + const struct ad9516_init_param *init_param) +{ + int ret = SUCCESS; + struct ad9516_dev *dev; + + dev = (struct ad9516_dev *)malloc(sizeof(*dev)); + if (!dev) + return FAILURE; + + /* SPI */ + ret = spi_init(&dev->spi_desc, init_param->spi_init); + + *device = dev; + + return ret; +} + +/***************************************************************************//** + * @brief Free the resources allocated by ad9516_setup(). + * + * @param dev - The device structure. + * + * @return SUCCESS in case of success, negative error code otherwise. +*******************************************************************************/ +int32_t ad9516_remove(struct ad9516_dev *dev) +{ + int32_t ret; + + ret = spi_remove(dev->spi_desc); + + free(dev); + + return ret; +} diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/frequency/ad9516/ad9516.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/frequency/ad9516/ad9516.h new file mode 100644 index 0000000..04fc637 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/frequency/ad9516/ad9516.h @@ -0,0 +1,89 @@ +/***************************************************************************//** + * @file ad9516.h + * @brief Header file of ad9516 Driver. + * @author DBogdan (dragos.bogdan@analog.com) + ******************************************************************************** + * Copyright 2014-2016(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *******************************************************************************/ +#ifndef AD9516_H_ +#define AD9516_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "../../../include/delay.h" +#include "../../../include/spi.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ +struct ad9516_dev { + /* SPI */ + spi_desc *spi_desc; +}; + +struct ad9516_init_param { + /* SPI */ + spi_init_param *spi_init; +}; + +struct ad9516_config { + uint16_t addr; + uint8_t value; +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +int32_t ad9516_read(struct ad9516_dev *dev, + uint16_t reg_addr, + uint8_t *reg_data); + +int32_t ad9516_write(struct ad9516_dev *dev, + uint16_t reg_addr, + uint8_t reg_data); + +int32_t ad9516_init(struct ad9516_dev **device, + const struct ad9516_init_param *init_param); + +int32_t ad9516_remove(struct ad9516_dev *dev); + +#endif diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/axi_io.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/axi_io.c new file mode 100644 index 0000000..d7b5a82 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/axi_io.c @@ -0,0 +1,79 @@ +/***************************************************************************//** + * @file xilinx/axi_io.c + * @brief Implementation of Xilinx AXI IO. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include "../../include/error.h" +#include "../../include/axi_io.h" + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief AXI IO Xilinx specific read function. + * @param base - Base address + * @param offset - Address offset + * @param data - variable where returned data is stored + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data) +{ + *data = Xil_In32(base + offset); + + return SUCCESS; +} + +/** + * @brief AXI IO Xilinx specific write function. + * @param base - Base address + * @param offset - Address offset + * @param data - data to be written. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data) +{ + Xil_Out32(base + offset, data); + + return SUCCESS; +} + diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/delay.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/delay.c new file mode 100644 index 0000000..ca06169 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/delay.c @@ -0,0 +1,77 @@ +/***************************************************************************//** + * @file xilinx/delay.c + * @brief Implementation of Xilinx Delay Functions. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include "../../include/delay.h" +#include + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Generate microseconds delay. + * @param usecs - Delay in microseconds. + * @return None. + */ +void udelay(uint32_t usecs) +{ +#ifdef _XPARAMETERS_PS_H_ + usleep(usecs); +#else + usleep(usecs / 20); // FIXME +#endif +} + +/** + * @brief Generate miliseconds delay. + * @param msecs - Delay in miliseconds. + * @return None. + */ +void mdelay(uint32_t msecs) +{ +#ifdef _XPARAMETERS_PS_H_ + usleep(msecs * 1000); +#else + usleep(msecs * 50); // FIXME +#endif +} diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/gpio_extra.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/gpio_extra.h new file mode 100644 index 0000000..dbc64b9 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/gpio_extra.h @@ -0,0 +1,95 @@ +/******************************************************************************* + * @file xilinx/gpio_extra.h + * @brief Header containing extra types used in the gpio driver + * @author scuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef GPIO_EXTRA_H_ +#define GPIO_EXTRA_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum xil_gpio_type + * @brief Xilinx platform architecture sections + */ +typedef enum xil_gpio_type { + /** Programmable Logic */ + GPIO_PL, + /** Processing System */ + GPIO_PS +} xil_gpio_type; + +/** + * @struct xil_gpio_init_param + * @brief Structure holding the initialization parameters for Xilinx platform + * specific GPIO parameters. + */ +typedef struct xil_gpio_init_param { + /** Xilinx architecture */ + enum xil_gpio_type type; + /** Device ID */ + uint32_t device_id; +} xil_gpio_init_param; + +/** + * @struct xil_gpio_desc + * @brief Xilinx platform specific GPIO descriptor + */ +typedef struct xil_gpio_desc { + /** Xilinx architecture */ + enum xil_gpio_type type; + /** Xilinx GPIO configuration */ + void *config; + /** Xilinx GPIO Instance */ + void *instance; +} xil_gpio_desc; + +/** + * @brief Xilinx platform specific gpio platform ops structure + */ +extern const struct gpio_platform_ops xil_gpio_ops; + +#endif diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/irq_extra.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/irq_extra.h new file mode 100644 index 0000000..1c9b959 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/irq_extra.h @@ -0,0 +1,91 @@ +/******************************************************************************* + * @file irq_extra.h + * @brief Header containing types used in the irq driver. + * @author Cristian Pop (cristian.pop@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef IRQ_EXTRA_H_ +#define IRQ_EXTRA_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include "../../include/irq.h" + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum xil_irq_type + * @brief Xilinx platform architecture sections + */ +enum xil_irq_type { + /** Programmable Logic */ + IRQ_PL, + /** Processing System */ + IRQ_PS +}; + +/** + * @struct xil_irq_init_param + * @brief Structure holding the initialization parameters for Xilinx platform + * specific IRQ parameters. + */ +struct xil_irq_init_param { + /** Xilinx architecture */ + enum xil_irq_type type; +}; + +/** + * @struct xil_irq_desc + * @brief Xilinx platform specific IRQ descriptor + */ +struct xil_irq_desc { + /** Xilinx architecture */ + enum xil_irq_type type; + /** Xilinx IRQ Instance */ + void *instance; +}; + +/** + * @brief Xilinx specific IRQ platform ops structure + */ +extern const struct irq_platform_ops xil_irq_ops; + +#endif diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/spi_extra.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/spi_extra.h new file mode 100644 index 0000000..2edb42c --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/spi_extra.h @@ -0,0 +1,115 @@ +/******************************************************************************* + * @file xilinx/spi_extra.h + * @brief Header containing extra types used in the spi driver. + * @author scuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef SPI_EXTRA_H_ +#define SPI_EXTRA_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include "../../include/spi.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define SPI_CS_DECODE 0x01 +#define SPI_DEASSERT_CURRENT_SS 0x0F + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum xil_spi_type + * @brief Xilinx platform architecture sections + */ +enum xil_spi_type { + /** Programmable Logic */ + SPI_PL, + /** Processing System */ + SPI_PS, + /** SPI Engine */ + SPI_ENGINE +}; + +/** + * @struct xil_spi_init_param + * @brief Structure holding the initialization parameters for Xilinx platform + * specific SPI parameters when using xil_spi_ops. + */ +typedef struct xil_spi_init_param { + /** Xilinx architecture */ + enum xil_spi_type type; + /** SPI flags */ + uint32_t flags; +} xil_spi_init_param; + +/** + * @struct xil_spi_desc + * @brief Xilinx platform specific SPI descriptor + */ +typedef struct xil_spi_desc { + /** Xilinx architecture */ + enum xil_spi_type type; + /** SPI flags */ + uint32_t flags; + /** SPI configuration */ + void *config; + /** SPI instance */ + void *instance; +} xil_spi_desc; + +/** + * @brief SPI engine platform ops structure + */ +extern const struct spi_platform_ops spi_eng_platform_ops; + +/** + * @brief Xilinx specific SPI platform ops structure + */ +extern const struct spi_platform_ops xil_spi_ops; + +/** + * @brief Xilinx SPI PS register functions. No extra param needed + */ +extern const struct spi_platform_ops xil_spi_reg_ops_pl; + +#endif // SPI_EXTRA_H_ diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/uart_extra.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/uart_extra.h new file mode 100644 index 0000000..c877ebf --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/uart_extra.h @@ -0,0 +1,107 @@ +/******************************************************************************* + * @file xilinx/uart_extra.h + * @brief Header containing types used in the uart driver. + * @author Cristian Pop (cristian.pop@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef UART_EXTRA_H_ +#define UART_EXTRA_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define UART_BUFF_LENGTH 256 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum xil_uart_type + * @brief Xilinx platform architecture sections + */ +enum xil_uart_type { + /** Programmable Logic */ + UART_PL, + /** Processing System */ + UART_PS +}; + +/** + * @struct xil_uart_init_param + * @brief Structure holding the initialization parameters for Xilinx platform + * specific UART parameters. + */ +struct xil_uart_init_param { + /** Xilinx architecture */ + enum xil_uart_type type; + /** Interrupt Request ID */ + uint32_t irq_id; + /** Interrupt Request Descriptor */ + struct irq_ctrl_desc *irq_desc; +}; + +/** + * @struct xil_uart_desc + * @brief Xilinx platform specific UART descriptor + */ +struct xil_uart_desc { + /** Xilinx architecture */ + enum xil_uart_type type; + /** Interrupt Request ID */ + uint32_t irq_id; + /** Interrupt Request Descriptor */ + struct irq_ctrl_desc *irq_desc; + /** FIFO */ + struct fifo_element *fifo; + /** FIFO read offset */ + uint32_t fifo_read_offset; + /** UART Buffer */ + char buff[UART_BUFF_LENGTH]; + /** Number of bytes received */ + uint32_t bytes_received; + /** Total number of errors */ + uint32_t total_error_count; + /** UART Instance */ + void *instance; +}; + +#endif diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/xilinx_gpio.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/xilinx_gpio.c new file mode 100644 index 0000000..08ed15f --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/xilinx_gpio.c @@ -0,0 +1,464 @@ +/***************************************************************************//** + * @file xilinx/xilinx_gpio.c + * @brief Implementation of Xilinx GPIO Generic Driver. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +#include +#ifdef XPAR_XGPIO_NUM_INSTANCES +#include +#endif +#ifdef XPAR_XGPIOPS_NUM_INSTANCES +#include +#endif + +#include "gpio_extra.h" +#include "../../include/error.h" +#include "../../include/gpio.h" + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Prepare the GPIO decriptor. + * @param desc - The GPIO descriptor. + * @param param - The structure that contains the GPIO parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t _gpio_init(struct gpio_desc *desc, + const struct gpio_init_param *param) +{ + int32_t ret; + struct xil_gpio_desc *xdesc; + struct xil_gpio_init_param *xinit; + + ret = FAILURE; + + xdesc = desc->extra; + xinit = param->extra; + + xdesc->type = xinit->type; + desc->number = param->number; + + switch (xinit->type) { + case GPIO_PL: +#ifdef XGPIO_H + xdesc->instance = (XGpio *)malloc(sizeof(XGpio)); + if(!xdesc->instance) + goto pl_error; + + xdesc->config = XGpio_LookupConfig(xinit->device_id); + if(xdesc->config == NULL) + goto pl_error; + + ret = XGpio_CfgInitialize(xdesc->instance, + xdesc->config, + ((XGpio_Config*)xdesc->config) + ->BaseAddress); + if(ret < 0) + goto pl_error; + + break; +pl_error: + free(xdesc->instance); +#endif + goto error; + case GPIO_PS: +#ifdef XGPIOPS_H + xdesc->instance = (XGpioPs *)malloc(sizeof(XGpioPs)); + if(!xdesc->instance) + goto ps_error; + + xdesc->config = XGpioPs_LookupConfig(xinit->device_id); + if(xdesc->config == NULL) + goto ps_error; + + ret = XGpioPs_CfgInitialize(xdesc->instance, + xdesc->config, + ((XGpioPs_Config*)xdesc->config)->BaseAddr); + if(ret < 0) + goto ps_error; + break; +ps_error: + free(xdesc->instance); +#endif + goto error; +error: + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Obtain the GPIO decriptor. + * @param desc - The GPIO descriptor. + * @param param - GPIO initialization parameters + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_get(struct gpio_desc **desc, + const struct gpio_init_param *param) +{ + struct gpio_desc *descriptor; + struct xil_gpio_desc *extra; + int32_t ret; + + descriptor = (struct gpio_desc *)malloc(sizeof(*descriptor)); + extra = (struct xil_gpio_desc*)malloc(sizeof(*extra)); + + if (!descriptor || !extra) + return FAILURE; + + descriptor->extra = extra; + ret = _gpio_init(descriptor, param); + + if(ret != SUCCESS) + goto error; + + *desc = descriptor; + + return SUCCESS; +error: + free(extra); + free(descriptor); + + return FAILURE; +} + +/** + * @brief Get the value of an optional GPIO. + * @param desc - The GPIO descriptor. + * @param param - GPIO Initialization parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_get_optional(struct gpio_desc **desc, + const struct gpio_init_param *param) +{ + if(param == NULL) { + *desc = NULL; + return SUCCESS; + } + + return xil_gpio_get(desc, param); +} + +/** + * @brief Free the resources allocated by gpio_get(). + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_remove(struct gpio_desc *desc) +{ + if (desc != NULL) { + free(((xil_gpio_desc *)(desc->extra))->instance); + free(desc->extra); + free(desc); + } + + return SUCCESS; +} + +/** + * @brief Enable the input direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_direction_input(struct gpio_desc *desc) +{ + struct xil_gpio_desc *extra; +#ifdef XGPIO_H + uint8_t pin = desc->number; + uint32_t channel = 1; + uint32_t config = 0; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + /* We assume that pin 32 is the first pin from channel 2 */ + if (pin >= 32) { + channel = 2; + pin -= 32; + } + + config = XGpio_GetDataDirection((XGpio *)extra->instance, + channel); + config |= (1 << pin); + XGpio_SetDataDirection((XGpio *)extra->instance, + channel, + config); +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + XGpioPs_SetDirectionPin(extra->instance, + desc->number, + GPIO_IN); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Enable the output direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_direction_output(struct gpio_desc *desc, + uint8_t value) +{ + struct xil_gpio_desc *extra; +#ifdef XGPIO_H + uint8_t pin = desc->number; + uint8_t channel; + uint32_t reg_val; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + + reg_val = XGpio_GetDataDirection(extra->instance, + channel); + reg_val &= ~(1 << pin); + XGpio_SetDataDirection(extra->instance, + channel, + reg_val); + reg_val = XGpio_DiscreteRead(extra->instance, + channel); + if(value) + reg_val |= (1 << pin); + else + reg_val &= ~(1 << pin); + XGpio_DiscreteWrite(extra->instance, + channel, + reg_val); +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + XGpioPs_SetDirectionPin(extra->instance, + desc->number, + GPIO_OUT); + XGpioPs_SetOutputEnablePin(extra->instance, + desc->number, + GPIO_OUT); + XGpioPs_WritePin(extra->instance, + desc->number, + value); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Get the direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param direction - The direction. + * Example: GPIO_OUT + * GPIO_IN + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_get_direction(struct gpio_desc *desc, + uint8_t *direction) +{ + if (!desc) + return FAILURE; + + struct xil_gpio_desc *extra; + uint8_t pin = desc->number; + +#ifdef XGPIO_H + uint8_t channel; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + *direction = ((XGpio_GetDataDirection(extra->instance, + channel) >> pin) & 0x1) ^ 0x1; +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + *direction = XGpioPs_GetDirectionPin(extra->instance, pin); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Set the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_set_value(struct gpio_desc *desc, + uint8_t value) +{ + struct xil_gpio_desc *extra; +#ifdef XGPIO_H + uint8_t pin = desc->number; + uint8_t channel; + uint32_t reg_val; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + + reg_val = XGpio_DiscreteRead(extra->instance, channel); + if(value) + reg_val |= (1 << pin); + else + reg_val &= ~(1 << pin); + XGpio_DiscreteWrite(extra->instance, channel, reg_val); +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + XGpioPs_WritePin(extra->instance, desc->number, value); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Get the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_get_value(struct gpio_desc *desc, + uint8_t *value) +{ + if (!desc) + return FAILURE; + + struct xil_gpio_desc *extra; + uint8_t pin = desc->number; + +#ifdef XGPIO_H + uint8_t channel; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + *value = (XGpio_DiscreteRead(extra->instance, channel) >> pin) & 0x01; +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + *value = XGpioPs_ReadPin(extra->instance, pin); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Xilinx platform specific GPIO platform ops structure + */ +const struct gpio_platform_ops xil_gpio_ops = { + .gpio_ops_get = &xil_gpio_get, + .gpio_ops_get_optional = &xil_gpio_get_optional, + .gpio_ops_remove = &xil_gpio_remove, + .gpio_ops_direction_input = &xil_gpio_direction_input, + .gpio_ops_direction_output = &xil_gpio_direction_output, + .gpio_ops_get_direction = &xil_gpio_get_direction, + .gpio_ops_set_value = &xil_gpio_set_value, + .gpio_ops_get_value = &xil_gpio_get_value, +}; diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/xilinx_irq.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/xilinx_irq.c new file mode 100644 index 0000000..e688a3a --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/xilinx_irq.c @@ -0,0 +1,384 @@ +/***************************************************************************//** + * @file xilinx/xilinx_irq.c + * @brief Implementation of Xilinx IRQ Generic Driver. + * @author Cristian Pop (cristian.pop@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include +#include "irq_extra.h" +#include "../../include/irq.h" +#include "../../include/error.h" +#ifdef XPAR_XSCUGIC_NUM_INSTANCES +#include +#endif +#ifdef XPAR_XINTC_NUM_INSTANCES +#include +#endif +#ifdef XPAR_XTMRCTR_NUM_INSTANCES +#include +#endif + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Initialize the IRQ interrupts. + * @param desc - The IRQ controller descriptor. + * @param param - The structure that contains the IRQ parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_ctrl_init(struct irq_ctrl_desc **desc, + const struct irq_init_param *param) +{ + int32_t status; + struct irq_ctrl_desc *descriptor; + struct xil_irq_desc *xil_dev; +#ifdef XSCUGIC_H + void *config; +#endif + + descriptor = (struct irq_ctrl_desc *)calloc(1, sizeof *descriptor); + if(!descriptor) + return FAILURE; + xil_dev = (struct xil_irq_desc *)calloc(1, sizeof *xil_dev); + if(!xil_dev) { + free(descriptor); + return FAILURE; + } + + Xil_ExceptionInit(); + + descriptor->irq_ctrl_id = param->irq_ctrl_id; + descriptor->extra = xil_dev; + xil_dev->type = ((struct xil_irq_init_param *)param->extra)->type; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + xil_dev->instance = calloc(1, sizeof(XScuGic)); + if(!xil_dev->instance) + goto error; + + config = XScuGic_LookupConfig(descriptor->irq_ctrl_id); + if(!config) + goto ps_error; + + status = XScuGic_CfgInitialize(xil_dev->instance, config, + ((XScuGic_Config *)config)->CpuBaseAddress); + if (status != SUCCESS) + goto ps_error; + + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler)XScuGic_InterruptHandler, + xil_dev->instance); + + break; +ps_error: + free(xil_dev->instance); +#endif + goto error; + case IRQ_PL: +#ifdef XINTC_H + xil_dev->instance = calloc(1, sizeof(XIntc)); + if(!xil_dev->instance) + goto error; + + status = XIntc_Initialize(xil_dev->instance, descriptor->irq_ctrl_id); + if(status != SUCCESS) + goto pl_error; + + status = XIntc_Start(xil_dev->instance, XIN_REAL_MODE); + if(status != SUCCESS) + goto pl_error; + + break; +pl_error: + free(xil_dev->instance); +#endif + goto error; + default: + goto error; + + break; + } + + *desc = descriptor; + + return SUCCESS; + +error: + free(xil_dev); + free(descriptor); + + return FAILURE; +} + +/** + * @brief Enable global interrupts. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_global_enable(struct irq_ctrl_desc *desc) +{ + /* Enable interrupts */ + Xil_ExceptionEnable(); + + return SUCCESS; +} + +/** + * @brief Disable global interrupts. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_global_disable(struct irq_ctrl_desc *desc) +{ + /* Disable interrupts */ + Xil_ExceptionDisable(); + + return SUCCESS; +} + +/** + * @brief Enable specific interrupt. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + XScuGic_Enable(xil_dev->instance, irq_id); +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + XIntc_Enable(xil_dev->instance, irq_id); +#endif + break; + default: + + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Disable specific interrupt. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + XScuGic_Disable(xil_dev->instance, irq_id); +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + XIntc_Disable(xil_dev->instance, irq_id); +#endif + break; + default: + + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Register a callback to handle the irq events. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @param callback_desc - Callback descriptor + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id, + struct callback_desc *callback_desc) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + return XScuGic_Connect(xil_dev->instance, irq_id, + (Xil_InterruptHandler) callback_desc->callback, + callback_desc->ctx); +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + if (irq_id == XPAR_AXI_INTC_AXI_TIMER_INTERRUPT_INTR) { + int32_t ret; + + ret = XIntc_Connect(xil_dev->instance, irq_id, + XTmrCtr_InterruptHandler, callback_desc->config); + if (IS_ERR_VALUE(ret)) + return FAILURE; + XTmrCtr_SetHandler(callback_desc->config, + (XTmrCtr_Handler)callback_desc->callback, + callback_desc->ctx); + + return SUCCESS; + } + return XIntc_Connect(xil_dev->instance, irq_id, + (XInterruptHandler) callback_desc->callback, + callback_desc->ctx); +#endif + break; + default: + break; + } + + return FAILURE; +} + +/** + * @brief Set interrupt trigger level. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @param trig - New trigger level for the interrupt. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id, + enum irq_trig_level trig) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + if(trig == IRQ_EDGE_BOTH) + return -EINVAL; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + ; + uint8_t priority, trigger; + + XScuGic_GetPriorityTriggerType(xil_dev->instance, irq_id, &priority, + &trigger); + trigger = trig; + XScuGic_SetPriorityTriggerType(xil_dev->instance, irq_id, priority, + trigger); + + return SUCCESS; +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + /* Interrupt trigger determined in hardware. TODO: verify */ + return SUCCESS; +#endif + break; + default: + break; + } + + return FAILURE; +} + +/** + * @brief Unregisters a generic IRQ handling function. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + XScuGic_Disconnect(xil_dev->instance, irq_id); +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + XIntc_Disconnect(xil_dev->instance, irq_id); +#endif + break; + default: + + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by irq_ctrl_init(). + * @param desc - The IRQ control descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_ctrl_remove(struct irq_ctrl_desc *desc) +{ + struct xil_irq_desc *xil_dev = desc->extra; + free(xil_dev->instance); + free(desc->extra); + free(desc); + + return SUCCESS; +} + +/** + * @brief Xilinx platform specific IRQ platform ops structure + */ +const struct irq_platform_ops xil_irq_ops = { + .init = &xil_irq_ctrl_init, + .register_callback = &xil_irq_register_callback, + .unregister = &xil_irq_unregister, + .global_enable = &xil_irq_global_enable, + .global_disable = &xil_irq_global_disable, + .trigger_level_set = &xil_irq_trigger_level_set, + .enable = &xil_irq_enable, + .disable = &xil_irq_disable, + .remove = &xil_irq_ctrl_remove +}; diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/xilinx_spi.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/xilinx_spi.c new file mode 100644 index 0000000..adc3832 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/xilinx_spi.c @@ -0,0 +1,461 @@ +/***************************************************************************//** + * @file xilinx/xilinx_spi.c + * @brief Implementation of Xilinx SPI Generic Driver. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +#include +#ifdef XPAR_XSPI_NUM_INSTANCES +#include +#endif +#ifdef XPAR_XSPIPS_NUM_INSTANCES +#include +#endif + +#include "../../include/error.h" +#include "../../include/spi.h" +#include "spi_extra.h" + +#if defined(PLATFORM_ZYNQ) +#define SPI_CLK_FREQ_HZ(dev) (XPAR_PS7_SPI_ ## dev ## _SPI_CLK_FREQ_HZ) +#define SPI_NUM_INSTANCES XPAR_XSPIPS_NUM_INSTANCES +#elif defined(PLATFORM_ZYNQMP) +#define SPI_CLK_FREQ_HZ(dev) (XPAR_PSU_SPI_ ## dev ## _SPI_CLK_FREQ_HZ) +#define SPI_NUM_INSTANCES XPAR_XSPIPS_NUM_INSTANCES +#else +#define SPI_NUM_INSTANCES 0 +#endif + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Initialize the hardware SPI peripherial + * + * @param xdesc Platform specific SPI descriptor + * @param xinit Platform specific SPI init param + * @return int32_t FAILURE if the device couldn't be found or configured + */ +static int32_t spi_init_pl(struct spi_desc *desc, + const struct spi_init_param *param) +{ +#ifdef XSPI_H + int32_t ret; + struct xil_spi_desc *xdesc; + struct xil_spi_init_param *xinit; + + xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc)); + if(!xdesc) { + free(xdesc); + return FAILURE; + } + + desc->extra = xdesc; + xinit = param->extra; + xdesc->type = xinit->type; + xdesc->flags = xinit->flags; + + xdesc->instance = (XSpi*)calloc(1, sizeof(XSpi)); + if(!xdesc->instance) + goto pl_error; + + xdesc->config = XSpi_LookupConfig(param->device_id); + if(xdesc->config == NULL) + goto pl_error; + + ret = XSpi_CfgInitialize(xdesc->instance, + xdesc->config, + ((XSpi_Config*)xdesc->config) + ->BaseAddress); + if(ret != SUCCESS) + goto pl_error; + + ret = XSpi_Initialize(xdesc->instance, param->device_id); + if (ret != SUCCESS) + goto pl_error; + + ret = XSpi_SetOptions(xdesc->instance, + XSP_MASTER_OPTION | + ((desc->mode & SPI_CPOL) ? + XSP_CLK_ACTIVE_LOW_OPTION : 0) | + ((desc->mode & SPI_CPHA) ? + XSP_CLK_PHASE_1_OPTION : 0)); + if (ret != SUCCESS) + goto pl_error; + + ret = XSpi_Start(xdesc->instance); + if (ret != SUCCESS) + goto pl_error; + + XSpi_IntrGlobalDisable((XSpi *)(xdesc->instance)); + + return SUCCESS; + +pl_error: + free(xdesc->instance); + free(xdesc); +#endif + return FAILURE; +} + +/** + * @brief Initialize the hardware SPI peripherial + * + * @param xdesc Platform specific SPI descriptor + * @param xinit Platform specific SPI init param + * @return int32_t FAILURE if the device couldn't be found or configured + */ +static int32_t spi_init_ps(struct spi_desc *desc, + const struct spi_init_param *param) +{ +#ifdef XSPIPS_H + int32_t ret; + struct xil_spi_desc *xdesc; + struct xil_spi_init_param *xinit; + const uint32_t prescaler_default = XSPIPS_CLK_PRESCALE_64; + const uint32_t prescaler_min = XSPIPS_CLK_PRESCALE_4; + const uint32_t prescaler_max = XSPIPS_CLK_PRESCALE_256; + uint32_t prescaler = 0u; + uint32_t input_clock = 0u; + + xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc)); + if(!xdesc) { + free(xdesc); + return FAILURE; + } + + desc->extra = xdesc; + xinit = param->extra; + xdesc->type = xinit->type; + xdesc->flags = xinit->flags; + + xdesc->instance = (XSpiPs*)malloc(sizeof(XSpiPs)); + if(!xdesc->instance) + goto ps_error; + + xdesc->config = XSpiPs_LookupConfig(param->device_id); + if(xdesc->config == NULL) + goto ps_error; + + ret = XSpiPs_CfgInitialize(xdesc->instance, + xdesc->config, + ((XSpiPs_Config*)xdesc->config) + ->BaseAddress); + if(ret != SUCCESS) + goto ps_error; + + switch (param->device_id) { +#if (SPI_NUM_INSTANCES >= 1) + case 0: + input_clock = SPI_CLK_FREQ_HZ(0); + break; +#endif +#if (SPI_NUM_INSTANCES >= 2) + case 1: + input_clock = SPI_CLK_FREQ_HZ(1); + break; +#endif + default: + goto ps_error; + }; + + if (desc->max_speed_hz != 0u) { + uint32_t div = input_clock / desc->max_speed_hz; + uint32_t rem = input_clock % desc->max_speed_hz; + uint32_t po2 = !(div & (div - 1)) && !rem; + + // find the power of two just higher than div and + // store the exponent in prescaler + while(div) { + prescaler += 1; + div >>= 1u; + } + + // this exponent - 1 is needed because of the way + // xilinx stores it into registers + if (prescaler) + prescaler -= 1; + + // this exponent - 1 is needed when initial div was + // precisely a power of two + if (prescaler && po2) + prescaler -= 1; + + if (prescaler < prescaler_min) + prescaler = prescaler_min; + + if (prescaler > prescaler_max) + prescaler = prescaler_max; + } else + prescaler = prescaler_default; + + ret = XSpiPs_SetClkPrescaler(xdesc->instance, prescaler); + + if(ret != SUCCESS) + goto ps_error; + + return SUCCESS; + +ps_error: + free(xdesc->instance); + free(xdesc); +#endif + return FAILURE; +} + +/** + * @brief Initialize the SPI communication peripheral. + * @param desc - The SPI descriptor. + * @param param - The structure that contains the SPI parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_spi_init(struct spi_desc **desc, + const struct spi_init_param *param) +{ + int32_t ret; + enum xil_spi_type *spi_type; + + if (!param) { + return FAILURE; + } + + *desc = malloc(sizeof(**desc)); + if(! *desc) { + free(*desc); + return FAILURE; + } + + spi_type = param->extra; + + if(!spi_type) + goto init_error; + + (*desc)->max_speed_hz = param->max_speed_hz; + (*desc)->mode = param->mode; + (*desc)->bit_order = param->bit_order; + (*desc)->chip_select = param->chip_select; + + switch (*spi_type) { + case SPI_PL: + ret = spi_init_pl(*desc, param); + break; + case SPI_PS: + ret = spi_init_ps(*desc, param); + break; + + default: + goto init_error; + break; + } + + if (ret != SUCCESS) { +init_error: + free(*desc); + + return FAILURE; + } + + return ret; +} + +/** + * @brief Free the resources allocated by spi_init(). + * @param desc - The SPI descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_spi_remove(struct spi_desc *desc) +{ +#ifdef XSPI_H + int32_t ret; +#endif + struct xil_spi_desc *xdesc = NULL; + enum xil_spi_type *spi_type; + + spi_type = desc->extra; + + if(!spi_type) + return FAILURE; + + switch (*spi_type ) { + case SPI_PL: +#ifdef XSPI_H + xdesc = desc->extra; + + if(!xdesc) + return FAILURE; + + ret = XSpi_Stop((XSpi *)(xdesc->instance)); + if(ret != SUCCESS) + goto error; +#endif + break; + case SPI_PS: +#ifdef XSPIPS_H + xdesc = desc->extra; + + if(!xdesc) + return FAILURE; +#endif + break; + + /* Intended fallthrough */ +#ifdef XSPI_H +error: +#endif + default: + return FAILURE; + } + + if(xdesc) + free(xdesc->instance); + free(desc->extra); + free(desc); + + return SUCCESS; +} + +/** + * @brief Write and read data to/from SPI. + * @param desc - The SPI descriptor. + * @param data - The buffer with the transmitted/received data. + * @param bytes_number - Number of bytes to write/read. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number) +{ + int32_t ret; +#ifdef XSPI_H + uint32_t ctrl_reg; +#endif + struct xil_spi_desc *xdesc; + enum xil_spi_type *spi_type; + + ret = FAILURE; + + spi_type = desc->extra; + + if(!spi_type) + return FAILURE; + + xdesc = desc->extra; + + switch (*spi_type) { + case SPI_PL: +#ifdef XSPI_H + ret = XSpi_SetOptions(xdesc->instance, + XSP_MASTER_OPTION | + ((desc->mode & SPI_CPOL) ? + XSP_CLK_ACTIVE_LOW_OPTION : 0) | + ((desc->mode & SPI_CPHA) ? + XSP_CLK_PHASE_1_OPTION : 0)); + if (ret != SUCCESS) + goto error; + + ctrl_reg = XSpi_GetControlReg(((XSpi*)xdesc->instance)); + if (desc->bit_order == SPI_BIT_ORDER_LSB_FIRST) + ctrl_reg |= XSP_CR_LSB_MSB_FIRST_MASK; + else + ctrl_reg &= ~ XSP_CR_LSB_MSB_FIRST_MASK; + XSpi_SetControlReg(((XSpi*)xdesc->instance), ctrl_reg); + + ret = XSpi_SetSlaveSelect(xdesc->instance, + 0x01 << desc->chip_select); + if (ret != SUCCESS) + goto error; + + ret = XSpi_Transfer(xdesc->instance, + data, + data, + bytes_number); + if (ret != SUCCESS) + goto error; +#endif + break; + case SPI_PS: +#ifdef XSPIPS_H + ret = XSpiPs_SetOptions(xdesc->instance, + XSPIPS_MASTER_OPTION | + ((xdesc->flags & SPI_CS_DECODE) ? + XSPIPS_DECODE_SSELECT_OPTION : 0) | + XSPIPS_FORCE_SSELECT_OPTION | + ((desc->mode & SPI_CPOL) ? + XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) | + ((desc->mode & SPI_CPHA) ? + XSPIPS_CLK_PHASE_1_OPTION : 0)); + if (ret != SUCCESS) + goto error; + + ret = XSpiPs_SetSlaveSelect(xdesc->instance, + desc->chip_select); + if (ret != SUCCESS) + goto error; + ret = XSpiPs_PolledTransfer(xdesc->instance, + data, + data, + bytes_number); + if (ret != SUCCESS) + goto error; + ret = XSpiPs_SetSlaveSelect(xdesc->instance, SPI_DEASSERT_CURRENT_SS); + if (ret != SUCCESS) + goto error; +#endif + break; +error: + default: + return FAILURE; + } + + return ret; +} + +/** + * @brief Xilinx platform specific SPI platform ops structure + */ +const struct spi_platform_ops xil_spi_ops = { + .init = &xil_spi_init, + .write_and_read = &xil_spi_write_and_read, + .write_and_read_3wire = NULL, // Not support. + .remove = &xil_spi_remove +}; diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/xilinx_spi_pl.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/xilinx_spi_pl.c new file mode 100644 index 0000000..ed74cc8 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/platform/xilinx_spi_pl.c @@ -0,0 +1,531 @@ +/******************************************************************************* + * @file xilinx/xilinx_spi_pl.c + * @brief Driver for spi pl device using registers + * @author Mihail Chindris (mihail.chindris@analog.com) +******************************************************************************** + * Copyright 2021(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#include + +#ifdef XPAR_XSPI_NUM_INSTANCES + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include +#include +#include "spi.h" +#include "error.h" +#include "delay.h" +#include "util.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define XPS_TYPE_WRITE 0x1 +#define XPS_TYPE_READ 0x2 +#define XSP_DEFAULT_SR_VALUE 0x25 +#define XSP_DUMMY_DATA 0xFF + +/* + * Used to store current spi device configuration in order to not update it for + * each spi transaction if not needed. + */ +static struct spi_desc g_spi_desc[XPAR_XSPI_NUM_INSTANCES]; + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/* Xilinx PL spi specific data */ +struct xspi_desc { + uint32_t base_addr; + uint32_t disable_slaves_mask; + uint32_t fifo_depth; + uint8_t cs_asserted; +}; + +/* Structure used to iterate over SPI messages */ +struct msg_iter { + struct spi_msg *msgs; + uint32_t len; + uint32_t i; + uint32_t buff_i; + uint8_t is_wr; +}; + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/* Read device register */ +static inline uint32_t _read(struct xspi_desc *xdesc, uint32_t reg) +{ + return Xil_In32(xdesc->base_addr + reg); +} + +/* Write device register */ +static inline void _write(struct xspi_desc *xdesc, uint32_t reg, uint32_t val) +{ + Xil_Out32(xdesc->base_addr + reg, val); +} + +/* Update device register. Only bits set to 1 in mask will be modified */ +static inline void _wr_mask(struct xspi_desc *xdesc, uint32_t reg, + uint32_t val, uint32_t mask) +{ + uint32_t tmp; + + tmp = _read(xdesc, reg); + tmp &= ~mask; + tmp |= val & mask; + _write(xdesc, reg, tmp); +} + +/* Update spi device configuration if needed */ +static void _update_mode(struct spi_desc *desc) +{ + uint32_t val; + uint32_t mask; + + if (desc->mode == g_spi_desc[desc->device_id].mode && + desc->bit_order == g_spi_desc[desc->device_id].bit_order) + return ; + + /* Update mode */ + val = desc->mode | SPI_CPOL ? XSP_CR_CLK_POLARITY_MASK : 0; + val |= desc->mode | SPI_CPHA ? XSP_CR_CLK_PHASE_MASK : 0; + mask = XSP_CR_CLK_POLARITY_MASK | XSP_CR_CLK_PHASE_MASK; + + val |= desc->bit_order == SPI_BIT_ORDER_LSB_FIRST ? + XSP_CR_LSB_MSB_FIRST_MASK : 0; + mask |= XSP_CR_LSB_MSB_FIRST_MASK; + + _wr_mask(desc->extra, XSP_CR_OFFSET, val, mask); + g_spi_desc[desc->device_id] = *desc; +} + +/* Configure SPI PL device */ +static int32_t _xil_spi_init_dev(struct xspi_desc *xdesc) +{ + uint32_t val; + + /* Software reset */ + _write(xdesc, XSP_SRR_OFFSET, XSP_SRR_RESET_MASK); + mdelay(1); + + /* Check if success reset */ + val = _read(xdesc, XSP_SR_OFFSET); + if (val != XSP_DEFAULT_SR_VALUE) + return -ENODEV; + + /* Disable interrupts. Drivers only works with pooled mode */ + _write(xdesc, XSP_IIER_OFFSET, 0); + + /* Deasert chip selects */ + _write(xdesc, XSP_SSR_OFFSET, 0xFFFFFFFF); + + /* Get fifo depth */ + while (!(_read(xdesc, XSP_SR_OFFSET) & XSP_SR_TX_FULL_MASK)) + _write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA); + xdesc->fifo_depth = _read(xdesc, XSP_TFO_OFFSET) + 1; + + /* Configure spi device */ + val = XSP_CR_ENABLE_MASK | + XSP_CR_MANUAL_SS_MASK | + XSP_CR_TXFIFO_RESET_MASK | + XSP_CR_RXFIFO_RESET_MASK | + XSP_CR_MASTER_MODE_MASK | + XSP_CR_TRANS_INHIBIT_MASK; + + _write(xdesc, XSP_CR_OFFSET, val); + + return SUCCESS; +} + +/* Initialize spi_desc structure and device */ +static int32_t xil_spi_init_pl(struct spi_desc **desc, + const struct spi_init_param *param) +{ + struct spi_desc *ldesc; + struct xspi_desc *xdesc; + int32_t err; + XSpi_Config *cfg; + + if (!desc || !param || param->device_id >= XPAR_XSPI_NUM_INSTANCES) + return -EINVAL; + + cfg = XSpi_LookupConfig(param->device_id); + if (!cfg) + return -EINVAL; + + if (param->chip_select > cfg->NumSlaveBits) + return -EINVAL; + + ldesc = (struct spi_desc *)calloc(1, sizeof(*ldesc)); + if (!ldesc) + return -ENOMEM; + + xdesc = (struct xspi_desc *)calloc(1, sizeof(*xdesc)); + if (!xdesc) { + err = -ENOMEM; + goto error; + } + + ldesc->bit_order = param->bit_order; + ldesc->chip_select = param->chip_select; + ldesc->mode = param->mode; + xdesc->base_addr = cfg->BaseAddress; + xdesc->disable_slaves_mask = (1 << cfg->NumSlaveBits) - 1; + xdesc->cs_asserted = 0; + + err = _xil_spi_init_dev(xdesc); + if (IS_ERR_VALUE(err)) + goto error; + + ldesc->extra = xdesc; + *desc = ldesc; + + return SUCCESS; + +error: + free(xdesc); + free(ldesc); + + return err; +} + +/* Remove allocated resources */ +static int32_t xil_spi_remove_pl(struct spi_desc *desc) +{ + if (!desc) + return -EINVAL; + + free(desc->extra); + free(desc); + + return SUCCESS; +} + +/* + * Fill fifo until fifo is full or no more data available. + * Return the number of written bytes. + */ +static uint32_t _wr_fifo(struct xspi_desc *xdesc, uint8_t *data, + uint32_t len) +{ + uint32_t i; + uint32_t to_write; + uint32_t tx_available; + + tx_available = xdesc->fifo_depth - _read(xdesc, XSP_TFO_OFFSET); + to_write = min(tx_available, len); + for (i = 0; i < to_write; ++i) + if (data) + _write(xdesc, XSP_DTR_OFFSET, data[i]); + else + _write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA); + + return to_write; +} + +/* + * Read fifo until fifo is empty or no more buffer available to read into + * Returns the number of read bytes + */ +static uint32_t _rd_fifo(struct xspi_desc *xdesc, uint8_t *data, + uint32_t len) +{ + uint32_t rx_available; + uint32_t to_read; + uint32_t tmp; + uint32_t i; + + tmp = _read(xdesc, XSP_SR_OFFSET); + if (tmp & XSP_SR_RX_EMPTY_MASK) + return 0; + + rx_available = _read(xdesc, XSP_RFO_OFFSET) + 1; + to_read = min(rx_available, len); + for (i = 0; i < to_read; ++i) { + tmp = _read(xdesc, XSP_DRR_OFFSET); + if (data) + data[i] = tmp; + } + + return to_read; +} + +/* If start is 0 stop transfer, else start it. + * CS will be asserted if needed. If different CS othere than the one needed + * is asserted. Deassert it and assert correct one */ +static void _xil_spi_start_transfer(struct spi_desc *desc, uint8_t start) +{ + struct xspi_desc *xdesc; + + xdesc = desc->extra; + if (start) { + if (xdesc->cs_asserted) { + if (desc->chip_select == + g_spi_desc[desc->device_id].chip_select) + return ; + else + /* Stop transfer to start again with new CS */ + _xil_spi_start_transfer(desc, 0); + } + _write(xdesc, XSP_SSR_OFFSET, ~(1 << desc->chip_select)); + _wr_mask(xdesc, XSP_CR_OFFSET, 0, XSP_CR_TRANS_INHIBIT_MASK); + } else { + _wr_mask(xdesc, XSP_CR_OFFSET, XSP_CR_TRANS_INHIBIT_MASK, + XSP_CR_TRANS_INHIBIT_MASK); + _write(xdesc, XSP_SSR_OFFSET, xdesc->disable_slaves_mask); + } + xdesc->cs_asserted = start; +} + + +/* SPI polled transfer */ +static int32_t xil_spi_write_and_read_pl(struct spi_desc *desc, uint8_t *data, + uint16_t bytes_number) +{ + struct xspi_desc *xdesc; + uint32_t rx; + uint32_t tx; + + if (!desc || !desc->extra) + return -EINVAL; + + xdesc = desc->extra; + _update_mode(desc); + + _xil_spi_start_transfer(desc, 1); + rx = 0; + tx = 0; + while (rx < bytes_number) { + if (tx < bytes_number) + tx += _wr_fifo(xdesc, data + tx, bytes_number - tx); + rx += _rd_fifo(xdesc, data + rx, bytes_number - rx); + } + _xil_spi_start_transfer(desc, 0); + + return SUCCESS; +} + +/* Get type of message. It can be READ, WRITE or both */ +static uint32_t _get_msg_type(struct spi_msg *msg) +{ + uint32_t type; + + type = 0; + if (msg->tx_buff) + type |= XPS_TYPE_WRITE; + if (msg->rx_buff) + type |= XPS_TYPE_READ; + + return type; +} + +/* Get information based on current iterator position */ +static void _get_data(struct msg_iter *it, uint8_t **buff, uint32_t *len, + uint32_t *type) +{ + struct spi_msg *msg; + + if (it->i == it->len) { + *len = 0; + return ; + } + + msg = it->msgs + it->i; + if (it->is_wr) + *buff = msg->tx_buff; + else + *buff = msg->rx_buff; + + if (*buff) + *buff += it->buff_i; + + *len = msg->bytes_number - it->buff_i; + if (type) + *type = _get_msg_type(msg); +} + +/* + * Increment iterator position with desired length. + * If the new position has a different message type, new_type will be set to 1 + * If a CS change is needed, cs_change is set + */ +static void _increment_iter(struct msg_iter *it, uint32_t len, + uint8_t *cs_change, uint8_t *new_type) +{ + struct spi_msg *msg; + uint32_t type; + uint32_t extra_len; + + if (!len) + return ; + + *cs_change = 0; + *new_type = 0; + msg = it->msgs + it->i; + if (it->buff_i + len > msg->bytes_number) + extra_len = it->buff_i + len - msg->bytes_number; + else + extra_len = 0; + len -= extra_len; + it->buff_i += len; + if (it->buff_i == msg->bytes_number) { + type = _get_msg_type(msg); + ++it->i; + it->buff_i = 0; + if (cs_change && msg->cs_change) + *cs_change = 1; + if (new_type) + if (it->i == it->len || + type != _get_msg_type(it->msgs + it->i)) + *new_type = 1; + } + if (extra_len) + _increment_iter(it, extra_len, cs_change, new_type); +} + +/* + * SPI polling transfer of multiple messages. + */ +static int32_t xil_spi_transfer_pl(struct spi_desc *desc, struct spi_msg *msgs, + uint32_t len) + +{ + struct xspi_desc *xdesc; + uint8_t cs_change; + uint8_t new_type; + struct msg_iter rx = {.msgs = msgs, .len = len, .is_wr = 0}; + struct msg_iter tx = {.msgs = msgs, .len = len, .is_wr = 1}; + uint8_t *buff; + uint32_t bytes; + uint32_t type; + /* Bytes to increment rx when only a write transaction is executed */ + uint32_t to_inc_rx; + /* Difference between rx and tx iterators in bytes */ + uint32_t tx_advance; + /* Save bytes sent during a write loop */ + uint32_t tx_sent; + /* Used to loop if need to empty the RX FIFO */ + uint32_t loop; + + if (!desc || !desc->extra) + return -EINVAL; + + xdesc = desc->extra; + _update_mode(desc); + + tx_advance = 0; + to_inc_rx = 0; + buff = NULL; + type = 0; + do { + _xil_spi_start_transfer(desc, 1); + + tx_sent = 0; + /* Writing loop */ + do { + _get_data(&tx, &buff, &bytes, &type); + if (type & XPS_TYPE_READ) + /* + * Do not write more bytes than fifo_depth if + * they haven't been read. + */ + bytes = min(bytes, + xdesc->fifo_depth - tx_advance); + bytes = _wr_fifo(xdesc, buff, bytes); + tx_sent += bytes; + _increment_iter(&tx, bytes, &cs_change, &new_type); + tx_advance += bytes; + } while (!cs_change && !new_type && bytes); + + if (type & XPS_TYPE_READ) { + loop = 1; + /* + * Loop only when no more data to write otherwise read + * only available data. + */ + while (loop) { + if (!new_type) + loop = 0; + _get_data(&rx, &buff, &bytes, NULL); + bytes = _rd_fifo(xdesc, buff, bytes); + _increment_iter(&rx, bytes, &cs_change, &new_type); + tx_advance -= bytes; + if (loop && new_type) + break; + } + } else { + /* Clean RX FIFO if it was only a WRITE message */ + to_inc_rx += tx_sent; + if (new_type) { + /* Wait for TX to be sent */ + while (!(_read(xdesc, XSP_SR_OFFSET) & + XSP_SR_TX_EMPTY_MASK)) + ; + /* Reset fifo. Only write was performed */ + _wr_mask(xdesc, XSP_CR_OFFSET, + XSP_CR_RXFIFO_RESET_MASK, + XSP_CR_RXFIFO_RESET_MASK); + + _increment_iter(&rx, to_inc_rx, NULL, NULL); + tx_advance -= to_inc_rx; + to_inc_rx = 0; + } + } + + if ((cs_change && rx.i != len) || (!cs_change && rx.i == len)) + _xil_spi_start_transfer(desc, 0); + } while (rx.i < len); + + return SUCCESS; +} + +const struct spi_platform_ops xil_spi_reg_ops_pl = { + .init = xil_spi_init_pl, + .remove = xil_spi_remove_pl, + .write_and_read = xil_spi_write_and_read_pl, + .write_and_read_3wire = NULL, // Not support. + .transfer = xil_spi_transfer_pl +}; + +#endif // XPAR_XSPI_NUM_INSTANCES diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.c new file mode 100644 index 0000000..5cf7d2d --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.c @@ -0,0 +1,151 @@ +/***************************************************************************//** + * @file ad9361_reg.c + * @brief Implementation of AD9680 Driver. + * @author DBogdan (dragos.bogdan@analog.com) + ******************************************************************************** + * Copyright 2014-2016(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include "ad9361_reg.h" + +#include +#include +#include "../../../include/error.h" + +/***************************************************************************//** + * @brief ad9361_reg_read + *******************************************************************************/ +int32_t ad9361_reg_read(struct ad9361_reg_dev *dev, + uint16_t reg_addr, + uint8_t *reg_data) +{ + uint8_t tx_buf[2]; + uint8_t rx_buf[1]; + int32_t ret; + + tx_buf[0] = reg_addr >> 8; + tx_buf[1] = reg_addr & 0xFF; + + + ret = spi_write_and_read_3wire(dev->spi_desc, + tx_buf, rx_buf, 2, 1); + + *reg_data = rx_buf[0]; + + return ret; +} + +/***************************************************************************//** + * @brief ad9361_reg_write + *******************************************************************************/ +int32_t ad9361_reg_write(struct ad9361_reg_dev *dev, + uint16_t reg_addr, + uint8_t reg_data) +{ + uint8_t buf[3]; + + int32_t ret; + + buf[0] = 0x80 | reg_addr >> 8; + buf[1] = reg_addr & 0xFF; + buf[2] = reg_data; + + ret = spi_write_and_read_3wire(dev->spi_desc, + buf, NULL, 3, 0); + return ret; +} + +/***************************************************************************//** + * @brief ad9361_reg_init + *******************************************************************************/ +int32_t ad9361_reg_init(struct ad9361_reg_dev **device, + const struct ad9361_reg_init_param *init_param) +{ + int ret = SUCCESS; + struct ad9361_reg_dev *dev; + + dev = (struct ad9361_reg_dev *)malloc(sizeof(*dev)); + if (!dev) + return FAILURE; + + /* SPI */ + ret = spi_init(&dev->spi_desc, init_param->spi_init); + ret |= gpio_get(&dev->gpio_desc_resetb, init_param->gpio_resetb); + +// gpio_direction_output(dev->gpio_desc_resetb, 0); +// +// ad9361_reg_reset(dev); + + *device = dev; + + return ret; +} + +/** + * AD9361 Device Reset + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_reg_reset(struct ad9361_reg_dev *dev) +{ + if (dev->gpio_desc_resetb) { + gpio_set_value(dev->gpio_desc_resetb, 0); + mdelay(10); + gpio_set_value(dev->gpio_desc_resetb, 1); + mdelay(10); + return 0; + } + return 0; +} + +/***************************************************************************//** + * @brief Free the resources allocated by ad9361_reg_setup(). + * + * @param dev - The device structure. + * + * @return SUCCESS in case of success, negative error code otherwise. +*******************************************************************************/ +int32_t ad9361_reg_remove(struct ad9361_reg_dev *dev) +{ + int32_t ret; + + ret = spi_remove(dev->spi_desc); + + free(dev); + + return ret; +} diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h new file mode 100644 index 0000000..46c486b --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h @@ -0,0 +1,104 @@ +/***************************************************************************//** + * @file ad9361_reg.h + * @brief Header file of ad9361_reg Driver. + * @author DBogdan (dragos.bogdan@analog.com) + ******************************************************************************** + * Copyright 2014-2016(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *******************************************************************************/ +#ifndef ad9361_reg_H_ +#define ad9361_reg_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "../../../include/delay.h" +#include "../../../include/spi.h" +#include "../../../include/gpio.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ +struct ad9361_reg_dev { + /* SPI */ + spi_desc *spi_desc; + gpio_desc *gpio_desc_resetb; +}; + +struct ad9361_reg_init_param { + /* SPI */ + spi_init_param *spi_init; + gpio_init_param *gpio_resetb; +}; + +enum Operation_Type{ + AD9361_WRITE, + AD9361_READ, + AD9361_WAIT, + AD9361_WHEN +}; + +struct ad9361_reg_config { + int operation; + uint16_t val1; + uint16_t val2; +}; + + + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +int32_t ad9361_reg_read(struct ad9361_reg_dev *dev, + uint16_t reg_addr, + uint8_t *reg_data); + +int32_t ad9361_reg_write(struct ad9361_reg_dev *dev, + uint16_t reg_addr, + uint8_t reg_data); + +int32_t ad9361_reg_init(struct ad9361_reg_dev **device, + const struct ad9361_reg_init_param *init_param); + +int32_t ad9361_reg_reset(struct ad9361_reg_dev *dev); + +int32_t ad9361_reg_remove(struct ad9361_reg_dev *dev); + +#endif diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/axi_io.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/axi_io.h new file mode 100644 index 0000000..92b689a --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/axi_io.h @@ -0,0 +1,59 @@ +/***************************************************************************//** + * @file axi_io.h + * @brief Header file of AXI IO. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef AXI_IO_H_ +#define AXI_IO_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* AXI IO Read data */ +int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data); + +/* AXI IO Write data */ +int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data); + +#endif // AXI_IO_H_ diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/delay.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/delay.h new file mode 100644 index 0000000..7937a9d --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/delay.h @@ -0,0 +1,59 @@ +/***************************************************************************//** + * @file delay.h + * @brief Header file of Delay functions + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef DELAY_H_ +#define DELAY_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Generate microseconds delay. */ +void udelay(uint32_t usecs); + +/* Generate miliseconds delay. */ +void mdelay(uint32_t msecs); + +#endif // DELAY_H_ diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/error.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/error.h new file mode 100644 index 0000000..275b126 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/error.h @@ -0,0 +1,67 @@ +/***************************************************************************//** + * @file error.h + * @brief Error codes definition + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef ERROR_H_ +#define ERROR_H_ + +#include + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#ifdef SUCCESS +#undef SUCCESS +#endif +#define SUCCESS 0 +#ifdef FAILURE +#undef FAILURE +#endif +#define FAILURE -1 + +#ifndef __ELASTERROR +#define __ELASTERROR 2000 +#endif + +#define EOVERRUN (__ELASTERROR + 1) /* Circular buffer overrun */ + + +#define IS_ERR_VALUE(x) ((x) < 0) + +#endif // ERROR_H_ diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/gpio.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/gpio.h new file mode 100644 index 0000000..5c057cb --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/gpio.h @@ -0,0 +1,165 @@ +/***************************************************************************//** + * @file gpio.h + * @brief Header file of GPIO Interface + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef GPIO_H_ +#define GPIO_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define GPIO_OUT 0x01 +#define GPIO_IN 0x00 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @struct gpio_platform_ops + * @brief Structure holding gpio function pointers that point to the platform + * specific function + */ +struct gpio_platform_ops ; + +/** + * @struct gpio_init_param + * @brief Structure holding the parameters for GPIO initialization. + */ +typedef struct gpio_init_param { + /** GPIO number */ + int32_t number; + /** GPIO platform specific functions */ + const struct gpio_platform_ops *platform_ops; + /** GPIO extra parameters (device specific) */ + void *extra; +} gpio_init_param; + +/** + * @struct gpio_desc + * @brief Structure holding the GPIO descriptor. + */ +typedef struct gpio_desc { + /** GPIO number */ + int32_t number; + /** GPIO platform specific functions */ + const struct gpio_platform_ops *platform_ops; + /** GPIO extra parameters (device specific) */ + void *extra; +} gpio_desc; + +/** + * @enum gpio_values + * @brief Enum that holds the possible output states of a GPIO. + */ +enum gpio_values { + /** GPIO logic low */ + GPIO_LOW, + /** GPIO logic high */ + GPIO_HIGH, + /** GPIO high impedance */ + GPIO_HIGH_Z +}; + +/** + * @struct gpio_platform_ops + * @brief Structure holding gpio function pointers that point to the platform + * specific function + */ +struct gpio_platform_ops { + /** gpio initialization function pointer */ + int32_t (*gpio_ops_get)(struct gpio_desc **, const struct gpio_init_param *); + /** gpio optional descriptor function pointer */ + int32_t (*gpio_ops_get_optional)(struct gpio_desc **, + const struct gpio_init_param *); + /** gpio remove function pointer */ + int32_t (*gpio_ops_remove)(struct gpio_desc *); + /** gpio direction input function pointer */ + int32_t (*gpio_ops_direction_input)(struct gpio_desc *); + /** gpio direction output function pointer */ + int32_t (*gpio_ops_direction_output)(struct gpio_desc *, uint8_t); + /** gpio get direction function pointer */ + int32_t (*gpio_ops_get_direction)(struct gpio_desc *, uint8_t *); + /** gpio set value function pointer */ + int32_t (*gpio_ops_set_value)(struct gpio_desc *, uint8_t); + /** gpio get value function pointer */ + int32_t (*gpio_ops_get_value)(struct gpio_desc *, uint8_t *); +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Obtain the GPIO decriptor. */ +int32_t gpio_get(struct gpio_desc **desc, + const struct gpio_init_param *param); + +/* Obtain optional GPIO descriptor. */ +int32_t gpio_get_optional(struct gpio_desc **desc, + const struct gpio_init_param *param); + +/* Free the resources allocated by gpio_get() */ +int32_t gpio_remove(struct gpio_desc *desc); + +/* Enable the input direction of the specified GPIO. */ +int32_t gpio_direction_input(struct gpio_desc *desc); + +/* Enable the output direction of the specified GPIO. */ +int32_t gpio_direction_output(struct gpio_desc *desc, + uint8_t value); + +/* Get the direction of the specified GPIO. */ +int32_t gpio_get_direction(struct gpio_desc *desc, + uint8_t *direction); + +/* Set the value of the specified GPIO. */ +int32_t gpio_set_value(struct gpio_desc *desc, + uint8_t value); + +/* Get the value of the specified GPIO. */ +int32_t gpio_get_value(struct gpio_desc *desc, + uint8_t *value); + +#endif // GPIO_H_ diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/irq.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/irq.h new file mode 100644 index 0000000..7db97e9 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/irq.h @@ -0,0 +1,188 @@ +/***************************************************************************//** + * @file irq.h + * @brief Header file of IRQ interface. + * @author Cristian Pop (cristian.pop@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef IRQ_H_ +#define IRQ_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum irq_uart_event_e + * @brief Possible events for uart interrupt + */ +enum irq_uart_event_e { + /** Write operation finalized */ + IRQ_WRITE_DONE, + /** Read operation finalized */ + IRQ_READ_DONE, + /** An error occurred */ + IRQ_ERROR +}; + +enum irq_trig_level { + IRQ_LEVEL_LOW, + IRQ_LEVEL_HIGH, + IRQ_EDGE_FALLING, + IRQ_EDGE_RISING, + IRQ_EDGE_BOTH +}; + +/** + * @struct irq_platform_ops + * @brief Structure holding IRQ function pointers that point to the platform + * specific function + */ +struct irq_platform_ops ; + +/** + * @struct irq_init_param + * @brief Structure holding the initial parameters for Interrupt Request. + */ +struct irq_init_param { + /** Interrupt request controller ID. */ + uint32_t irq_ctrl_id; + /** Platform specific IRQ platform ops structure. */ + const struct irq_platform_ops *platform_ops; + /** IRQ extra parameters (device specific) */ + void *extra; +}; + +/** + * @struct irq_desc + * @brief Structure for Interrupt Request descriptor. + */ +struct irq_ctrl_desc { + /** Interrupt request controller ID. */ + uint32_t irq_ctrl_id; + /** Platform specific IRQ platform ops structure. */ + const struct irq_platform_ops *platform_ops; + /** IRQ extra parameters (device specific) */ + void *extra; +}; + +/** + * @struct callback_desc + * @brief Structure describing a callback to be registered + */ +struct callback_desc { + /** + * Callback to be called when the event an event occurs + * @param ctx - Same as \ref callback_desc.ctx + * @param event - Event that generated the callback + * @param extra - Platform specific data + */ + void (*callback)(void *ctx, uint32_t event, void *extra); + /** Parameter to be passed when the callback is called */ + void *ctx; + /** Platform specific configuration for a callback */ + void *config; +}; + +/** + * @struct irq_platform_ops + * @brief Structure holding IRQ function pointers that point to the platform + * specific function + */ +struct irq_platform_ops { + /** Initialize a interrupt controller peripheral. */ + int32_t (*init)(struct irq_ctrl_desc **desc, + const struct irq_init_param *param); + /** Register a callback to handle the irq events */ + int32_t (*register_callback)(struct irq_ctrl_desc *desc, uint32_t irq_id, + struct callback_desc *callback_desc); + /** Unregisters a generic IRQ handling function */ + int32_t (*unregister)(struct irq_ctrl_desc *desc, uint32_t irq_id); + /** Global interrupt enable */ + int32_t (*global_enable)(struct irq_ctrl_desc *desc); + /** Global interrupt disable */ + int32_t (*global_disable)(struct irq_ctrl_desc *desc); + /** Set interrupt trigger level. */ + int32_t (*trigger_level_set)(struct irq_ctrl_desc *desc, uint32_t irq_id, + enum irq_trig_level trig); + /** Enable specific interrupt */ + int32_t (*enable)(struct irq_ctrl_desc *desc, uint32_t irq_id); + /** Disable specific interrupt */ + int32_t (*disable)(struct irq_ctrl_desc *desc, uint32_t irq_id); + /** IRQ remove function pointer */ + int32_t (*remove)(struct irq_ctrl_desc *desc); +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Initialize a interrupt controller peripheral. */ +int32_t irq_ctrl_init(struct irq_ctrl_desc **desc, + const struct irq_init_param *param); + +/* Free the resources allocated by irq_ctrl_init(). */ +int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc); + +/* Register a callback to handle the irq events */ +int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id, + struct callback_desc *callback_desc); + +/* Unregisters a generic IRQ handling function */ +int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id); + +/* Global interrupt enable */ +int32_t irq_global_enable(struct irq_ctrl_desc *desc); + +/* Global interrupt disable */ +int32_t irq_global_disable(struct irq_ctrl_desc *desc); + +/* Set interrupt trigger level. */ +int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id, + enum irq_trig_level trig); + +/* Enable specific interrupt */ +int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id); + +/* Disable specific interrupt */ +int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id); + +#endif // IRQ_H_ diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/spi.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/spi.h new file mode 100644 index 0000000..0e9b8e0 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/spi.h @@ -0,0 +1,194 @@ +/***************************************************************************//** + * @file spi.h + * @brief Header file of SPI Interface + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef SPI_H_ +#define SPI_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define SPI_CPHA 0x01 +#define SPI_CPOL 0x02 +#define SPI_3WIRE 0x04 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum spi_mode + * @brief SPI configuration for clock phase and polarity. + */ +typedef enum spi_mode { + /** Data on rising, shift out on falling */ + SPI_MODE_0 = (0 | 0), + /** Data on falling, shift out on rising */ + SPI_MODE_1 = (0 | SPI_CPHA), + /** Data on falling, shift out on rising */ + SPI_MODE_2 = (SPI_CPOL | 0), + /** Data on rising, shift out on falling */ + SPI_MODE_3 = (SPI_CPOL | SPI_CPHA), + /** Data on rising, shift out on falling */ + SPI_MODE_4 = SPI_3WIRE +} spi_mode; + +/** + * @enum spi_bit_order + * @brief SPI configuration for bit order (MSB/LSB). + */ +typedef enum spi_bit_order { + /** Most-significant bit (MSB) first */ + SPI_BIT_ORDER_MSB_FIRST = 0, + /** Least-significant bit (LSB) first */ + SPI_BIT_ORDER_LSB_FIRST = 1, +} spi_bit_order; + +/** + * @struct spi_msg_list + * @brief List item describing a SPI transfer + */ +struct spi_msg { + /** Buffer with data to send. If NULL, 0x00 will be sent */ + uint8_t *tx_buff; + /** Buffer where to store data. If NULL, incoming data won't be saved */ + uint8_t *rx_buff; + /** Length of buffers. Must have equal size. */ + uint32_t bytes_number; + /** If set, CS will be deasserted after the transfer */ + uint8_t cs_change; +}; + +/** + * @struct spi_platform_ops + * @brief Structure holding SPI function pointers that point to the platform + * specific function + */ +struct spi_platform_ops ; + +/** + * @struct spi_init_param + * @brief Structure holding the parameters for SPI initialization + */ +typedef struct spi_init_param { + /** Device ID */ + uint32_t device_id; + /** maximum transfer speed */ + uint32_t max_speed_hz; + /** SPI chip select */ + uint8_t chip_select; + /** SPI mode */ + enum spi_mode mode; + /** SPI bit order */ + enum spi_bit_order bit_order; + const struct spi_platform_ops *platform_ops; + /** SPI extra parameters (device specific) */ + void *extra; +} spi_init_param; + +/** + * @struct spi_desc + * @brief Structure holding SPI descriptor. + */ +typedef struct spi_desc { + /** Device ID */ + uint32_t device_id; + /** maximum transfer speed */ + uint32_t max_speed_hz; + /** SPI chip select */ + uint8_t chip_select; + /** SPI mode */ + enum spi_mode mode; + /** SPI bit order */ + enum spi_bit_order bit_order; + const struct spi_platform_ops *platform_ops; + /** SPI extra parameters (device specific) */ + void *extra; +} spi_desc; + +/** + * @struct spi_platform_ops + * @brief Structure holding SPI function pointers that point to the platform + * specific function + */ +struct spi_platform_ops { + /** SPI initialization function pointer */ + int32_t (*init)(struct spi_desc **, const struct spi_init_param *); + /** SPI write/read function pointer */ + int32_t (*write_and_read)(struct spi_desc *, uint8_t *, uint16_t); + /** SPI write function pointer */ + int32_t (*write_and_read_3wire)(struct spi_desc *, uint8_t *,uint8_t *,uint16_t, uint16_t); + /** Iterate over the spi_msg array and send all messages at once */ + int32_t (*transfer)(struct spi_desc *, struct spi_msg *, uint32_t); + /** SPI remove function pointer */ + int32_t (*remove)(struct spi_desc *); +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Initialize the SPI communication peripheral. */ +int32_t spi_init(struct spi_desc **desc, + const struct spi_init_param *param); + +/* Free the resources allocated by spi_init(). */ +int32_t spi_remove(struct spi_desc *desc); + +/* Write and read data to/from SPI. */ +int32_t spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number); +int32_t spi_write_and_read_3wire(struct spi_desc *desc, + uint8_t *write_data, + uint8_t *read_data, + uint16_t write_bytes_number, + uint16_t read_bytes_number); + +/* Iterate over the spi_msg array and send all messages at once */ +int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len); + + +#endif // SPI_H_ diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/util.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/util.h new file mode 100644 index 0000000..4255cd9 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/include/util.h @@ -0,0 +1,165 @@ +/***************************************************************************//** + * @file util.h + * @brief Implementation of utility functions. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef UTIL_H_ +#define UTIL_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#define BIT(x) (1 << (x)) + +#define ARRAY_SIZE(x) \ + (sizeof(x) / sizeof((x)[0])) + +#define DIV_ROUND_UP(x,y) \ + (((x) + (y) - 1) / (y)) +#define DIV_ROUND_CLOSEST(x, y) \ + (((x) + (y) / 2) / (y)) +#define DIV_ROUND_CLOSEST_ULL(x, y) \ + DIV_ROUND_CLOSEST(x, y) + +#define min(x, y) \ + (((x) < (y)) ? (x) : (y)) +#define min_t(type, x, y) \ + (type)min((type)(x), (type)(y)) + +#define max(x, y) \ + (((x) > (y)) ? (x) : (y)) +#define max_t(type, x, y) \ + (type)max((type)(x), (type)(y)) + +#define clamp(val, min_val, max_val) \ + (max(min((val), (max_val)), (min_val))) +#define clamp_t(type, val, min_val, max_val) \ + (type)clamp((type)(val), (type)(min_val), (type)(max_val)) + +#define swap(x, y) \ + {typeof(x) _tmp_ = (x); (x) = (y); (y) = _tmp_;} + +#define round_up(x,y) \ + (((x)+(y)-1)/(y)) + +#define BITS_PER_LONG 32 + +#define GENMASK(h, l) ({ \ + uint32_t t = (uint32_t)(~0UL); \ + t = t << (BITS_PER_LONG - (h - l + 1)); \ + t = t >> (BITS_PER_LONG - (h + 1)); \ + t; \ +}) + +#define bswap_constant_32(x) \ + ((((x) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | (((x) & 0x000000ff) << 24)) + +#define bswap_constant_16(x) ((((x) & (uint16_t)0xff00) >> 8) | \ + (((x) & (uint16_t)0x00ff) << 8)) + +#define bit_swap_constant_8(x) \ + ((((x) & 0x80) >> 7) | \ + (((x) & 0x40) >> 5) | \ + (((x) & 0x20) >> 3) | \ + (((x) & 0x10) >> 1) | \ + (((x) & 0x08) << 1) | \ + (((x) & 0x04) << 3) | \ + (((x) & 0x02) << 5) | \ + (((x) & 0x01) << 7)) + +#define U16_MAX ((uint16_t)~0U) +#define S16_MAX ((int16_t)(U16_MAX>>1)) + +#define DIV_U64(x, y) (x / y) + +#define UNUSED_PARAM(x) ((void)x) + +#define shift_right(x, s) ((x) < 0 ? -(-(x) >> (s)) : (x) >> (s)) + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ +/* Find first set bit in word. */ +uint32_t find_first_set_bit(uint32_t word); +/* Find last set bit in word. */ +uint32_t find_last_set_bit(uint32_t word); +/* Locate the closest element in an array. */ +uint32_t find_closest(int32_t val, + const int32_t *array, + uint32_t size); +/* Shift the value and apply the specified mask. */ +uint32_t field_prep(uint32_t mask, uint32_t val); +/* Get a field specified by a mask from a word. */ +uint32_t field_get(uint32_t mask, uint32_t word); +/* Log base 2 of the given number. */ +int32_t log_base_2(uint32_t x); +/* Find greatest common divisor of the given two numbers. */ +uint32_t greatest_common_divisor(uint32_t a, + uint32_t b); +/* Calculate best rational approximation for a given fraction. */ +void rational_best_approximation(uint32_t given_numerator, + uint32_t given_denominator, + uint32_t max_numerator, + uint32_t max_denominator, + uint32_t *best_numerator, + uint32_t *best_denominator); +/* Calculate the number of set bits. */ +uint32_t hweight8(uint32_t word); +/* Calculate the quotient and the remainder of an integer division. */ +uint64_t do_div(uint64_t* n, + uint64_t base); +/* Unsigned 64bit divide with 64bit divisor and remainder */ +uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor, + uint64_t *remainder); +/* Unsigned 64bit divide with 32bit divisor with remainder */ +uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder); +int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder); +/* Unsigned 64bit divide with 32bit divisor */ +uint64_t div_u64(uint64_t dividend, uint32_t divisor); +int64_t div_s64(int64_t dividend, int32_t divisor); +/* Converts from string to int32_t */ +int32_t str_to_int32(const char *str); +/* Converts from string to uint32_t */ +uint32_t srt_to_uint32(const char *str); +#endif // UTIL_H_ + diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/util/util.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/util/util.c new file mode 100644 index 0000000..58c6a83 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/adi_noos/util/util.c @@ -0,0 +1,283 @@ +/***************************************************************************//** + * @file util.c + * @brief Implementation of utility functions. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include "errno.h" +#include "../include/util.h" + +/******************************************************************************/ +/************************** Functions Implementation **************************/ +/******************************************************************************/ + +/** + * Find first set bit in word. + */ +uint32_t find_first_set_bit(uint32_t word) +{ + uint32_t first_set_bit = 0; + + while (word) { + if (word & 0x1) + return first_set_bit; + word >>= 1; + first_set_bit ++; + } + + return 32; +} + +/** + * Find last set bit in word. + */ +uint32_t find_last_set_bit(uint32_t word) +{ + uint32_t bit = 0; + uint32_t last_set_bit = 32; + + while (word) { + if (word & 0x1) + last_set_bit = bit; + word >>= 1; + bit ++; + } + + return last_set_bit; +} + +/** + * Locate the closest element in an array. + */ +uint32_t find_closest(int32_t val, + const int32_t *array, + uint32_t size) +{ + int32_t diff = abs(array[0] - val); + uint32_t ret = 0; + uint32_t i; + + for (i = 1; i < size; i++) { + if (abs(array[i] - val) < diff) { + diff = abs(array[i] - val); + ret = i; + } + } + + return ret; +} + +/** + * Shift the value and apply the specified mask. + */ +uint32_t field_prep(uint32_t mask, uint32_t val) +{ + return (val << find_first_set_bit(mask)) & mask; +} + +/** + * Get a field specified by a mask from a word. + */ +uint32_t field_get(uint32_t mask, uint32_t word) +{ + return (word & mask) >> find_first_set_bit(mask); +} + +/** + * Log base 2 of the given number. + */ +int32_t log_base_2(uint32_t x) +{ + return find_last_set_bit(x); +} + +/** + * Find greatest common divisor of the given two numbers. + */ +uint32_t greatest_common_divisor(uint32_t a, + uint32_t b) +{ + uint32_t div; + uint32_t common_div = 1; + + if ((a == 0) || (b == 0)) + return max(a, b); + + for (div = 1; (div <= a) && (div <= b); div++) + if (!(a % div) && !(b % div)) + common_div = div; + + return common_div; +} + +/** + * Calculate best rational approximation for a given fraction. + */ +void rational_best_approximation(uint32_t given_numerator, + uint32_t given_denominator, + uint32_t max_numerator, + uint32_t max_denominator, + uint32_t *best_numerator, + uint32_t *best_denominator) +{ + uint32_t gcd; + + gcd = greatest_common_divisor(given_numerator, given_denominator); + + *best_numerator = given_numerator / gcd; + *best_denominator = given_denominator / gcd; + + if ((*best_numerator > max_numerator) || + (*best_denominator > max_denominator)) { + *best_numerator = 0; + *best_denominator = 0; + } +} + +/** + * Calculate the number of set bits. + */ +uint32_t hweight8(uint32_t word) +{ + uint32_t count = 0; + + while (word) { + if (word & 0x1) + count++; + word >>= 1; + } + + return count; +} + +/** + * Calculate the quotient and the remainder of an integer division. + */ +uint64_t do_div(uint64_t* n, + uint64_t base) +{ + uint64_t mod = 0; + + mod = *n % base; + *n = *n / base; + + return mod; +} + +/** + * Unsigned 64bit divide with 64bit divisor and remainder + */ +uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor, uint64_t *remainder) +{ + *remainder = dividend % divisor; + + return dividend / divisor; +} + +/** + * Unsigned 64bit divide with 32bit divisor with remainder + */ +uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) +{ + *remainder = do_div(÷nd, divisor); + + return dividend; +} + +/** + * Signed 64bit divide with 32bit divisor with remainder + */ +int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder) +{ + *remainder = dividend % divisor; + return dividend / divisor; +} + +/** + * Unsigned 64bit divide with 32bit divisor + */ +uint64_t div_u64(uint64_t dividend, uint32_t divisor) +{ + uint32_t remainder; + + return div_u64_rem(dividend, divisor, &remainder); +} + +/** + * Signed 64bit divide with 32bit divisor + */ +int64_t div_s64(int64_t dividend, int32_t divisor) +{ + int32_t remainder; + return div_s64_rem(dividend, divisor, &remainder); +} + +/** + * Converts from string to int32_t + * @param *str + * @return int32_t + */ +int32_t str_to_int32(const char *str) +{ + char *end; + int32_t value = strtol(str, &end, 0); + + if (end == str) + return -EINVAL; + else + return value; +} + +/** + * Converts from string to uint32_t + * @param *str + * @return uint32_t + */ +uint32_t srt_to_uint32(const char *str) +{ + char *end; + uint32_t value = strtoul(str, &end, 0); + + if (end == str) + return -EINVAL; + else + return value; +} diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/app_config.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/app_config.h new file mode 100644 index 0000000..d8ec385 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/app_config.h @@ -0,0 +1,55 @@ +/***************************************************************************//** + * @file app_config.h + * @brief Config file of AD9361/API Driver. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2015(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef CONFIG_H_ +#define CONFIG_H_ + +#define XILINX_PLATFORM +#define SPI_INTERFACE_SPI_ENGINE + +#define HAVE_SPLIT_GAIN_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/ +#define HAVE_TDD_SYNTH_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/ + +#define AD9361_DEVICE 1 /* set it 1 if AD9361 device is used, 0 otherwise */ +#define AD9364_DEVICE 0 /* set it 1 if AD9364 device is used, 0 otherwise */ +#define AD9363A_DEVICE 0 /* set it 1 if AD9363A device is used, 0 otherwise */ + +#define HAVE_VERBOSE_MESSAGES /* Recommended during development prints errors and warnings */ +//#define HAVE_DEBUG_MESSAGES /* For Debug purposes only */ + +#endif diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/dev_profile/ad9361_reg_profile.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/dev_profile/ad9361_reg_profile.c new file mode 100644 index 0000000..f35c161 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/dev_profile/ad9361_reg_profile.c @@ -0,0 +1,1730 @@ +#include "dev_profile.h" +#include "../app_config.h" +#include "../adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h" + +#define TIMEOUT_TH 2000 + +// ad9361-1 +static spi_init_param ad9361_1_reg_spi_init = { + .device_id = SPI_DEVICE_ID, + .max_speed_hz = SPI_ENGINE_MAX_SPEED, + .mode = SPI_MODE_1, + .chip_select = SPI_CS_AD9361_1, + .platform_ops = SPI_OPS, + .extra = SPI_PARAM +}; + +static gpio_init_param ad9361_1_reg_gpio_resetb_init = { + .number = AD9361_1_RESET_B, + .platform_ops = GPIO_OPS, + .extra = GPIO_PARAM +}; +struct ad9361_reg_init_param ad9361_1_reg_default_init_param = { + /* SPI */ + .spi_init = &ad9361_1_reg_spi_init, + .gpio_resetb = &ad9361_1_reg_gpio_resetb_init +}; + +// ad9361-2 +static spi_init_param ad9361_2_reg_spi_init = { + .device_id = SPI_DEVICE_ID, + .max_speed_hz = SPI_ENGINE_MAX_SPEED, + .mode = SPI_MODE_1, + .chip_select = SPI_CS_AD9361_2, + .platform_ops = SPI_OPS, + .extra = SPI_PARAM +}; + +static gpio_init_param ad9361_2_reg_gpio_resetb_init = { + .number = AD9361_2_RESET_B, + .platform_ops = GPIO_OPS, + .extra = GPIO_PARAM +}; +struct ad9361_reg_init_param ad9361_2_reg_default_init_param = { + /* SPI */ + .spi_init = &ad9361_2_reg_spi_init, + .gpio_resetb = &ad9361_2_reg_gpio_resetb_init +}; + +uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){ + int32_t status = 0; + uint8_t value = 0; + int32_t time_out_cnt = 0; + +//************************************************************ +// AD9361 R2 Auto Generated Initialization Script: This script was +// generated using the AD9361 Customer software Version 2.1.3 +//************************************************************ +// Profile: Custom +// REFCLK_IN: 25.000 MHz + + + status = ad9361_reg_write(dev, 0x03DF, 0x01); // Required for proper operation + status = ad9361_reg_write(dev, 0x02A6, 0x0E); // Enable Master Bias + status = ad9361_reg_write(dev, 0x02A8, 0x0E); // Set Bandgap Trim + status = ad9361_reg_write(dev, 0x02AB, 0x07); // Set RF PLL reflclk scale to REFCLK * 2 + status = ad9361_reg_write(dev, 0x02AC, 0xFF); // Set RF PLL reflclk scale to REFCLK * 2 + status = ad9361_reg_write(dev, 0x0009, 0x17); // Enable Clocks + mdelay(20) ;// waits 20 ms + +//************************************************************ +// Set BBPLL Frequency: 1152.000000 +//************************************************************ + status = ad9361_reg_write(dev, 0x0045, 0x03); // Set BBPLL reflclk scale to REFCLK * 2 + status = ad9361_reg_write(dev, 0x0046, 0x03); // Set BBPLL Loop Filter Charge Pump current + status = ad9361_reg_write(dev, 0x0048, 0xE8); // Set BBPLL Loop Filter C1, R1 + status = ad9361_reg_write(dev, 0x0049, 0x5B); // Set BBPLL Loop Filter R2, C2, C1 + status = ad9361_reg_write(dev, 0x004A, 0x35); // Set BBPLL Loop Filter C3,R2 + status = ad9361_reg_write(dev, 0x004B, 0xE0); // Allow calibration to occur and set cal count to 1024 for max accuracy + status = ad9361_reg_write(dev, 0x004E, 0x10); // Set calibration clock to REFCLK/4 for more accuracy + status = ad9361_reg_write(dev, 0x0043, 0x66); // BBPLL Freq Word (Fractional[7:0]) + status = ad9361_reg_write(dev, 0x0042, 0x46); // BBPLL Freq Word (Fractional[15:8]) + status = ad9361_reg_write(dev, 0x0041, 0x01); // BBPLL Freq Word (Fractional[23:16]) + status = ad9361_reg_write(dev, 0x0044, 0x17); // BBPLL Freq Word (Integer[7:0]) + status = ad9361_reg_write(dev, 0x003F, 0x05); // Start BBPLL Calibration + status = ad9361_reg_write(dev, 0x003F, 0x01); // Clear BBPLL start calibration bit + status = ad9361_reg_write(dev, 0x004C, 0x86); // Increase BBPLL KV and phase margin + status = ad9361_reg_write(dev, 0x004D, 0x01); // Increase BBPLL KV and phase margin + status = ad9361_reg_write(dev, 0x004D, 0x05); // Increase BBPLL KV and phase margin + + // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 276.480 us (Done when 0x05E[7]==1) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x005E, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x80) != 0x80 && time_out_cnt <= TIMEOUT_TH); + + + status = ad9361_reg_write(dev, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels + status = ad9361_reg_write(dev, 0x0003, 0xE5); // Setup Rx Digital Filters/ Channels + status = ad9361_reg_write(dev, 0x0004, 0x03); // Select Rx input pin(A,B,C)/ Tx out pin (A,B) + status = ad9361_reg_write(dev, 0x000A, 0x12); // Set BBPLL post divide rate + +//************************************************************ +// Program Rx FIR: C:\Users\josh\Desktop\Config\rx64.txt +//************************************************************ + status = ad9361_reg_write(dev, 0x00F5, 0x9A); // Enable clock to Rx FIR Filter + status = ad9361_reg_write(dev, 0x00F6, 0x02); // Write Filter Gain setting + status = ad9361_reg_write(dev, 0x00F0, 0x00); // Write FIR coefficient address + status = ad9361_reg_write(dev, 0x00F1, 0x00); // Write FIR coefficient data[7:0] + status = ad9361_reg_write(dev, 0x00F2, 0x00); // Write FIR coefficient data[15:8] + status = ad9361_reg_write(dev, 0x00F5, 0x9E); // Set Write EN to push data into FIR filter register map + status = ad9361_reg_write(dev, 0x00F4, 0x00); // Dummy Write to Read only register to delay ~1us + status = ad9361_reg_write(dev, 0x00F4, 0x00); // Dummy Write to Read only register to delay ~1us + status = ad9361_reg_write(dev, 0x00F0, 0x01); + status = ad9361_reg_write(dev, 0x00F1, 0xB6); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x02); + status = ad9361_reg_write(dev, 0x00F1, 0xA5); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x03); + status = ad9361_reg_write(dev, 0x00F1, 0xEA); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x04); + status = ad9361_reg_write(dev, 0x00F1, 0x61); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x05); + status = ad9361_reg_write(dev, 0x00F1, 0xA3); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x06); + status = ad9361_reg_write(dev, 0x00F1, 0x4D); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x07); + status = ad9361_reg_write(dev, 0x00F1, 0x77); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x08); + status = ad9361_reg_write(dev, 0x00F1, 0xD5); + status = ad9361_reg_write(dev, 0x00F2, 0xFE); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x09); + status = ad9361_reg_write(dev, 0x00F1, 0x38); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x0A); + status = ad9361_reg_write(dev, 0x00F1, 0xA5); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x0B); + status = ad9361_reg_write(dev, 0x00F1, 0xF8); + status = ad9361_reg_write(dev, 0x00F2, 0x01); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x0C); + status = ad9361_reg_write(dev, 0x00F1, 0xAD); + status = ad9361_reg_write(dev, 0x00F2, 0x01); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x0D); + status = ad9361_reg_write(dev, 0x00F1, 0x75); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x0E); + status = ad9361_reg_write(dev, 0x00F1, 0xFD); + status = ad9361_reg_write(dev, 0x00F2, 0xFC); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x0F); + status = ad9361_reg_write(dev, 0x00F1, 0xD8); + status = ad9361_reg_write(dev, 0x00F2, 0xFC); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x10); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x11); + status = ad9361_reg_write(dev, 0x00F1, 0x3A); + status = ad9361_reg_write(dev, 0x00F2, 0x04); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x12); + status = ad9361_reg_write(dev, 0x00F1, 0x6B); + status = ad9361_reg_write(dev, 0x00F2, 0x05); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x13); + status = ad9361_reg_write(dev, 0x00F1, 0x51); + status = ad9361_reg_write(dev, 0x00F2, 0x01); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x14); + status = ad9361_reg_write(dev, 0x00F1, 0x80); + status = ad9361_reg_write(dev, 0x00F2, 0xFA); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x15); + status = ad9361_reg_write(dev, 0x00F1, 0x34); + status = ad9361_reg_write(dev, 0x00F2, 0xF7); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x16); + status = ad9361_reg_write(dev, 0x00F1, 0x08); + status = ad9361_reg_write(dev, 0x00F2, 0xFC); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x17); + status = ad9361_reg_write(dev, 0x00F1, 0xB2); + status = ad9361_reg_write(dev, 0x00F2, 0x06); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x18); + status = ad9361_reg_write(dev, 0x00F1, 0x1A); + status = ad9361_reg_write(dev, 0x00F2, 0x0E); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x19); + status = ad9361_reg_write(dev, 0x00F1, 0x44); + status = ad9361_reg_write(dev, 0x00F2, 0x09); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x1A); + status = ad9361_reg_write(dev, 0x00F1, 0x54); + status = ad9361_reg_write(dev, 0x00F2, 0xF8); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x1B); + status = ad9361_reg_write(dev, 0x00F1, 0xD1); + status = ad9361_reg_write(dev, 0x00F2, 0xE7); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x1C); + status = ad9361_reg_write(dev, 0x00F1, 0xC2); + status = ad9361_reg_write(dev, 0x00F2, 0xE9); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x1D); + status = ad9361_reg_write(dev, 0x00F1, 0x4F); + status = ad9361_reg_write(dev, 0x00F2, 0x08); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x1E); + status = ad9361_reg_write(dev, 0x00F1, 0xB2); + status = ad9361_reg_write(dev, 0x00F2, 0x3B); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x1F); + status = ad9361_reg_write(dev, 0x00F1, 0x2A); + status = ad9361_reg_write(dev, 0x00F2, 0x6C); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x20); + status = ad9361_reg_write(dev, 0x00F1, 0xFF); + status = ad9361_reg_write(dev, 0x00F2, 0x7F); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x21); + status = ad9361_reg_write(dev, 0x00F1, 0x2A); + status = ad9361_reg_write(dev, 0x00F2, 0x6C); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x22); + status = ad9361_reg_write(dev, 0x00F1, 0xB2); + status = ad9361_reg_write(dev, 0x00F2, 0x3B); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x23); + status = ad9361_reg_write(dev, 0x00F1, 0x4F); + status = ad9361_reg_write(dev, 0x00F2, 0x08); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x24); + status = ad9361_reg_write(dev, 0x00F1, 0xC2); + status = ad9361_reg_write(dev, 0x00F2, 0xE9); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x25); + status = ad9361_reg_write(dev, 0x00F1, 0xD1); + status = ad9361_reg_write(dev, 0x00F2, 0xE7); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x26); + status = ad9361_reg_write(dev, 0x00F1, 0x54); + status = ad9361_reg_write(dev, 0x00F2, 0xF8); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x27); + status = ad9361_reg_write(dev, 0x00F1, 0x44); + status = ad9361_reg_write(dev, 0x00F2, 0x09); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x28); + status = ad9361_reg_write(dev, 0x00F1, 0x1A); + status = ad9361_reg_write(dev, 0x00F2, 0x0E); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x29); + status = ad9361_reg_write(dev, 0x00F1, 0xB2); + status = ad9361_reg_write(dev, 0x00F2, 0x06); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x2A); + status = ad9361_reg_write(dev, 0x00F1, 0x08); + status = ad9361_reg_write(dev, 0x00F2, 0xFC); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x2B); + status = ad9361_reg_write(dev, 0x00F1, 0x34); + status = ad9361_reg_write(dev, 0x00F2, 0xF7); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x2C); + status = ad9361_reg_write(dev, 0x00F1, 0x80); + status = ad9361_reg_write(dev, 0x00F2, 0xFA); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x2D); + status = ad9361_reg_write(dev, 0x00F1, 0x51); + status = ad9361_reg_write(dev, 0x00F2, 0x01); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x2E); + status = ad9361_reg_write(dev, 0x00F1, 0x6B); + status = ad9361_reg_write(dev, 0x00F2, 0x05); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x2F); + status = ad9361_reg_write(dev, 0x00F1, 0x3A); + status = ad9361_reg_write(dev, 0x00F2, 0x04); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x30); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x31); + status = ad9361_reg_write(dev, 0x00F1, 0xD8); + status = ad9361_reg_write(dev, 0x00F2, 0xFC); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x32); + status = ad9361_reg_write(dev, 0x00F1, 0xFD); + status = ad9361_reg_write(dev, 0x00F2, 0xFC); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x33); + status = ad9361_reg_write(dev, 0x00F1, 0x75); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x34); + status = ad9361_reg_write(dev, 0x00F1, 0xAD); + status = ad9361_reg_write(dev, 0x00F2, 0x01); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x35); + status = ad9361_reg_write(dev, 0x00F1, 0xF8); + status = ad9361_reg_write(dev, 0x00F2, 0x01); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x36); + status = ad9361_reg_write(dev, 0x00F1, 0xA5); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x37); + status = ad9361_reg_write(dev, 0x00F1, 0x38); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x38); + status = ad9361_reg_write(dev, 0x00F1, 0xD5); + status = ad9361_reg_write(dev, 0x00F2, 0xFE); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x39); + status = ad9361_reg_write(dev, 0x00F1, 0x77); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x3A); + status = ad9361_reg_write(dev, 0x00F1, 0x4D); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x3B); + status = ad9361_reg_write(dev, 0x00F1, 0xA3); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x3C); + status = ad9361_reg_write(dev, 0x00F1, 0x61); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x3D); + status = ad9361_reg_write(dev, 0x00F1, 0xEA); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x3E); + status = ad9361_reg_write(dev, 0x00F1, 0xA5); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x3F); + status = ad9361_reg_write(dev, 0x00F1, 0xB6); + status = ad9361_reg_write(dev, 0x00F2, 0xFF); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x40); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x41); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x42); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x43); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x44); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x45); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x46); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x47); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x48); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x49); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x4A); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x4B); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x4C); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x4D); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x4E); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F0, 0x4F); + status = ad9361_reg_write(dev, 0x00F1, 0x00); + status = ad9361_reg_write(dev, 0x00F2, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x9E); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F4, 0x00); + status = ad9361_reg_write(dev, 0x00F5, 0x98); // Disable clock to Rx Filter + +//************************************************************ +// Setup the Parallel Port (Digital Data Interface) +//************************************************************ + status = ad9361_reg_write(dev, 0x0010, 0xC8); // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK + status = ad9361_reg_write(dev, 0x0011, 0x00); // I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data + status = ad9361_reg_write(dev, 0x0012, 0x02); // I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits + status = ad9361_reg_write(dev, 0x0006, 0x00); // PPORT Rx Delay (adjusts Tco Dataclk->Data) + status = ad9361_reg_write(dev, 0x0007, 0x0F); // PPORT TX Delay (adjusts setup/hold FBCLK->Data) + +//************************************************************ +// Setup AuxDAC +//************************************************************ + status = ad9361_reg_write(dev, 0x0018, 0x00); // AuxDAC1 Word[9:2] + status = ad9361_reg_write(dev, 0x0019, 0x00); // AuxDAC2 Word[9:2] + status = ad9361_reg_write(dev, 0x001A, 0x00); // AuxDAC1 Config and Word[1:0] + status = ad9361_reg_write(dev, 0x001B, 0x00); // AuxDAC2 Config and Word[1:0] + status = ad9361_reg_write(dev, 0x0023, 0xFF); // AuxDAC Manaul/Auto Control + status = ad9361_reg_write(dev, 0x0026, 0x00); // AuxDAC Manual Select Bit/GPO Manual Select + status = ad9361_reg_write(dev, 0x0030, 0x00); // AuxDAC1 Rx Delay + status = ad9361_reg_write(dev, 0x0031, 0x00); // AuxDAC1 Tx Delay + status = ad9361_reg_write(dev, 0x0032, 0x00); // AuxDAC2 Rx Delay + status = ad9361_reg_write(dev, 0x0033, 0x00); // AuxDAC2 Tx Delay + +//************************************************************ +// Setup AuxADC +//************************************************************ + status = ad9361_reg_write(dev, 0x000B, 0x00); // Temp Sensor Setup (Offset) + status = ad9361_reg_write(dev, 0x000C, 0x00); // Temp Sensor Setup (Temp Window) + status = ad9361_reg_write(dev, 0x000D, 0x03); // Temp Sensor Setup (Periodic Measure) + status = ad9361_reg_write(dev, 0x000F, 0x04); // Temp Sensor Setup (Decimation) + status = ad9361_reg_write(dev, 0x001C, 0x00); // AuxADC Setup (Clock Div) + status = ad9361_reg_write(dev, 0x001D, 0x01); // AuxADC Setup (Decimation/Enable) + +//************************************************************ +// Setup Control Outs +//************************************************************ + status = ad9361_reg_write(dev, 0x0035, 0x00); // Ctrl Out index + status = ad9361_reg_write(dev, 0x0036, 0xFF); // Ctrl Out [7:0] output enable + +//************************************************************ +// Setup GPO +//************************************************************ + status = ad9361_reg_write(dev, 0x003A, 0x18); // Set number of REFCLK cycles for 1us delay timer + status = ad9361_reg_write(dev, 0x0020, 0x00); // GPO Auto Enable Setup in RX and TX + status = ad9361_reg_write(dev, 0x0027, 0x00); // GPO Manual and GPO auto value in ALERT + status = ad9361_reg_write(dev, 0x0028, 0x00); // GPO_0 RX Delay + status = ad9361_reg_write(dev, 0x0029, 0x00); // GPO_1 RX Delay + status = ad9361_reg_write(dev, 0x002A, 0x00); // GPO_2 RX Delay + status = ad9361_reg_write(dev, 0x002B, 0x00); // GPO_3 RX Delay + status = ad9361_reg_write(dev, 0x002C, 0x00); // GPO_0 TX Delay + status = ad9361_reg_write(dev, 0x002D, 0x00); // GPO_1 TX Delay + status = ad9361_reg_write(dev, 0x002E, 0x00); // GPO_2 TX Delay + status = ad9361_reg_write(dev, 0x002F, 0x00); // GPO_3 TX Delay + +//************************************************************ +// Setup RF PLL non-frequency-dependent registers +//************************************************************ + status = ad9361_reg_write(dev, 0x0261, 0x00); // Set Rx LO Power mode + status = ad9361_reg_write(dev, 0x02A1, 0x00); // Set Tx LO Power mode + status = ad9361_reg_write(dev, 0x0248, 0x0B); // Enable Rx VCO LDO + status = ad9361_reg_write(dev, 0x0288, 0x0B); // Enable Tx VCO LDO + status = ad9361_reg_write(dev, 0x0246, 0x02); // Set VCO Power down TCF bits + status = ad9361_reg_write(dev, 0x0286, 0x02); // Set VCO Power down TCF bits + status = ad9361_reg_write(dev, 0x0249, 0x8E); // Set VCO cal length + status = ad9361_reg_write(dev, 0x0289, 0x8E); // Set VCO cal length + status = ad9361_reg_write(dev, 0x023B, 0x80); // Enable Rx VCO cal + status = ad9361_reg_write(dev, 0x027B, 0x80); // Enable Tx VCO cal + status = ad9361_reg_write(dev, 0x0243, 0x0D); // Set Rx prescaler bias + status = ad9361_reg_write(dev, 0x0283, 0x0D); // Set Tx prescaler bias + status = ad9361_reg_write(dev, 0x023D, 0x00); // Clear Half VCO cal clock setting + status = ad9361_reg_write(dev, 0x027D, 0x00); // Clear Half VCO cal clock setting + + status = ad9361_reg_write(dev, 0x0015, 0x0C); // Set Dual Synth mode bit + status = ad9361_reg_write(dev, 0x0014, 0x1D); // Set Force ALERT State bit + status = ad9361_reg_write(dev, 0x0013, 0x01); // Set ENSM FDD mode + mdelay(1); // waits 1 ms + + status = ad9361_reg_write(dev, 0x023D, 0x04); // Start RX CP cal + + // Wait for CP cal to complete, Max RXCP Cal time: 737.280 (us)(Done when 0x244[7]==1) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0244, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x80) != 0x80 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x027D, 0x04); // Start TX CP cal + + // Wait for CP cal to complete, Max TXCP Cal time: 737.280 (us)(Done when 0x284[7]==1) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0284, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x80) != 0x80 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x023D, 0x00); // Disable RX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT + status = ad9361_reg_write(dev, 0x027D, 0x00); // Disable TX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT +//************************************************************ +// FDD RX,TX Synth Frequency: 125.000000,4125.000000 MHz +//************************************************************ +//************************************************************ +// Setup Rx Frequency-Dependent Syntheisizer Registers +//************************************************************ + status = ad9361_reg_write(dev, 0x023A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0239, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0242, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0238, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0245, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0251, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0250, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x023B, 0x94); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x023E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x023F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0240, 0x0A); // Set Synth Loop Filter R3 + +//************************************************************ +// Setup Tx Frequency-Dependent Syntheisizer Registers +//************************************************************ + status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 + +//************************************************************ +// Write Rx and Tx Frequency Words +//************************************************************ + status = ad9361_reg_write(dev, 0x0233, 0x00); // Write Rx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0234, 0x00); // Write Rx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0235, 0x00); // Write Rx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0232, 0x00); // Write Rx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0231, 0xA0); // Write Rx Synth Integer Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0005, 0x05); // Set LO divider setting + status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) + status = ad9361_reg_write(dev, 0x0005, 0x05); // Set LO divider setting + +//************************************************************ +// Program Mixer GM Sub-table +//************************************************************ + status = ad9361_reg_write(dev, 0x013F, 0x02); // Start Clock + status = ad9361_reg_write(dev, 0x0138, 0x0F); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x78); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x00); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0E); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x74); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x0D); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0D); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x70); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x15); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0C); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x6C); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x1B); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0B); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x68); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x21); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0A); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x64); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x25); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x09); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x60); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x29); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x08); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x5C); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x2C); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x07); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x58); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x2F); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x06); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x54); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x31); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x05); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x50); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x33); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x04); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x4C); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x34); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x03); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x48); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x35); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x02); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x30); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x3A); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x01); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x18); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x3D); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x00); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x00); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x3E); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x013F, 0x02); // Clear Write Bit + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x013F, 0x00); // Stop Clock + +//************************************************************ +// Program Rx Gain Tables with GainTable800MHz.csv +//************************************************************ + + status = ad9361_reg_write(dev, 0x0137, 0x1A); // Start Gain Table Clock + status = ad9361_reg_write(dev, 0x0130, 0x00); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x01); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x02); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x03); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x01); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x04); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x02); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x05); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x03); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x06); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x04); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x07); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x05); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x08); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x03); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x09); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x04); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x05); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x06); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x07); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x08); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x09); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0A); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x10); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x11); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0C); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x12); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0D); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x13); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0E); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x14); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x09); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x15); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0A); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x16); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x17); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0C); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x18); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0D); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x19); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0E); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0F); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x10); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2C); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x04); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x28); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x04); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x29); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x20); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x04); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2A); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x21); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x04); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x22); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x24); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x20); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x23); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x24); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x21); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x24); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x20); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x25); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x21); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x26); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x22); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x27); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x23); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x28); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x24); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x29); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x25); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x26); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x27); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x28); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x29); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2A); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x30); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2C); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x31); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2D); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x32); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2E); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x33); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2F); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x34); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x30); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x35); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x31); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x36); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x32); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x37); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2E); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x38); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2F); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x39); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x30); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x31); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x32); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x33); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x34); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x35); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x36); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x40); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x37); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x41); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x42); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x65); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x43); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x66); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x44); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x67); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x45); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x68); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x46); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x69); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x47); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6A); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x48); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6B); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x49); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6C); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6D); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6E); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6F); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x50); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x51); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x52); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x53); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x54); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x55); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x56); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x57); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x58); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x59); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x5A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0137, 0x1A); // Clear Write Bit + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0137, 0x00); // Stop Gain Table Clock +//************************************************************ +// Setup Rx Manual Gain Registers +//************************************************************ + status = ad9361_reg_write(dev, 0x00FA, 0xE0); // Gain Control Mode Select + status = ad9361_reg_write(dev, 0x00FB, 0x08); // Table, Digital Gain, Man Gain Ctrl + status = ad9361_reg_write(dev, 0x00FC, 0x23); // Incr Step Size, ADC Overrange Size + status = ad9361_reg_write(dev, 0x00FD, 0x4C); // Max Full/LMT Gain Table Index + status = ad9361_reg_write(dev, 0x00FE, 0x44); // Decr Step Size, Peak Overload Time + status = ad9361_reg_write(dev, 0x0100, 0x6F); // Max Digital Gain + status = ad9361_reg_write(dev, 0x0104, 0x2F); // ADC Small Overload Threshold + status = ad9361_reg_write(dev, 0x0105, 0x3A); // ADC Large Overload Threshold + status = ad9361_reg_write(dev, 0x0107, 0x2B); // Small LMT Overload Threshold + status = ad9361_reg_write(dev, 0x0108, 0x31); // Large LMT Overload Threshold + status = ad9361_reg_write(dev, 0x0109, 0x00); // Rx1 Full/LMT Gain Index + status = ad9361_reg_write(dev, 0x010A, 0x58); // Rx1 LPF Gain Index + status = ad9361_reg_write(dev, 0x010B, 0x00); // Rx1 Digital Gain Index + status = ad9361_reg_write(dev, 0x010C, 0x00); // Rx2 Full/LMT Gain Index + status = ad9361_reg_write(dev, 0x010D, 0x18); // Rx2 LPF Gain Index + status = ad9361_reg_write(dev, 0x010E, 0x00); // Rx2 Digital Gain Index + status = ad9361_reg_write(dev, 0x0114, 0x30); // Low Power Threshold + status = ad9361_reg_write(dev, 0x011A, 0x27); // Initial LMT Gain Limit + status = ad9361_reg_write(dev, 0x0081, 0x00); // Tx Symbol Gain Control +//************************************************************ +// RX Baseband Filter Tuning (Real BW: 7.500000 MHz) 3dB Filter +// Corner @ 10.500000 MHz) +//************************************************************ + status = ad9361_reg_write(dev, 0x01FB, 0x07); // RX Freq Corner (MHz) + status = ad9361_reg_write(dev, 0x01FC, 0x40); // RX Freq Corner (Khz) + status = ad9361_reg_write(dev, 0x01F8, 0x0D); // Rx BBF Tune Divider[7:0] + status = ad9361_reg_write(dev, 0x01F9, 0x1E); // RX BBF Tune Divider[8] + + status = ad9361_reg_write(dev, 0x01D5, 0x3F); // Set Rx Mix LO CM + status = ad9361_reg_write(dev, 0x01C0, 0x03); // Set GM common mode + status = ad9361_reg_write(dev, 0x01E2, 0x02); // Enable Rx1 Filter Tuner + status = ad9361_reg_write(dev, 0x01E3, 0x02); // Enable Rx2 Filter Tuner + status = ad9361_reg_write(dev, 0x0016, 0x80); // Start RX Filter Tune + + // Wait for RX filter to tune, Max Cal Time: 6.884 us (Done when 0x016[7]==0) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x80) != 0x00 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x01E2, 0x03); // Disable Rx Filter Tuner (Rx1) + status = ad9361_reg_write(dev, 0x01E3, 0x03); // Disable Rx Filter Tuner (Rx2) +//************************************************************ +// TX Baseband Filter Tuning (Real BW: 7.500000 MHz) 3dB Filter +// Corner @ 12.000000 MHz) +//************************************************************ + status = ad9361_reg_write(dev, 0x00D6, 0x0B); // TX BBF Tune Divider[7:0] + status = ad9361_reg_write(dev, 0x00D7, 0x1E); // TX BBF Tune Divider[8] + + status = ad9361_reg_write(dev, 0x00CA, 0x22); // Enable Tx Filter Tuner + status = ad9361_reg_write(dev, 0x0016, 0x40); // Start Tx Filter Tune + + // Wait for TX filter to tune, Max Cal Time: 3.390 us (Done when 0x016[6]==0) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x40) != 0x00 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x00CA, 0x26); // Disable Tx Filter Tuner (Both Channels) +//************************************************************ +// RX TIA Setup: Setup values scale based on RxBBF calibration +// results. See information in Calibration Guide. +//************************************************************ + status = ad9361_reg_write(dev, 0x01DB, 0x60); // Set TIA selcc[2:0] + status = ad9361_reg_write(dev, 0x01DD, 0x00); // Set RX TIA1 C MSB[6:0] + status = ad9361_reg_write(dev, 0x01DF, 0x00); // Set RX TIA2 C MSB[6:0] + status = ad9361_reg_write(dev, 0x01DC, 0x72); // Set RX TIA1 C LSB[5:0] + status = ad9361_reg_write(dev, 0x01DE, 0x72); // Set RX TIA2 C LSB[5:0] + +//************************************************************ +// TX Secondary Filter Calibration Setup: Real Bandwidth +// 7.500000MHz, 3dB Corner @ 37.500000MHz +//************************************************************ + status = ad9361_reg_write(dev, 0x00D2, 0x1E); // TX Secondary Filter PDF Cap cal[5:0] + status = ad9361_reg_write(dev, 0x00D1, 0x0C); // TX Secondary Filter PDF Res cal[3:0] + status = ad9361_reg_write(dev, 0x00D0, 0x56); // Pdampbias + +//************************************************************ +// ADC Setup: Tune ADC Performance based on RX analog filter tune +// corner. Real Bandwidth: 6.982753 MHz, ADC Clock Frequency: +// 288.000000 MHz. The values in registers 0x200 - 0x227 need to be +// calculated using the equations in the Calibration Guide. +//************************************************************ + + status = ad9361_reg_write(dev, 0x0200, 0x00); + status = ad9361_reg_write(dev, 0x0201, 0x00); + status = ad9361_reg_write(dev, 0x0202, 0x00); + status = ad9361_reg_write(dev, 0x0203, 0x24); + status = ad9361_reg_write(dev, 0x0204, 0x24); + status = ad9361_reg_write(dev, 0x0205, 0x00); + status = ad9361_reg_write(dev, 0x0206, 0x00); + status = ad9361_reg_write(dev, 0x0207, 0x7C); + status = ad9361_reg_write(dev, 0x0208, 0x46); + status = ad9361_reg_write(dev, 0x0209, 0x3C); + status = ad9361_reg_write(dev, 0x020A, 0x4C); + status = ad9361_reg_write(dev, 0x020B, 0x2C); + status = ad9361_reg_write(dev, 0x020C, 0x4F); + status = ad9361_reg_write(dev, 0x020D, 0x2A); + status = ad9361_reg_write(dev, 0x020E, 0x00); + status = ad9361_reg_write(dev, 0x020F, 0x7F); + status = ad9361_reg_write(dev, 0x0210, 0x7F); + status = ad9361_reg_write(dev, 0x0211, 0x7F); + status = ad9361_reg_write(dev, 0x0212, 0x4A); + status = ad9361_reg_write(dev, 0x0213, 0x4A); + status = ad9361_reg_write(dev, 0x0214, 0x4A); + status = ad9361_reg_write(dev, 0x0215, 0x4D); + status = ad9361_reg_write(dev, 0x0216, 0x4D); + status = ad9361_reg_write(dev, 0x0217, 0x4D); + status = ad9361_reg_write(dev, 0x0218, 0x2E); + status = ad9361_reg_write(dev, 0x0219, 0x9C); + status = ad9361_reg_write(dev, 0x021A, 0x1F); + status = ad9361_reg_write(dev, 0x021B, 0x15); + status = ad9361_reg_write(dev, 0x021C, 0x9C); + status = ad9361_reg_write(dev, 0x021D, 0x1F); + status = ad9361_reg_write(dev, 0x021E, 0x15); + status = ad9361_reg_write(dev, 0x021F, 0x9C); + status = ad9361_reg_write(dev, 0x0220, 0x1F); + status = ad9361_reg_write(dev, 0x0221, 0x2A); + status = ad9361_reg_write(dev, 0x0222, 0x2A); + status = ad9361_reg_write(dev, 0x0223, 0x40); + status = ad9361_reg_write(dev, 0x0224, 0x40); + status = ad9361_reg_write(dev, 0x0225, 0x2C); + status = ad9361_reg_write(dev, 0x0226, 0x00); + status = ad9361_reg_write(dev, 0x0227, 0x00); +//************************************************************ +// Setup and Run BB DC and RF DC Offset Calibrations +//************************************************************ + status = ad9361_reg_write(dev, 0x0193, 0x3F); + status = ad9361_reg_write(dev, 0x0190, 0x0F); // Set BBDC tracking shift M value, only applies when BB DC tracking enabled + status = ad9361_reg_write(dev, 0x0194, 0x01); // BBDC Cal setting + status = ad9361_reg_write(dev, 0x0016, 0x01); // Start BBDC offset cal + + // BBDC Max Cal Time: 8416.667 us. Cal done when 0x016[0]==0 + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x01) != 0x00 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x0185, 0x20); // Set RF DC offset Wait Count + status = ad9361_reg_write(dev, 0x0186, 0x32); // Set RF DC Offset Count[7:0] + status = ad9361_reg_write(dev, 0x0187, 0x24); // Settings for RF DC cal + status = ad9361_reg_write(dev, 0x018B, 0x83); // Settings for RF DC cal + status = ad9361_reg_write(dev, 0x0188, 0x05); // Settings for RF DC cal + status = ad9361_reg_write(dev, 0x0189, 0x30); // Settings for RF DC cal + status = ad9361_reg_write(dev, 0x0016, 0x02); // Start RFDC offset cal + + // RFDC Max Cal Time: 114511.250 us + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x01) != 0x00 && time_out_cnt <= TIMEOUT_TH); + +//************************************************************ +// Tx Quadrature Calibration Settings +//************************************************************ + status = ad9361_reg_write(dev, 0x00A0, 0x15); // Set TxQuadcal NCO frequency + status = ad9361_reg_write(dev, 0x00A3, 0x00); // Set TxQuadcal NCO frequency (Only update bits [7:6]) + status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable + status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count + status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp + status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index + status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count + status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used + + status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration + status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal + + // Wait for cal to complete (Done when 0x016[4]==0) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x10) != 0x00 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x016A, 0x75); // Set Kexp Phase + status = ad9361_reg_write(dev, 0x016B, 0x95); // Set Kexp Amplitude & Prevent Positive Gain Bit + status = ad9361_reg_write(dev, 0x0169, 0xCF); // Enable Rx Quadrature Calibration Tracking + status = ad9361_reg_write(dev, 0x018B, 0xAD); // Enable BB and RF DC Tracking Calibrations + status = ad9361_reg_write(dev, 0x0012, 0x02); // Cals done, Set PPORT Config + status = ad9361_reg_write(dev, 0x0013, 0x01); // Set ENSM FDD/TDD bit + status = ad9361_reg_write(dev, 0x0015, 0x0C); // Set Dual Synth Mode, FDD External Control bits properly + +//************************************************************ +// Set Tx Attenuation: Tx1: 0.00 dB, Tx2: 0.00 dB +//************************************************************ + status = ad9361_reg_write(dev, 0x0073, 0x00); + status = ad9361_reg_write(dev, 0x0074, 0x00); + status = ad9361_reg_write(dev, 0x0075, 0x00); + status = ad9361_reg_write(dev, 0x0076, 0x00); +//************************************************************ +// Setup RSSI and Power Measurement Duration Registers +//************************************************************ + status = ad9361_reg_write(dev, 0x0150, 0x0E); // RSSI Measurement Duration 0, 1 + status = ad9361_reg_write(dev, 0x0151, 0x00); // RSSI Measurement Duration 2, 3 + status = ad9361_reg_write(dev, 0x0152, 0xFF); // RSSI Weighted Multiplier 0 + status = ad9361_reg_write(dev, 0x0153, 0x00); // RSSI Weighted Multiplier 1 + status = ad9361_reg_write(dev, 0x0154, 0x00); // RSSI Weighted Multiplier 2 + status = ad9361_reg_write(dev, 0x0155, 0x00); // RSSI Weighted Multiplier 3 + status = ad9361_reg_write(dev, 0x0156, 0x00); // RSSI Delay + status = ad9361_reg_write(dev, 0x0157, 0x00); // RSSI Wait + status = ad9361_reg_write(dev, 0x0158, 0x0D); // RSSI Mode Select + status = ad9361_reg_write(dev, 0x015C, 0x67); // Power Measurement Duration + +//************************************************************ +// Enable External LO & External VCO Buffer +//************************************************************ + status |= ad9361_reg_write(dev, 0x0005, 0x07); + status |= ad9361_reg_write(dev, 0x0057, 0x1C); + + return status; +} diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/dev_profile/ad9516_profile.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/dev_profile/ad9516_profile.c new file mode 100644 index 0000000..65764aa --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/dev_profile/ad9516_profile.c @@ -0,0 +1,89 @@ +#include "dev_profile.h" +#include "../app_config.h" +#include "../adi_noos/drivers/frequency/ad9516/ad9516.h" + + +static spi_init_param ad9516_spi_init = { + .device_id = SPI_DEVICE_ID, + .max_speed_hz = SPI_ENGINE_MAX_SPEED, + .mode = SPI_MODE_4, + .chip_select = SPI_CS_AD9516, + .platform_ops = SPI_OPS, + .extra = SPI_PARAM +}; + +struct ad9516_init_param ad9516_default_init_param = { + /* SPI */ + .spi_init = &ad9516_spi_init +}; + +const uint32_t ad9516_default_config_len = 66; +const struct ad9516_config ad9516_default_config[] = { + {0x0000,0x18}, // 16-bit instruction, MSB first, 3-wire SPI + {0x0004,0x00}, // reads back buffer registers + {0x0010,0x7C}, + {0x0011,0x04}, // R divider LSBs, R = 4 + {0x0012,0x00}, // R divider MSBs, R = 4 + {0x0013,0x08}, // A counter, A = 8 + {0x0014,0x09}, // B counter LSBs, B = 9 + {0x0015,0x00}, // B counter MSBs, B = 9 + {0x0016,0x04}, // Divide-by-8 (8/9 mode) + {0x0017,0x10}, // STATUS pin output: Prescaler output + {0x0018,0x06}, + {0x0019,0x80}, // R, A, B counters synchronous reset on SYNCB + {0x001A,0x00}, // LD pin output: Digital lock detect (high = lock, low = unlock) + {0x001B,0xA1}, // enables VCO, REF1 frequency monitor; REFMON pin output: REF1 clock + {0x001C,0x07}, // selects REF1; REF1, REF2 power on; differential reference mode + {0x001D,0x00}, + {0x001E,0x00}, + {0x00A0,0x01}, + {0x00A1,0x00}, + {0x00A2,0x00}, + {0x00A3,0x01}, + {0x00A4,0x00}, + {0x00A5,0x00}, + {0x00A6,0x01}, + {0x00A7,0x00}, + {0x00A8,0x00}, + {0x00A9,0x01}, + {0x00AA,0x00}, + {0x00AB,0x00}, + {0x00F0,0x08}, + {0x00F1,0x08}, + {0x00F2,0x08}, + {0x00F3,0x08}, + {0x00F4,0x08}, + {0x00F5,0x08}, + {0x0140,0x59}, + {0x0141,0x5A}, + {0x0142,0x5A}, + {0x0143,0x42}, + {0x0190,0x33}, + {0x0191,0x40}, + {0x0192,0x00}, + {0x0193,0x33}, + {0x0194,0x40}, + {0x0195,0x00}, + {0x0196,0x44}, + {0x0197,0x40}, + {0x0198,0x00}, + {0x0199,0x99}, // divider 3.1, Low Cycles = 10, High Cycles = 10 + {0x019A,0x00}, + {0x019B,0x00}, // divider 3.1, Low Cycles = 1, High Cycles = 1 + {0x019C,0x00}, + {0x019D,0x00}, +// {0x019E,0xFF}, + {0x019E,0x11}, + {0x019F,0x00}, + {0x01A0,0x11}, + {0x01A1,0x20}, + {0x01A2,0x00}, + {0x01A3,0x00}, + {0x01E0,0x00}, + {0x01E1,0x02}, + {0x0230,0x00}, + {0x0231,0x00}, + {0x0232,0x01}, // Update all registers + {0x0018,0x07}, // initiate the VCO calibration + {0x0232,0x01} // Update all registers +}; diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/dev_profile/dev_profile.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/dev_profile/dev_profile.h new file mode 100644 index 0000000..11393c2 --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/dev_profile/dev_profile.h @@ -0,0 +1,43 @@ +#ifndef DEV_PROFILE_H_ +#define DEV_PROFILE_H_ + +#include +#include "../app_config.h" +#include "../parameters.h" +#include "../adi_noos/include/spi.h" +#include "../adi_noos/include/gpio.h" +#include "../adi_noos/include/delay.h" +#include "../adi_noos/include/irq.h" +#include "../adi_noos/include/error.h" +#include "../adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h" +#include "../adi_noos/drivers/frequency/ad9516/ad9516.h" + +// Platform includes +#include "../adi_noos/drivers/platform/spi_extra.h" +#include "../adi_noos/drivers/platform/gpio_extra.h" +#include "../adi_noos/drivers/platform/irq_extra.h" + +// AXI-Cores includes +#include "../adi_noos/drivers/axi_core/spi_engine/spi_engine.h" + +// Declare in mian.c +extern struct spi_engine_init_param spi_engine_param; +extern struct xil_gpio_init_param xil_gpio_param; + +#define GPIO_PARAM &xil_gpio_param +#define SPI_PARAM &spi_engine_param +#define GPIO_OPS &xil_gpio_ops +#define SPI_OPS &spi_eng_platform_ops + +extern struct ad9516_init_param ad9516_default_init_param; +extern const struct ad9516_config ad9516_default_config[]; +extern const uint32_t ad9516_default_config_len; + +extern struct ad9361_reg_init_param ad9361_1_reg_default_init_param; +extern struct ad9361_reg_init_param ad9361_2_reg_default_init_param; + +uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev); +uint32_t ad9361_1_reg_config(struct ad9361_reg_dev *dev); +uint32_t ad9361_2_reg_config(struct ad9361_reg_dev *dev); + +#endif /* SRC_DEV_PROFILE_H_ */ diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/main.c b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/main.c new file mode 100644 index 0000000..d68166d --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/main.c @@ -0,0 +1,422 @@ +/***************************************************************************//** + * @file ad9361/src/main.c + * @brief Implementation of Main Function. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2013(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +// Platform includes +#include +#include "xparameters.h" +#include "xil_assert.h" +#include "xgpio.h" +// ADI Drivers +#include "app_config.h" +#include "dev_profile/dev_profile.h" +#include "adi_noos/drivers/axi_core/spi_engine/spi_engine.h" +// AXI-Cores includes +#include "adi_noos/drivers/axi_core/spi_engine/spi_engine.h" +#include "adi_noos/drivers/platform/gpio_extra.h" + +/******************************************************************************/ +/************************ Variables Definitions *******************************/ +/******************************************************************************/ + +struct spi_engine_init_param spi_engine_param = { + .ref_clk_hz = SPI_ENGINE_REF_CLK, + .type = SPI_ENGINE, + .spi_engine_baseaddr = SPI_ENGINE_BASEADDR, + .cs_delay = SPI_ENGINE_CS_DELAY, + .data_width = SPI_ENGINE_DATA_WIDTH +}; + +struct xil_gpio_init_param xil_gpio_param = { + .type = GPIO_PS, + .device_id = GPIO_DEVICE_ID +}; + +struct ad9516_dev *ad9516_inst; +struct ad9361_reg_dev *ad9361_1_reg_inst; +struct ad9361_reg_dev *ad9361_2_reg_inst; +struct ad9361_rf_phy *ad9361_phy; + +XGpio Gpio; + +int XGpio_WritePin(XGpio *InstPtr, unsigned Channel, u32 Pin, u8 Value); +int Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq); + +/***************************************************************************//** + * @brief main +*******************************************************************************/ +int main(void) +{ + int32_t Status; + Status = XGpio_Initialize(&Gpio, GPIO_DEVICE_ID); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + XGpio_SetDataDirection(&Gpio, GPIO_BANK_OUT, 0x00000000); // Bank 1 output + XGpio_SetDataDirection(&Gpio, GPIO_BANK_IN, 0xFFFFFFFF); // Bank 0 input + + XGpio_DiscreteWrite(&Gpio, GPIO_BANK_OUT, 0x00000000); + + /**********************************************************/ + /****************** AD9516 Configuration ******************/ + /**********************************************************/ + Status = ad9516_init(&ad9516_inst, &ad9516_default_init_param); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_POWEDOWN_B, 1); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_SYNC_B, 1); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_RESET_B, 0); + mdelay(200); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_RESET_B, 1); + for(int i = 0; i < ad9516_default_config_len; i++){ + Status = ad9516_write(ad9516_inst, ad9516_default_config[i].addr, ad9516_default_config[i].value); + if (ad9516_default_config[i].addr == 0x0000){ + mdelay(500); + } + } + + uint8_t rd_back; + Status = ad9516_read(ad9516_inst, 0x0003, &rd_back); + do + { + Status = ad9516_read(ad9516_inst, 0x001F, &rd_back); + } + while((rd_back & 0x01) != 0x01); + + /**********************************************************/ + /***************** AD9361-1 Configuration *****************/ + /**********************************************************/ + ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param); + + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_RESET_B, 0); + mdelay(200); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_RESET_B, 1); + + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_ENABLE, 0); + ad9361_reg_config(ad9361_1_reg_inst); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_ENABLE, 1); + + /**********************************************************/ + /***************** AD9361-2 Configuration *****************/ + /**********************************************************/ + ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param); + + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_RESET_B, 0); + mdelay(200); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_RESET_B, 1); + + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_ENABLE, 0); + ad9361_reg_config(ad9361_2_reg_inst); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_ENABLE, 1); + + /**********************************************************/ + /******* AD9361 Baseband Multichip Synchronization ********/ + /**********************************************************/ + // sync clock output + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_SYNC_B, 0); + mdelay(500); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_SYNC_B, 1); + + // SYNC BBPLL and DIGITAL SAMPLING CLOCKS + ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable + ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D); + ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable + ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 0); + mdelay(20); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin + mdelay(500); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 0); + mdelay(2000); + ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable + ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin + mdelay(500); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 0); + ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits + ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08); + + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_RX_FIFO_RST, 0); + mdelay(20); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_RX_FIFO_RST, 1); + mdelay(20); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_RX_FIFO_RST, 0); + + /**********************************************************/ + /********* AD9361 Multichip Rx Phase Calibration **********/ + /**********************************************************/ + // switch to lower frequency + Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_TX_SW, 1); + mdelay(20); + + // switch rx channel + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30); + Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30); + + // enable dual ad9361 tx channels + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels + +#ifdef DL814_BOARD_V3 + // switch ad9361 tx channel + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B) + mdelay(20); +#endif + + // begin to calibrate the 1st ad9361 + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_CAL_START, 0); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_CAL_START, 1); + mdelay(1); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_CAL_START, 0); + + // read calibration status + int32_t time_out_cnt = 0; + do{ + mdelay(1);// Wait 1ms + time_out_cnt++; + }while((((XGpio_DiscreteRead(&Gpio, GPIO_BANK_IN) >> AD9361_1_CAL_DONE) & 0x00000001) == 0) && time_out_cnt <= TIMEOUT_TH); + + if (time_out_cnt == TIMEOUT_TH){ + return FAILURE; + } + +#ifdef DL814_BOARD_V2 + // switch ad9361 tx channel + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B) + mdelay(20); +#endif + + // begin to calibrate the 2nd ad9361 + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_CAL_START, 1); + mdelay(1); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_CAL_START, 0); + + // read calibration status + time_out_cnt = 0; + do{ + mdelay(1);// Wait 1ms + time_out_cnt++; + }while((((XGpio_DiscreteRead(&Gpio, GPIO_BANK_IN) >> AD9361_2_CAL_DONE) & 0x00000001) == 0) && time_out_cnt <= TIMEOUT_TH); + + if (time_out_cnt == TIMEOUT_TH){ + return FAILURE; + } + + // enable single ad9361 tx channels + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels + + // switch ad9361 tx & rx channel + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03); + Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03); + + // switch to higher frequency + Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_TX_SW, 0); + + print("Done.\n"); + + return 0; +} + +int Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq){ + int32_t status = 0; + uint8_t value = 0; + int32_t time_out_cnt = 0; + + switch(freq){ + case TX_FREQ_125: { + //************************************************************ + // Setup Tx Frequency-Dependent Syntheisizer Registers + //************************************************************ + status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 + + //************************************************************ + // Write Tx Frequency Words + //************************************************************ + status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) + status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting + + //************************************************************ + // Tx Quadrature Calibration Settings + //************************************************************ + status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency + status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6]) + status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable + status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count + status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp + status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index + status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count + status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used + + status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration + status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal + + break; + } + case TX_FREQ_126: { + //************************************************************ + // Setup Tx Frequency-Dependent Syntheisizer Registers + //************************************************************ + status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 + + //************************************************************ + // Write Tx Frequency Words + //************************************************************ + status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) + status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting + + //************************************************************ + // Tx Quadrature Calibration Settings + //************************************************************ + status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency + status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6]) + status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable + status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count + status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp + status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index + status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count + status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used + + status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration + status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal + + break; + } + case TX_FREQ_4125: { + //************************************************************ + // Setup Tx Frequency-Dependent Syntheisizer Registers + //************************************************************ + status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 + + //************************************************************ + // Write Rx Frequency Words + //************************************************************ + status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) + status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting + + //************************************************************ + // Tx Quadrature Calibration Settings + //************************************************************ + status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency + status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6]) + status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable + status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count + status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp + status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index + status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count + status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used + + status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration + status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal + + break; + } + + // Wait for cal to complete (Done when 0x016[4]==0) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x10) != 0x00 && time_out_cnt <= TIMEOUT_TH); + } + + return status; +} +int XGpio_WritePin(XGpio *InstPtr, unsigned Channel, u32 Pin, u8 Value){ + Xil_AssertNonvoid(Pin <= 31 && Pin >=0 ); + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(InstPtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((Channel == 1) || + ((Channel == 2) && (InstPtr->IsDual == TRUE))); + u32 CurrValue = XGpio_DiscreteRead(InstPtr, Channel); + CurrValue = (Value == 0)? (CurrValue & (~(0x00000001 << Pin))) : (CurrValue | (0x00000001 << Pin)); + XGpio_DiscreteWrite(InstPtr, Channel, CurrValue); + return XST_SUCCESS; +} + diff --git a/dl814_k7_cal_coarse/vitis_classic_autobuild/source/parameters.h b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/parameters.h new file mode 100644 index 0000000..ec1a7ce --- /dev/null +++ b/dl814_k7_cal_coarse/vitis_classic_autobuild/source/parameters.h @@ -0,0 +1,137 @@ +/***************************************************************************//** + * @file ad9361/src/parameters.h + * @brief Parameters Definitions. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2013(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef __PARAMETERS_H__ +#define __PARAMETERS_H__ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "app_config.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#ifdef XILINX_PLATFORM + +#define FCLK_CLK0_HZ 25000000 + +#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID + +#define GPIO_DEVICE_ID XPAR_AXI_GPIO_DEVICE_ID +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 +#define GPIO_DISABLE 0 +#define GPIO_ENABLE 1 + +#define AD9516_POWEDOWN_B 0 +#define AD9516_RESET_B 1 +#define AD9516_SYNC_B 2 +#define AD9361_1_TXNRX 3 +#define AD9361_1_ENABLE 4 +#define AD9361_1_EN_AGC 5 +#define AD9361_1_RESET_B 6 +#define AD9361_1_CTRL_IN_0 7 +#define AD9361_1_CTRL_IN_1 8 +#define AD9361_1_CTRL_IN_2 9 +#define AD9361_1_CTRL_IN_3 10 +#define AD9361_2_TXNRX 11 +#define AD9361_2_ENABLE 12 +#define AD9361_2_EN_AGC 13 +#define AD9361_2_RESET_B 14 +#define AD9361_2_CTRL_IN_0 15 +#define AD9361_2_CTRL_IN_1 16 +#define AD9361_2_CTRL_IN_2 17 +#define AD9361_2_CTRL_IN_3 18 +#define AD9361_SYNC 19 +#define AD9361_RX_FIFO_RST 20 +#define AD9361_1_CAL_START 21 +#define AD9361_2_CAL_START 22 +#define AD9361_RECAL 23 +#define AD9361_TX_SW 24 + +#define AD9361_1_CTRL_OUT_0 0 +#define AD9361_1_CTRL_OUT_1 1 +#define AD9361_1_CTRL_OUT_2 2 +#define AD9361_1_CTRL_OUT_3 3 +#define AD9361_1_CTRL_OUT_4 4 +#define AD9361_1_CTRL_OUT_5 5 +#define AD9361_1_CTRL_OUT_6 6 +#define AD9361_1_CTRL_OUT_7 7 +#define AD9361_2_CTRL_OUT_0 8 +#define AD9361_2_CTRL_OUT_1 9 +#define AD9361_2_CTRL_OUT_2 10 +#define AD9361_2_CTRL_OUT_3 11 +#define AD9361_2_CTRL_OUT_4 12 +#define AD9361_2_CTRL_OUT_5 13 +#define AD9361_2_CTRL_OUT_6 14 +#define AD9361_2_CTRL_OUT_7 15 +#define AD9516_REFMON 16 +#define AD9516_LOCKDETECT 17 +#define AD9516_STARUS 18 +#define AD9361_1_CAL_DONE 19 +#define AD9361_2_CAL_DONE 20 +#define AD9361_CAL_RESULT 21 + +#define GPIO_BANK_OUT 1 +#define GPIO_BANK_IN 2 + +#define SPI_DEVICE_ID 0 +#define SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define SPI_ENGINE_MAX_SPEED 5000000 +#define SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR +#define SPI_ENGINE_DATA_WIDTH 8 +#define SPI_ENGINE_CS_DELAY 3 +#define SPI_CS_AD9516 0x00 +#define SPI_CS_AD9361_1 0x01 +#define SPI_CS_AD9361_2 0x02 + +#define DL814_BOARD_V3 +#define TIMEOUT_TH 2000 + +typedef enum +{ + TX_FREQ_125, + TX_FREQ_126, + TX_FREQ_4125 +} ad9361TxFreq; + +#endif + +#endif // __PARAMETERS_H__ diff --git a/scripts b/scripts new file mode 160000 index 0000000..af260c1 --- /dev/null +++ b/scripts @@ -0,0 +1 @@ +Subproject commit af260c1610963bd97c014d6c64b066bbbc875b94