2222 lines
134 KiB
XML
2222 lines
134 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2024.1.2 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Workspace/vivado/proj_dl814/dl814_k7_cal_coarse/dl814_k7_cal_coarse.xpr">
|
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
|
<Configuration>
|
|
<Option Name="Id" Val="6b5c265e78b24c9a980d5bdc67b35182"/>
|
|
<Option Name="Part" Val="xc7k410tffg900-2"/>
|
|
<Option Name="CompiledLibDir" Val="$PPRDIR/../../../../Tools/XilCompLib/vcs/2023.2"/>
|
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
|
<Option Name="CompiledLibDirVCS" Val="$PPRDIR/../../../../Tools/XilCompLib/vcs/2023.2"/>
|
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
|
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
|
|
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
|
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
|
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
|
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
|
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
|
|
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
|
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
|
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
|
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
|
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
|
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
|
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
|
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
|
<Option Name="TargetSimulator" Val="VCS"/>
|
|
<Option Name="BoardPart" Val=""/>
|
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
|
<Option Name="ProjectType" Val="Default"/>
|
|
<Option Name="IPRepoPath" Val="$PPRDIR/../../adi_library"/>
|
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
|
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
|
<Option Name="IPCachePermission" Val="read"/>
|
|
<Option Name="IPCachePermission" Val="write"/>
|
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
|
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
|
<Option Name="SimCompileState" Val="TRUE"/>
|
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
|
<Option Name="EnableBDX" Val="FALSE"/>
|
|
<Option Name="WTXSimLaunchSim" Val="0"/>
|
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
|
<Option Name="WTVcsLaunchSim" Val="10"/>
|
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
|
<Option Name="WTXSimExportSim" Val="48"/>
|
|
<Option Name="WTModelSimExportSim" Val="48"/>
|
|
<Option Name="WTQuestaExportSim" Val="48"/>
|
|
<Option Name="WTIesExportSim" Val="0"/>
|
|
<Option Name="WTVcsExportSim" Val="48"/>
|
|
<Option Name="WTRivieraExportSim" Val="47"/>
|
|
<Option Name="WTActivehdlExportSim" Val="47"/>
|
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
|
<Option Name="XSimRadix" Val="hex"/>
|
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
|
<Option Name="SimTypes" Val="rtl"/>
|
|
<Option Name="SimTypes" Val="bfm"/>
|
|
<Option Name="SimTypes" Val="tlm"/>
|
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
|
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
|
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
|
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
|
</Configuration>
|
|
<FileSets Version="1" Minor="32">
|
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
|
<Filter Type="Srcs"/>
|
|
<File Path="$PSRCDIR/sources_1/ip/cmpy_18x18_mult/cmpy_18x18_mult.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/ad9361_fifo/ad9361_fifo.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/cmpy_18x8/cmpy_18x8.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/dds_32b_8b/dds_32b_8b.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/bd/system_bd/system_bd.bd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0.xci">
|
|
<Proxy FileSetName="system_bd_axi_gpio_0_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci">
|
|
<Proxy FileSetName="system_bd_axi_spi_engine_0_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_clk_wiz_1_0/system_bd_clk_wiz_1_0.xci">
|
|
<Proxy FileSetName="system_bd_clk_wiz_1_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.xci">
|
|
<Proxy FileSetName="system_bd_dlmb_bram_if_cntlr_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.xci">
|
|
<Proxy FileSetName="system_bd_dlmb_v10_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.xci">
|
|
<Proxy FileSetName="system_bd_ilmb_bram_if_cntlr_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.xci">
|
|
<Proxy FileSetName="system_bd_ilmb_v10_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.xci">
|
|
<Proxy FileSetName="system_bd_lmb_bram_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_mdm_riscv_0/system_bd_mdm_riscv_0.xci">
|
|
<Proxy FileSetName="system_bd_mdm_riscv_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_microblaze_ps_riscv_0/system_bd_microblaze_ps_riscv_0.xci">
|
|
<Proxy FileSetName="system_bd_microblaze_ps_riscv_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_rst_clk_wiz_1_100M_0/system_bd_rst_clk_wiz_1_100M_0.xci">
|
|
<Proxy FileSetName="system_bd_rst_clk_wiz_1_100M_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci">
|
|
<Proxy FileSetName="system_bd_spi_engine_execution_0_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_xbar_0/system_bd_xbar_0.xci">
|
|
<Proxy FileSetName="system_bd_xbar_0"/>
|
|
</CompFileExtendedInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/ADF4351_2.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/FRAC1.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/INT_ROMb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/R_CAL_1.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/R_CAL_2.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/R_CAL_3.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/R_CAL_4.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/Sisyif.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/T_CAL.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_pre_process/accor_mat_formatting.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_pre_process/accum_cmplx_mat.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_pre_process/acorr_cmplx_col_vec.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_pre_process/ad9361_phase_cal_coarse.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_dual.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_dual.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/adder_tree_ppl.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/adf4371_a.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/adf4371_b.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/ant_rf_ctrl.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/band_rom_a.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/band_rom_b.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/hdwr/clk_dist.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/ds18b20_temp.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/frac2_rom.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/fre_caliatt.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/mgc_ctrl.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/mod2_rom.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_pre_process/null_ctrl.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_pre_process/phase_comp.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_pre_process/rx_pre_process.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_pre_process/rx_pre_test.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_pre_process/spatial_filter.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/spi_master.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/spi_salve.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ant_rf/Sisyif_src/spi_tx.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PGENDIR/sources_1/bd/system_bd/hdl/system_bd_wrapper.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/tx_pre_process.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/tx_qpsk.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/var_cal.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_pre_process/weight_vec_formatting.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/system_top.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_pre_process/phase_compensate.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_pre_process/ad9361_phase_cal_fine.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_64_12_025.coe">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/coe/sweep_freq.coe">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/coe/one_hop_data.coe">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/atan2_16b/atan2_16b.xci">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/atan2_16b/atan2_16b.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310598"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/vio_ant_rd/vio_ant_rd.xci">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/vio_ant_rd/vio_ant_rd.xci"/>
|
|
<Attr Name="ImportTime" Val="1707311065"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/vio_cal/vio_cal.xci">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/vio_cal/vio_cal.xci"/>
|
|
<Attr Name="ImportTime" Val="1707311088"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"/>
|
|
<Attr Name="ImportTime" Val="1707311110"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/ApproxModuli_26bit.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/trunc_32bit_to_12bit.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="DesignMode" Val="RTL"/>
|
|
<Option Name="TopModule" Val="system_top"/>
|
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
|
<Filter Type="Constrs"/>
|
|
<File Path="$PSRCDIR/constrs_1/new/k7401t_ad9516_2ad9361_physical.xdc">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/constrs_1/new/k7410t_ad9516_2ad9361_timing.xdc">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="ConstrsType" Val="XDC"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
|
<Filter Type="Srcs"/>
|
|
<File Path="$PSRCDIR/sim_1/new/tb_rx_pre.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sim_1/new/tb_rx_pre_test.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sim_1/new/tb_acorr.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sim_1/new/tb_null_ctrl.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sim_1/new/tb_accum.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sim_1/new/tb_xpm_cdc_pulse.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sim_1/new/tb_rx_test.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sim_1/new/tb_tx_pre_process.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="DesignMode" Val="RTL"/>
|
|
<Option Name="TopModule" Val="tb_rx_pre"/>
|
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
|
<Option Name="TransportPathDelay" Val="0"/>
|
|
<Option Name="TransportIntDelay" Val="0"/>
|
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
|
<Option Name="PamDesignTestbench" Val=""/>
|
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
|
<Option Name="SrcSet" Val="sources_1"/>
|
|
<Option Name="vcs.compile.vlogan.more_options" Val="-v2005 -kdb"/>
|
|
<Option Name="vcs.elaborate.vcs.more_options" Val="-debug_access+all"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
|
<Filter Type="Utils"/>
|
|
<File Path="$PSRCDIR/utils_1/imports/synth_1/system_top.dcp">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedInSteps" Val="synth_1"/>
|
|
<Attr Name="AutoDcp" Val="1"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_clk_wiz_1_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_clk_wiz_1_0" RelGenDir="$PGENDIR/system_bd_clk_wiz_1_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_clk_wiz_1_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ila_AntCtrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_AntCtrl" RelGenDir="$PGENDIR/ila_AntCtrl">
|
|
<File Path="$PSRCDIR/sources_1/ip/ila_AntCtrl/ila_AntCtrl.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ila_AntCtrl/ila_AntCtrl.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310699"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ila_AntCtrl"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ila_2x12x1024" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_2x12x1024" RelGenDir="$PGENDIR/ila_2x12x1024">
|
|
<File Path="$PSRCDIR/sources_1/ip/ila_2x12x1024/ila_2x12x1024.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ila_2x12x1024/ila_2x12x1024.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310722"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ila_2x12x1024"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ila_8x12_2x30_131072" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_8x12_2x30_131072" RelGenDir="$PGENDIR/ila_8x12_2x30_131072">
|
|
<File Path="$PSRCDIR/sources_1/ip/ila_8x12_2x30_131072/ila_8x12_2x30_131072.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ila_8x12_2x30_131072/ila_8x12_2x30_131072.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310754"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ila_8x12_2x30_131072"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ila_cal" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_cal" RelGenDir="$PGENDIR/ila_cal">
|
|
<File Path="$PSRCDIR/sources_1/ip/ila_cal/ila_cal.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ila_cal/ila_cal.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310800"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ila_cal"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ila_rx_pre_sys" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_rx_pre_sys" RelGenDir="$PGENDIR/ila_rx_pre_sys">
|
|
<File Path="$PSRCDIR/sources_1/ip/ila_rx_pre_sys/ila_rx_pre_sys.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ila_rx_pre_sys/ila_rx_pre_sys.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310971"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ila_rx_pre_sys"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ila_rx_pre_ant" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_rx_pre_ant" RelGenDir="$PGENDIR/ila_rx_pre_ant">
|
|
<File Path="$PSRCDIR/sources_1/ip/ila_rx_pre_ant/ila_rx_pre_ant.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ila_rx_pre_ant/ila_rx_pre_ant.xci"/>
|
|
<Attr Name="ImportTime" Val="1707311003"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ila_rx_pre_ant"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ant_clk_gen_stg2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ant_clk_gen_stg2" RelGenDir="$PGENDIR/ant_clk_gen_stg2">
|
|
<File Path="$PSRCDIR/sources_1/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci"/>
|
|
<Attr Name="ImportTime" Val="1707311457"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ant_clk_gen_stg2"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_axi_gpio_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_axi_gpio_0_0" RelGenDir="$PGENDIR/system_bd_axi_gpio_0_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_axi_gpio_0_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_spi_engine_execution_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_spi_engine_execution_0_0" RelGenDir="$PGENDIR/system_bd_spi_engine_execution_0_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_spi_engine_execution_0_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_dlmb_bram_if_cntlr_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_dlmb_bram_if_cntlr_0" RelGenDir="$PGENDIR/system_bd_dlmb_bram_if_cntlr_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_dlmb_bram_if_cntlr_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_ilmb_v10_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_ilmb_v10_0" RelGenDir="$PGENDIR/system_bd_ilmb_v10_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_ilmb_v10_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_rst_clk_wiz_1_100M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_rst_clk_wiz_1_100M_0" RelGenDir="$PGENDIR/system_bd_rst_clk_wiz_1_100M_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_rst_clk_wiz_1_100M_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_axi_spi_engine_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_axi_spi_engine_0_0" RelGenDir="$PGENDIR/system_bd_axi_spi_engine_0_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_axi_spi_engine_0_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_dlmb_v10_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_dlmb_v10_0" RelGenDir="$PGENDIR/system_bd_dlmb_v10_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_dlmb_v10_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ant_clk_gen_stg1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ant_clk_gen_stg1" RelGenDir="$PGENDIR/ant_clk_gen_stg1">
|
|
<File Path="$PSRCDIR/sources_1/ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci"/>
|
|
<Attr Name="ImportTime" Val="1707309163"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ant_clk_gen_stg1"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ad9361_clk_gen_cmos_2t2r" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ad9361_clk_gen_cmos_2t2r" RelGenDir="$PGENDIR/ad9361_clk_gen_cmos_2t2r">
|
|
<File Path="$PSRCDIR/sources_1/ip/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci"/>
|
|
<Attr Name="ImportTime" Val="1707309227"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ad9361_clk_gen_cmos_2t2r"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="fifo_AntCtrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_AntCtrl" RelGenDir="$PGENDIR/fifo_AntCtrl">
|
|
<File Path="$PSRCDIR/sources_1/ip/fifo_AntCtrl/fifo_AntCtrl.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/fifo_AntCtrl/fifo_AntCtrl.xci"/>
|
|
<Attr Name="ImportTime" Val="1707309287"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="fifo_AntCtrl"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="rotate_16b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rotate_16b" RelGenDir="$PGENDIR/rotate_16b">
|
|
<File Path="$PSRCDIR/sources_1/ip/rotate_16b/rotate_16b.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/rotate_16b/rotate_16b.xci"/>
|
|
<Attr Name="ImportTime" Val="1707309395"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="rotate_16b"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="cmpy_12x12" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_12x12" RelGenDir="$PGENDIR/cmpy_12x12">
|
|
<File Path="$PSRCDIR/sources_1/ip/cmpy_12x12/cmpy_12x12.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/cmpy_12x12/cmpy_12x12.xci"/>
|
|
<Attr Name="ImportTime" Val="1707309523"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="cmpy_12x12"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ram_hop_data" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ram_hop_data" RelGenDir="$PGENDIR/ram_hop_data">
|
|
<File Path="$PSRCDIR/sources_1/ip/ram_hop_data/ram_hop_data.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ram_hop_data/ram_hop_data.xci"/>
|
|
<Attr Name="ImportTime" Val="1707309462"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ram_hop_data"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="fifo_accor_cdc" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_accor_cdc" RelGenDir="$PGENDIR/fifo_accor_cdc">
|
|
<File Path="$PSRCDIR/sources_1/ip/fifo_accor_cdc/fifo_accor_cdc.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/fifo_accor_cdc/fifo_accor_cdc.xci"/>
|
|
<Attr Name="ImportTime" Val="1707309575"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="fifo_accor_cdc"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="cmpy_16x12" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_16x12" RelGenDir="$PGENDIR/cmpy_16x12">
|
|
<File Path="$PSRCDIR/sources_1/ip/cmpy_16x12/cmpy_16x12.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/cmpy_16x12/cmpy_16x12.xci"/>
|
|
<Attr Name="ImportTime" Val="1707309607"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="cmpy_16x12"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="rom_hop_data" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rom_hop_data" RelGenDir="$PGENDIR/rom_hop_data">
|
|
<File Path="$PSRCDIR/sources_1/ip/rom_hop_data/rom_hop_data.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/rom_hop_data/rom_hop_data.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310208"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="rom_hop_data"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="fifo_weight_cdc" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_weight_cdc" RelGenDir="$PGENDIR/fifo_weight_cdc">
|
|
<File Path="$PSRCDIR/sources_1/ip/fifo_weight_cdc/fifo_weight_cdc.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/fifo_weight_cdc/fifo_weight_cdc.xci"/>
|
|
<Attr Name="ImportTime" Val="1707309647"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="fifo_weight_cdc"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="vio_rfcontrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_rfcontrl" RelGenDir="$PGENDIR/vio_rfcontrl">
|
|
<File Path="$PSRCDIR/sources_1/ip/vio_rfcontrl/vio_rfcontrl.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/vio_rfcontrl/vio_rfcontrl.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310281"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="vio_rfcontrl"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="vio_ant_test" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_ant_test" RelGenDir="$PGENDIR/vio_ant_test">
|
|
<File Path="$PSRCDIR/sources_1/ip/vio_ant_test/vio_ant_test.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/vio_ant_test/vio_ant_test.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310308"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="vio_ant_test"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="vio_rf_rd" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_rf_rd" RelGenDir="$PGENDIR/vio_rf_rd">
|
|
<File Path="$PSRCDIR/sources_1/ip/vio_rf_rd/vio_rf_rd.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/vio_rf_rd/vio_rf_rd.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310347"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="vio_rf_rd"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="vio_manual_ctrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_manual_ctrl" RelGenDir="$PGENDIR/vio_manual_ctrl">
|
|
<File Path="$PSRCDIR/sources_1/ip/vio_manual_ctrl/vio_manual_ctrl.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/vio_manual_ctrl/vio_manual_ctrl.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310382"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="vio_manual_ctrl"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="vio_phase_comp" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_phase_comp" RelGenDir="$PGENDIR/vio_phase_comp">
|
|
<File Path="$PSRCDIR/sources_1/ip/vio_phase_comp/vio_phase_comp.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/vio_phase_comp/vio_phase_comp.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310428"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="vio_phase_comp"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ila_rfcontrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_rfcontrl" RelGenDir="$PGENDIR/ila_rfcontrl">
|
|
<File Path="$PSRCDIR/sources_1/ip/ila_rfcontrl/ila_rfcontrl.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../vivado_all/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ila_rfcontrl/ila_rfcontrl.xci"/>
|
|
<Attr Name="ImportTime" Val="1707310662"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ila_rfcontrl"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_ilmb_bram_if_cntlr_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_ilmb_bram_if_cntlr_0" RelGenDir="$PGENDIR/system_bd_ilmb_bram_if_cntlr_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_ilmb_bram_if_cntlr_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_lmb_bram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_lmb_bram_0" RelGenDir="$PGENDIR/system_bd_lmb_bram_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_lmb_bram_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_xbar_0" RelGenDir="$PGENDIR/system_bd_xbar_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_xbar_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_microblaze_ps_riscv_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_microblaze_ps_riscv_0" RelGenDir="$PGENDIR/system_bd_microblaze_ps_riscv_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_microblaze_ps_riscv_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_bd_mdm_riscv_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_mdm_riscv_0" RelGenDir="$PGENDIR/system_bd_mdm_riscv_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_bd_mdm_riscv_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="hop_rom" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hop_rom" RelGenDir="$PGENDIR/hop_rom">
|
|
<File Path="$PSRCDIR/sources_1/ip/hop_rom/hop_rom.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="hop_rom"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="hrc_64_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_64_12_025" RelGenDir="$PGENDIR/hrc_64_12_025">
|
|
<File Path="$PSRCDIR/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="hrc_64_12_025"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
</FileSets>
|
|
<Simulators>
|
|
<Simulator Name="XSim">
|
|
<Option Name="Description" Val="Vivado Simulator"/>
|
|
<Option Name="CompiledLib" Val="0"/>
|
|
</Simulator>
|
|
<Simulator Name="ModelSim">
|
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="Questa">
|
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="Xcelium">
|
|
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="VCS">
|
|
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
|
</Simulator>
|
|
<Simulator Name="Riviera">
|
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
|
</Simulator>
|
|
</Simulators>
|
|
<Runs Version="1" Minor="22">
|
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/system_top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_clk_wiz_1_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_clk_wiz_1_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_clk_wiz_1_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_clk_wiz_1_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_clk_wiz_1_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_clk_wiz_1_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_AntCtrl_synth_1" Type="Ft3:Synth" SrcSet="ila_AntCtrl" Part="xc7k410tffg900-2" ConstrsSet="ila_AntCtrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_AntCtrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_AntCtrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_AntCtrl_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_2x12x1024_synth_1" Type="Ft3:Synth" SrcSet="ila_2x12x1024" Part="xc7k410tffg900-2" ConstrsSet="ila_2x12x1024" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_2x12x1024_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_2x12x1024_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_2x12x1024_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_8x12_2x30_131072_synth_1" Type="Ft3:Synth" SrcSet="ila_8x12_2x30_131072" Part="xc7k410tffg900-2" ConstrsSet="ila_8x12_2x30_131072" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_8x12_2x30_131072_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_8x12_2x30_131072_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_8x12_2x30_131072_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_cal_synth_1" Type="Ft3:Synth" SrcSet="ila_cal" Part="xc7k410tffg900-2" ConstrsSet="ila_cal" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_cal_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_cal_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_cal_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_rx_pre_sys_synth_1" Type="Ft3:Synth" SrcSet="ila_rx_pre_sys" Part="xc7k410tffg900-2" ConstrsSet="ila_rx_pre_sys" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_rx_pre_sys_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_rx_pre_sys_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_rx_pre_sys_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_rx_pre_ant_synth_1" Type="Ft3:Synth" SrcSet="ila_rx_pre_ant" Part="xc7k410tffg900-2" ConstrsSet="ila_rx_pre_ant" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_rx_pre_ant_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_rx_pre_ant_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_rx_pre_ant_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ant_clk_gen_stg2_synth_1" Type="Ft3:Synth" SrcSet="ant_clk_gen_stg2" Part="xc7k410tffg900-2" ConstrsSet="ant_clk_gen_stg2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ant_clk_gen_stg2_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg2_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg2_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_axi_gpio_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_axi_gpio_0_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_axi_gpio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_axi_gpio_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_gpio_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_gpio_0_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_spi_engine_execution_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_spi_engine_execution_0_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_spi_engine_execution_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_spi_engine_execution_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_dlmb_bram_if_cntlr_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_dlmb_bram_if_cntlr_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_dlmb_bram_if_cntlr_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_dlmb_bram_if_cntlr_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_bram_if_cntlr_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_bram_if_cntlr_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_ilmb_v10_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_ilmb_v10_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_ilmb_v10_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_ilmb_v10_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_v10_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_v10_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_rst_clk_wiz_1_100M_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_rst_clk_wiz_1_100M_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_rst_clk_wiz_1_100M_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_rst_clk_wiz_1_100M_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_rst_clk_wiz_1_100M_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_rst_clk_wiz_1_100M_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_axi_spi_engine_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_axi_spi_engine_0_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_dlmb_v10_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_dlmb_v10_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_dlmb_v10_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_dlmb_v10_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_v10_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_v10_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ant_clk_gen_stg1_synth_1" Type="Ft3:Synth" SrcSet="ant_clk_gen_stg1" Part="xc7k410tffg900-2" ConstrsSet="ant_clk_gen_stg1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ant_clk_gen_stg1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg1_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ad9361_clk_gen_cmos_2t2r_synth_1" Type="Ft3:Synth" SrcSet="ad9361_clk_gen_cmos_2t2r" Part="xc7k410tffg900-2" ConstrsSet="ad9361_clk_gen_cmos_2t2r" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ad9361_clk_gen_cmos_2t2r_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_clk_gen_cmos_2t2r_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_clk_gen_cmos_2t2r_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="fifo_AntCtrl_synth_1" Type="Ft3:Synth" SrcSet="fifo_AntCtrl" Part="xc7k410tffg900-2" ConstrsSet="fifo_AntCtrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_AntCtrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_AntCtrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_AntCtrl_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="rotate_16b_synth_1" Type="Ft3:Synth" SrcSet="rotate_16b" Part="xc7k410tffg900-2" ConstrsSet="rotate_16b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/rotate_16b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/rotate_16b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/rotate_16b_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="cmpy_12x12_synth_1" Type="Ft3:Synth" SrcSet="cmpy_12x12" Part="xc7k410tffg900-2" ConstrsSet="cmpy_12x12" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_12x12_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_12x12_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_12x12_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ram_hop_data_synth_1" Type="Ft3:Synth" SrcSet="ram_hop_data" Part="xc7k410tffg900-2" ConstrsSet="ram_hop_data" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ram_hop_data_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ram_hop_data_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ram_hop_data_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="fifo_accor_cdc_synth_1" Type="Ft3:Synth" SrcSet="fifo_accor_cdc" Part="xc7k410tffg900-2" ConstrsSet="fifo_accor_cdc" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_accor_cdc_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_accor_cdc_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_accor_cdc_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="cmpy_16x12_synth_1" Type="Ft3:Synth" SrcSet="cmpy_16x12" Part="xc7k410tffg900-2" ConstrsSet="cmpy_16x12" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_16x12_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_16x12_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_16x12_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="rom_hop_data_synth_1" Type="Ft3:Synth" SrcSet="rom_hop_data" Part="xc7k410tffg900-2" ConstrsSet="rom_hop_data" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/rom_hop_data_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/rom_hop_data_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/rom_hop_data_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="fifo_weight_cdc_synth_1" Type="Ft3:Synth" SrcSet="fifo_weight_cdc" Part="xc7k410tffg900-2" ConstrsSet="fifo_weight_cdc" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_weight_cdc_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_weight_cdc_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_weight_cdc_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_rfcontrl_synth_1" Type="Ft3:Synth" SrcSet="vio_rfcontrl" Part="xc7k410tffg900-2" ConstrsSet="vio_rfcontrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_rfcontrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_rfcontrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_rfcontrl_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_ant_test_synth_1" Type="Ft3:Synth" SrcSet="vio_ant_test" Part="xc7k410tffg900-2" ConstrsSet="vio_ant_test" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_ant_test_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_ant_test_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_ant_test_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_rf_rd_synth_1" Type="Ft3:Synth" SrcSet="vio_rf_rd" Part="xc7k410tffg900-2" ConstrsSet="vio_rf_rd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_rf_rd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_rf_rd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_rf_rd_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_manual_ctrl_synth_1" Type="Ft3:Synth" SrcSet="vio_manual_ctrl" Part="xc7k410tffg900-2" ConstrsSet="vio_manual_ctrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_manual_ctrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_phase_comp_synth_1" Type="Ft3:Synth" SrcSet="vio_phase_comp" Part="xc7k410tffg900-2" ConstrsSet="vio_phase_comp" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_phase_comp_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_phase_comp_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_phase_comp_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_rfcontrl_synth_1" Type="Ft3:Synth" SrcSet="ila_rfcontrl" Part="xc7k410tffg900-2" ConstrsSet="ila_rfcontrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_rfcontrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_rfcontrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_rfcontrl_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_ilmb_bram_if_cntlr_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_ilmb_bram_if_cntlr_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_ilmb_bram_if_cntlr_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_ilmb_bram_if_cntlr_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_bram_if_cntlr_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_bram_if_cntlr_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_lmb_bram_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_lmb_bram_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_lmb_bram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_lmb_bram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_lmb_bram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_lmb_bram_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_xbar_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_microblaze_ps_riscv_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_microblaze_ps_riscv_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_microblaze_ps_riscv_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_microblaze_ps_riscv_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_microblaze_ps_riscv_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_microblaze_ps_riscv_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_mdm_riscv_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_mdm_riscv_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_mdm_riscv_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_mdm_riscv_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_mdm_riscv_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_mdm_riscv_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="hop_rom_synth_1" Type="Ft3:Synth" SrcSet="hop_rom" Part="xc7k410tffg900-2" ConstrsSet="hop_rom" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hop_rom_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="hrc_64_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_64_12_025" Part="xc7k410tffg900-2" ConstrsSet="hrc_64_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_64_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 16 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_clk_wiz_1_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_clk_wiz_1_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_clk_wiz_1_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_clk_wiz_1_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_clk_wiz_1_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_AntCtrl_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_AntCtrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_AntCtrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_AntCtrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_AntCtrl_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_2x12x1024_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_2x12x1024" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_2x12x1024_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_2x12x1024_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_2x12x1024_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_8x12_2x30_131072_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_8x12_2x30_131072" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_8x12_2x30_131072_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_8x12_2x30_131072_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_8x12_2x30_131072_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_cal_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_cal" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_cal_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_cal_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_cal_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_rx_pre_sys_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_rx_pre_sys" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_rx_pre_sys_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_rx_pre_sys_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_rx_pre_sys_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_rx_pre_ant_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_rx_pre_ant" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_rx_pre_ant_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_rx_pre_ant_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_rx_pre_ant_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ant_clk_gen_stg2_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ant_clk_gen_stg2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ant_clk_gen_stg2_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg2_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg2_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_axi_gpio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_axi_gpio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_axi_gpio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_gpio_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_gpio_0_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_spi_engine_execution_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_spi_engine_execution_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_spi_engine_execution_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_dlmb_bram_if_cntlr_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_dlmb_bram_if_cntlr_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_dlmb_bram_if_cntlr_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_bram_if_cntlr_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_bram_if_cntlr_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_ilmb_v10_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_ilmb_v10_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_ilmb_v10_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_v10_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_v10_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_rst_clk_wiz_1_100M_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_rst_clk_wiz_1_100M_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_rst_clk_wiz_1_100M_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_rst_clk_wiz_1_100M_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_rst_clk_wiz_1_100M_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_axi_spi_engine_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_dlmb_v10_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_dlmb_v10_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_dlmb_v10_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_v10_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_v10_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ant_clk_gen_stg1_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ant_clk_gen_stg1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ant_clk_gen_stg1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg1_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ad9361_clk_gen_cmos_2t2r_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ad9361_clk_gen_cmos_2t2r" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ad9361_clk_gen_cmos_2t2r_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_clk_gen_cmos_2t2r_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_clk_gen_cmos_2t2r_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="fifo_AntCtrl_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="fifo_AntCtrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_AntCtrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_AntCtrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_AntCtrl_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="rotate_16b_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="rotate_16b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="rotate_16b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/rotate_16b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/rotate_16b_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="cmpy_12x12_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="cmpy_12x12" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_12x12_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_12x12_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_12x12_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ram_hop_data_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ram_hop_data" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ram_hop_data_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ram_hop_data_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ram_hop_data_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="fifo_accor_cdc_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="fifo_accor_cdc" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_accor_cdc_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_accor_cdc_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_accor_cdc_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="cmpy_16x12_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="cmpy_16x12" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_16x12_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_16x12_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_16x12_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="rom_hop_data_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="rom_hop_data" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="rom_hop_data_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/rom_hop_data_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/rom_hop_data_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="fifo_weight_cdc_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="fifo_weight_cdc" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_weight_cdc_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_weight_cdc_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_weight_cdc_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_rfcontrl_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_rfcontrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_rfcontrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_rfcontrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_rfcontrl_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_ant_test_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_ant_test" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_ant_test_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_ant_test_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_ant_test_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_rf_rd_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_rf_rd" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_rf_rd_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_rf_rd_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_rf_rd_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_manual_ctrl_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_manual_ctrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_manual_ctrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_phase_comp_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_phase_comp" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_phase_comp_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_phase_comp_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_phase_comp_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_rfcontrl_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_rfcontrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_rfcontrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_rfcontrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_rfcontrl_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_ilmb_bram_if_cntlr_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_ilmb_bram_if_cntlr_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_ilmb_bram_if_cntlr_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_bram_if_cntlr_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_bram_if_cntlr_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_lmb_bram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_lmb_bram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_lmb_bram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_lmb_bram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_lmb_bram_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_microblaze_ps_riscv_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_microblaze_ps_riscv_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_microblaze_ps_riscv_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_microblaze_ps_riscv_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_microblaze_ps_riscv_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_bd_mdm_riscv_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_mdm_riscv_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_mdm_riscv_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_mdm_riscv_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_mdm_riscv_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="hop_rom_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="hop_rom" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hop_rom_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="hrc_64_12_025_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="hrc_64_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_64_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
</Runs>
|
|
<Board/>
|
|
<DashboardSummary Version="1" Minor="0">
|
|
<Dashboards>
|
|
<Dashboard Name="default_dashboard">
|
|
<Gadgets>
|
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
|
</Gadget>
|
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
|
</Gadget>
|
|
</Gadgets>
|
|
</Dashboard>
|
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
|
</Dashboards>
|
|
</DashboardSummary>
|
|
</Project>
|