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update sjl_df_rfsoc_df project, phy test is passed

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josh
2024-10-30 23:16:28 +08:00
parent 923d5c439f
commit 217de5babb
25 changed files with 14609 additions and 7611 deletions
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sjl_dj_rfsoc_df/vitis_classic_autobuild/source/config/app_config.h
+5 -3
View File
@@ -105,7 +105,9 @@
//#define AD9694
// RFSoC Configuration
#ifdef RFSOC
#define RFDC_DEVICE_ID XPAR_XRFDC_0_DEVICE_ID
#endif
// AD9361 Configuration
#define SPI_INTERFACE_SPI_ENGINE
@@ -123,8 +125,8 @@
#define AD9361_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define AD9361_SPI_ENGINE_DATA_WIDTH 8
#define AD9361_SPI_ENGINE_CS_DELAY 3
#define AD9361_SPI_CS_AD9361_1 0x01
#define AD9361_SPI_CS_AD9361_2 0x02
#define AD9361_1_SPI_CS 0x01
#define AD9361_2_SPI_CS 0x02
#define AD9361_TIMEOUT_TH 2000
// -- AD9361 GPIO Configurations
#define AD9361_GPIO_DEVICE_ID 0
@@ -201,7 +203,7 @@ typedef enum
#define HMC7044_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define HMC7044_SPI_ENGINE_DATA_WIDTH 8
#define HMC7044_SPI_ENGINE_CS_DELAY 3
#define HMC7044_SPI_CS_HMC7044 0x00
#define HMC7044_SPI_CS 0x00
// AD9528 Configurations
#define AD9528_GPIO_DEVICE_ID 0
sjl_dj_rfsoc_df/vitis_classic_autobuild/source/dev_profile/ad9361_profile.c
+1 -1
View File
@@ -273,7 +273,7 @@ AD9361_InitParam ad9361_default_init_param = {
{
.device_id = AD9361_SPI_DEVICE_ID,
.mode = SPI_MODE_1,
.chip_select = AD9361_SPI_CS_AD9361_1,
.chip_select = AD9361_1_SPI_CS,
.platform_ops = &spi_eng_platform_ops,
.extra = &spi_engine_param
},
sjl_dj_rfsoc_df/vitis_classic_autobuild/source/dev_profile/ad9361_reg_profile.c
+2 -2
View File
@@ -25,7 +25,7 @@ static struct spi_init_param ad9361_1_reg_spi_init = {
.device_id = AD9361_SPI_DEVICE_ID,
.max_speed_hz = AD9361_SPI_ENGINE_MAX_SPEED,
.mode = SPI_MODE_1,
.chip_select = AD9361_SPI_CS_AD9361_1,
.chip_select = AD9361_1_SPI_CS,
.platform_ops = &spi_eng_platform_ops,
.extra = &spi_engine_param
};
@@ -46,7 +46,7 @@ static struct spi_init_param ad9361_2_reg_spi_init = {
.device_id = AD9361_SPI_DEVICE_ID,
.max_speed_hz = AD9361_SPI_ENGINE_MAX_SPEED,
.mode = SPI_MODE_1,
.chip_select = AD9361_SPI_CS_AD9361_2,
.chip_select = AD9361_2_SPI_CS,
.platform_ops = &spi_eng_platform_ops,
.extra = &spi_engine_param
};
sjl_dj_rfsoc_df/vitis_classic_autobuild/source/dev_profile/hmc7044_profile.c
+1 -1
View File
@@ -23,7 +23,7 @@ static struct spi_init_param hmc7044_spi_init_param = {
.device_id = HMC7044_SPI_DEVICE_ID,
.max_speed_hz = HMC7044_SPI_ENGINE_MAX_SPEED,
.mode = SPI_MODE_4,
.chip_select = HMC7044_SPI_CS_HMC7044,
.chip_select = HMC7044_SPI_CS,
.platform_ops = &spi_eng_platform_ops,
.extra = &spi_engine_param
};
sjl_dj_rfsoc_df/vitis_classic_autobuild/source/hwconfig.c
+99 -15
View File
@@ -20,7 +20,6 @@
#include <stdbool.h>
// Xilinx
#include "xgpiops.h"
#include "xrfdc.h"
#include "drivers/axi_core/spi_engine/spi_engine.h"
// App
#include "common.h"
@@ -31,6 +30,10 @@
#include "config/app_config.h"
#include "dev_profile/dev_profile.h"
#ifdef RFSOC
#include "xrfdc.h"
#endif
/************************** Function Prototypes ******************************/
/*********************** Driver Instance Definitions **************************/
static struct hmc7044_dev *hmc7044_inst;
@@ -45,7 +48,9 @@ static struct ad9653_dev *ad9653_inst;
static struct ad9694_dev *ad9694_inst;
XGpioPs Gpio;
#ifdef RFSOC
XRFdc RFdc;
#endif
/*****************************************************************************/
/**
@@ -69,20 +74,6 @@ int32_t Hardware_Init(void)
return FAILURE;
}
#ifdef RFSOC
/**********************************************************/
/************* RF Data Converter Configuration ************/
/**********************************************************/
// rf data converter initialization
XRFdc_Config *RFdc_ConfigPtr;
RFdc_ConfigPtr = XRFdc_LookupConfig(RFDC_DEVICE_ID);
Status = XRFdc_CfgInitialize(&RFdc, RFdc_ConfigPtr);
if (Status != XST_SUCCESS)
{
return XST_FAILURE;
}
#endif
#ifdef HMC7044
/**********************************************************/
/****************** HMC7044 Configuration *****************/
@@ -394,6 +385,99 @@ int32_t Hardware_Init(void)
// ad9694_read(ad9694_inst,0x008,&reg0008);
// ad9694_read(ad9694_inst,0x56F,&reg056F);
// ad9694_read(ad9694_inst,0x571,&reg0571);
#endif
#ifdef RFSOC
/**********************************************************/
/************* RF Data Converter Configuration ************/
/**********************************************************/
// rf data converter initialization
XRFdc_Config *RFdc_ConfigPtr;
RFdc_ConfigPtr = XRFdc_LookupConfig(RFDC_DEVICE_ID);
Status = XRFdc_CfgInitialize(&RFdc, RFdc_ConfigPtr);
if (Status != XST_SUCCESS)
{
return XST_FAILURE;
}
mdelay(100);
/*
* DAC Mapping:
* Number Tile Block
* 1 (VOUT_00) 228 (XRFDC_TILE_ID0) DAC 0/DUC 0 (XRFDC_BLK_ID0)
* 2 (VOUT_02) 228 (XRFDC_TILE_ID0) DAC 1/DUC 2 (XRFDC_BLK_ID2)
* 3 (VOUT_10) 229 (XRFDC_TILE_ID1) DAC 1/DUC 0 (XRFDC_BLK_ID0)
* 4 (VOUT_12) 229 (XRFDC_TILE_ID1) DAC 1/DUC 2 (XRFDC_BLK_ID2)
* 5 (VOUT_20) 230 (XRFDC_TILE_ID2) DAC 0/DUC 0 (XRFDC_BLK_ID0)
* 6 (VOUT_22) 230 (XRFDC_TILE_ID2) DAC 1/DUC 2 (XRFDC_BLK_ID2)
* 7 (VOUT_30) 231 (XRFDC_TILE_ID3) DAC 0/DUC 0 (XRFDC_BLK_ID0)
* 8 (VOUT_32) 231 (XRFDC_TILE_ID3) DAC 1/DUC 2 (XRFDC_BLK_ID2)
*
*/
// get & set mixer settings
XRFdc_Mixer_Settings Mixer_Settings_DAC;
// 3rd channel
Status = XRFdc_GetMixerSettings(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
XRFDC_BLK_ID0, &Mixer_Settings_DAC);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Mixer_Settings_DAC.Freq = 1500;
Status = XRFdc_SetMixerSettings(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
XRFDC_BLK_ID0, &Mixer_Settings_DAC);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = XRFdc_UpdateEvent(&RFdc, XRFDC_DAC_TILE, XRFDC_TILE_ID1,
XRFDC_BLK_ID0, XRFDC_EVENT_MIXER);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* ADC Mapping:
* Number Tile Block
* 1 (VIN0_01) 224 (XRFDC_TILE_ID0) ADC 0 (XRFDC_BLK_ID0)
* 2 (VIN0_12) 224 (XRFDC_TILE_ID0) ADC 1 (XRFDC_BLK_ID1)
* 3 (VIN1_01) 225 (XRFDC_TILE_ID1) ADC 0 (XRFDC_BLK_ID0)
* 4 (VIN1_23) 225 (XRFDC_TILE_ID1) ADC 1 (XRFDC_BLK_ID1)
* 5 (VIN2_01) 226 (XRFDC_TILE_ID2) ADC 0 (XRFDC_BLK_ID0)
* 6 (VIN2_23) 227 (XRFDC_TILE_ID2) ADC 1 (XRFDC_BLK_ID1)
* 7 (VIN3_01) 224 (XRFDC_TILE_ID0) ADC 0 (XRFDC_BLK_ID0)
* 8 (VIN3_23) 227 (XRFDC_TILE_ID3) ADC 1 (XRFDC_BLK_ID1)
*
*/
// get & set mixer settings
XRFdc_Mixer_Settings Mixer_Settings_ADC;
// 3rd channel
Status = XRFdc_GetMixerSettings(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
XRFDC_BLK_ID0, &Mixer_Settings_ADC);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Mixer_Settings_ADC.Freq = 1500;
Mixer_Settings_ADC.EventSource = XRFDC_EVNT_SRC_TILE;
Status = XRFdc_SetMixerSettings(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
XRFDC_BLK_ID0, &Mixer_Settings_ADC);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = XRFdc_UpdateEvent(&RFdc, XRFDC_ADC_TILE, XRFDC_TILE_ID1,
XRFDC_BLK_ID0, XRFDC_EVENT_MIXER);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif
DBG_INFO("HDWR: Configuration Done.\n");