diff --git a/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.runs/impl_1/system_top.bit b/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.runs/impl_1/system_top.bit
index c758142..3b73ec7 100644
--- a/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.runs/impl_1/system_top.bit
+++ b/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.runs/impl_1/system_top.bit
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:95611fc20324fe1b2c15cd8a2ddd49299b6c5898b29c327f15e37e4307018c30
-size 34437472
+oid sha256:9c500f1bfd2cc892115642815d34810cee2e11521760a5dd86f151e679fc7287
+size 34437474
diff --git a/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/constrs_1/imports/new/dj_47dr.xdc b/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/constrs_1/imports/new/dj_47dr.xdc
index 792a5a9..2df684d 100644
--- a/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/constrs_1/imports/new/dj_47dr.xdc
+++ b/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/constrs_1/imports/new/dj_47dr.xdc
@@ -16,12 +16,23 @@ set_property  -dict  {PACKAGE_PIN G13   IOSTANDARD LVCMOS33}  [get_ports lmx_dac
 set_property  -dict  {PACKAGE_PIN J14   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_mosi       ] ;# LMX_RF_DAC_SDI
 set_property  -dict  {PACKAGE_PIN H15   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_miso       ] ;# LMX_RF_DAC_SDO
 
-#RS485
+# RS485
 set_property  -dict  {PACKAGE_PIN J12   IOSTANDARD LVCMOS33}  [get_ports RS_485_RxD        		] ;# 47DR_RS422_RO_1
 set_property  -dict  {PACKAGE_PIN K12   IOSTANDARD LVCMOS33}  [get_ports RS_485_RE_n      		] ;# 47DR_RS422_RE_B_1
 set_property  -dict  {PACKAGE_PIN K10   IOSTANDARD LVCMOS33}  [get_ports RS_485_TxD       		] ;# 47DR_RS422_DI_1
 set_property  -dict  {PACKAGE_PIN K11   IOSTANDARD LVCMOS33}  [get_ports RS_485_DE       	    ] ;# 47DR_RS422_DE
 
+# DEBUG IO
+set_property  -dict  {PACKAGE_PIN E9    IOSTANDARD LVCMOS33}  [get_ports debug_io_1             ] ;# 47DR_LVCMOS_1
+set_property  -dict  {PACKAGE_PIN E10   IOSTANDARD LVCMOS33}  [get_ports debug_io_2             ] ;# 47DR_LVCMOS_2
+set_property  -dict  {PACKAGE_PIN D11   IOSTANDARD LVCMOS33}  [get_ports debug_io_3             ] ;# 47DR_LVCMOS_3
+set_property  -dict  {PACKAGE_PIN E11   IOSTANDARD LVCMOS33}  [get_ports debug_io_4             ] ;# 47DR_LVCMOS_4
+set_property  -dict  {PACKAGE_PIN C9    IOSTANDARD LVCMOS33}  [get_ports debug_io_5             ] ;# 47DR_LVCMOS_5
+set_property  -dict  {PACKAGE_PIN D9    IOSTANDARD LVCMOS33}  [get_ports debug_io_6             ] ;# 47DR_LVCMOS_6
+set_property  -dict  {PACKAGE_PIN A9    IOSTANDARD LVCMOS33}  [get_ports debug_io_7             ] ;# 47DR_LVCMOS_7
+set_property  -dict  {PACKAGE_PIN A10   IOSTANDARD LVCMOS33}  [get_ports debug_io_8             ] ;# 47DR_LVCMOS_8
+set_property  -dict  {PACKAGE_PIN B10   IOSTANDARD LVCMOS33}  [get_ports debug_io_9             ] ;# 47DR_LVCMOS_9
+
 # Route HDGC clock through BUFG to adjacent CMT
 #set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O]
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_wrapper_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O]
diff --git a/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/imports/new/system_top.v b/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/imports/new/system_top.v
index d1b0407..dc4a620 100644
--- a/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/imports/new/system_top.v
+++ b/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/imports/new/system_top.v
@@ -110,10 +110,19 @@ module system_top
     input       RS_485_RxD          ,
     output      RS_485_RE_n         ,
     output      RS_485_TxD          ,
-    output      RS_485_DE
+    output      RS_485_DE           ,
 	// *************************************************************************
     // ******************************* DEBUG IO ********************************
     // *************************************************************************
+	output      debug_io_1          ,
+	output      debug_io_2          ,
+	output      debug_io_3          ,
+	output      debug_io_4          ,
+	output      debug_io_5          ,
+	output      debug_io_6          ,
+	output      debug_io_7          ,
+	output      debug_io_8          ,
+	output      debug_io_9
 );
 
 
diff --git a/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/utils_1/imports/synth_1/system_top.dcp b/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/utils_1/imports/synth_1/system_top.dcp
index 468d4e8..d096a90 100644
--- a/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/utils_1/imports/synth_1/system_top.dcp
+++ b/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/utils_1/imports/synth_1/system_top.dcp
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:79526b7248fdbe3db88795843b495384be65ab16d671ac4f0e749410cc04e5f4
-size 35546813
+oid sha256:d59872597c72d011b18f91c1cff0044a7ce8d3533a4d0b757b53d9d037d5db3a
+size 37351278
diff --git a/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.xpr b/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.xpr
index a80bcef..0d5a1d7 100644
--- a/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.xpr
+++ b/sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.xpr
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1.2 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
 <!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
@@ -4414,9 +4414,7 @@
     </Run>
     <Run Id="system_bd_wrapper_auto_pc_4_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_auto_pc_4" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_4" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_auto_pc_4_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -4426,9 +4424,7 @@
     </Run>
     <Run Id="system_bd_wrapper_auto_pc_3_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_auto_pc_3" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_3" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_auto_pc_3_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -6105,9 +6101,7 @@
     </Run>
     <Run Id="system_bd_wrapper_auto_pc_4_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_4" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_auto_pc_4_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -6124,9 +6118,7 @@
     </Run>
     <Run Id="system_bd_wrapper_auto_pc_3_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_3" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_auto_pc_3_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
diff --git a/sjl_dj_rfsoc_df/system_top.xsa b/sjl_dj_rfsoc_df/system_top.xsa
index 1bdc44c..061700a 100644
--- a/sjl_dj_rfsoc_df/system_top.xsa
+++ b/sjl_dj_rfsoc_df/system_top.xsa
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:5199936622387abe23d1df33b21ec140b6d5bc2bf2e06445ddfbae3207f7ebf3
-size 6262272
+oid sha256:7882a0e92d07448c930336a3f2dc2f8876e4176beb3d7f9a22a6845801d09e8b
+size 6295037