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feat: 升级到2024.1.2;增加将485引到调试口,增加宣统;ps增加485信号观测

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josh
2024-11-05 13:41:55 +08:00
parent 461332434c
commit b67a3e75e8
42 changed files with 2119 additions and 1355 deletions
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sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.runs/impl_1/debug_nets.ltx
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sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.runs/impl_1/system_top.bit
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sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.runs/impl_1/system_top.ltx
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sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_ant_beam_bram_0/system_bd_wrapper_ant_beam_bram_0.xci
+1 -1
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@@ -179,7 +179,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_ant_beam_bram_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_ant_beam_bram_ctrl_0/system_bd_wrapper_ant_beam_bram_ctrl_0.xci
+1 -1
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@@ -64,7 +64,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_ant_beam_bram_ctrl_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_ant_config_bram_0/system_bd_wrapper_ant_config_bram_0.xci
+1 -1
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@@ -179,7 +179,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_ant_config_bram_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_ant_config_bram_ctrl_0/system_bd_wrapper_ant_config_bram_ctrl_0.xci
+1 -1
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@@ -64,7 +64,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_ant_config_bram_ctrl_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_0/system_bd_wrapper_auto_pc_0.xci
+3 -3
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@@ -4,7 +4,7 @@
"xci_name": "system_bd_wrapper_auto_pc_0",
"cell_name": "zynq_ultra_ps_axi_periph/m00_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"gen_directory": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_0",
"parameters": {
"component_parameters": {
@@ -56,12 +56,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "31" } ],
"IPREVISION": [ { "value": "32" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_0" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_1/system_bd_wrapper_auto_pc_1.xci
+3 -3
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@@ -4,7 +4,7 @@
"xci_name": "system_bd_wrapper_auto_pc_1",
"cell_name": "zynq_ultra_ps_axi_periph/m05_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"gen_directory": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_1",
"parameters": {
"component_parameters": {
@@ -56,12 +56,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "31" } ],
"IPREVISION": [ { "value": "32" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_1" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_2/system_bd_wrapper_auto_pc_2.xci
+3 -3
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@@ -4,7 +4,7 @@
"xci_name": "system_bd_wrapper_auto_pc_2",
"cell_name": "zynq_ultra_ps_axi_periph/m06_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"gen_directory": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_2",
"parameters": {
"component_parameters": {
@@ -56,12 +56,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "31" } ],
"IPREVISION": [ { "value": "32" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_2" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_3/system_bd_wrapper_auto_pc_3.xci
+3 -3
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@@ -4,7 +4,7 @@
"xci_name": "system_bd_wrapper_auto_pc_3",
"cell_name": "zynq_ultra_ps_axi_periph/m07_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"gen_directory": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_3",
"parameters": {
"component_parameters": {
@@ -56,12 +56,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "31" } ],
"IPREVISION": [ { "value": "32" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_3" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_4/system_bd_wrapper_auto_pc_4.xci
+3 -3
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@@ -4,7 +4,7 @@
"xci_name": "system_bd_wrapper_auto_pc_4",
"cell_name": "zynq_ultra_ps_axi_periph/m08_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"gen_directory": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_4",
"parameters": {
"component_parameters": {
@@ -56,12 +56,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "31" } ],
"IPREVISION": [ { "value": "32" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_4" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_5/system_bd_wrapper_auto_pc_5.xci
+4 -4
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@@ -4,7 +4,7 @@
"xci_name": "system_bd_wrapper_auto_pc_5",
"cell_name": "zynq_ultra_ps_axi_periph/m09_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"gen_directory": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_5",
"parameters": {
"component_parameters": {
@@ -56,12 +56,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "31" } ],
"IPREVISION": [ { "value": "32" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_5" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
@@ -137,7 +137,7 @@
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "16", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "16", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "13", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_6/system_bd_wrapper_auto_pc_6.xci
+4 -4
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@@ -4,7 +4,7 @@
"xci_name": "system_bd_wrapper_auto_pc_6",
"cell_name": "zynq_ultra_ps_axi_periph/m10_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"gen_directory": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_6",
"parameters": {
"component_parameters": {
@@ -56,12 +56,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "31" } ],
"IPREVISION": [ { "value": "32" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_auto_pc_6" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
@@ -137,7 +137,7 @@
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "16", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "16", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "40", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_axi_spi_engine_0_2/system_bd_wrapper_axi_spi_engine_0_2.xci
+1 -1
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@@ -65,7 +65,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_axi_spi_engine_0_2" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_axi_timer_0_0/system_bd_wrapper_axi_timer_0_0.xci
+3 -3
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@@ -4,7 +4,7 @@
"xci_name": "system_bd_wrapper_axi_timer_0_0",
"cell_name": "axi_timer",
"component_reference": "xilinx.com:ip:axi_timer:2.0",
"ip_revision": "33",
"ip_revision": "34",
"gen_directory": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_axi_timer_0_0",
"parameters": {
"component_parameters": {
@@ -44,12 +44,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "33" } ],
"IPREVISION": [ { "value": "34" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_axi_timer_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_clk_wiz_pl_clk_0/system_bd_wrapper_clk_wiz_pl_clk_0.xci
+1 -1
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@@ -604,7 +604,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_clk_wiz_pl_clk_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_rst_zynq_ultra_ps_99M_0/system_bd_wrapper_rst_zynq_ultra_ps_99M_0.xci
+1 -1
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@@ -52,7 +52,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_rst_zynq_ultra_ps_99M_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_rx_frame_bram_0/system_bd_wrapper_rx_frame_bram_0.xci
+1 -1
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@@ -179,7 +179,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_rx_frame_bram_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_rx_frame_bram_ctrl_0/system_bd_wrapper_rx_frame_bram_ctrl_0.xci
+1 -1
View File
@@ -64,7 +64,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_rx_frame_bram_ctrl_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_spi_engine_execution_0_1/system_bd_wrapper_spi_engine_execution_0_1.xci
+1 -1
View File
@@ -49,7 +49,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_spi_engine_execution_0_1" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_system_ila_0_0/system_bd_wrapper_system_ila_0_0.xci
+9 -7
View File
@@ -4,7 +4,7 @@
"xci_name": "system_bd_wrapper_system_ila_0_0",
"cell_name": "system_ila",
"component_reference": "xilinx.com:ip:system_ila:1.1",
"ip_revision": "17",
"ip_revision": "18",
"gen_directory": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_system_ila_0_0",
"parameters": {
"component_parameters": {
@@ -1546,8 +1546,8 @@
"C_PROBE4_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE3_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE2_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE1_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE0_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE1_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE0_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE1023_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_PROBE1022_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_PROBE1021_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
@@ -2572,7 +2572,7 @@
"C_PROBE1_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_PROBE0_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "1024", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "system_bd_wrapper_system_ila_0_0", "resolve_type": "user", "usage": "all" } ],
"C_PROBE70_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
@@ -3653,7 +3653,7 @@
"C_SLOT_13_INTF_TYPE": [ { "value": "xilinx.com:interface:aximm_rtl:1.0", "resolve_type": "user", "usage": "all" } ],
"C_SLOT_14_INTF_TYPE": [ { "value": "xilinx.com:interface:aximm_rtl:1.0", "resolve_type": "user", "usage": "all" } ],
"C_SLOT_15_INTF_TYPE": [ { "value": "xilinx.com:interface:aximm_rtl:1.0", "resolve_type": "user", "usage": "all" } ],
"C_MON_TYPE": [ { "value": "INTERFACE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"C_MON_TYPE": [ { "value": "MIX", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"C_SLOT_2_AXI_ARUSER_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_SLOT_2_AXI_RUSER_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_SLOT_2_AXI_AWUSER_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -3854,18 +3854,20 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "17" } ],
"IPREVISION": [ { "value": "18" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_system_ila_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"clk": [ { "direction": "in" } ],
"probe0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"probe1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"SLOT_0_AXI_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"SLOT_0_AXI_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
"SLOT_0_AXI_awvalid": [ { "direction": "in", "driver_value": "0" } ],
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_system_management_wiz_0_0/system_bd_wrapper_system_management_wiz_0_0.xci
+1 -1
View File
@@ -912,7 +912,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_system_management_wiz_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_systembus_0_0/system_bd_wrapper_systembus_0_0.xci
+1 -1
View File
@@ -51,7 +51,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_systembus_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_tx_frame_bram_0/system_bd_wrapper_tx_frame_bram_0.xci
+1 -1
View File
@@ -179,7 +179,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_tx_frame_bram_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_tx_frame_bram_ctrl_0/system_bd_wrapper_tx_frame_bram_ctrl_0.xci
+1 -1
View File
@@ -64,7 +64,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_tx_frame_bram_ctrl_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_usp_rf_data_converter_0_0/system_bd_wrapper_usp_rf_data_converter_0_0.xci
+1 -1
View File
@@ -1673,7 +1673,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_usp_rf_data_converter_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_util_bufg_pl_clk_0/system_bd_wrapper_util_bufg_pl_clk_0.xci
+1 -1
View File
@@ -50,7 +50,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_util_bufg_pl_clk_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_util_ds_buf_pl_clk_0/system_bd_wrapper_util_ds_buf_pl_clk_0.xci
+1 -1
View File
@@ -50,7 +50,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_util_ds_buf_pl_clk_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_util_ds_buf_pl_sysref_0/system_bd_wrapper_util_ds_buf_pl_sysref_0.xci
+1 -1
View File
@@ -50,7 +50,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_util_ds_buf_pl_sysref_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_xbar_0/system_bd_wrapper_xbar_0.xci
+67 -67
View File
@@ -2,9 +2,9 @@
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_wrapper_xbar_0",
"cell_name": "zynq_ultra_ps_axi_periph/xbar",
"cell_name": "zynq_ultra_ps_axi_periph_upgraded_ipi/xbar",
"component_reference": "xilinx.com:ip:axi_crossbar:2.1",
"ip_revision": "32",
"ip_revision": "33",
"gen_directory": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_xbar_0",
"parameters": {
"component_parameters": {
@@ -1256,12 +1256,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "32" } ],
"IPREVISION": [ { "value": "33" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_xbar_0" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
@@ -1358,7 +1358,7 @@
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
@@ -2195,37 +2195,37 @@
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "master",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"ID_WIDTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_LOCK": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_QOS": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_wrapper_zynq_ultra_ps_e_0_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_wrapper_zynq_ultra_ps_e_0_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"AWID": [ { "physical_name": "m_axi_awid", "physical_left": "159", "physical_right": "144" } ],
@@ -2276,37 +2276,37 @@
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "master",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"ID_WIDTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_LOCK": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_QOS": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_wrapper_zynq_ultra_ps_e_0_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_wrapper_zynq_ultra_ps_e_0_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"AWID": [ { "physical_name": "m_axi_awid", "physical_left": "175", "physical_right": "160" } ],
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_xlconcat_0_0/system_bd_wrapper_xlconcat_0_0.xci
+1 -1
View File
@@ -293,7 +293,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_xlconcat_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_xlconstant_0_0/system_bd_wrapper_xlconstant_0_0.xci
+1 -1
View File
@@ -37,7 +37,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_xlconstant_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_xpm_cdc_gen_mts_sysref_0/system_bd_wrapper_xpm_cdc_gen_mts_sysref_0.xci
+1 -1
View File
@@ -63,7 +63,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_xpm_cdc_gen_mts_sysref_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_xpm_cdc_gen_pl_sysref_0/system_bd_wrapper_xpm_cdc_gen_pl_sysref_0.xci
+1 -1
View File
@@ -63,7 +63,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_xpm_cdc_gen_pl_sysref_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_zynq_ultra_ps_axi_periph_0/system_bd_wrapper_zynq_ultra_ps_axi_periph_0.xci
+3 -3
View File
@@ -4,7 +4,7 @@
"xci_name": "system_bd_wrapper_zynq_ultra_ps_axi_periph_0",
"cell_name": "zynq_ultra_ps_axi_periph",
"component_reference": "xilinx.com:ip:axi_interconnect:2.1",
"ip_revision": "32",
"ip_revision": "33",
"gen_directory": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_zynq_ultra_ps_axi_periph_0",
"parameters": {
"component_parameters": {
@@ -340,12 +340,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator_AppCore" } ],
"IPREVISION": [ { "value": "32" } ],
"IPREVISION": [ { "value": "33" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_zynq_ultra_ps_axi_periph_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
}
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_zynq_ultra_ps_e_0_0/system_bd_wrapper_zynq_ultra_ps_e_0_0.xci
+8 -5
View File
@@ -4,7 +4,7 @@
"xci_name": "system_bd_wrapper_zynq_ultra_ps_e_0_0",
"cell_name": "zynq_ultra_ps",
"component_reference": "xilinx.com:ip:zynq_ultra_ps_e:3.5",
"ip_revision": "3",
"ip_revision": "4",
"gen_directory": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_zynq_ultra_ps_e_0_0",
"parameters": {
"component_parameters": {
@@ -63,7 +63,7 @@
"PSU__ENET3__GRP_MDIO__ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"PSU__ENET3__GRP_MDIO__IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PSU__GPIO_EMIO__PERIPHERAL__ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"PSU__GPIO_EMIO__PERIPHERAL__IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PSU__GPIO_EMIO__PERIPHERAL__IO": [ { "value": "<Select>", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PSU__GPIO0_MIO__PERIPHERAL__ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"PSU__GPIO0_MIO__IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PSU__GPIO1_MIO__PERIPHERAL__ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
@@ -225,7 +225,10 @@
"SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsyste",
"m|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem"
], "resolve_type": "user", "usage": "all" } ],
"PSU__PROTECTION__FPD_SEGMENTS": [ { "value": "SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem", "resolve_type": "user", "usage": "all" } ],
"PSU__PROTECTION__FPD_SEGMENTS": [ { "value": [
"SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Su",
"bsystem"
], "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"PSU__PROTECTION__DEBUG": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PSU__PROTECTION__SLAVES": [ { "value": [
"LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;0|LPD;USB3_0;FF9D0000;FF9DFFFF;0|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;0|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cac",
@@ -1763,12 +1766,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "3" } ],
"IPREVISION": [ { "value": "4" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../sjl_dj_rfsoc_df.gen/sources_1/bd/system_bd_wrapper/ip/system_bd_wrapper_zynq_ultra_ps_e_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/system_bd_wrapper.bd
+74 -37
View File
@@ -7,7 +7,7 @@
"name": "system_bd_wrapper",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2024.1",
"tool_version": "2024.1.2",
"validated": "true"
},
"design_tree": {
@@ -4188,7 +4188,7 @@
"components": {
"zynq_ultra_ps": {
"vlnv": "xilinx.com:ip:zynq_ultra_ps_e:3.5",
"ip_revision": "3",
"ip_revision": "4",
"xci_name": "system_bd_wrapper_zynq_ultra_ps_e_0_0",
"xci_path": "ip/system_bd_wrapper_zynq_ultra_ps_e_0_0/system_bd_wrapper_zynq_ultra_ps_e_0_0.xci",
"inst_hier_path": "zynq_ultra_ps",
@@ -4490,6 +4490,16 @@
"PSU__PMU__PLERROR__ENABLE": {
"value": "0"
},
"PSU__PROTECTION__FPD_SEGMENTS": {
"value": [
"SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |",
" SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | ",
"SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | ",
"SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | ",
"SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure",
"Subsystem"
]
},
"PSU__PROTECTION__MASTERS": {
"value": "USB1:NonSecure;0|USB0:NonSecure;0|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;0|SD0:NonSecure;0|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1"
},
@@ -5949,7 +5959,7 @@
"components": {
"xbar": {
"vlnv": "xilinx.com:ip:axi_crossbar:2.1",
"ip_revision": "32",
"ip_revision": "33",
"xci_name": "system_bd_wrapper_xbar_0",
"xci_path": "ip/system_bd_wrapper_xbar_0/system_bd_wrapper_xbar_0.xci",
"inst_hier_path": "zynq_ultra_ps_axi_periph/xbar",
@@ -6090,7 +6100,7 @@
"components": {
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"xci_name": "system_bd_wrapper_auto_pc_0",
"xci_path": "ip/system_bd_wrapper_auto_pc_0/system_bd_wrapper_auto_pc_0.xci",
"inst_hier_path": "zynq_ultra_ps_axi_periph/m00_couplers/auto_pc",
@@ -6416,7 +6426,7 @@
"components": {
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"xci_name": "system_bd_wrapper_auto_pc_1",
"xci_path": "ip/system_bd_wrapper_auto_pc_1/system_bd_wrapper_auto_pc_1.xci",
"inst_hier_path": "zynq_ultra_ps_axi_periph/m05_couplers/auto_pc",
@@ -6518,7 +6528,7 @@
"components": {
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"xci_name": "system_bd_wrapper_auto_pc_2",
"xci_path": "ip/system_bd_wrapper_auto_pc_2/system_bd_wrapper_auto_pc_2.xci",
"inst_hier_path": "zynq_ultra_ps_axi_periph/m06_couplers/auto_pc",
@@ -6620,7 +6630,7 @@
"components": {
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"xci_name": "system_bd_wrapper_auto_pc_3",
"xci_path": "ip/system_bd_wrapper_auto_pc_3/system_bd_wrapper_auto_pc_3.xci",
"inst_hier_path": "zynq_ultra_ps_axi_periph/m07_couplers/auto_pc",
@@ -6722,7 +6732,7 @@
"components": {
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"xci_name": "system_bd_wrapper_auto_pc_4",
"xci_path": "ip/system_bd_wrapper_auto_pc_4/system_bd_wrapper_auto_pc_4.xci",
"inst_hier_path": "zynq_ultra_ps_axi_periph/m08_couplers/auto_pc",
@@ -6824,7 +6834,7 @@
"components": {
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"xci_name": "system_bd_wrapper_auto_pc_5",
"xci_path": "ip/system_bd_wrapper_auto_pc_5/system_bd_wrapper_auto_pc_5.xci",
"inst_hier_path": "zynq_ultra_ps_axi_periph/m09_couplers/auto_pc",
@@ -6926,7 +6936,7 @@
"components": {
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"xci_name": "system_bd_wrapper_auto_pc_6",
"xci_path": "ip/system_bd_wrapper_auto_pc_6/system_bd_wrapper_auto_pc_6.xci",
"inst_hier_path": "zynq_ultra_ps_axi_periph/m10_couplers/auto_pc",
@@ -7668,7 +7678,7 @@
},
"axi_timer": {
"vlnv": "xilinx.com:ip:axi_timer:2.0",
"ip_revision": "33",
"ip_revision": "34",
"xci_name": "system_bd_wrapper_axi_timer_0_0",
"xci_path": "ip/system_bd_wrapper_axi_timer_0_0/system_bd_wrapper_axi_timer_0_0.xci",
"inst_hier_path": "axi_timer",
@@ -7680,7 +7690,7 @@
},
"system_ila": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"ip_revision": "17",
"ip_revision": "18",
"xci_name": "system_bd_wrapper_system_ila_0_0",
"xci_path": "ip/system_bd_wrapper_system_ila_0_0/system_bd_wrapper_system_ila_0_0.xci",
"inst_hier_path": "system_ila",
@@ -7689,11 +7699,20 @@
"value": "1024"
},
"C_MON_TYPE": {
"value": "INTERFACE"
"value": "MIX"
},
"C_NUM_MONITOR_SLOTS": {
"value": "3"
},
"C_NUM_OF_PROBES": {
"value": "2"
},
"C_PROBE0_TYPE": {
"value": "0"
},
"C_PROBE1_TYPE": {
"value": "0"
},
"C_SLOT_0_APC_EN": {
"value": "0"
},
@@ -8299,8 +8318,17 @@
"UART_RX_0_1": {
"ports": [
"SYSBUS_rx",
"systembus/UART_RX"
]
"systembus/UART_RX",
"system_ila/probe1"
],
"hdl_attributes": {
"DEBUG": {
"value": "true"
},
"MARK_DEBUG": {
"value": "true"
}
}
},
"axi_spi_engine_irq": {
"ports": [
@@ -8390,27 +8418,27 @@
"rst_zynq_ultra_ps_99M_peripheral_aresetn": {
"ports": [
"rst_zynq_ultra_ps_99M/peripheral_aresetn",
"phy_data_interface/s_axi_aresetn",
"usp_rf_data_converter/s_axi_aresetn",
"systembus/S_AXI_ARESETN",
"REF_aresetn",
"axi_spi_engine/s_axi_aresetn",
"system_management/s_axi_aresetn",
"axi_timer/s_axi_aresetn",
"system_ila/resetn",
"zynq_ultra_ps_axi_periph/ARESETN",
"zynq_ultra_ps_axi_periph/S00_ARESETN",
"zynq_ultra_ps_axi_periph/M00_ARESETN",
"zynq_ultra_ps_axi_periph/ARESETN",
"phy_data_interface/s_axi_aresetn",
"zynq_ultra_ps_axi_periph/M01_ARESETN",
"zynq_ultra_ps_axi_periph/M02_ARESETN",
"zynq_ultra_ps_axi_periph/M03_ARESETN",
"zynq_ultra_ps_axi_periph/M04_ARESETN",
"usp_rf_data_converter/s_axi_aresetn",
"zynq_ultra_ps_axi_periph/M05_ARESETN",
"zynq_ultra_ps_axi_periph/M06_ARESETN",
"systembus/S_AXI_ARESETN",
"zynq_ultra_ps_axi_periph/M07_ARESETN",
"zynq_ultra_ps_axi_periph/M08_ARESETN",
"REF_aresetn",
"axi_spi_engine/s_axi_aresetn",
"system_management/s_axi_aresetn",
"zynq_ultra_ps_axi_periph/M09_ARESETN",
"axi_timer/s_axi_aresetn",
"zynq_ultra_ps_axi_periph/M10_ARESETN",
"system_ila/resetn"
"zynq_ultra_ps_axi_periph/M10_ARESETN"
]
},
"s0_axis_aclk_0_1": {
@@ -8488,8 +8516,17 @@
"systembus_0_UART_TX": {
"ports": [
"systembus/UART_TX",
"SYSBUS_tx"
]
"SYSBUS_tx",
"system_ila/probe0"
],
"hdl_attributes": {
"DEBUG": {
"value": "true"
},
"MARK_DEBUG": {
"value": "true"
}
}
},
"usp_rf_data_converter_0_irq": {
"ports": [
@@ -8555,28 +8592,28 @@
"ports": [
"zynq_ultra_ps/pl_clk0",
"REF_aclk",
"zynq_ultra_ps/maxihpm0_lpd_aclk",
"zynq_ultra_ps_axi_periph/S00_ACLK",
"rst_zynq_ultra_ps_99M/slowest_sync_clk",
"zynq_ultra_ps_axi_periph/M00_ACLK",
"zynq_ultra_ps_axi_periph/ACLK",
"phy_data_interface/ps_clk_50M",
"usp_rf_data_converter/s_axi_aclk",
"systembus/S_AXI_ACLK",
"axi_spi_engine/s_axi_aclk",
"system_management/s_axi_aclk",
"axi_timer/s_axi_aclk",
"system_ila/clk",
"zynq_ultra_ps_axi_periph/ACLK",
"zynq_ultra_ps_axi_periph/S00_ACLK",
"zynq_ultra_ps_axi_periph/M00_ACLK",
"zynq_ultra_ps_axi_periph/M01_ACLK",
"zynq_ultra_ps_axi_periph/M02_ACLK",
"zynq_ultra_ps_axi_periph/M03_ACLK",
"zynq_ultra_ps_axi_periph/M04_ACLK",
"usp_rf_data_converter/s_axi_aclk",
"zynq_ultra_ps_axi_periph/M05_ACLK",
"systembus/S_AXI_ACLK",
"zynq_ultra_ps_axi_periph/M06_ACLK",
"zynq_ultra_ps_axi_periph/M07_ACLK",
"zynq_ultra_ps_axi_periph/M08_ACLK",
"axi_spi_engine/s_axi_aclk",
"system_management/s_axi_aclk",
"zynq_ultra_ps_axi_periph/M09_ACLK",
"axi_timer/s_axi_aclk",
"zynq_ultra_ps_axi_periph/M10_ACLK",
"system_ila/clk"
"zynq_ultra_ps/maxihpm0_lpd_aclk"
]
},
"zynq_ultra_ps_pl_resetn0": {
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/bd/system_bd_wrapper/ui/bd_ca47f3a6.ui
+76 -76
View File
@@ -1,15 +1,15 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"0.867292",
"Default View_TopLeft":"-354,339",
"Default View_ScaleFactor":"2.2888",
"Default View_TopLeft":"1005,578",
"ExpandedHierarchyInLayout":"",
"commentid":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port vin2_01 -pg 1 -lvl 0 -x 0 -y 1590 -defaultsOSRD
preplace port s20_axis -pg 1 -lvl 0 -x 0 -y 1390 -defaultsOSRD
preplace port m21_axis -pg 1 -lvl 4 -x 1590 -y 1620 -defaultsOSRD
preplace port m20_axis -pg 1 -lvl 4 -x 1590 -y 1600 -defaultsOSRD
preplace port m21_axis -pg 1 -lvl 4 -x 1650 -y 1620 -defaultsOSRD
preplace port m20_axis -pg 1 -lvl 4 -x 1650 -y 1600 -defaultsOSRD
preplace port dac2_nco -pg 1 -lvl 0 -x 0 -y 1730 -defaultsOSRD
preplace port adc2_nco -pg 1 -lvl 0 -x 0 -y 1810 -defaultsOSRD
preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 2360 -defaultsOSRD
@@ -17,8 +17,8 @@ preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 2340 -defaultsOSRD
preplace port ANT_CONFIG -pg 1 -lvl 0 -x 0 -y 290 -defaultsOSRD
preplace port RX_FRAME -pg 1 -lvl 0 -x 0 -y 310 -defaultsOSRD
preplace port TX_FRAME -pg 1 -lvl 0 -x 0 -y 330 -defaultsOSRD
preplace port PHYC -pg 1 -lvl 4 -x 1590 -y 970 -defaultsOSRD
preplace port TMC -pg 1 -lvl 4 -x 1590 -y 1000 -defaultsOSRD
preplace port PHYC -pg 1 -lvl 4 -x 1650 -y 970 -defaultsOSRD
preplace port TMC -pg 1 -lvl 4 -x 1650 -y 1000 -defaultsOSRD
preplace port ANT_BEAM -pg 1 -lvl 0 -x 0 -y 410 -defaultsOSRD
preplace port sysref_in -pg 1 -lvl 0 -x 0 -y 1670 -defaultsOSRD
preplace port Vp_Vn -pg 1 -lvl 0 -x 0 -y 120 -defaultsOSRD
@@ -44,44 +44,44 @@ preplace port dac3_nco -pg 1 -lvl 0 -x 0 -y 1750 -defaultsOSRD
preplace port adc0_nco -pg 1 -lvl 0 -x 0 -y 1770 -defaultsOSRD
preplace port adc1_nco -pg 1 -lvl 0 -x 0 -y 1790 -defaultsOSRD
preplace port adc3_nco -pg 1 -lvl 0 -x 0 -y 1830 -defaultsOSRD
preplace port m00_axis -pg 1 -lvl 4 -x 1590 -y 1440 -defaultsOSRD
preplace port m01_axis -pg 1 -lvl 4 -x 1590 -y 1460 -defaultsOSRD
preplace port m02_axis -pg 1 -lvl 4 -x 1590 -y 1480 -defaultsOSRD
preplace port m03_axis -pg 1 -lvl 4 -x 1590 -y 1500 -defaultsOSRD
preplace port m10_axis -pg 1 -lvl 4 -x 1590 -y 1520 -defaultsOSRD
preplace port m11_axis -pg 1 -lvl 4 -x 1590 -y 1540 -defaultsOSRD
preplace port m12_axis -pg 1 -lvl 4 -x 1590 -y 1560 -defaultsOSRD
preplace port m13_axis -pg 1 -lvl 4 -x 1590 -y 1580 -defaultsOSRD
preplace port m22_axis -pg 1 -lvl 4 -x 1590 -y 1640 -defaultsOSRD
preplace port m23_axis -pg 1 -lvl 4 -x 1590 -y 1660 -defaultsOSRD
preplace port m30_axis -pg 1 -lvl 4 -x 1590 -y 1680 -defaultsOSRD
preplace port m31_axis -pg 1 -lvl 4 -x 1590 -y 1700 -defaultsOSRD
preplace port m32_axis -pg 1 -lvl 4 -x 1590 -y 1720 -defaultsOSRD
preplace port m33_axis -pg 1 -lvl 4 -x 1590 -y 1740 -defaultsOSRD
preplace port vout00 -pg 1 -lvl 4 -x 1590 -y 1760 -defaultsOSRD
preplace port vout02 -pg 1 -lvl 4 -x 1590 -y 1780 -defaultsOSRD
preplace port vout10 -pg 1 -lvl 4 -x 1590 -y 1800 -defaultsOSRD
preplace port vout12 -pg 1 -lvl 4 -x 1590 -y 1820 -defaultsOSRD
preplace port vout20 -pg 1 -lvl 4 -x 1590 -y 1840 -defaultsOSRD
preplace port vout22 -pg 1 -lvl 4 -x 1590 -y 1860 -defaultsOSRD
preplace port vout30 -pg 1 -lvl 4 -x 1590 -y 1880 -defaultsOSRD
preplace port vout32 -pg 1 -lvl 4 -x 1590 -y 1900 -defaultsOSRD
preplace port spi -pg 1 -lvl 4 -x 1590 -y 830 -defaultsOSRD
preplace port m00_axis -pg 1 -lvl 4 -x 1650 -y 1440 -defaultsOSRD
preplace port m01_axis -pg 1 -lvl 4 -x 1650 -y 1460 -defaultsOSRD
preplace port m02_axis -pg 1 -lvl 4 -x 1650 -y 1480 -defaultsOSRD
preplace port m03_axis -pg 1 -lvl 4 -x 1650 -y 1500 -defaultsOSRD
preplace port m10_axis -pg 1 -lvl 4 -x 1650 -y 1520 -defaultsOSRD
preplace port m11_axis -pg 1 -lvl 4 -x 1650 -y 1540 -defaultsOSRD
preplace port m12_axis -pg 1 -lvl 4 -x 1650 -y 1560 -defaultsOSRD
preplace port m13_axis -pg 1 -lvl 4 -x 1650 -y 1580 -defaultsOSRD
preplace port m22_axis -pg 1 -lvl 4 -x 1650 -y 1640 -defaultsOSRD
preplace port m23_axis -pg 1 -lvl 4 -x 1650 -y 1660 -defaultsOSRD
preplace port m30_axis -pg 1 -lvl 4 -x 1650 -y 1680 -defaultsOSRD
preplace port m31_axis -pg 1 -lvl 4 -x 1650 -y 1700 -defaultsOSRD
preplace port m32_axis -pg 1 -lvl 4 -x 1650 -y 1720 -defaultsOSRD
preplace port m33_axis -pg 1 -lvl 4 -x 1650 -y 1740 -defaultsOSRD
preplace port vout00 -pg 1 -lvl 4 -x 1650 -y 1760 -defaultsOSRD
preplace port vout02 -pg 1 -lvl 4 -x 1650 -y 1780 -defaultsOSRD
preplace port vout10 -pg 1 -lvl 4 -x 1650 -y 1800 -defaultsOSRD
preplace port vout12 -pg 1 -lvl 4 -x 1650 -y 1820 -defaultsOSRD
preplace port vout20 -pg 1 -lvl 4 -x 1650 -y 1840 -defaultsOSRD
preplace port vout22 -pg 1 -lvl 4 -x 1650 -y 1860 -defaultsOSRD
preplace port vout30 -pg 1 -lvl 4 -x 1650 -y 1880 -defaultsOSRD
preplace port vout32 -pg 1 -lvl 4 -x 1650 -y 1900 -defaultsOSRD
preplace port spi -pg 1 -lvl 4 -x 1650 -y 830 -defaultsOSRD
preplace port port-id_s2_axis_aclk -pg 1 -lvl 0 -x 0 -y 2190 -defaultsOSRD
preplace port port-id_s2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 2170 -defaultsOSRD
preplace port port-id_m2_axis_aclk -pg 1 -lvl 0 -x 0 -y 2030 -defaultsOSRD
preplace port port-id_m2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 2010 -defaultsOSRD
preplace port port-id_sys_rstn -pg 1 -lvl 4 -x 1590 -y 2350 -defaultsOSRD
preplace port port-id_sys_clk -pg 1 -lvl 4 -x 1590 -y 2370 -defaultsOSRD
preplace port port-id_REF_aclk -pg 1 -lvl 4 -x 1590 -y 240 -defaultsOSRD
preplace port port-id_spi_active -pg 1 -lvl 4 -x 1590 -y 850 -defaultsOSRD
preplace port port-id_sys_rstn -pg 1 -lvl 4 -x 1650 -y 2350 -defaultsOSRD
preplace port port-id_sys_clk -pg 1 -lvl 4 -x 1650 -y 2370 -defaultsOSRD
preplace port port-id_REF_aclk -pg 1 -lvl 4 -x 1650 -y 240 -defaultsOSRD
preplace port port-id_spi_active -pg 1 -lvl 4 -x 1650 -y 850 -defaultsOSRD
preplace port port-id_PHY_irq -pg 1 -lvl 0 -x 0 -y 620 -defaultsOSRD
preplace port port-id_PHY_5ms -pg 1 -lvl 0 -x 0 -y 640 -defaultsOSRD
preplace port port-id_PHY_5ms_delay_2ms -pg 1 -lvl 0 -x 0 -y 660 -defaultsOSRD
preplace port port-id_SYSBUS_tx -pg 1 -lvl 4 -x 1590 -y 1090 -defaultsOSRD
preplace port port-id_SYSBUS_rx -pg 1 -lvl 4 -x 1590 -y 1070 -defaultsOSRD -right
preplace port port-id_SYSBUS_rx_busy -pg 1 -lvl 4 -x 1590 -y 1170 -defaultsOSRD
preplace port port-id_SYSBUS_tx_busy -pg 1 -lvl 4 -x 1590 -y 1150 -defaultsOSRD
preplace port port-id_SYSBUS_tx -pg 1 -lvl 4 -x 1650 -y 1090 -defaultsOSRD
preplace port port-id_SYSBUS_rx -pg 1 -lvl 4 -x 1650 -y 1070 -defaultsOSRD -right
preplace port port-id_SYSBUS_rx_busy -pg 1 -lvl 4 -x 1650 -y 1170 -defaultsOSRD
preplace port port-id_SYSBUS_tx_busy -pg 1 -lvl 4 -x 1650 -y 1150 -defaultsOSRD
preplace port port-id_m0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1930 -defaultsOSRD
preplace port port-id_m0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1950 -defaultsOSRD
preplace port port-id_m1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1970 -defaultsOSRD
@@ -94,15 +94,15 @@ preplace port port-id_s1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 2130 -defaultsOSRD
preplace port port-id_s1_axis_aclk -pg 1 -lvl 0 -x 0 -y 2150 -defaultsOSRD
preplace port port-id_s3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 2210 -defaultsOSRD
preplace port port-id_s3_axis_aclk -pg 1 -lvl 0 -x 0 -y 2230 -defaultsOSRD
preplace port port-id_clk_adc0 -pg 1 -lvl 4 -x 1590 -y 1920 -defaultsOSRD
preplace port port-id_clk_adc1 -pg 1 -lvl 4 -x 1590 -y 1940 -defaultsOSRD
preplace port port-id_clk_adc2 -pg 1 -lvl 4 -x 1590 -y 1960 -defaultsOSRD
preplace port port-id_clk_adc3 -pg 1 -lvl 4 -x 1590 -y 1980 -defaultsOSRD
preplace port port-id_clk_dac0 -pg 1 -lvl 4 -x 1590 -y 2000 -defaultsOSRD
preplace port port-id_clk_dac1 -pg 1 -lvl 4 -x 1590 -y 2020 -defaultsOSRD
preplace port port-id_clk_dac2 -pg 1 -lvl 4 -x 1590 -y 2040 -defaultsOSRD
preplace port port-id_clk_dac3 -pg 1 -lvl 4 -x 1590 -y 2060 -defaultsOSRD
preplace portBus REF_aresetn -pg 1 -lvl 4 -x 1590 -y 20 -defaultsOSRD
preplace port port-id_clk_adc0 -pg 1 -lvl 4 -x 1650 -y 1920 -defaultsOSRD
preplace port port-id_clk_adc1 -pg 1 -lvl 4 -x 1650 -y 1940 -defaultsOSRD
preplace port port-id_clk_adc2 -pg 1 -lvl 4 -x 1650 -y 1960 -defaultsOSRD
preplace port port-id_clk_adc3 -pg 1 -lvl 4 -x 1650 -y 1980 -defaultsOSRD
preplace port port-id_clk_dac0 -pg 1 -lvl 4 -x 1650 -y 2000 -defaultsOSRD
preplace port port-id_clk_dac1 -pg 1 -lvl 4 -x 1650 -y 2020 -defaultsOSRD
preplace port port-id_clk_dac2 -pg 1 -lvl 4 -x 1650 -y 2040 -defaultsOSRD
preplace port port-id_clk_dac3 -pg 1 -lvl 4 -x 1650 -y 2060 -defaultsOSRD
preplace portBus REF_aresetn -pg 1 -lvl 4 -x 1650 -y 20 -defaultsOSRD
preplace inst zynq_ultra_ps -pg 1 -lvl 2 -x 750 -y 520 -defaultsOSRD
preplace inst intr_xconcate -pg 1 -lvl 1 -x 250 -y 630 -defaultsOSRD
preplace inst phy_data_interface -pg 1 -lvl 1 -x 250 -y 380 -defaultsOSRD
@@ -110,17 +110,17 @@ preplace inst mts_clk_gen -pg 1 -lvl 2 -x 750 -y 2350 -defaultsOSRD
preplace inst usp_rf_data_converter -pg 1 -lvl 2 -x 750 -y 1760 -defaultsOSRD
preplace inst zynq_ultra_ps_axi_periph -pg 1 -lvl 2 -x 750 -y 930 -defaultsOSRD
preplace inst rst_zynq_ultra_ps_99M -pg 1 -lvl 2 -x 750 -y 340 -defaultsOSRD
preplace inst systembus -pg 1 -lvl 3 -x 1370 -y 1110 -defaultsOSRD
preplace inst axi_spi_engine -pg 1 -lvl 3 -x 1370 -y 850 -defaultsOSRD
preplace inst system_management -pg 1 -lvl 3 -x 1370 -y 130 -defaultsOSRD
preplace inst systembus -pg 1 -lvl 3 -x 1400 -y 1110 -defaultsOSRD
preplace inst axi_spi_engine -pg 1 -lvl 3 -x 1400 -y 870 -defaultsOSRD
preplace inst system_management -pg 1 -lvl 3 -x 1400 -y 130 -defaultsOSRD
preplace inst axi_timer -pg 1 -lvl 1 -x 250 -y 870 -defaultsOSRD
preplace inst system_ila -pg 1 -lvl 3 -x 1370 -y 690 -defaultsOSRD
preplace inst system_ila -pg 1 -lvl 3 -x 1400 -y 690 -defaultsOSRD
preplace netloc PHY_5ms_1 1 0 1 N 640
preplace netloc PHY_5ms_delay_2ms_1 1 0 1 N 660
preplace netloc PHY_irq_1 1 0 1 N 620
preplace netloc UART_RX_0_1 1 3 1 NJ 1070
preplace netloc axi_spi_engine_irq 1 0 4 40 160 NJ 160 1110J 270 1520
preplace netloc axi_spi_engine_spi_active 1 3 1 NJ 850
preplace netloc UART_RX_0_1 1 2 2 1250 980 1590J
preplace netloc axi_spi_engine_irq 1 0 4 40 160 NJ 160 1130J 270 1560
preplace netloc axi_spi_engine_spi_active 1 3 1 1610J 850n
preplace netloc axi_timer_0_interrupt 1 0 2 120 760 380
preplace netloc m0_axis_aclk_0_1 1 0 2 NJ 1950 NJ
preplace netloc m0_axis_aresetn_0_1 1 0 2 NJ 1930 NJ
@@ -130,10 +130,10 @@ preplace netloc m2_axis_aclk_0_1 1 0 2 NJ 2030 NJ
preplace netloc m2_axis_aresetn_0_1 1 0 2 NJ 2010 NJ
preplace netloc m3_axis_aclk_0_1 1 0 2 NJ 2070 NJ
preplace netloc m3_axis_aresetn_0_1 1 0 2 NJ 2050 NJ
preplace netloc mts_clk_gen_mts_sysref 1 1 2 420 180 1140
preplace netloc mts_clk_gen_mts_sysref 1 1 2 420 180 1160
preplace netloc mts_clk_gen_sys_clk 1 2 2 N 2370 N
preplace netloc mts_clk_gen_sys_rstn 1 2 2 N 2350 N
preplace netloc rst_zynq_ultra_ps_99M_peripheral_aresetn 1 0 4 60 180 390 90 1200 20 N
preplace netloc rst_zynq_ultra_ps_99M_peripheral_aresetn 1 0 4 60 180 390 90 1210 20 N
preplace netloc s0_axis_aclk_0_1 1 0 2 NJ 2110 NJ
preplace netloc s0_axis_aresetn_0_1 1 0 2 NJ 2090 NJ
preplace netloc s1_axis_aclk_0_1 1 0 2 NJ 2150 NJ
@@ -143,11 +143,11 @@ preplace netloc s2_axis_aresetn_0_1 1 0 2 NJ 2170 NJ
preplace netloc s3_axis_aclk_0_1 1 0 2 NJ 2230 NJ
preplace netloc s3_axis_aresetn_0_1 1 0 2 NJ 2210 NJ
preplace netloc systembus_0_RX_BUSY 1 3 1 N 1170
preplace netloc systembus_0_RX_DONE 1 0 4 50 170 NJ 170 1220J 250 1540
preplace netloc systembus_0_RX_DONE 1 0 4 50 170 NJ 170 1240J 250 1580
preplace netloc systembus_0_TX_BUSY 1 3 1 N 1150
preplace netloc systembus_0_TX_DONE 1 0 4 70 190 NJ 190 1210J 260 1530
preplace netloc systembus_0_UART_TX 1 3 1 N 1090
preplace netloc usp_rf_data_converter_0_irq 1 0 3 90 200 NJ 200 1130
preplace netloc systembus_0_TX_DONE 1 0 4 70 190 NJ 190 1230J 260 1570
preplace netloc systembus_0_UART_TX 1 2 2 1240 940 1610
preplace netloc usp_rf_data_converter_0_irq 1 0 3 90 200 NJ 200 1150
preplace netloc usp_rf_data_converter_clk_adc0 1 2 2 NJ 1920 NJ
preplace netloc usp_rf_data_converter_clk_adc1 1 2 2 NJ 1940 NJ
preplace netloc usp_rf_data_converter_clk_adc2 1 2 2 NJ 1960 NJ
@@ -157,8 +157,8 @@ preplace netloc usp_rf_data_converter_clk_dac1 1 2 2 NJ 2020 NJ
preplace netloc usp_rf_data_converter_clk_dac2 1 2 2 NJ 2040 NJ
preplace netloc usp_rf_data_converter_clk_dac3 1 2 2 NJ 2060 NJ
preplace netloc xlconcat_0_dout 1 1 1 400 530n
preplace netloc zynq_ultra_ps_pl_clk0 1 0 4 100 220 410 110 1190 240 N
preplace netloc zynq_ultra_ps_pl_resetn0 1 1 2 440 220 1080J
preplace netloc zynq_ultra_ps_pl_clk0 1 0 4 100 220 410 110 1200 240 N
preplace netloc zynq_ultra_ps_pl_resetn0 1 1 2 440 220 1100J
preplace netloc PHY_ANT_0_1 1 0 1 NJ 290
preplace netloc PHY_BEAM_0_1 1 0 1 NJ 410
preplace netloc PHY_RX_0_1 1 0 1 NJ 310
@@ -169,7 +169,7 @@ preplace netloc adc1_clk_0_1 1 0 2 NJ 1470 NJ
preplace netloc adc1_nco_0_1 1 0 2 NJ 1790 NJ
preplace netloc adc2_nco_0_1 1 0 2 NJ 1810 NJ
preplace netloc adc3_nco_0_1 1 0 2 NJ 1830 NJ
preplace netloc axi_spi_engine_spi_0 1 3 1 N 830
preplace netloc axi_spi_engine_spi_0 1 3 1 1600 830n
preplace netloc dac0_clk_0_1 1 0 2 NJ 1490 NJ
preplace netloc dac0_nco_0_1 1 0 2 NJ 1690 NJ
preplace netloc dac1_nco_0_1 1 0 2 NJ 1710 NJ
@@ -218,20 +218,20 @@ preplace netloc vin2_01_0_1 1 0 2 NJ 1590 NJ
preplace netloc vin2_23_0_1 1 0 2 NJ 1610 NJ
preplace netloc vin3_01_0_1 1 0 2 NJ 1630 NJ
preplace netloc vin3_23_0_1 1 0 2 NJ 1650 NJ
preplace netloc zynq_ultra_ps_M_AXI_HPM0_LPD 1 1 2 430 240 1150
preplace netloc zynq_ultra_ps_axi_periph_M00_AXI 1 2 1 N 830
preplace netloc zynq_ultra_ps_axi_periph_M01_AXI 1 0 3 20 140 N 140 1090
preplace netloc zynq_ultra_ps_axi_periph_M02_AXI 1 0 3 120 100 N 100 1100
preplace netloc zynq_ultra_ps_axi_periph_M03_AXI 1 0 3 30 150 N 150 1070
preplace netloc zynq_ultra_ps_axi_periph_M04_AXI 1 0 3 110 230 N 230 1060
preplace netloc zynq_ultra_ps_axi_periph_M05_AXI 1 1 2 440 610 1110
preplace netloc zynq_ultra_ps_axi_periph_M06_AXI 1 2 1 1150 950n
preplace netloc zynq_ultra_ps_axi_periph_M07_AXI 1 2 2 1210 970 NJ
preplace netloc zynq_ultra_ps_axi_periph_M08_AXI 1 2 2 1220 990 1550J
preplace netloc zynq_ultra_ps_axi_periph_M09_AXI 1 2 1 1160 100n
preplace netloc zynq_ultra_ps_axi_periph_M10_AXI 1 0 3 80 210 NJ 210 1120
levelinfo -pg 1 0 250 750 1370 1590
pagesize -pg 1 -db -bbox -sgen -200 0 1770 2420
preplace netloc zynq_ultra_ps_M_AXI_HPM0_LPD 1 1 2 430 240 1190
preplace netloc zynq_ultra_ps_axi_periph_M00_AXI 1 2 1 1170 830n
preplace netloc zynq_ultra_ps_axi_periph_M01_AXI 1 0 3 20 140 N 140 1110
preplace netloc zynq_ultra_ps_axi_periph_M02_AXI 1 0 3 120 100 N 100 1120
preplace netloc zynq_ultra_ps_axi_periph_M03_AXI 1 0 3 30 150 N 150 1090
preplace netloc zynq_ultra_ps_axi_periph_M04_AXI 1 0 3 110 230 N 230 1080
preplace netloc zynq_ultra_ps_axi_periph_M05_AXI 1 1 2 440 610 1130
preplace netloc zynq_ultra_ps_axi_periph_M06_AXI 1 2 1 1170 950n
preplace netloc zynq_ultra_ps_axi_periph_M07_AXI 1 2 2 1220 970 NJ
preplace netloc zynq_ultra_ps_axi_periph_M08_AXI 1 2 2 1230 990 1600J
preplace netloc zynq_ultra_ps_axi_periph_M09_AXI 1 2 1 1180 100n
preplace netloc zynq_ultra_ps_axi_periph_M10_AXI 1 0 3 80 210 NJ 210 1140
levelinfo -pg 1 0 250 750 1400 1650
pagesize -pg 1 -db -bbox -sgen -200 0 1830 2420
"
}
{
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/imports/new/system_top.v
+16 -6
View File
@@ -114,7 +114,7 @@ module system_top
// *************************************************************************
// ******************************* DEBUG IO ********************************
// *************************************************************************
output debug_io_1 ,
input debug_io_1 ,
output debug_io_2 ,
output debug_io_3 ,
output debug_io_4 ,
@@ -307,8 +307,8 @@ wire PHY_5ms_delay_2ms;
//485
wire SYSBUS_tx_busy;
assign RS_485_RE_n = SYSBUS_tx_busy;
assign RS_485_DE = SYSBUS_tx_busy;
assign RS_485_RE_n = 1'b0;
assign RS_485_DE = 1'b1;
//BRAM
wire [31:0] ANT_CONFIG_addr ;
@@ -590,8 +590,11 @@ wire [31:0] PC_I_RF_callback_2 ;
//与自动建网接口
wire PC_O_AutoNet_state ;//自动建网状态 0:不在自动建网 1:正在自动建网
reg RS_485_RxD_buf = 'b0;
wire RS_485_TxD_buf;
assign RS_485_TxD = RS_485_TxD_buf;
assign debug_io_2 = RS_485_TxD_buf;
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// Block Design Interface ////////////////////////////
@@ -1185,8 +1188,8 @@ system_bd_wrapper_wrapper u_system_bd_wrapper
.TX_FRAME_rst (sys_rst ),
.TX_FRAME_we (4'b0000 ),
// 485
.SYSBUS_rx (RS_485_RxD ),
.SYSBUS_tx (RS_485_TxD ),
.SYSBUS_rx (RS_485_RxD_buf ),
.SYSBUS_tx (RS_485_TxD_buf ),
.SYSBUS_rx_busy (/* Keep NC */ ),
.SYSBUS_tx_busy (SYSBUS_tx_busy ),
// *************************************************************************
@@ -2118,6 +2121,13 @@ timesync_ctrl #(
end
endcase
if (vio_debug_3[0]) begin
RS_485_RxD_buf <= RS_485_RxD;
end
else begin
RS_485_RxD_buf <= debug_io_1;
end
case(vio_debug_1[2:0])
3'd0:begin
debug_io_1_buf <= tor_state_debug;
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/utils_1/imports/synth_1/system_top.dcp
LFS
BIN
View File
Binary file not shown.
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.xpr
+701 -121
View File
@@ -66,13 +66,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="193"/>
<Option Name="WTModelSimExportSim" Val="193"/>
<Option Name="WTQuestaExportSim" Val="193"/>
<Option Name="WTXSimExportSim" Val="194"/>
<Option Name="WTModelSimExportSim" Val="194"/>
<Option Name="WTQuestaExportSim" Val="194"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="192"/>
<Option Name="WTRivieraExportSim" Val="192"/>
<Option Name="WTActivehdlExportSim" Val="192"/>
<Option Name="WTVcsExportSim" Val="193"/>
<Option Name="WTRivieraExportSim" Val="193"/>
<Option Name="WTActivehdlExportSim" Val="193"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -764,11 +764,17 @@
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_auto_pc_3/system_bd_wrapper_auto_pc_3.xci">
<Proxy FileSetName="system_bd_wrapper_auto_pc_3"/>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_ant_beam_bram_0/system_bd_wrapper_ant_beam_bram_0.xci">
<Proxy FileSetName="system_bd_wrapper_ant_beam_bram_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_auto_pc_4/system_bd_wrapper_auto_pc_4.xci">
<Proxy FileSetName="system_bd_wrapper_auto_pc_4"/>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_ant_beam_bram_ctrl_0/system_bd_wrapper_ant_beam_bram_ctrl_0.xci">
<Proxy FileSetName="system_bd_wrapper_ant_beam_bram_ctrl_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_ant_config_bram_0/system_bd_wrapper_ant_config_bram_0.xci">
<Proxy FileSetName="system_bd_wrapper_ant_config_bram_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_ant_config_bram_ctrl_0/system_bd_wrapper_ant_config_bram_ctrl_0.xci">
<Proxy FileSetName="system_bd_wrapper_ant_config_bram_ctrl_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_axi_spi_engine_0_2/system_bd_wrapper_axi_spi_engine_0_2.xci">
<Proxy FileSetName="system_bd_wrapper_axi_spi_engine_0_2"/>
@@ -776,24 +782,60 @@
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_axi_timer_0_0/system_bd_wrapper_axi_timer_0_0.xci">
<Proxy FileSetName="system_bd_wrapper_axi_timer_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_clk_wiz_pl_clk_0/system_bd_wrapper_clk_wiz_pl_clk_0.xci">
<Proxy FileSetName="system_bd_wrapper_clk_wiz_pl_clk_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_rst_zynq_ultra_ps_99M_0/system_bd_wrapper_rst_zynq_ultra_ps_99M_0.xci">
<Proxy FileSetName="system_bd_wrapper_rst_zynq_ultra_ps_99M_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_rx_frame_bram_0/system_bd_wrapper_rx_frame_bram_0.xci">
<Proxy FileSetName="system_bd_wrapper_rx_frame_bram_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_rx_frame_bram_ctrl_0/system_bd_wrapper_rx_frame_bram_ctrl_0.xci">
<Proxy FileSetName="system_bd_wrapper_rx_frame_bram_ctrl_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_spi_engine_execution_0_1/system_bd_wrapper_spi_engine_execution_0_1.xci">
<Proxy FileSetName="system_bd_wrapper_spi_engine_execution_0_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_system_ila_0_0/system_bd_wrapper_system_ila_0_0.xci">
<Proxy FileSetName="system_bd_wrapper_system_ila_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_system_management_wiz_0_0/system_bd_wrapper_system_management_wiz_0_0.xci">
<Proxy FileSetName="system_bd_wrapper_system_management_wiz_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_systembus_0_0/system_bd_wrapper_systembus_0_0.xci">
<Proxy FileSetName="system_bd_wrapper_systembus_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_tx_frame_bram_0/system_bd_wrapper_tx_frame_bram_0.xci">
<Proxy FileSetName="system_bd_wrapper_tx_frame_bram_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_tx_frame_bram_ctrl_0/system_bd_wrapper_tx_frame_bram_ctrl_0.xci">
<Proxy FileSetName="system_bd_wrapper_tx_frame_bram_ctrl_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_usp_rf_data_converter_0_0/system_bd_wrapper_usp_rf_data_converter_0_0.xci">
<Proxy FileSetName="system_bd_wrapper_usp_rf_data_converter_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_util_bufg_pl_clk_0/system_bd_wrapper_util_bufg_pl_clk_0.xci">
<Proxy FileSetName="system_bd_wrapper_util_bufg_pl_clk_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_util_ds_buf_pl_clk_0/system_bd_wrapper_util_ds_buf_pl_clk_0.xci">
<Proxy FileSetName="system_bd_wrapper_util_ds_buf_pl_clk_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_util_ds_buf_pl_sysref_0/system_bd_wrapper_util_ds_buf_pl_sysref_0.xci">
<Proxy FileSetName="system_bd_wrapper_util_ds_buf_pl_sysref_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_xbar_0/system_bd_wrapper_xbar_0.xci">
<Proxy FileSetName="system_bd_wrapper_xbar_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_xpm_cdc_gen_mts_sysref_0/system_bd_wrapper_xpm_cdc_gen_mts_sysref_0.xci">
<Proxy FileSetName="system_bd_wrapper_xpm_cdc_gen_mts_sysref_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_xpm_cdc_gen_pl_sysref_0/system_bd_wrapper_xpm_cdc_gen_pl_sysref_0.xci">
<Proxy FileSetName="system_bd_wrapper_xpm_cdc_gen_pl_sysref_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd_wrapper.bd" FileRelPathName="ip/system_bd_wrapper_zynq_ultra_ps_e_0_0/system_bd_wrapper_zynq_ultra_ps_e_0_0.xci">
<Proxy FileSetName="system_bd_wrapper_zynq_ultra_ps_e_0_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/new/Recv_src/TurboDec/ACU.v">
<FileInfo>
@@ -3367,9 +3409,111 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_xbar_0" RelGenDir="$PGENDIR/system_bd_wrapper_xbar_0">
<FileSet Name="system_bd_wrapper_spi_engine_execution_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_spi_engine_execution_0_1" RelGenDir="$PGENDIR/system_bd_wrapper_spi_engine_execution_0_1">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_xbar_0"/>
<Option Name="TopModule" Val="system_bd_wrapper_spi_engine_execution_0_1"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_axi_spi_engine_0_2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_axi_spi_engine_0_2" RelGenDir="$PGENDIR/system_bd_wrapper_axi_spi_engine_0_2">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_axi_spi_engine_0_2"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_zynq_ultra_ps_e_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_zynq_ultra_ps_e_0_0" RelGenDir="$PGENDIR/system_bd_wrapper_zynq_ultra_ps_e_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_zynq_ultra_ps_e_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_tx_frame_bram_ctrl_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_tx_frame_bram_ctrl_0" RelGenDir="$PGENDIR/system_bd_wrapper_tx_frame_bram_ctrl_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_tx_frame_bram_ctrl_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_rx_frame_bram_ctrl_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_rx_frame_bram_ctrl_0" RelGenDir="$PGENDIR/system_bd_wrapper_rx_frame_bram_ctrl_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_rx_frame_bram_ctrl_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_ant_config_bram_ctrl_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_ant_config_bram_ctrl_0" RelGenDir="$PGENDIR/system_bd_wrapper_ant_config_bram_ctrl_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_ant_config_bram_ctrl_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_tx_frame_bram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_tx_frame_bram_0" RelGenDir="$PGENDIR/system_bd_wrapper_tx_frame_bram_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_tx_frame_bram_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_rx_frame_bram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_rx_frame_bram_0" RelGenDir="$PGENDIR/system_bd_wrapper_rx_frame_bram_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_rx_frame_bram_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_ant_config_bram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_ant_config_bram_0" RelGenDir="$PGENDIR/system_bd_wrapper_ant_config_bram_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_ant_config_bram_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_ant_beam_bram_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_ant_beam_bram_0" RelGenDir="$PGENDIR/system_bd_wrapper_ant_beam_bram_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_ant_beam_bram_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_ant_beam_bram_ctrl_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_ant_beam_bram_ctrl_0" RelGenDir="$PGENDIR/system_bd_wrapper_ant_beam_bram_ctrl_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_ant_beam_bram_ctrl_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_util_ds_buf_pl_sysref_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_util_ds_buf_pl_sysref_0" RelGenDir="$PGENDIR/system_bd_wrapper_util_ds_buf_pl_sysref_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_util_ds_buf_pl_sysref_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_clk_wiz_pl_clk_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_clk_wiz_pl_clk_0" RelGenDir="$PGENDIR/system_bd_wrapper_clk_wiz_pl_clk_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_clk_wiz_pl_clk_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_xpm_cdc_gen_pl_sysref_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_xpm_cdc_gen_pl_sysref_0" RelGenDir="$PGENDIR/system_bd_wrapper_xpm_cdc_gen_pl_sysref_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_xpm_cdc_gen_pl_sysref_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_xpm_cdc_gen_mts_sysref_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_xpm_cdc_gen_mts_sysref_0" RelGenDir="$PGENDIR/system_bd_wrapper_xpm_cdc_gen_mts_sysref_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_xpm_cdc_gen_mts_sysref_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_usp_rf_data_converter_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_usp_rf_data_converter_0_0" RelGenDir="$PGENDIR/system_bd_wrapper_usp_rf_data_converter_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_usp_rf_data_converter_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_rst_zynq_ultra_ps_99M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_rst_zynq_ultra_ps_99M_0" RelGenDir="$PGENDIR/system_bd_wrapper_rst_zynq_ultra_ps_99M_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_rst_zynq_ultra_ps_99M_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_system_management_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_system_management_wiz_0_0" RelGenDir="$PGENDIR/system_bd_wrapper_system_management_wiz_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_system_management_wiz_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
@@ -3385,27 +3529,9 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_spi_engine_execution_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_spi_engine_execution_0_1" RelGenDir="$PGENDIR/system_bd_wrapper_spi_engine_execution_0_1">
<FileSet Name="system_bd_wrapper_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_xbar_0" RelGenDir="$PGENDIR/system_bd_wrapper_xbar_0">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_spi_engine_execution_0_1"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_axi_spi_engine_0_2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_axi_spi_engine_0_2" RelGenDir="$PGENDIR/system_bd_wrapper_axi_spi_engine_0_2">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_axi_spi_engine_0_2"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_auto_pc_4" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_auto_pc_4" RelGenDir="$PGENDIR/system_bd_wrapper_auto_pc_4">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_auto_pc_4"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_wrapper_auto_pc_3" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_wrapper_auto_pc_3" RelGenDir="$PGENDIR/system_bd_wrapper_auto_pc_3">
<Config>
<Option Name="TopModule" Val="system_bd_wrapper_auto_pc_3"/>
<Option Name="TopModule" Val="system_bd_wrapper_xbar_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
@@ -4362,36 +4488,6 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_xbar_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_xbar_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_xbar_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_axi_timer_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_axi_timer_0_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_axi_timer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_axi_timer_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_axi_timer_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_axi_timer_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_system_ila_0_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_system_ila_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_spi_engine_execution_0_1_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_spi_engine_execution_0_1" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_spi_engine_execution_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_spi_engine_execution_0_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_spi_engine_execution_0_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_spi_engine_execution_0_1_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
@@ -4412,9 +4508,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_auto_pc_4_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_auto_pc_4" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_4" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_auto_pc_4_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_synth_1" ParallelReportGen="true">
<Run Id="system_bd_wrapper_zynq_ultra_ps_e_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_zynq_ultra_ps_e_0_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_zynq_ultra_ps_e_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_zynq_ultra_ps_e_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_zynq_ultra_ps_e_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_zynq_ultra_ps_e_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -4422,9 +4520,215 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_auto_pc_3_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_auto_pc_3" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_3" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_auto_pc_3_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_synth_1" ParallelReportGen="true">
<Run Id="system_bd_wrapper_tx_frame_bram_ctrl_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_tx_frame_bram_ctrl_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_tx_frame_bram_ctrl_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_tx_frame_bram_ctrl_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_tx_frame_bram_ctrl_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_tx_frame_bram_ctrl_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_rx_frame_bram_ctrl_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_rx_frame_bram_ctrl_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_rx_frame_bram_ctrl_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_rx_frame_bram_ctrl_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_rx_frame_bram_ctrl_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_rx_frame_bram_ctrl_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_ant_config_bram_ctrl_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_ant_config_bram_ctrl_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_ant_config_bram_ctrl_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_ant_config_bram_ctrl_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_ant_config_bram_ctrl_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_ant_config_bram_ctrl_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_tx_frame_bram_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_tx_frame_bram_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_tx_frame_bram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_tx_frame_bram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_tx_frame_bram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_tx_frame_bram_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_rx_frame_bram_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_rx_frame_bram_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_rx_frame_bram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_rx_frame_bram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_rx_frame_bram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_rx_frame_bram_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_ant_config_bram_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_ant_config_bram_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_ant_config_bram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_ant_config_bram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_ant_config_bram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_ant_config_bram_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_ant_beam_bram_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_ant_beam_bram_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_ant_beam_bram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_ant_beam_bram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_ant_beam_bram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_ant_beam_bram_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_ant_beam_bram_ctrl_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_ant_beam_bram_ctrl_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_ant_beam_bram_ctrl_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_ant_beam_bram_ctrl_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_ant_beam_bram_ctrl_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_ant_beam_bram_ctrl_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_util_ds_buf_pl_sysref_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_util_ds_buf_pl_sysref_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_util_ds_buf_pl_sysref_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_util_ds_buf_pl_sysref_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_util_ds_buf_pl_sysref_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_util_ds_buf_pl_sysref_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_clk_wiz_pl_clk_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_clk_wiz_pl_clk_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_clk_wiz_pl_clk_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_clk_wiz_pl_clk_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_clk_wiz_pl_clk_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_clk_wiz_pl_clk_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_xpm_cdc_gen_pl_sysref_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_xpm_cdc_gen_pl_sysref_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_xpm_cdc_gen_pl_sysref_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_xpm_cdc_gen_pl_sysref_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_xpm_cdc_gen_pl_sysref_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_xpm_cdc_gen_pl_sysref_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_xpm_cdc_gen_mts_sysref_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_xpm_cdc_gen_mts_sysref_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_xpm_cdc_gen_mts_sysref_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_xpm_cdc_gen_mts_sysref_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_xpm_cdc_gen_mts_sysref_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_xpm_cdc_gen_mts_sysref_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_usp_rf_data_converter_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_usp_rf_data_converter_0_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_usp_rf_data_converter_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_usp_rf_data_converter_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_usp_rf_data_converter_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_usp_rf_data_converter_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_rst_zynq_ultra_ps_99M_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_rst_zynq_ultra_ps_99M_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_rst_zynq_ultra_ps_99M_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_rst_zynq_ultra_ps_99M_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_rst_zynq_ultra_ps_99M_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_rst_zynq_ultra_ps_99M_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_system_management_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_system_management_wiz_0_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_system_management_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_system_management_wiz_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_system_management_wiz_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_system_management_wiz_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_axi_timer_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_axi_timer_0_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_axi_timer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_axi_timer_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_axi_timer_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_axi_timer_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_system_ila_0_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_system_ila_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_xbar_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_xbar_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_xbar_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -6014,57 +6318,6 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_xbar_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_xbar_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_axi_timer_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_axi_timer_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_axi_timer_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_axi_timer_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_axi_timer_0_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_system_ila_0_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_spi_engine_execution_0_1_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_spi_engine_execution_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_spi_engine_execution_0_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_spi_engine_execution_0_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_spi_engine_execution_0_1_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
@@ -6099,9 +6352,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_auto_pc_4_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_4" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_auto_pc_4_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_impl_1" ParallelReportGen="true">
<Run Id="system_bd_wrapper_zynq_ultra_ps_e_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_zynq_ultra_ps_e_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_zynq_ultra_ps_e_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_zynq_ultra_ps_e_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_zynq_ultra_ps_e_0_0_impl_1" ParallelReportGen="true">
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<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -6116,9 +6371,334 @@
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<RQSFiles/>
</Run>
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<Run Id="system_bd_wrapper_tx_frame_bram_ctrl_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_tx_frame_bram_ctrl_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_tx_frame_bram_ctrl_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_tx_frame_bram_ctrl_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_tx_frame_bram_ctrl_0_impl_1" ParallelReportGen="true">
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<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_system_ila_0_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_wrapper_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_xbar_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_xbar_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>