ila_8x12_2x30_131072.v,verilog,xil_defaultlib,../../../ip/ila_8x12_2x30_131072/sim/ila_8x12_2x30_131072.v,incdir="../../../ip/ila_8x12_2x30_131072/hdl/verilog"
glbl.v,Verilog,xil_defaultlib,glbl.v
