update duifei_cal_coarse

in duifei_cal_coarse, split tx and rx ila, resynthesis with new ad9361 rx mapping strategy
2023-04-06 15:26:02 +08:00
parent 53bd4d459d
commit 14ac34e794
181 changed files with 458261 additions and 894532 deletions
@@ -53,7 +53,7 @@

 //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

-ila_tx_rx your_instance_name (
+ila_rx your_instance_name (
 	.clk(clk), // input wire clk


@@ -64,15 +64,13 @@ ila_tx_rx your_instance_name (
 	.probe4(probe4), // input wire [11:0]  probe4 
 	.probe5(probe5), // input wire [11:0]  probe5 
 	.probe6(probe6), // input wire [11:0]  probe6 
-	.probe7(probe7), // input wire [11:0]  probe7 
-	.probe8(probe8), // input wire [11:0]  probe8 
-	.probe9(probe9) // input wire [11:0]  probe9
+	.probe7(probe7) // input wire [11:0]  probe7
 );

 // INST_TAG_END ------ End INSTANTIATION Template ---------

-// You must compile the wrapper file ila_tx_rx when simulating
-// the core, ila_tx_rx. When compiling the wrapper file, be sure to
+// You must compile the wrapper file ila_rx when simulating
+// the core, ila_rx. When compiling the wrapper file, be sure to
 // reference the Verilog simulation library.


@@ -1,11 +1,11 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Thu Mar 30 16:45:40 2023
+// Date        : Thu Apr  6 10:26:43 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
-//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/ila_tx_rx_synth_1/ila_tx_rx_stub.v
-// Design      : ila_tx_rx
+//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_basic/ip/managed_ip_project/managed_ip_project.runs/ila_rx_synth_1/ila_rx_stub.v
+// Design      : ila_rx
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7z100ffg900-2
 // --------------------------------------------------------------------------------
@@ -14,9 +14,9 @@
 // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
-module ila_tx_rx(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
-  probe6, probe7, probe8, probe9)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[11:0]" */;
+module ila_rx(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
+  probe6, probe7)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0]" */;
  input clk;
  input [11:0]probe0;
  input [11:0]probe1;
@@ -26,6 +26,4 @@ module ila_tx_rx(clk, probe0, probe1, probe2, probe3, probe4, probe5,
  input [11:0]probe5;
  input [11:0]probe6;
  input [11:0]probe7;
-  input [11:0]probe8;
-  input [11:0]probe9;
 endmodule
@@ -1,18 +1,18 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-- Date        : Thu Mar 30 16:45:40 2023
+-- Date        : Thu Apr  6 10:26:43 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
--               /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/ila_tx_rx_synth_1/ila_tx_rx_stub.vhdl
-- Design      : ila_tx_rx
+--               /home/josh/Workspace/vivado-git/projects/duifei/duifei_basic/ip/managed_ip_project/managed_ip_project.runs/ila_rx_synth_1/ila_rx_stub.vhdl
+-- Design      : ila_rx
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7z100ffg900-2
 -- --------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

-entity ila_tx_rx is
+entity ila_rx is
  Port ( 
    clk : in STD_LOGIC;
    probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
@@ -22,18 +22,16 @@ entity ila_tx_rx is
    probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 );
    probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 );
    probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 );
-    probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 );
-    probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 );
-    probe9 : in STD_LOGIC_VECTOR ( 11 downto 0 )
+    probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );

-end ila_tx_rx;
+end ila_rx;

-architecture stub of ila_tx_rx is
+architecture stub of ila_rx is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[11:0]";
+attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
 begin
@@ -46,7 +46,7 @@
 //
 // DO NOT MODIFY THIS FILE.
 `timescale 1ns / 1ps
-module ila_tx_rx (
+module ila_rx (
 clk,


@@ -57,9 +57,7 @@ probe3,
 probe4,
 probe5,
 probe6,
-probe7,
-probe8,
-probe9
+probe7
 );

 input clk;
@@ -73,8 +71,6 @@ input [11 : 0] probe4;
 input [11 : 0] probe5;
 input [11 : 0] probe6;
 input [11 : 0] probe7;
-input [11 : 0] probe8;
-input [11 : 0] probe9;


 endmodule
@@ -0,0 +1,70 @@
+// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+ila_tx your_instance_name (
+	.clk(clk), // input wire clk
+
+
+	.probe0(probe0), // input wire [11:0]  probe0  
+	.probe1(probe1) // input wire [11:0]  probe1
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file ila_tx when simulating
+// the core, ila_tx. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
+
@@ -0,0 +1,22 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Thu Apr  6 10:25:36 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_basic/ip/managed_ip_project/managed_ip_project.runs/ila_tx_synth_1/ila_tx_stub.v
+// Design      : ila_tx
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
+module ila_tx(clk, probe0, probe1)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0]" */;
+  input clk;
+  input [11:0]probe0;
+  input [11:0]probe1;
+endmodule
@@ -0,0 +1,32 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Thu Apr  6 10:25:36 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/josh/Workspace/vivado-git/projects/duifei/duifei_basic/ip/managed_ip_project/managed_ip_project.runs/ila_tx_synth_1/ila_tx_stub.vhdl
+-- Design      : ila_tx
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity ila_tx is
+  Port ( 
+    clk : in STD_LOGIC;
+    probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 )
+  );
+
+end ila_tx;
+
+architecture stub of ila_tx is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
+begin
+end;
@@ -0,0 +1,64 @@
+// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+`timescale 1ns / 1ps
+module ila_tx (
+clk,
+
+
+probe0,
+probe1
+);
+
+input clk;
+
+
+input [11 : 0] probe0;
+input [11 : 0] probe1;
+
+
+endmodule
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 30 16:43:21 CST 2023
+# Generated by export_simulation on Thu Apr 06 15:13:17 CST 2023
 #
 ################################################################################

@@ -12,7 +12,7 @@

 From the shell prompt in the current directory, issue the following command:-

-./ila_tx_rx.sh
+./ila_rx.sh

 This command will launch the 'compile', 'elaborate' and 'simulate' functions
 implemented in the script file for the 3-step flow. These functions are called
@@ -26,16 +26,16 @@ current directory.
 The 'setup' function is also used for removing the simulator generated data in
 order to reset the current directory to the original state when export_simulation
 was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './ila_tx_rx.sh' script.
+'-reset_run' switch to the './ila_rx.sh' script.

-./ila_tx_rx.sh -reset_run
+./ila_rx.sh -reset_run

 To keep the generated data from the previous run but regenerate the setup files and
 library directories, use the '-noclean_files' switch.

-./ila_tx_rx.sh -noclean_files
+./ila_rx.sh -noclean_files

-For more information on the script, please type './ila_tx_rx.sh -help'.
+For more information on the script, please type './ila_rx.sh -help'.

 2. Additional design information files:-

@@ -7,15 +7,15 @@ vlib activehdl/xpm
 vmap xil_defaultlib activehdl/xil_defaultlib
 vmap xpm activehdl/xpm

-vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/ila_tx_rx/hdl/verilog" \
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/ila_rx/hdl/verilog" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \

 vcom -work xpm -93 \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \

-vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/ila_tx_rx/hdl/verilog" \
-"../../../ip/ila_tx_rx/sim/ila_tx_rx.v" \
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/ila_rx/hdl/verilog" \
+"../../../ip/ila_rx/sim/ila_rx.v" \

 vlog -work xil_defaultlib \
 "glbl.v"
@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_tx_rx/hdl/verilog"
-xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_tx_rx/hdl/verilog"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_tx_rx/hdl/verilog"
-ila_tx_rx.v,verilog,xil_defaultlib,../../../ip/ila_tx_rx/sim/ila_tx_rx.v,incdir="../../../ip/ila_tx_rx/hdl/verilog"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx/hdl/verilog"
+ila_rx.v,verilog,xil_defaultlib,../../../ip/ila_rx/sim/ila_rx.v,incdir="../../../ip/ila_rx/hdl/verilog"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : ila_tx_rx.sh
+# Filename    : ila_rx.sh
 # Simulator   : Aldec Active-HDL Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 30 16:43:21 CST 2023
+# Generated by Vivado on Thu Apr 06 15:13:17 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: ila_tx_rx.sh [-help]
-# usage: ila_tx_rx.sh [-lib_map_path]
-# usage: ila_tx_rx.sh [-noclean_files]
-# usage: ila_tx_rx.sh [-reset_run]
+# usage: ila_rx.sh [-help]
+# usage: ila_rx.sh [-lib_map_path]
+# usage: ila_rx.sh [-noclean_files]
+# usage: ila_rx.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'ila_tx_rx.sh -help' for more information.
+# executing this script. Please type 'ila_rx.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -35,7 +35,7 @@


 # Script info
-echo -e "ila_tx_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "ila_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"

 # Main steps
 run()
@@ -66,7 +66,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_tx_rx.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx.sh -help\" for more information)\n"
        exit 1
      fi
     map_setup_file $2
@@ -121,7 +121,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_tx_rx.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx.sh -help\" for more information)\n"
    exit 1
  fi

@@ -133,10 +133,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: ila_tx_rx.sh [-help]\n\
-Usage: ila_tx_rx.sh [-lib_map_path]\n\
-Usage: ila_tx_rx.sh [-reset_run]\n\
-Usage: ila_tx_rx.sh [-noclean_files]\n\n\
+  msg="Usage: ila_rx.sh [-help]\n\
+Usage: ila_rx.sh [-lib_map_path]\n\
+Usage: ila_rx.sh [-reset_run]\n\
+Usage: ila_rx.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+ila_rx -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rx xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {ila_rx.udo}
+
+run -all
+
+endsim
+
+quit -force
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 30 16:43:21 CST 2023
+# Generated by export_simulation on Thu Apr 06 15:13:17 CST 2023
 #
 ################################################################################

@@ -12,7 +12,7 @@

 From the shell prompt in the current directory, issue the following command:-

-./ila_tx_rx.sh
+./ila_rx.sh

 This command will launch the 'execute' function for the single-step flow. This
 function is called from the main 'run' function in the script file.
@@ -25,16 +25,16 @@ current directory.
 The 'setup' function is also used for removing the simulator generated data in
 order to reset the current directory to the original state when export_simulation
 was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './ila_tx_rx.sh' script.
+'-reset_run' switch to the './ila_rx.sh' script.

-./ila_tx_rx.sh -reset_run
+./ila_rx.sh -reset_run

 To keep the generated data from the previous run but regenerate the setup files and
 library directories, use the '-noclean_files' switch.

-./ila_tx_rx.sh -noclean_files
+./ila_rx.sh -noclean_files

-For more information on the script, please type './ila_tx_rx.sh -help'.
+For more information on the script, please type './ila_rx.sh -help'.

 2. Additional design information files:-

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_tx_rx/hdl/verilog"
-xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_tx_rx/hdl/verilog"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_tx_rx/hdl/verilog"
-ila_tx_rx.v,verilog,xil_defaultlib,../../../ip/ila_tx_rx/sim/ila_tx_rx.v,incdir="../../../ip/ila_tx_rx/hdl/verilog"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx/hdl/verilog"
+ila_rx.v,verilog,xil_defaultlib,../../../ip/ila_rx/sim/ila_rx.v,incdir="../../../ip/ila_rx/hdl/verilog"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : ila_tx_rx.sh
+# Filename    : ila_rx.sh
 # Simulator   : Cadence Incisive Enterprise Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 30 16:43:21 CST 2023
+# Generated by Vivado on Thu Apr 06 15:13:17 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: ila_tx_rx.sh [-help]
-# usage: ila_tx_rx.sh [-lib_map_path]
-# usage: ila_tx_rx.sh [-noclean_files]
-# usage: ila_tx_rx.sh [-reset_run]
+# usage: ila_rx.sh [-help]
+# usage: ila_rx.sh [-lib_map_path]
+# usage: ila_rx.sh [-noclean_files]
+# usage: ila_rx.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'ila_tx_rx.sh -help' for more information.
+# executing this script. Please type 'ila_rx.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm)
 sim_lib_dir="ies_lib"

 # Script info
-echo -e "ila_tx_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "ila_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"

 # Main steps
 run()
@@ -73,11 +73,11 @@ execute()
       -reflib "$ref_lib_dir/secureip:secureip" \
       -reflib "$ref_lib_dir/unimacro:unimacro" \
       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
-       -top xil_defaultlib.ila_tx_rx \
+       -top xil_defaultlib.ila_rx \
       -f run.f \
       -top glbl \
       glbl.v \
-       +incdir+"../../../ip/ila_tx_rx/hdl/verilog"
+       +incdir+"../../../ip/ila_rx/hdl/verilog"
 }

 # STEP: setup
@@ -86,7 +86,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_tx_rx.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx.sh -help\" for more information)\n"
        exit 1
      else
        ref_lib_dir=$2
@@ -145,7 +145,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_tx_rx.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx.sh -help\" for more information)\n"
    exit 1
  fi

@@ -157,10 +157,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: ila_tx_rx.sh [-help]\n\
-Usage: ila_tx_rx.sh [-lib_map_path]\n\
-Usage: ila_tx_rx.sh [-reset_run]\n\
-Usage: ila_tx_rx.sh [-noclean_files]\n\n\
+  msg="Usage: ila_rx.sh [-help]\n\
+Usage: ila_rx.sh [-lib_map_path]\n\
+Usage: ila_rx.sh [-reset_run]\n\
+Usage: ila_rx.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -6,7 +6,7 @@
  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 -endlib
 -makelib ies_lib/xil_defaultlib \
-  "../../../ip/ila_tx_rx/sim/ila_tx_rx.v" \
+  "../../../ip/ila_rx/sim/ila_rx.v" \
 -endlib
 -makelib ies_lib/xil_defaultlib \
  glbl.v
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 30 16:43:21 CST 2023
+# Generated by export_simulation on Thu Apr 06 15:13:17 CST 2023
 #
 ################################################################################

@@ -12,7 +12,7 @@

 From the shell prompt in the current directory, issue the following command:-

-./ila_tx_rx.sh
+./ila_rx.sh

 This command will launch the 'compile', 'elaborate' and 'simulate' functions
 implemented in the script file for the 3-step flow. These functions are called
@@ -26,16 +26,16 @@ current directory.
 The 'setup' function is also used for removing the simulator generated data in
 order to reset the current directory to the original state when export_simulation
 was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './ila_tx_rx.sh' script.
+'-reset_run' switch to the './ila_rx.sh' script.

-./ila_tx_rx.sh -reset_run
+./ila_rx.sh -reset_run

 To keep the generated data from the previous run but regenerate the setup files and
 library directories, use the '-noclean_files' switch.

-./ila_tx_rx.sh -noclean_files
+./ila_rx.sh -noclean_files

-For more information on the script, please type './ila_tx_rx.sh -help'.
+For more information on the script, please type './ila_rx.sh -help'.

 2. Additional design information files:-

@@ -0,0 +1,22 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/xpm
+
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap xpm modelsim_lib/msim/xpm
+
+vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/ila_rx/hdl/verilog" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_rx/hdl/verilog" \
+"../../../ip/ila_rx/sim/ila_rx.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_tx_rx/hdl/verilog"
-xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_tx_rx/hdl/verilog"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_tx_rx/hdl/verilog"
-ila_tx_rx.v,verilog,xil_defaultlib,../../../ip/ila_tx_rx/sim/ila_tx_rx.v,incdir="../../../ip/ila_tx_rx/hdl/verilog"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx/hdl/verilog"
+ila_rx.v,verilog,xil_defaultlib,../../../ip/ila_rx/sim/ila_rx.v,incdir="../../../ip/ila_rx/hdl/verilog"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : ila_tx_rx.sh
+# Filename    : ila_rx.sh
 # Simulator   : Mentor Graphics ModelSim Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 30 16:43:21 CST 2023
+# Generated by Vivado on Thu Apr 06 15:13:17 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: ila_tx_rx.sh [-help]
-# usage: ila_tx_rx.sh [-lib_map_path]
-# usage: ila_tx_rx.sh [-noclean_files]
-# usage: ila_tx_rx.sh [-reset_run]
+# usage: ila_rx.sh [-help]
+# usage: ila_rx.sh [-lib_map_path]
+# usage: ila_rx.sh [-noclean_files]
+# usage: ila_rx.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'ila_tx_rx.sh -help' for more information.
+# executing this script. Please type 'ila_rx.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -35,7 +35,7 @@


 # Script info
-echo -e "ila_tx_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "ila_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"

 # Main steps
 run()
@@ -66,7 +66,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_tx_rx.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx.sh -help\" for more information)\n"
        exit 1
      fi
     copy_setup_file $2
@@ -95,10 +95,11 @@ setup()
 copy_setup_file()
 {
  file="modelsim.ini"
-  if [[ ($1 != "") ]]; then
+  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+  if [[ ($1 != "" && -e $1) ]]; then
    lib_map_path="$1"
  else
-    lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1"
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
  fi
  if [[ ($lib_map_path != "") ]]; then
    src_file="$lib_map_path/$file"
@@ -136,7 +137,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_tx_rx.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx.sh -help\" for more information)\n"
    exit 1
  fi

@@ -148,10 +149,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: ila_tx_rx.sh [-help]\n\
-Usage: ila_tx_rx.sh [-lib_map_path]\n\
-Usage: ila_tx_rx.sh [-reset_run]\n\
-Usage: ila_tx_rx.sh [-noclean_files]\n\n\
+  msg="Usage: ila_rx.sh [-help]\n\
+Usage: ila_rx.sh [-lib_map_path]\n\
+Usage: ila_rx.sh [-reset_run]\n\
+Usage: ila_rx.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.ila_rx xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {ila_rx.udo}
+
+run -all
+
+quit -force
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 30 16:43:21 CST 2023
+# Generated by export_simulation on Thu Apr 06 15:13:17 CST 2023
 #
 ################################################################################

@@ -12,7 +12,7 @@

 From the shell prompt in the current directory, issue the following command:-

-./ila_tx_rx.sh
+./ila_rx.sh

 This command will launch the 'compile', 'elaborate' and 'simulate' functions
 implemented in the script file for the 3-step flow. These functions are called
@@ -26,16 +26,16 @@ current directory.
 The 'setup' function is also used for removing the simulator generated data in
 order to reset the current directory to the original state when export_simulation
 was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './ila_tx_rx.sh' script.
+'-reset_run' switch to the './ila_rx.sh' script.

-./ila_tx_rx.sh -reset_run
+./ila_rx.sh -reset_run

 To keep the generated data from the previous run but regenerate the setup files and
 library directories, use the '-noclean_files' switch.

-./ila_tx_rx.sh -noclean_files
+./ila_rx.sh -noclean_files

-For more information on the script, please type './ila_tx_rx.sh -help'.
+For more information on the script, please type './ila_rx.sh -help'.

 2. Additional design information files:-

@@ -7,15 +7,15 @@ vlib questa_lib/msim/xpm
 vmap xil_defaultlib questa_lib/msim/xil_defaultlib
 vmap xpm questa_lib/msim/xpm

-vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_tx_rx/hdl/verilog" \
+vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_rx/hdl/verilog" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \

 vcom -work xpm -64 -93 \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \

-vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_tx_rx/hdl/verilog" \
-"../../../ip/ila_tx_rx/sim/ila_tx_rx.v" \
+vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_rx/hdl/verilog" \
+"../../../ip/ila_rx/sim/ila_rx.v" \

 vlog -work xil_defaultlib \
 "glbl.v"
@@ -1 +1 @@
-vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_tx_rx xil_defaultlib.glbl -o ila_tx_rx_opt
+vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_rx xil_defaultlib.glbl -o ila_rx_opt
@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_tx_rx/hdl/verilog"
-xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_tx_rx/hdl/verilog"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_tx_rx/hdl/verilog"
-ila_tx_rx.v,verilog,xil_defaultlib,../../../ip/ila_tx_rx/sim/ila_tx_rx.v,incdir="../../../ip/ila_tx_rx/hdl/verilog"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx/hdl/verilog"
+ila_rx.v,verilog,xil_defaultlib,../../../ip/ila_rx/sim/ila_rx.v,incdir="../../../ip/ila_rx/hdl/verilog"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : ila_tx_rx.sh
+# Filename    : ila_rx.sh
 # Simulator   : Mentor Graphics Questa Advanced Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 30 16:43:21 CST 2023
+# Generated by Vivado on Thu Apr 06 15:13:17 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: ila_tx_rx.sh [-help]
-# usage: ila_tx_rx.sh [-lib_map_path]
-# usage: ila_tx_rx.sh [-noclean_files]
-# usage: ila_tx_rx.sh [-reset_run]
+# usage: ila_rx.sh [-help]
+# usage: ila_rx.sh [-lib_map_path]
+# usage: ila_rx.sh [-noclean_files]
+# usage: ila_rx.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'ila_tx_rx.sh -help' for more information.
+# executing this script. Please type 'ila_rx.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -35,7 +35,7 @@


 # Script info
-echo -e "ila_tx_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "ila_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"

 # Main steps
 run()
@@ -73,7 +73,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_tx_rx.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx.sh -help\" for more information)\n"
        exit 1
      fi
     copy_setup_file $2
@@ -102,10 +102,9 @@ setup()
 copy_setup_file()
 {
  file="modelsim.ini"
+  lib_map_path=""
  if [[ ($1 != "") ]]; then
    lib_map_path="$1"
-  else
-    lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
  fi
  if [[ ($lib_map_path != "") ]]; then
    src_file="$lib_map_path/$file"
@@ -143,7 +142,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_tx_rx.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx.sh -help\" for more information)\n"
    exit 1
  fi

@@ -155,10 +154,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: ila_tx_rx.sh [-help]\n\
-Usage: ila_tx_rx.sh [-lib_map_path]\n\
-Usage: ila_tx_rx.sh [-reset_run]\n\
-Usage: ila_tx_rx.sh [-noclean_files]\n\n\
+  msg="Usage: ila_rx.sh [-help]\n\
+Usage: ila_rx.sh [-lib_map_path]\n\
+Usage: ila_rx.sh [-reset_run]\n\
+Usage: ila_rx.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -1,7 +1,7 @@
 onbreak {quit -f}
 onerror {quit -f}

-vsim -t 1ps -lib xil_defaultlib ila_tx_rx_opt
+vsim -t 1ps -lib xil_defaultlib ila_rx_opt

 do {wave.do}

@@ -9,7 +9,7 @@ view wave
 view structure
 view signals

-do {ila_tx_rx.udo}
+do {ila_rx.udo}

 run -all

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 30 16:43:21 CST 2023
+# Generated by export_simulation on Thu Apr 06 15:13:17 CST 2023
 #
 ################################################################################

@@ -12,7 +12,7 @@

 From the shell prompt in the current directory, issue the following command:-

-./ila_tx_rx.sh
+./ila_rx.sh

 This command will launch the 'compile', 'elaborate' and 'simulate' functions
 implemented in the script file for the 3-step flow. These functions are called
@@ -26,16 +26,16 @@ current directory.
 The 'setup' function is also used for removing the simulator generated data in
 order to reset the current directory to the original state when export_simulation
 was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './ila_tx_rx.sh' script.
+'-reset_run' switch to the './ila_rx.sh' script.

-./ila_tx_rx.sh -reset_run
+./ila_rx.sh -reset_run

 To keep the generated data from the previous run but regenerate the setup files and
 library directories, use the '-noclean_files' switch.

-./ila_tx_rx.sh -noclean_files
+./ila_rx.sh -noclean_files

-For more information on the script, please type './ila_tx_rx.sh -help'.
+For more information on the script, please type './ila_rx.sh -help'.

 2. Additional design information files:-

@@ -7,15 +7,15 @@ vlib riviera/xpm
 vmap xil_defaultlib riviera/xil_defaultlib
 vmap xpm riviera/xpm

-vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/ila_tx_rx/hdl/verilog" \
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/ila_rx/hdl/verilog" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \

 vcom -work xpm -93 \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \

-vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/ila_tx_rx/hdl/verilog" \
-"../../../ip/ila_tx_rx/sim/ila_tx_rx.v" \
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/ila_rx/hdl/verilog" \
+"../../../ip/ila_rx/sim/ila_rx.v" \

 vlog -work xil_defaultlib \
 "glbl.v"
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx/hdl/verilog"
+ila_rx.v,verilog,xil_defaultlib,../../../ip/ila_rx/sim/ila_rx.v,incdir="../../../ip/ila_rx/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : ila_tx_rx.sh
+# Filename    : ila_rx.sh
 # Simulator   : Aldec Riviera-PRO Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 30 16:43:21 CST 2023
+# Generated by Vivado on Thu Apr 06 15:13:17 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: ila_tx_rx.sh [-help]
-# usage: ila_tx_rx.sh [-lib_map_path]
-# usage: ila_tx_rx.sh [-noclean_files]
-# usage: ila_tx_rx.sh [-reset_run]
+# usage: ila_rx.sh [-help]
+# usage: ila_rx.sh [-lib_map_path]
+# usage: ila_rx.sh [-noclean_files]
+# usage: ila_rx.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'ila_tx_rx.sh -help' for more information.
+# executing this script. Please type 'ila_rx.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -35,7 +35,7 @@


 # Script info
-echo -e "ila_tx_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "ila_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"

 # Main steps
 run()
@@ -66,7 +66,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_tx_rx.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx.sh -help\" for more information)\n"
        exit 1
      fi
     map_setup_file $2
@@ -93,10 +93,9 @@ setup()
 map_setup_file()
 {
  file="library.cfg"
+  lib_map_path=""
  if [[ ($1 != "") ]]; then
    lib_map_path="$1"
-  else
-    lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
  fi
  if [[ ($lib_map_path != "") ]]; then
    src_file="$lib_map_path/$file"
@@ -122,7 +121,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_tx_rx.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx.sh -help\" for more information)\n"
    exit 1
  fi

@@ -134,10 +133,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: ila_tx_rx.sh [-help]\n\
-Usage: ila_tx_rx.sh [-lib_map_path]\n\
-Usage: ila_tx_rx.sh [-reset_run]\n\
-Usage: ila_tx_rx.sh [-noclean_files]\n\n\
+  msg="Usage: ila_rx.sh [-help]\n\
+Usage: ila_rx.sh [-lib_map_path]\n\
+Usage: ila_rx.sh [-reset_run]\n\
+Usage: ila_rx.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+ila_rx -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rx xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {ila_rx.udo}
+
+run -all
+
+endsim
+
+quit -force
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu Apr 06 15:13:17 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_rx.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_rx.sh' script.
+
+./ila_rx.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_rx.sh -noclean_files
+
+For more information on the script, please type './ila_rx.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx/hdl/verilog"
+ila_rx.v,verilog,xil_defaultlib,../../../ip/ila_rx/sim/ila_rx.v,incdir="../../../ip/ila_rx/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : ila_tx_rx.sh
+# Filename    : ila_rx.sh
 # Simulator   : Synopsys Verilog Compiler Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 30 16:43:21 CST 2023
+# Generated by Vivado on Thu Apr 06 15:13:17 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: ila_tx_rx.sh [-help]
-# usage: ila_tx_rx.sh [-lib_map_path]
-# usage: ila_tx_rx.sh [-noclean_files]
-# usage: ila_tx_rx.sh [-reset_run]
+# usage: ila_rx.sh [-help]
+# usage: ila_rx.sh [-lib_map_path]
+# usage: ila_rx.sh [-noclean_files]
+# usage: ila_rx.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'ila_tx_rx.sh -help' for more information.
+# executing this script. Please type 'ila_rx.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -48,13 +48,13 @@ vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
 vcs_sim_opts="-ucli -licqueue -l simulate.log"

 # Design libraries
-design_libs=(xil_defaultlib)
+design_libs=(xil_defaultlib xpm)

 # Simulation root library directory
 sim_lib_dir="vcs_lib"

 # Script info
-echo -e "ila_tx_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "ila_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"

 # Main steps
 run()
@@ -70,8 +70,17 @@ run()
 compile()
 {
  # Compile design files
-  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ila_tx_rx/hdl/verilog" \
-    "$ref_dir/../../../ip/ila_tx_rx/sim/ila_tx_rx.v" \
+  vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/ila_rx/hdl/verilog" \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ila_rx/hdl/verilog" \
+    "$ref_dir/../../../ip/ila_rx/sim/ila_rx.v" \
  2>&1 | tee -a vlogan.log


@@ -84,13 +93,13 @@ compile()
 # RUN_STEP: <elaborate>
 elaborate()
 {
-  vcs $vcs_elab_opts xil_defaultlib.ila_tx_rx xil_defaultlib.glbl -o ila_tx_rx_simv
+  vcs $vcs_elab_opts xil_defaultlib.ila_rx xil_defaultlib.glbl -o ila_rx_simv
 }

 # RUN_STEP: <simulate>
 simulate()
 {
-  ./ila_tx_rx_simv $vcs_sim_opts -do simulate.do
+  ./ila_rx_simv $vcs_sim_opts -do simulate.do
 }

 # STEP: setup
@@ -99,7 +108,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_tx_rx.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx.sh -help\" for more information)\n"
        exit 1
      fi
      create_lib_mappings $2
@@ -138,10 +147,9 @@ create_lib_mappings()

  touch $file

+  lib_map_path=""
  if [[ ($1 != "") ]]; then
    lib_map_path="$1"
-  else
-    lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1"
  fi

  for (( i=0; i<${#design_libs[*]}; i++ )); do
@@ -175,7 +183,7 @@ create_lib_dir()
 # Delete generated data from the previous run
 reset_run()
 {
-  files_to_remove=(ucli.key ila_tx_rx_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ila_tx_rx_simv.daidir)
+  files_to_remove=(ucli.key ila_rx_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ila_rx_simv.daidir)
  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
    file="${files_to_remove[i]}"
    if [[ -e $file ]]; then
@@ -190,7 +198,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_tx_rx.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx.sh -help\" for more information)\n"
    exit 1
  fi

@@ -202,10 +210,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: ila_tx_rx.sh [-help]\n\
-Usage: ila_tx_rx.sh [-lib_map_path]\n\
-Usage: ila_tx_rx.sh [-reset_run]\n\
-Usage: ila_tx_rx.sh [-noclean_files]\n\n\
+  msg="Usage: ila_rx.sh [-help]\n\
+Usage: ila_rx.sh [-lib_map_path]\n\
+Usage: ila_rx.sh [-reset_run]\n\
+Usage: ila_rx.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 30 16:43:21 CST 2023
+# Generated by export_simulation on Thu Apr 06 15:13:17 CST 2023
 #
 ################################################################################

@@ -12,7 +12,7 @@

 From the shell prompt in the current directory, issue the following command:-

-./ila_tx_rx.sh
+./ila_rx.sh

 This command will launch the 'execute' function for the single-step flow. This
 function is called from the main 'run' function in the script file.
@@ -25,16 +25,16 @@ current directory.
 The 'setup' function is also used for removing the simulator generated data in
 order to reset the current directory to the original state when export_simulation
 was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './ila_tx_rx.sh' script.
+'-reset_run' switch to the './ila_rx.sh' script.

-./ila_tx_rx.sh -reset_run
+./ila_rx.sh -reset_run

 To keep the generated data from the previous run but regenerate the setup files and
 library directories, use the '-noclean_files' switch.

-./ila_tx_rx.sh -noclean_files
+./ila_rx.sh -noclean_files

-For more information on the script, please type './ila_tx_rx.sh -help'.
+For more information on the script, please type './ila_rx.sh -help'.

 2. Additional design information files:-

@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx/hdl/verilog"
+ila_rx.v,verilog,xil_defaultlib,../../../ip/ila_rx/sim/ila_rx.v,incdir="../../../ip/ila_rx/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : ila_tx_rx.sh
+# Filename    : ila_rx.sh
 # Simulator   : Cadence Xcelium Parallel Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 30 16:43:21 CST 2023
+# Generated by Vivado on Thu Apr 06 15:13:17 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: ila_tx_rx.sh [-help]
-# usage: ila_tx_rx.sh [-lib_map_path]
-# usage: ila_tx_rx.sh [-noclean_files]
-# usage: ila_tx_rx.sh [-reset_run]
+# usage: ila_rx.sh [-help]
+# usage: ila_rx.sh [-lib_map_path]
+# usage: ila_rx.sh [-noclean_files]
+# usage: ila_rx.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'ila_tx_rx.sh -help' for more information.
+# executing this script. Please type 'ila_rx.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm)
 sim_lib_dir="xcelium_lib"

 # Script info
-echo -e "ila_tx_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "ila_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"

 # Main steps
 run()
@@ -73,11 +73,11 @@ execute()
       -reflib "$ref_lib_dir/secureip:secureip" \
       -reflib "$ref_lib_dir/unimacro:unimacro" \
       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
-       -top xil_defaultlib.ila_tx_rx \
+       -top xil_defaultlib.ila_rx \
       -f run.f \
       -top glbl \
       glbl.v \
-       +incdir+"../../../ip/ila_tx_rx/hdl/verilog"
+       +incdir+"../../../ip/ila_rx/hdl/verilog"
 }

 # STEP: setup
@@ -86,7 +86,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_tx_rx.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx.sh -help\" for more information)\n"
        exit 1
      else
        ref_lib_dir=$2
@@ -145,7 +145,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_tx_rx.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx.sh -help\" for more information)\n"
    exit 1
  fi

@@ -157,10 +157,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: ila_tx_rx.sh [-help]\n\
-Usage: ila_tx_rx.sh [-lib_map_path]\n\
-Usage: ila_tx_rx.sh [-reset_run]\n\
-Usage: ila_tx_rx.sh [-noclean_files]\n\n\
+  msg="Usage: ila_rx.sh [-help]\n\
+Usage: ila_rx.sh [-lib_map_path]\n\
+Usage: ila_rx.sh [-reset_run]\n\
+Usage: ila_rx.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -6,7 +6,7 @@
  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 -endlib
 -makelib xcelium_lib/xil_defaultlib \
-  "../../../ip/ila_tx_rx/sim/ila_tx_rx.v" \
+  "../../../ip/ila_rx/sim/ila_rx.v" \
 -endlib
 -makelib xcelium_lib/xil_defaultlib \
  glbl.v
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu Apr 06 15:13:17 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_rx.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_rx.sh' script.
+
+./ila_rx.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_rx.sh -noclean_files
+
+For more information on the script, please type './ila_rx.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,2 @@
+ila_rx.v,verilog,xil_defaultlib,../../../ip/ila_rx/sim/ila_rx.v,incdir="../../../ip/ila_rx/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : ila_tx_rx.sh
+# Filename    : ila_rx.sh
 # Simulator   : Xilinx Vivado Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 30 16:43:21 CST 2023
+# Generated by Vivado on Thu Apr 06 15:13:17 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: ila_tx_rx.sh [-help]
-# usage: ila_tx_rx.sh [-lib_map_path]
-# usage: ila_tx_rx.sh [-noclean_files]
-# usage: ila_tx_rx.sh [-reset_run]
+# usage: ila_rx.sh [-help]
+# usage: ila_rx.sh [-lib_map_path]
+# usage: ila_rx.sh [-noclean_files]
+# usage: ila_rx.sh [-reset_run]
 #
 #*********************************************************************************************************

@@ -27,7 +27,7 @@ xvlog_opts="--relax"


 # Script info
-echo -e "ila_tx_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "ila_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"

 # Main steps
 run()
@@ -50,13 +50,13 @@ compile()
 # RUN_STEP: <elaborate>
 elaborate()
 {
-  xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ila_tx_rx xil_defaultlib.ila_tx_rx xil_defaultlib.glbl -log elaborate.log
+  xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ila_rx xil_defaultlib.ila_rx xil_defaultlib.glbl -log elaborate.log
 }

 # RUN_STEP: <simulate>
 simulate()
 {
-  xsim ila_tx_rx -key {Behavioral:sim_1:Functional:ila_tx_rx} -tclbatch cmd.tcl -log simulate.log
+  xsim ila_rx -key {Behavioral:sim_1:Functional:ila_rx} -tclbatch cmd.tcl -log simulate.log
 }

 # STEP: setup
@@ -65,7 +65,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_tx_rx.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx.sh -help\" for more information)\n"
        exit 1
      fi
     copy_setup_file $2
@@ -168,7 +168,7 @@ map_local_libs()
 # Delete generated data from the previous run
 reset_run()
 {
-  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ila_tx_rx.wdb xsim.dir)
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ila_rx.wdb xsim.dir)
  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
    file="${files_to_remove[i]}"
    if [[ -e $file ]]; then
@@ -181,7 +181,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_tx_rx.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx.sh -help\" for more information)\n"
    exit 1
  fi

@@ -193,10 +193,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: ila_tx_rx.sh [-help]\n\
-Usage: ila_tx_rx.sh [-lib_map_path]\n\
-Usage: ila_tx_rx.sh [-reset_run]\n\
-Usage: ila_tx_rx.sh [-noclean_files]\n\n\
+  msg="Usage: ila_rx.sh [-help]\n\
+Usage: ila_rx.sh [-lib_map_path]\n\
+Usage: ila_rx.sh [-reset_run]\n\
+Usage: ila_rx.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -0,0 +1,6 @@
+verilog xil_defaultlib --include "../../../ip/ila_rx/hdl/verilog" \
+"../../../ip/ila_rx/sim/ila_rx.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu Apr 06 15:13:21 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_tx.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_tx.sh' script.
+
+./ila_tx.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_tx.sh -noclean_files
+
+For more information on the script, please type './ila_tx.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,22 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xil_defaultlib
+vlib activehdl/xpm
+
+vmap xil_defaultlib activehdl/xil_defaultlib
+vmap xpm activehdl/xpm
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/ila_tx/hdl/verilog" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/ila_tx/hdl/verilog" \
+"../../../ip/ila_tx/sim/ila_tx.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_tx/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_tx/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_tx/hdl/verilog"
+ila_tx.v,verilog,xil_defaultlib,../../../ip/ila_tx/sim/ila_tx.v,incdir="../../../ip/ila_tx/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : ila_tx.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu Apr 06 15:13:21 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: ila_tx.sh [-help]
+# usage: ila_tx.sh [-lib_map_path]
+# usage: ila_tx.sh [-noclean_files]
+# usage: ila_tx.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'ila_tx.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "ila_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_tx.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_tx.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: ila_tx.sh [-help]\n\
+Usage: ila_tx.sh [-lib_map_path]\n\
+Usage: ila_tx.sh [-reset_run]\n\
+Usage: ila_tx.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+ila_tx -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_tx xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {ila_tx.udo}
+
+run -all
+
+endsim
+
+quit -force
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu Apr 06 15:13:21 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_tx.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_tx.sh' script.
+
+./ila_tx.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_tx.sh -noclean_files
+
+For more information on the script, please type './ila_tx.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_tx/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_tx/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_tx/hdl/verilog"
+ila_tx.v,verilog,xil_defaultlib,../../../ip/ila_tx/sim/ila_tx.v,incdir="../../../ip/ila_tx/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : ila_tx.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu Apr 06 15:13:21 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: ila_tx.sh [-help]
+# usage: ila_tx.sh [-lib_map_path]
+# usage: ila_tx.sh [-noclean_files]
+# usage: ila_tx.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'ila_tx.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "ila_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.ila_tx \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"../../../ip/ila_tx/hdl/verilog"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_tx.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_tx.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: ila_tx.sh [-help]\n\
+Usage: ila_tx.sh [-lib_map_path]\n\
+Usage: ila_tx.sh [-reset_run]\n\
+Usage: ila_tx.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,14 @@
+-makelib ies_lib/xil_defaultlib -sv \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../ip/ila_tx/sim/ila_tx.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu Apr 06 15:13:21 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_tx.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_tx.sh' script.
+
+./ila_tx.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_tx.sh -noclean_files
+
+For more information on the script, please type './ila_tx.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,22 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/xpm
+
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap xpm modelsim_lib/msim/xpm
+
+vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/ila_tx/hdl/verilog" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_tx/hdl/verilog" \
+"../../../ip/ila_tx/sim/ila_tx.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_tx/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_tx/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_tx/hdl/verilog"
+ila_tx.v,verilog,xil_defaultlib,../../../ip/ila_tx/sim/ila_tx.v,incdir="../../../ip/ila_tx/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,168 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : ila_tx.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu Apr 06 15:13:21 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: ila_tx.sh [-help]
+# usage: ila_tx.sh [-lib_map_path]
+# usage: ila_tx.sh [-noclean_files]
+# usage: ila_tx.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'ila_tx.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "ila_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_tx.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+  if [[ ($1 != "" && -e $1) ]]; then
+    lib_map_path="$1"
+  else
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_tx.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: ila_tx.sh [-help]\n\
+Usage: ila_tx.sh [-lib_map_path]\n\
+Usage: ila_tx.sh [-reset_run]\n\
+Usage: ila_tx.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.ila_tx xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {ila_tx.udo}
+
+run -all
+
+quit -force
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu Apr 06 15:13:21 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_tx.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_tx.sh' script.
+
+./ila_tx.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_tx.sh -noclean_files
+
+For more information on the script, please type './ila_tx.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,22 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xil_defaultlib
+vlib questa_lib/msim/xpm
+
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+vmap xpm questa_lib/msim/xpm
+
+vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_tx/hdl/verilog" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_tx/hdl/verilog" \
+"../../../ip/ila_tx/sim/ila_tx.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
@@ -0,0 +1 @@
+vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_tx xil_defaultlib.glbl -o ila_tx_opt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_tx/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_tx/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_tx/hdl/verilog"
+ila_tx.v,verilog,xil_defaultlib,../../../ip/ila_tx/sim/ila_tx.v,incdir="../../../ip/ila_tx/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,173 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : ila_tx.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu Apr 06 15:13:21 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: ila_tx.sh [-help]
+# usage: ila_tx.sh [-lib_map_path]
+# usage: ila_tx.sh [-noclean_files]
+# usage: ila_tx.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'ila_tx.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "ila_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_tx.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_tx.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: ila_tx.sh [-help]\n\
+Usage: ila_tx.sh [-lib_map_path]\n\
+Usage: ila_tx.sh [-reset_run]\n\
+Usage: ila_tx.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -t 1ps -lib xil_defaultlib ila_tx_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {ila_tx.udo}
+
+run -all
+
+quit -force
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu Apr 06 15:13:21 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_tx.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_tx.sh' script.
+
+./ila_tx.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_tx.sh -noclean_files
+
+For more information on the script, please type './ila_tx.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,22 @@
+vlib work
+vlib riviera
+
+vlib riviera/xil_defaultlib
+vlib riviera/xpm
+
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap xpm riviera/xpm
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/ila_tx/hdl/verilog" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/ila_tx/hdl/verilog" \
+"../../../ip/ila_tx/sim/ila_tx.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
--- a/Show More
+++ b/Show More
				`@@ -0,0 +1 @@`
				`vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_tx xil_defaultlib.glbl -o ila_tx_opt`