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update duifei_cal_coarse

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in duifei_cal_coarse, split tx and rx ila, resynthesis with new ad9361 rx mapping strategy
This commit is contained in:
josh
2023-04-06 15:26:02 +08:00
parent 53bd4d459d
commit 14ac34e794
181 changed files with 458261 additions and 894532 deletions
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projects/duifei/duifei_cal_coarse/rtl/system_top.v
+15 -10
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@@ -739,19 +739,24 @@ vio_ant_rd u_vio_ant_rd (
.probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [95 : 0] probe_in5
);
ila_tx_rx u_ila_tx_rx
ila_tx u_ila_tx
(
.clk (sys_clk ), // input wire clk
.probe0 (tx_data_i ), // input wire [11:0] probe0
.probe1 (tx_data_q ), // input wire [11:0] probe1
.probe2 (rx_ch1_i ), // input wire [11:0] probe2
.probe3 (rx_ch1_q ), // input wire [11:0] probe3
.probe4 (rx_ch2_i ), // input wire [11:0] probe4
.probe5 (rx_ch2_q ), // input wire [11:0] probe5
.probe6 (rx_ch3_i ), // input wire [11:0] probe6
.probe7 (rx_ch3_q ), // input wire [11:0] probe7
.probe8 (rx_ch4_i ), // input wire [11:0] probe8
.probe9 (rx_ch4_q ) // input wire [11:0] probe9
.probe1 (tx_data_q ) // input wire [11:0] probe1
);
ila_rx u_ila_rx
(
.clk (sys_clk ), // input wire clk
.probe0 (rx_ch1_i ), // input wire [11:0] probe0
.probe1 (rx_ch1_q ), // input wire [11:0] probe1
.probe2 (rx_ch2_i ), // input wire [11:0] probe2
.probe3 (rx_ch2_q ), // input wire [11:0] probe3
.probe4 (rx_ch3_i ), // input wire [11:0] probe4
.probe5 (rx_ch3_q ), // input wire [11:0] probe5
.probe6 (rx_ch4_i ), // input wire [11:0] probe6
.probe7 (rx_ch4_q ) // input wire [11:0] probe7
);
ila_cal u_ila_cal