Archived
release duifei_cmos_v1.0
the function of duifei_cmos is tested, add vio_rfcontrol initial value
This commit is contained in:
+810
@@ -0,0 +1,810 @@
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<?xml version="1.0" encoding="UTF-8"?>
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</spirit:configurableElementValues>
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</spirit:componentInstance>
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</spirit:design>
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BIN
Binary file not shown.
+10394
File diff suppressed because one or more lines are too long
+14923
File diff suppressed because it is too large
Load Diff
+35
@@ -0,0 +1,35 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sat Apr 1 15:00:25 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.v
|
||||
// Design : vio_rfcontrl
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_out0, probe_out1, probe_out2,
|
||||
probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9,
|
||||
probe_out10, probe_out11, probe_out12)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0]" */;
|
||||
input clk;
|
||||
output [0:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
output [15:0]probe_out2;
|
||||
output [7:0]probe_out3;
|
||||
output [3:0]probe_out4;
|
||||
output [3:0]probe_out5;
|
||||
output [3:0]probe_out6;
|
||||
output [3:0]probe_out7;
|
||||
output [7:0]probe_out8;
|
||||
output [7:0]probe_out9;
|
||||
output [15:0]probe_out10;
|
||||
output [15:0]probe_out11;
|
||||
output [15:0]probe_out12;
|
||||
endmodule
|
||||
+43
@@ -0,0 +1,43 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sat Apr 1 15:00:25 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.vhdl
|
||||
-- Design : vio_rfcontrl
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_out9 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_out10 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out11 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out12 : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+5
-5
@@ -1,12 +1,12 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:31:00:00
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||||
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||||
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||||
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||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:32:00:00
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||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:34:00:00
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||||
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||||
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||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3738:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3836:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:33:00:00
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||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:31:00:00
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||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:32:00:00
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||||
@@ -20,10 +20,10 @@ version:1
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||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72657365745f636f6d706f736974655f66696c65:31:00:00
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7870675f636f6566696c65776964676465745f62726f777365:32:00:00
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||||
eof:2194046006
|
||||
eof:2846107009
|
||||
|
||||
+3
-3
@@ -4,8 +4,8 @@ version:1
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||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265706f72746970737461747573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757067726164656970:31:00:00
|
||||
eof:2810087140
|
||||
eof:1018782184
|
||||
|
||||
+1
-1
@@ -1,3 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:4
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:5
|
||||
eof:
|
||||
|
||||
+5
-5
@@ -1,7 +1,7 @@
|
||||
version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a3130306666673930302d32:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:616e745f636c6b5f67656e5f73746732:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:76696f5f7266636f6e74726c:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
@@ -33,7 +33,7 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313073:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323031332e3934314d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3631312e3035394d42:00:00
|
||||
eof:1824198752
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313173:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323131322e3738394d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3730372e3933344d42:00:00
|
||||
eof:3718360243
|
||||
|
||||
+9
-9
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Thu Mar 30 16:53:12 2023">
|
||||
<application name="pa" timeStamp="Sat Apr 1 15:00:58 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="fcb0b19a2b6a4584be9564047568bef1" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
@@ -22,20 +22,20 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="ManageCompositeTargets" value="3" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="2" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="1" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="10" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="2" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="13" type="JavaHandler"/>
|
||||
<property name="ReportIPStatus" value="1" type="JavaHandler"/>
|
||||
<property name="UpgradeIP" value="1" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="13" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="14" type="GuiHandlerData"/>
|
||||
<property name="BaseReportTab_RERUN" value="1" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="5" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="11" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="78" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="86" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="3" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
||||
<property name="HACGCCoeFileWidget_BROWSE" value="2" type="GuiHandlerData"/>
|
||||
@@ -49,17 +49,17 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="4" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="9" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="10" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="3" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="2" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="1" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="2" type="GuiHandlerData"/>
|
||||
<property name="XPG_CoeFileWidgdet_BROWSE" value="2" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="52" type="GuiMode"/>
|
||||
<property name="GuiMode" value="58" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="35" type="TclMode"/>
|
||||
<property name="TclMode" value="39" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="vio_rfcontrl_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="COSLUT_10_16bit_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
||||
<File Type="RDS-UTIL-PB" Name="COSLUT_10_16bit_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="COSLUT_10_16bit_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="COSLUT_10_16bit_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="COSLUT_10_16bit.vds"/>
|
||||
<File Type="RDS-DCP" Name="COSLUT_10_16bit.dcp"/>
|
||||
<File Type="PA-TCL" Name="COSLUT_10_16bit.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="GaussFir_12m_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
||||
<File Type="RDS-UTIL-PB" Name="GaussFir_12m_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="GaussFir_12m_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="GaussFir_12m_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="GaussFir_12m.vds"/>
|
||||
<File Type="RDS-DCP" Name="GaussFir_12m.dcp"/>
|
||||
<File Type="PA-TCL" Name="GaussFir_12m.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="GaussFir_1mp5_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
||||
<File Type="RDS-UTIL-PB" Name="GaussFir_1mp5_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="GaussFir_1mp5_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="GaussFir_1mp5_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="GaussFir_1mp5.vds"/>
|
||||
<File Type="RDS-DCP" Name="GaussFir_1mp5.dcp"/>
|
||||
<File Type="PA-TCL" Name="GaussFir_1mp5.tcl"/>
|
||||
|
||||
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ant_clk_gen_stg1_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680166379">
|
||||
<File Type="VDS-TIMING-PB" Name="ant_clk_gen_stg1_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ant_clk_gen_stg1_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg1_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ant_clk_gen_stg1_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg1_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg1_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ant_clk_gen_stg1">
|
||||
<File Path="$PPRDIR/../ant_clk_gen_stg1/ant_clk_gen_stg1.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ant_clk_gen_stg2_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680166392">
|
||||
<File Type="VDS-TIMING-PB" Name="ant_clk_gen_stg2_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ant_clk_gen_stg2_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg2_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ant_clk_gen_stg2_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg2_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg2_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ant_clk_gen_stg2">
|
||||
<File Path="$PPRDIR/../ant_clk_gen_stg2/ant_clk_gen_stg2.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="data_1p5m_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
||||
<File Type="RDS-UTIL-PB" Name="data_1p5m_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="data_1p5m_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="data_1p5m_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="data_1p5m.vds"/>
|
||||
<File Type="RDS-DCP" Name="data_1p5m.dcp"/>
|
||||
<File Type="PA-TCL" Name="data_1p5m.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="fifo_AntCtrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
||||
<File Type="RDS-UTIL-PB" Name="fifo_AntCtrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="fifo_AntCtrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="fifo_AntCtrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="fifo_AntCtrl.vds"/>
|
||||
<File Type="RDS-DCP" Name="fifo_AntCtrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="fifo_AntCtrl.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_AntCtrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
||||
<File Type="RDS-UTIL-PB" Name="ila_AntCtrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_AntCtrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_AntCtrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="ila_AntCtrl.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_AntCtrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_AntCtrl.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_rfcontrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||
<File Type="RDS-UTIL-PB" Name="ila_rfcontrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_rfcontrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_rfcontrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="ila_rfcontrl.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_rfcontrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_rfcontrl.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_tx_rx_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||
<File Type="RDS-UTIL-PB" Name="ila_tx_rx_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_tx_rx_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_tx_rx_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="ila_tx_rx.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_tx_rx.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_tx_rx.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_ant_rd_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||
<File Type="RDS-UTIL-PB" Name="vio_ant_rd_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_ant_rd_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_ant_rd_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="vio_ant_rd.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_ant_rd.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_ant_rd.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_ant_test_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||
<File Type="RDS-UTIL-PB" Name="vio_ant_test_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_ant_test_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_ant_test_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="vio_ant_test.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_ant_test.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_ant_test.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_clk_ld_rd_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||
<File Type="RDS-UTIL-PB" Name="vio_clk_ld_rd_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_clk_ld_rd_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_clk_ld_rd_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="vio_clk_ld_rd.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_clk_ld_rd.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_clk_ld_rd.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_manual_ctrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||
<File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_manual_ctrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_rf_rd_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||
<File Type="RDS-UTIL-PB" Name="vio_rf_rd_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_rf_rd_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_rf_rd_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="vio_rf_rd.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_rf_rd.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_rf_rd.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1236616" HostCore="20" HostMemory="65588996">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="21687" HostCore="20" HostMemory="65589000">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
+10
-7
@@ -1,20 +1,23 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_rfcontrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||
<GenRun Id="vio_rfcontrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680332406">
|
||||
<File Type="VDS-TIMING-PB" Name="vio_rfcontrl_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="vio_rfcontrl_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="vio_rfcontrl.dcp"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_rfcontrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_rfcontrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="vio_rfcontrl_drc_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="vio_rfcontrl.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_rfcontrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_rfcontrl.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="vio_rfcontrl_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="vio_rfcontrl.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_rfcontrl">
|
||||
<File Path="$PPRDIR/../vio_rfcontrl/vio_rfcontrl.xci">
|
||||
<File Path="$PPRDIR/../vio_rfcontrl.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../vio_rfcontrl.xcix">
|
||||
<File Path="$PPRDIR/../vio_rfcontrl/vio_rfcontrl.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
@@ -27,14 +30,14 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_rfcontrl">
|
||||
<File Path="$PPRDIR/../vio_rfcontrl/vio_rfcontrl.xci">
|
||||
<File Path="$PPRDIR/../vio_rfcontrl.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../vio_rfcontrl.xcix">
|
||||
<File Path="$PPRDIR/../vio_rfcontrl/vio_rfcontrl.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
|
||||
+11
-11
@@ -1,13 +1,13 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
@@ -37,12 +37,12 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3430:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3430:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3430:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3430:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3430:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3430:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3430:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6162313361656133326334373465343162373332306435626531383733633465:506172656e742050412070726f6a656374204944:00
|
||||
eof:1974806739
|
||||
eof:2407083661
|
||||
|
||||
BIN
Binary file not shown.
+79
-63
@@ -2,8 +2,8 @@
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Mar 30 16:42:15 2023
|
||||
# Process ID: 1237071
|
||||
# Start of session at: Sat Apr 1 15:00:07 2023
|
||||
# Process ID: 21726
|
||||
# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1
|
||||
# Command line: vivado -log vio_rfcontrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rfcontrl.tcl
|
||||
# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds
|
||||
@@ -16,16 +16,30 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100'
|
||||
INFO: [Device 21-403] Loading part xc7z100ffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 1237431
|
||||
INFO: Helper process launched with PID 21828
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1858.664 ; gain = 152.719 ; free physical = 423 ; free virtual = 39456
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.508 ; gain = 153.719 ; free physical = 28641 ; free virtual = 57975
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'vio_rfcontrl' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59]
|
||||
WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rfcontrl does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/vio_rfcontrl/synth/vio_rfcontrl.v:95]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'vio_rfcontrl' (7#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[14]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[13]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[12]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[11]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[10]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[9]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[8]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[15]
|
||||
@@ -52,6 +66,9 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unc
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[5]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[4]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15]
|
||||
@@ -106,26 +123,9 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in34[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in35[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in36[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in37[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in38[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in39[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in40[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in41[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in42[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in43[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in44[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in45[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in46[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in47[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in48[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in49[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in50[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in51[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in52[0]
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1921.352 ; gain = 215.406 ; free physical = 433 ; free virtual = 38809
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1922.195 ; gain = 215.406 ; free physical = 28666 ; free virtual = 58002
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -138,10 +138,10 @@ Report Check Netlist:
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1924.320 ; gain = 218.375 ; free physical = 553 ; free virtual = 38862
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.164 ; gain = 218.375 ; free physical = 28665 ; free virtual = 58001
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1924.320 ; gain = 218.375 ; free physical = 553 ; free virtual = 38861
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.164 ; gain = 218.375 ; free physical = 28665 ; free virtual = 58001
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
@@ -153,29 +153,29 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip
|
||||
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/vio_rfcontrl/vio_rfcontrl.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2097.977 ; gain = 0.000 ; free physical = 511 ; free virtual = 38386
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.852 ; gain = 0.000 ; free physical = 28545 ; free virtual = 57895
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2105.914 ; gain = 7.938 ; free physical = 497 ; free virtual = 38371
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2112.789 ; gain = 6.938 ; free physical = 28545 ; free virtual = 57895
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 504 ; free virtual = 38382
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28646 ; free virtual = 57997
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z100ffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 503 ; free virtual = 38381
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28646 ; free virtual = 57997
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 496 ; free virtual = 38374
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28647 ; free virtual = 57997
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 571 ; free virtual = 38460
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28640 ; free virtual = 57991
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -235,6 +235,21 @@ Detailed RTL Component Info :
|
||||
4 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_one__parameterized3
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
8 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_one__parameterized4
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 2
|
||||
Module vio_v3_0_20_probe_out_one__parameterized5
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 2
|
||||
Module vio_v3_0_20_probe_out_all
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
@@ -404,7 +419,7 @@ INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int
|
||||
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] )
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 514 ; free virtual = 38415
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28623 ; free virtual = 57976
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -416,13 +431,13 @@ Report RTL Partitions:
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 412 ; free virtual = 37849
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28491 ; free virtual = 57852
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 405 ; free virtual = 37840
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28491 ; free virtual = 57852
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -434,7 +449,7 @@ Report RTL Partitions:
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 439 ; free virtual = 37809
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -495,7 +510,7 @@ WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 444 ; free virtual = 37817
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -508,7 +523,7 @@ Report Check Netlist:
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 444 ; free virtual = 37817
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -520,25 +535,25 @@ Report RTL Partitions:
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 442 ; free virtual = 37815
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 442 ; free virtual = 37815
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 439 ; free virtual = 37812
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 439 ; free virtual = 37812
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -559,7 +574,8 @@ Report Cell Usage:
|
||||
|3 |LUT4 | 8|
|
||||
|4 |LUT5 | 20|
|
||||
|5 |LUT6 | 112|
|
||||
|6 |FDRE | 479|
|
||||
|6 |FDRE | 455|
|
||||
|7 |FDSE | 24|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
@@ -572,47 +588,47 @@ Report Instance Areas:
|
||||
|4 | DECODER_INST |vio_v3_0_20_decoder | 85|
|
||||
|5 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 302|
|
||||
|6 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3|
|
||||
|7 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 32|
|
||||
|8 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_0 | 32|
|
||||
|9 | \G_PROBE_OUT[12].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_1 | 32|
|
||||
|10 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 3|
|
||||
|11 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_3 | 32|
|
||||
|7 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4 | 32|
|
||||
|8 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4_0 | 32|
|
||||
|9 | \G_PROBE_OUT[12].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized5 | 32|
|
||||
|10 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 3|
|
||||
|11 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 32|
|
||||
|12 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 16|
|
||||
|13 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 8|
|
||||
|14 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_4 | 8|
|
||||
|15 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_5 | 8|
|
||||
|16 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_6 | 8|
|
||||
|17 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_7 | 16|
|
||||
|18 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_8 | 16|
|
||||
|14 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_2 | 8|
|
||||
|15 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_3 | 8|
|
||||
|16 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_4 | 8|
|
||||
|17 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_5 | 16|
|
||||
|18 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 16|
|
||||
|19 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 18|
|
||||
+------+----------------------------------------+--------------------------------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 439 ; free virtual = 37812
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 293 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2105.914 ; gain = 218.375 ; free physical = 494 ; free virtual = 37866
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 510 ; free virtual = 37878
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2112.789 ; gain = 218.375 ; free physical = 28544 ; free virtual = 57905
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28558 ; free virtual = 57918
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.914 ; gain = 0.000 ; free physical = 1251 ; free virtual = 38617
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2112.789 ; gain = 0.000 ; free physical = 28478 ; free virtual = 57839
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
123 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 2105.914 ; gain = 708.902 ; free physical = 1296 ; free virtual = 38663
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.914 ; gain = 0.000 ; free physical = 1300 ; free virtual = 38667
|
||||
synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2112.789 ; gain = 713.871 ; free physical = 28571 ; free virtual = 57931
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2112.789 ; gain = 0.000 ; free physical = 28571 ; free virtual = 57931
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rfcontrl, cache-ID = 2d036cfb99334b0d
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rfcontrl, cache-ID = 88af289b6f841f2b
|
||||
INFO: [Coretcl 2-1174] Renamed 18 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2129.926 ; gain = 0.000 ; free physical = 1232 ; free virtual = 38604
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2136.801 ; gain = 0.000 ; free physical = 28574 ; free virtual = 57936
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Mar 30 16:42:42 2023...
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Apr 1 15:00:25 2023...
|
||||
|
||||
+1062
-1062
File diff suppressed because one or more lines are too long
+1266
-1266
File diff suppressed because it is too large
Load Diff
+1
-1
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:42:42 2023
|
||||
// Date : Sat Apr 1 15:00:25 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:42:42 2023
|
||||
-- Date : Sat Apr 1 15:00:25 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl
|
||||
|
||||
+5
-4
@@ -1,7 +1,7 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
| Date : Thu Mar 30 16:42:42 2023
|
||||
| Date : Sat Apr 1 15:00:25 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
| Command : report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb
|
||||
| Design : vio_rfcontrl
|
||||
@@ -56,8 +56,8 @@ Table of Contents
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 479 | Yes | Reset | - |
|
||||
| 24 | Yes | Set | - |
|
||||
| 455 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@@ -152,9 +152,10 @@ Table of Contents
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 479 | Flop & Latch |
|
||||
| FDRE | 455 | Flop & Latch |
|
||||
| LUT6 | 112 | LUT |
|
||||
| LUT3 | 43 | LUT |
|
||||
| FDSE | 24 | Flop & Latch |
|
||||
| LUT5 | 20 | LUT |
|
||||
| LUT4 | 8 | LUT |
|
||||
| LUT2 | 7 | LUT |
|
||||
|
||||
BIN
Binary file not shown.
@@ -39,13 +39,13 @@
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="40"/>
|
||||
<Option Name="WTModelSimExportSim" Val="40"/>
|
||||
<Option Name="WTQuestaExportSim" Val="40"/>
|
||||
<Option Name="WTIesExportSim" Val="40"/>
|
||||
<Option Name="WTVcsExportSim" Val="40"/>
|
||||
<Option Name="WTRivieraExportSim" Val="40"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="40"/>
|
||||
<Option Name="WTXSimExportSim" Val="41"/>
|
||||
<Option Name="WTModelSimExportSim" Val="41"/>
|
||||
<Option Name="WTQuestaExportSim" Val="41"/>
|
||||
<Option Name="WTIesExportSim" Val="41"/>
|
||||
<Option Name="WTVcsExportSim" Val="41"/>
|
||||
<Option Name="WTRivieraExportSim" Val="41"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="41"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -607,9 +607,7 @@
|
||||
</Run>
|
||||
<Run Id="ant_clk_gen_stg1_synth_1" Type="Ft3:Synth" SrcSet="ant_clk_gen_stg1" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ant_clk_gen_stg1_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -618,9 +616,7 @@
|
||||
</Run>
|
||||
<Run Id="ant_clk_gen_stg2_synth_1" Type="Ft3:Synth" SrcSet="ant_clk_gen_stg2" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ant_clk_gen_stg2_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -869,9 +865,7 @@
|
||||
</Run>
|
||||
<Run Id="ant_clk_gen_stg1_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ant_clk_gen_stg1_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -887,9 +881,7 @@
|
||||
</Run>
|
||||
<Run Id="ant_clk_gen_stg2_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ant_clk_gen_stg2_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
|
||||
Reference in New Issue
Block a user