Archived
release duifei_cmos_v1.0
the function of duifei_cmos is tested, add vio_rfcontrol initial value
This commit is contained in:
-283
@@ -1,283 +0,0 @@
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`pragma protect begin_protected
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`pragma protect version = 1
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`pragma protect encrypt_agent = "XILINX"
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`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
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`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`pragma protect key_block
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XWe4lBDDrw==
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`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`pragma protect key_block
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eVhT3XSIJDvufMyiJUc=
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`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`pragma protect key_block
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`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`pragma protect key_block
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4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A==
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`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`pragma protect key_block
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draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg==
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`pragma protect key_block
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R19uHYIhWP+7IpmjTiQ=
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`pragma protect key_block
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mf7t4ZoEITJYnmd5zcenAnw+6AO3fUwtTLT81Q==
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`pragma protect data_method = "AES128-CBC"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
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`pragma protect data_block
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dXHULePP/Gipl82oGh1JJCdAQ9LDpey65p0KEjYXXANeTZwhPYOga4BHA0oN4pwOdnTeCb5A4iZ/
|
|
||||||
heS3mgFhvHAhevmsEhIK2h2zSF3Akf5BwgPCbpnCYkYb+ME0TdvNEiJCphU9jUE4p5X9A9dSGDJj
|
|
||||||
khYzrG0vqQ5aTHUtA/ettxOdp4eUS7ysX0thI24EuES+7VvT4f8wgeSqBHZFzQ/CElgrRx4ExPs7
|
|
||||||
D0v5Ej5wagiorCgqq7nJ+WVo4jzSjwP1YPz0OorE1bZuBq7lGr3Rbp63T09vP9TTzlMsJSWxGHqT
|
|
||||||
JeKFlv86ZJ1h39w2Zj+8gJ4U4AZbOygG4bLImMVZigruDqvkaOxNreC1k+1vLgOPtZ/kWzXOwH+O
|
|
||||||
/KlC0MjIWmtLxc4WQHgphsph364TvIk2pNXhw0kVpwDtyTQQTZ0uelX9+IewGOhxjBSp71WJ3KS6
|
|
||||||
vd6oUylWNSjtHxK7eVyclTxCvy8AwzP5K+8lwRzhDkWw2j7nriqzZ6sBQ8sc55H3/PkQ1nhDvP3S
|
|
||||||
Y4mETg95nQKorrqSDgb6WO6YmD7apM6gCf2H5/4poh7YLqjOw7ajEzyPcoHqdJRC+6dswNNb8pdu
|
|
||||||
Eynk1RGGG3fnXVSGn5SSGA2S8xxJpeOPXqhwWm47l709TR53pdlNgeNlLSat/LE3Yr6f3dzCO3+M
|
|
||||||
mLQSSv4FDwGW+hU2bHZPiUhUUQSmaa9T19pbpa6s8ZJ0xLEbS3z1xEajwM0bFGEGE+lodnN0Ziu+
|
|
||||||
StlkG0O7ozjg6V6hRnz8KkJqNDirqESfbjE6WMHtc599lGztc/77jnBfdHd3VIuf4IgUcezITMqj
|
|
||||||
5MGygT2/VAEb4BZAbcRxPGqKcLfYnJZ63t3QEqbgblMA1vFo4VgSV1ajLUyoDGBGLV28ExlwTut1
|
|
||||||
HzIaED7RvsGxFpR26+1akJ1/8bReaeZFhca9QQVHRvj1X698r4C/XUsrSc+05XtjMx6HM5q1yZwu
|
|
||||||
pU7X3s5l0gEMjqTKe4cxHPW2hjvKhiEEb66pzjN7HK0y5nrjMJxzwtfqbNV7b76TcDtX27W08c9U
|
|
||||||
hsEprM3gDA7yAWiwAy3nxW57jdofbM5LfU0HVc1mK3FN0pfA/Fg0HWk0RX6K1vbYorZ2YFYwkpIK
|
|
||||||
Spx8l1Y/4Kpd/0yvO9c4f8OcsEc6LfaQSV83l2H8v6NalHbhaZ2gKxmDZi/k03xDyL8v6GCn18bp
|
|
||||||
dB5LUUJUKbnsl6q5E9b8DkJqSnAaHRLJDnEvMp6EfGlpc52On3lCg0wI5XERerziamjcMH44VZfd
|
|
||||||
j8z1WUyHlyOSmkvZdJ66PfYWu5BxCG7hfdtSGROPtIxs36iLmesyYm4yHKwwbWgNIrLgra92DF2L
|
|
||||||
R6e0RM1WWkcJHei4v89Nmwym4k0dKMTX1HkfTogoprrdIyDYj4qMmeTqfl0U8pRehVs6/zy4x8HS
|
|
||||||
0V2+smFFQ/BZxLQ4eV8NHKeszc4kI6jJ3OCncsP57tfkE6TmVTtWKiimERISYB4KhUpblsbN6zyX
|
|
||||||
Bni5ezNwl9XdaBq9c90k+QQmaMGeyQbczdGy9ufcC269vB1FU5+a67Ew8h0jPAPeYHvsw4kGsTSh
|
|
||||||
xnhGNUHRuPoNmQYBjI2LztvnbGuoucUVntUi5quKpKAK1fOZerZTh+kr5PjaW0YlozpL5CtElvS3
|
|
||||||
eqqkVT8a5mdW+sWTxJxTjqronag0QACsSwbA9qurCW9IdcOO+0D7nzfIJIFrWKx+D71JhKNvOmUa
|
|
||||||
NmCy9l+wzdpcLs1zvS3o3zwEgUWOOHzITgzOxtDhIuBcJkg9lS+o5b+W+U9fplCbVFjYd5ZDa2sX
|
|
||||||
90/8XCJA0a9VcsSrh1LoO0V3YX80VWdNPY79OUOlqftl3rNXVXE=
|
|
||||||
`pragma protect end_protected
|
|
||||||
@@ -68,17 +68,17 @@ input clk;
|
|||||||
|
|
||||||
output reg [0 : 0] probe_out0 = 'h0 ;
|
output reg [0 : 0] probe_out0 = 'h0 ;
|
||||||
output reg [0 : 0] probe_out1 = 'h0 ;
|
output reg [0 : 0] probe_out1 = 'h0 ;
|
||||||
output reg [15 : 0] probe_out2 = 'h0000 ;
|
output reg [15 : 0] probe_out2 = 'h05DC ;
|
||||||
output reg [7 : 0] probe_out3 = 'h00 ;
|
output reg [7 : 0] probe_out3 = 'h00 ;
|
||||||
output reg [3 : 0] probe_out4 = 'h0 ;
|
output reg [3 : 0] probe_out4 = 'h0 ;
|
||||||
output reg [3 : 0] probe_out5 = 'h0 ;
|
output reg [3 : 0] probe_out5 = 'h0 ;
|
||||||
output reg [3 : 0] probe_out6 = 'h0 ;
|
output reg [3 : 0] probe_out6 = 'h0 ;
|
||||||
output reg [3 : 0] probe_out7 = 'h0 ;
|
output reg [3 : 0] probe_out7 = 'h0 ;
|
||||||
output reg [7 : 0] probe_out8 = 'h00 ;
|
output reg [7 : 0] probe_out8 = 'h00 ;
|
||||||
output reg [7 : 0] probe_out9 = 'h00 ;
|
output reg [7 : 0] probe_out9 = 'h04 ;
|
||||||
output reg [15 : 0] probe_out10 = 'h0000 ;
|
output reg [15 : 0] probe_out10 = 'h0000 ;
|
||||||
output reg [15 : 0] probe_out11 = 'h0000 ;
|
output reg [15 : 0] probe_out11 = 'h0000 ;
|
||||||
output reg [15 : 0] probe_out12 = 'h0000 ;
|
output reg [15 : 0] probe_out12 = 'h1680 ;
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
+1062
-1062
File diff suppressed because one or more lines are too long
+1266
-1266
File diff suppressed because it is too large
Load Diff
@@ -1,7 +1,7 @@
|
|||||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
// --------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------
|
||||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
// Date : Thu Mar 30 16:42:42 2023
|
// Date : Sat Apr 1 15:00:25 2023
|
||||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
// Command : write_verilog -force -mode synth_stub
|
// Command : write_verilog -force -mode synth_stub
|
||||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v
|
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v
|
||||||
|
|||||||
@@ -1,7 +1,7 @@
|
|||||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
-- Date : Thu Mar 30 16:42:42 2023
|
-- Date : Sat Apr 1 15:00:25 2023
|
||||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
-- Command : write_vhdl -force -mode synth_stub
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl
|
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl
|
||||||
|
|||||||
@@ -1,671 +0,0 @@
|
|||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
//
|
|
||||||
// Company: Xilinx
|
|
||||||
// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
|
|
||||||
// Date: 7/30/2014
|
|
||||||
// Design Name: MMCME2 DRP
|
|
||||||
// Module Name: mmcme2_drp_func.h
|
|
||||||
// Version: 1.04
|
|
||||||
// Target Devices: 7 Series || MMCM
|
|
||||||
// Tool versions: 2014.3
|
|
||||||
// Description: This header provides the functions necessary to
|
|
||||||
// calculate the DRP register values for the V6 MMCM.
|
|
||||||
//
|
|
||||||
// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR)
|
|
||||||
// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
|
|
||||||
//
|
|
||||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
|
||||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
|
||||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
|
||||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
|
||||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
|
||||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
|
||||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
|
||||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
|
||||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
|
||||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
|
||||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
|
||||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
|
||||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
|
||||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
|
||||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
|
||||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
// PURPOSE.
|
|
||||||
//
|
|
||||||
// (c) Copyright 2009-2010 Xilinx, Inc.
|
|
||||||
// All rights reserved.
|
|
||||||
//
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
|
|
||||||
// These are user functions that should not be modified. Changes to the defines
|
|
||||||
// or code within the functions may alter the accuracy of the calculations.
|
|
||||||
|
|
||||||
// Define debug to provide extra messages durring elaboration
|
|
||||||
//`define DEBUG 1
|
|
||||||
|
|
||||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
|
||||||
// point numbers. These should not be modified, they are for development
|
|
||||||
// only
|
|
||||||
`define FRAC_PRECISION 10
|
|
||||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
|
||||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
|
||||||
// greater than 32
|
|
||||||
`define FIXED_WIDTH 32
|
|
||||||
|
|
||||||
// This function takes a fixed point number and rounds it to the nearest
|
|
||||||
// fractional precision bit.
|
|
||||||
function [`FIXED_WIDTH:1] round_frac
|
|
||||||
(
|
|
||||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
|
||||||
input [`FIXED_WIDTH:1] decimal,
|
|
||||||
|
|
||||||
// This describes the precision of the fraction, for example a value
|
|
||||||
// of 1 would modify the fractional so that instead of being a .16
|
|
||||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
|
||||||
input [`FIXED_WIDTH:1] precision
|
|
||||||
);
|
|
||||||
|
|
||||||
begin
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
|
||||||
`endif
|
|
||||||
// If the fractional precision bit is high then round up
|
|
||||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
|
||||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
|
||||||
end else begin
|
|
||||||
round_frac = decimal;
|
|
||||||
end
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("round_frac: %h", round_frac);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function calculates high_time, low_time, w_edge, and no_count
|
|
||||||
// of a non-fractional counter based on the divide and duty cycle
|
|
||||||
//
|
|
||||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
|
||||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
|
||||||
// ignore the overflow)
|
|
||||||
function [13:0] mmcm_pll_divider
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
|
||||||
|
|
||||||
// High/Low time is initially calculated with a wider integer to prevent a
|
|
||||||
// calculation error when it overflows to 64.
|
|
||||||
reg [6:0] high_time;
|
|
||||||
reg [6:0] low_time;
|
|
||||||
reg w_edge;
|
|
||||||
reg no_count;
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] temp;
|
|
||||||
|
|
||||||
begin
|
|
||||||
// Duty Cycle must be between 0 and 1,000
|
|
||||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
|
||||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
|
||||||
// Other values are dummies
|
|
||||||
if(divide == 7'h01) begin
|
|
||||||
high_time = 7'h01;
|
|
||||||
w_edge = 1'b0;
|
|
||||||
low_time = 7'h01;
|
|
||||||
no_count = 1'b1;
|
|
||||||
end else begin
|
|
||||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
|
||||||
|
|
||||||
// comes from above round_frac
|
|
||||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
|
||||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
|
||||||
// is set.
|
|
||||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
|
||||||
|
|
||||||
// If the high time comes out to 0, it needs to be set to at least 1
|
|
||||||
// and w_edge set to 0
|
|
||||||
if(high_time == 7'h00) begin
|
|
||||||
high_time = 7'h01;
|
|
||||||
w_edge = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
if(high_time == divide) begin
|
|
||||||
high_time = divide - 1;
|
|
||||||
w_edge = 1'b1;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Calculate low_time based on the divide setting and set no_count to
|
|
||||||
// 0 as it is only used when divide is 1.
|
|
||||||
low_time = divide - high_time;
|
|
||||||
no_count = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Set the return value.
|
|
||||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function calculates mx, delay_time, and phase_mux
|
|
||||||
// of a non-fractional counter based on the divide and phase
|
|
||||||
//
|
|
||||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
|
||||||
// is used.
|
|
||||||
function [10:0] mmcm_pll_phase
|
|
||||||
(
|
|
||||||
// divide must be an integer (use fractional if not)
|
|
||||||
// assumed that divide already checked to be valid
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
|
|
||||||
// Phase is given in degrees (-360,000 to 360,000)
|
|
||||||
input signed [31:0] phase
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
|
||||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
|
||||||
reg [1:0] mx;
|
|
||||||
reg [5:0] delay_time;
|
|
||||||
reg [2:0] phase_mux;
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] temp;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_pll_phase-divide:%d,phase:%d",
|
|
||||||
divide, phase);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
if ((phase < -360000) || (phase > 360000)) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
// If phase is less than 0, convert it to a positive phase shift
|
|
||||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
|
||||||
if(phase < 0) begin
|
|
||||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
|
||||||
end else begin
|
|
||||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Put phase in terms of decimal number of vco clock cycles
|
|
||||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
|
|
||||||
temp = round_frac(phase_in_cycles, 3);
|
|
||||||
|
|
||||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
|
||||||
mx = 2'b00;
|
|
||||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
|
||||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("temp: %h", temp);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// Setup the return value
|
|
||||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes the divide value and outputs the necessary lock values
|
|
||||||
function [39:0] mmcm_pll_lock_lookup
|
|
||||||
(
|
|
||||||
input [6:0] divide // Max divide is 64
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [2559:0] lookup;
|
|
||||||
|
|
||||||
begin
|
|
||||||
lookup = {
|
|
||||||
// This table is composed of:
|
|
||||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
|
||||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
|
||||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
|
||||||
40'b01000_01000_1111101000_1111101001_0000000001,
|
|
||||||
40'b01011_01011_1111101000_1111101001_0000000001,
|
|
||||||
40'b01110_01110_1111101000_1111101001_0000000001,
|
|
||||||
40'b10001_10001_1111101000_1111101001_0000000001,
|
|
||||||
40'b10011_10011_1111101000_1111101001_0000000001,
|
|
||||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
|
||||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
|
||||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001
|
|
||||||
};
|
|
||||||
|
|
||||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
|
||||||
mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes the divide value and the bandwidth setting of the MMCM
|
|
||||||
// and outputs the digital filter settings necessary.
|
|
||||||
function [9:0] mmcm_pll_filter_lookup
|
|
||||||
(
|
|
||||||
input [6:0] divide, // Max divide is 64
|
|
||||||
input [8*9:0] BANDWIDTH
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [639:0] lookup_low;
|
|
||||||
reg [639:0] lookup_high;
|
|
||||||
|
|
||||||
reg [9:0] lookup_entry;
|
|
||||||
|
|
||||||
begin
|
|
||||||
lookup_low = {
|
|
||||||
// CP_RES_LFHF
|
|
||||||
10'b0010_1111_00,
|
|
||||||
10'b0010_1111_00,
|
|
||||||
10'b0010_1111_00,
|
|
||||||
10'b0010_1111_00,
|
|
||||||
10'b0010_0111_00,
|
|
||||||
10'b0010_1011_00,
|
|
||||||
10'b0010_1101_00,
|
|
||||||
10'b0010_0011_00,
|
|
||||||
10'b0010_0101_00,
|
|
||||||
10'b0010_0101_00,
|
|
||||||
10'b0010_1001_00,
|
|
||||||
10'b0010_1110_00,
|
|
||||||
10'b0010_1110_00,
|
|
||||||
10'b0010_1110_00,
|
|
||||||
10'b0010_1110_00,
|
|
||||||
10'b0010_0001_00,
|
|
||||||
10'b0010_0001_00,
|
|
||||||
10'b0010_0001_00,
|
|
||||||
10'b0010_0110_00,
|
|
||||||
10'b0010_0110_00,
|
|
||||||
10'b0010_0110_00,
|
|
||||||
10'b0010_0110_00,
|
|
||||||
10'b0010_0110_00,
|
|
||||||
10'b0010_0110_00,
|
|
||||||
10'b0010_0110_00,
|
|
||||||
10'b0010_1010_00,
|
|
||||||
10'b0010_1010_00,
|
|
||||||
10'b0010_1010_00,
|
|
||||||
10'b0010_1010_00,
|
|
||||||
10'b0010_1010_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00
|
|
||||||
};
|
|
||||||
|
|
||||||
lookup_high = {
|
|
||||||
// CP_RES_LFHF
|
|
||||||
10'b0010_1111_00,
|
|
||||||
10'b0100_1111_00,
|
|
||||||
10'b0101_1011_00,
|
|
||||||
10'b0111_0111_00,
|
|
||||||
10'b1101_0111_00,
|
|
||||||
10'b1110_1011_00,
|
|
||||||
10'b1110_1101_00,
|
|
||||||
10'b1111_0011_00,
|
|
||||||
10'b1110_0101_00,
|
|
||||||
10'b1111_0101_00,
|
|
||||||
10'b1111_1001_00,
|
|
||||||
10'b1101_0001_00,
|
|
||||||
10'b1111_1001_00,
|
|
||||||
10'b1111_1001_00,
|
|
||||||
10'b1111_1001_00,
|
|
||||||
10'b1111_1001_00,
|
|
||||||
10'b1111_0101_00,
|
|
||||||
10'b1111_0101_00,
|
|
||||||
10'b1100_0001_00,
|
|
||||||
10'b1100_0001_00,
|
|
||||||
10'b1100_0001_00,
|
|
||||||
10'b0101_1100_00,
|
|
||||||
10'b0101_1100_00,
|
|
||||||
10'b0101_1100_00,
|
|
||||||
10'b0101_1100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0111_0001_00,
|
|
||||||
10'b0111_0001_00,
|
|
||||||
10'b0100_1100_00,
|
|
||||||
10'b0100_1100_00,
|
|
||||||
10'b0100_1100_00,
|
|
||||||
10'b0100_1100_00,
|
|
||||||
10'b0110_0001_00,
|
|
||||||
10'b0110_0001_00,
|
|
||||||
10'b0101_0110_00,
|
|
||||||
10'b0101_0110_00,
|
|
||||||
10'b0101_0110_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0100_1010_00,
|
|
||||||
10'b0011_1100_00,
|
|
||||||
10'b0011_1100_00
|
|
||||||
};
|
|
||||||
|
|
||||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
|
||||||
if(BANDWIDTH == "LOW") begin
|
|
||||||
// Low Bandwidth
|
|
||||||
mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
|
|
||||||
end else begin
|
|
||||||
// High or optimized bandwidth
|
|
||||||
mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
|
|
||||||
end
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes in the divide, phase, and duty cycle
|
|
||||||
// setting to calculate the upper and lower counter registers.
|
|
||||||
function [37:0] mmcm_pll_count_calc
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input signed [31:0] phase,
|
|
||||||
input [31:0] duty_cycle // Multiplied by 100,000
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [13:0] div_calc;
|
|
||||||
reg [16:0] phase_calc;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
|
||||||
divide, phase, duty_cycle);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
|
||||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
|
||||||
// mx[10:9], pm[8:6], dt[5:0]
|
|
||||||
phase_calc = mmcm_pll_phase(divide, phase);
|
|
||||||
|
|
||||||
// Return value is the upper and lower address of counter
|
|
||||||
// Upper address is:
|
|
||||||
// RESERVED [31:26]
|
|
||||||
// MX [25:24]
|
|
||||||
// EDGE [23]
|
|
||||||
// NOCOUNT [22]
|
|
||||||
// DELAY_TIME [21:16]
|
|
||||||
// Lower Address is:
|
|
||||||
// PHASE_MUX [15:13]
|
|
||||||
// RESERVED [12]
|
|
||||||
// HIGH_TIME [11:6]
|
|
||||||
// LOW_TIME [5:0]
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
|
||||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
|
||||||
div_calc[13], div_calc[12],
|
|
||||||
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
mmcm_pll_count_calc =
|
|
||||||
{
|
|
||||||
// Upper Address
|
|
||||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
|
||||||
// Lower Address
|
|
||||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
|
||||||
};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
|
|
||||||
// This function takes in the divide, phase, and duty cycle
|
|
||||||
// setting to calculate the upper and lower counter registers.
|
|
||||||
// for fractional multiply/divide functions.
|
|
||||||
//
|
|
||||||
//
|
|
||||||
function [37:0] mmcm_frac_count_calc
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input signed [31:0] phase,
|
|
||||||
input [31:0] duty_cycle, // Multiplied by 1,000
|
|
||||||
input [9:0] frac // Multiplied by 1000
|
|
||||||
);
|
|
||||||
|
|
||||||
//Required for fractional divide calculations
|
|
||||||
reg [7:0] lt_frac;
|
|
||||||
reg [7:0] ht_frac;
|
|
||||||
|
|
||||||
reg /*[7:0]*/ wf_fall_frac;
|
|
||||||
reg /*[7:0]*/ wf_rise_frac;
|
|
||||||
|
|
||||||
reg [31:0] a;
|
|
||||||
reg [7:0] pm_rise_frac_filtered ;
|
|
||||||
reg [7:0] pm_fall_frac_filtered ;
|
|
||||||
reg [7:0] clkout0_divide_int;
|
|
||||||
reg [2:0] clkout0_divide_frac;
|
|
||||||
reg [7:0] even_part_high;
|
|
||||||
reg [7:0] even_part_low;
|
|
||||||
|
|
||||||
reg [7:0] odd;
|
|
||||||
reg [7:0] odd_and_frac;
|
|
||||||
|
|
||||||
reg [7:0] pm_fall;
|
|
||||||
reg [7:0] pm_rise;
|
|
||||||
reg [7:0] dt;
|
|
||||||
reg [7:0] dt_int;
|
|
||||||
reg [63:0] dt_calc;
|
|
||||||
|
|
||||||
reg [7:0] pm_rise_frac;
|
|
||||||
reg [7:0] pm_fall_frac;
|
|
||||||
|
|
||||||
reg [31:0] a_per_in_octets;
|
|
||||||
reg [31:0] a_phase_in_cycles;
|
|
||||||
|
|
||||||
parameter precision = 0.125;
|
|
||||||
|
|
||||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
|
||||||
reg [31: 0] phase_pos;
|
|
||||||
reg [31: 0] phase_vco;
|
|
||||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
|
||||||
reg [13:0] div_calc;
|
|
||||||
reg [16:0] phase_calc;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
|
||||||
divide, phase, duty_cycle);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
//convert phase to fixed
|
|
||||||
if ((phase < -360000) || (phase > 360000)) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
// Return value is
|
|
||||||
// Transfer data
|
|
||||||
// RESERVED [37:36]
|
|
||||||
// FRAC_TIME [35:33]
|
|
||||||
// FRAC_WF_FALL [32]
|
|
||||||
// Upper address is:
|
|
||||||
// RESERVED [31:26]
|
|
||||||
// MX [25:24]
|
|
||||||
// EDGE [23]
|
|
||||||
// NOCOUNT [22]
|
|
||||||
// DELAY_TIME [21:16]
|
|
||||||
// Lower Address is:
|
|
||||||
// PHASE_MUX [15:13]
|
|
||||||
// RESERVED [12]
|
|
||||||
// HIGH_TIME [11:6]
|
|
||||||
// LOW_TIME [5:0]
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
clkout0_divide_frac = frac / 125;
|
|
||||||
clkout0_divide_int = divide;
|
|
||||||
|
|
||||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
|
||||||
even_part_low = even_part_high;
|
|
||||||
|
|
||||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
|
||||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
|
||||||
|
|
||||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
|
||||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
|
||||||
|
|
||||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
|
||||||
pm_rise = 0; //0
|
|
||||||
|
|
||||||
wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
|
|
||||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//Calculate phase in fractional cycles
|
|
||||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
|
||||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
|
||||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
|
||||||
|
|
||||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
|
||||||
dt = dt_calc[7:0];
|
|
||||||
|
|
||||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
|
||||||
|
|
||||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
|
||||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
|
||||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
|
||||||
|
|
||||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
|
||||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
|
||||||
|
|
||||||
mmcm_frac_count_calc[37:0] =
|
|
||||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
|
||||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
|
||||||
pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
|
||||||
} ;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
@@ -1,531 +0,0 @@
|
|||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
//
|
|
||||||
// Company: Xilinx
|
|
||||||
// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
|
|
||||||
// Date: 7/30/2014
|
|
||||||
// Design Name: PLLE2 DRP
|
|
||||||
// Module Name: plle2_drp_func.h
|
|
||||||
// Version: 2.00
|
|
||||||
// Target Devices: 7 Series || PLL
|
|
||||||
// Tool versions: 2014.3
|
|
||||||
// Description: This header provides the functions necessary to
|
|
||||||
// calculate the DRP register values for the V6 PLL.
|
|
||||||
// Updated for CR663854.
|
|
||||||
//
|
|
||||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
|
||||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
|
||||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
|
||||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
|
||||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
|
||||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
|
||||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
|
||||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
|
||||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
|
||||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
|
||||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
|
||||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
|
||||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
|
||||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
|
||||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
|
||||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
// PURPOSE.
|
|
||||||
//
|
|
||||||
// (c) Copyright 2009-2010 Xilinx, Inc.
|
|
||||||
// All rights reserved.
|
|
||||||
//
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
|
|
||||||
// These are user functions that should not be modified. Changes to the defines
|
|
||||||
// or code within the functions may alter the accuracy of the calculations.
|
|
||||||
|
|
||||||
// Define debug to provide extra messages durring elaboration
|
|
||||||
//`define DEBUG 1
|
|
||||||
|
|
||||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
|
||||||
// point numbers. These should not be modified, they are for development
|
|
||||||
// only
|
|
||||||
`define FRAC_PRECISION 10
|
|
||||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
|
||||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
|
||||||
// greater than 32
|
|
||||||
`define FIXED_WIDTH 32
|
|
||||||
|
|
||||||
// This function takes a fixed point number and rounds it to the nearest
|
|
||||||
// fractional precision bit.
|
|
||||||
function [`FIXED_WIDTH:1] round_frac
|
|
||||||
(
|
|
||||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
|
||||||
input [`FIXED_WIDTH:1] decimal,
|
|
||||||
|
|
||||||
// This describes the precision of the fraction, for example a value
|
|
||||||
// of 1 would modify the fractional so that instead of being a .16
|
|
||||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
|
||||||
input [`FIXED_WIDTH:1] precision
|
|
||||||
);
|
|
||||||
|
|
||||||
begin
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
|
||||||
`endif
|
|
||||||
// If the fractional precision bit is high then round up
|
|
||||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
|
||||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
|
||||||
end else begin
|
|
||||||
round_frac = decimal;
|
|
||||||
end
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("round_frac: %h", round_frac);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function calculates high_time, low_time, w_edge, and no_count
|
|
||||||
// of a non-fractional counter based on the divide and duty cycle
|
|
||||||
//
|
|
||||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
|
||||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
|
||||||
// ignore the overflow)
|
|
||||||
function [13:0] mmcm_pll_divider
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
|
||||||
|
|
||||||
// High/Low time is initially calculated with a wider integer to prevent a
|
|
||||||
// calculation error when it overflows to 64.
|
|
||||||
reg [6:0] high_time;
|
|
||||||
reg [6:0] low_time;
|
|
||||||
reg w_edge;
|
|
||||||
reg no_count;
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] temp;
|
|
||||||
|
|
||||||
begin
|
|
||||||
// Duty Cycle must be between 0 and 1,000
|
|
||||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
|
||||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
|
||||||
// Other values are dummies
|
|
||||||
if(divide == 7'h01) begin
|
|
||||||
high_time = 7'h01;
|
|
||||||
w_edge = 1'b0;
|
|
||||||
low_time = 7'h01;
|
|
||||||
no_count = 1'b1;
|
|
||||||
end else begin
|
|
||||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
|
||||||
|
|
||||||
// comes from above round_frac
|
|
||||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
|
||||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
|
||||||
// is set.
|
|
||||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
|
||||||
|
|
||||||
// If the high time comes out to 0, it needs to be set to at least 1
|
|
||||||
// and w_edge set to 0
|
|
||||||
if(high_time == 7'h00) begin
|
|
||||||
high_time = 7'h01;
|
|
||||||
w_edge = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
if(high_time == divide) begin
|
|
||||||
high_time = divide - 1;
|
|
||||||
w_edge = 1'b1;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Calculate low_time based on the divide setting and set no_count to
|
|
||||||
// 0 as it is only used when divide is 1.
|
|
||||||
low_time = divide - high_time;
|
|
||||||
no_count = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Set the return value.
|
|
||||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function calculates mx, delay_time, and phase_mux
|
|
||||||
// of a non-fractional counter based on the divide and phase
|
|
||||||
//
|
|
||||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
|
||||||
// is used.
|
|
||||||
function [10:0] mmcm_pll_phase
|
|
||||||
(
|
|
||||||
// divide must be an integer (use fractional if not)
|
|
||||||
// assumed that divide already checked to be valid
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
|
|
||||||
// Phase is given in degrees (-360,000 to 360,000)
|
|
||||||
input signed [31:0] phase
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
|
||||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
|
||||||
reg [1:0] mx;
|
|
||||||
reg [5:0] delay_time;
|
|
||||||
reg [2:0] phase_mux;
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] temp;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_pll_phase-divide:%d,phase:%d",
|
|
||||||
divide, phase);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
if ((phase < -360000) || (phase > 360000)) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
// If phase is less than 0, convert it to a positive phase shift
|
|
||||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
|
||||||
if(phase < 0) begin
|
|
||||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
|
||||||
end else begin
|
|
||||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Put phase in terms of decimal number of vco clock cycles
|
|
||||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
|
|
||||||
temp = round_frac(phase_in_cycles, 3);
|
|
||||||
|
|
||||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
|
||||||
mx = 2'b00;
|
|
||||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
|
||||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("temp: %h", temp);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// Setup the return value
|
|
||||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes the divide value and outputs the necessary lock values
|
|
||||||
function [39:0] mmcm_pll_lock_lookup
|
|
||||||
(
|
|
||||||
input [6:0] divide // Max divide is 64
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [2559:0] lookup;
|
|
||||||
|
|
||||||
begin
|
|
||||||
lookup = {
|
|
||||||
// This table is composed of:
|
|
||||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
|
||||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
|
||||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
|
||||||
40'b01000_01000_1111101000_1111101001_0000000001,
|
|
||||||
40'b01011_01011_1111101000_1111101001_0000000001,
|
|
||||||
40'b01110_01110_1111101000_1111101001_0000000001,
|
|
||||||
40'b10001_10001_1111101000_1111101001_0000000001,
|
|
||||||
40'b10011_10011_1111101000_1111101001_0000000001,
|
|
||||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
|
||||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
|
||||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001
|
|
||||||
};
|
|
||||||
|
|
||||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
|
||||||
mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes the divide value and the bandwidth setting of the PLL
|
|
||||||
// and outputs the digital filter settings necessary.
|
|
||||||
function [9:0] mmcm_pll_filter_lookup
|
|
||||||
(
|
|
||||||
input [6:0] divide, // Max divide is 64
|
|
||||||
input [8*9:0] BANDWIDTH
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [639:0] lookup_low;
|
|
||||||
reg [639:0] lookup_high;
|
|
||||||
|
|
||||||
reg [9:0] lookup_entry;
|
|
||||||
|
|
||||||
begin
|
|
||||||
lookup_low = {
|
|
||||||
// CP_RES_LFHF
|
|
||||||
10'b0010_1111_00,
|
|
||||||
10'b0010_1111_00,
|
|
||||||
10'b0010_0111_00,
|
|
||||||
10'b0010_1101_00,
|
|
||||||
10'b0010_0101_00,
|
|
||||||
10'b0010_0101_00,
|
|
||||||
10'b0010_1001_00,
|
|
||||||
10'b0010_1110_00,
|
|
||||||
10'b0010_1110_00,
|
|
||||||
10'b0010_0001_00,
|
|
||||||
10'b0010_0001_00,
|
|
||||||
10'b0010_0110_00,
|
|
||||||
10'b0010_0110_00,
|
|
||||||
10'b0010_0110_00,
|
|
||||||
10'b0010_0110_00,
|
|
||||||
10'b0010_1010_00,
|
|
||||||
10'b0010_1010_00,
|
|
||||||
10'b0010_1010_00,
|
|
||||||
10'b0010_1010_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_1100_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0010_0010_00,
|
|
||||||
10'b0011_1100_00,
|
|
||||||
10'b0011_1100_00,
|
|
||||||
10'b0011_1100_00,
|
|
||||||
10'b0011_1100_00,
|
|
||||||
10'b0011_1100_00,
|
|
||||||
10'b0011_1100_00,
|
|
||||||
10'b0011_1100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00
|
|
||||||
};
|
|
||||||
|
|
||||||
lookup_high = {
|
|
||||||
// CP_RES_LFHF
|
|
||||||
10'b0011_0111_00,
|
|
||||||
10'b0011_0111_00,
|
|
||||||
10'b0101_1111_00,
|
|
||||||
10'b0111_1111_00,
|
|
||||||
10'b0111_1011_00,
|
|
||||||
10'b1101_0111_00,
|
|
||||||
10'b1110_1011_00,
|
|
||||||
10'b1110_1101_00,
|
|
||||||
10'b1111_1101_00,
|
|
||||||
10'b1111_0111_00,
|
|
||||||
10'b1111_1011_00,
|
|
||||||
10'b1111_1101_00,
|
|
||||||
10'b1111_0011_00,
|
|
||||||
10'b1110_0101_00,
|
|
||||||
10'b1111_0101_00,
|
|
||||||
10'b1111_0101_00,
|
|
||||||
10'b1111_0101_00,
|
|
||||||
10'b1111_0101_00,
|
|
||||||
10'b0111_0110_00,
|
|
||||||
10'b0111_0110_00,
|
|
||||||
10'b0111_0110_00,
|
|
||||||
10'b0111_0110_00,
|
|
||||||
10'b0101_1100_00,
|
|
||||||
10'b0101_1100_00,
|
|
||||||
10'b0101_1100_00,
|
|
||||||
10'b1100_0001_00,
|
|
||||||
10'b1100_0001_00,
|
|
||||||
10'b1100_0001_00,
|
|
||||||
10'b1100_0001_00,
|
|
||||||
10'b1100_0001_00,
|
|
||||||
10'b1100_0001_00,
|
|
||||||
10'b1100_0001_00,
|
|
||||||
10'b1100_0001_00,
|
|
||||||
10'b0100_0010_00,
|
|
||||||
10'b0100_0010_00,
|
|
||||||
10'b0100_0010_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0011_0100_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0010_1000_00,
|
|
||||||
10'b0100_1100_00,
|
|
||||||
10'b0100_1100_00,
|
|
||||||
10'b0100_1100_00,
|
|
||||||
10'b0100_1100_00,
|
|
||||||
10'b0100_1100_00,
|
|
||||||
10'b0100_1100_00,
|
|
||||||
10'b0100_1100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00,
|
|
||||||
10'b0010_0100_00
|
|
||||||
};
|
|
||||||
|
|
||||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
|
||||||
if(BANDWIDTH == "LOW") begin
|
|
||||||
// Low Bandwidth
|
|
||||||
mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
|
|
||||||
end else begin
|
|
||||||
// High or optimized bandwidth
|
|
||||||
mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
|
|
||||||
end
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes in the divide, phase, and duty cycle
|
|
||||||
// setting to calculate the upper and lower counter registers.
|
|
||||||
function [37:0] mmcm_pll_count_calc
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input signed [31:0] phase,
|
|
||||||
input [31:0] duty_cycle // Multiplied by 100,000
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [13:0] div_calc;
|
|
||||||
reg [16:0] phase_calc;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
|
||||||
divide, phase, duty_cycle);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
|
||||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
|
||||||
// mx[10:9], pm[8:6], dt[5:0]
|
|
||||||
phase_calc = mmcm_pll_phase(divide, phase);
|
|
||||||
|
|
||||||
// Return value is the upper and lower address of counter
|
|
||||||
// Upper address is:
|
|
||||||
// RESERVED [31:26]
|
|
||||||
// MX [25:24]
|
|
||||||
// EDGE [23]
|
|
||||||
// NOCOUNT [22]
|
|
||||||
// DELAY_TIME [21:16]
|
|
||||||
// Lower Address is:
|
|
||||||
// PHASE_MUX [15:13]
|
|
||||||
// RESERVED [12]
|
|
||||||
// HIGH_TIME [11:6]
|
|
||||||
// LOW_TIME [5:0]
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
|
||||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
|
||||||
div_calc[13], div_calc[12],
|
|
||||||
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
mmcm_pll_count_calc =
|
|
||||||
{
|
|
||||||
// Upper Address
|
|
||||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
|
||||||
// Lower Address
|
|
||||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
|
||||||
};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
@@ -1,671 +0,0 @@
|
|||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
//
|
|
||||||
// Company: Xilinx
|
|
||||||
// Engineer: Jim Tatsukawa
|
|
||||||
// Date: 7/30/2014
|
|
||||||
// Design Name: MMCME2 DRP
|
|
||||||
// Module Name: mmcme2_drp_func.h
|
|
||||||
// Version: 1.04
|
|
||||||
// Target Devices: UltraScale Architecture || MMCM
|
|
||||||
// Tool versions: 2014.3
|
|
||||||
// Description: This header provides the functions necessary to
|
|
||||||
// calculate the DRP register values for the V6 MMCM.
|
|
||||||
//
|
|
||||||
// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
|
|
||||||
// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
|
|
||||||
//
|
|
||||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
|
||||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
|
||||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
|
||||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
|
||||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
|
||||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
|
||||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
|
||||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
|
||||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
|
||||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
|
||||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
|
||||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
|
||||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
|
||||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
|
||||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
|
||||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
// PURPOSE.
|
|
||||||
//
|
|
||||||
// (c) Copyright 2009-2010 Xilinx, Inc.
|
|
||||||
// All rights reserved.
|
|
||||||
//
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
|
|
||||||
// These are user functions that should not be modified. Changes to the defines
|
|
||||||
// or code within the functions may alter the accuracy of the calculations.
|
|
||||||
|
|
||||||
// Define debug to provide extra messages durring elaboration
|
|
||||||
//`define DEBUG 1
|
|
||||||
|
|
||||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
|
||||||
// point numbers. These should not be modified, they are for development
|
|
||||||
// only
|
|
||||||
`define FRAC_PRECISION 10
|
|
||||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
|
||||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
|
||||||
// greater than 32
|
|
||||||
`define FIXED_WIDTH 32
|
|
||||||
|
|
||||||
// This function takes a fixed point number and rounds it to the nearest
|
|
||||||
// fractional precision bit.
|
|
||||||
function [`FIXED_WIDTH:1] round_frac
|
|
||||||
(
|
|
||||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
|
||||||
input [`FIXED_WIDTH:1] decimal,
|
|
||||||
|
|
||||||
// This describes the precision of the fraction, for example a value
|
|
||||||
// of 1 would modify the fractional so that instead of being a .16
|
|
||||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
|
||||||
input [`FIXED_WIDTH:1] precision
|
|
||||||
);
|
|
||||||
|
|
||||||
begin
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
|
||||||
`endif
|
|
||||||
// If the fractional precision bit is high then round up
|
|
||||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
|
||||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
|
||||||
end else begin
|
|
||||||
round_frac = decimal;
|
|
||||||
end
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("round_frac: %h", round_frac);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function calculates high_time, low_time, w_edge, and no_count
|
|
||||||
// of a non-fractional counter based on the divide and duty cycle
|
|
||||||
//
|
|
||||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
|
||||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
|
||||||
// ignore the overflow)
|
|
||||||
function [13:0] mmcm_pll_divider
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
|
||||||
|
|
||||||
// High/Low time is initially calculated with a wider integer to prevent a
|
|
||||||
// calculation error when it overflows to 64.
|
|
||||||
reg [6:0] high_time;
|
|
||||||
reg [6:0] low_time;
|
|
||||||
reg w_edge;
|
|
||||||
reg no_count;
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] temp;
|
|
||||||
|
|
||||||
begin
|
|
||||||
// Duty Cycle must be between 0 and 1,000
|
|
||||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
|
||||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
|
||||||
// Other values are dummies
|
|
||||||
if(divide == 7'h01) begin
|
|
||||||
high_time = 7'h01;
|
|
||||||
w_edge = 1'b0;
|
|
||||||
low_time = 7'h01;
|
|
||||||
no_count = 1'b1;
|
|
||||||
end else begin
|
|
||||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
|
||||||
|
|
||||||
// comes from above round_frac
|
|
||||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
|
||||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
|
||||||
// is set.
|
|
||||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
|
||||||
|
|
||||||
// If the high time comes out to 0, it needs to be set to at least 1
|
|
||||||
// and w_edge set to 0
|
|
||||||
if(high_time == 7'h00) begin
|
|
||||||
high_time = 7'h01;
|
|
||||||
w_edge = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
if(high_time == divide) begin
|
|
||||||
high_time = divide - 1;
|
|
||||||
w_edge = 1'b1;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Calculate low_time based on the divide setting and set no_count to
|
|
||||||
// 0 as it is only used when divide is 1.
|
|
||||||
low_time = divide - high_time;
|
|
||||||
no_count = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Set the return value.
|
|
||||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function calculates mx, delay_time, and phase_mux
|
|
||||||
// of a non-fractional counter based on the divide and phase
|
|
||||||
//
|
|
||||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
|
||||||
// is used.
|
|
||||||
function [10:0] mmcm_pll_phase
|
|
||||||
(
|
|
||||||
// divide must be an integer (use fractional if not)
|
|
||||||
// assumed that divide already checked to be valid
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
|
|
||||||
// Phase is given in degrees (-360,000 to 360,000)
|
|
||||||
input signed [31:0] phase
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
|
||||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
|
||||||
reg [1:0] mx;
|
|
||||||
reg [5:0] delay_time;
|
|
||||||
reg [2:0] phase_mux;
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] temp;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_pll_phase-divide:%d,phase:%d",
|
|
||||||
divide, phase);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
if ((phase < -360000) || (phase > 360000)) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
// If phase is less than 0, convert it to a positive phase shift
|
|
||||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
|
||||||
if(phase < 0) begin
|
|
||||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
|
||||||
end else begin
|
|
||||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Put phase in terms of decimal number of vco clock cycles
|
|
||||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
|
|
||||||
temp = round_frac(phase_in_cycles, 3);
|
|
||||||
|
|
||||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
|
||||||
mx = 2'b00;
|
|
||||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
|
||||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("temp: %h", temp);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// Setup the return value
|
|
||||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes the divide value and outputs the necessary lock values
|
|
||||||
function [39:0] mmcm_pll_lock_lookup
|
|
||||||
(
|
|
||||||
input [6:0] divide // Max divide is 64
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [2559:0] lookup;
|
|
||||||
|
|
||||||
begin
|
|
||||||
lookup = {
|
|
||||||
// This table is composed of:
|
|
||||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
|
||||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
|
||||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
|
||||||
40'b01000_01000_1111101000_1111101001_0000000001,
|
|
||||||
40'b01011_01011_1111101000_1111101001_0000000001,
|
|
||||||
40'b01110_01110_1111101000_1111101001_0000000001,
|
|
||||||
40'b10001_10001_1111101000_1111101001_0000000001,
|
|
||||||
40'b10011_10011_1111101000_1111101001_0000000001,
|
|
||||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
|
||||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
|
||||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001
|
|
||||||
};
|
|
||||||
|
|
||||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
|
||||||
mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes the divide value and the bandwidth setting of the MMCM
|
|
||||||
// and outputs the digital filter settings necessary.
|
|
||||||
function [9:0] mmcm_pll_filter_lookup
|
|
||||||
(
|
|
||||||
input [6:0] divide, // Max divide is 64
|
|
||||||
input [8*9:0] BANDWIDTH
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [639:0] lookup_low;
|
|
||||||
reg [639:0] lookup_high;
|
|
||||||
|
|
||||||
reg [9:0] lookup_entry;
|
|
||||||
|
|
||||||
begin
|
|
||||||
lookup_low = {
|
|
||||||
// CP_RES_LFHF
|
|
||||||
10'b0010_1111_11,
|
|
||||||
10'b0010_1111_11,
|
|
||||||
10'b0010_1111_11,
|
|
||||||
10'b0010_1111_11,
|
|
||||||
10'b0010_1111_11,
|
|
||||||
10'b0010_1111_11,
|
|
||||||
10'b0010_0111_11,
|
|
||||||
10'b0010_0111_11,
|
|
||||||
10'b0010_0111_11,
|
|
||||||
10'b0010_1101_11,
|
|
||||||
10'b0010_1101_11,
|
|
||||||
10'b0010_1101_11,
|
|
||||||
10'b0010_0011_11,
|
|
||||||
10'b0010_0101_11,
|
|
||||||
10'b0010_0101_11,
|
|
||||||
10'b0010_0101_11,
|
|
||||||
10'b0010_1001_11,
|
|
||||||
10'b0010_1001_11,
|
|
||||||
10'b0010_1110_11,
|
|
||||||
10'b0010_1110_11,
|
|
||||||
10'b0010_1110_11,
|
|
||||||
10'b0010_1110_11,
|
|
||||||
10'b0010_1110_11,
|
|
||||||
10'b0010_1110_11,
|
|
||||||
10'b0010_0001_11,
|
|
||||||
10'b0010_0001_11,
|
|
||||||
10'b0010_0001_11,
|
|
||||||
10'b0010_0001_11,
|
|
||||||
10'b0010_0001_11,
|
|
||||||
10'b0010_0110_11,
|
|
||||||
10'b0010_0110_11,
|
|
||||||
10'b0010_0110_11,
|
|
||||||
10'b0010_0110_11,
|
|
||||||
10'b0010_0110_11,
|
|
||||||
10'b0010_0110_11,
|
|
||||||
10'b0010_0110_11,
|
|
||||||
10'b0010_0110_11,
|
|
||||||
10'b0010_0110_11,
|
|
||||||
10'b0010_0110_11,
|
|
||||||
10'b0010_1010_11,
|
|
||||||
10'b0010_1010_11,
|
|
||||||
10'b0010_1010_11,
|
|
||||||
10'b0010_1010_11,
|
|
||||||
10'b0010_1010_11,
|
|
||||||
10'b0010_1010_11,
|
|
||||||
10'b0010_1010_11,
|
|
||||||
10'b0010_1010_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11,
|
|
||||||
10'b0010_1100_11
|
|
||||||
};
|
|
||||||
|
|
||||||
lookup_high = {
|
|
||||||
// CP_RES_LFHF
|
|
||||||
10'b0010_1111_11,
|
|
||||||
10'b0010_1111_11,
|
|
||||||
10'b0010_1011_11,
|
|
||||||
10'b0011_1111_11,
|
|
||||||
10'b0100_1111_11,
|
|
||||||
10'b0100_1111_11,
|
|
||||||
10'b0101_1111_11,
|
|
||||||
10'b0110_1111_11,
|
|
||||||
10'b0111_1111_11,
|
|
||||||
10'b0111_1111_11,
|
|
||||||
10'b1100_1111_11,
|
|
||||||
10'b1101_1111_11,
|
|
||||||
10'b1110_1111_11,
|
|
||||||
10'b1111_1111_11,
|
|
||||||
10'b1111_1111_11,
|
|
||||||
10'b1110_0111_11,
|
|
||||||
10'b1110_1011_11,
|
|
||||||
10'b1111_0111_11,
|
|
||||||
10'b1111_1011_11,
|
|
||||||
10'b1111_1011_11,
|
|
||||||
10'b1110_1101_11,
|
|
||||||
10'b1111_1101_11,
|
|
||||||
10'b1111_1101_11,
|
|
||||||
10'b1111_0011_11,
|
|
||||||
10'b1111_0011_11,
|
|
||||||
10'b1111_0011_11,
|
|
||||||
10'b1110_0101_11,
|
|
||||||
10'b1110_0101_11,
|
|
||||||
10'b1110_0101_11,
|
|
||||||
10'b1111_0101_11,
|
|
||||||
10'b1111_0101_11,
|
|
||||||
10'b1111_0101_11,
|
|
||||||
10'b1111_1001_11,
|
|
||||||
10'b1111_1001_11,
|
|
||||||
10'b1111_1001_11,
|
|
||||||
10'b1111_1001_11,
|
|
||||||
10'b1111_1001_11,
|
|
||||||
10'b1110_1110_11,
|
|
||||||
10'b1110_1110_11,
|
|
||||||
10'b1110_1110_11,
|
|
||||||
10'b1110_1110_11,
|
|
||||||
10'b1111_1110_11,
|
|
||||||
10'b1111_1110_11,
|
|
||||||
10'b1111_1110_11,
|
|
||||||
10'b1111_1110_11,
|
|
||||||
10'b1111_1110_11,
|
|
||||||
10'b1111_1110_11,
|
|
||||||
10'b1111_1110_11,
|
|
||||||
10'b1110_0001_11,
|
|
||||||
10'b1110_0001_11,
|
|
||||||
10'b1110_0001_11,
|
|
||||||
10'b1110_0001_11,
|
|
||||||
10'b1110_0001_11,
|
|
||||||
10'b1100_0110_11,
|
|
||||||
10'b1100_0110_11,
|
|
||||||
10'b1100_0110_11,
|
|
||||||
10'b1100_0110_11,
|
|
||||||
10'b1100_0110_11,
|
|
||||||
10'b1100_0110_11,
|
|
||||||
10'b1100_0110_11,
|
|
||||||
10'b1100_1010_11,
|
|
||||||
10'b1100_1010_11,
|
|
||||||
10'b1100_1010_11,
|
|
||||||
10'b1100_1010_11
|
|
||||||
};
|
|
||||||
|
|
||||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
|
||||||
if(BANDWIDTH == "LOW") begin
|
|
||||||
// Low Bandwidth
|
|
||||||
mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
|
|
||||||
end else begin
|
|
||||||
// High or optimized bandwidth
|
|
||||||
mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
|
|
||||||
end
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes in the divide, phase, and duty cycle
|
|
||||||
// setting to calculate the upper and lower counter registers.
|
|
||||||
function [37:0] mmcm_pll_count_calc
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input signed [31:0] phase,
|
|
||||||
input [31:0] duty_cycle // Multiplied by 100,000
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [13:0] div_calc;
|
|
||||||
reg [16:0] phase_calc;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
|
||||||
divide, phase, duty_cycle);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
|
||||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
|
||||||
// mx[10:9], pm[8:6], dt[5:0]
|
|
||||||
phase_calc = mmcm_pll_phase(divide, phase);
|
|
||||||
|
|
||||||
// Return value is the upper and lower address of counter
|
|
||||||
// Upper address is:
|
|
||||||
// RESERVED [31:26]
|
|
||||||
// MX [25:24]
|
|
||||||
// EDGE [23]
|
|
||||||
// NOCOUNT [22]
|
|
||||||
// DELAY_TIME [21:16]
|
|
||||||
// Lower Address is:
|
|
||||||
// PHASE_MUX [15:13]
|
|
||||||
// RESERVED [12]
|
|
||||||
// HIGH_TIME [11:6]
|
|
||||||
// LOW_TIME [5:0]
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
|
||||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
|
||||||
div_calc[13], div_calc[12],
|
|
||||||
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
mmcm_pll_count_calc =
|
|
||||||
{
|
|
||||||
// Upper Address
|
|
||||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
|
||||||
// Lower Address
|
|
||||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
|
||||||
};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
|
|
||||||
// This function takes in the divide, phase, and duty cycle
|
|
||||||
// setting to calculate the upper and lower counter registers.
|
|
||||||
// for fractional multiply/divide functions.
|
|
||||||
//
|
|
||||||
//
|
|
||||||
function [37:0] mmcm_frac_count_calc
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input signed [31:0] phase,
|
|
||||||
input [31:0] duty_cycle, // Multiplied by 1,000
|
|
||||||
input [9:0] frac // Multiplied by 1000
|
|
||||||
);
|
|
||||||
|
|
||||||
//Required for fractional divide calculations
|
|
||||||
reg [7:0] lt_frac;
|
|
||||||
reg [7:0] ht_frac;
|
|
||||||
|
|
||||||
reg /*[7:0]*/ wf_fall_frac;
|
|
||||||
reg /*[7:0]*/ wf_rise_frac;
|
|
||||||
|
|
||||||
reg [31:0] a;
|
|
||||||
reg [7:0] pm_rise_frac_filtered ;
|
|
||||||
reg [7:0] pm_fall_frac_filtered ;
|
|
||||||
reg [7:0] clkout0_divide_int;
|
|
||||||
reg [2:0] clkout0_divide_frac;
|
|
||||||
reg [7:0] even_part_high;
|
|
||||||
reg [7:0] even_part_low;
|
|
||||||
|
|
||||||
reg [7:0] odd;
|
|
||||||
reg [7:0] odd_and_frac;
|
|
||||||
|
|
||||||
reg [7:0] pm_fall;
|
|
||||||
reg [7:0] pm_rise;
|
|
||||||
reg [7:0] dt;
|
|
||||||
reg [7:0] dt_int;
|
|
||||||
reg [63:0] dt_calc;
|
|
||||||
|
|
||||||
reg [7:0] pm_rise_frac;
|
|
||||||
reg [7:0] pm_fall_frac;
|
|
||||||
|
|
||||||
reg [31:0] a_per_in_octets;
|
|
||||||
reg [31:0] a_phase_in_cycles;
|
|
||||||
|
|
||||||
parameter precision = 0.125;
|
|
||||||
|
|
||||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
|
||||||
reg [31: 0] phase_pos;
|
|
||||||
reg [31: 0] phase_vco;
|
|
||||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
|
||||||
reg [13:0] div_calc;
|
|
||||||
reg [16:0] phase_calc;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
|
||||||
divide, phase, duty_cycle);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
//convert phase to fixed
|
|
||||||
if ((phase < -360000) || (phase > 360000)) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
// Return value is
|
|
||||||
// Transfer data
|
|
||||||
// RESERVED [37:36]
|
|
||||||
// FRAC_TIME [35:33]
|
|
||||||
// FRAC_WF_FALL [32]
|
|
||||||
// Upper address is:
|
|
||||||
// RESERVED [31:26]
|
|
||||||
// MX [25:24]
|
|
||||||
// EDGE [23]
|
|
||||||
// NOCOUNT [22]
|
|
||||||
// DELAY_TIME [21:16]
|
|
||||||
// Lower Address is:
|
|
||||||
// PHASE_MUX [15:13]
|
|
||||||
// RESERVED [12]
|
|
||||||
// HIGH_TIME [11:6]
|
|
||||||
// LOW_TIME [5:0]
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
clkout0_divide_frac = frac / 125;
|
|
||||||
clkout0_divide_int = divide;
|
|
||||||
|
|
||||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
|
||||||
even_part_low = even_part_high;
|
|
||||||
|
|
||||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
|
||||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
|
||||||
|
|
||||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
|
||||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
|
||||||
|
|
||||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
|
||||||
pm_rise = 0; //0
|
|
||||||
|
|
||||||
wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
|
|
||||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//Calculate phase in fractional cycles
|
|
||||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
|
||||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
|
||||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
|
||||||
|
|
||||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
|
||||||
dt = dt_calc[7:0];
|
|
||||||
|
|
||||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
|
||||||
|
|
||||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
|
||||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
|
||||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
|
||||||
|
|
||||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
|
||||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
|
||||||
|
|
||||||
mmcm_frac_count_calc[37:0] =
|
|
||||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
|
||||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
|
||||||
pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
|
||||||
} ;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
@@ -1,530 +0,0 @@
|
|||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
//
|
|
||||||
// Company: Xilinx
|
|
||||||
// Engineer: Jim Tatsukawa
|
|
||||||
// Date: 6/15/2015
|
|
||||||
// Design Name: PLLE3 DRP
|
|
||||||
// Module Name: plle3_drp_func.h
|
|
||||||
// Version: 1.10
|
|
||||||
// Target Devices: UltraScale Architecture
|
|
||||||
// Tool versions: 2015.1
|
|
||||||
// Description: This header provides the functions necessary to
|
|
||||||
// calculate the DRP register values for the V6 PLL.
|
|
||||||
//
|
|
||||||
// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
|
|
||||||
// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
|
|
||||||
// PM_Rise bits have been removed for PLLE3
|
|
||||||
//
|
|
||||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
|
||||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
|
||||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
|
||||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
|
||||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
|
||||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
|
||||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
|
||||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
|
||||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
|
||||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
|
||||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
|
||||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
|
||||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
|
||||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
|
||||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
|
||||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
// PURPOSE.
|
|
||||||
//
|
|
||||||
// (c) Copyright 2009-2010 Xilinx, Inc.
|
|
||||||
// All rights reserved.
|
|
||||||
//
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
|
|
||||||
// These are user functions that should not be modified. Changes to the defines
|
|
||||||
// or code within the functions may alter the accuracy of the calculations.
|
|
||||||
|
|
||||||
// Define debug to provide extra messages durring elaboration
|
|
||||||
//`define DEBUG 1
|
|
||||||
|
|
||||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
|
||||||
// point numbers. These should not be modified, they are for development
|
|
||||||
// only
|
|
||||||
`define FRAC_PRECISION 10
|
|
||||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
|
||||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
|
||||||
// greater than 32
|
|
||||||
`define FIXED_WIDTH 32
|
|
||||||
|
|
||||||
// This function takes a fixed point number and rounds it to the nearest
|
|
||||||
// fractional precision bit.
|
|
||||||
function [`FIXED_WIDTH:1] round_frac
|
|
||||||
(
|
|
||||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
|
||||||
input [`FIXED_WIDTH:1] decimal,
|
|
||||||
|
|
||||||
// This describes the precision of the fraction, for example a value
|
|
||||||
// of 1 would modify the fractional so that instead of being a .16
|
|
||||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
|
||||||
input [`FIXED_WIDTH:1] precision
|
|
||||||
);
|
|
||||||
|
|
||||||
begin
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
|
||||||
`endif
|
|
||||||
// If the fractional precision bit is high then round up
|
|
||||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
|
||||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
|
||||||
end else begin
|
|
||||||
round_frac = decimal;
|
|
||||||
end
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("round_frac: %h", round_frac);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function calculates high_time, low_time, w_edge, and no_count
|
|
||||||
// of a non-fractional counter based on the divide and duty cycle
|
|
||||||
//
|
|
||||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
|
||||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
|
||||||
// ignore the overflow)
|
|
||||||
function [13:0] mmcm_pll_divider
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
|
||||||
|
|
||||||
// High/Low time is initially calculated with a wider integer to prevent a
|
|
||||||
// calculation error when it overflows to 64.
|
|
||||||
reg [6:0] high_time;
|
|
||||||
reg [6:0] low_time;
|
|
||||||
reg w_edge;
|
|
||||||
reg no_count;
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] temp;
|
|
||||||
|
|
||||||
begin
|
|
||||||
// Duty Cycle must be between 0 and 1,000
|
|
||||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
|
||||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
|
||||||
// Other values are dummies
|
|
||||||
if(divide == 7'h01) begin
|
|
||||||
high_time = 7'h01;
|
|
||||||
w_edge = 1'b0;
|
|
||||||
low_time = 7'h01;
|
|
||||||
no_count = 1'b1;
|
|
||||||
end else begin
|
|
||||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
|
||||||
|
|
||||||
// comes from above round_frac
|
|
||||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
|
||||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
|
||||||
// is set.
|
|
||||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
|
||||||
|
|
||||||
// If the high time comes out to 0, it needs to be set to at least 1
|
|
||||||
// and w_edge set to 0
|
|
||||||
if(high_time == 7'h00) begin
|
|
||||||
high_time = 7'h01;
|
|
||||||
w_edge = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
if(high_time == divide) begin
|
|
||||||
high_time = divide - 1;
|
|
||||||
w_edge = 1'b1;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Calculate low_time based on the divide setting and set no_count to
|
|
||||||
// 0 as it is only used when divide is 1.
|
|
||||||
low_time = divide - high_time;
|
|
||||||
no_count = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Set the return value.
|
|
||||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function calculates mx, delay_time, and phase_mux
|
|
||||||
// of a non-fractional counter based on the divide and phase
|
|
||||||
//
|
|
||||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
|
||||||
// is used.
|
|
||||||
function [10:0] mmcm_pll_phase
|
|
||||||
(
|
|
||||||
// divide must be an integer (use fractional if not)
|
|
||||||
// assumed that divide already checked to be valid
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
|
|
||||||
// Phase is given in degrees (-360,000 to 360,000)
|
|
||||||
input signed [31:0] phase
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
|
||||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
|
||||||
reg [1:0] mx;
|
|
||||||
reg [5:0] delay_time;
|
|
||||||
reg [2:0] phase_mux;
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] temp;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_pll_phase-divide:%d,phase:%d",
|
|
||||||
divide, phase);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
if ((phase < -360000) || (phase > 360000)) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
// If phase is less than 0, convert it to a positive phase shift
|
|
||||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
|
||||||
if(phase < 0) begin
|
|
||||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
|
||||||
end else begin
|
|
||||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Put phase in terms of decimal number of vco clock cycles
|
|
||||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
|
|
||||||
temp = round_frac(phase_in_cycles, 3);
|
|
||||||
|
|
||||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
|
||||||
mx = 2'b00;
|
|
||||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
|
||||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("temp: %h", temp);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// Setup the return value
|
|
||||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes the divide value and outputs the necessary lock values
|
|
||||||
function [39:0] mmcm_pll_lock_lookup
|
|
||||||
(
|
|
||||||
input [6:0] divide // Max divide is 64
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [759:0] lookup;
|
|
||||||
|
|
||||||
begin
|
|
||||||
lookup = {
|
|
||||||
// This table is composed of:
|
|
||||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
|
||||||
40'b00110_00110_1111101000_1111101001_0000000001, //1
|
|
||||||
40'b00110_00110_1111101000_1111101001_0000000001, //2
|
|
||||||
40'b01000_01000_1111101000_1111101001_0000000001, //3
|
|
||||||
40'b01011_01011_1111101000_1111101001_0000000001, //4
|
|
||||||
40'b01110_01110_1111101000_1111101001_0000000001, //5
|
|
||||||
40'b10001_10001_1111101000_1111101001_0000000001, //6
|
|
||||||
40'b10011_10011_1111101000_1111101001_0000000001, //7
|
|
||||||
40'b10110_10110_1111101000_1111101001_0000000001, //8
|
|
||||||
40'b11001_11001_1111101000_1111101001_0000000001, //9
|
|
||||||
40'b11100_11100_1111101000_1111101001_0000000001, //10
|
|
||||||
40'b11111_11111_1110000100_1111101001_0000000001, //11
|
|
||||||
40'b11111_11111_1100111001_1111101001_0000000001, //12
|
|
||||||
40'b11111_11111_1011101110_1111101001_0000000001, //13
|
|
||||||
40'b11111_11111_1010111100_1111101001_0000000001, //14
|
|
||||||
40'b11111_11111_1010001010_1111101001_0000000001, //15
|
|
||||||
40'b11111_11111_1001110001_1111101001_0000000001, //16
|
|
||||||
40'b11111_11111_1000111111_1111101001_0000000001, //17
|
|
||||||
40'b11111_11111_1000100110_1111101001_0000000001, //18
|
|
||||||
40'b11111_11111_1000001101_1111101001_0000000001 //19
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
|
||||||
mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes the divide value and the bandwidth setting of the PLL
|
|
||||||
// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
|
|
||||||
function [9:0] mmcm_pll_filter_lookup
|
|
||||||
(
|
|
||||||
input [6:0] divide // Max divide is 19
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [639:0] lookup;
|
|
||||||
reg [9:0] lookup_entry;
|
|
||||||
|
|
||||||
begin
|
|
||||||
|
|
||||||
lookup = {
|
|
||||||
// CP_RES_LFHF
|
|
||||||
10'b0010_1111_01, //1
|
|
||||||
10'b0010_0011_11, //2
|
|
||||||
10'b0011_0011_11, //3
|
|
||||||
10'b0010_0001_11, //4
|
|
||||||
10'b0010_0110_11, //5
|
|
||||||
10'b0010_1010_11, //6
|
|
||||||
10'b0010_1010_11, //7
|
|
||||||
10'b0011_0110_11, //8
|
|
||||||
10'b0010_1100_11, //9
|
|
||||||
10'b0010_1100_11, //10
|
|
||||||
10'b0010_1100_11, //11
|
|
||||||
10'b0010_0010_11, //12
|
|
||||||
10'b0011_1100_11, //13
|
|
||||||
10'b0011_1100_11, //14
|
|
||||||
10'b0011_1100_11, //15
|
|
||||||
10'b0011_1100_11, //16
|
|
||||||
10'b0011_0010_11, //17
|
|
||||||
10'b0011_0010_11, //18
|
|
||||||
10'b0011_0010_11 //19
|
|
||||||
};
|
|
||||||
|
|
||||||
mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function set the CLKOUTPHY divide settings to match
|
|
||||||
// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
|
|
||||||
// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
|
|
||||||
// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
|
|
||||||
function [9:0] mmcm_pll_clkoutphy_calc
|
|
||||||
(
|
|
||||||
input [8*9:0] CLKOUTPHY_MODE
|
|
||||||
);
|
|
||||||
|
|
||||||
if(CLKOUTPHY_MODE == "VCO_X2") begin
|
|
||||||
mmcm_pll_clkoutphy_calc= 2'b00;
|
|
||||||
end else if(CLKOUTPHY_MODE == "VCO") begin
|
|
||||||
mmcm_pll_clkoutphy_calc= 2'b01;
|
|
||||||
end else if(CLKOUTPHY_MODE == "CLKIN") begin
|
|
||||||
mmcm_pll_clkoutphy_calc= 2'b11;
|
|
||||||
end else begin // Assume "VCO_HALF"
|
|
||||||
mmcm_pll_clkoutphy_calc= 2'b10;
|
|
||||||
end
|
|
||||||
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
|
|
||||||
// This function takes in the divide, phase, and duty cycle
|
|
||||||
// setting to calculate the upper and lower counter registers.
|
|
||||||
function [37:0] mmcm_pll_count_calc
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input signed [31:0] phase,
|
|
||||||
input [31:0] duty_cycle // Multiplied by 100,000
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [13:0] div_calc;
|
|
||||||
reg [16:0] phase_calc;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
|
||||||
divide, phase, duty_cycle);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
|
||||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
|
||||||
// mx[10:9], pm[8:6], dt[5:0]
|
|
||||||
phase_calc = mmcm_pll_phase(divide, phase);
|
|
||||||
|
|
||||||
// Return value is the upper and lower address of counter
|
|
||||||
// Upper address is:
|
|
||||||
// RESERVED [31:26]
|
|
||||||
// MX [25:24]
|
|
||||||
// EDGE [23]
|
|
||||||
// NOCOUNT [22]
|
|
||||||
// DELAY_TIME [21:16]
|
|
||||||
// Lower Address is:
|
|
||||||
// PHASE_MUX [15:13]
|
|
||||||
// RESERVED [12]
|
|
||||||
// HIGH_TIME [11:6]
|
|
||||||
// LOW_TIME [5:0]
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
|
||||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
|
||||||
div_calc[13], div_calc[12],
|
|
||||||
phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
|
|
||||||
`endif
|
|
||||||
|
|
||||||
mmcm_pll_count_calc =
|
|
||||||
{
|
|
||||||
// Upper Address
|
|
||||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
|
||||||
// Lower Address
|
|
||||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
|
||||||
};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
|
|
||||||
// This function takes in the divide, phase, and duty cycle
|
|
||||||
// setting to calculate the upper and lower counter registers.
|
|
||||||
// for fractional multiply/divide functions.
|
|
||||||
//
|
|
||||||
//
|
|
||||||
function [37:0] mmcm_pll_frac_count_calc
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input signed [31:0] phase,
|
|
||||||
input [31:0] duty_cycle, // Multiplied by 1,000
|
|
||||||
input [9:0] frac // Multiplied by 1000
|
|
||||||
);
|
|
||||||
|
|
||||||
//Required for fractional divide calculations
|
|
||||||
reg [7:0] lt_frac;
|
|
||||||
reg [7:0] ht_frac;
|
|
||||||
|
|
||||||
reg /*[7:0]*/ wf_fall_frac;
|
|
||||||
reg /*[7:0]*/ wf_rise_frac;
|
|
||||||
|
|
||||||
reg [31:0] a;
|
|
||||||
reg [7:0] pm_rise_frac_filtered ;
|
|
||||||
reg [7:0] pm_fall_frac_filtered ;
|
|
||||||
reg [7:0] clkout0_divide_int;
|
|
||||||
reg [2:0] clkout0_divide_frac;
|
|
||||||
reg [7:0] even_part_high;
|
|
||||||
reg [7:0] even_part_low;
|
|
||||||
|
|
||||||
reg [7:0] odd;
|
|
||||||
reg [7:0] odd_and_frac;
|
|
||||||
|
|
||||||
reg [7:0] pm_fall;
|
|
||||||
reg [7:0] pm_rise;
|
|
||||||
reg [7:0] dt;
|
|
||||||
reg [7:0] dt_int;
|
|
||||||
reg [63:0] dt_calc;
|
|
||||||
|
|
||||||
reg [7:0] pm_rise_frac;
|
|
||||||
reg [7:0] pm_fall_frac;
|
|
||||||
|
|
||||||
reg [31:0] a_per_in_octets;
|
|
||||||
reg [31:0] a_phase_in_cycles;
|
|
||||||
|
|
||||||
parameter precision = 0.125;
|
|
||||||
|
|
||||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
|
||||||
reg [31: 0] phase_pos;
|
|
||||||
reg [31: 0] phase_vco;
|
|
||||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
|
||||||
reg [13:0] div_calc;
|
|
||||||
reg [16:0] phase_calc;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
|
||||||
divide, phase, duty_cycle);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
//convert phase to fixed
|
|
||||||
if ((phase < -360000) || (phase > 360000)) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
// Return value is
|
|
||||||
// Transfer data
|
|
||||||
// RESERVED [37:36]
|
|
||||||
// FRAC_TIME [35:33]
|
|
||||||
// FRAC_WF_FALL [32]
|
|
||||||
// Upper address is:
|
|
||||||
// RESERVED [31:26]
|
|
||||||
// MX [25:24]
|
|
||||||
// EDGE [23]
|
|
||||||
// NOCOUNT [22]
|
|
||||||
// DELAY_TIME [21:16]
|
|
||||||
// Lower Address is:
|
|
||||||
// PHASE_MUX [15:13]
|
|
||||||
// RESERVED [12]
|
|
||||||
// HIGH_TIME [11:6]
|
|
||||||
// LOW_TIME [5:0]
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
clkout0_divide_frac = frac / 125;
|
|
||||||
clkout0_divide_int = divide;
|
|
||||||
|
|
||||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
|
||||||
even_part_low = even_part_high;
|
|
||||||
|
|
||||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
|
||||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
|
||||||
|
|
||||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
|
||||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
|
||||||
|
|
||||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
|
||||||
pm_rise = 0; //0
|
|
||||||
|
|
||||||
wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
|
|
||||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//Calculate phase in fractional cycles
|
|
||||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
|
||||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
|
||||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
|
||||||
|
|
||||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
|
||||||
dt = dt_calc[7:0];
|
|
||||||
|
|
||||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
|
||||||
|
|
||||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
|
||||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
|
||||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
|
||||||
|
|
||||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
|
||||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
|
||||||
|
|
||||||
mmcm_pll_frac_count_calc[37:0] =
|
|
||||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
|
||||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
|
||||||
3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
|
|
||||||
// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
|
||||||
} ;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
|
|
||||||
-861
@@ -1,861 +0,0 @@
|
|||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
//
|
|
||||||
// Company: Xilinx
|
|
||||||
// Engineer: Jim Tatsukawa. Updated by Ralf Krueger
|
|
||||||
// Date: 7/30/2014
|
|
||||||
// Design Name: MMCME4 DRP
|
|
||||||
// Module Name: mmcme4_drp_func.h
|
|
||||||
// Version: 1.31
|
|
||||||
// Target Devices: UltraScale Plus Architecture
|
|
||||||
// Tool versions: 2017.1
|
|
||||||
// Description: This header provides the functions necessary to
|
|
||||||
// calculate the DRP register values for UltraScal+ MMCM.
|
|
||||||
//
|
|
||||||
// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
|
|
||||||
// 4/13 - Fractional divide function in mmcm_frac_count_calc function
|
|
||||||
// 2/28/17 - Updated for Ultrascale Plus
|
|
||||||
//
|
|
||||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
|
||||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
|
||||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
|
||||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
|
||||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
|
||||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
|
||||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
|
||||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
|
||||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
|
||||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
|
||||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
|
||||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
|
||||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
|
||||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
|
||||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
|
||||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
// PURPOSE.
|
|
||||||
//
|
|
||||||
// (c) Copyright 2009-2017 Xilinx, Inc.
|
|
||||||
// All rights reserved.
|
|
||||||
//
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
|
|
||||||
// These are user functions that should not be modified. Changes to the defines
|
|
||||||
// or code within the functions may alter the accuracy of the calculations.
|
|
||||||
|
|
||||||
// Define debug to provide extra messages during elaboration
|
|
||||||
//`define DEBUG 1
|
|
||||||
|
|
||||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
|
||||||
// point numbers. These should not be modified, they are for development only
|
|
||||||
`define FRAC_PRECISION 10
|
|
||||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
|
||||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
|
||||||
// greater than 32
|
|
||||||
`define FIXED_WIDTH 32
|
|
||||||
|
|
||||||
// This function takes a fixed point number and rounds it to the nearest
|
|
||||||
// fractional precision bit.
|
|
||||||
function [`FIXED_WIDTH:1] round_frac
|
|
||||||
(
|
|
||||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
|
||||||
input [`FIXED_WIDTH:1] decimal,
|
|
||||||
|
|
||||||
// This describes the precision of the fraction, for example a value
|
|
||||||
// of 1 would modify the fractional so that instead of being a .16
|
|
||||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
|
||||||
input [`FIXED_WIDTH:1] precision
|
|
||||||
);
|
|
||||||
|
|
||||||
begin
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
|
||||||
`endif
|
|
||||||
// If the fractional precision bit is high then round up
|
|
||||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
|
||||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
|
||||||
end else begin
|
|
||||||
round_frac = decimal;
|
|
||||||
end
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("round_frac: %h", round_frac);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function calculates high_time, low_time, w_edge, and no_count
|
|
||||||
// of a non-fractional counter based on the divide and duty cycle
|
|
||||||
//
|
|
||||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
|
||||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
|
||||||
// ignore the overflow)
|
|
||||||
function [13:0] mmcm_pll_divider
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
|
||||||
|
|
||||||
// High/Low time is initially calculated with a wider integer to prevent a
|
|
||||||
// calculation error when it overflows to 64.
|
|
||||||
reg [6:0] high_time;
|
|
||||||
reg [6:0] low_time;
|
|
||||||
reg w_edge;
|
|
||||||
reg no_count;
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] temp;
|
|
||||||
|
|
||||||
begin
|
|
||||||
// Duty Cycle must be between 0 and 1,000
|
|
||||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
|
||||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
|
||||||
// Other values are dummies
|
|
||||||
if(divide == 7'h01) begin
|
|
||||||
high_time = 7'h01;
|
|
||||||
w_edge = 1'b0;
|
|
||||||
low_time = 7'h01;
|
|
||||||
no_count = 1'b1;
|
|
||||||
end else begin
|
|
||||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
|
||||||
|
|
||||||
// comes from above round_frac
|
|
||||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
|
||||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
|
||||||
// is set.
|
|
||||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
|
||||||
|
|
||||||
// If the high time comes out to 0, it needs to be set to at least 1
|
|
||||||
// and w_edge set to 0
|
|
||||||
if(high_time == 7'h00) begin
|
|
||||||
high_time = 7'h01;
|
|
||||||
w_edge = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
if(high_time == divide) begin
|
|
||||||
high_time = divide - 1;
|
|
||||||
w_edge = 1'b1;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Calculate low_time based on the divide setting and set no_count to
|
|
||||||
// 0 as it is only used when divide is 1.
|
|
||||||
low_time = divide - high_time;
|
|
||||||
no_count = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Set the return value.
|
|
||||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function calculates mx, delay_time, and phase_mux
|
|
||||||
// of a non-fractional counter based on the divide and phase
|
|
||||||
//
|
|
||||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
|
||||||
// is used.
|
|
||||||
function [10:0] mmcm_pll_phase
|
|
||||||
(
|
|
||||||
// divide must be an integer (use fractional if not)
|
|
||||||
// assumed that divide already checked to be valid
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
|
|
||||||
// Phase is given in degrees (-360,000 to 360,000)
|
|
||||||
input signed [31:0] phase
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
|
||||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
|
||||||
reg [1:0] mx;
|
|
||||||
reg [5:0] delay_time;
|
|
||||||
reg [2:0] phase_mux;
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] temp;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_phase-divide:%d,phase:%d", divide, phase);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
if ((phase < -360000) || (phase > 360000)) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
// If phase is less than 0, convert it to a positive phase shift
|
|
||||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
|
||||||
if(phase < 0) begin
|
|
||||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
|
||||||
end else begin
|
|
||||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Put phase in terms of decimal number of vco clock cycles
|
|
||||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
temp = round_frac(phase_in_cycles, 3);
|
|
||||||
|
|
||||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
|
||||||
mx = 2'b00;
|
|
||||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
|
||||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("temp: %h", temp);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// Setup the return value
|
|
||||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes the divide value and outputs the necessary lock values
|
|
||||||
function [39:0] mmcm_pll_lock_lookup
|
|
||||||
(
|
|
||||||
input [7:0] divide // Max M divide is 128 in UltrascalePlus
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [5119:0] lookup;
|
|
||||||
|
|
||||||
begin
|
|
||||||
lookup = {
|
|
||||||
// This table is composed of:
|
|
||||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
|
||||||
40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed)
|
|
||||||
40'b00110_00110_1111101000_1111101001_0000000001, // M=2
|
|
||||||
40'b01000_01000_1111101000_1111101001_0000000001, // M=3
|
|
||||||
40'b01011_01011_1111101000_1111101001_0000000001, // M=4
|
|
||||||
40'b01110_01110_1111101000_1111101001_0000000001, // M=5
|
|
||||||
40'b10001_10001_1111101000_1111101001_0000000001, // M=6
|
|
||||||
40'b10011_10011_1111101000_1111101001_0000000001, // M=7
|
|
||||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
|
||||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
|
||||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001, // M=127
|
|
||||||
40'b11111_11111_0011111010_1111101001_0000000001 // M=128
|
|
||||||
};
|
|
||||||
|
|
||||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
|
||||||
mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes the divide value and the bandwidth setting of the MMCM
|
|
||||||
// and outputs the digital filter settings necessary.
|
|
||||||
function [9:0] mmcm_pll_filter_lookup
|
|
||||||
(
|
|
||||||
input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus
|
|
||||||
input [8*9:0] BANDWIDTH
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [1279:0] lookup_low;
|
|
||||||
reg [1279:0] lookup_high;
|
|
||||||
|
|
||||||
reg [9:0] lookup_entry;
|
|
||||||
|
|
||||||
begin
|
|
||||||
lookup_low = {
|
|
||||||
// CP_RES_LFHF
|
|
||||||
10'b0011_1111_11, // M=1 - not legal
|
|
||||||
10'b0011_1111_11, // M=2
|
|
||||||
10'b0011_1101_11, // M=3
|
|
||||||
10'b0011_0101_11, // M=4
|
|
||||||
10'b0011_1001_11, // M=5
|
|
||||||
10'b0011_1110_11, // M=6
|
|
||||||
10'b0011_1110_11, // M=7
|
|
||||||
10'b0011_0001_11,
|
|
||||||
10'b0011_0110_11,
|
|
||||||
10'b0011_0110_11,
|
|
||||||
10'b0011_0110_11,
|
|
||||||
10'b0011_1010_11,
|
|
||||||
10'b0011_1010_11,
|
|
||||||
10'b0011_1010_11,
|
|
||||||
10'b0100_0110_11,
|
|
||||||
10'b0011_1100_11,
|
|
||||||
10'b1110_0110_11,
|
|
||||||
10'b1111_0110_11,
|
|
||||||
10'b1110_1010_11,
|
|
||||||
10'b1110_1010_11,
|
|
||||||
10'b1111_1010_11,
|
|
||||||
10'b1111_1010_11,
|
|
||||||
10'b1111_1010_11,
|
|
||||||
10'b1111_1010_11,
|
|
||||||
10'b1111_1010_11,
|
|
||||||
10'b1101_1100_11,
|
|
||||||
10'b1101_1100_11,
|
|
||||||
10'b1101_1100_11,
|
|
||||||
10'b1110_1100_11,
|
|
||||||
10'b1110_1100_11,
|
|
||||||
10'b1110_1100_11,
|
|
||||||
10'b1111_1100_11,
|
|
||||||
10'b1111_1100_11,
|
|
||||||
10'b1111_1100_11,
|
|
||||||
10'b1111_1100_11,
|
|
||||||
10'b1111_1100_11,
|
|
||||||
10'b1111_1100_11,
|
|
||||||
10'b1110_0010_11,
|
|
||||||
10'b1110_0010_11,
|
|
||||||
10'b1110_0010_11,
|
|
||||||
10'b1110_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11, // M=127
|
|
||||||
10'b1101_1000_11 // M=128
|
|
||||||
};
|
|
||||||
|
|
||||||
lookup_high = {
|
|
||||||
// CP_RES_LFHF
|
|
||||||
10'b0111_1111_11, // M=1 - not legal
|
|
||||||
10'b0111_1111_11, // M=2
|
|
||||||
10'b1110_1111_11, // M=3
|
|
||||||
10'b1111_1111_11, // M=4
|
|
||||||
10'b1111_1011_11, // M=5
|
|
||||||
10'b1111_1101_11, // M=6
|
|
||||||
10'b1111_0011_11, // M=7
|
|
||||||
10'b1110_0101_11,
|
|
||||||
10'b1111_1001_11,
|
|
||||||
10'b1111_1001_11,
|
|
||||||
10'b1110_1110_11,
|
|
||||||
10'b1111_1110_11,
|
|
||||||
10'b1111_0001_11,
|
|
||||||
10'b1111_0001_11,
|
|
||||||
10'b1111_0001_11,
|
|
||||||
10'b1110_0110_11,
|
|
||||||
10'b1110_0110_11,
|
|
||||||
10'b1111_0110_11,
|
|
||||||
10'b1110_1010_11,
|
|
||||||
10'b1110_1010_11,
|
|
||||||
10'b1111_1010_11,
|
|
||||||
10'b1111_1010_11,
|
|
||||||
10'b1111_1010_11,
|
|
||||||
10'b1111_1010_11,
|
|
||||||
10'b1111_1010_11,
|
|
||||||
10'b1101_1100_11,
|
|
||||||
10'b1101_1100_11,
|
|
||||||
10'b1101_1100_11,
|
|
||||||
10'b1110_1100_11,
|
|
||||||
10'b1110_1100_11,
|
|
||||||
10'b1110_1100_11,
|
|
||||||
10'b1111_1100_11,
|
|
||||||
10'b1111_1100_11,
|
|
||||||
10'b1111_1100_11,
|
|
||||||
10'b1111_1100_11,
|
|
||||||
10'b1111_1100_11,
|
|
||||||
10'b1111_1100_11,
|
|
||||||
10'b1110_0010_11,
|
|
||||||
10'b1110_0010_11,
|
|
||||||
10'b1110_0010_11,
|
|
||||||
10'b1110_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1111_0010_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1100_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1101_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1110_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1111_0100_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11,
|
|
||||||
10'b1101_1000_11 // M=128
|
|
||||||
};
|
|
||||||
|
|
||||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
|
||||||
if(BANDWIDTH == "LOW") begin
|
|
||||||
// Low Bandwidth
|
|
||||||
mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
|
|
||||||
end else begin
|
|
||||||
// High or optimized bandwidth
|
|
||||||
mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
|
|
||||||
end
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes in the divide, phase, and duty cycle
|
|
||||||
// setting to calculate the upper and lower counter registers.
|
|
||||||
function [37:0] mmcm_pll_count_calc
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input signed [31:0] phase,
|
|
||||||
input [31:0] duty_cycle // Multiplied by 100,000
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [13:0] div_calc;
|
|
||||||
reg [16:0] phase_calc;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
|
||||||
divide, phase, duty_cycle);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
|
||||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
|
||||||
// mx[10:9], pm[8:6], dt[5:0]
|
|
||||||
phase_calc = mmcm_pll_phase(divide, phase);
|
|
||||||
|
|
||||||
// Return value is the upper and lower address of counter
|
|
||||||
// Upper address is:
|
|
||||||
// RESERVED [31:26]
|
|
||||||
// MX [25:24]
|
|
||||||
// EDGE [23]
|
|
||||||
// NOCOUNT [22]
|
|
||||||
// DELAY_TIME [21:16]
|
|
||||||
// Lower Address is:
|
|
||||||
// PHASE_MUX [15:13]
|
|
||||||
// RESERVED [12]
|
|
||||||
// HIGH_TIME [11:6]
|
|
||||||
// LOW_TIME [5:0]
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
|
||||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
|
||||||
div_calc[13], div_calc[12],
|
|
||||||
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
mmcm_pll_count_calc =
|
|
||||||
{
|
|
||||||
// Upper Address
|
|
||||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
|
||||||
// Lower Address
|
|
||||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
|
||||||
};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
|
|
||||||
// This function takes in the divide, phase, and duty cycle
|
|
||||||
// setting to calculate the upper and lower counter registers.
|
|
||||||
// for fractional multiply/divide functions.
|
|
||||||
//
|
|
||||||
//
|
|
||||||
function [37:0] mmcm_frac_count_calc
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input signed [31:0] phase,
|
|
||||||
input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
|
|
||||||
input [9:0] frac // Multiplied by 1000
|
|
||||||
);
|
|
||||||
|
|
||||||
//Required for fractional divide calculations
|
|
||||||
reg [7:0] lt_frac;
|
|
||||||
reg [7:0] ht_frac;
|
|
||||||
|
|
||||||
reg /*[7:0]*/ wf_fall_frac;
|
|
||||||
reg /*[7:0]*/ wf_rise_frac;
|
|
||||||
|
|
||||||
reg [31:0] a;
|
|
||||||
reg [7:0] pm_rise_frac_filtered ;
|
|
||||||
reg [7:0] pm_fall_frac_filtered ;
|
|
||||||
reg [7:0] clkout0_divide_int;
|
|
||||||
reg [2:0] clkout0_divide_frac;
|
|
||||||
reg [7:0] even_part_high;
|
|
||||||
reg [7:0] even_part_low;
|
|
||||||
|
|
||||||
reg [7:0] odd;
|
|
||||||
reg [7:0] odd_and_frac;
|
|
||||||
|
|
||||||
reg [7:0] pm_fall;
|
|
||||||
reg [7:0] pm_rise;
|
|
||||||
reg [7:0] dt;
|
|
||||||
reg [7:0] dt_int;
|
|
||||||
reg [63:0] dt_calc;
|
|
||||||
|
|
||||||
reg [7:0] pm_rise_frac;
|
|
||||||
reg [7:0] pm_fall_frac;
|
|
||||||
|
|
||||||
reg [31:0] a_per_in_octets;
|
|
||||||
reg [31:0] a_phase_in_cycles;
|
|
||||||
|
|
||||||
parameter precision = 0.125;
|
|
||||||
|
|
||||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
|
||||||
reg [31: 0] phase_pos;
|
|
||||||
reg [31: 0] phase_vco;
|
|
||||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
|
||||||
reg [13:0] div_calc;
|
|
||||||
reg [16:0] phase_calc;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
|
||||||
divide, phase, duty_cycle);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
//convert phase to fixed
|
|
||||||
if ((phase < -360000) || (phase > 360000)) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
// Return value is
|
|
||||||
// Transfer data
|
|
||||||
// RESERVED [37:36]
|
|
||||||
// FRAC_TIME [35:33]
|
|
||||||
// FRAC_WF_FALL [32]
|
|
||||||
// Upper address is:
|
|
||||||
// RESERVED [31:26]
|
|
||||||
// MX [25:24]
|
|
||||||
// EDGE [23]
|
|
||||||
// NOCOUNT [22]
|
|
||||||
// DELAY_TIME [21:16]
|
|
||||||
// Lower Address is:
|
|
||||||
// PHASE_MUX [15:13]
|
|
||||||
// RESERVED [12]
|
|
||||||
// HIGH_TIME [11:6]
|
|
||||||
// LOW_TIME [5:0]
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
clkout0_divide_frac = frac / 125;
|
|
||||||
clkout0_divide_int = divide;
|
|
||||||
|
|
||||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
|
||||||
even_part_low = even_part_high;
|
|
||||||
|
|
||||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
|
||||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
|
||||||
|
|
||||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
|
||||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
|
||||||
|
|
||||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
|
||||||
pm_rise = 0; //0
|
|
||||||
|
|
||||||
wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
|
|
||||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//Calculate phase in fractional cycles
|
|
||||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
|
||||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
|
||||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
|
||||||
|
|
||||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
|
||||||
dt = dt_calc[7:0];
|
|
||||||
|
|
||||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
|
||||||
|
|
||||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
|
||||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
|
||||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
|
||||||
|
|
||||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
|
||||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
|
||||||
|
|
||||||
mmcm_frac_count_calc[37:0] =
|
|
||||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
|
||||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0],
|
|
||||||
pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
|
||||||
} ;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
-536
@@ -1,536 +0,0 @@
|
|||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
//
|
|
||||||
// Company: Xilinx
|
|
||||||
// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+
|
|
||||||
// Date: 6/15/2015
|
|
||||||
// Design Name: PLLE4 DRP
|
|
||||||
// Module Name: plle4_drp_func.h
|
|
||||||
// Version: 2.0
|
|
||||||
// Target Devices: UltraScale+ Architecture
|
|
||||||
// Tool versions: 2017.1
|
|
||||||
// Description: This header provides the functions necessary to
|
|
||||||
// calculate the DRP register values for the V6 PLL.
|
|
||||||
//
|
|
||||||
// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
|
|
||||||
// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
|
|
||||||
// M_Rise bits have been removed for PLLE3
|
|
||||||
// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for
|
|
||||||
// Ultrascale+ and for max M of 21
|
|
||||||
//
|
|
||||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
|
||||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
|
||||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
|
||||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
|
||||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
|
||||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
|
||||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
|
||||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
|
||||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
|
||||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
|
||||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
|
||||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
|
||||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
|
||||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
|
||||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
|
||||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
// PURPOSE.
|
|
||||||
//
|
|
||||||
// (c) Copyright 2009-2017 Xilinx, Inc.
|
|
||||||
// All rights reserved.
|
|
||||||
//
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
|
|
||||||
// These are user functions that should not be modified. Changes to the defines
|
|
||||||
// or code within the functions may alter the accuracy of the calculations.
|
|
||||||
|
|
||||||
// Define debug to provide extra messages durring elaboration
|
|
||||||
//`define DEBUG 1
|
|
||||||
|
|
||||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
|
||||||
// point numbers. These should not be modified, they are for development
|
|
||||||
// only
|
|
||||||
`define FRAC_PRECISION 10
|
|
||||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
|
||||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
|
||||||
// greater than 32
|
|
||||||
`define FIXED_WIDTH 32
|
|
||||||
|
|
||||||
// This function takes a fixed point number and rounds it to the nearest
|
|
||||||
// fractional precision bit.
|
|
||||||
function [`FIXED_WIDTH:1] round_frac
|
|
||||||
(
|
|
||||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
|
||||||
input [`FIXED_WIDTH:1] decimal,
|
|
||||||
|
|
||||||
// This describes the precision of the fraction, for example a value
|
|
||||||
// of 1 would modify the fractional so that instead of being a .16
|
|
||||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
|
||||||
input [`FIXED_WIDTH:1] precision
|
|
||||||
);
|
|
||||||
|
|
||||||
begin
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
|
||||||
`endif
|
|
||||||
// If the fractional precision bit is high then round up
|
|
||||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
|
||||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
|
||||||
end else begin
|
|
||||||
round_frac = decimal;
|
|
||||||
end
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("round_frac: %h", round_frac);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function calculates high_time, low_time, w_edge, and no_count
|
|
||||||
// of a non-fractional counter based on the divide and duty cycle
|
|
||||||
//
|
|
||||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
|
||||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
|
||||||
// ignore the overflow)
|
|
||||||
function [13:0] mmcm_pll_divider
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
|
||||||
|
|
||||||
// High/Low time is initially calculated with a wider integer to prevent a
|
|
||||||
// calculation error when it overflows to 64.
|
|
||||||
reg [6:0] high_time;
|
|
||||||
reg [6:0] low_time;
|
|
||||||
reg w_edge;
|
|
||||||
reg no_count;
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] temp;
|
|
||||||
|
|
||||||
begin
|
|
||||||
// Duty Cycle must be between 0 and 1,000
|
|
||||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
|
||||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
|
||||||
// Other values are dummies
|
|
||||||
if(divide == 7'h01) begin
|
|
||||||
high_time = 7'h01;
|
|
||||||
w_edge = 1'b0;
|
|
||||||
low_time = 7'h01;
|
|
||||||
no_count = 1'b1;
|
|
||||||
end else begin
|
|
||||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
|
||||||
|
|
||||||
// comes from above round_frac
|
|
||||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
|
||||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
|
||||||
// is set.
|
|
||||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
|
||||||
|
|
||||||
// If the high time comes out to 0, it needs to be set to at least 1
|
|
||||||
// and w_edge set to 0
|
|
||||||
if(high_time == 7'h00) begin
|
|
||||||
high_time = 7'h01;
|
|
||||||
w_edge = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
if(high_time == divide) begin
|
|
||||||
high_time = divide - 1;
|
|
||||||
w_edge = 1'b1;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Calculate low_time based on the divide setting and set no_count to
|
|
||||||
// 0 as it is only used when divide is 1.
|
|
||||||
low_time = divide - high_time;
|
|
||||||
no_count = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Set the return value.
|
|
||||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function calculates mx, delay_time, and phase_mux
|
|
||||||
// of a non-fractional counter based on the divide and phase
|
|
||||||
//
|
|
||||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
|
||||||
// is used.
|
|
||||||
function [10:0] mmcm_pll_phase
|
|
||||||
(
|
|
||||||
// divide must be an integer (use fractional if not)
|
|
||||||
// assumed that divide already checked to be valid
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
|
|
||||||
// Phase is given in degrees (-360,000 to 360,000)
|
|
||||||
input signed [31:0] phase
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
|
||||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
|
||||||
reg [1:0] mx;
|
|
||||||
reg [5:0] delay_time;
|
|
||||||
reg [2:0] phase_mux;
|
|
||||||
|
|
||||||
reg [`FIXED_WIDTH:1] temp;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("pll_phase-divide:%d,phase:%d",
|
|
||||||
divide, phase);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
if ((phase < -360000) || (phase > 360000)) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
// If phase is less than 0, convert it to a positive phase shift
|
|
||||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
|
||||||
if(phase < 0) begin
|
|
||||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
|
||||||
end else begin
|
|
||||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Put phase in terms of decimal number of vco clock cycles
|
|
||||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
|
|
||||||
temp = round_frac(phase_in_cycles, 3);
|
|
||||||
|
|
||||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
|
||||||
mx = 2'b00;
|
|
||||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
|
||||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("temp: %h", temp);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// Setup the return value
|
|
||||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes the divide value and outputs the necessary lock values
|
|
||||||
function [39:0] mmcm_pll_lock_lookup
|
|
||||||
(
|
|
||||||
input [6:0] divide // Max divide is 21
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [839:0] lookup;
|
|
||||||
|
|
||||||
begin
|
|
||||||
lookup = {
|
|
||||||
// This table is composed of:
|
|
||||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
|
||||||
40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
|
|
||||||
40'b00110_00110_1111101000_1111101001_0000000001, //2
|
|
||||||
40'b01000_01000_1111101000_1111101001_0000000001, //3
|
|
||||||
40'b01011_01011_1111101000_1111101001_0000000001, //4
|
|
||||||
40'b01110_01110_1111101000_1111101001_0000000001, //5
|
|
||||||
40'b10001_10001_1111101000_1111101001_0000000001, //6
|
|
||||||
40'b10011_10011_1111101000_1111101001_0000000001, //7
|
|
||||||
40'b10110_10110_1111101000_1111101001_0000000001, //8
|
|
||||||
40'b11001_11001_1111101000_1111101001_0000000001, //9
|
|
||||||
40'b11100_11100_1111101000_1111101001_0000000001, //10
|
|
||||||
40'b11111_11111_1110000100_1111101001_0000000001, //11
|
|
||||||
40'b11111_11111_1100111001_1111101001_0000000001, //12
|
|
||||||
40'b11111_11111_1011101110_1111101001_0000000001, //13
|
|
||||||
40'b11111_11111_1010111100_1111101001_0000000001, //14
|
|
||||||
40'b11111_11111_1010001010_1111101001_0000000001, //15
|
|
||||||
40'b11111_11111_1001110001_1111101001_0000000001, //16
|
|
||||||
40'b11111_11111_1000111111_1111101001_0000000001, //17
|
|
||||||
40'b11111_11111_1000100110_1111101001_0000000001, //18
|
|
||||||
40'b11111_11111_1000001101_1111101001_0000000001, //19
|
|
||||||
40'b11111_11111_0111110100_1111101001_0000000001, //20
|
|
||||||
40'b11111_11111_0111011011_1111101001_0000000001 //21
|
|
||||||
};
|
|
||||||
|
|
||||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
|
||||||
mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("lock_lookup: %b", pll_lock_lookup);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function takes the divide value and the bandwidth setting of the PLL
|
|
||||||
// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
|
|
||||||
function [9:0] mmcm_pll_filter_lookup
|
|
||||||
(
|
|
||||||
input [6:0] divide // Max divide is 21
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [209:0] lookup;
|
|
||||||
reg [9:0] lookup_entry;
|
|
||||||
|
|
||||||
begin
|
|
||||||
|
|
||||||
lookup = {
|
|
||||||
// CP_RES_LFHF
|
|
||||||
10'b0011_0111_11, //1 not legal in Ultrascale+
|
|
||||||
10'b0011_0111_11, //2
|
|
||||||
10'b0011_0011_11, //3
|
|
||||||
10'b0011_1001_11, //4
|
|
||||||
10'b0011_0001_11, //5
|
|
||||||
10'b0100_1110_11, //6
|
|
||||||
10'b0011_0110_11, //7
|
|
||||||
10'b0011_1010_11, //8
|
|
||||||
10'b0111_1001_11, //9
|
|
||||||
10'b0111_1001_11, //10
|
|
||||||
10'b0101_0110_11, //11
|
|
||||||
10'b1100_0101_11, //12
|
|
||||||
10'b0101_1010_11, //13
|
|
||||||
10'b0110_0110_11, //14
|
|
||||||
10'b0110_1010_11, //15
|
|
||||||
10'b0111_0110_11, //16
|
|
||||||
10'b1111_0101_11, //17
|
|
||||||
10'b1100_0110_11, //18
|
|
||||||
10'b1110_0001_11, //19
|
|
||||||
10'b1101_0110_11, //20
|
|
||||||
10'b1111_0001_11 //21
|
|
||||||
};
|
|
||||||
|
|
||||||
mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("filter_lookup: %b", pll_filter_lookup);
|
|
||||||
`endif
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// This function set the CLKOUTPHY divide settings to match
|
|
||||||
// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
|
|
||||||
// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
|
|
||||||
// doubled and 2'b00 will represent divide by 1. Similarly "VCO"
|
|
||||||
// will need to divide the doubled clock VCO clock frequency by
|
|
||||||
// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will
|
|
||||||
// need to divide the doubled VCO by 4, therefore 2'b10
|
|
||||||
function [9:0] mmcm_pll_clkoutphy_calc
|
|
||||||
(
|
|
||||||
input [8*9:0] CLKOUTPHY_MODE
|
|
||||||
);
|
|
||||||
|
|
||||||
if(CLKOUTPHY_MODE == "VCO_X2") begin
|
|
||||||
mmcm_pll_clkoutphy_calc= 2'b00;
|
|
||||||
end else if(CLKOUTPHY_MODE == "VCO") begin
|
|
||||||
mmcm_pll_clkoutphy_calc= 2'b01;
|
|
||||||
end else if(CLKOUTPHY_MODE == "CLKIN") begin
|
|
||||||
mmcm_pll_clkoutphy_calc= 2'b11;
|
|
||||||
end else begin // Assume "VCO_HALF"
|
|
||||||
mmcm_pll_clkoutphy_calc= 2'b10;
|
|
||||||
end
|
|
||||||
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
|
|
||||||
// This function takes in the divide, phase, and duty cycle
|
|
||||||
// setting to calculate the upper and lower counter registers.
|
|
||||||
function [37:0] mmcm_pll_count_calc
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input signed [31:0] phase,
|
|
||||||
input [31:0] duty_cycle // Multiplied by 100,000
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [13:0] div_calc;
|
|
||||||
reg [16:0] phase_calc;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
|
||||||
divide, phase, duty_cycle);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
|
||||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
|
||||||
// mx[10:9], pm[8:6], dt[5:0]
|
|
||||||
phase_calc = mmcm_pll_phase(divide, phase);
|
|
||||||
|
|
||||||
// Return value is the upper and lower address of counter
|
|
||||||
// Upper address is:
|
|
||||||
// RESERVED [31:26]
|
|
||||||
// MX [25:24]
|
|
||||||
// EDGE [23]
|
|
||||||
// NOCOUNT [22]
|
|
||||||
// DELAY_TIME [21:16]
|
|
||||||
// Lower Address is:
|
|
||||||
// PHASE_MUX [15:13]
|
|
||||||
// RESERVED [12]
|
|
||||||
// HIGH_TIME [11:6]
|
|
||||||
// LOW_TIME [5:0]
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
|
||||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
|
||||||
div_calc[13], div_calc[12],
|
|
||||||
phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
|
|
||||||
`endif
|
|
||||||
|
|
||||||
mmcm_pll_count_calc =
|
|
||||||
{
|
|
||||||
// Upper Address
|
|
||||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
|
||||||
// Lower Address
|
|
||||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
|
||||||
};
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
|
|
||||||
// This function takes in the divide, phase, and duty cycle
|
|
||||||
// setting to calculate the upper and lower counter registers.
|
|
||||||
// for fractional multiply/divide functions.
|
|
||||||
//
|
|
||||||
//
|
|
||||||
function [37:0] mmcm_pll_frac_count_calc
|
|
||||||
(
|
|
||||||
input [7:0] divide, // Max divide is 128
|
|
||||||
input signed [31:0] phase,
|
|
||||||
input [31:0] duty_cycle, // Multiplied by 1,000
|
|
||||||
input [9:0] frac // Multiplied by 1000
|
|
||||||
);
|
|
||||||
|
|
||||||
//Required for fractional divide calculations
|
|
||||||
reg [7:0] lt_frac;
|
|
||||||
reg [7:0] ht_frac;
|
|
||||||
|
|
||||||
reg /*[7:0]*/ wf_fall_frac;
|
|
||||||
reg /*[7:0]*/ wf_rise_frac;
|
|
||||||
|
|
||||||
reg [31:0] a;
|
|
||||||
reg [7:0] pm_rise_frac_filtered ;
|
|
||||||
reg [7:0] pm_fall_frac_filtered ;
|
|
||||||
reg [7:0] clkout0_divide_int;
|
|
||||||
reg [2:0] clkout0_divide_frac;
|
|
||||||
reg [7:0] even_part_high;
|
|
||||||
reg [7:0] even_part_low;
|
|
||||||
|
|
||||||
reg [7:0] odd;
|
|
||||||
reg [7:0] odd_and_frac;
|
|
||||||
|
|
||||||
reg [7:0] pm_fall;
|
|
||||||
reg [7:0] pm_rise;
|
|
||||||
reg [7:0] dt;
|
|
||||||
reg [7:0] dt_int;
|
|
||||||
reg [63:0] dt_calc;
|
|
||||||
|
|
||||||
reg [7:0] pm_rise_frac;
|
|
||||||
reg [7:0] pm_fall_frac;
|
|
||||||
|
|
||||||
reg [31:0] a_per_in_octets;
|
|
||||||
reg [31:0] a_phase_in_cycles;
|
|
||||||
|
|
||||||
parameter precision = 0.125;
|
|
||||||
|
|
||||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
|
||||||
reg [31: 0] phase_pos;
|
|
||||||
reg [31: 0] phase_vco;
|
|
||||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
|
||||||
reg [13:0] div_calc;
|
|
||||||
reg [16:0] phase_calc;
|
|
||||||
|
|
||||||
begin
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
|
||||||
divide, phase, duty_cycle);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
//convert phase to fixed
|
|
||||||
if ((phase < -360000) || (phase > 360000)) begin
|
|
||||||
`ifndef SYNTHESIS
|
|
||||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
|
||||||
`endif
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
// Return value is
|
|
||||||
// Transfer data
|
|
||||||
// RESERVED [37:36]
|
|
||||||
// FRAC_TIME [35:33]
|
|
||||||
// FRAC_WF_FALL [32]
|
|
||||||
// Upper address is:
|
|
||||||
// RESERVED [31:26]
|
|
||||||
// MX [25:24]
|
|
||||||
// EDGE [23]
|
|
||||||
// NOCOUNT [22]
|
|
||||||
// DELAY_TIME [21:16]
|
|
||||||
// Lower Address is:
|
|
||||||
// PHASE_MUX [15:13]
|
|
||||||
// RESERVED [12]
|
|
||||||
// HIGH_TIME [11:6]
|
|
||||||
// LOW_TIME [5:0]
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
clkout0_divide_frac = frac / 125;
|
|
||||||
clkout0_divide_int = divide;
|
|
||||||
|
|
||||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
|
||||||
even_part_low = even_part_high;
|
|
||||||
|
|
||||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
|
||||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
|
||||||
|
|
||||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
|
||||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
|
||||||
|
|
||||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
|
||||||
pm_rise = 0; //0
|
|
||||||
|
|
||||||
wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
|
|
||||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//Calculate phase in fractional cycles
|
|
||||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
|
||||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
|
||||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
|
||||||
|
|
||||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
|
||||||
dt = dt_calc[7:0];
|
|
||||||
|
|
||||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
|
||||||
|
|
||||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
|
||||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
|
||||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
|
||||||
|
|
||||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
|
||||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
|
||||||
|
|
||||||
mmcm_pll_frac_count_calc[37:0] =
|
|
||||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
|
||||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
|
||||||
3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
|
|
||||||
} ;
|
|
||||||
|
|
||||||
`ifdef DEBUG
|
|
||||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
|
|
||||||
`endif
|
|
||||||
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu Mar 30 16:43:42 CST 2023
|
# Generated by export_simulation on Sat Apr 01 15:00:06 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu Mar 30 16:43:42 CST 2023
|
# Generated by Vivado on Sat Apr 01 15:00:06 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu Mar 30 16:43:42 CST 2023
|
# Generated by export_simulation on Sat Apr 01 15:00:06 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu Mar 30 16:43:42 CST 2023
|
# Generated by Vivado on Sat Apr 01 15:00:06 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu Mar 30 16:43:42 CST 2023
|
# Generated by export_simulation on Sat Apr 01 15:00:06 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu Mar 30 16:43:42 CST 2023
|
# Generated by Vivado on Sat Apr 01 15:00:06 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu Mar 30 16:43:42 CST 2023
|
# Generated by export_simulation on Sat Apr 01 15:00:06 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu Mar 30 16:43:42 CST 2023
|
# Generated by Vivado on Sat Apr 01 15:00:06 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu Mar 30 16:43:42 CST 2023
|
# Generated by export_simulation on Sat Apr 01 15:00:06 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu Mar 30 16:43:42 CST 2023
|
# Generated by Vivado on Sat Apr 01 15:00:06 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu Mar 30 16:43:42 CST 2023
|
# Generated by export_simulation on Sat Apr 01 15:00:06 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu Mar 30 16:43:42 CST 2023
|
# Generated by Vivado on Sat Apr 01 15:00:06 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu Mar 30 16:43:42 CST 2023
|
# Generated by export_simulation on Sat Apr 01 15:00:06 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu Mar 30 16:43:42 CST 2023
|
# Generated by Vivado on Sat Apr 01 15:00:06 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+1
-1
@@ -4,7 +4,7 @@
|
|||||||
# README.txt: Please read the sections below to understand the steps required to
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
# run the exported script and information about the source files.
|
# run the exported script and information about the source files.
|
||||||
#
|
#
|
||||||
# Generated by export_simulation on Thu Mar 30 16:43:42 CST 2023
|
# Generated by export_simulation on Sat Apr 01 15:00:06 CST 2023
|
||||||
#
|
#
|
||||||
################################################################################
|
################################################################################
|
||||||
|
|
||||||
|
|||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu Mar 30 16:43:42 CST 2023
|
# Generated by Vivado on Sat Apr 01 15:00:06 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
|||||||
+810
@@ -0,0 +1,810 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||||
|
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||||
|
<spirit:library>ipcache</spirit:library>
|
||||||
|
<spirit:name>88af289b6f841f2b</spirit:name>
|
||||||
|
<spirit:version>0</spirit:version>
|
||||||
|
<spirit:componentInstances>
|
||||||
|
<spirit:componentInstance>
|
||||||
|
<spirit:instanceName>vio_rfcontrl</spirit:instanceName>
|
||||||
|
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="vio" spirit:version="3.0"/>
|
||||||
|
<spirit:configurableElementValues>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_SYNCHRONIZATION">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT">13</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN100_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN101_WIDTH">1</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT6_INIT_VAL">0x0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT70_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT75_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT76_INIT_VAL">0x0</spirit:configurableElementValue>
|
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|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT76_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT77_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT77_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT78_INIT_VAL">0x0</spirit:configurableElementValue>
|
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|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT78_WIDTH">1</spirit:configurableElementValue>
|
||||||
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT79_INIT_VAL">0x0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT79_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT7_INIT_VAL">0x0</spirit:configurableElementValue>
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|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT7_WIDTH">4</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT80_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT80_WIDTH">1</spirit:configurableElementValue>
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|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT81_INIT_VAL">0x0</spirit:configurableElementValue>
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|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT81_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT82_INIT_VAL">0x0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT82_WIDTH">1</spirit:configurableElementValue>
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||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT83_INIT_VAL">0x0</spirit:configurableElementValue>
|
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|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT83_WIDTH">1</spirit:configurableElementValue>
|
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|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT84_INIT_VAL">0x0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT84_WIDTH">1</spirit:configurableElementValue>
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||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT85_INIT_VAL">0x0</spirit:configurableElementValue>
|
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|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT85_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT86_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT86_WIDTH">1</spirit:configurableElementValue>
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||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT87_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT87_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT88_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT88_WIDTH">1</spirit:configurableElementValue>
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||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT89_INIT_VAL">0x0</spirit:configurableElementValue>
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||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT89_WIDTH">1</spirit:configurableElementValue>
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|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT8_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT8_WIDTH">8</spirit:configurableElementValue>
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||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT90_INIT_VAL">0x0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT90_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT91_INIT_VAL">0x0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT91_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT92_INIT_VAL">0x0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT92_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT93_INIT_VAL">0x0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT93_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT94_INIT_VAL">0x0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT94_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT95_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT95_WIDTH">1</spirit:configurableElementValue>
|
||||||
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT96_INIT_VAL">0x0</spirit:configurableElementValue>
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||||||
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT96_WIDTH">1</spirit:configurableElementValue>
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||||||
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT97_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT97_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT98_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT98_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT99_INIT_VAL">0x0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT99_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_INIT_VAL">0x04</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_WIDTH">8</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">vio_rfcontrl</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">88af289b6f841f2b</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">9a10a187</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">14</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">20</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||||
|
</spirit:configurableElementValues>
|
||||||
|
</spirit:componentInstance>
|
||||||
|
</spirit:componentInstances>
|
||||||
|
</spirit:design>
|
||||||
BIN
Binary file not shown.
+10394
File diff suppressed because one or more lines are too long
+14923
File diff suppressed because it is too large
Load Diff
+35
@@ -0,0 +1,35 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
// Date : Sat Apr 1 15:00:25 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
|
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||||
|
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.v
|
||||||
|
// Design : vio_rfcontrl
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||||
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_out0, probe_out1, probe_out2,
|
||||||
|
probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9,
|
||||||
|
probe_out10, probe_out11, probe_out12)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0]" */;
|
||||||
|
input clk;
|
||||||
|
output [0:0]probe_out0;
|
||||||
|
output [0:0]probe_out1;
|
||||||
|
output [15:0]probe_out2;
|
||||||
|
output [7:0]probe_out3;
|
||||||
|
output [3:0]probe_out4;
|
||||||
|
output [3:0]probe_out5;
|
||||||
|
output [3:0]probe_out6;
|
||||||
|
output [3:0]probe_out7;
|
||||||
|
output [7:0]probe_out8;
|
||||||
|
output [7:0]probe_out9;
|
||||||
|
output [15:0]probe_out10;
|
||||||
|
output [15:0]probe_out11;
|
||||||
|
output [15:0]probe_out12;
|
||||||
|
endmodule
|
||||||
+43
@@ -0,0 +1,43 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
-- Date : Sat Apr 1 15:00:25 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||||
|
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.vhdl
|
||||||
|
-- Design : vio_rfcontrl
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||||
|
Port (
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||||
|
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||||
|
probe_out5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||||
|
probe_out6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||||
|
probe_out7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||||
|
probe_out8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||||
|
probe_out9 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||||
|
probe_out10 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
probe_out11 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
probe_out12 : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||||
|
|
||||||
|
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0]";
|
||||||
|
attribute X_CORE_INFO : string;
|
||||||
|
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
+5
-5
@@ -1,12 +1,12 @@
|
|||||||
version:1
|
version:1
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3133:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3134:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173657265706f72747461625f726572756e:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173657265706f72747461625f726572756e:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:32:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:32:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:34:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:34:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:35:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:35:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3131:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3131:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3738:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3836:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:33:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:33:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:32:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:32:00:00
|
||||||
@@ -20,10 +20,10 @@ version:1
|
|||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72657365745f636f6d706f736974655f66696c65:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72657365745f636f6d706f736974655f66696c65:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f636c6f73655f6469616c6f675f756e73617665645f6368616e6765735f77696c6c:34:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f636c6f73655f6469616c6f675f756e73617665645f6368616e6765735f77696c6c:34:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:39:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3130:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f72657365745f6f75747075745f70726f6475637473:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f72657365745f6f75747075745f70726f6475637473:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:33:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:33:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:32:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:32:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:32:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7870675f636f6566696c65776964676465745f62726f777365:32:00:00
|
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7870675f636f6566696c65776964676465745f62726f777365:32:00:00
|
||||||
eof:2194046006
|
eof:2846107009
|
||||||
|
|||||||
+3
-3
@@ -4,8 +4,8 @@ version:1
|
|||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:33:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:33:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:32:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:32:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:32:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3130:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3133:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265706f72746970737461747573:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265706f72746970737461747573:31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757067726164656970:31:00:00
|
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757067726164656970:31:00:00
|
||||||
eof:2810087140
|
eof:1018782184
|
||||||
|
|||||||
+1
-1
@@ -1,3 +1,3 @@
|
|||||||
version:1
|
version:1
|
||||||
6d6f64655f636f756e7465727c4755494d6f6465:4
|
6d6f64655f636f756e7465727c4755494d6f6465:5
|
||||||
eof:
|
eof:
|
||||||
|
|||||||
+5
-5
@@ -1,7 +1,7 @@
|
|||||||
version:1
|
version:1
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a3130306666673930302d32:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a3130306666673930302d32:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:616e745f636c6b5f67656e5f73746732:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:76696f5f7266636f6e74726c:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
@@ -33,7 +33,7 @@ version:1
|
|||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313073:00:00
|
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313173:00:00
|
||||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323031332e3934314d42:00:00
|
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323131322e3738394d42:00:00
|
||||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3631312e3035394d42:00:00
|
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3730372e3933344d42:00:00
|
||||||
eof:1824198752
|
eof:3718360243
|
||||||
|
|||||||
+9
-9
@@ -3,7 +3,7 @@
|
|||||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||||
The structure and the elements are likely to change over the next few releases.
|
The structure and the elements are likely to change over the next few releases.
|
||||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||||
<application name="pa" timeStamp="Thu Mar 30 16:53:12 2023">
|
<application name="pa" timeStamp="Sat Apr 1 15:00:58 2023">
|
||||||
<section name="Project Information" visible="false">
|
<section name="Project Information" visible="false">
|
||||||
<property name="ProjectID" value="fcb0b19a2b6a4584be9564047568bef1" type="ProjectID"/>
|
<property name="ProjectID" value="fcb0b19a2b6a4584be9564047568bef1" type="ProjectID"/>
|
||||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||||
@@ -22,20 +22,20 @@ This means code written to parse this file will need to be revisited each subseq
|
|||||||
<property name="ManageCompositeTargets" value="3" type="JavaHandler"/>
|
<property name="ManageCompositeTargets" value="3" type="JavaHandler"/>
|
||||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||||
<property name="OpenIPLocationHandler" value="2" type="JavaHandler"/>
|
<property name="OpenIPLocationHandler" value="2" type="JavaHandler"/>
|
||||||
<property name="OpenPreviousIPHandler" value="1" type="JavaHandler"/>
|
<property name="OpenPreviousIPHandler" value="2" type="JavaHandler"/>
|
||||||
<property name="RecustomizeCore" value="10" type="JavaHandler"/>
|
<property name="RecustomizeCore" value="13" type="JavaHandler"/>
|
||||||
<property name="ReportIPStatus" value="1" type="JavaHandler"/>
|
<property name="ReportIPStatus" value="1" type="JavaHandler"/>
|
||||||
<property name="UpgradeIP" value="1" type="JavaHandler"/>
|
<property name="UpgradeIP" value="1" type="JavaHandler"/>
|
||||||
</item>
|
</item>
|
||||||
<item name="Gui Handlers">
|
<item name="Gui Handlers">
|
||||||
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
|
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
|
||||||
<property name="BaseDialog_OK" value="13" type="GuiHandlerData"/>
|
<property name="BaseDialog_OK" value="14" type="GuiHandlerData"/>
|
||||||
<property name="BaseReportTab_RERUN" value="1" type="GuiHandlerData"/>
|
<property name="BaseReportTab_RERUN" value="1" type="GuiHandlerData"/>
|
||||||
<property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/>
|
<property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/>
|
||||||
<property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/>
|
<property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/>
|
||||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="5" type="GuiHandlerData"/>
|
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="5" type="GuiHandlerData"/>
|
||||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="11" type="GuiHandlerData"/>
|
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="11" type="GuiHandlerData"/>
|
||||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="78" type="GuiHandlerData"/>
|
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="86" type="GuiHandlerData"/>
|
||||||
<property name="GettingStartedView_MANAGE_IP" value="3" type="GuiHandlerData"/>
|
<property name="GettingStartedView_MANAGE_IP" value="3" type="GuiHandlerData"/>
|
||||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
||||||
<property name="HACGCCoeFileWidget_BROWSE" value="2" type="GuiHandlerData"/>
|
<property name="HACGCCoeFileWidget_BROWSE" value="2" type="GuiHandlerData"/>
|
||||||
@@ -49,17 +49,17 @@ This means code written to parse this file will need to be revisited each subseq
|
|||||||
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="1" type="GuiHandlerData"/>
|
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="1" type="GuiHandlerData"/>
|
||||||
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
|
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
|
||||||
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="4" type="GuiHandlerData"/>
|
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="4" type="GuiHandlerData"/>
|
||||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="9" type="GuiHandlerData"/>
|
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="10" type="GuiHandlerData"/>
|
||||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="3" type="GuiHandlerData"/>
|
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="3" type="GuiHandlerData"/>
|
||||||
<property name="SrcMenu_IP_DOCUMENTATION" value="2" type="GuiHandlerData"/>
|
<property name="SrcMenu_IP_DOCUMENTATION" value="2" type="GuiHandlerData"/>
|
||||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="1" type="GuiHandlerData"/>
|
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="2" type="GuiHandlerData"/>
|
||||||
<property name="XPG_CoeFileWidgdet_BROWSE" value="2" type="GuiHandlerData"/>
|
<property name="XPG_CoeFileWidgdet_BROWSE" value="2" type="GuiHandlerData"/>
|
||||||
</item>
|
</item>
|
||||||
<item name="Other">
|
<item name="Other">
|
||||||
<property name="GuiMode" value="52" type="GuiMode"/>
|
<property name="GuiMode" value="58" type="GuiMode"/>
|
||||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||||
<property name="TclMode" value="35" type="TclMode"/>
|
<property name="TclMode" value="39" type="TclMode"/>
|
||||||
</item>
|
</item>
|
||||||
</section>
|
</section>
|
||||||
</application>
|
</application>
|
||||||
|
|||||||
+8
@@ -0,0 +1,8 @@
|
|||||||
|
<?xml version="1.0"?>
|
||||||
|
<Runs Version="1" Minor="0">
|
||||||
|
<Run Id="vio_rfcontrl_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||||
|
<Parameters>
|
||||||
|
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||||
|
</Parameters>
|
||||||
|
</Runs>
|
||||||
|
|
||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="COSLUT_10_16bit_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
<GenRun Id="COSLUT_10_16bit_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
||||||
<File Type="RDS-UTIL-PB" Name="COSLUT_10_16bit_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="COSLUT_10_16bit_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="COSLUT_10_16bit_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="COSLUT_10_16bit_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="COSLUT_10_16bit.vds"/>
|
<File Type="RDS-RDS" Name="COSLUT_10_16bit.vds"/>
|
||||||
<File Type="RDS-DCP" Name="COSLUT_10_16bit.dcp"/>
|
<File Type="RDS-DCP" Name="COSLUT_10_16bit.dcp"/>
|
||||||
<File Type="PA-TCL" Name="COSLUT_10_16bit.tcl"/>
|
<File Type="PA-TCL" Name="COSLUT_10_16bit.tcl"/>
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="GaussFir_12m_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
<GenRun Id="GaussFir_12m_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
||||||
<File Type="RDS-UTIL-PB" Name="GaussFir_12m_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="GaussFir_12m_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="GaussFir_12m_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="GaussFir_12m_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="GaussFir_12m.vds"/>
|
<File Type="RDS-RDS" Name="GaussFir_12m.vds"/>
|
||||||
<File Type="RDS-DCP" Name="GaussFir_12m.dcp"/>
|
<File Type="RDS-DCP" Name="GaussFir_12m.dcp"/>
|
||||||
<File Type="PA-TCL" Name="GaussFir_12m.tcl"/>
|
<File Type="PA-TCL" Name="GaussFir_12m.tcl"/>
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="GaussFir_1mp5_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
<GenRun Id="GaussFir_1mp5_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
||||||
<File Type="RDS-UTIL-PB" Name="GaussFir_1mp5_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="GaussFir_1mp5_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="GaussFir_1mp5_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="GaussFir_1mp5_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="GaussFir_1mp5.vds"/>
|
<File Type="RDS-RDS" Name="GaussFir_1mp5.vds"/>
|
||||||
<File Type="RDS-DCP" Name="GaussFir_1mp5.dcp"/>
|
<File Type="RDS-DCP" Name="GaussFir_1mp5.dcp"/>
|
||||||
<File Type="PA-TCL" Name="GaussFir_1mp5.tcl"/>
|
<File Type="PA-TCL" Name="GaussFir_1mp5.tcl"/>
|
||||||
|
|||||||
+6
-11
@@ -1,14 +1,11 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="ant_clk_gen_stg1_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680166379">
|
<GenRun Id="ant_clk_gen_stg1_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680166379">
|
||||||
<File Type="VDS-TIMING-PB" Name="ant_clk_gen_stg1_timing_summary_synth.pb"/>
|
|
||||||
<File Type="VDS-TIMINGSUMMARY" Name="ant_clk_gen_stg1_timing_summary_synth.rpt"/>
|
|
||||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
|
|
||||||
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg1_reports.tcl"/>
|
|
||||||
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
|
|
||||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
|
|
||||||
<File Type="RDS-PROPCONSTRS" Name="ant_clk_gen_stg1_drc_synth.rpt"/>
|
|
||||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
|
||||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg1_utilization_synth.pb"/>
|
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg1_utilization_synth.pb"/>
|
||||||
|
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
|
||||||
|
<File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
|
||||||
|
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
|
||||||
|
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg1_reports.tcl"/>
|
||||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ant_clk_gen_stg1">
|
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ant_clk_gen_stg1">
|
||||||
<File Path="$PPRDIR/../ant_clk_gen_stg1/ant_clk_gen_stg1.xci">
|
<File Path="$PPRDIR/../ant_clk_gen_stg1/ant_clk_gen_stg1.xci">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
@@ -56,9 +53,7 @@
|
|||||||
</Config>
|
</Config>
|
||||||
</FileSet>
|
</FileSet>
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||||
<Desc>Vivado Synthesis Defaults</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="synth_design"/>
|
<Step Id="synth_design"/>
|
||||||
</Strategy>
|
</Strategy>
|
||||||
</GenRun>
|
</GenRun>
|
||||||
|
|||||||
+6
-11
@@ -1,14 +1,11 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="ant_clk_gen_stg2_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680166392">
|
<GenRun Id="ant_clk_gen_stg2_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680166392">
|
||||||
<File Type="VDS-TIMING-PB" Name="ant_clk_gen_stg2_timing_summary_synth.pb"/>
|
|
||||||
<File Type="VDS-TIMINGSUMMARY" Name="ant_clk_gen_stg2_timing_summary_synth.rpt"/>
|
|
||||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
|
|
||||||
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg2_reports.tcl"/>
|
|
||||||
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
|
|
||||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
|
|
||||||
<File Type="RDS-PROPCONSTRS" Name="ant_clk_gen_stg2_drc_synth.rpt"/>
|
|
||||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
|
||||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg2_utilization_synth.pb"/>
|
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg2_utilization_synth.pb"/>
|
||||||
|
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
|
||||||
|
<File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
|
||||||
|
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
|
||||||
|
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg2_reports.tcl"/>
|
||||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ant_clk_gen_stg2">
|
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ant_clk_gen_stg2">
|
||||||
<File Path="$PPRDIR/../ant_clk_gen_stg2/ant_clk_gen_stg2.xci">
|
<File Path="$PPRDIR/../ant_clk_gen_stg2/ant_clk_gen_stg2.xci">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
@@ -56,9 +53,7 @@
|
|||||||
</Config>
|
</Config>
|
||||||
</FileSet>
|
</FileSet>
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||||
<Desc>Vivado Synthesis Defaults</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="synth_design"/>
|
<Step Id="synth_design"/>
|
||||||
</Strategy>
|
</Strategy>
|
||||||
</GenRun>
|
</GenRun>
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="data_1p5m_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
<GenRun Id="data_1p5m_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
||||||
<File Type="RDS-UTIL-PB" Name="data_1p5m_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="data_1p5m_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="data_1p5m_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="data_1p5m_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="data_1p5m.vds"/>
|
<File Type="RDS-RDS" Name="data_1p5m.vds"/>
|
||||||
<File Type="RDS-DCP" Name="data_1p5m.dcp"/>
|
<File Type="RDS-DCP" Name="data_1p5m.dcp"/>
|
||||||
<File Type="PA-TCL" Name="data_1p5m.tcl"/>
|
<File Type="PA-TCL" Name="data_1p5m.tcl"/>
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="fifo_AntCtrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
<GenRun Id="fifo_AntCtrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
||||||
<File Type="RDS-UTIL-PB" Name="fifo_AntCtrl_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="fifo_AntCtrl_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="fifo_AntCtrl_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="fifo_AntCtrl_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="fifo_AntCtrl.vds"/>
|
<File Type="RDS-RDS" Name="fifo_AntCtrl.vds"/>
|
||||||
<File Type="RDS-DCP" Name="fifo_AntCtrl.dcp"/>
|
<File Type="RDS-DCP" Name="fifo_AntCtrl.dcp"/>
|
||||||
<File Type="PA-TCL" Name="fifo_AntCtrl.tcl"/>
|
<File Type="PA-TCL" Name="fifo_AntCtrl.tcl"/>
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="ila_AntCtrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
<GenRun Id="ila_AntCtrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165733">
|
||||||
<File Type="RDS-UTIL-PB" Name="ila_AntCtrl_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="ila_AntCtrl_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="ila_AntCtrl_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="ila_AntCtrl_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="ila_AntCtrl.vds"/>
|
<File Type="RDS-RDS" Name="ila_AntCtrl.vds"/>
|
||||||
<File Type="RDS-DCP" Name="ila_AntCtrl.dcp"/>
|
<File Type="RDS-DCP" Name="ila_AntCtrl.dcp"/>
|
||||||
<File Type="PA-TCL" Name="ila_AntCtrl.tcl"/>
|
<File Type="PA-TCL" Name="ila_AntCtrl.tcl"/>
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="ila_rfcontrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
<GenRun Id="ila_rfcontrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||||
<File Type="RDS-UTIL-PB" Name="ila_rfcontrl_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="ila_rfcontrl_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="ila_rfcontrl_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="ila_rfcontrl_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="ila_rfcontrl.vds"/>
|
<File Type="RDS-RDS" Name="ila_rfcontrl.vds"/>
|
||||||
<File Type="RDS-DCP" Name="ila_rfcontrl.dcp"/>
|
<File Type="RDS-DCP" Name="ila_rfcontrl.dcp"/>
|
||||||
<File Type="PA-TCL" Name="ila_rfcontrl.tcl"/>
|
<File Type="PA-TCL" Name="ila_rfcontrl.tcl"/>
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="ila_tx_rx_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
<GenRun Id="ila_tx_rx_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||||
<File Type="RDS-UTIL-PB" Name="ila_tx_rx_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="ila_tx_rx_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="ila_tx_rx_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="ila_tx_rx_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="ila_tx_rx.vds"/>
|
<File Type="RDS-RDS" Name="ila_tx_rx.vds"/>
|
||||||
<File Type="RDS-DCP" Name="ila_tx_rx.dcp"/>
|
<File Type="RDS-DCP" Name="ila_tx_rx.dcp"/>
|
||||||
<File Type="PA-TCL" Name="ila_tx_rx.tcl"/>
|
<File Type="PA-TCL" Name="ila_tx_rx.tcl"/>
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="vio_ant_rd_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
<GenRun Id="vio_ant_rd_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||||
<File Type="RDS-UTIL-PB" Name="vio_ant_rd_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="vio_ant_rd_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="vio_ant_rd_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="vio_ant_rd_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="vio_ant_rd.vds"/>
|
<File Type="RDS-RDS" Name="vio_ant_rd.vds"/>
|
||||||
<File Type="RDS-DCP" Name="vio_ant_rd.dcp"/>
|
<File Type="RDS-DCP" Name="vio_ant_rd.dcp"/>
|
||||||
<File Type="PA-TCL" Name="vio_ant_rd.tcl"/>
|
<File Type="PA-TCL" Name="vio_ant_rd.tcl"/>
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="vio_ant_test_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
<GenRun Id="vio_ant_test_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||||
<File Type="RDS-UTIL-PB" Name="vio_ant_test_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="vio_ant_test_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="vio_ant_test_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="vio_ant_test_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="vio_ant_test.vds"/>
|
<File Type="RDS-RDS" Name="vio_ant_test.vds"/>
|
||||||
<File Type="RDS-DCP" Name="vio_ant_test.dcp"/>
|
<File Type="RDS-DCP" Name="vio_ant_test.dcp"/>
|
||||||
<File Type="PA-TCL" Name="vio_ant_test.tcl"/>
|
<File Type="PA-TCL" Name="vio_ant_test.tcl"/>
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="vio_clk_ld_rd_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
<GenRun Id="vio_clk_ld_rd_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||||
<File Type="RDS-UTIL-PB" Name="vio_clk_ld_rd_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="vio_clk_ld_rd_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="vio_clk_ld_rd_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="vio_clk_ld_rd_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="vio_clk_ld_rd.vds"/>
|
<File Type="RDS-RDS" Name="vio_clk_ld_rd.vds"/>
|
||||||
<File Type="RDS-DCP" Name="vio_clk_ld_rd.dcp"/>
|
<File Type="RDS-DCP" Name="vio_clk_ld_rd.dcp"/>
|
||||||
<File Type="PA-TCL" Name="vio_clk_ld_rd.tcl"/>
|
<File Type="PA-TCL" Name="vio_clk_ld_rd.tcl"/>
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="vio_manual_ctrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
<GenRun Id="vio_manual_ctrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||||
<File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="vio_manual_ctrl_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="vio_manual_ctrl_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
|
<File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
|
||||||
<File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
|
<File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
|
||||||
<File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
|
<File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="vio_rf_rd_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
<GenRun Id="vio_rf_rd_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
||||||
<File Type="RDS-UTIL-PB" Name="vio_rf_rd_utilization_synth.pb"/>
|
|
||||||
<File Type="RDS-UTIL" Name="vio_rf_rd_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="vio_rf_rd_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-UTIL-PB" Name="vio_rf_rd_utilization_synth.pb"/>
|
||||||
<File Type="RDS-RDS" Name="vio_rf_rd.vds"/>
|
<File Type="RDS-RDS" Name="vio_rf_rd.vds"/>
|
||||||
<File Type="RDS-DCP" Name="vio_rf_rd.dcp"/>
|
<File Type="RDS-DCP" Name="vio_rf_rd.dcp"/>
|
||||||
<File Type="PA-TCL" Name="vio_rf_rd.tcl"/>
|
<File Type="PA-TCL" Name="vio_rf_rd.tcl"/>
|
||||||
|
|||||||
+1
-1
@@ -1,5 +1,5 @@
|
|||||||
<?xml version="1.0"?>
|
<?xml version="1.0"?>
|
||||||
<ProcessHandle Version="1" Minor="0">
|
<ProcessHandle Version="1" Minor="0">
|
||||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1236616" HostCore="20" HostMemory="65588996">
|
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="21687" HostCore="20" HostMemory="65589000">
|
||||||
</Process>
|
</Process>
|
||||||
</ProcessHandle>
|
</ProcessHandle>
|
||||||
|
|||||||
+10
-7
@@ -1,20 +1,23 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<GenRun Id="vio_rfcontrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680165734">
|
<GenRun Id="vio_rfcontrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1680332406">
|
||||||
|
<File Type="VDS-TIMING-PB" Name="vio_rfcontrl_timing_summary_synth.pb"/>
|
||||||
|
<File Type="VDS-TIMINGSUMMARY" Name="vio_rfcontrl_timing_summary_synth.rpt"/>
|
||||||
|
<File Type="RDS-DCP" Name="vio_rfcontrl.dcp"/>
|
||||||
<File Type="RDS-UTIL-PB" Name="vio_rfcontrl_utilization_synth.pb"/>
|
<File Type="RDS-UTIL-PB" Name="vio_rfcontrl_utilization_synth.pb"/>
|
||||||
<File Type="RDS-UTIL" Name="vio_rfcontrl_utilization_synth.rpt"/>
|
<File Type="RDS-UTIL" Name="vio_rfcontrl_utilization_synth.rpt"/>
|
||||||
|
<File Type="RDS-PROPCONSTRS" Name="vio_rfcontrl_drc_synth.rpt"/>
|
||||||
<File Type="RDS-RDS" Name="vio_rfcontrl.vds"/>
|
<File Type="RDS-RDS" Name="vio_rfcontrl.vds"/>
|
||||||
<File Type="RDS-DCP" Name="vio_rfcontrl.dcp"/>
|
|
||||||
<File Type="PA-TCL" Name="vio_rfcontrl.tcl"/>
|
|
||||||
<File Type="REPORTS-TCL" Name="vio_rfcontrl_reports.tcl"/>
|
<File Type="REPORTS-TCL" Name="vio_rfcontrl_reports.tcl"/>
|
||||||
|
<File Type="PA-TCL" Name="vio_rfcontrl.tcl"/>
|
||||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_rfcontrl">
|
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_rfcontrl">
|
||||||
<File Path="$PPRDIR/../vio_rfcontrl/vio_rfcontrl.xci">
|
<File Path="$PPRDIR/../vio_rfcontrl.xcix">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
<File Path="$PPRDIR/../vio_rfcontrl.xcix">
|
<File Path="$PPRDIR/../vio_rfcontrl/vio_rfcontrl.xci">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
@@ -27,14 +30,14 @@
|
|||||||
</Config>
|
</Config>
|
||||||
</FileSet>
|
</FileSet>
|
||||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_rfcontrl">
|
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_rfcontrl">
|
||||||
<File Path="$PPRDIR/../vio_rfcontrl/vio_rfcontrl.xci">
|
<File Path="$PPRDIR/../vio_rfcontrl.xcix">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
<File Path="$PPRDIR/../vio_rfcontrl.xcix">
|
<File Path="$PPRDIR/../vio_rfcontrl/vio_rfcontrl.xci">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
|||||||
+11
-11
@@ -1,13 +1,13 @@
|
|||||||
version:1
|
version:1
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3134:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3135:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3137:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3135:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3137:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||||
@@ -37,12 +37,12 @@ version:1
|
|||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3231:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3430:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3231:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3430:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3231:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3430:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3231:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3430:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3231:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3430:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3231:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3430:00:00
|
||||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3231:00:00
|
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3430:00:00
|
||||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6162313361656133326334373465343162373332306435626531383733633465:506172656e742050412070726f6a656374204944:00
|
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6162313361656133326334373465343162373332306435626531383733633465:506172656e742050412070726f6a656374204944:00
|
||||||
eof:1974806739
|
eof:2407083661
|
||||||
|
|||||||
BIN
Binary file not shown.
+79
-63
@@ -2,8 +2,8 @@
|
|||||||
# Vivado v2019.1.3 (64-bit)
|
# Vivado v2019.1.3 (64-bit)
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||||
# Start of session at: Thu Mar 30 16:42:15 2023
|
# Start of session at: Sat Apr 1 15:00:07 2023
|
||||||
# Process ID: 1237071
|
# Process ID: 21726
|
||||||
# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1
|
# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1
|
||||||
# Command line: vivado -log vio_rfcontrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rfcontrl.tcl
|
# Command line: vivado -log vio_rfcontrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rfcontrl.tcl
|
||||||
# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds
|
# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds
|
||||||
@@ -16,16 +16,30 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100'
|
|||||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100'
|
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100'
|
||||||
INFO: [Device 21-403] Loading part xc7z100ffg900-2
|
INFO: [Device 21-403] Loading part xc7z100ffg900-2
|
||||||
INFO: Launching helper process for spawning children vivado processes
|
INFO: Launching helper process for spawning children vivado processes
|
||||||
INFO: Helper process launched with PID 1237431
|
INFO: Helper process launched with PID 21828
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1858.664 ; gain = 152.719 ; free physical = 423 ; free virtual = 39456
|
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.508 ; gain = 153.719 ; free physical = 28641 ; free virtual = 57975
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
INFO: [Synth 8-6157] synthesizing module 'vio_rfcontrl' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59]
|
INFO: [Synth 8-6157] synthesizing module 'vio_rfcontrl' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59]
|
||||||
WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rfcontrl does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/vio_rfcontrl/synth/vio_rfcontrl.v:95]
|
WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rfcontrl does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/vio_rfcontrl/synth/vio_rfcontrl.v:95]
|
||||||
INFO: [Synth 8-6155] done synthesizing module 'vio_rfcontrl' (7#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59]
|
INFO: [Synth 8-6155] done synthesizing module 'vio_rfcontrl' (7#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59]
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Bus_rst
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Read
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Internal_cnt_rst
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Bus_rst
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Read
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Internal_cnt_rst
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15]
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[14]
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[13]
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[12]
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[11]
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[10]
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[9]
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[8]
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Internal_cnt_rst
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[15]
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[15]
|
||||||
@@ -52,6 +66,9 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unc
|
|||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[5]
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[5]
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[4]
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[4]
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read
|
||||||
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15]
|
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15]
|
||||||
@@ -106,26 +123,9 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0
|
|||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0]
|
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0]
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in34[0]
|
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in34[0]
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in35[0]
|
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in35[0]
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in36[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in37[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in38[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in39[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in40[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in41[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in42[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in43[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in44[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in45[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in46[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in47[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in48[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in49[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in50[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in51[0]
|
|
||||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in52[0]
|
|
||||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1921.352 ; gain = 215.406 ; free physical = 433 ; free virtual = 38809
|
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1922.195 ; gain = 215.406 ; free physical = 28666 ; free virtual = 58002
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
Report Check Netlist:
|
Report Check Netlist:
|
||||||
@@ -138,10 +138,10 @@ Report Check Netlist:
|
|||||||
Start Handling Custom Attributes
|
Start Handling Custom Attributes
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1924.320 ; gain = 218.375 ; free physical = 553 ; free virtual = 38862
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.164 ; gain = 218.375 ; free physical = 28665 ; free virtual = 58001
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1924.320 ; gain = 218.375 ; free physical = 553 ; free virtual = 38861
|
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.164 ; gain = 218.375 ; free physical = 28665 ; free virtual = 58001
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||||
|
|
||||||
@@ -153,29 +153,29 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip
|
|||||||
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/vio_rfcontrl/vio_rfcontrl.xdc]
|
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/vio_rfcontrl/vio_rfcontrl.xdc]
|
||||||
Completed Processing XDC Constraints
|
Completed Processing XDC Constraints
|
||||||
|
|
||||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2097.977 ; gain = 0.000 ; free physical = 511 ; free virtual = 38386
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.852 ; gain = 0.000 ; free physical = 28545 ; free virtual = 57895
|
||||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||||
No Unisim elements were transformed.
|
No Unisim elements were transformed.
|
||||||
|
|
||||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2105.914 ; gain = 7.938 ; free physical = 497 ; free virtual = 38371
|
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2112.789 ; gain = 6.938 ; free physical = 28545 ; free virtual = 57895
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 504 ; free virtual = 38382
|
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28646 ; free virtual = 57997
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Start Loading Part and Timing Information
|
Start Loading Part and Timing Information
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Loading part: xc7z100ffg900-2
|
Loading part: xc7z100ffg900-2
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 503 ; free virtual = 38381
|
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28646 ; free virtual = 57997
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Start Applying 'set_property' XDC Constraints
|
Start Applying 'set_property' XDC Constraints
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 496 ; free virtual = 38374
|
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28647 ; free virtual = 57997
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 571 ; free virtual = 38460
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28640 ; free virtual = 57991
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
Report RTL Partitions:
|
Report RTL Partitions:
|
||||||
@@ -235,6 +235,21 @@ Detailed RTL Component Info :
|
|||||||
4 Bit Registers := 1
|
4 Bit Registers := 1
|
||||||
+---Muxes :
|
+---Muxes :
|
||||||
2 Input 1 Bit Muxes := 1
|
2 Input 1 Bit Muxes := 1
|
||||||
|
Module vio_v3_0_20_probe_out_one__parameterized3
|
||||||
|
Detailed RTL Component Info :
|
||||||
|
+---Registers :
|
||||||
|
16 Bit Registers := 1
|
||||||
|
8 Bit Registers := 1
|
||||||
|
+---Muxes :
|
||||||
|
2 Input 1 Bit Muxes := 1
|
||||||
|
Module vio_v3_0_20_probe_out_one__parameterized4
|
||||||
|
Detailed RTL Component Info :
|
||||||
|
+---Registers :
|
||||||
|
16 Bit Registers := 2
|
||||||
|
Module vio_v3_0_20_probe_out_one__parameterized5
|
||||||
|
Detailed RTL Component Info :
|
||||||
|
+---Registers :
|
||||||
|
16 Bit Registers := 2
|
||||||
Module vio_v3_0_20_probe_out_all
|
Module vio_v3_0_20_probe_out_all
|
||||||
Detailed RTL Component Info :
|
Detailed RTL Component Info :
|
||||||
+---Registers :
|
+---Registers :
|
||||||
@@ -404,7 +419,7 @@ INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int
|
|||||||
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] )
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] )
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 514 ; free virtual = 38415
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28623 ; free virtual = 57976
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
Report RTL Partitions:
|
Report RTL Partitions:
|
||||||
@@ -416,13 +431,13 @@ Report RTL Partitions:
|
|||||||
Start Applying XDC Timing Constraints
|
Start Applying XDC Timing Constraints
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 412 ; free virtual = 37849
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28491 ; free virtual = 57852
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Start Timing Optimization
|
Start Timing Optimization
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 405 ; free virtual = 37840
|
Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28491 ; free virtual = 57852
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
Report RTL Partitions:
|
Report RTL Partitions:
|
||||||
@@ -434,7 +449,7 @@ Report RTL Partitions:
|
|||||||
Start Technology Mapping
|
Start Technology Mapping
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 439 ; free virtual = 37809
|
Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
Report RTL Partitions:
|
Report RTL Partitions:
|
||||||
@@ -495,7 +510,7 @@ WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0
|
|||||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0
|
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0
|
||||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0
|
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 444 ; free virtual = 37817
|
Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
Report Check Netlist:
|
Report Check Netlist:
|
||||||
@@ -508,7 +523,7 @@ Report Check Netlist:
|
|||||||
Start Renaming Generated Instances
|
Start Renaming Generated Instances
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 444 ; free virtual = 37817
|
Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
Report RTL Partitions:
|
Report RTL Partitions:
|
||||||
@@ -520,25 +535,25 @@ Report RTL Partitions:
|
|||||||
Start Rebuilding User Hierarchy
|
Start Rebuilding User Hierarchy
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 442 ; free virtual = 37815
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Start Renaming Generated Ports
|
Start Renaming Generated Ports
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 442 ; free virtual = 37815
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Start Handling Custom Attributes
|
Start Handling Custom Attributes
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 439 ; free virtual = 37812
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Start Renaming Generated Nets
|
Start Renaming Generated Nets
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 439 ; free virtual = 37812
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Start Writing Synthesis Report
|
Start Writing Synthesis Report
|
||||||
@@ -559,7 +574,8 @@ Report Cell Usage:
|
|||||||
|3 |LUT4 | 8|
|
|3 |LUT4 | 8|
|
||||||
|4 |LUT5 | 20|
|
|4 |LUT5 | 20|
|
||||||
|5 |LUT6 | 112|
|
|5 |LUT6 | 112|
|
||||||
|6 |FDRE | 479|
|
|6 |FDRE | 455|
|
||||||
|
|7 |FDSE | 24|
|
||||||
+------+-----+------+
|
+------+-----+------+
|
||||||
|
|
||||||
Report Instance Areas:
|
Report Instance Areas:
|
||||||
@@ -572,47 +588,47 @@ Report Instance Areas:
|
|||||||
|4 | DECODER_INST |vio_v3_0_20_decoder | 85|
|
|4 | DECODER_INST |vio_v3_0_20_decoder | 85|
|
||||||
|5 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 302|
|
|5 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 302|
|
||||||
|6 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3|
|
|6 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3|
|
||||||
|7 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 32|
|
|7 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4 | 32|
|
||||||
|8 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_0 | 32|
|
|8 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4_0 | 32|
|
||||||
|9 | \G_PROBE_OUT[12].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_1 | 32|
|
|9 | \G_PROBE_OUT[12].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized5 | 32|
|
||||||
|10 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 3|
|
|10 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 3|
|
||||||
|11 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_3 | 32|
|
|11 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 32|
|
||||||
|12 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 16|
|
|12 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 16|
|
||||||
|13 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 8|
|
|13 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 8|
|
||||||
|14 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_4 | 8|
|
|14 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_2 | 8|
|
||||||
|15 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_5 | 8|
|
|15 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_3 | 8|
|
||||||
|16 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_6 | 8|
|
|16 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_4 | 8|
|
||||||
|17 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_7 | 16|
|
|17 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_5 | 16|
|
||||||
|18 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_8 | 16|
|
|18 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 16|
|
||||||
|19 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 18|
|
|19 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 18|
|
||||||
+------+----------------------------------------+--------------------------------------------+------+
|
+------+----------------------------------------+--------------------------------------------+------+
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 439 ; free virtual = 37812
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28485 ; free virtual = 57845
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
Synthesis finished with 0 errors, 0 critical warnings and 293 warnings.
|
Synthesis finished with 0 errors, 0 critical warnings and 293 warnings.
|
||||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2105.914 ; gain = 218.375 ; free physical = 494 ; free virtual = 37866
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2112.789 ; gain = 218.375 ; free physical = 28544 ; free virtual = 57905
|
||||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2105.914 ; gain = 399.969 ; free physical = 510 ; free virtual = 37878
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.789 ; gain = 406.000 ; free physical = 28558 ; free virtual = 57918
|
||||||
INFO: [Project 1-571] Translating synthesized netlist
|
INFO: [Project 1-571] Translating synthesized netlist
|
||||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.914 ; gain = 0.000 ; free physical = 1251 ; free virtual = 38617
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2112.789 ; gain = 0.000 ; free physical = 28478 ; free virtual = 57839
|
||||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||||
No Unisim elements were transformed.
|
No Unisim elements were transformed.
|
||||||
|
|
||||||
INFO: [Common 17-83] Releasing license: Synthesis
|
INFO: [Common 17-83] Releasing license: Synthesis
|
||||||
123 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
123 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||||
synth_design completed successfully
|
synth_design completed successfully
|
||||||
synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 2105.914 ; gain = 708.902 ; free physical = 1296 ; free virtual = 38663
|
synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2112.789 ; gain = 713.871 ; free physical = 28571 ; free virtual = 57931
|
||||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.914 ; gain = 0.000 ; free physical = 1300 ; free virtual = 38667
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2112.789 ; gain = 0.000 ; free physical = 28571 ; free virtual = 57931
|
||||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated.
|
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated.
|
||||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rfcontrl, cache-ID = 2d036cfb99334b0d
|
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rfcontrl, cache-ID = 88af289b6f841f2b
|
||||||
INFO: [Coretcl 2-1174] Renamed 18 cell refs.
|
INFO: [Coretcl 2-1174] Renamed 18 cell refs.
|
||||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2129.926 ; gain = 0.000 ; free physical = 1232 ; free virtual = 38604
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2136.801 ; gain = 0.000 ; free physical = 28574 ; free virtual = 57936
|
||||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated.
|
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated.
|
||||||
INFO: [runtcl-4] Executing : report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb
|
INFO: [runtcl-4] Executing : report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb
|
||||||
INFO: [Common 17-206] Exiting Vivado at Thu Mar 30 16:42:42 2023...
|
INFO: [Common 17-206] Exiting Vivado at Sat Apr 1 15:00:25 2023...
|
||||||
|
|||||||
+1062
-1062
File diff suppressed because one or more lines are too long
+1266
-1266
File diff suppressed because it is too large
Load Diff
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
// --------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------
|
||||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
// Date : Thu Mar 30 16:42:42 2023
|
// Date : Sat Apr 1 15:00:25 2023
|
||||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
// Command : write_verilog -force -mode synth_stub
|
// Command : write_verilog -force -mode synth_stub
|
||||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v
|
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v
|
||||||
|
|||||||
+1
-1
@@ -1,7 +1,7 @@
|
|||||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
-- Date : Thu Mar 30 16:42:42 2023
|
-- Date : Sat Apr 1 15:00:25 2023
|
||||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
-- Command : write_vhdl -force -mode synth_stub
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl
|
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl
|
||||||
|
|||||||
+5
-4
@@ -1,7 +1,7 @@
|
|||||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-------------------------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------------------------
|
||||||
| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
| Date : Thu Mar 30 16:42:42 2023
|
| Date : Sat Apr 1 15:00:25 2023
|
||||||
| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
| Command : report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb
|
| Command : report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb
|
||||||
| Design : vio_rfcontrl
|
| Design : vio_rfcontrl
|
||||||
@@ -56,8 +56,8 @@ Table of Contents
|
|||||||
| 0 | Yes | - | - |
|
| 0 | Yes | - | - |
|
||||||
| 0 | Yes | - | Set |
|
| 0 | Yes | - | Set |
|
||||||
| 0 | Yes | - | Reset |
|
| 0 | Yes | - | Reset |
|
||||||
| 0 | Yes | Set | - |
|
| 24 | Yes | Set | - |
|
||||||
| 479 | Yes | Reset | - |
|
| 455 | Yes | Reset | - |
|
||||||
+-------+--------------+-------------+--------------+
|
+-------+--------------+-------------+--------------+
|
||||||
|
|
||||||
|
|
||||||
@@ -152,9 +152,10 @@ Table of Contents
|
|||||||
+----------+------+---------------------+
|
+----------+------+---------------------+
|
||||||
| Ref Name | Used | Functional Category |
|
| Ref Name | Used | Functional Category |
|
||||||
+----------+------+---------------------+
|
+----------+------+---------------------+
|
||||||
| FDRE | 479 | Flop & Latch |
|
| FDRE | 455 | Flop & Latch |
|
||||||
| LUT6 | 112 | LUT |
|
| LUT6 | 112 | LUT |
|
||||||
| LUT3 | 43 | LUT |
|
| LUT3 | 43 | LUT |
|
||||||
|
| FDSE | 24 | Flop & Latch |
|
||||||
| LUT5 | 20 | LUT |
|
| LUT5 | 20 | LUT |
|
||||||
| LUT4 | 8 | LUT |
|
| LUT4 | 8 | LUT |
|
||||||
| LUT2 | 7 | LUT |
|
| LUT2 | 7 | LUT |
|
||||||
|
|||||||
BIN
Binary file not shown.
@@ -39,13 +39,13 @@
|
|||||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
<Option Name="WTXSimExportSim" Val="40"/>
|
<Option Name="WTXSimExportSim" Val="41"/>
|
||||||
<Option Name="WTModelSimExportSim" Val="40"/>
|
<Option Name="WTModelSimExportSim" Val="41"/>
|
||||||
<Option Name="WTQuestaExportSim" Val="40"/>
|
<Option Name="WTQuestaExportSim" Val="41"/>
|
||||||
<Option Name="WTIesExportSim" Val="40"/>
|
<Option Name="WTIesExportSim" Val="41"/>
|
||||||
<Option Name="WTVcsExportSim" Val="40"/>
|
<Option Name="WTVcsExportSim" Val="41"/>
|
||||||
<Option Name="WTRivieraExportSim" Val="40"/>
|
<Option Name="WTRivieraExportSim" Val="41"/>
|
||||||
<Option Name="WTActivehdlExportSim" Val="40"/>
|
<Option Name="WTActivehdlExportSim" Val="41"/>
|
||||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
<Option Name="XSimRadix" Val="hex"/>
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
@@ -607,9 +607,7 @@
|
|||||||
</Run>
|
</Run>
|
||||||
<Run Id="ant_clk_gen_stg1_synth_1" Type="Ft3:Synth" SrcSet="ant_clk_gen_stg1" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ant_clk_gen_stg1_synth_1" IncludeInArchive="true">
|
<Run Id="ant_clk_gen_stg1_synth_1" Type="Ft3:Synth" SrcSet="ant_clk_gen_stg1" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ant_clk_gen_stg1_synth_1" IncludeInArchive="true">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||||
<Desc>Vivado Synthesis Defaults</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="synth_design"/>
|
<Step Id="synth_design"/>
|
||||||
</Strategy>
|
</Strategy>
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
@@ -618,9 +616,7 @@
|
|||||||
</Run>
|
</Run>
|
||||||
<Run Id="ant_clk_gen_stg2_synth_1" Type="Ft3:Synth" SrcSet="ant_clk_gen_stg2" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ant_clk_gen_stg2_synth_1" IncludeInArchive="true">
|
<Run Id="ant_clk_gen_stg2_synth_1" Type="Ft3:Synth" SrcSet="ant_clk_gen_stg2" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ant_clk_gen_stg2_synth_1" IncludeInArchive="true">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||||
<Desc>Vivado Synthesis Defaults</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="synth_design"/>
|
<Step Id="synth_design"/>
|
||||||
</Strategy>
|
</Strategy>
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
@@ -869,9 +865,7 @@
|
|||||||
</Run>
|
</Run>
|
||||||
<Run Id="ant_clk_gen_stg1_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ant_clk_gen_stg1_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
<Run Id="ant_clk_gen_stg1_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ant_clk_gen_stg1_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||||
<Desc>Default settings for Implementation.</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="init_design"/>
|
<Step Id="init_design"/>
|
||||||
<Step Id="opt_design"/>
|
<Step Id="opt_design"/>
|
||||||
<Step Id="power_opt_design"/>
|
<Step Id="power_opt_design"/>
|
||||||
@@ -887,9 +881,7 @@
|
|||||||
</Run>
|
</Run>
|
||||||
<Run Id="ant_clk_gen_stg2_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ant_clk_gen_stg2_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
<Run Id="ant_clk_gen_stg2_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ant_clk_gen_stg2_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||||
<Desc>Default settings for Implementation.</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="init_design"/>
|
<Step Id="init_design"/>
|
||||||
<Step Id="opt_design"/>
|
<Step Id="opt_design"/>
|
||||||
<Step Id="power_opt_design"/>
|
<Step Id="power_opt_design"/>
|
||||||
|
|||||||
Binary file not shown.
@@ -3,7 +3,7 @@
|
|||||||
#
|
#
|
||||||
# project.tcl: Tcl script for re-creating project 'project'
|
# project.tcl: Tcl script for re-creating project 'project'
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Thu Mar 30 17:07:25 CST 2023
|
# Generated by Vivado on Sat Apr 01 15:36:09 CST 2023
|
||||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||||
#
|
#
|
||||||
# This file contains the Vivado Tcl commands for re-creating the project to the state*
|
# This file contains the Vivado Tcl commands for re-creating the project to the state*
|
||||||
@@ -199,7 +199,6 @@ set_property -name "webtalk.modelsim_export_sim" -value "22" -objects $obj
|
|||||||
set_property -name "webtalk.questa_export_sim" -value "22" -objects $obj
|
set_property -name "webtalk.questa_export_sim" -value "22" -objects $obj
|
||||||
set_property -name "webtalk.riviera_export_sim" -value "22" -objects $obj
|
set_property -name "webtalk.riviera_export_sim" -value "22" -objects $obj
|
||||||
set_property -name "webtalk.vcs_export_sim" -value "22" -objects $obj
|
set_property -name "webtalk.vcs_export_sim" -value "22" -objects $obj
|
||||||
set_property -name "webtalk.xcelium_export_sim" -value "22" -objects $obj
|
|
||||||
set_property -name "webtalk.xsim_export_sim" -value "22" -objects $obj
|
set_property -name "webtalk.xsim_export_sim" -value "22" -objects $obj
|
||||||
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
|
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
|
||||||
|
|
||||||
|
|||||||
Binary file not shown.
Binary file not shown.
Reference in New Issue
Block a user