Archived
fix dl814_k7_cmos_1t2r sdk typo, add dl814_k7_cmos_1t1r
This commit is contained in:
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################################################################################
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########################### Single Project Specific ############################
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################################################################################
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# ------------------------------------------------------------------------------
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# ------------------------------ Vivado Specific -------------------------------
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# ------------------------------------------------------------------------------
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# exclude everything in project directory
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project/**
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# include hardware manager projects and sources
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# 1. include `.hw` directory
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# 2. include everything in `.hw` directory
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!project/*.hw/
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!project/*.hw/**
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# include design run results
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# 1. include `*.runs` directory
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# 2. exclude everything in `.runs` directory
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# 3. include `.impl_*` directory
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# 4. include `*.bit` file in `.impl_*` directory
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# 5. include `*.ltx` file in `.impl_*` directory
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!/project/*.runs/
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/project/*.runs/**
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!/project/*.runs/impl_*/
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!/project/*.runs/impl_*/*.bit
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!/project/*.runs/impl_*/*.ltx
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# ------------------------------------------------------------------------------
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# -------------------------------- SDK Specific --------------------------------
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# ------------------------------------------------------------------------------
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# include sdk directory and everything in it
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!/project/*.sdk/
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!/project/*.sdk/**
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/project/*.sdk/**.log
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# exclude some obscure hidden SDK folders
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/project/*.sdk/.metadata/
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/project/*.sdk/.sdk/
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/project/*.sdk/RemoteSystemsTempFiles/
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/project/*.sdk/webtalk/
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# hw_platform: exclude the entire hw_platform folder, as everything can be
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# generated from the .hdf file. Make sure to include the bitstream in the .hdf
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# file when exporting from Vivado!
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/project/*.sdk/*_hw_platform_*/
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# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
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# Makefile, ps lib files are regenerated automatically
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/project/*.sdk/*_bsp/*
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!/project/*.sdk/*_bsp/*.cproject
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!/project/*.sdk/*_bsp/*.project
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!/project/*.sdk/*_bsp/*.sdkproject
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!/project/*.sdk/*_bsp/system.mss
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!/project/*.sdk/*_bsp/Makefile
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# Application: ignored file patterns, exclude Debug & Release folders
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/project/*.sdk/**/*.o
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/project/*.sdk/**/*.d
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/project/*.sdk/**/*.a
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/project/*.sdk/*/Debug/
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/project/*.sdk/*/Release/
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################################################################################
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# ############################ Multi Project Specific ############################
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# ################################################################################
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# # ------------------------------------------------------------------------------
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# # ------------------------------ Vivado Specific -------------------------------
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# # ------------------------------------------------------------------------------
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# # exclude everything in project directory expect for top level directory
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# project/**
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# !/project/*/
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# # include hardware manager projects and sources
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# # 1. include `.hw` directory
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# # 2. include everything in `.hw` directory
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# !project/*/*.hw/
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# !project/*/*.hw/**
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# # include design run results
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# # 1. include `*.runs` directory
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# # 2. exclude everything in `.runs` directory
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# # 3. include `.impl_*` directory
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# # 4. include `*.bit` file in `.impl_*` directory
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# # 5. include `*.ltx` file in `.impl_*` directory
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# !/project/*/*.runs/
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# /project/*/*.runs/**
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# !/project/*/*.runs/impl_*/
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# !/project/*/*.runs/impl_*/*.bit
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# !/project/*/*.runs/impl_*/*.ltx
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# # ------------------------------------------------------------------------------
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# # -------------------------------- SDK Specific --------------------------------
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# # ------------------------------------------------------------------------------
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# # include sdk directory and everything in it
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# !/project/*/*.sdk/
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# !/project/*/*.sdk/**
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# /project/*/*.sdk/**.log
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# # exclude some obscure hidden SDK folders
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# /project/*/*.sdk/.metadata/
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# /project/*/*.sdk/.sdk/
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# /project/*/*.sdk/RemoteSystemsTempFiles/
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# /project/*/*.sdk/webtalk/
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# # hw_platform: exclude the entire hw_platform folder, as everything can be
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# # generated from the .hdf file. Make sure to include the bitstream in the .hdf
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# # file when exporting from Vivado!
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# /project/*/*.sdk/*_hw_platform_*/
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# # BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
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# # Makefile, ps lib files are regenerated automatically
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# /project/*/*.sdk/*_bsp/*
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# !/project/*/*.sdk/*_bsp/*.cproject
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# !/project/*/*.sdk/*_bsp/*.project
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# !/project/*/*.sdk/*_bsp/*.sdkproject
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# !/project/*/*.sdk/*_bsp/system.mss
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# !/project/*/*.sdk/*_bsp/Makefile
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# # Application: ignored file patterns, exclude Debug & Release folders
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# /project/*/*.sdk/**/*.o
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# /project/*/*.sdk/**/*.d
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# /project/*/*.sdk/**/*.a
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# /project/*/*.sdk/*/Debug/
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# /project/*/*.sdk/*/Release/
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+220
@@ -0,0 +1,220 @@
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# smq7k410t_b9361
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## Timing Assertions Section
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## Physical Constraints Section
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# Clocks
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set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports clk_25m ] ;# CLK_25M
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set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 } [get_ports clk_250m_p ] ;# CLK_250M_P
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set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# B9361_1_CLK_OUT
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B9361_2_CLK_OUT
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# HMC7044-1 Interface
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set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_clk ] ;# GM4526C_SPI_SCLK
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_csn ] ;# GM4526C_SPI_CSB
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set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_mosi ] ;# GM4526C_SPI_SDIO
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set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_miso ] ;# GM4526C_SPI_SDO
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set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports ad9516_refmon ] ;# GM4526C_REFMON
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set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS33} [get_ports ad9516_ld ] ;# GM4526C_LD
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set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS33} [get_ports ad9516_status ] ;# GM4526C_STATUS
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set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports ad9516_pd_b ] ;# GM4526C_PDB
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set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports ad9516_reset_b ] ;# GM4526C_RESETB
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set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33} [get_ports ad9516_sync_b ] ;# GM4526C_SYNCB
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# AD9361-1 Interface
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set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# B9361_1_DATA_CLK
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set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# B9361_1_RX_FRAME
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set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# B9361_1_P0_00_TX0_N
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set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# B9361_1_P0_01_TX0_P
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set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# B9361_1_P0_02_TX1_N
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set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# B9361_1_P0_03_TX1_P
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set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# B9361_1_P0_04_TX2_N
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set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# B9361_1_P0_05_TX2_P
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set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# B9361_1_P0_06_TX3_N
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set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# B9361_1_P0_07_TX3_P
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set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# B9361_1_P0_08_TX4_N
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set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# B9361_1_P0_09_TX4_P
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set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# B9361_1_P0_10_TX5_N
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set_property -dict {PACKAGE_PIN G23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# B9361_1_P0_11_TX5_P
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set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# B9361_1_FB_CLK
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set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# B9361_1_TX_FRAME
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set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# B9361_1_P1_00_RX0_N
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set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# B9361_1_P1_01_RX0_P
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set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# B9361_1_P1_02_RX1_N
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set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# B9361_1_P1_03_RX1_P
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set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# B9361_1_P1_04_RX2_N
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set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# B9361_1_P1_05_RX2_P
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set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# B9361_1_P1_06_RX3_N
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set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# B9361_1_P1_07_RX3_P
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set_property -dict {PACKAGE_PIN F28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# B9361_1_P1_08_RX4_N
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set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# B9361_1_P1_09_RX4_P
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set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# B9361_1_P1_10_RX5_N
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set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# B9361_1_P1_11_RX5_P
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set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# B9361_1_SPI_CLK
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set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# B9361_1_SPI_ENB
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set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# B9361_1_SPI_DI
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set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# B9361_1_SPI_DO
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set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# B9361_1_RESETB
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set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# B9361_1_EN_AGC
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set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# B9361_1_ENABLE
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set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# B9361_1_TXNRX
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# B9361_1_CTRL_IN0
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set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# B9361_1_CTRL_IN1
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set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# B9361_1_CTRL_IN2
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set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# B9361_1_CTRL_IN3
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set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# B9361_1_CTRL_OUT0
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set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# B9361_1_CTRL_OUT1
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set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# B9361_1_CTRL_OUT2
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set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# B9361_1_CTRL_OUT3
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set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# B9361_1_CTRL_OUT4
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set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# B9361_1_CTRL_OUT5
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set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# B9361_1_CTRL_OUT6
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set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# B9361_1_CTRL_OUT7
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set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports ad9361_sync ] ;# B9361_SYNC
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# AD9361-2 Interface
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set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B9361_2_DATA_CLK
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set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B9361_2_RX_FRAME
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set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B9361_2_P0_00_TX0_N
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set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B9361_2_P0_01_TX0_P
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set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B9361_2_P0_02_TX1_N
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set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B9361_2_P0_03_TX1_P
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set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B9361_2_P0_04_TX2_N
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set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B9361_2_P0_05_TX2_P
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set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B9361_2_P0_06_TX3_N
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set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B9361_2_P0_07_TX3_P
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B9361_2_P0_08_TX4_N
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set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B9361_2_P0_09_TX4_P
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set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B9361_2_P0_10_TX5_N
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set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B9361_2_P0_11_TX5_P
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set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B9361_2_FB_CLK
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set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B9361_2_TX_FRAME
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set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B9361_2_P1_00_RX0_N
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set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B9361_2_P1_01_RX0_P
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set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B9361_2_P1_02_RX1_N
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set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B9361_2_P1_03_RX1_P
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set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B9361_2_P1_04_RX2_N
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set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B9361_2_P1_05_RX2_P
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set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B9361_2_P1_06_RX3_N
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set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B9361_2_P1_07_RX3_P
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set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B9361_2_P1_08_RX4_N
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set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B9361_2_P1_09_RX4_P
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set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B9361_2_P1_10_RX5_N
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set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B9361_2_P1_11_RX5_P
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set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B9361_2_SPI_CLK
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set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B9361_2_SPI_ENB
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set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B9361_2_SPI_DI
|
||||
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B9361_2_SPI_DO
|
||||
|
||||
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B9361_2_RESETB
|
||||
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B9361_2_EN_AGC
|
||||
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B9361_2_ENABLE
|
||||
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B9361_2_TXNRX
|
||||
|
||||
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B9361_2_CTRL_IN0
|
||||
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B9361_2_CTRL_IN1
|
||||
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B9361_2_CTRL_IN2
|
||||
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B9361_2_CTRL_IN3
|
||||
|
||||
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B9361_2_CTRL_OUT0
|
||||
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B9361_2_CTRL_OUT1
|
||||
set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B9361_2_CTRL_OUT2
|
||||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B9361_2_CTRL_OUT3
|
||||
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B9361_2_CTRL_OUT4
|
||||
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B9361_2_CTRL_OUT5
|
||||
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B9361_2_CTRL_OUT6
|
||||
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B9361_2_CTRL_OUT7
|
||||
|
||||
# Phased-Array Control
|
||||
set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVTTL } [get_ports ant_cin ] ;# ANT_CIN0
|
||||
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVTTL } [get_ports ant_din0 ] ;# ANT_DIN0
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVTTL } [get_ports ant_din1 ] ;# ANT_DIN1
|
||||
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVTTL } [get_ports ant_cout ] ;# ANT_COUT0
|
||||
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVTTL } [get_ports ant_dout0 ] ;# ANT_DOUT0
|
||||
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVTTL } [get_ports ant_dout1 ] ;# ANT_DOUT1
|
||||
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR_IN
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY_IN
|
||||
|
||||
# RF Synthesizer Control
|
||||
set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVTTL } [get_ports rf_standby ] ;# RF_STANDBY
|
||||
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVTTL } [get_ports rf_sw_pll ] ;# RF_SW_PLL
|
||||
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVTTL } [get_ports rf_t ] ;# RF_T
|
||||
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVTTL } [get_ports rf_r ] ;# RF_R
|
||||
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVTTL } [get_ports rf_sw_bpf ] ;# RF_SW_BPF
|
||||
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVTTL } [get_ports rf_sclk1 ] ;# RF_SCLK1
|
||||
set_property -dict {PACKAGE_PIN AA26 IOSTANDARD LVTTL } [get_ports rf_sdio1 ] ;# RF_SDIO1
|
||||
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVTTL } [get_ports rf_cs1 ] ;# RF_CS1
|
||||
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVTTL } [get_ports rf_ld1 ] ;# RF_LD1
|
||||
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVTTL } [get_ports rf_sclk2 ] ;# RF_SCLK2
|
||||
set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVTTL } [get_ports rf_sdio2 ] ;# RF_SDIO2
|
||||
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports rf_cs2 ] ;# RF_CS2
|
||||
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports rf_ld2 ] ;# RF_LD2
|
||||
set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVTTL } [get_ports rf_sclk3 ] ;# RF_SCLK3
|
||||
set_property -dict {PACKAGE_PIN AE29 IOSTANDARD LVTTL } [get_ports rf_sdio3 ] ;# RF_SDIO3
|
||||
set_property -dict {PACKAGE_PIN AB28 IOSTANDARD LVTTL } [get_ports rf_cs3 ] ;# RF_CS3
|
||||
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports rf_ld3 ] ;# RF_LD3
|
||||
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVTTL } [get_ports rf_tmgc_16 ] ;# RF_TMGC_16
|
||||
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVTTL } [get_ports rf_tmgc_8 ] ;# RF_TMGC_8
|
||||
set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVTTL } [get_ports rf_tmgc_4 ] ;# RF_TMGC_4
|
||||
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVTTL } [get_ports rf_tmgc_2 ] ;# RF_TMGC_2
|
||||
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVTTL } [get_ports rf_tmgc_1 ] ;# RF_TMGC_1
|
||||
set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVTTL } [get_ports rf_rmgc_16 ] ;# RF_RMGC_16
|
||||
set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVTTL } [get_ports rf_rmgc_8 ] ;# RF_RMGC_8
|
||||
set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVTTL } [get_ports rf_rmgc_4 ] ;# RF_RMGC_4
|
||||
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVTTL } [get_ports rf_rmgc_2 ] ;# RF_RMGC_2
|
||||
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVTTL } [get_ports rf_rmgc_1 ] ;# RF_RMGC_1
|
||||
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVTTL } [get_ports rf_enable ] ;# RF_ENABLE
|
||||
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVTTL } [get_ports rf_sc ] ;# RF_SC
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVTTL } [get_ports rf_sd ] ;# RF_SD
|
||||
set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVTTL } [get_ports rf_endsyn ] ;# RF_END_SYN
|
||||
set_property -dict {PACKAGE_PIN W27 IOSTANDARD LVTTL } [get_ports rf_sdout ] ;# RF_SDOUT
|
||||
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVTTL } [get_ports rf_dq_wd ] ;# RF_DQ_WD
|
||||
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVTTL } [get_ports rf_sw_rx ] ;# RF_SW_RX
|
||||
|
||||
# LVDS for Time Synchronization
|
||||
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS33} [get_ports lvds_in_1 ] ;# LVDS_IN1
|
||||
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports lvds_out_1 ] ;# LVDS_OUT1
|
||||
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports lvds_in_2 ] ;# LVDS_IN2
|
||||
set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS33} [get_ports lvds_out_2 ] ;# LVDS_OUT2
|
||||
|
||||
# Debug IO
|
||||
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART_1_TXD
|
||||
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART_1_RXD
|
||||
set_property -dict {PACKAGE_PIN U23 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART_2_TXD
|
||||
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART_2_RXD
|
||||
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART_3_TXD
|
||||
set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART_3_RXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN V25 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# DEBUG_IO_1
|
||||
set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# DEBUG_IO_2
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3
|
||||
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4
|
||||
set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5
|
||||
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6
|
||||
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7
|
||||
set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports debug_io_8 ] ;# DEBUG_IO_8
|
||||
|
||||
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25 } [get_ports debug_io_00_p ] ;# DEBUG_IO_00_P
|
||||
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVDS_25 } [get_ports debug_io_01_p ] ;# DEBUG_IO_01_P
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25 } [get_ports debug_io_02_p ] ;# DEBUG_IO_02_P
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25 } [get_ports debug_io_03_p ] ;# DEBUG_IO_03_P
|
||||
set_property -dict {PACKAGE_PIN AC20 IOSTANDARD LVDS_25 } [get_ports debug_io_04_p ] ;# DEBUG_IO_04_P
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 } [get_ports debug_io_05_p ] ;# DEBUG_IO_05_P
|
||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS_25 } [get_ports debug_io_06_p ] ;# DEBUG_IO_06_P
|
||||
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVDS_25 } [get_ports debug_io_07_p ] ;# DEBUG_IO_07_P
|
||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25 } [get_ports debug_io_08_p ] ;# DEBUG_IO_08_P
|
||||
|
||||
# FLASH
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1 @@
|
||||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
+99
@@ -0,0 +1,99 @@
|
||||
|
||||
// file: ad9361_clk_gen.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____48.000______0.000______50.0______176.382____161.578
|
||||
// clk_out2____96.000______0.000______50.0______148.620____161.578
|
||||
// clk_out3___144.000______0.000______50.0______137.385____161.578
|
||||
// clk_out4___192.000______0.000______50.0______131.258____161.578
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________48____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "ad9361_clk_gen,clk_wiz_v6_0_3_0_0,{component_name=ad9361_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=20.833,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module ad9361_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
// Clock in ports
|
||||
input clk_in1
|
||||
);
|
||||
|
||||
ad9361_clk_gen_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
.clk_out2(clk_out2),
|
||||
.clk_out3(clk_out3),
|
||||
.clk_out4(clk_out4),
|
||||
// Status and control signals
|
||||
.locked(locked),
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
+85
@@ -0,0 +1,85 @@
|
||||
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____48.000______0.000______50.0______176.382____161.578
|
||||
// clk_out2____96.000______0.000______50.0______148.620____161.578
|
||||
// clk_out3___144.000______0.000______50.0______137.385____161.578
|
||||
// clk_out4___192.000______0.000______50.0______131.258____161.578
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________48____________0.010
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ad9361_clk_gen instance_name
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1), // output clk_out1
|
||||
.clk_out2(clk_out2), // output clk_out2
|
||||
.clk_out3(clk_out3), // output clk_out3
|
||||
.clk_out4(clk_out4), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked(locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)); // input clk_in1
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
+228
@@ -0,0 +1,228 @@
|
||||
|
||||
// file: ad9361_clk_gen.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____48.000______0.000______50.0______176.382____161.578
|
||||
// clk_out2____96.000______0.000______50.0______148.620____161.578
|
||||
// clk_out3___144.000______0.000______50.0______137.385____161.578
|
||||
// clk_out4___192.000______0.000______50.0______131.258____161.578
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________48____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module ad9361_clk_gen_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
input clk_in1
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_ad9361_clk_gen;
|
||||
wire clk_in2_ad9361_clk_gen;
|
||||
IBUF clkin1_ibufg
|
||||
(.O (clk_in1_ad9361_clk_gen),
|
||||
.I (clk_in1));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_ad9361_clk_gen;
|
||||
wire clk_out2_ad9361_clk_gen;
|
||||
wire clk_out3_ad9361_clk_gen;
|
||||
wire clk_out4_ad9361_clk_gen;
|
||||
wire clk_out5_ad9361_clk_gen;
|
||||
wire clk_out6_ad9361_clk_gen;
|
||||
wire clk_out7_ad9361_clk_gen;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_ad9361_clk_gen;
|
||||
wire clkfbout_buf_ad9361_clk_gen;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT_F (24.000),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (24.000),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT1_DIVIDE (12),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT2_DIVIDE (8),
|
||||
.CLKOUT2_PHASE (0.000),
|
||||
.CLKOUT2_DUTY_CYCLE (0.500),
|
||||
.CLKOUT2_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT3_DIVIDE (6),
|
||||
.CLKOUT3_PHASE (0.000),
|
||||
.CLKOUT3_DUTY_CYCLE (0.500),
|
||||
.CLKOUT3_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (20.833))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_ad9361_clk_gen),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (clk_out1_ad9361_clk_gen),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clk_out2_ad9361_clk_gen),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clk_out3_ad9361_clk_gen),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clk_out4_ad9361_clk_gen),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_ad9361_clk_gen),
|
||||
.CLKIN1 (clk_in1_ad9361_clk_gen),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (1'b0));
|
||||
|
||||
assign locked = locked_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_ad9361_clk_gen),
|
||||
.I (clkfbout_ad9361_clk_gen));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_ad9361_clk_gen));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (clk_out2),
|
||||
.I (clk_out2_ad9361_clk_gen));
|
||||
|
||||
BUFG clkout3_buf
|
||||
(.O (clk_out3),
|
||||
.I (clk_out3_ad9361_clk_gen));
|
||||
|
||||
BUFG clkout4_buf
|
||||
(.O (clk_out4),
|
||||
.I (clk_out4_ad9361_clk_gen));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+271
@@ -0,0 +1,271 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 6 12:05:54 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cmos_1t1r/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/ad9361_clk_gen_sim_netlist.v
|
||||
// Design : ad9361_clk_gen
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* NotValidForBitStream *)
|
||||
module ad9361_clk_gen
|
||||
(clk_out1,
|
||||
clk_out2,
|
||||
clk_out3,
|
||||
clk_out4,
|
||||
locked,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
output clk_out2;
|
||||
output clk_out3;
|
||||
output clk_out4;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
(* IBUF_LOW_PWR *) wire clk_in1;
|
||||
wire clk_out1;
|
||||
wire clk_out2;
|
||||
wire clk_out3;
|
||||
wire clk_out4;
|
||||
wire locked;
|
||||
|
||||
ad9361_clk_gen_ad9361_clk_gen_clk_wiz inst
|
||||
(.clk_in1(clk_in1),
|
||||
.clk_out1(clk_out1),
|
||||
.clk_out2(clk_out2),
|
||||
.clk_out3(clk_out3),
|
||||
.clk_out4(clk_out4),
|
||||
.locked(locked));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "ad9361_clk_gen_clk_wiz" *)
|
||||
module ad9361_clk_gen_ad9361_clk_gen_clk_wiz
|
||||
(clk_out1,
|
||||
clk_out2,
|
||||
clk_out3,
|
||||
clk_out4,
|
||||
locked,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
output clk_out2;
|
||||
output clk_out3;
|
||||
output clk_out4;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
wire clk_in1;
|
||||
wire clk_in1_ad9361_clk_gen;
|
||||
wire clk_out1;
|
||||
wire clk_out1_ad9361_clk_gen;
|
||||
wire clk_out2;
|
||||
wire clk_out2_ad9361_clk_gen;
|
||||
wire clk_out3;
|
||||
wire clk_out3_ad9361_clk_gen;
|
||||
wire clk_out4;
|
||||
wire clk_out4_ad9361_clk_gen;
|
||||
wire clkfbout_ad9361_clk_gen;
|
||||
wire clkfbout_buf_ad9361_clk_gen;
|
||||
wire locked;
|
||||
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
|
||||
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkf_buf
|
||||
(.I(clkfbout_ad9361_clk_gen),
|
||||
.O(clkfbout_buf_ad9361_clk_gen));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF #(
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
clkin1_ibufg
|
||||
(.I(clk_in1),
|
||||
.O(clk_in1_ad9361_clk_gen));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout1_buf
|
||||
(.I(clk_out1_ad9361_clk_gen),
|
||||
.O(clk_out1));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout2_buf
|
||||
(.I(clk_out2_ad9361_clk_gen),
|
||||
.O(clk_out2));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout3_buf
|
||||
(.I(clk_out3_ad9361_clk_gen),
|
||||
.O(clk_out3));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout4_buf
|
||||
(.I(clk_out4_ad9361_clk_gen),
|
||||
.O(clk_out4));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
MMCME2_ADV #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKFBOUT_MULT_F(24.000000),
|
||||
.CLKFBOUT_PHASE(0.000000),
|
||||
.CLKFBOUT_USE_FINE_PS("FALSE"),
|
||||
.CLKIN1_PERIOD(20.833000),
|
||||
.CLKIN2_PERIOD(0.000000),
|
||||
.CLKOUT0_DIVIDE_F(24.000000),
|
||||
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT0_PHASE(0.000000),
|
||||
.CLKOUT0_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT1_DIVIDE(12),
|
||||
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT1_PHASE(0.000000),
|
||||
.CLKOUT1_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT2_DIVIDE(8),
|
||||
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT2_PHASE(0.000000),
|
||||
.CLKOUT2_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT3_DIVIDE(6),
|
||||
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT3_PHASE(0.000000),
|
||||
.CLKOUT3_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT4_PHASE(0.000000),
|
||||
.CLKOUT4_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT5_PHASE(0.000000),
|
||||
.CLKOUT5_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT6_PHASE(0.000000),
|
||||
.CLKOUT6_USE_FINE_PS("FALSE"),
|
||||
.COMPENSATION("ZHOLD"),
|
||||
.DIVCLK_DIVIDE(1),
|
||||
.IS_CLKINSEL_INVERTED(1'b0),
|
||||
.IS_PSEN_INVERTED(1'b0),
|
||||
.IS_PSINCDEC_INVERTED(1'b0),
|
||||
.IS_PWRDWN_INVERTED(1'b0),
|
||||
.IS_RST_INVERTED(1'b0),
|
||||
.REF_JITTER1(0.010000),
|
||||
.REF_JITTER2(0.010000),
|
||||
.SS_EN("FALSE"),
|
||||
.SS_MODE("CENTER_HIGH"),
|
||||
.SS_MOD_PERIOD(10000),
|
||||
.STARTUP_WAIT("FALSE"))
|
||||
mmcm_adv_inst
|
||||
(.CLKFBIN(clkfbout_buf_ad9361_clk_gen),
|
||||
.CLKFBOUT(clkfbout_ad9361_clk_gen),
|
||||
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
|
||||
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
|
||||
.CLKIN1(clk_in1_ad9361_clk_gen),
|
||||
.CLKIN2(1'b0),
|
||||
.CLKINSEL(1'b1),
|
||||
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
|
||||
.CLKOUT0(clk_out1_ad9361_clk_gen),
|
||||
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
|
||||
.CLKOUT1(clk_out2_ad9361_clk_gen),
|
||||
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
|
||||
.CLKOUT2(clk_out3_ad9361_clk_gen),
|
||||
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
|
||||
.CLKOUT3(clk_out4_ad9361_clk_gen),
|
||||
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
|
||||
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
|
||||
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
|
||||
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
|
||||
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DCLK(1'b0),
|
||||
.DEN(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
|
||||
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
|
||||
.DWE(1'b0),
|
||||
.LOCKED(locked),
|
||||
.PSCLK(1'b0),
|
||||
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
|
||||
.PSEN(1'b0),
|
||||
.PSINCDEC(1'b0),
|
||||
.PWRDWN(1'b0),
|
||||
.RST(1'b0));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+214
@@ -0,0 +1,214 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 6 12:05:54 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cmos_1t1r/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/ad9361_clk_gen_sim_netlist.vhdl
|
||||
-- Design : ad9361_clk_gen
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity ad9361_clk_gen_ad9361_clk_gen_clk_wiz is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
clk_out2 : out STD_LOGIC;
|
||||
clk_out3 : out STD_LOGIC;
|
||||
clk_out4 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of ad9361_clk_gen_ad9361_clk_gen_clk_wiz : entity is "ad9361_clk_gen_clk_wiz";
|
||||
end ad9361_clk_gen_ad9361_clk_gen_clk_wiz;
|
||||
|
||||
architecture STRUCTURE of ad9361_clk_gen_ad9361_clk_gen_clk_wiz is
|
||||
signal clk_in1_ad9361_clk_gen : STD_LOGIC;
|
||||
signal clk_out1_ad9361_clk_gen : STD_LOGIC;
|
||||
signal clk_out2_ad9361_clk_gen : STD_LOGIC;
|
||||
signal clk_out3_ad9361_clk_gen : STD_LOGIC;
|
||||
signal clk_out4_ad9361_clk_gen : STD_LOGIC;
|
||||
signal clkfbout_ad9361_clk_gen : STD_LOGIC;
|
||||
signal clkfbout_buf_ad9361_clk_gen : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
|
||||
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkout4_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
|
||||
begin
|
||||
clkf_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clkfbout_ad9361_clk_gen,
|
||||
O => clkfbout_buf_ad9361_clk_gen
|
||||
);
|
||||
clkin1_ibufg: unisim.vcomponents.IBUF
|
||||
generic map(
|
||||
IOSTANDARD => "DEFAULT"
|
||||
)
|
||||
port map (
|
||||
I => clk_in1,
|
||||
O => clk_in1_ad9361_clk_gen
|
||||
);
|
||||
clkout1_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out1_ad9361_clk_gen,
|
||||
O => clk_out1
|
||||
);
|
||||
clkout2_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out2_ad9361_clk_gen,
|
||||
O => clk_out2
|
||||
);
|
||||
clkout3_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out3_ad9361_clk_gen,
|
||||
O => clk_out3
|
||||
);
|
||||
clkout4_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out4_ad9361_clk_gen,
|
||||
O => clk_out4
|
||||
);
|
||||
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
|
||||
generic map(
|
||||
BANDWIDTH => "OPTIMIZED",
|
||||
CLKFBOUT_MULT_F => 24.000000,
|
||||
CLKFBOUT_PHASE => 0.000000,
|
||||
CLKFBOUT_USE_FINE_PS => false,
|
||||
CLKIN1_PERIOD => 20.833000,
|
||||
CLKIN2_PERIOD => 0.000000,
|
||||
CLKOUT0_DIVIDE_F => 24.000000,
|
||||
CLKOUT0_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT0_PHASE => 0.000000,
|
||||
CLKOUT0_USE_FINE_PS => false,
|
||||
CLKOUT1_DIVIDE => 12,
|
||||
CLKOUT1_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT1_PHASE => 0.000000,
|
||||
CLKOUT1_USE_FINE_PS => false,
|
||||
CLKOUT2_DIVIDE => 8,
|
||||
CLKOUT2_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT2_PHASE => 0.000000,
|
||||
CLKOUT2_USE_FINE_PS => false,
|
||||
CLKOUT3_DIVIDE => 6,
|
||||
CLKOUT3_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT3_PHASE => 0.000000,
|
||||
CLKOUT3_USE_FINE_PS => false,
|
||||
CLKOUT4_CASCADE => false,
|
||||
CLKOUT4_DIVIDE => 1,
|
||||
CLKOUT4_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT4_PHASE => 0.000000,
|
||||
CLKOUT4_USE_FINE_PS => false,
|
||||
CLKOUT5_DIVIDE => 1,
|
||||
CLKOUT5_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT5_PHASE => 0.000000,
|
||||
CLKOUT5_USE_FINE_PS => false,
|
||||
CLKOUT6_DIVIDE => 1,
|
||||
CLKOUT6_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT6_PHASE => 0.000000,
|
||||
CLKOUT6_USE_FINE_PS => false,
|
||||
COMPENSATION => "ZHOLD",
|
||||
DIVCLK_DIVIDE => 1,
|
||||
IS_CLKINSEL_INVERTED => '0',
|
||||
IS_PSEN_INVERTED => '0',
|
||||
IS_PSINCDEC_INVERTED => '0',
|
||||
IS_PWRDWN_INVERTED => '0',
|
||||
IS_RST_INVERTED => '0',
|
||||
REF_JITTER1 => 0.010000,
|
||||
REF_JITTER2 => 0.010000,
|
||||
SS_EN => "FALSE",
|
||||
SS_MODE => "CENTER_HIGH",
|
||||
SS_MOD_PERIOD => 10000,
|
||||
STARTUP_WAIT => false
|
||||
)
|
||||
port map (
|
||||
CLKFBIN => clkfbout_buf_ad9361_clk_gen,
|
||||
CLKFBOUT => clkfbout_ad9361_clk_gen,
|
||||
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
|
||||
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
|
||||
CLKIN1 => clk_in1_ad9361_clk_gen,
|
||||
CLKIN2 => '0',
|
||||
CLKINSEL => '1',
|
||||
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
|
||||
CLKOUT0 => clk_out1_ad9361_clk_gen,
|
||||
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
|
||||
CLKOUT1 => clk_out2_ad9361_clk_gen,
|
||||
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
|
||||
CLKOUT2 => clk_out3_ad9361_clk_gen,
|
||||
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
|
||||
CLKOUT3 => clk_out4_ad9361_clk_gen,
|
||||
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
|
||||
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
|
||||
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
|
||||
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
|
||||
DADDR(6 downto 0) => B"0000000",
|
||||
DCLK => '0',
|
||||
DEN => '0',
|
||||
DI(15 downto 0) => B"0000000000000000",
|
||||
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
|
||||
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
|
||||
DWE => '0',
|
||||
LOCKED => locked,
|
||||
PSCLK => '0',
|
||||
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
|
||||
PSEN => '0',
|
||||
PSINCDEC => '0',
|
||||
PWRDWN => '0',
|
||||
RST => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity ad9361_clk_gen is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
clk_out2 : out STD_LOGIC;
|
||||
clk_out3 : out STD_LOGIC;
|
||||
clk_out4 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of ad9361_clk_gen : entity is true;
|
||||
end ad9361_clk_gen;
|
||||
|
||||
architecture STRUCTURE of ad9361_clk_gen is
|
||||
begin
|
||||
inst: entity work.ad9361_clk_gen_ad9361_clk_gen_clk_wiz
|
||||
port map (
|
||||
clk_in1 => clk_in1,
|
||||
clk_out1 => clk_out1,
|
||||
clk_out2 => clk_out2,
|
||||
clk_out3 => clk_out3,
|
||||
clk_out4 => clk_out4,
|
||||
locked => locked
|
||||
);
|
||||
end STRUCTURE;
|
||||
+25
@@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 6 12:05:54 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cmos_1t1r/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/ad9361_clk_gen_stub.v
|
||||
// Design : ad9361_clk_gen
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module ad9361_clk_gen(clk_out1, clk_out2, clk_out3, clk_out4, locked,
|
||||
clk_in1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1" */;
|
||||
output clk_out1;
|
||||
output clk_out2;
|
||||
output clk_out3;
|
||||
output clk_out4;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
endmodule
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 6 12:05:54 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cmos_1t1r/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/ad9361_clk_gen_stub.vhdl
|
||||
-- Design : ad9361_clk_gen
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ad9361_clk_gen is
|
||||
Port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
clk_out2 : out STD_LOGIC;
|
||||
clk_out3 : out STD_LOGIC;
|
||||
clk_out4 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
|
||||
end ad9361_clk_gen;
|
||||
|
||||
architecture stub of ad9361_clk_gen is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1";
|
||||
begin
|
||||
end;
|
||||
+92
@@ -0,0 +1,92 @@
|
||||
|
||||
// file: ant_clk_gen_stg1.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____96.000______0.000______50.0______168.397____161.614
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_____________250____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "ant_clk_gen_stg1,clk_wiz_v6_0_3_0_0,{component_name=ant_clk_gen_stg1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module ant_clk_gen_stg1
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
// Clock in ports
|
||||
input clk_in1_p,
|
||||
input clk_in1_n
|
||||
);
|
||||
|
||||
ant_clk_gen_stg1_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
// Status and control signals
|
||||
.locked(locked),
|
||||
// Clock in ports
|
||||
.clk_in1_p(clk_in1_p),
|
||||
.clk_in1_n(clk_in1_n)
|
||||
);
|
||||
|
||||
endmodule
|
||||
+80
@@ -0,0 +1,80 @@
|
||||
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____96.000______0.000______50.0______168.397____161.614
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_____________250____________0.010
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ant_clk_gen_stg1 instance_name
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1), // output clk_out1
|
||||
// Status and control signals
|
||||
.locked(locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1_p(clk_in1_p), // input clk_in1_p
|
||||
.clk_in1_n(clk_in1_n)); // input clk_in1_n
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
+203
@@ -0,0 +1,203 @@
|
||||
|
||||
// file: ant_clk_gen_stg1.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____96.000______0.000______50.0______168.397____161.614
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_____________250____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module ant_clk_gen_stg1_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
input clk_in1_p,
|
||||
input clk_in1_n
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_ant_clk_gen_stg1;
|
||||
wire clk_in2_ant_clk_gen_stg1;
|
||||
IBUFDS clkin1_ibufgds
|
||||
(.O (clk_in1_ant_clk_gen_stg1),
|
||||
.I (clk_in1_p),
|
||||
.IB (clk_in1_n));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_ant_clk_gen_stg1;
|
||||
wire clk_out2_ant_clk_gen_stg1;
|
||||
wire clk_out3_ant_clk_gen_stg1;
|
||||
wire clk_out4_ant_clk_gen_stg1;
|
||||
wire clk_out5_ant_clk_gen_stg1;
|
||||
wire clk_out6_ant_clk_gen_stg1;
|
||||
wire clk_out7_ant_clk_gen_stg1;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_ant_clk_gen_stg1;
|
||||
wire clkfbout_buf_ant_clk_gen_stg1;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (5),
|
||||
.CLKFBOUT_MULT_F (18.000),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (9.375),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (4.000))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_ant_clk_gen_stg1),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (clk_out1_ant_clk_gen_stg1),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clkout1_unused),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_ant_clk_gen_stg1),
|
||||
.CLKIN1 (clk_in1_ant_clk_gen_stg1),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (1'b0));
|
||||
|
||||
assign locked = locked_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_ant_clk_gen_stg1),
|
||||
.I (clkfbout_ant_clk_gen_stg1));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_ant_clk_gen_stg1));
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+245
@@ -0,0 +1,245 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:33:33 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top ant_clk_gen_stg1 -prefix
|
||||
// ant_clk_gen_stg1_ ant_clk_gen_stg1_sim_netlist.v
|
||||
// Design : ant_clk_gen_stg1
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* NotValidForBitStream *)
|
||||
module ant_clk_gen_stg1
|
||||
(clk_out1,
|
||||
locked,
|
||||
clk_in1_p,
|
||||
clk_in1_n);
|
||||
output clk_out1;
|
||||
output locked;
|
||||
input clk_in1_p;
|
||||
input clk_in1_n;
|
||||
|
||||
(* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_n;
|
||||
(* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_p;
|
||||
wire clk_out1;
|
||||
wire locked;
|
||||
|
||||
ant_clk_gen_stg1_ant_clk_gen_stg1_clk_wiz inst
|
||||
(.clk_in1_n(clk_in1_n),
|
||||
.clk_in1_p(clk_in1_p),
|
||||
.clk_out1(clk_out1),
|
||||
.locked(locked));
|
||||
endmodule
|
||||
|
||||
module ant_clk_gen_stg1_ant_clk_gen_stg1_clk_wiz
|
||||
(clk_out1,
|
||||
locked,
|
||||
clk_in1_p,
|
||||
clk_in1_n);
|
||||
output clk_out1;
|
||||
output locked;
|
||||
input clk_in1_p;
|
||||
input clk_in1_n;
|
||||
|
||||
wire clk_in1_ant_clk_gen_stg1;
|
||||
wire clk_in1_n;
|
||||
wire clk_in1_p;
|
||||
wire clk_out1;
|
||||
wire clk_out1_ant_clk_gen_stg1;
|
||||
wire clkfbout_ant_clk_gen_stg1;
|
||||
wire clkfbout_buf_ant_clk_gen_stg1;
|
||||
wire locked;
|
||||
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
|
||||
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkf_buf
|
||||
(.I(clkfbout_ant_clk_gen_stg1),
|
||||
.O(clkfbout_buf_ant_clk_gen_stg1));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUFDS #(
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
clkin1_ibufgds
|
||||
(.I(clk_in1_p),
|
||||
.IB(clk_in1_n),
|
||||
.O(clk_in1_ant_clk_gen_stg1));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout1_buf
|
||||
(.I(clk_out1_ant_clk_gen_stg1),
|
||||
.O(clk_out1));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
MMCME2_ADV #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKFBOUT_MULT_F(18.000000),
|
||||
.CLKFBOUT_PHASE(0.000000),
|
||||
.CLKFBOUT_USE_FINE_PS("FALSE"),
|
||||
.CLKIN1_PERIOD(4.000000),
|
||||
.CLKIN2_PERIOD(0.000000),
|
||||
.CLKOUT0_DIVIDE_F(9.375000),
|
||||
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT0_PHASE(0.000000),
|
||||
.CLKOUT0_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT1_PHASE(0.000000),
|
||||
.CLKOUT1_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT2_PHASE(0.000000),
|
||||
.CLKOUT2_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT3_PHASE(0.000000),
|
||||
.CLKOUT3_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT4_PHASE(0.000000),
|
||||
.CLKOUT4_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT5_PHASE(0.000000),
|
||||
.CLKOUT5_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT6_PHASE(0.000000),
|
||||
.CLKOUT6_USE_FINE_PS("FALSE"),
|
||||
.COMPENSATION("ZHOLD"),
|
||||
.DIVCLK_DIVIDE(5),
|
||||
.IS_CLKINSEL_INVERTED(1'b0),
|
||||
.IS_PSEN_INVERTED(1'b0),
|
||||
.IS_PSINCDEC_INVERTED(1'b0),
|
||||
.IS_PWRDWN_INVERTED(1'b0),
|
||||
.IS_RST_INVERTED(1'b0),
|
||||
.REF_JITTER1(0.010000),
|
||||
.REF_JITTER2(0.010000),
|
||||
.SS_EN("FALSE"),
|
||||
.SS_MODE("CENTER_HIGH"),
|
||||
.SS_MOD_PERIOD(10000),
|
||||
.STARTUP_WAIT("FALSE"))
|
||||
mmcm_adv_inst
|
||||
(.CLKFBIN(clkfbout_buf_ant_clk_gen_stg1),
|
||||
.CLKFBOUT(clkfbout_ant_clk_gen_stg1),
|
||||
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
|
||||
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
|
||||
.CLKIN1(clk_in1_ant_clk_gen_stg1),
|
||||
.CLKIN2(1'b0),
|
||||
.CLKINSEL(1'b1),
|
||||
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
|
||||
.CLKOUT0(clk_out1_ant_clk_gen_stg1),
|
||||
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
|
||||
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
|
||||
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
|
||||
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
|
||||
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
|
||||
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
|
||||
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
|
||||
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
|
||||
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
|
||||
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
|
||||
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DCLK(1'b0),
|
||||
.DEN(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
|
||||
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
|
||||
.DWE(1'b0),
|
||||
.LOCKED(locked),
|
||||
.PSCLK(1'b0),
|
||||
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
|
||||
.PSEN(1'b0),
|
||||
.PSINCDEC(1'b0),
|
||||
.PWRDWN(1'b0),
|
||||
.RST(1'b0));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+189
@@ -0,0 +1,189 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:33:33 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top ant_clk_gen_stg1 -prefix
|
||||
-- ant_clk_gen_stg1_ ant_clk_gen_stg1_sim_netlist.vhdl
|
||||
-- Design : ant_clk_gen_stg1
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity ant_clk_gen_stg1_ant_clk_gen_stg1_clk_wiz is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1_p : in STD_LOGIC;
|
||||
clk_in1_n : in STD_LOGIC
|
||||
);
|
||||
end ant_clk_gen_stg1_ant_clk_gen_stg1_clk_wiz;
|
||||
|
||||
architecture STRUCTURE of ant_clk_gen_stg1_ant_clk_gen_stg1_clk_wiz is
|
||||
signal clk_in1_ant_clk_gen_stg1 : STD_LOGIC;
|
||||
signal clk_out1_ant_clk_gen_stg1 : STD_LOGIC;
|
||||
signal clkfbout_ant_clk_gen_stg1 : STD_LOGIC;
|
||||
signal clkfbout_buf_ant_clk_gen_stg1 : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkin1_ibufgds : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of clkin1_ibufgds : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of clkin1_ibufgds : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of clkin1_ibufgds : label is "AUTO";
|
||||
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
|
||||
begin
|
||||
clkf_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clkfbout_ant_clk_gen_stg1,
|
||||
O => clkfbout_buf_ant_clk_gen_stg1
|
||||
);
|
||||
clkin1_ibufgds: unisim.vcomponents.IBUFDS
|
||||
generic map(
|
||||
IOSTANDARD => "DEFAULT"
|
||||
)
|
||||
port map (
|
||||
I => clk_in1_p,
|
||||
IB => clk_in1_n,
|
||||
O => clk_in1_ant_clk_gen_stg1
|
||||
);
|
||||
clkout1_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out1_ant_clk_gen_stg1,
|
||||
O => clk_out1
|
||||
);
|
||||
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
|
||||
generic map(
|
||||
BANDWIDTH => "OPTIMIZED",
|
||||
CLKFBOUT_MULT_F => 18.000000,
|
||||
CLKFBOUT_PHASE => 0.000000,
|
||||
CLKFBOUT_USE_FINE_PS => false,
|
||||
CLKIN1_PERIOD => 4.000000,
|
||||
CLKIN2_PERIOD => 0.000000,
|
||||
CLKOUT0_DIVIDE_F => 9.375000,
|
||||
CLKOUT0_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT0_PHASE => 0.000000,
|
||||
CLKOUT0_USE_FINE_PS => false,
|
||||
CLKOUT1_DIVIDE => 1,
|
||||
CLKOUT1_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT1_PHASE => 0.000000,
|
||||
CLKOUT1_USE_FINE_PS => false,
|
||||
CLKOUT2_DIVIDE => 1,
|
||||
CLKOUT2_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT2_PHASE => 0.000000,
|
||||
CLKOUT2_USE_FINE_PS => false,
|
||||
CLKOUT3_DIVIDE => 1,
|
||||
CLKOUT3_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT3_PHASE => 0.000000,
|
||||
CLKOUT3_USE_FINE_PS => false,
|
||||
CLKOUT4_CASCADE => false,
|
||||
CLKOUT4_DIVIDE => 1,
|
||||
CLKOUT4_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT4_PHASE => 0.000000,
|
||||
CLKOUT4_USE_FINE_PS => false,
|
||||
CLKOUT5_DIVIDE => 1,
|
||||
CLKOUT5_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT5_PHASE => 0.000000,
|
||||
CLKOUT5_USE_FINE_PS => false,
|
||||
CLKOUT6_DIVIDE => 1,
|
||||
CLKOUT6_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT6_PHASE => 0.000000,
|
||||
CLKOUT6_USE_FINE_PS => false,
|
||||
COMPENSATION => "ZHOLD",
|
||||
DIVCLK_DIVIDE => 5,
|
||||
IS_CLKINSEL_INVERTED => '0',
|
||||
IS_PSEN_INVERTED => '0',
|
||||
IS_PSINCDEC_INVERTED => '0',
|
||||
IS_PWRDWN_INVERTED => '0',
|
||||
IS_RST_INVERTED => '0',
|
||||
REF_JITTER1 => 0.010000,
|
||||
REF_JITTER2 => 0.010000,
|
||||
SS_EN => "FALSE",
|
||||
SS_MODE => "CENTER_HIGH",
|
||||
SS_MOD_PERIOD => 10000,
|
||||
STARTUP_WAIT => false
|
||||
)
|
||||
port map (
|
||||
CLKFBIN => clkfbout_buf_ant_clk_gen_stg1,
|
||||
CLKFBOUT => clkfbout_ant_clk_gen_stg1,
|
||||
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
|
||||
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
|
||||
CLKIN1 => clk_in1_ant_clk_gen_stg1,
|
||||
CLKIN2 => '0',
|
||||
CLKINSEL => '1',
|
||||
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
|
||||
CLKOUT0 => clk_out1_ant_clk_gen_stg1,
|
||||
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
|
||||
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
|
||||
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
|
||||
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
|
||||
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
|
||||
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
|
||||
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
|
||||
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
|
||||
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
|
||||
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
|
||||
DADDR(6 downto 0) => B"0000000",
|
||||
DCLK => '0',
|
||||
DEN => '0',
|
||||
DI(15 downto 0) => B"0000000000000000",
|
||||
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
|
||||
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
|
||||
DWE => '0',
|
||||
LOCKED => locked,
|
||||
PSCLK => '0',
|
||||
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
|
||||
PSEN => '0',
|
||||
PSINCDEC => '0',
|
||||
PWRDWN => '0',
|
||||
RST => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity ant_clk_gen_stg1 is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1_p : in STD_LOGIC;
|
||||
clk_in1_n : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of ant_clk_gen_stg1 : entity is true;
|
||||
end ant_clk_gen_stg1;
|
||||
|
||||
architecture STRUCTURE of ant_clk_gen_stg1 is
|
||||
begin
|
||||
inst: entity work.ant_clk_gen_stg1_ant_clk_gen_stg1_clk_wiz
|
||||
port map (
|
||||
clk_in1_n => clk_in1_n,
|
||||
clk_in1_p => clk_in1_p,
|
||||
clk_out1 => clk_out1,
|
||||
locked => locked
|
||||
);
|
||||
end STRUCTURE;
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:33:33 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top ant_clk_gen_stg1 -prefix
|
||||
// ant_clk_gen_stg1_ ant_clk_gen_stg1_stub.v
|
||||
// Design : ant_clk_gen_stg1
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module ant_clk_gen_stg1(clk_out1, locked, clk_in1_p, clk_in1_n)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1_p,clk_in1_n" */;
|
||||
output clk_out1;
|
||||
output locked;
|
||||
input clk_in1_p;
|
||||
input clk_in1_n;
|
||||
endmodule
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:33:33 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top ant_clk_gen_stg1 -prefix
|
||||
-- ant_clk_gen_stg1_ ant_clk_gen_stg1_stub.vhdl
|
||||
-- Design : ant_clk_gen_stg1
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ant_clk_gen_stg1 is
|
||||
Port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1_p : in STD_LOGIC;
|
||||
clk_in1_n : in STD_LOGIC
|
||||
);
|
||||
|
||||
end ant_clk_gen_stg1;
|
||||
|
||||
architecture stub of ant_clk_gen_stg1 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1_p,clk_in1_n";
|
||||
begin
|
||||
end;
|
||||
+99
@@ -0,0 +1,99 @@
|
||||
|
||||
// file: ant_clk_gen_stg2.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____96.000______0.000______50.0______136.435____101.715
|
||||
// clk_out2____48.000______0.000______50.0______158.351____101.715
|
||||
// clk_out3____32.000______0.000______50.0______172.426____101.715
|
||||
// clk_out4____19.200______0.000______50.0______190.665____101.715
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________96____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "ant_clk_gen_stg2,clk_wiz_v6_0_3_0_0,{component_name=ant_clk_gen_stg2,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.417,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module ant_clk_gen_stg2
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
// Clock in ports
|
||||
input clk_in1
|
||||
);
|
||||
|
||||
ant_clk_gen_stg2_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
.clk_out2(clk_out2),
|
||||
.clk_out3(clk_out3),
|
||||
.clk_out4(clk_out4),
|
||||
// Status and control signals
|
||||
.locked(locked),
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
+85
@@ -0,0 +1,85 @@
|
||||
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____96.000______0.000______50.0______136.435____101.715
|
||||
// clk_out2____48.000______0.000______50.0______158.351____101.715
|
||||
// clk_out3____32.000______0.000______50.0______172.426____101.715
|
||||
// clk_out4____19.200______0.000______50.0______190.665____101.715
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________96____________0.010
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ant_clk_gen_stg2 instance_name
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1), // output clk_out1
|
||||
.clk_out2(clk_out2), // output clk_out2
|
||||
.clk_out3(clk_out3), // output clk_out3
|
||||
.clk_out4(clk_out4), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked(locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)); // input clk_in1
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
+228
@@ -0,0 +1,228 @@
|
||||
|
||||
// file: ant_clk_gen_stg2.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____96.000______0.000______50.0______136.435____101.715
|
||||
// clk_out2____48.000______0.000______50.0______158.351____101.715
|
||||
// clk_out3____32.000______0.000______50.0______172.426____101.715
|
||||
// clk_out4____19.200______0.000______50.0______190.665____101.715
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________96____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module ant_clk_gen_stg2_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
input clk_in1
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_ant_clk_gen_stg2;
|
||||
wire clk_in2_ant_clk_gen_stg2;
|
||||
BUFG clkin1_bufg
|
||||
(.O (clk_in1_ant_clk_gen_stg2),
|
||||
.I (clk_in1));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_ant_clk_gen_stg2;
|
||||
wire clk_out2_ant_clk_gen_stg2;
|
||||
wire clk_out3_ant_clk_gen_stg2;
|
||||
wire clk_out4_ant_clk_gen_stg2;
|
||||
wire clk_out5_ant_clk_gen_stg2;
|
||||
wire clk_out6_ant_clk_gen_stg2;
|
||||
wire clk_out7_ant_clk_gen_stg2;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_ant_clk_gen_stg2;
|
||||
wire clkfbout_buf_ant_clk_gen_stg2;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT_F (10.000),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (10.000),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT1_DIVIDE (20),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT2_DIVIDE (30),
|
||||
.CLKOUT2_PHASE (0.000),
|
||||
.CLKOUT2_DUTY_CYCLE (0.500),
|
||||
.CLKOUT2_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT3_DIVIDE (50),
|
||||
.CLKOUT3_PHASE (0.000),
|
||||
.CLKOUT3_DUTY_CYCLE (0.500),
|
||||
.CLKOUT3_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (10.417))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_ant_clk_gen_stg2),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (clk_out1_ant_clk_gen_stg2),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clk_out2_ant_clk_gen_stg2),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clk_out3_ant_clk_gen_stg2),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clk_out4_ant_clk_gen_stg2),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_ant_clk_gen_stg2),
|
||||
.CLKIN1 (clk_in1_ant_clk_gen_stg2),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (1'b0));
|
||||
|
||||
assign locked = locked_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_ant_clk_gen_stg2),
|
||||
.I (clkfbout_ant_clk_gen_stg2));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_ant_clk_gen_stg2));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (clk_out2),
|
||||
.I (clk_out2_ant_clk_gen_stg2));
|
||||
|
||||
BUFG clkout3_buf
|
||||
(.O (clk_out3),
|
||||
.I (clk_out3_ant_clk_gen_stg2));
|
||||
|
||||
BUFG clkout4_buf
|
||||
(.O (clk_out4),
|
||||
.I (clk_out4_ant_clk_gen_stg2));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+265
@@ -0,0 +1,265 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:33:33 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top ant_clk_gen_stg2 -prefix
|
||||
// ant_clk_gen_stg2_ ant_clk_gen_stg2_sim_netlist.v
|
||||
// Design : ant_clk_gen_stg2
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* NotValidForBitStream *)
|
||||
module ant_clk_gen_stg2
|
||||
(clk_out1,
|
||||
clk_out2,
|
||||
clk_out3,
|
||||
clk_out4,
|
||||
locked,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
output clk_out2;
|
||||
output clk_out3;
|
||||
output clk_out4;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
wire clk_in1;
|
||||
wire clk_out1;
|
||||
wire clk_out2;
|
||||
wire clk_out3;
|
||||
wire clk_out4;
|
||||
wire locked;
|
||||
|
||||
ant_clk_gen_stg2_ant_clk_gen_stg2_clk_wiz inst
|
||||
(.clk_in1(clk_in1),
|
||||
.clk_out1(clk_out1),
|
||||
.clk_out2(clk_out2),
|
||||
.clk_out3(clk_out3),
|
||||
.clk_out4(clk_out4),
|
||||
.locked(locked));
|
||||
endmodule
|
||||
|
||||
module ant_clk_gen_stg2_ant_clk_gen_stg2_clk_wiz
|
||||
(clk_out1,
|
||||
clk_out2,
|
||||
clk_out3,
|
||||
clk_out4,
|
||||
locked,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
output clk_out2;
|
||||
output clk_out3;
|
||||
output clk_out4;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
wire clk_in1;
|
||||
wire clk_in1_ant_clk_gen_stg2;
|
||||
wire clk_out1;
|
||||
wire clk_out1_ant_clk_gen_stg2;
|
||||
wire clk_out2;
|
||||
wire clk_out2_ant_clk_gen_stg2;
|
||||
wire clk_out3;
|
||||
wire clk_out3_ant_clk_gen_stg2;
|
||||
wire clk_out4;
|
||||
wire clk_out4_ant_clk_gen_stg2;
|
||||
wire clkfbout_ant_clk_gen_stg2;
|
||||
wire clkfbout_buf_ant_clk_gen_stg2;
|
||||
wire locked;
|
||||
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
|
||||
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkf_buf
|
||||
(.I(clkfbout_ant_clk_gen_stg2),
|
||||
.O(clkfbout_buf_ant_clk_gen_stg2));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkin1_bufg
|
||||
(.I(clk_in1),
|
||||
.O(clk_in1_ant_clk_gen_stg2));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout1_buf
|
||||
(.I(clk_out1_ant_clk_gen_stg2),
|
||||
.O(clk_out1));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout2_buf
|
||||
(.I(clk_out2_ant_clk_gen_stg2),
|
||||
.O(clk_out2));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout3_buf
|
||||
(.I(clk_out3_ant_clk_gen_stg2),
|
||||
.O(clk_out3));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout4_buf
|
||||
(.I(clk_out4_ant_clk_gen_stg2),
|
||||
.O(clk_out4));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
MMCME2_ADV #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKFBOUT_MULT_F(10.000000),
|
||||
.CLKFBOUT_PHASE(0.000000),
|
||||
.CLKFBOUT_USE_FINE_PS("FALSE"),
|
||||
.CLKIN1_PERIOD(10.417000),
|
||||
.CLKIN2_PERIOD(0.000000),
|
||||
.CLKOUT0_DIVIDE_F(10.000000),
|
||||
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT0_PHASE(0.000000),
|
||||
.CLKOUT0_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT1_DIVIDE(20),
|
||||
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT1_PHASE(0.000000),
|
||||
.CLKOUT1_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT2_DIVIDE(30),
|
||||
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT2_PHASE(0.000000),
|
||||
.CLKOUT2_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT3_DIVIDE(50),
|
||||
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT3_PHASE(0.000000),
|
||||
.CLKOUT3_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT4_PHASE(0.000000),
|
||||
.CLKOUT4_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT5_PHASE(0.000000),
|
||||
.CLKOUT5_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT6_PHASE(0.000000),
|
||||
.CLKOUT6_USE_FINE_PS("FALSE"),
|
||||
.COMPENSATION("BUF_IN"),
|
||||
.DIVCLK_DIVIDE(1),
|
||||
.IS_CLKINSEL_INVERTED(1'b0),
|
||||
.IS_PSEN_INVERTED(1'b0),
|
||||
.IS_PSINCDEC_INVERTED(1'b0),
|
||||
.IS_PWRDWN_INVERTED(1'b0),
|
||||
.IS_RST_INVERTED(1'b0),
|
||||
.REF_JITTER1(0.010000),
|
||||
.REF_JITTER2(0.010000),
|
||||
.SS_EN("FALSE"),
|
||||
.SS_MODE("CENTER_HIGH"),
|
||||
.SS_MOD_PERIOD(10000),
|
||||
.STARTUP_WAIT("FALSE"))
|
||||
mmcm_adv_inst
|
||||
(.CLKFBIN(clkfbout_buf_ant_clk_gen_stg2),
|
||||
.CLKFBOUT(clkfbout_ant_clk_gen_stg2),
|
||||
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
|
||||
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
|
||||
.CLKIN1(clk_in1_ant_clk_gen_stg2),
|
||||
.CLKIN2(1'b0),
|
||||
.CLKINSEL(1'b1),
|
||||
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
|
||||
.CLKOUT0(clk_out1_ant_clk_gen_stg2),
|
||||
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
|
||||
.CLKOUT1(clk_out2_ant_clk_gen_stg2),
|
||||
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
|
||||
.CLKOUT2(clk_out3_ant_clk_gen_stg2),
|
||||
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
|
||||
.CLKOUT3(clk_out4_ant_clk_gen_stg2),
|
||||
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
|
||||
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
|
||||
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
|
||||
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
|
||||
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DCLK(1'b0),
|
||||
.DEN(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
|
||||
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
|
||||
.DWE(1'b0),
|
||||
.LOCKED(locked),
|
||||
.PSCLK(1'b0),
|
||||
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
|
||||
.PSEN(1'b0),
|
||||
.PSINCDEC(1'b0),
|
||||
.PWRDWN(1'b0),
|
||||
.RST(1'b0));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+203
@@ -0,0 +1,203 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:33:33 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top ant_clk_gen_stg2 -prefix
|
||||
-- ant_clk_gen_stg2_ ant_clk_gen_stg2_sim_netlist.vhdl
|
||||
-- Design : ant_clk_gen_stg2
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity ant_clk_gen_stg2_ant_clk_gen_stg2_clk_wiz is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
clk_out2 : out STD_LOGIC;
|
||||
clk_out3 : out STD_LOGIC;
|
||||
clk_out4 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
end ant_clk_gen_stg2_ant_clk_gen_stg2_clk_wiz;
|
||||
|
||||
architecture STRUCTURE of ant_clk_gen_stg2_ant_clk_gen_stg2_clk_wiz is
|
||||
signal clk_in1_ant_clk_gen_stg2 : STD_LOGIC;
|
||||
signal clk_out1_ant_clk_gen_stg2 : STD_LOGIC;
|
||||
signal clk_out2_ant_clk_gen_stg2 : STD_LOGIC;
|
||||
signal clk_out3_ant_clk_gen_stg2 : STD_LOGIC;
|
||||
signal clk_out4_ant_clk_gen_stg2 : STD_LOGIC;
|
||||
signal clkfbout_ant_clk_gen_stg2 : STD_LOGIC;
|
||||
signal clkfbout_buf_ant_clk_gen_stg2 : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkin1_bufg : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkout4_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
|
||||
begin
|
||||
clkf_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clkfbout_ant_clk_gen_stg2,
|
||||
O => clkfbout_buf_ant_clk_gen_stg2
|
||||
);
|
||||
clkin1_bufg: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_in1,
|
||||
O => clk_in1_ant_clk_gen_stg2
|
||||
);
|
||||
clkout1_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out1_ant_clk_gen_stg2,
|
||||
O => clk_out1
|
||||
);
|
||||
clkout2_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out2_ant_clk_gen_stg2,
|
||||
O => clk_out2
|
||||
);
|
||||
clkout3_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out3_ant_clk_gen_stg2,
|
||||
O => clk_out3
|
||||
);
|
||||
clkout4_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out4_ant_clk_gen_stg2,
|
||||
O => clk_out4
|
||||
);
|
||||
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
|
||||
generic map(
|
||||
BANDWIDTH => "OPTIMIZED",
|
||||
CLKFBOUT_MULT_F => 10.000000,
|
||||
CLKFBOUT_PHASE => 0.000000,
|
||||
CLKFBOUT_USE_FINE_PS => false,
|
||||
CLKIN1_PERIOD => 10.417000,
|
||||
CLKIN2_PERIOD => 0.000000,
|
||||
CLKOUT0_DIVIDE_F => 10.000000,
|
||||
CLKOUT0_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT0_PHASE => 0.000000,
|
||||
CLKOUT0_USE_FINE_PS => false,
|
||||
CLKOUT1_DIVIDE => 20,
|
||||
CLKOUT1_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT1_PHASE => 0.000000,
|
||||
CLKOUT1_USE_FINE_PS => false,
|
||||
CLKOUT2_DIVIDE => 30,
|
||||
CLKOUT2_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT2_PHASE => 0.000000,
|
||||
CLKOUT2_USE_FINE_PS => false,
|
||||
CLKOUT3_DIVIDE => 50,
|
||||
CLKOUT3_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT3_PHASE => 0.000000,
|
||||
CLKOUT3_USE_FINE_PS => false,
|
||||
CLKOUT4_CASCADE => false,
|
||||
CLKOUT4_DIVIDE => 1,
|
||||
CLKOUT4_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT4_PHASE => 0.000000,
|
||||
CLKOUT4_USE_FINE_PS => false,
|
||||
CLKOUT5_DIVIDE => 1,
|
||||
CLKOUT5_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT5_PHASE => 0.000000,
|
||||
CLKOUT5_USE_FINE_PS => false,
|
||||
CLKOUT6_DIVIDE => 1,
|
||||
CLKOUT6_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT6_PHASE => 0.000000,
|
||||
CLKOUT6_USE_FINE_PS => false,
|
||||
COMPENSATION => "BUF_IN",
|
||||
DIVCLK_DIVIDE => 1,
|
||||
IS_CLKINSEL_INVERTED => '0',
|
||||
IS_PSEN_INVERTED => '0',
|
||||
IS_PSINCDEC_INVERTED => '0',
|
||||
IS_PWRDWN_INVERTED => '0',
|
||||
IS_RST_INVERTED => '0',
|
||||
REF_JITTER1 => 0.010000,
|
||||
REF_JITTER2 => 0.010000,
|
||||
SS_EN => "FALSE",
|
||||
SS_MODE => "CENTER_HIGH",
|
||||
SS_MOD_PERIOD => 10000,
|
||||
STARTUP_WAIT => false
|
||||
)
|
||||
port map (
|
||||
CLKFBIN => clkfbout_buf_ant_clk_gen_stg2,
|
||||
CLKFBOUT => clkfbout_ant_clk_gen_stg2,
|
||||
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
|
||||
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
|
||||
CLKIN1 => clk_in1_ant_clk_gen_stg2,
|
||||
CLKIN2 => '0',
|
||||
CLKINSEL => '1',
|
||||
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
|
||||
CLKOUT0 => clk_out1_ant_clk_gen_stg2,
|
||||
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
|
||||
CLKOUT1 => clk_out2_ant_clk_gen_stg2,
|
||||
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
|
||||
CLKOUT2 => clk_out3_ant_clk_gen_stg2,
|
||||
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
|
||||
CLKOUT3 => clk_out4_ant_clk_gen_stg2,
|
||||
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
|
||||
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
|
||||
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
|
||||
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
|
||||
DADDR(6 downto 0) => B"0000000",
|
||||
DCLK => '0',
|
||||
DEN => '0',
|
||||
DI(15 downto 0) => B"0000000000000000",
|
||||
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
|
||||
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
|
||||
DWE => '0',
|
||||
LOCKED => locked,
|
||||
PSCLK => '0',
|
||||
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
|
||||
PSEN => '0',
|
||||
PSINCDEC => '0',
|
||||
PWRDWN => '0',
|
||||
RST => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity ant_clk_gen_stg2 is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
clk_out2 : out STD_LOGIC;
|
||||
clk_out3 : out STD_LOGIC;
|
||||
clk_out4 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of ant_clk_gen_stg2 : entity is true;
|
||||
end ant_clk_gen_stg2;
|
||||
|
||||
architecture STRUCTURE of ant_clk_gen_stg2 is
|
||||
begin
|
||||
inst: entity work.ant_clk_gen_stg2_ant_clk_gen_stg2_clk_wiz
|
||||
port map (
|
||||
clk_in1 => clk_in1,
|
||||
clk_out1 => clk_out1,
|
||||
clk_out2 => clk_out2,
|
||||
clk_out3 => clk_out3,
|
||||
clk_out4 => clk_out4,
|
||||
locked => locked
|
||||
);
|
||||
end STRUCTURE;
|
||||
+25
@@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:33:33 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top ant_clk_gen_stg2 -prefix
|
||||
// ant_clk_gen_stg2_ ant_clk_gen_stg2_stub.v
|
||||
// Design : ant_clk_gen_stg2
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module ant_clk_gen_stg2(clk_out1, clk_out2, clk_out3, clk_out4, locked,
|
||||
clk_in1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1" */;
|
||||
output clk_out1;
|
||||
output clk_out2;
|
||||
output clk_out3;
|
||||
output clk_out4;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
endmodule
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:33:33 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top ant_clk_gen_stg2 -prefix
|
||||
-- ant_clk_gen_stg2_ ant_clk_gen_stg2_stub.vhdl
|
||||
-- Design : ant_clk_gen_stg2
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ant_clk_gen_stg2 is
|
||||
Port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
clk_out2 : out STD_LOGIC;
|
||||
clk_out3 : out STD_LOGIC;
|
||||
clk_out4 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
|
||||
end ant_clk_gen_stg2;
|
||||
|
||||
architecture stub of ant_clk_gen_stg2 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,72 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_rx your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [11:0] probe0
|
||||
.probe1(probe1), // input wire [11:0] probe1
|
||||
.probe2(probe2), // input wire [11:0] probe2
|
||||
.probe3(probe3) // input wire [11:0] probe3
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_rx when simulating
|
||||
// the core, ila_rx. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
+112482
File diff suppressed because one or more lines are too long
+143655
File diff suppressed because one or more lines are too long
@@ -0,0 +1,24 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 6 13:08:29 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cmos_1t1r/ip/managed_ip_project/managed_ip_project.runs/ila_rx_synth_1/ila_rx_stub.v
|
||||
// Design : ila_rx
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_rx(clk, probe0, probe1, probe2, probe3)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0]" */;
|
||||
input clk;
|
||||
input [11:0]probe0;
|
||||
input [11:0]probe1;
|
||||
input [11:0]probe2;
|
||||
input [11:0]probe3;
|
||||
endmodule
|
||||
@@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 6 13:08:29 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cmos_1t1r/ip/managed_ip_project/managed_ip_project.runs/ila_rx_synth_1/ila_rx_stub.vhdl
|
||||
-- Design : ila_rx
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_rx is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||
);
|
||||
|
||||
end ila_rx;
|
||||
|
||||
architecture stub of ila_rx is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_rx (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [11 : 0] probe0;
|
||||
input [11 : 0] probe1;
|
||||
input [11 : 0] probe2;
|
||||
input [11 : 0] probe3;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,70 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_tx your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [11:0] probe0
|
||||
.probe1(probe1) // input wire [11:0] probe1
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_tx when simulating
|
||||
// the core, ila_tx. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
+76661
File diff suppressed because one or more lines are too long
+104835
File diff suppressed because one or more lines are too long
@@ -0,0 +1,22 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 6 11:28:49 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cmos_1t2r/ip/managed_ip_project/managed_ip_project.runs/ila_tx_synth_1/ila_tx_stub.v
|
||||
// Design : ila_tx
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_tx(clk, probe0, probe1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0]" */;
|
||||
input clk;
|
||||
input [11:0]probe0;
|
||||
input [11:0]probe1;
|
||||
endmodule
|
||||
@@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 6 11:28:49 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cmos_1t2r/ip/managed_ip_project/managed_ip_project.runs/ila_tx_synth_1/ila_tx_stub.vhdl
|
||||
-- Design : ila_tx
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_tx is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||
);
|
||||
|
||||
end ila_tx;
|
||||
|
||||
architecture stub of ila_tx is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,64 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_tx (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [11 : 0] probe0;
|
||||
input [11 : 0] probe1;
|
||||
|
||||
|
||||
endmodule
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module vio_manual_ctrl (
|
||||
clk,
|
||||
|
||||
probe_out0,
|
||||
probe_out1,
|
||||
probe_out2,
|
||||
probe_out3,
|
||||
probe_out4
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
output reg [1 : 0] probe_out0 = 'h0 ;
|
||||
output reg [0 : 0] probe_out1 = 'h0 ;
|
||||
output reg [31 : 0] probe_out2 = 'h00000000 ;
|
||||
output reg [1 : 0] probe_out3 = 'h3 ;
|
||||
output reg [3 : 0] probe_out4 = 'h0 ;
|
||||
|
||||
|
||||
endmodule
|
||||
+70
@@ -0,0 +1,70 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||
// IP Revision: 20
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_manual_ctrl your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_out0(probe_out0), // output wire [1 : 0] probe_out0
|
||||
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [31 : 0] probe_out2
|
||||
.probe_out3(probe_out3), // output wire [1 : 0] probe_out3
|
||||
.probe_out4(probe_out4) // output wire [3 : 0] probe_out4
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file vio_manual_ctrl.v when simulating
|
||||
// the core, vio_manual_ctrl. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
+85
@@ -0,0 +1,85 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||
-- IP Revision: 20
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT vio_manual_ctrl
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : vio_manual_ctrl
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_out0 => probe_out0,
|
||||
probe_out1 => probe_out1,
|
||||
probe_out2 => probe_out2,
|
||||
probe_out3 => probe_out3,
|
||||
probe_out4 => probe_out4
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file vio_manual_ctrl.vhd when simulating
|
||||
-- the core, vio_manual_ctrl. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
+9034
File diff suppressed because one or more lines are too long
+13218
File diff suppressed because it is too large
Load Diff
+26
@@ -0,0 +1,26 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed Mar 29 16:41:24 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_basic/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
|
||||
// Design : vio_manual_ctrl
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2,
|
||||
probe_out3, probe_out4)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
|
||||
input clk;
|
||||
output [1:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
output [31:0]probe_out2;
|
||||
output [1:0]probe_out3;
|
||||
output [3:0]probe_out4;
|
||||
endmodule
|
||||
+35
@@ -0,0 +1,35 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Mar 29 16:41:24 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_basic/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
|
||||
-- Design : vio_manual_ctrl
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_manual_ctrl is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 )
|
||||
);
|
||||
|
||||
end vio_manual_ctrl;
|
||||
|
||||
architecture stub of vio_manual_ctrl is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+3821
File diff suppressed because it is too large
Load Diff
+5264
File diff suppressed because it is too large
Load Diff
+533
@@ -0,0 +1,533 @@
|
||||
`protect begin_protected
|
||||
`protect version = 1
|
||||
`protect encrypt_agent = "XILINX"
|
||||
`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
|
||||
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
|
||||
`protect key_block
|
||||
UujpFoYKoOQ7/Jw6owEbggI2AGOgzbHR6JXF4x/izP5Fh4WM0VoNKTT/CrUpcaxvPcEB3VSFIRdM
|
||||
zEjgl5GLbQ==
|
||||
|
||||
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`protect key_block
|
||||
f5RyCaHb5HYoLsPpSBrPYpBu75i3LvPQ71qIEa/aoXsNX59UTv8AuKxtAPmKJn2lGzU85o93pPUz
|
||||
6IUTdlLhcarMbqU68e5TlXbOXaga3KUj4uXh5FkcNdjPsjNT76FRa5yaah1J4szu7iiw3tPnuQJ4
|
||||
sJ7X6wRWQIJF6RZJQ7M=
|
||||
|
||||
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
vzUpOnYACJ0VEPnozBdDHNmglN8CrKvVmd7FT58A6TVLlrgZoYwyIPQMIh+Wfc+wTlVynnNf5/KC
|
||||
BJOYRsHDGsi5eQBIqFs4IO2s0YluOIEcuhjI1NL49HG90oDLDYg5vQsfvfkgIfXdSUeO4CWL1STz
|
||||
dN+bN5lJol2g3oFIppEAT76jtuKAX3VW+ZQrlhdFxRe2XfR61bUfZTyxy1sxEjh6zx1lNk15Bh6G
|
||||
TvDbeQpS3X3IwQkda126umKLhxhuzVYI/Dj5ubjHn9iROohcwaJUKVYfiSpg7OvIQh0dIocm/Pr8
|
||||
Jnq8RYOlltOXK63GToRwOuvaEVsyYwXPCsJhYw==
|
||||
|
||||
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
IqsYPmYfJRgqWcpVxxx5JKL2K5lwiA3+TGmGkzXMe1mM6wTat1h3LqSohdSynrSese1HtJw7NjBS
|
||||
R4sEHDCJLtLiIBXUDNOxs3/aFcfwI2ggGKVL7gj8LerPTvjancZ3CPrFi7suJ8va4ScDXJ2+AZpv
|
||||
1HkaXhquWtX+ecTMvlBUJ0kGRmT3QvqsqdoJvLaUtWmOb/zcl/Nh7cyBWKwOJ6JJUCsg2Ny6n0Mi
|
||||
CPGTsfurek7+yGad+10NV+Jdn5hHQLBf66QBRg5ezreuYSEBodVOIKAo3y+OLqpGrkjVyZP2Jekj
|
||||
3gAE3AlS23WF2E2B8gWcKlRCe5mstjPwmciAjQ==
|
||||
|
||||
`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
SDlGuJ8/IFDM5qipR8lmqUiiSg8fMligX7gsobHkQDqRLsLrXijbx23aj4mkUAgF+oPb9moRXMT+
|
||||
ZQitvA5/h3W0YwLdK0P5IZuLURPqDlMwqENJrGM7d3xQu4APt2TsYcIWzy69vwDhvpVhiU2guQ2w
|
||||
RmJXF7B1uLONLo7iKhljzh08U3MalnpvLRgTyF13HjlkISLQE5uevFCzYB2in3CEPm7UvLorqhnJ
|
||||
57vVjcU+wSz1mFigbG2ffzUXycQttuY0ZXalTnSornuILhiF6Dz1ntTVIkPAsSmCzM2pkya326bi
|
||||
VR6/Ww0KJSGjMc9QAcY1dzerdA/O/FHc0wHRqg==
|
||||
|
||||
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`protect key_block
|
||||
nv62qaAPOM1gKXHVylxNODJ0FORpIfmG0VU8DOE0VYy7QuPs1fSFKwqsmeCqLmk1iBF2iwzM4HaH
|
||||
n4NZzzSC9moQCnEWQQr7ujbbmsQhrn/tqwtWMSAdsDvskDzQxglQ6QGrybhxOmpv4ptOmwdiPiSh
|
||||
mzNT3tLbjqrWoFAIUD0=
|
||||
|
||||
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
jF3d2E6CGZp/hS8coNep5TPowf3sa0SgNHwNmqsow9h+brgrP4csczpm7KBBcJ5v+YbOvx0z+gYy
|
||||
WBAxHAq2icNSvmrHAZTXOGdEJEE5hVch+yxypEclXFAnDShH7A6r+9IACIFI6vQ+UJJ84TGn2SDU
|
||||
MI/Rg/QIXumqkI7aPcOA1ytQg6cRR+iT/gU6b/7+TGQ21uUGNcdcFNGGw3MiCeeQAO453zksyf3f
|
||||
3q13lH5nspjdUO+EOyLip3iyWk1rVfZM5a6iueAPrsJM0H4hecXe3sh42f/VZjC7pKxZNTyNG0pY
|
||||
f73A6j6rB0cnGG9VyIOhkjLQ4APwBFMYDfhmYA==
|
||||
|
||||
`protect data_method = "AES128-CBC"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26688)
|
||||
`protect data_block
|
||||
auFlWvzwTlijGjIhqR/ss7jiLTvsXp+egZIq4uAUthZKmSRgCzdfKQJtCyDrfnelW2c86fhZjq+t
|
||||
lWQZYI9WjvnZ0JU2uGdNFxU58FefXMuWqO5D9nCJ65XItEeL0vzS/SP+1zBySpuIc7Q5zDV0pdKd
|
||||
lq6mhdbOQrrv+/IxXsGALMEYvEHcRetx9lqTiaApoNudY6rv3DlxKnHZQhP73ne2ZDE8euAKgCJR
|
||||
drfhGw9j+MzXYkhMsrOPKK9B9dznkTtUz7U2tRAdAV8/nT+PIA+YI0VcZedBEc2V1hNbj5dVm5G1
|
||||
BP6yPi5ul5bl64ltAHuolbjnPrRDoL4mkp+6EMy1qjQf4ILb8EByJgEfX93wc9l056Qy8f0ZEmyz
|
||||
i7WPz8dvBEkmT4qAwDFOGJS8NguOYj4O98eAU+vTjLn7SgkoSld9PSwNoRvLyHwmZPxm4/t9Oskz
|
||||
1ViVbGkPzrDZDaODEULpw9iiYDsZ5QtSL2YhgKRVhmrUeq014Q4pl94p817+MWjEKUEftsBv9RjX
|
||||
SHKLHd0/lNQ0HbZPawUacx2EVqVwg2uv+1oz2jJ0yRtxcU4vAd9Dzu/4MsWUsw7PNWPOP3ifWfXy
|
||||
PrL3xky8EoAdhlBobIHe5CWkkPPPBnzc2chybm2c1AXO7uZejaHDIAc5e0Lb35lBZ0K4+Nutleng
|
||||
GZq3uMWqkAptW1NIm/dlmfhMrtOXoZJQeWcfKMHFXN9lVfaJl5gQDTwyCiQMFAn1O4idtqxd5onK
|
||||
ZanyQunv3FgP8x+MZ4cVdPWsGwhGQMovKED2pPB7Kv1o1LeUF9HBaicICei6ODY/S7Hteqz9hPqb
|
||||
zYhkNrx3qva4SZ9qk2lInetwQ8EyZROMWtFuXUQkRUlHpDnDVmMjhM2qqi0sZaSdejRQXKe17x1Z
|
||||
BACyV1JiMep9quW2aO9tmmSPtrzmB1IugaOElyllBFYegpAxSTYSSbsbC8PPkTHKjjPwQSJ1/Z4D
|
||||
7IKT7DQz3vssE6p9sjB9ixF7UBPWQef8FxZfgotlECjyyR423sMfrb8H4q/ywbo7TFgmf5bt8ypC
|
||||
sQAP1J1frMR5b395CaGpcbmZGLREr8XsyuNXpY1oY6p6exaRVfakp8yrY0b3f0GVcB+JRlvfPmdw
|
||||
yPstSamgvjJ6tz8IKRV949Ehm+eVt9Cgbjz6X62H2L72hH2Po+gAMakkDXOoBNOThhwPnOuMcV3n
|
||||
H8mjEMPhcXfUHRKumuYbpJOloWRbjuZV4jn5cVs0XuVwhOkRSMI+zx1EbCWMZkLLQnNCxRF3La+n
|
||||
6BUsaeCqMZSujsR4gm27B7QxMLY4hxzUcR83BcpRrdlDYbjNX5oNe+Kn3rUK96UclyDTfeSlUSrz
|
||||
Sj/3MPiNIQyd4YrIrLRPxF/fKkqxPWAF6rUiK6JZR4RFzc/9jSoK8Gf3zesgctISqPsGHklUAoA7
|
||||
6xerFe1VQmX0nyPoJ+iLLaXjCMc+1r4quTIUTR5nt07hFgulYXVjCIdAmTbULSPh35KPeK2cM47t
|
||||
Ydtt6HFEHzDS2+AOTIcq8qJzmWmrDM/BrmZw7YjXbI+9nWqxwojyFw1BJqnnOz95alGIjkKZMBp+
|
||||
FiMxBhJxp/1ykAvW0SN/UEq/Zo4VFEmfl8m7OYx3/oK3imiS8vdBZCk5sTAeOvVqQfvBgGqcBsMx
|
||||
okNHpf/1waJZZBX1TOyEJEGsH0X02dcK1n+OOvrLX3gItGxfMlYjWOcj3E7U/TcnqLY6/+BYdyZf
|
||||
HYfaThexpvE//tRw7nKV6Ff4IG1HbLgs5PtUr2TQ0awGe4Ml+CDnmXQd1b6B8YOH2/AW7jiB03+N
|
||||
WwxL+MLnElfTgjZzG8Qpapud4tVyOfZ54VBVDGzebzuxSMuZnbFIc/G3dB9ueIlWLFZ6wx8rYbzD
|
||||
I+Vb5MRFXM8lrvLDorMvGKxp4nubWRB2qkGXctDBK1EWIYa10ViSkyZ8/aIohApAhesomddZl7uf
|
||||
vO+04QiDoNWuG+opPrbUQTr2Ab28aSg//plYmAFqPtx3631U1aMwgcf4Ds1fHWt7iypITd6qJxz4
|
||||
vXVaieSl2rZBf40usujjVX0C4M5vQsp1Gmn/jNhNurbRe0iNX4ZI8NR8TYTUQRJ6rHQqZqxtWLEJ
|
||||
UrCb4uff4b10FcvYQRZgYR2F7dSwCyBGY5qiPGoy8zCKIxyWVszZOGcITHc7BJlqFc0J3uciHcoe
|
||||
r7UWf/QZPBiHAzkvBLLF/x/zb965GIlgkHGjZEBje9wRNGOlFElh0nOYzr0izE9PJd06xEwBkjpT
|
||||
1xXNpJEmn3/PcEimha3QAB9zaxWW2Ftfddzul7t91G6ZXo+2JyTCwAu790T4D1xHrfon+RhebO6z
|
||||
C/jKy7HkKf+dFf75xJLcpnCVEomXlqZvQCn+m4GtdaAI1XhXp8JWmaWrSS0l3LzSd4dOX0c9rztC
|
||||
W9YGcT5VOok1N7y4OJzeMvmojMEni7Sx/c1PJP43gqCtqrzTpghlu6tM2T9s6SyxjcahEj74RS6O
|
||||
KvvyZmc0/MzeDfoey+EOp7hcgFp5dJ+Vts6NDeUfZ8KHG2ggh0kH8Dyma+V+gMnyE5nh2ZUAinjJ
|
||||
JKtk39UE2blRsxQUo4UbTsCNl6PQH/r1clgHEwpXe7374GpyA0J8btMl8UU8jUJGjgxle+fJgCOP
|
||||
XIxhgQqlHwCMG6WHRf4uz0T9gJKlZo9vd3w5mYa5ahdteulhkqp7mOe0tOo6hSQc2P1wd3Stgrme
|
||||
inBrkvMMuTpEPzOI/+Mup2YgZ26WHMo6+EApyk5HLe3WOA1y3H+UgKIBcQKvYbIosf6qvFCj9XA/
|
||||
vZPEQsstH1e1twK8bIocelSKcTsOdh2++aV42YmaeD+NxZSjO4BV/QpBzkOdwX/Z+L+fedVbQ1hd
|
||||
CfwXG72pgS98jxvwyiHBoQ2BKH00kbSE0THlAOxLzJp8YexTLi8gycdk0WaKqVkExBiQmwZmZ23e
|
||||
8ytD1WQgUkmBhRM8LrEihNDtiTWbAebuaDWsKr44sbeFFPiKMoeimQWT4/AAppfpDorFyTxvrTtZ
|
||||
I/r/RdiAwf3cSDWqxsAad/NHcW+drV6q/zj2/vt0SuvJY+fCQAdHjiAOuPnPO1l6f/3IRW7GbHGY
|
||||
isvF40uQtYClhGbAOHP9UE0l5vliVXAUs3/ZlNRFbXGiyUCbK5jcP9ml1NM4KLT9W/MmmicTm9B6
|
||||
Ab1KLLzZ0P34t7Lh6OrApQFpvsOTQC5IlbEKzw557kai9QGEi+QbsMJd2/1z+CBn1RZd5KuHfIGL
|
||||
GVYEQLUk6/gl78whl4VUeyF1Ick8gRBgVPSDtn80fg1G7sp7FV/Gxjf78lubz1o90wHvMgUmnj6D
|
||||
Qj266zBtP3j1CqHCfeWAHZeB2vDMnszu6WIHF30zMxkpUUt85szSr3mOL99MYAn+TXrrIKlqLiSf
|
||||
iftVo4x1IiJJ1iA1ZpuQ3oB5RBK+MQYzrvGeRVixVugidKi+xYhkNCfA7T+HOMJ4JKKokrliqIvk
|
||||
KXE3NMtmjjo89k/daPMaW8rpzuXpIBF7+56+CNIwQHp8L+wlCpiuWaLK/OFvnpUy+rxVWVuc3384
|
||||
qvmKMPnmNKzvgrR8BZiDFUbP6p0ZPR+ErJgkhVwPCi6hwaYPzZoixDnL2s8exdHRXNL4E9nVPkRz
|
||||
C82Cs3sYZo4q/XQHmcpmKaVDYqh3unacTkKGtY7snLsN2CCx/mljLZl93y21y3X8ZfH+ho2J8Wln
|
||||
yiFXgzfCF+c01ktnWLwPObC4/t3ZLQLegWPz/9vHA9D/la6aUJoOJmSIs6JJFTlo0A9kJ2irp6Nf
|
||||
hIXvHNfCts4W6fnLteoi7hrmIyXc6ponzBR2cPiTT6nAcxg1bnabRnxNt5sxfFZ8ImtZvixmo9Wx
|
||||
Rpr0Cz5aMn4RWXElcS7RFQICT/T1KJtrfNyRkpNC4S1EN4PrsbAhzk5XImbP+Yj2DhKKHUAomO4L
|
||||
kt7vRpFert5OK0jD00QUnQUK9zRimuCnLNe2JQxtsbMLqdeTtk4mBYgmEU1gyTVQsXgnzRlPvaBK
|
||||
pCxGO2x/RfrKQjwXuld1RC0OuXSZhqUBLDv0/jYb7H97xm82ggiRKigCx2ewCgpVrT4vWnwyxRD8
|
||||
dvl79Y+2K4qplNQqYbmrDM+jbByoGWiUQshvGjrg+87LX6VaPDBWL7FiX5YWW0Q1kMRbD6WVPXb8
|
||||
l90BuzToWooxGTQv2N4W5bXG024rrFJliBPKRB2vKWe+QqtjjOkMCsg6U7AGcD6gnHgApOPICfL4
|
||||
oLNBXlsF39TMF/34ONn77AjczOoH6G7+3BtBfGxF+NZck87qo84LrROHs+J360gLC7xXXfGS7fR7
|
||||
GHx23RJxRLmBsYp9ceeu+2QDcBADrkwHXl+m1CY/aST+ASnNaetAfYsMlCTiwnlWrTUUzYiE/zWB
|
||||
NukBgvjer4FPcm9WOex43vUWhexn+NYrfq1dO81/QvZ6/zfB+iU2DPHxQ+ShC9dGsH6n7zkiRU35
|
||||
deVmFzTPtU2QyvUbZzaMaXmuvlSGqSWCFxhu329FSMXduOjQP2D96d60PQHRYPJ/8c9x8awRWTAo
|
||||
t0R6qtutPofwkuBFuZImKI+0ULa/EU1/xh1mpQ42oXwZ4ArQcjb7gGgMGc7m+d2uVVUC96c9c3Dr
|
||||
eJii3KcmmVnoSBGsmh6NlsxfSLsUgl2DtInYybZFl+IyMJ8LJfDaXE+5SjliOUn6WHbqyylBZnUV
|
||||
A5wLnY7jidlHBOFDJz7AUOYxaPOd7ne7T0eA7Szs/r608+ZBn8ah5GYXMYBEqfySe+JP4keJnssO
|
||||
SMqf2qPDeOaQq4KHxqwjcfpJC2pi0rr2RAJhuCHPy8QT6ZogNRcWUIw366X/AH8Qrup18G7rjER5
|
||||
Fm8wMl9LLUcEf7+keOFhhvpPIEzphy1mQC06hTHEuYksRpFnMrEVmYY+CkX8QROoqXFRgT6ONsuR
|
||||
RStGfHA0Dgi+Ci6T6RZ5i5U/ijcG8TTk80Y/TrvKSu9dkaLotdxInPowg4/t8tICtjQ/IM8oLYG7
|
||||
KyRc9Z0OoPjkIX9/WDU/e8en+AOAqiwvd7Qj3xUQFU7vQ4nxEuClJN7YPGgqsWFK2rPE5i3u9i08
|
||||
e8wXVfZ3QG/5W6GCh2JPpDyHAtiqJEyXPq75mmQFZhR3jdKKbfqQQi5owU1NFZX2vRQ0NlQWSAuJ
|
||||
ZDDqudkW9INTUCWTkd73XVocFfFsV/WaOxGKPCbGNc+VGvB8ishb0lqGhRiub7yJnAZCvZiWImUl
|
||||
sCWgGMwGGoEcTwV5s5QoIuhXEz5Y9iudMxlNtGaBN9KpBnkiBezhXO/Zd5kW1UDDDj9JKwJDULt2
|
||||
orKiMcenSB1vKcPMwxBqVWwd0RLE4lI8z3FB08SlXH9PoOZMKXfHhamiqi+1qz/6Tzng7aZkatFD
|
||||
y4pMfAihzMMLqGTjO/qrHeIIRy0q2Kmq6kU9hNinXVqkkx4X2/IHKtbopfe2oA7hwQT51+LebR1+
|
||||
/X/k1cr4Bo629+9RP6fhSxuJRyUoBTa6v0uiEyYR26YMCrjDkcnQKe0svbqymoTdjS6CPDtt0ho8
|
||||
kEZtCMxnMldHZHef0eZUxytaAqY3unBHccJPCw+HZsGU3+gEG6D/5wRiiSKQgMqfA5syYAQ4IozW
|
||||
hJLSQzOvFEEqMwaXm6wBCWmfBbGSX9ARbDN2nkMU4XaUM4UcFhGKyhmv6Bn+JBcpZrTovhHLdE8V
|
||||
6nHcPcGvEMg0NME6KNdgRpWtlgiBkgmz7fmWvRsanO5VPpv3uzsCFc7drxxdtqq8kTD5glPBB5b+
|
||||
/rqp7t6gZHk1dT/NdIkqxXOQpNF9n4HZ/Iy6mz02TaNhiNPKnKStTgQTGJvyFCnusstYP3qIjEy1
|
||||
7c5y3Yg+fm7qeMXoaAIuYgEVt48efY2Nw+uj8aJVuo6XcIE7htSo9XZTKufx2hP9WAddXAvoDgtt
|
||||
v6X8oDvTODXe9DAvgWpn2qJA0wlR0Qm2ENfg1Vm8VrL5FxHWm2WX5loPM9Tgtq9zXcmjM2ljXvZC
|
||||
sE+pcUjGsonm1whgGRHs2m5QYx8sGw/hDZTv9wwlDImMyDxGu/MBQdHJOXiVAY3MApxQqU/seR6k
|
||||
19l5RS9qY1VwoeIvDBT8xY5Wx9ZQN4vty1zoQV28nP4GnAsIl65dQhxdNd2wwK23uaykB7Z5KllW
|
||||
pdBtUyxrncfL5MRwuVMSK5A6C00MglbxLivSz/gfLoy7ulBbvQoa+yzW2moJ67BEJO/uTk0fmyDH
|
||||
qLJtdE0r+V8n3EozGd7hSC8BYZhuDM70N2vsOjBc7rL1YG9S+l57pKlCBrr+pqlePqm85cDZRv2Y
|
||||
hG+rkNiVkJbbIJ5tPtCb3nwqASkOC6BawEidBEyeUDT970EEMZ5KsU08cMQKBo5RrhukOyLtGaP/
|
||||
6JqN9c0pZXnInbktp8npX6NuK6Fv9cYzZPe+naCUXzWGFxEva1751jGrZTnrnCe0kqW5sH1fYKbx
|
||||
NQLmIlhZ+pjbmmSJ6ENTyTBTIPs86sBym+99EA39zNhRsRUN5dbaX4sa9U8kLp73VGWzTy3r/u8X
|
||||
3giFWIo35cSb/rARvk+73C2fN2GzGoqX/fFIbReC7XvK6jBcMPZjy0uoo4Yl4wqipXmJmm6u06Gc
|
||||
tXmT51tlapxilN7PWVNsKyiBwmt977FfKWYwharVjf49UakkOx5LYERL0+IannjPvqW79LVId22D
|
||||
21hbs91IumCXPnqjS6Ag6r11jQK1TAyfLuXrHs9eil8kbWwScsyONzZg9nKjq4tcPnFSejnsOGDg
|
||||
QxyzjUowbRFRgIfYuB/IQizAAF+bLRhDBG1VAi1dKW+EFt9OMVO0PKjDE6Rzxg+XTQZ4xQJZFaR1
|
||||
loH+/lfeAk8Z2QEsgcud2xyctn/cl3A0TbwmHSg2lF23W3HENpKmAjHeZ7iYzV3oM8MRH/c2Y1rL
|
||||
4Fk3IY8ACvMBY/y+K+6pa2NMHUhSOnL3PtaqROx6rbYIvkWLyyoyyi54vTzOWFsK4HqpEmIOf8/P
|
||||
lsqRSTc63RfjZKQAIKmH00I3bavh7ADX7gqQMUtITmyWWZ+1iDZnuanohvXQx1QgL31qZ3A+a+uJ
|
||||
SiPg8OtZlatRqv6D4PlxnaekP3hH1NhQONmvVs+otj58C7GjPDKING+IGt+GgP6a43sck46AhMnU
|
||||
VRKpI18byDwkchCeBIvmZDSmb1MEImKexCPasE37Dhfr2MzvS0wiub8IY5Q8TMFaDCMk7SNrhdA7
|
||||
2GFyce7H+M5og21Qh7TYxWCbb854Wrxd4lvwpugyQHpAN3qfP8B5mBQUZvkEI3VXmX4TpH006+v6
|
||||
zp9LdX6feBUbjI83VFVoqNOKJmH1mUTtND7aKzPHcWjmR+JsK/v6W/lI+nV/nzFLh+SczZXLSBgw
|
||||
9EY5SyuBNXw/G/xYJAAzoiF1wCdIgPzNZCO+frf7+/b7AAiMgfA1PlsAbjLSli6k9h+uCw4rzTfi
|
||||
tGIB2weFw1uC1FyaacVS8MxBVA9T7zG03K92hc7Himiq5A/0jksc47dq54lpMLwWpckOzgnJjSo2
|
||||
ZM5ngA36rDwbMApd+Ws/2jfDhwM0USxDg2Cx1YaVNdbuQXs5nR+sJjMq0WCbqJ5y1Gwe8xcZzGaa
|
||||
10CzdG9hsnQ1HatYjf+tonG644FbM61I7vFGhZ0T0RuaTR9dJM7Yg4wPumaY6AK2MegNxxDyMS2r
|
||||
3LmbUq3DPzV7KjO4m/D+kExNxPbLQSmSEpwIOaQ8Ch+d6w2z9IW0fnpyrR8ZnZTJssar5Vtii9YW
|
||||
4OOXNmSUEHoiXxooRIYzEKHRH8UE60gD0ZOcMNAAE4xmpb0R+SfEvUDtKubhauNcQEED0kEREG8z
|
||||
HZqe+b7xzs/J/k+k9iYWiudWcohxfTSU9DFw9ZJh/J3XDkZO2pJ1oS59aQ68yo8WncTJgwtboJso
|
||||
oSlSuwEgiuGgnrkL8w4PKexCMOg9uV90tBofNEG1cpZsd/g6kuhnPXCatc3xnJdKK0hm1sSB1u7n
|
||||
5TuFh5RgMUjVh6JUuPd2KABZmuj0UdVi8w2C10dAZB7vHFlBxgHgF6vIOEfr8sWi9R6GpczgFN3Q
|
||||
SZ2Sm8T8osKMcP831cOtJBFTEZx2Ywv1NMAXvA9v8K3mQHupMcdPBi2KwgN58BACzcvzzvlJyXbJ
|
||||
L81XYkj2zyR+mJR+/YgBRi2EW5cEuOSNR0/y85nwCzMZVbQPvuxso+zU2xrppT8LFeGNpT8V1hyR
|
||||
3EqAqaN+xWk/H+91cHwvPFAqcUyUmKLjQTN60B/AegL3Jxh1oRVfCPNZjCsLrnb3ztzLz05P8uDh
|
||||
x1TmXk0xiijUW6TR87G7AQJs++vSfQGlV6C/7HNPc+oU7HtHzIsQPaY+jXbB5j+iasL+rCW4cvi7
|
||||
NW74UlSQmPDM0NCoLwxtosskhBX/pSbH2QZnO4WVvwhGQ/1CnQJu8U0njil+Dt0f5Y260W2RxLNz
|
||||
zI2rrjoZB1O88O8+sECu+lJBoWQDOSpCAJKEKHVa6bcO+KIb4lU3o8Qvq8Y5Zz/y0cgyLXjgijIh
|
||||
LK+7LMrtArirKneXgemxqxupPfHaOJ7GuONlf/6Rgz8gpfpUNhMP4iGW383XHvZBZB3xjrdLbzDa
|
||||
oatPUWt0ZCS9SoNdbiJpXwNMTBZBka2AOapNJKN7hUNc67ZS9tc51b4TAmop06kLzN/6S7YR9LEA
|
||||
g1nUPBBDPrTB7EKzixj/fBhdfTmOsvL1Yjfox58Y1/Cu6bBuotVMBYS/F3xsGJEfxj+K8xIBS+vz
|
||||
0Ax/M83VDUHcVrPMiAbi2miBchgrsVSdw5kaEx10wCMQAnYx/ALVgo+W4HTfrPmPmGGKki9As5AU
|
||||
4Fj9+siRY4jAjGgIKnQLMpKbSNBypkxiaVak1PPpWXqMd2pavwZ5yZPRW3dWj1rVVo+bEDI/OUrF
|
||||
Zg+cqZIP+zdsSAHHw8ZaAbohlFFs6OFwvLZuwYDCIaNU8o8eoCuHckKmuFJdBB0BKWuQTf/0M4S+
|
||||
mOvFmjHqSOjvAAppAIRci9fcpm2SQ6pDR2RAinVqCuV+Gw+vKO4bArAaYR+kEqq7nBE4rhExs0Kz
|
||||
lM6W7x+EtSQQlXOgTYkCc/TGfPv3BoUkixla2aV0U/Cmyi7zVws0HCR/HQo0/BErq7Jdqw9BuaRg
|
||||
mdw/y7s6tMg3HqwNOLD9yyEpIgn1zAUTKgrOqT+Jzec8M4bGVag4SBfY+tU2WyuaqoFBELA5rC8G
|
||||
e3YT6hl/33NTBiF0hns5mO8EcSzdViJ9NzbOZaKUkXLokxcDI7QnlAgLHP4eWWEp9uj6/9qFAoTZ
|
||||
DbXoOD1X7zEbGUJ8ACwYfZBJRVCGB8272pD/XFAU3j6Oz3lS/HgAJCLgkTcBtdnp2aZL1Uzj5waP
|
||||
dsAZ1wqM0Gf/pYPeoS00YgTityDqzperb9gL3qh6yvJbbCbAUlT7wQqIriak7W/CT5vIKHPRZ+VC
|
||||
7P8g1IA6R/RlOMM1psBWObbHiBFXaBTkadW/+sdheSxY02bBIMRJ9GBs/14qPhBfDI1VDPsT/KKx
|
||||
TnNviSPJvbFr2Kb4iCrroIEBeQEAfKeOVHj8t/LQm0P8GGuo/lVl4Q2npA2WugBBLc3WJNC0a7n6
|
||||
kGtP9YToHGDkeouX4yJFPBEQP87QGozCDiNGQAA5447bAYzwt736gj4A6AUhjDBgIN/OhWUV/o5d
|
||||
rXIy2FRVfBWHgjK3Udusc+b5uu22gQ5aSGRzKMCMqeS5eeTz1bKspiMYWduCe1OiDqh0qK9QU3Ym
|
||||
4Fo7sFJ7NQCRt6bPBZvXPM0ILGvct2W5RQvBZ4vc2EGs0+P6ClwihSSfRRfIbElmsKA2tP8cVGIh
|
||||
sGAhLETqGfmx3znXlUmf1FUAepkv1xcrW1KXlhoyA5D/1DoVtEaubBTHT6gyBLUXAKz/CI6Xnfg3
|
||||
qe8TqsD33DMonI4Qaac3wjc1iMCG1INFCMqkJRhtKvGF11Q8CdJZ4a7QG2Sanz960O7EkksjL98D
|
||||
noKnzbGLTagInX2WNjUiStnHnBFBkxcCd4gyXVtmoRhcj/EEqcuncLAAmR6FWIIGa2t3oqFRI893
|
||||
II+FJN4kNU7JrUof1LM2GfbNLdyMR4w082BpGLukTnSiPHyfSDEQUVtPLsAFetkRyZ2M+lJE988T
|
||||
9+/gvyX5jx1NG0zBzHgoycgrVZF3aEJlT4kifEdxE+zIQCTZpYUcJxyLkDmvkPp2IuLBVwX+t8TV
|
||||
Qv0/fWCdwD2dE3cZh08QI9WzSYBlgGI0M8V91NNF8H9PXsGVbIViWSeELAyqiE0kKU6N3lWIJ7fA
|
||||
nI6TaeRqQ09/ZpgA2/pfIgrUxQp4xKq9P0GSa7RAqTVgUHRcFkTKLwMCC3NT2/0+yJfCRmcb+Y1z
|
||||
3zcI2Ii0uz2NeOpiQH/BTKgdD0WoK12V2e1zqYwCznL1M44LM3h744ARy2Vg6ylRqWGwT5Hy6Ue9
|
||||
uUYURPABfCbBDc5Mji64fBoKEOsPSmwn4V5h5aYHDsK4iJLiyRoADBzu5TUxqkdOGxv+eUG0DJ+x
|
||||
q3Eb0cukyi9iBq6vxQz8pzNiTcwNCcM32jivAedClbtCXtv/7lD550Scj627OTrKlUptnG/VfCZi
|
||||
lTtVxUfNJHOj6RSSevuoDnYCgHIy7332sVJyJENNyDh16b6RJr/1jkrAvdBs8FVkjwAkurvtfX0L
|
||||
UYkkbCSCoRY0dED2kdv1UfmQljnTY7G2stTADHFV4UKbrtNSknwTc0QjE4isgcmrIVH+49Fep0ZT
|
||||
nsBzJ3fYVWdQwWttdZCRbKgE10WyymSese6WkhjhDnXIYXtplAM4BENbz5LoYwlBAmbtP9bnfcpx
|
||||
rcgMz0LYdp+NmxcrCcgOLLr6YyY+aDExIG1peFQQUDjztTO/7Izr0cvnqftrxz1aLn7idfOXCsLd
|
||||
dFlaP4PY/fTyJmkp+Hf1xv5kEkgIKNoPC/uQfZZ5ts9x+kRDF3/uQpri/FGOjFobWT4rAzNElxaB
|
||||
fgTZbvaOFCxrxJVUAWuQIbd2XmJLfqGZYXPuIQ8nBWVqDautVO1QFHs21oGZeEDCnSiKKZl920T6
|
||||
f+ZoJYc1IaOHulaCf/Vb+ZVKTfNWXcgBqeXPcSWxtUWJHFPhinxUTymsP1fNgRamKGe2WNx7CnC3
|
||||
9vRgYwg0U1kkWJT18k4bS+8XSpEbdmBeEeypp+1TZhIBsitrJEoP9kBirRiGIdrsf+zwBfzmhCOO
|
||||
IMGKT9STrKWdXES4FYechVCPxmC1IiuEmvC23rTyhOU+G8Uj0Ty2gDRF/6cTe0aX7e8Zpbsmpj8P
|
||||
XyE0961qM3HCxId9B+NUfmcIr7FWSu+8sPB7oHt+GqFB+H2UFnATyeKgXMLr4+DC+vJyrmcWKmHm
|
||||
M//zfC5G/RqjNYDQVAkJrRdTJilP3JIFFpG93L/zuSjAql7Z3zTsnZIp4YdWWKBzI8FHc9ilHV1a
|
||||
90QTJozt1rsGLnmfD7yVVLc/mkpDqw344fd4HH5metKeOeDj8+WPEuWyMjVLa+kpd6aUbqE1vD/K
|
||||
Q/oom5pLdbxe8N416kAsizPfLWarJU4vBA1NUr6mscyMgOpO1Pt7UcAvZGtcROg8oD+6wYKq/tqV
|
||||
1ba8w45+kJ07N2X5uAXsL+aMpG9o+32rRYM7Hw/Y6m+H0DrgKXNS9WZnBJ8Ip/Nze/KKWUEt7xyc
|
||||
73S2hxYbf20AOKdUlgLiG96Tr3gdGscBtQyeJRMQ3JPFAdVqZ1YGI+7KtkSFIX/riKvyfRY+t/ql
|
||||
aIgKeXZnGRedAfrcTjpTMDoiCAzJufbcFnJmlC3V73qXYQqp2ZQerxJTfF6riaP6JHtxwRX0WWIa
|
||||
1iX8E4gATvFA73N+s9iuGurgELb9COXyV7WiFRiiDtLf60qjEzCZbL/iI+60XRLCmCJbeSKfvaIA
|
||||
G7BGwOPTeSh2xtYXOEgqjmk7/CGL1hHG/81e4ZPxTdKk6NVoQqRSc4+GmRcROcDHizLH+4PMSA2D
|
||||
6/T/BuxS5QkFqWc1Hdjabn32fpn1hLmOhlzFPvkdvrdrcSA79KQ+4pbpzJ6vxxnV2sVJtFl+trEC
|
||||
3/agipK1X03AFjAA84ozmKUUqdl0vGmhCwKTXTj3pDld1PV3dnMOgirhi06gP03StmPrQEwDoscm
|
||||
+VlPnglD0xbpEjokQgMMxghnG/cFB5kYDJZNAiGkCFSiJHRXjwZDuhqFhWODs0wefpM+JHl3OTu5
|
||||
UDsESXtKI+Q/iOcz1CgLu9Vq2+xePLTzFaKzfwBL4+08t7XZHtNq9vVXIJWyt+eqvqmUx6qGEahh
|
||||
u0Jkj4puj67HQrA2N/f63quWGMBcgXDLCt4txDRlQNI1V6EfEqzZNMCFZMDFiScD68lTqQC1jgE3
|
||||
0bRXmdx1GBYMJmvapEHZ1H8EYz2qQ07qUNdsyfSyU6ZUsX5OAGQNp0iNBZTQgCZNbNxLYGxU2rSx
|
||||
QvpVieAH04TR3sDYOf2K2ZY1lU0vJlqD1PTAWZaDaP7+NgON0WG4nrmtAhgFJuJUgWvwuSwURE8H
|
||||
Ps1Teyei6mXynW+X8b537JJx4xexilvfrsziWBe/PiLpqzChLvI0u0vUoBJ/MtSFQphAcHG2n7n/
|
||||
KlFc6ADDmKsQ2HNWQ15tJSSF+VaAM7oY0WhGHeUA9q0Gyvqii25+vwkvgCpeMB6jyM5YHKVMdqn/
|
||||
cpb/vBF+YQMfVId//gH1YIImurOLyZ1VXwMAw2zC8EisFbYbWPjNHdELtVBZdaLqf+tiUEh7GwdI
|
||||
T5ne+l4SPV2vN3hELeuHyNMzij9XXfwtmpDbv5hhzrw8ls9278qslxpq4+Q5d7MklyWp0OHv7dWs
|
||||
NKPRSzLxLTXh0foHfQrky2MDodiZVmHa7rM5xLw4rseV25FWSr66jw76+oqCQb79aMSC8iQ5HU7+
|
||||
z7pdSFCLEWh0qQbgit7rkxx4Fqh/v9vZi065+YRTF65prq31fNx4NZRi/TptS9o5ywYEwbiVU7A3
|
||||
+ZtqbV8WZolpgd6/R1f6yMvvwPSsIkPbrxzOxE38tCICaWJ+6sjMlUROaojEoYWk4h5sqZwXi64x
|
||||
E6iQ6/6QoJqjRtNoCmB6ZbDy1M7ekXIzIg6Q6iHiji4IsKg75YNT4vEan5ViFWgmtTuaqRT94ybZ
|
||||
IIaxkwCh5/5QfqGdi8Nixl0hi5MZ8N2Ja+2xarIGTJP2Zdat4Adha4g1WVb92yUTfIS9A1weCJiy
|
||||
PcalnoxSaGBjHXX2tw+SsHJfZxOUKVDxzoRTw8/SG53y9sn7Aaya2J3qyneTQHpR1xKmSor0FdIY
|
||||
4TFepMTLYuwOJ7lIvWAqnKu5GxjuOmSeU+wEBO1UPCH6jJ/oZ3+4tdMRSFRT69iz0uyUpw+4v41Y
|
||||
La0i/Z0cdMA7zqe13P1dDiyPsIAN0TQ4v7A+SxnDvofJimDRqutSdrEude9NTkfVoy3zRjYLRqII
|
||||
zgot44NXMW1b1zDmQsE+5uWeecdXfjUWPBthLh6401XuG0EOCmMerPO3RTGXaoqCa6xKfRAuaNPS
|
||||
mDUo8ObVlZxuheVJRwdfxF3/vsYa2+GLrOqhMjlT88k60wHmLTYyunIvocVpnlptoVAdbRrB/tnS
|
||||
MazgUoGEy6mqIbfKEkA60kpJcSSxMoPDR481rpK9Z+SNJcx8Ky/FWNxTNM507JNNFynOcxtDLttS
|
||||
pX0SBiVIbbOQMgEBujrauqS5hEj23SedTC4NpIeSNjSgLiMyE5clTkOx5Tle6D+279FHUiKeBTEu
|
||||
mu43WRLRItYz/7QoNB0uTPBDysDDDE0bz8QYvfZ7fZ0EIuP9Ke7L/0ieO36rjY63oFGTIK5+fglX
|
||||
r6J/5DvTKUhcMsfpXbVgLsFN+f0frzDhM2rPH/umjZzSdAdunTxC3SN9sl3bl4bcMzBYXLzlkz5E
|
||||
cyVHQhUBLOfF0pbJMJfyWyqH+QLlKnE5OekF5/a8IKI6Pi0HrUHA0syCuE+8EUxh4BGyBWyYuA8t
|
||||
dvXW4gjF5aNR67Ua9WO4qp/90lWla6VTRgN3zPxjYTyTbUkWejnwekuptP4S6TDnbAMQ3VHeWWey
|
||||
ExoUu3fZtXN9qlaEW2OL6AMtFm4LLI3+zt/cBw3JBL0jc4vKkduvRlBYf59NGyK6nQIMXgZSsWec
|
||||
EZFHdWGNEwAnl25FuLSuLONLKdKOH5mv2Cs/c6ICx5YbIM2FBST5oeAbbCHDxlgLOYhZkXgK2gio
|
||||
B4YFuoqwEzZ+TE8Spj84G7jXj3tfYCAW+j/KLoq+sMRfk7Y2hkoAzxHPX4fYNQ7jc+p173Cpd7bm
|
||||
CoW+G/IZaAYB2GlGPxFsBFWpBw+k/hlCJCxHWIDRCCWIdgoPWJ47M3IVG2s1PqTCWcezF4WzAbJP
|
||||
ijqdRuWsNgKmIOy2rg7eOjoo8V5B2XMhrRHX1CgB6FmlYIwYFO9g4CkQh2RBUWMHITMd0bS0OEgW
|
||||
iBShmNoqe0mvMrY8jlu5tUkHQnUuyDoSQA7OUmFogTs/LmH1YLbs7KJ0ON05lZVjatTyeHSX4y5x
|
||||
ynRf6WMqxZIQrYm49ZBvBKvIWa4HNaE61YjGE/a7RdCI9c0CepDmB4q8p1YkXCp3/NUnjTDzoXV4
|
||||
TNQMJeiPhmloOU3NqdtTui1bspr58H6TbPGVXJ8VpbWlmV2gWSq0Xq1T5unjNB/94xvRDH3Jd0C5
|
||||
5A765BhWltfOW0kAdRxE23Nj40Fax8HzWADSbIhJfAs2gV1CB7QRTCInaBpIMUevQFMNqxw1/ZQX
|
||||
nZXM4SA2f5wqh0d9grsXUXtKXYmtwN6ews+KKx3kbHRJR80uMSdFpB5D1ftekTndGGiif40ZCCxH
|
||||
BYUlc/2h27H/cBVyRbdnnC19jMtLiV56/unGIpgcavthZXJwCr5TcdNgfwbhFSI2XjgpPqSo/uF5
|
||||
WM1vMzXWbsjgdsgRNlL4Ppn9CMc77RvjbpWzyvTICehprQKQeYoOsbPRkUWGaDPkfPNTvjBDe3gs
|
||||
ux7WN36Mk/JHFgAg8q0Kx+KIwp2wcoqaKJ0B8amS9HYv84AM/D9gxO3bG3Nsu5wZPP4vMPuSaLmR
|
||||
km0NFxm+gJoEu04vJ61NfX8DkWojapDtUEiR4iRZfblK7LKl9V8/u8qMDQ7wLJ3TmFKiJ9FNOx6Y
|
||||
RKaRXA0y0IV0bWiwq5xRP4hdGB+W29kR1bPrXwaIp3mLgn1gwmn9g/Nr73yd9yI97+6hrKIZRIF6
|
||||
7W6KPrkUOaR9OsQO5W4noa7XinKdg+YSHppytWlBQlvS1SPgPf6mTCkrVKlh5UKpClGtj+sIX20p
|
||||
rfo8wIwjqNjUdhvjVZdjqTTWsSBg2WMzzsh73ATvRNuF0KR8n2nDWxbU8rH/+2PLCYbj6lIFuOMH
|
||||
ZtU8jUPiJhKDnnBROWWyMekUYw1oiFU3MklT3fEHn/pUeo1n5R38XJCaqLSIZyiXye800NKW6d/J
|
||||
KF+/6uYj0PzbWnyJhRP3NZw4FD/rnR+R2BUWQzPXpf/AcKAz2UKs/jmoEOXtJxWOaFQdsdNQhwKz
|
||||
M6tNc3DOCCVJqeflJfu9vSkn3+mmuXLT+ma4O+abaDYfv+yClA7e3DagvfMk2oNR9dGHat0TKdWl
|
||||
QpRSH+k/sht6SH1ble2vLdQpdnht53TVY7esv8qmwqpKlyU7GGUqCopW2NrebrI/gM+0opwQVJO3
|
||||
3JDbI38eHO61rzUbQG3mCI3gxzxUl4wR77cpCEZtisvRJwQSKhasPxXQk09k+VN8QcC3KtGJbZlW
|
||||
O3Sngf7y7zVBT23g8FPpPrQyPDRN2xNUoiXM7f0jsDsC7JYx/vx8DQQFWB3E8pwF9rs1Hsp7hBAM
|
||||
uPPZxdCub54aoVymYLwWY56A0ZlJXz4hXDvDpfZ7QAdMa9st2dgwIBVHEHoHO9WL2OTlLQ9z9aM2
|
||||
00sRs3M9XI8/DDwlKyIiKpkWHc6cnzSQt9sShoy4XVdGqSVuOaXqTkxco3GaSYhg0IPXnk8vNCth
|
||||
4sDYGZHYDIcyGZ0ARNN994RUxO1d+SBaL8DijsMvE648H+4CbUBQoxLReuWfhNfmqaVpAlTYZJCY
|
||||
kqZn5hikrdEkywSpm39Ie9wqMAEGPPC30RX/mZa8UtJuTEjemYs0LDkEN/XkBLCjc5soJN8yRXAh
|
||||
6uSoEQ16IRdgdq6qGh6cdASQtNG8T30aIxrc2vQfvR+mI7yFKvc922FiQWYGOH5+62M6j5lpln2Q
|
||||
ngdzO19bagetjOlIx4TtXm1DqjaUtmpBGDy71L9vwfazCgBI+kDlalRTn/4iq2QJu0nBieAnPW8e
|
||||
GIP9T9hdcga3omMLo8etAFISVUvpbiVo5XPmeUt9G3kmgDVZLxtEFEYEijY18x4CL/lxoveCwQ1L
|
||||
g/yomSM+OLAxIn4lcsHUWGGVYUFfcPuzHKy5v4Zi2ML2Lx/y2XfqX3ETHvWi+ICf6Rnl/eEzdHRZ
|
||||
avfUa3Q+GQcS/xe44F9+jRaSS18aa583plA3eLPlV0y1UsJIz2hriM6dnKv6lFF7f6mBXZynOolq
|
||||
z7IVgNl1dU6Gxe5awweB3JfAmIJFamz8/AmuPpp0+gSkKnLNwaYcS4DgHIDeayICks2jRacKfKBo
|
||||
VeyLlbIM3QwqU4+s2SU7aJ9C9GpeGvHqXAmC/vPWMaisN1ivX4f8hXAC614ZibDqB+7JAwlaaF/f
|
||||
Ojod7ysyZ5KgnREe58IEqRs72EukNqQf9oRftfPSoFzvY3XSbeM+9QVkdQxPAfav7Dmi9+QViiLa
|
||||
H2DL5j9qZef8so5q1qVuB/4wG/QXmO+XjrhcLF8Ih/odoy1t/UP1MMtUfzZzlD9Eo8DanL1EZFdI
|
||||
MsXpi87Ob9DCVmoU4TLxngj5CqfBmzJcVxTEB6ZKOFwtpcPR304mIpLtJHBVNbMIOxgxQJQqlg9c
|
||||
AekxmTKVOz73KKu9/SSJVEUOz7VggADw7LrOAIvRlP86vlq0pvxUX8Sbwvq+wxMpQq/OpAUoHlmg
|
||||
HyWmCENpGteX8ckVykXqudpAlfYGcI7XqKZTi5wHIpHF+mK773HNMd25O8fo+AhHs6HNfBzeALJ6
|
||||
WxvKSwiexQZQCw9mc4gkIKfWe0S47KcjSHxaeFnXyobVaUieO15oNlZm3o6IFrYow8gaZ9FMbBH1
|
||||
S7kHLqStFizCyFwkpy7Dv3Sw2CvgUrFBMwDaLAhlacf4fLKnFOE5fNJGAvrGLYP+etjq981DgCQS
|
||||
tbLCA7Q6jFkx/+JCLX+7Jo3QgzA8Sa3sxMNrmpuddAR6dGniOKuMEHFICWtVlo51qsnNZXtfPNWj
|
||||
a2TMkDcgAN/zU1SEDQUBIe/EV7LFuFa8h9GOr5Px+bqGDVBRE4gKdMWD5Q2inu5KbR/qx3eNcd+a
|
||||
pV0Yhh5/p7XWNH5YvuD/iXhirPLTvqaCsX7tDP3xvzYD3hSuL8ri6D/xpbbTRAzSlvcGEbgXZjj+
|
||||
6b5zBRTzz/1GETFSWCljSfBfe4BpfslAkntDDHQmGZea3SF7+n6WmbtJeXfpTKR3ijEn0FnM5uPV
|
||||
T27OTMHjkkC8xA8S16XIUyujJ9iu42fvQ4Dn0JjZaK52FjvMalbofYG/LY4sTm95GgfWy8+s7K2F
|
||||
Aa/9RIJ+mfhNb5OyWEa1ekPkAg4BjuMkZoIYUvh9xbOv9fyNK52828TeGFaH+adNDWW4IFyWIHHq
|
||||
JGKTbGMNFtpB1bKrdLZ8lYc0/fwg8cpj0SSBHNEDODiSBMBDDrqsOlJrcNIVqt09bX/6J2+lrKvp
|
||||
gjQV0eZ3/LpFRqHQbobISFk62ABkh5CfNnUs/npt9a5O9Y1VSR4Qn/vvOMpv2bcodAD8/hV3RKDA
|
||||
m0yNdIDVUxScJdEl9FVF//a15r1ag5KXGsA8ciKM9AJn2lRLDdn4U8uM6bh59D0leyIo2dqeunmv
|
||||
4wU68Z+mMPpGp6b8pE/FzFwspn4ALSc413MfY1yDZ/W1viorc/S01VHbaPvKozyN9nvdTQoDKxs1
|
||||
aoAkKsUCCkILWIwKUsxoSGW+FvN2DAxkEkzucLJnF86GytV8AKvE8qXRDLIZxwwQmbrV8nxVRRAd
|
||||
rMA8akMHEEq7uy0u2bw4+FlTdfWl/e1i8Tb3x47M1smLmizXXHoeXmuV2R7jUgyJ9SgZdH5VTiBl
|
||||
1gzo/t9lzDAABCJ2CXPP8pbXc5xwxKISiivRmcjZrbd0pRiBoihuSoIgJxac8DoIByG+gYJ8cFFP
|
||||
fgqwj5RjV1xm+hoB15HfV6ZiEJGphEuKqKbBziAjGouN1ys2IVU9MuThfnegWc7pqZxpabO4iB0x
|
||||
dm97XHavrZi5r7omMxUPMevkXsh+Ekc9URLT/iggHGcq6qmYlX0EG6H9iw6E1HE5DR7Jo4TWV3cI
|
||||
iu6rYqmMWcH5Y/T8bsBBehGOIdsOsIIZvfI9aNex4+22yDLff6fCw8l5y6npnILfmajkv9/y76UN
|
||||
Y73Qw1DVoXEZsMkVuspbGU0hNhg5l7ZL1/wrtMfSQanhDKONY/hI4QAj/ROP7H8sD1+7vWpw+8Gz
|
||||
srQul+jBA5Wy35XxgS1nF1a9bzI6ur8MfoTCK/pEVKecNPG4oKwcpsGTmZBpkhskDES3iIUO9YRI
|
||||
VU+rtyZHfb3D7No4vjb2vIdhzO7xXwTJuyhdcQGEuw3FdVNmcj5gT7Tb7ssmoU2+CY0TtPPgHMer
|
||||
RrgdfV4QVYzDJdBjPa6TowcIZWM1GqyfFGP893fhgjwvrCMEHcEhl1JjE3zd4T8HlHdnDVynNnt8
|
||||
06JrypH6863dvy1IPopi2RLmw6jT9243fTEJ7F5Ja6rlxCewqSZ4bL2hwbMiitDJGlmv9KX7T6tU
|
||||
YrDAcR691uesbdLPmg4LxTzsb9r7LrFH4BFH2wHkeDQP4Ukmv45q8FhFFDgfgYk+mtwb4KRWay4E
|
||||
eylc/Jbu3qVuB8wNsIgDiEXJZWkzZEI0Nsyi+CpUoqQh46hwFLYTZg1LVaMEtMDxB/qjItG25rwT
|
||||
MgT03fP3GOykyZYyOedXhknW865EsVAxuttrZ+ZNBousOVjrHlrAyqj1yFm83E5jtlQtwIWpvx4K
|
||||
vIFPpKojswsQ7MiMP3+ftkHu0usBa6PfPQiBOyREUH9/rYIr5Pb28X78rpzDTrrRVjkFODnJTMyi
|
||||
Uq+z843TJtwyW/IRCmuMDs00hOx6I36GnvOergDbH3Oz3HoqgTadJkx8CL3x+idlNsZCbuBNCTg3
|
||||
lq8HbWHefQzYN+rY5B2t5C3ISPzxQObKRsezosuIhTy4nH2BNxxN9OFiUYYx94GJWclw1lcWQKWU
|
||||
SQ8S5EJkz/PPDOG/ItOd2eMerwHNMzHESquw9iFpRFCerBs/0KPDDWwkYxLZ5yUFYYvSmysVbQID
|
||||
OvD+WI/AiNpiDzGck7GXQdOscHzFni+m2wB/7Z257s71f3zkRGGn6dfPo79mOa+w5OZPstvYmosk
|
||||
29elTy/7AKY7RSB3ytU0oX9bKOUQURUBlW1T5GMSSqRVemQ+uGuv4OxXud797ZTN4yi1iwkzNQbZ
|
||||
fBkEm2DT5OQ+voWgK+XUW75Eqrc4YSBD3YGCPHLIHsWjmftqRZeTIjv1ZdFNDZmKJcmdTN2nVyiU
|
||||
cMriJK1I7x927Blm30bLR0kkqwLqco4MWwCpA2++vCoY/9Ba78uoDIEE2/u5OrxFu2CU5uhMilCW
|
||||
kDwTfbQz1TbxO7qNyJnOvKvorZ+rK3TKt/HWR5Xf/wpi+ca9F4VMq3o7+kxPUlVKoMwVlPAiiJxO
|
||||
8NXELquMVCUt2hHWmdXmLqKBqX0D9mjYLck2qMBufZF1vaUzqe6JYioTp4ji9SxVv94O96Tu+qlV
|
||||
alivv+XNjfCtHJd2n4kQL0Z9Wgi04EZq4biLauOqH2bJl3Q7H13w3Ty8IAOjv38YdSuVORwjQ4Lu
|
||||
Q5mtAfDxFFTIfE3LKeleemtCKCdEfsj4yyT42qPWMt630wJGiSED1O9QIEs5W9bgetc/QYaQlbf4
|
||||
zkgATDJd9S/iHbyboKaBVf0YI4NYzRw/AGvkYQ2Z34260FMsr3OCjXxYEFqJsqSuJtP59L0FHxbr
|
||||
b/jx4KOE6C/VfCT6UjWg15/9+1p0RXHtQZUXWzaJjKKIwEAlPuqFbUrs+zr66cG4zlt88yFeDO3C
|
||||
6rrRd6lyd8FzqvZkrMg4gZq2V+PYYDJ68obyGTlaU2zpw6Ii2ntXZgex2MaXOelEXz6MGgRct27n
|
||||
lJzpblrlUiWD7TBjqukvrop3MX9+QBOF+mKgCBfgxalpLtRM8fNNI1HTYSd1zHqJtYebnsVZ/82c
|
||||
5yH9o+T/mbllXgks+jK8f3moGXwPpNcvnrk7skPzRAQZHwfZ4wcMgJAnCqfXumNHltAklJnLDp6f
|
||||
WivwZnEkx5Q7UBy0k/CQ3Cp//4qHv8KdXfFssK1RSNW63UL9xIe+wIJVDHh4gybPhnggUDIZWInf
|
||||
vLOGNKrLQagWc/t41eP2otiLwDJ2RB3eZdy50y4ZCwvCyfJjjP1O3ILtx4rpKaTiu7/uPViVMuAJ
|
||||
gvN9IrVQWVQ0N+lNL79rn47kQ79WDyA1n6N4wSW8tDNf8bDDEzFirppcn602RvF/66EY/0Ns5Jhk
|
||||
wAzydaMlWjUfk/MKPcNrw4lyH9eBqulw1P6+grjXoTIagSW1YmRr+bOh3vyRk4xTWSWtgL8UFRZc
|
||||
RNofcyx/dEr5XJemxze/lF0ZSTWRCr5OcXGgiUWQ4NZ+uyJYd4CKSALo8J76bEQdP+i+YnQkdf4q
|
||||
DcvxtSpbnLkcTyijOj6Cb9YJY7rcR28DmD4/WGNMV5C51K+SaR+39WDU5y2sBt7UB1q2n+4hqVB1
|
||||
AnZ2+tQWsDTe8xN6IykwOnqSjgqy4RkT549nqBldpd059umxbEtUrJEimYU5/WsApfjm/4D/PZ2Z
|
||||
odq+thAB8Cg9UqDSNllYT2GstkyXe3cFegpvc9daYOH34PgGe6xB4kFAVvR0zHqe+MVn6RxyP0C9
|
||||
QCX0roRnrUcEU/aioZyYLp/IHbknYcvsYKIyyb4DHvcjtZ5STT9eG808X+gJC+z4psllvjb/nlRU
|
||||
11GFumxnuZFkpe9B65Lp9gsyhjut1zfP/TXmImOdsl2b/7U9dbCVZGAPntCaKS79d4BWALd/yLbo
|
||||
LB0SJHm9yZlxrzdMRZKNrzMFWcQX+ygnYfrjNWNiijOovTEGBD1yTAxQyWUMIcoRPFCLvY5UQLNK
|
||||
a6iKt1aKCzXK/GroxVpC/NvAWuKYEPpr6crRiHlEhzimnPSh69UKwk5IUY1kBbM8UnLmTfh5qQQn
|
||||
cEFH41TuS5MkU5ch2AxhGnjGQJyMYOxhkhYjkYzpoNRmcIQAVVEgUVknsLkjsnPhoH/55TTKHjCs
|
||||
oFx4PY25CkDaFhU/oRrt5kFk6MAEOYBjSrhtbw7don1XjCb6sTP8DhW8liNROjzSFF33vOdJNOCl
|
||||
6gtC4pPHYWuQp1uUwGquY1aJ/Tl601jfv9RR0szH3zimHolnue62OpJ7w6EOc3Xt8KPi4bA5N3ZK
|
||||
QqFt40S1wGSPVUK2IciioiKHLK49wHRx4nQfN2mbmfGveXWa5TwlgueTkiK6ZNCtz2eI4vqLFnfD
|
||||
vOdtSaB9zymL4qP4HxQeA8msvJJihkq8gWiuQO9UlzwRlFgqGH0V1bvFfVIAYRReWdLOr1YqXCFP
|
||||
n0KN8vDu9Unl5ZEqCgQ2jIdopNe9Bm+/0NEHJDQWGgaGuVioxMJnMoi5d8kGxQ9c43dEhkhJ2kZi
|
||||
mFgq6UVhq9PRmEElxgJiPeWsTF071UZ018ufXWJKGBxB9spAAg3T4ePjIwkLkYplguKofg7OCkMy
|
||||
3rEMRpZInhJLJL3aR+lA8WfYvfugzWbCo9AnIpKbWU5RM/FBf6xXzUh3qZDSoPHyOTAfPeUl2FbY
|
||||
75cWQWgzI3HQi8U7pibNbtK5e2c5X+JHKdowTDiji/ciRES38coIrA732q4jXUGOxsp+Zc+/HMzO
|
||||
mkG8TfGEHRYDa3v0wDU8bI1LRmGHsj4Kb284cBKkoMxB+1jXY2nCaWukGibXw9uashVoZCKibycl
|
||||
OWALQApGhK4Gzq2iGki5gOWHQXX4c4OVZawsTjDj8HsQK7I/WV5/Bb43Me0C5V9yCfbwbFqbCm9d
|
||||
3rBz9DYvkOIfqdu53/b9+3E66xkrP0RN2v73gjIeRIrbcNYJzaolx2Pzkj4v1mBsHflDyhRmNS5Q
|
||||
hlMvQtyKZC7qqkE+VSps7w8KKn7aOjgaeujAyePQXDyNbCxgs/B+kW5VZvtQjCZejBjZZOfjttzO
|
||||
MPqTcpx8o6m+dDcjKH1SIJaDDia89Ktv8Lhr2UQYStq7CCR4UFNkYNPg2Cu6QZNK1y5sOkYLhN5E
|
||||
hE/Zt9MStIMM9Zw5E7fZbMGfOQVf7TY68Los5AvAicpD8ZcVW6WWJDq/J30Og9sRTs5CX5Fg9hyN
|
||||
sbx+OOtd7PIfl9r3KjUzeAu0I3HUjHnkf4DdnYop2joc2RIU3cqVAVNCbEru0kVnXZy3TsMl7PcW
|
||||
8mooIShXBDN1NqiYe+wnRPskcF5MupUiu1l1Egyo/xZUJcWiK0RSWUCWwPP6csqqNd1SIMJnG0A6
|
||||
eMLb25XpLRyi4KP6m/1+aqODrDh7TQy5YK3rzkeOsm+YfhP/itWV1dyOsW8m7sSCQBhxygrqknRr
|
||||
T9XOFF3ftOpH95eROCHR5ZdSg8IbzUW/IeP7Num1gW89bwLNr65Abvt3xKxyanems5UrwvQsctJG
|
||||
prOVTdVd8dYnKeQEI33M21Babr/8PVz5PFxLXqnIzprFIpHTiieQzc7WfKvIc2ofPR7lftV5PUoT
|
||||
WVXb/LynQn38A++0BYTupxEyOTDk/RucuYZalTS7uMcyvCyyeyC51NAk5w4rW095icGaoN7TvtbS
|
||||
OXry+zPmTdt+S5moIj0eSGoYrD5aU86EbGN8+TL7kHYxP8GzAXLpKgMwgi4wQaQbyKHHw6U1vOVu
|
||||
msQT0ODG4di/Utv67CxOXndTMTWrQIG6P4+4RnY7isyoKnIX3Y7XyP9/u8swh9XenQhui1wjFvI5
|
||||
CRkg+3Rgp29a38Oho7t/kdVjoEWsn1Fo0KzLvjSBjJR1B6MNTUo94nyH74IjiIpIO/YN1jBUBmDz
|
||||
3mwMtWyB3Kh2W9vs5g1s/IHvLHuYrJmO6eygjYDJpPpCeSGrO7xyRUClFS2VxmnwQALOFY9GxZfd
|
||||
axyNj5ilXclUPgiw/KO6390Rg3GmIwqk/0H1cp6BOkLp3yvQN2Jm5huHn77NNekX6sJNvRYlpwpL
|
||||
3vhgpKJ96apsQ+0etb37udQy81kwYQHykvLsMFdvv6DviqrmbTj8tX2y/UEicLcj/O9ZXWaAr0gP
|
||||
g7pm1dVqhgoaAuTYDUvlY2CuBPH4nHOCtJWarBPy8JdNYSZ16QJ2YmJMX18vttdOuzzaOB8CjncS
|
||||
Ku/qwfKajkAxm0ye0OJqZpzOKmWG1z8yB4ytc6CDsc80XWr9T3AHGXh2KVCc1Ab1i7vDMtyiCTQz
|
||||
q/KashOfjE5qexEylW7aSSVwQRu0WjM5Pt3XyKQCaVZk+YBjrN7KttcD2ny6juiQHa1bJ+RJrleq
|
||||
XJ/2tOo1iWVt2LQmkzSlNXDNHRnskqy2uE6ZWv5jfMKoOkJji7OkHbdWtWWLsT/JeHOUu9lz0LlA
|
||||
P5wZBkNaVXqp4z7mtzLLC2pGJ/wX4oLnKkdYP9C01IiUS0UZDZOvTcBSivR5v7JG/0LJy+1iER9C
|
||||
rh/lVDqHqyhVLyBlRhKcEhCJ5wEORti+os8n2kdAEgTp8wGx7ZvGhi0J5bChn30jm1aMeP3uMvma
|
||||
An7PrfMsYlG2Pkven2yZAQhjCZh9O4jsWUxlQwk4/A2pArSZZyyi+ILT8jo2vE5763TsYRGp8aRX
|
||||
LKcDY6lu81nRniecFfptJOxtzHRoNvhW1bmfMEPDSbg4jmIeNgf1ofaumeqcfcck6sikDEwzbzVr
|
||||
KOuaKknD1CIYN0aHz8ixFJSCyhQ7B3n5gQslrlgHc27MjNnqIJGmG9X8WcYelnV+AXKkHGtaLMHX
|
||||
FZmkkPBYdl7HrmDPQeoaqgUe7eoqP4T+zj+yPtasHxRWQcceKBOT5EAgfK0l9hNvyWqyDF9Zieno
|
||||
hXO68ymdtUAz0HfOprLFptmImG7pQNS5F/ABl2iYtvIq6I7y6OZL5saC4Rfbb1KMIhszRWW4Jhxy
|
||||
Ltpzd9QtCyp3oU2Evjhf7ymI3kbXpQp0HcYz3mJToy7DAiP2ClvXWb/PRrHUVjzPig9XQXDuPZya
|
||||
OHPKl0Du4bszIQviKMS9W0lQmzzpFRnv2i7z/SWBzUKP1s3wl9r9KoTfWtGZTJ/ph4Kz8l71BB6z
|
||||
8r3+Yr4iRZYHCS4t7JcW+uEGizZKGKWLJ2MlSBQ4NElnO15XhaosA9gipf/iLXa1GuAcadOFqnE6
|
||||
EUIseBp9CYXIMFCHsqqdWsrY376GZrDDHJ9sN28e+ppUK2cx8EnVDNzHkrRUaEZktSchTecclgzP
|
||||
fw3ePYITkVIEeZJocjR8wmVY2DZ2M75hh2TqGucRBx8v1d+xH7lKX/XODRexsFwDU5ihuBKkI3oh
|
||||
Eq8PfcU5nmQKIMa6jyLc0rUyxwoP4csRn6zCaLCzVpOi4byP+1D3XM2xZxFk8ChWJCuxthqZ/q3g
|
||||
7WrGmZBw3GSyV3vRZDs5CA0wS0+jd2SprtaS4bD4MmYrHPssT+80+3hqePxlrRhtPqEaaCtSxPBS
|
||||
oSjKko3jQlYwEBlcKyKqfUyB2PvNITF63k+zYFe8Eyll/Z0vtX40NIM74BeN2uF+iJTutfdDV9/p
|
||||
b40HkVvHghqmOEXWqrI7i8ih3IuASDPGVUFLVyd3cL0ZVWhGHu6sprsmFUO0bOVu0fgbxPGRgvCD
|
||||
mjjtZq9qmIdYjN3HyaYsuKQEDz2VmcFkkc3roheWM/aDuKd/nwhUK0ZNngqaPDKAXVx/ikhe7GnQ
|
||||
ifLF/8DzMvA9nOLIyrjwTaacJI4tLPO+/iW6XXZ2AKAOwjOIjMvRbr6EKERfoWw6bL0vdKkAEhdi
|
||||
eYCguxrFCu+KhcOvD4np3v1xA3BCOREsczj2SO+vnRx6sLy8U+IROKcCVZjWCQbT7Vu13KpW7/f6
|
||||
rQQa3spcpT2WUacyx8Y8dg8XYDPauBX5cr2+Y2yQH+Rp2tJ9F5R7+fWG6ebeyLcAaV1Y0EB4EAQS
|
||||
X+Grj8Yc6Ua9QAa0gJX8lTtam/vXszSMf7nZG4idFQj2AGap/nV9fjz7+20oi7ODodvDNU7Txcr1
|
||||
jzc+KfQ7avGocpjmunt5rRSFoQczunp+DPMFneRyWZgjvG0q5oBZMnZbkagUK2hAEUbWgUyvRe/v
|
||||
8DOCbgi0s8y/TDGyVnYqwSWQS32bF2T1uiTOrrpJ02BXgebI2NHIZ0r3DbMBosN9aPiIaLth9NQN
|
||||
WITn6dPlF9oZSF2ZeJNDnUsAl8m9UEf1uAjEuzyEv0aJrQWZXXmFd4URk0fJPf+h7TvZsfdOXtxk
|
||||
Ev9W3o+RjCmeO1qceXShknO3Vdua0w4SliustTDMFz4W+D5rdftRZEvvaYf9JVLBQNPRJNFRkkN0
|
||||
oRtuYSOyluHaV5H9ZsZC6CQz+5aJZNdA9sCBzGNq57K4ojrD0o7mdYyb//2fiAFUwy/n0yTMDM2F
|
||||
/cIdDRSnu+AgMgOT9ZE4rP741RpfDSvP8UnqTEW7qm50cEC3bbGABU28D36walorftvuFbPYNoiG
|
||||
gu24QabRcwDcvWVeSBxEYHSr9je4n0Df9ldk4D/Xtrv6fJoGncR/7YeD4eM+kKX5Rbqo/8eB/aST
|
||||
YcVOvyofIfYSkT4s30mOniE9r0w06KU5mXcmbcAbR8eTPnaOjm5Twkvh+OYeGZmV3Z15tgwAfmXH
|
||||
9YmIJajFOjI+jcF4ap17ZRw1NRZIBT0qz2sVKfze5IOQZ+62Xfo/AyOv5gKhbIvgsstRJs7jsc3B
|
||||
lmVn47Q99lYDp62/MVD7pq20S8CovsiV9QVe9BdyKXfLJMVEuKOVxk+U1yicc5mIDDtVG6nQMWtW
|
||||
VJz1mCVYfZ5jFnbUrFQAwL0xQY6QhK0sspJ/9pdh7dhKVNQ0bGgxjMjfwWJvkpRTTKCNTbYXSv39
|
||||
4QpHpYaUcsSAxofpfRh2pw6MTncnpFZf2CZXejX9VfEgP1A03vpv6QLeYYEmd2lPUY3MyQxLB6NG
|
||||
NnM7eacQXmlx34D+rvdrAZFSIA33XHi2ktvsfsaCG3mMV96obfqYyrz02HmDTI0h4phYfDA+bXRn
|
||||
n1VFxqbrf87cBlL+eid/L69ixscQBM0wMc8iriB8h/yv68Pk+8Uo6aDxEDTyCwlrRLnDIUmAccnw
|
||||
Zokj+v0H7kpS0RUmnK1fzNjIj4GvW0SRXB3ZZ++bmrx9PzlDf3TqnzFz7RieUYL3S8YifB2REg2l
|
||||
LHFXjMUV374E3Jp2imdigolyLmd1k81+hb426KO7csxOQDkjeiBR7mWaArwGxYF/zxUqMjzW+XWZ
|
||||
YO44A75uMMee8ckVY+OScamjh1YptrGMxDxlIeyv0qAw0urXtQJH4jCOHXODjRXBjDJhTcBtGhcZ
|
||||
Bh17+TyAISJHIqnF5WFcboflcKv4+vj1eDBsozv0FXfzj3XW6KLrrl0kI0JWkHL+rwRrwxMZzpRq
|
||||
iQuyqWg0IEV1yRiN7SaeCC7r8u7PW38bWXSf4Kd/hUmHyypx4l1PZR08dIo8HITfzTt0APVqld/q
|
||||
wmy+PHu+gcoVzthEtMijrjmijXojPtseZ1x6fjj7cVuewLCaEFOQ5ayVuduN8a33BxoiofYzDY8u
|
||||
j6XMYNI48dWhHlH2FaRyNps+jKT+FEarWnUBfLIJFTNTFGfPagjJNXPXKBcuqFcOmUCE1ghWzZZJ
|
||||
ML6xjc/Iyrp+Bn45queRxWAn/cIl8Sb5Izhiqa4tdrlq+xCnujEhLo+tJefKAe33MocT3UWeV8ba
|
||||
bvY349InxWy5D8P6UvqGQ4UgVME/A3dW4XRAl4bN5AsneQR+aAfWSSrqyN+ZPpN0L9Hiympqie6F
|
||||
llcgMXVETqPnz+0hwiRCQyJ1+ItQnKswFcX4Hxm9k3up1aA8PCnNoLYNkdac3J6DCid6kZXNsxqK
|
||||
srt+6UxZDClaG+fyMQQoRl7dyYwKI1Q7sWNDgzxnmS5/qas+KrhY+fNVzkNJ+EqJYjhSJxyjk51L
|
||||
7F07I7yVEmbBK8l4S5TWJ7j/wxHWjRLpSOLZ4duDSQas3wEMWdKTgMZEr1TrW6I7qXA4S64cxrBi
|
||||
x9tSJ1fJdAP1rikF8kmizcBByMtZ8j6bWd3TbKHnsLGx3kY+FA8J2mN7enNCWUhiQk7sATiDUkTr
|
||||
L+Ow6xTXkns/8oRP3Q7V3K0LdbAcePIm0EnJDqmZARLcUHLgk4OUsEGCdbPWy27yzF2KOGfliokM
|
||||
795tyvEPLt9arc+1Wtu53foq2T9nyW2uqGS5E8QLkcbD2APIdmaD+nYlg73PTaZc2Of+w1V7i+XD
|
||||
OsJTKqZ8mKQIlqhcEacNkysWElJMhZv4y2hu6TWuvKP3GHExskuh71bJo7qd8cJeN+aJxI5LIJ+N
|
||||
fS2sG0FjKHASGg02XVyHTBeqv3Zb2BOApvsToyEgGoXLxaevs3WVhNzhPjfYyncp6eGZ5/RFroNl
|
||||
KUkQxBAVuU//2AWtWKOb29Bk6h4d4y6OjM7v5sDgGiIoXdRLLikkStbEi3sYiM0Elo1yCQdPsmCj
|
||||
3hzo0E424TDUX5J9e71jUszmjECPlI5aou27ohuF5tSJN4990MXW8iYkTTyegfaPQRYJMbsGUZ+8
|
||||
ouRbXMHFW8CgEOd7DUhz+tIRd1inOXKOPAgkeGMGP3YWGUpxSKGmzhxB70qV7skHn82lb95OqhUm
|
||||
ZUtBGR7gbTuDq3jcFDKc1Jw7HElRxXF1gTvdkSwjCtl7ZL+EhTBrCQ552aJz6biU8SSOlspzMVQC
|
||||
aUQrbqO4OZb68pK6dmjSreK/sqwxliYqt6MDgO4hshkcU+kfpDdrQGvQuEkpfb+W4o83xfe1kMKE
|
||||
yZvmINcFuvxSx9T0pCQlBCZJtK8eEdiSt33dNpj9aIOjj89rrj0JExS37yH0HzXF4IzunFfZU2pD
|
||||
ojoxNSxBOVySWDZoK8qn5+zzDDw2P78JQ8fWwhTofdLEkSSj03ttEyyyBCt0pYaBYlgHobh/m85L
|
||||
/6uS4ovsyboHYLE6+EpUI9o7dQ8aPFcP1NUyJkTfNf1/xrcm0U1LFdBcazPx6zZTGUw4MmlcQnpX
|
||||
Qa121aESf9A+AIlNQUQ9BHFizfcmhqODgJmdm0MmITY8W3YF5wT2qoquYT6a1gad9yYgiaqKTEEk
|
||||
TO44C65MSF53ohqdA18k50daTWNn32+czBK6P8+8+sunqwnJzTa0eJs4yqTyuxSGQ6g2u80Oh5tf
|
||||
NVrrcHMfPcBIdlYEq4S1Z/terGzM1/Mql2JnV3/Whej84qAfU5hs1tJydTiIGVAj4nK6lW8IX7J6
|
||||
eRATKrqpe0styU3PjBHiec4FLETxmo2my14YHWyL+3pP68jMXMYy8ZOyuhq/QUzR7lWhOtAsJhsC
|
||||
0jzG0pnOzkosBDt7fhGP6KsJ4U0Srl1kuCqDUgakChAAxrb3dQjekCAzDto/G9m1uZJ9L+wtzY/9
|
||||
EE7+ZClWdQihNbflUxS/VDugKxm430XDnh0EAh0Ym+BI93LkZhhmoRVSssgCWlgl/8+NlNk77WFA
|
||||
pjoT6UlTbowVkS/KIGkJMjuU7lDU+xqxJ+AUdj73magA5byBe7cOAOLwvHslpB0C9OzWz20ZgMKb
|
||||
YSEGA68+6JoI5UmA5ARX7x9ZjAS85WEXunEnvNBJ3zF19D9AvWIZ8weDqkJp9FYBDPQ9E4kzCRkB
|
||||
udlV2MQLMWF34A76/4KpG0NcKVWdUX+HEBLm5EubKIpQ7eFv6c3uBQctMZEq+hILcsDkibKZrngw
|
||||
Xj7ocWyJ8igKZyBxyBohB34Irfn97LT18JjSSFlWI7ShU8B0mSvF7y+mNZ4KDBWj66bRr6OZ4LdB
|
||||
14ERlcvXrNQoQ7lHI0jvciTViGV1kIokHjrordMV4Zk134hzDyKjxSF9gxHJFK1ThmQLvzAqCy7F
|
||||
CbHEarlL0hCh62RYdEFtlQlEpgiotIlCO/NuQVJsS5imZycuxXQ43atblfbTKTZgtlVibtfI0lef
|
||||
EXvCLCKZjErqwRuaJQd9tTRVfTyNEHcRX9+MH+yhKDRV79Ys2RyVF5rU2qh4EQ6s4YMpSLPVGOCv
|
||||
w12hKTB4KVzq69A/nQxBZAPOtQkX3//JLBHA5XVw4cw2Af+1URWlbacMgddw2AI1hOA+n8MEpNLG
|
||||
R1ARYi6pge5SU/4DJa/wqt48aGCf2fRI+ruEsKyQ3BMQhl24hjGthGbHTNKZ8lP+xR/RLkUdMpvZ
|
||||
nVbaWcjdxWF96LcFLHGFxmrqKoHdNajrPHsCGyVecHJKvn1LZzNxUvVa2fqOenFdJnaiFHuN5PQi
|
||||
eat8ej6aB4wa8YqtsWG1DtTlq01RcU5bPJtFfAhOOuaeA675JWR09YlVBEX9ajD06KdX+w4fXw4T
|
||||
cDYUotNNtxjjJfeYod9PCliukcvHbfyM3B7dGfEwUMrJn91ZQVcZ9hFuUuE4MbRIoaqCYrI30J5/
|
||||
MRS6KbFeS7JtMVn7qwMdrVMpZiV450YRT8MOkgrfzZy+cExGUueX1Fv0fZPsuW3TcvQ2nWNNttrH
|
||||
RHQGsEio78mSxN/u2Q9F24srqMUcXftZQTt8MS1IGY54ja9DYUR+NCHk67hC3Qfw/lL5ocNzFAHW
|
||||
MFLQFIWMAdUEDQ9ykVZKxUZi+dCzlFXnjyoCkYSqmRweEF8TyiNlz1jJffzzXCGl8Eo4ULPVQnAN
|
||||
e9CbBbvsnpo05hK347OxSWGbY4rf1pPpNcGB/uuYodc1LAHRQl58XIErEHLnnj+wGdmw1t4HwxGB
|
||||
Ks3Naxd9b0lj9l1mR0GfyQR2GSzCi5zl6syqvTGg5hTs0T/0BJ/HRhnedHqB3c1TK8TS3LZLycYU
|
||||
r4qtZqaQZqeY6PDQ5RJpgioFZsK6xW9O8JQkzoNwAskR+F8NUHyfrtuBWC1NNXUV5rt88vIUaUcB
|
||||
T0a0Z3yAOfxvBi6mDzWVmQkN+LrMcHOuJdxBX7ClSsfjRmMNdGp1BD8rDc40sxWiyA2CWpg661Cl
|
||||
kySzfkeXFlK+aKSA7wtaApybyuT8HX27Bfd2mIhebCxNry9Q4fUlOejpGBw80azx5U4Y53fgbTvo
|
||||
gF2QA6Ftzex4q9UsVamZ01GDJBvttn8x7iFllsCBGp/Gvu64KK0y6Iz9fNLySCSm8Eazoub4mtDo
|
||||
I4pGvqGYKY7wW5GntGOgD0KLItEOob6eLMb9O7Iu+sWofBk/wLz+w3sZ+HCr13ZmX/2bc5MwzlOG
|
||||
zN+EqPGZSfb0x0FVMVZ0UXQks3Twq1mvgrhCbE+NgyM4OarxmuwsZQzq42y5pJrKjUfn4/Enszsf
|
||||
8O4cgJAeIUkc4wierWBbOmfU8Vd4RrBEicE5vMVImP7J1j/810e2c+vGwxyrbHA/SDqpUixtsfDU
|
||||
3v3zOfJv/FnIGei3hV72uf24gILbc6CdjBWfqsoVhbOSJMIyE3A6kELw2pFfVSDlcK547SfsZ6O8
|
||||
2L7wjOyqEq3xxDFPqQ4QINuooMdZywaH1KrYfYJ3cfM1eRQ+yagusPCKzY8JwGMvZOkWv153wVJq
|
||||
fRh+u2cus/eQZf8zjfqEv/o7YhK5TbiXbM1Q1Hsd7TtFH35CWJmjYLQHoTiHNI9fHy5UIXk51AgF
|
||||
Wh/bmjo96NbF3mBDJGEGqagN3O24XsU+6XzzHRGJ9Osgf/VYsn2kS77WIeOPkm1QMHca1vULOPJ0
|
||||
Nn27G0sssmcmz2RAdUUgbyTHoBcwofgb1lLsm784YjxZ1EYJT6aLIer34+INOvJJuYfKL7ja71qQ
|
||||
FKh/ukOCMcpfE2qFgOYdFZEdg2GcEsfdhspX9mQ4dE3f92P+NNq+TDkvyi/jxxC/ED03dQdRCJ99
|
||||
uXG1IjpKhqO1o6SK2tIFZfS3epHmPjeaKLivO/c5YQczlgSVXkQuS05vkgPy6uv4auxktuWdCa29
|
||||
dTq+uWDA19NK3NY6f2Spwcb0AvB4eYn0mxIk8QSU/RMetX3QPyDyoYrtQ0dZC01MBQ2ul5NxF6ia
|
||||
IcEFRHjTZXKM5gpWGjQOZXM6iKFcUZ92JzKuz28SXUEuB1zfvgEEfomMn3A9J/mwR4OH8EuTGi6B
|
||||
PaUbpS+mfkB0MjgY1rLIUeZ+SoRzgDY5oXnKw0YBKO3NypyoPQQbrXgd4oZ8OgGpWk0gOQasna4O
|
||||
r06tC26KblLGtv0zyuca9lCq38/Gmhk5Lf5tb51Fic+I8qpElMiruyDnRUimQ/h3rwMq+1nWEG4S
|
||||
GeAOTXEYxuPZy450XD6nMirZyN18/h2ZDY22sn6WfXCIpGsAJuzW2fvAsYjpSGw3RQjqp0BqgyWd
|
||||
fKkiGgGBt0qcVA9gp5V7BqXJ66+LajVnhO0Q6ey0gRlaj1IB19RV95mpksgq5iTs7ZtgMcRBN7jT
|
||||
udBWbmo9YgNtTtmqCbjRh8y1sKra9gwctDJ32iIHNDMximrU7pf/sbxSZlK5kIjWPGggBNBMTDU5
|
||||
sxdxBzTx8towSLD05aNAshn5G0JYWDQKObWZ7OEOJ+333Rg/mY6RYdKP5TLGvXkWtDM8yElsRAyy
|
||||
lI6yGrpJ9muDesQAjBEXJWMd6TncA2269QNOZgIjlwnzKIq6sNmOAttfVq6CLtlj5Lgl8p6dmLvA
|
||||
ihwmTxNSo5QlQmblxKJnIJvurBz54TL/SwWnKFXrKnw1Bx3zL5O6+/ooOOHbGsnAwmNEjQULTa8O
|
||||
+eBxe7LcK3kzTdEF0BCK2zttuxahFzoPrtcrVWeAp2k88t2Ui/X4QrsRL6pVTYpFfHVI+iQZwCax
|
||||
ktqfru/gc1438ws7pglSwH/voBz/LFfwu0T6eeOMWnmsJECRqwi1GeiRHL71vibsvCh3S/S4+rXJ
|
||||
Tf2y3d7diobEW+n8YUpSKhLmlGTARzozjrn3yi9AfmctsXxqvkJzlCkLaD0OlKN/N8lydQpeOUgS
|
||||
WfdXyGtXmWw4QOq0Q5SbMw6TTsotq6CLXHRBdqvAA4aCW76IFTiR/NPKHLRiFsE7BetDFODOgJ0p
|
||||
InucYOvOL3WLvLahV38i+Pcu0lYNb9eRT2aBD+5hUnC71BfDAmstqYk7iAURxMeRXwgBao9nmJX4
|
||||
qmBPntuyFaGhScCEZ89USQuhYdk5I1ssPAODOKdAXpkgmB7FZqDMYeddjK8QXW92p0Efil/ZSigE
|
||||
a2eiT/FS1MbvIkCFuLlIFGhROJxvfD82eZeCZgQCaa4hR3ME5TAqEB2VbwKTCk4RFf2D3cf9J+//
|
||||
kef++ohCzF5CpsXwxMb3TJ0EwWcevDeeL9iSBTHHzvZMkV6Ifsm5wio7aOd4hXPh5L97pLWwzWH0
|
||||
R4MPdVBAjtf0ebX8RicetKTuTmj9JzrZls1499Sfg2ajx07sqCgoEF3zcRoXYFzIQuApGIoIeHd9
|
||||
yW2qxQsgg8tYh/1MRNq10N9yHBdDOqB4V1kG6g6cwYATao8s3ESMxFJPtYxkJFfsLRnIbuCyt6fb
|
||||
t9vuZzp0+4M30vJhHmT2i87Av3x4WJqs2tQra4OjWDeWmyIqOnhDhTYlIq8E8qktTW3QcO+RN45n
|
||||
Oew3sstyWN0MJgF8w9GalbehNRfV22/Uhn6FmRLZfhm60w5zlhV6BEFJlETaNJbe99iUAjP4H5F+
|
||||
Avtai+nhMOqeHrBK/Ozf/LkqCL4ve0c/Amaxhd4rHZenZYDnwoV5xxDygb15SUIq+0paqaaHvmT2
|
||||
p9/6Hs4HPHWHiV99cBiqdk4jSQoXWqnfJN2vqTAm+hC7wE1ps4lPa1hWTRJ+0fIuiuiOlczXZ9JM
|
||||
lWRpMouedqj7x3YqCgg0Kx5NMLuBHDaoa9BlbrvG8B4NOfGhS2Gizl2GDTDWZ31TAkYmGOaDZJCG
|
||||
gOPDj8bnaLZUwPC9myW5uh17a7CSXHRnjx7CDZ/fDo1SP4EaB1a2xZZGvXbcNa13uN3SIdSqjub0
|
||||
BtRUmmd8QAgUHxWH36egHVim+dUKl7rgS/QVER5kiWRnn65mHGOpt/12J65uXJsYa02AadvgqIXS
|
||||
DvJNENlvVRdnask4jnYXPaKnQPyApd89DeuvfvcAklkYuA8kJ0uyDkLxQLaU/dd/0qmrzXBZyUCw
|
||||
zFuGdGIfg/IJwgr+8ke/gJ7QXZmsYuAcXPLPBMx/clF7N3zuJZ2Bmv3mxpjH1Czpzoqjj2lkETGF
|
||||
o1TeosDC0qDSFtAjkMh51kzIW/yE+ILVZt97xYOuNLzXF0wccwp8BqjMSXqvtlKtEtI8o+MKQuKG
|
||||
30SKDeg9jLJPnqjtFpI9AdwIZdXB/OFNs4V9+srCgNzmuHYW2kTZ/ZkTKHhCC58aq90ZBPaY1YYH
|
||||
UbKNuhIhwcvHRTplo5eJdXTyOEF7EmcUI0lBS+AIdj9/YyQzVXUV9kko1ZIuIK7b2TsIB1xbLGTk
|
||||
ZMPU580+5YZFkq1aYPnucsh6v6uQzYyFddsUYXVG4qfK+ItfWYgccFMT32oBQf8gxXqfxCUICakn
|
||||
UiI+gL5B79MSzGRFFfBo3xLF842cUQuHfNPO1T2E/LRQWfCtzCtPJCt40QO2C+bFazLfkdh2PP+5
|
||||
liex97quh0buILwS/Spp8IJYB3nnmAq7borw39WR8LJ4RKNEMJY/JyEw9LfA9EY4wrH2ZrVEW4vq
|
||||
3SlPtFSmC9f/I8cHWd1DsDUKzuYfVe0PYqaV/ZJ3MIZst2fmuBl39HWxCsVK8Z+EdX3nb23abSA5
|
||||
jjstE460D7DcP+bUMhhjGuKAe/vQC4O+VILpj/EUKwf9K4ZLvRMq4/rJiu4oL4D6cROLhC2SHapK
|
||||
TrZH0292oH9BXqP+A5p0Nfb29TJbcZM148jFXZz6HVVuCngh4c3dqrCA8P/f2jblSqwKKYSLDGE7
|
||||
MiZGRh5mujnZb/84PsaIEBxydEKMJk9ydE5MYf2IjafUEM1VzACOOUECwQm2Xqz6OVCuboTvfeMN
|
||||
hi0fKDdRFQG0Hn/iuL+Zh3eTMXtGnC7ryol1RYM6A+NiRK1q9WhuFCKaQZWwr1vuvVxf0OU5JMdr
|
||||
86dT1Q5d89+jIb0tnH6JHdgA0AwmF4vxL2OnxVW3JL975c0+FjOO9ojMLbqtlV0IyJU3gAfZEhSO
|
||||
QStLhUCKlnC2PQe6Yh1qeYGx8ePorxL8HSLBOW2Cz/lPD2cpd8jS/tQbj05Lz3i9g2WXP3m5kDGY
|
||||
cuDPq85CAPAQRQ0TAB+l/8DAeQWW7vj1gDO8lQYyl8XcueSSef8seZBgVJs6U1mrdEW3Ri9ulJ51
|
||||
mNXQLP7lpA5xaxkNL39SXr6ZF+KJUN8/IAtzp1ya/EHCdkZ3IADYDHXyGGrwlggP6gyCA5CkIiew
|
||||
zzlkSYgifV9UmCXP7b3nXV2rUH4A7zP0FC2BUNKYKSsEHI1L/MY26HIoRKNe6SGPiAGcXBg957/D
|
||||
wqpgtslwBbHrJAtSjc2gt1diW+ogdiCESsFkGFmHcshYI9/oG2ZZ/P5MpoDrAZjJ7PTUk2LJlcFl
|
||||
/iQ4Xh68L+fGSIkAryQpu/SuOTqYizi+6EnXcKY42TUKEQ0fGIPZUdtyJ9VVSJS9uRkN/1vIengu
|
||||
oDCWauVV3wwmq2OTSBjsu4bAnqDvFVqIQixcrwSRlJSPeNXsfuObDfa04jeQ1sNOQNhLT8hq2ywb
|
||||
kQLsBxQLQ0X51ys/6R2q1Jj2Se2dmCBu555Ayw8XTWI9KCGh3a7iRa+4YiD1Gsg85M3UH1x7rfaH
|
||||
tlAI+5wJ/4BjmHKuZX3tqMR1Aavq/Q5GhJRypOX7iPh/iuptdzUY9HPkNjySUmmQiQNeAcfjZdo9
|
||||
5piTVbnDd9wfzQY3MjAwPvgWVhFCxOLPSUC2miGW1VVKtbh82+1JbMRHbNevhyc62GOtZJtgXiau
|
||||
9o+3FNZb5DrZnWgumzD4T7efIvfYIwmCBKHg4ariYBzWF8QtNlj+8WpRyh7L4FdLDXX87d4x37HM
|
||||
uaatQ6MvkmvIAr+yAL2AUJcFHitZNUFBlDpT1EgF5rXZsnVkf9vbjJEV7h188ugHuipv/lxBr0tf
|
||||
ilkLDshDaoxQg+ncLDN7HOFHQxuCFeTNsPuSzzCef7d05vtQ6gPAA/dvU6hnYHpapiRotkOAkJ14
|
||||
ZRp36voCdirRVLPYSi7y81+WurF5GbHUIV4KPvE80B1gSTjX6mcK5oxj6aBEkurmX4jcw/UMntLT
|
||||
zVk8QTImFeqA//i6OLiqAOW1aq2nq2y1k5QJHHmyPWD6XM/SE8kLHWsDUPRgbdRjhfQv9kpMBrJQ
|
||||
0NrXeXF7j4PZNg+V+fS4ogQNoymWLqKXKnm2kiFo9ras09eYFX0EuMSLyavQAHw5OQ8cbUZc1SDi
|
||||
DqeIfSu3+v/4fMy1BCK5sQfxCaHBV092BGjE3CGv9bdeaVjGWNwcsQApv3LiGZGZ9kLWUEvoVLnw
|
||||
3Ji7BqER8xD0nKnA5LqqvrjlgJykzPNBrOiJCyE3FGNEi4YGZdfck9d1Pdc5K4oFIEX50XmmvIiC
|
||||
mEqOIWdhYsyzuCFCsG29vx/NeY+Iljte9Oz4SwUyJ7qrGLJvZpRgn+QxQ/0ptAE7uh4ELspQghds
|
||||
7uvfBntKdkCGzPeDOrEZ7iV2LSarjMo4CK6SIK/z6/+nwtLLVWRRKH//uw8kr2QPjsxuNfqiv2hR
|
||||
6x6bB2F8zhXiLw/eu8ytkjgjOObz2ef1USi6vyrj9E/68SI9W9FLePFNyIX6bKWX5+DCsG5w1vb5
|
||||
5NHaal+6kSoUwvN0
|
||||
`protect end_protected
|
||||
+12017
File diff suppressed because it is too large
Load Diff
+7657
File diff suppressed because it is too large
Load Diff
+7759
File diff suppressed because it is too large
Load Diff
+18807
File diff suppressed because it is too large
Load Diff
+55945
File diff suppressed because it is too large
Load Diff
+17045
File diff suppressed because it is too large
Load Diff
+469
@@ -0,0 +1,469 @@
|
||||
`protect begin_protected
|
||||
`protect version = 1
|
||||
`protect encrypt_agent = "XILINX"
|
||||
`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
|
||||
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
|
||||
`protect key_block
|
||||
CpEgUTZRhjVFip7O+FhXu8rNFxDZDaM4T9YTiq4qMzJl5WjFFG2k8UpCddGe6qAyeN73FJ56IX0p
|
||||
xCsMRh9trA==
|
||||
|
||||
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`protect key_block
|
||||
W124n4jTosh9cMXkZpMJbVt4FC58agi14/uVIDxZbr9/Wyxdbq+jUtbyb0Vp/Rinu7aHkbYDehCb
|
||||
cV1BvcBQbfc+T6GUqDtM0qpyd8lT+NBJgUxFDV2n97tx/9zs2QuwmlGwLoS3a09w3C2Gd/hckiNJ
|
||||
W99lcH4ayRjjpup8+6c=
|
||||
|
||||
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
w0oPwspDuB+TKHfZmx8MkntC88JyNsq1yfrWDINAmZZvDeh3kyQgWhSwyuz5ZfYujn9s5tO++7m0
|
||||
OavRu9JAvqtmM3K/FclsuLtUZ3+HzKqy1aS/PBtLCvMf8w4ExVO5osVLLHR312i688+QC6umRX4K
|
||||
/zwmDqOYeOLUh/+RGCX6StPhxi0oXmvk+LrqMaJR85c7qcYRPg0OoDrT1hblWtAXNxBRcYuxQc82
|
||||
/CqCpjHvSTS79lPoqAKvtlHKTCxMDYumG7c1z0IyA8UxxnX6dDEWuxqUN6pcD8QLhQG+SghSSfTM
|
||||
hD4hPJB1zJwqZxxbvySdiPBeLApmobBUFUUGLQ==
|
||||
|
||||
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
cG3WV6bB162cO7nvDwaMEkqY5zMqrlfIoTWtAVrp1pvjmabsZWybfweNPsDIcZlHRLNJSJpyoaCD
|
||||
ohQXbn3fTn74PnVSdoDvdgKrdGQdUiYs3axj22G47OZdQpCG4t+D8sTqC2mei3lJZ6ngbXMNFdo4
|
||||
vch2Y6DW+nkpgpyK228VlnApQ5CZa63jgB9mEPbDt/AF2KvoZbzHc7TKehSLGpcaPdeFLbEnd8U9
|
||||
GwWg4m8yXza1Q16jY13PzNyCuTxsLB39GbUMN8NdhGYK8FFRWyWEvemo1YIBLMzlp/0FHxV3d5vv
|
||||
UPlzG+SUFKs5GxPu+jza16rLE3bp1qQru5qKkA==
|
||||
|
||||
`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
X+SSwP3be+AKqv6E38pqiZoHUvwN5zrS6zZlnDNHrMAzgiH3SMuVihoJJRwiEM3fCYgsyrVMjO/7
|
||||
AhPTRAHNMEDuxAJz5S0fFywzqH/+krEhDmIjdmc1azH4Bi1OyuOS5DkveP6N1JWQCaHZG8GJUWs1
|
||||
qT42G0NRWF9t5M5ttCxcfj/eMiX7oox1Boy6yuolm/jDO5GvhFWC1zKbMsG5vCvLoswU3R3lnpug
|
||||
SmNOmMut/z95umqM69mzk6naScy81WxuLACZY+ZLzsa3W0EmoQpoFh6S0/TPaYHUmAqirxaweo9z
|
||||
eWnp+wy6dqi6Lbne6eReXH9h+5uGzHH41MPCMQ==
|
||||
|
||||
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`protect key_block
|
||||
FqbxiWfZx+AlFcc4w0L0ZV1jO1U/zdk+xJK7UfNljYj/tFrikWSj4/YCABK63/BY9X6IqlWE29WE
|
||||
qXj+sG1yrKt12AuMYebT2k+SI3AjNYGTanoHD6o/+rlQrYh1HVya4vsXxWQHSPJuRxgf2xyyZmZl
|
||||
OXf2weJKsAdIRrrLpQc=
|
||||
|
||||
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
AGj71Awj2B2Tw74FpkihWH+Sa5c7TMF3trJuuBFGZby7XIFX9KWSIdSq4LQbByQy4JzHRlXRo7B2
|
||||
89X/ZEdePYzlSYP13FUAoX3/9tvJGkFQuK8GswyOOYeHxAzlgjAEujTmHhDFmwUXu79c/fv3qhB5
|
||||
8JK/QbpCaS95IHLmqKlNRbPLipg1yit/ipGf6pe4mu/U/aJdsR6EJKw1ddaZnEzyEGiSJxY5J7IL
|
||||
bS76v1X8q1e+aEVU/C8nSk9or8ByIcsePvOZNKIU6ggznhI5fSFzh1WC9nenoB1hbjeqmC+lQ/L8
|
||||
0HJvaCrgSzLCcaNp3R//7PIaJTtOzXkL903AEA==
|
||||
|
||||
`protect data_method = "AES128-CBC"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23056)
|
||||
`protect data_block
|
||||
pgEhIB1MAdh+WeZD0HyDqobe2rriaLug0NvL6k+/O6omoTUMLq1L7qNnPzINW5eSUs7ipFuPWINf
|
||||
QCV/5U+GqvcDEWmLxKFS4Z7Xha6qrc1BX4F+Cllm1kE6pRiPFnmAAir6AZ8y4oy6knCH9S+Bl+Mf
|
||||
3jmh1OKRPjHqReoSshufcRQ+T42CvM+exkF9v6mtC+YNHfk61y8NRz1J8sEv49nvCgiOD6ijgz4L
|
||||
GMrrWHFlMpcWF09FxQK3hFosZXg1eFfw/dC7UxwOi8GNck1wg/juurocltlQQKkh9XgUfVUJeDX6
|
||||
52z2mL0Es2m1M7YMVh0Gg3OoJuTjYLYOPYUj6SEawVdoADreS/5jCfuvKfwthtPRUaI6y4elPFqH
|
||||
OYkm/YXuU7qA3AzKQnbvIQTaShXpp9J1RsNfJfipZfsPzdYcbcaPvaZc2sSCQZmrWIBhh8bKPdQ2
|
||||
9crbM5Ie8HpOjzKStLonqZjSyU6sE0kP1wwysGYMePzd6e+9rHCgb70LdrzTs5sOsTmbHm94QOsO
|
||||
ZhUcwqiA0ogSN8TNLw+/cYIopEcePq7Ug5w98xsYt+nQki6tBYEa5ksx3YXOP/lzncbgfMX0eAjl
|
||||
ZQtn2i4aGse85I4JpKAIKjQXCktw7waiVQlL/7ZA4vm5NGYtrPaZ3DKv/i6hc5RLaU/0w+ZaAQpM
|
||||
R9F05p0KV25O0zcvfHIZiLC2izweGyU+PgKmHINrZmr1FuTPA3sEIV82hQsR2WxM0NXoVUwrJLMs
|
||||
3hxYFcpewBXexMAokqs14XoNTiUipnBm1W1wZxTDMtjuUPnj6YwgKOmRiyHZ/gjA7ypeKS9Cmqpn
|
||||
nqZeqoksVI9xLVbFWQc5E2ATVzSrkGBA0SnNZPIuMlh16cawL85OX3uEh0P+klNZjMuGwY8/eSqN
|
||||
rFdY8tsz0GbpHQCR+C8sskkWE1UJxb4/L2SiMERzfT/g3n2JTL9FDZqfHj0qaQCXKq1XYG2NTaIL
|
||||
CAGpYbEBr1m0E7CCxHalr3vDd+pd8VnWleQzD7EMpPrhGXmIRbMsjYXPizJj8GsdSqDpDY8+JeNU
|
||||
GP9JGLlP1VRfSKOvepN7vVXaOqDRnSeJ8mXvyQefQervVhjFJ6YyE9ArnzHk1c++L3bWirQg16x/
|
||||
GOFNqVJUvZ+jDANPObkTvGkJOAVqq/ao5DiWm+eOtayQ/0v6hX48W3b2uefYCMiPCThEErRn3MfT
|
||||
dZV490/ylCXbbtSTnZy07rc4kcQNKaeTeJCNX4TxzUMy3IE/Ln7xw+R8e96tvw49nf5lRjTyVTcq
|
||||
X6rrrWXRc+1UNbi5Lhj5Bb3ZMCCQ4NHbszEgHm4DrE1tb4e1YbfUKsBxf4wkkBET1hKp6jkKW0pK
|
||||
NV4zbHboq/0c7A9qiHSD+/76n5xazq6rL0k8cspy2XfgTtY3yeCa1tf7EsfSyuIRu/cKG9PuhU08
|
||||
GKQ/CBPqfr2Wp7CuvZ3WPQdAzkKCclL+BMex6o4zfs3ux82HU1AjB1S/BAAwPSZpwpdUrar+hWSU
|
||||
u2r6dsEsPwX4S0jQr07OXtCcpXGe9BiIl5vyA/Sw+n9p25pUYSlSK3L8PTBRhF8Uzmxmtak4vO14
|
||||
6ejP6IltoWO84wYWDIlbwrpnu2+0stMT4j2EZV46tEk/B+0L90hnzDHM8A9iRVvc+Boprm88wHNS
|
||||
xv9Bp7mzt1Ei5wRI/cwAgJW8VMMFSHZXyG7HthpxlxuOEstAd7a3GwWZ47NNjrRUPIUsBDXZyJ7q
|
||||
MS6+PtM+sZznGgGiZmggHQmbl0KymMuoeYekgoL1jUpWsBhJjrsAU8WmFeSQN/P2EJUQIcmbvnGe
|
||||
GsxSsR1s4Y7j5GPOhGQOBszhnAjqBcuM8AewXAU23kXUNpmtyVMQNsRNd/rwojEerl7ErRe4xyML
|
||||
cFwM+UbmjPnB3HXXIYawdJ/pyZ4Qk9pTOJ/CxqmUSlxca1Ud+slzQShPNYQVCKTyX5Hh1munn64k
|
||||
SbVEAp1ikZNJyC0Y6gHUnoNAoYr6aHoLebsszcLwESEyfFxPnxKm/BLKaYWXcJwg4GDb+2CdGYyV
|
||||
09xOzTQ6KJ+sC4WRC6s4rFc8XVEuOa+wTEeEEcI7k3hKVFJJbfAtuc3KiBaz0s4tMCZQFSmFB746
|
||||
1KVKQiCH3v89ED4z9/gA/EkXUEw6G1rzZ4mmAC2N30EsXDdnMFjFvSUcwIdtgVD7KU7HVnH+61Of
|
||||
5rrcov+iRoPqOGYqUjbfH740gkqYrPszzf8TQn1TvsCBJwu0Q7O+xlH5Inp9CPwWVoepLTDYmhkq
|
||||
awUMwl7zVj/z6vkFFvaMbsiRNIX/2UKMf9ecocQOSzgyVvh+C7Ygyftm3TQfn9rDf1PlleKxr9ug
|
||||
/e3tsg3Qexpn6gBnzoqJXrlY1kiP1A9O1AGTw/ReSvspfoNatMqAEppuFt9/m/7HZkOHxVZuv5az
|
||||
zoMx1ZhUFlA7xorjMc/olM4c1tjhaiI7lQIkm9bSkwKi+mBi4oI2dVSockILjl7/iF46+TAi1F63
|
||||
Pgi6hlff23F4W8fJTRi/FGv+N1bvfeOg5OzTlnj7ckxCAkXQ8+3f5McEcDyxYQbUn9WbMPoYE+5G
|
||||
AwD6HDCTt6bnTHb22sTO+xrB7+udOBkv/R+LK9UYUMT5Dq/HDqukaZUDbPyRaTude4q4/7ITY5R9
|
||||
QDUAE1cOD43to2XWI1e7/T4qJjQ9FmR+QHwiquCw2ZpXrSVfZgfEUP1zZCrBM6uh4P+u4vi6W4fI
|
||||
LmPnOTJ26UXytCuGDufnWzRNYKlmRj1esr6eYSvT+Lu9Wkp9gFpw3NsvKMQ9B8EEwAjlcueTvlD4
|
||||
7FLH3soUd6VQ7O2/NgCiaXiq0N9ziMYJsg6Sjay7PhUmsXiCfkPi9/1ZlXGVV3RDDuqGa8yG7xBZ
|
||||
/oiJ81NhsAdwDANMcAowGiVtx2yUcSEPfTRyn+U5KLBVlKjsxGmSFpGlE2c7dSztaInxUbhdQG8y
|
||||
FUkTN3GWvyLI0hwJDWwi/641Rq1cGbiM0AjGOEAFw5TL/Pnpcaf7eTkjDDlCcd/LFA1YkmLbyH9a
|
||||
JxeSNeccLajxtegBFLiSqcnHdv+QoD+ENUv5s5p0Ffd2LT85vnzfwv1GJDAuuYgN5hUKR3kj2ib7
|
||||
R8ETVSD3gWgv+n3789Eh2ob+VRROZGW+AgEOd/VEOgofVQYHunaHjIRwNYAIjISKzeB05lDrektK
|
||||
gOfuVVmkkkl0hEAVfZz+JTFtxl36EGbJXijziK3L5DqGynHK2KaEzd/7Jp1+ftd8WouNPvgLPMoY
|
||||
SM64usRJgJyoLQMt8pkyLNg4tx2+atlccEFCkkKBqBI04fcSqero3vg/DfDcGfJxUf2GlEN9Oa84
|
||||
oCiTpCuWw8UEydlE75Ud+i/AvBpeYL/OPPaw3fXdsCB+jO0jVoNSMkKOFWK7fMucs3H8lGxIU5Cr
|
||||
yJfoiTQw+OJnKFmiEeKlq3ygJpO5D7Bi9j/cBQRoUkMp8tE4foaNSn8/3FfxneL7xk8ykex6e9JC
|
||||
uXJnoc+X9+zRAL3OGjLTj39wHPBlZ3AwN8vC8hcFlSD33wYcosFEKhnLiLBHh2GgCKUVOqzTQd1k
|
||||
kkDBj/uMxVu41Cdqh/B6UUwJBWKIVSzgUjcfgDmbFT+J2ITQdXJjYHbnEQqlTXY+zYvoC1buq7nw
|
||||
1hHKm+vqr6fkYiwGK9F9bSIzYgfeDspgGHUHN6mdjyTeM3jKLmzg9Vnp0um/WlT7LpqbLyL3poaV
|
||||
Houz9BxhbnmBiCr75HCAJsi54ikz7WfwGqH56FS9SFhouHcaUfiuFhBEivb1v72X5a9olz4AoPOh
|
||||
wvjJQhrVNUKlo+Xa6CFVjwEv9vYpMvc+Ir7XbR24jjVv6ePXMVbGjTdeDCFirXocB7WevWx35hGb
|
||||
LJK1BukpP1fNykrMxDFfxol0cUzXWn+SJ1JbYQ1v9S3ULLPAyxbpVWhx3w40BrEOqTILiP7DQC9P
|
||||
70NebMz2A+6uBiAELfNv/4Xr87MgyPJEErACB0VbKZsnZfWH3E6KtVOujG0H4e9tIFIX9tIPpCa/
|
||||
cpV4rjTIhX3sCGhG65nbQCwgNguG9780sDftOLb7S4I0p+WfVTySc3eTPRUkzX7jDl2El5GL+pVG
|
||||
THyDNp58clM+cn0AQijTIq8FZ3nderXg+QsL/raumUXxCz6mEHIeew8CQZHo9RroBw0l564ynja7
|
||||
gi5QcKn80BdxB4pX8StToIehZ26fU487YNd42aNyNFWyz3zI3cejfi4AaRFsSxE9ffQRfKESifj4
|
||||
Hi81frqq568qjw3YJEs1eTcc1HmGAKb017GF8s8EauHF985FS/7DNHeh4Tgwmnw4A7FU1t1pXvzL
|
||||
O1Et0FzTJV9dOYgR3Q2R803t+hcyC4ESb+bc1iPx65b1g84bkwi/z0+aux6HvrVTJ9X3oFyFxAFi
|
||||
VMpamgpkLr85Q3rT0vBfgW0/788n1PCsXGS+1/BQsiX3uZm2cNRNQ1RLtgX50SD4YjgE1ox4qJsB
|
||||
3o2FUzHklIElmk1CYJZWLTxanu3cktQ4l9/uHXUEWThCiFJ5bQPlq6AcipNmxw7ZEwsJPDQSTD7y
|
||||
15B9eYPKzM0ZCKb7YmYthqH6NFRg9xvuCY5q6peaIkZEaqAY1Q0IQxZZzzgv640YoYOuW7Mz07fj
|
||||
e1iE1aBiFdHypD8ENEZApUiYl0jdh016CKQYZBOhz9ezt+8qguLpaNwbEmJMoOiYwATCE1meafuJ
|
||||
dMfJ3h+Q4L9H85+/FyV9MdWpX1PWYFW5rLtK7HxTrsGMO2JHC0CLMKi/UidXqnEQjq2hkvhQc0hn
|
||||
kamkt6sA+jorEx+SMlkO55reDVqfTD3JEgWir2yytQEJSdxMNJ82InGKimtey7NYujV/fDP8BrjG
|
||||
Y8311e6fiZPKImBtpLCjDSolxF2qtyDTFO1qL5BsgDEBJE6fXzLELB7/QCmJMhgwkLkeXb0a8aYr
|
||||
B24QZ11GEFBm0Wkf2AD+7cSWkUqGvWfy2Cme2uU+x1uXy2xH+b5M4tKdRTrCQu0TgEiAm6u2WEZD
|
||||
q7sgu0o9ehFo5N8dEIMLra5Je4II1pBENoUW+xK35lQzzJXUXJTwxYef7rey++t8qohirZzMCkpO
|
||||
3cAvmqdSWylYMG2q5C0WmzZMl/wsYhsLgpdVMosjSZTJH8Frwc9I55vuwl6oZizyT+s3zBsEn/sf
|
||||
WDR6HIgtu/sULzO5yJ9OLc2fiNa5emzi3UnHNMVmf0mloXvRdAEmGDFqRRj5vajJS4mjcd31lV9c
|
||||
M0adS1NpibH1WLHPkNoWXhwBAEVh3VCl7+SIfF4a/bdTZBDXTmHAvLjVMVGOCJKmr+uzr1NGyUlS
|
||||
7SUej/EBY2EY56fzFOfuLR0cWvZptrCT4oXFrZ5ABALfWZKxbleBX7xDsIZ8HM/qI8C73t3qhT0J
|
||||
684MtmUswYYwJjtjWxgB3om0Vh4BJweU08F1x8JIXL/EQGOXZcvleEyKlG6BojhKdUP50cbPEjWY
|
||||
YjwnCmfflaot1HVgliBvjysXnzZyTKqEaW/YtZHA90U8S6iS7ZSXFwkVeUXOA0XEBI+hCPLwF8dB
|
||||
pfMcMl3IKeNcjuNR104iohKPOgfsGkB6dxD3KfHH8vQlIiQq8D4FVNOPQxg9ulBosPnKqah+Peoj
|
||||
HfzW7iOcxEa6pmFlM5pUCALuq1nPw9EZdl9jY0Wapg2WhFuMwzsHZv15AfoNG+yHOT4jqTunM6tx
|
||||
TJQMPYYg2rbnAm/uwzcFZH2IX3w6dAqy+9ZjyuKfp0sLyl/rdm4L4KYsHf+dFQJwHoZUntzJN1xl
|
||||
VjoQW4Bg+ajluKwGIp8ThSq8SA7CKBPJOzxeHy8HHz8bWkQBZ7c3W6hdV6EvZpbP+rvj4IUyMHmB
|
||||
1WVH2oT4iDJAzSgtQ3ZCCNDH262fx51MgYZP8fdKiQujBi3P6tKi+hjGeNTh5RJNN5vdGgpnHkYQ
|
||||
/rROlSDvB/9+rYch0bgQ7lX0SJot2sCZOl9wBcf5fTOUtT6d24GOmDpFpZtt7S29yqXjJ7OvufKW
|
||||
AojNCOEl/0g3L1GwzTgNbpAW8QzAkoNlZkbbG9N9dxOxqdhYct+KeXJeycJi+YB3EFqBR0P8JAo/
|
||||
oi7byfx6P4+CLTITl2+IgThEtWZdy59V65y+rE0oS0tXsn/RCXWhZ2T4R41BWfwavS6tL/CrQYnD
|
||||
8Fer7wgzLkAUXQtCvsZqOxtBPmAdbe7elncIPcl6EcKcf8BJxbFKGHimBE4Sv6y6ycvL0Cssuc0c
|
||||
ZC2Il5GZA4iz/ccTZ6W81PaVxzTozUxqPigvzHk6VIL/2LVv8rEMpx1SCemYLoLxGmHarGA+m2zM
|
||||
yyl8L4ZO5ODlUWF+cCbdOkWSwmooomRe+XftLFvC1ikAYBaHR7t0rBLU+mFHU3oHi/dCpXGovITi
|
||||
BIfS0mMfCIK1DIHJo79aUc6alHrl+EqWpwq8qPq3nGsdR9mR99EiT+n2arhMwoFtQE0CneEnIeeb
|
||||
pYP3Yf5svwgXuiksCMkwuIpxYX/KcTotNfS3AiLPhDtjIRq3MV86xH+ADZtY1lOXaTj76FTfmSf5
|
||||
I4IZyUOF3fBpxycKgAg5L+w7BN4yVZgZ599jDCWE/8KF/vrsQwTLrg4wjVy2y6FgKmYUsFQOr12x
|
||||
5dQemeGgj6cAmjTk3ni2sHu0NQpPUvkH4v1HgOzDAzgryJL3KP9dW51U4p9DfEXZzLnYJnQ6E0l8
|
||||
Pq+83lwKZ9K2J+vE0ViHDQ8y+Qi3htmZTcio6uOPJv4rgM84osNYuXE3Fa6RDXy2OUfo66LOk97n
|
||||
Ym4sy2IA4ZAQSGP9Wf2RILB1hA1gvHI/S1gXL1LHJSxwDEZBTSQQYtiwFdG6DvTqv1//Tov4a8cT
|
||||
MnJrUxkpSoh6KJoiUFcZ9rO/uxCNhwQJbz/erFBTTeP8uvAM6q3O3/gyduDGOuQrTRePmd+l7DaK
|
||||
b5IC1hk/0kKGsqvzg3yAljO+QtDSszolSqx5hgU2gMzmJmXV+ExyHj36uQCOt5T30M8erum/LnuB
|
||||
C0KFMTH4P/fTNWnG86OvW+bAfaFcvuwlEh3CamWC1uY0EcSHW8ffBkCDq07FvZFYnZS3fVuh0fJE
|
||||
oPq3tKgCpsVbT2qlr8w6wAcU7DO7z4ACpOEOraxy+dEkQiCDxkFnJgnngWIVBZogALUhjFZEV8VC
|
||||
HZI3BJ/pn2GGoHEyZNj2Fdnp+pWJpPcvDfxwm1e5JohepzkeTVW05sU/zya+waER3JGFyXD0GcsS
|
||||
W9BU/znE4xX7iCsXFZOSx0O3oqEZu/Td3Mz9vSQYA5XanWOnAE2oo5+iv4FDMBrDWMM4vX7rItsL
|
||||
L/hk5uP3J1FIHP9Y4qBUcvC1na3vaJO9EuCxiEfHt9xECLW3YIgSwk+kQfwapjVSvB5D+zG+lbKu
|
||||
40bIsHbB0qkGur2XMXAilzdcFYQ/FpewFbFjPYR1C3B6WZ3jNXq33GpQ4E6+HrsUO5slQ8S58epM
|
||||
JRxQDG/71w9BrrS2EH1UjikfConkZmFGob2ECHMyiy/itLmMJfag7b950Fh1e5V7IgnegJ7AUi5+
|
||||
5FhueH4nftB7St+UYz7SDAN1JLyApv/sml/Y3fmB4VfOVfZkQ/s3K10AI7Em0ZQPhWWi6pWSQKy0
|
||||
kk4ha6P69welUduhgzn9bX7A/Rm76E75EMY0Vde4lCDkA+34lq1I1Uw8CNTtlchL1jNgZu2nb4W7
|
||||
p17AtjLN4AExpRQKO3bWsNxmXhpIkofxerVKZrvFROSeXV+Vsa7COkz7kYsixkOmBtKFitOgcHwe
|
||||
zseEUIMN/PxzHfyIIl+Fx4QgMce4bxjdA8I6Ik9IYXCrHo9FeX3eayo/f0OhtilGPcTkQEz796GM
|
||||
qqWsB86Gkm/X1R9UNCaeg7tXTF7m9J2BNtI2GQE1ucTNaJiRmWRS5Xh+4128oZ8JzbvzUi7rgLfp
|
||||
rbCWcfNJ6tjL8HFFdogVkIZa4hEcCSW7kiJsrtO5NKRNMLvGVxetRNkiDADarFPopbkLki2wsgEN
|
||||
OGauaMhnR80nPSbhYAusO17aHgPxvejRSv8H/M4KkJ1R3VtlEJ1xpt8/SgVidgRfbOamb5uWBDMc
|
||||
9TOopnAHYAxwJOGbCKU2Gsd00iznlrV7BW2LF/cxXfhZgI+2D/a+/Nx1f4y6mSNC0oseyLlOhtB5
|
||||
9LamgxKoW9G7M8JiMeNXvdpDxebPvTd7sBGN4vY5A9bUp1l7NOB0uq2L1N3p1DNPvby2dgzSPZkE
|
||||
w50qpX2P83LK58jNHqJ8HGpEW3bdGJxu7jNTkmrhdRAcuNffd7h/GxNwvg/+bov2o3lZ0KZ0KczL
|
||||
8r7Q7b5ON4Emz0ZSzPdoAgqKMElX7YLBYJ1dy/OcKEJzWklaaIorkzVaXgpKJ7EZcQccMkQsOU/Y
|
||||
4lt2SeMIDEyz92MU0TfO8fRxUDZDVE54DK2W0ifw3vr5TdkkeqQwhBAH1R+Z+RBUOxm8hAMnNLZQ
|
||||
IrlVyIRz2FFIHKgZh9lkp8cYrXpoZLX9yAaM6j0xCW2Xb91+GF62JMImebH5PA5oEgVes2eM7aa8
|
||||
c5YxfDAizfn19fmbRG0FqE85FsXFO3ULpY+/DNrYi7cjiFY1yXZswgH9kccZ7gIkPoszaivT7EHj
|
||||
0Bzsdt0nK9mnJrRnSgjnve+s6h7TMyzeTXq2LN9Tq8RrC2yeqpMti+CjWZUdMfEEi0zMmjJX8iKG
|
||||
+y9hwWUbIAlNgNrb+kEC1xWAEuenz8VtPc2dz9FVnsmLgEzMBZwN+ZlYcYAZ3VkXbj9mhcMzv8Af
|
||||
Bw7TNU2EQus5xRXOGIy2p+xopMn8hNnnbjIEb+Oc4W+Kz4x3p3++4Zwrpi8jzOwV8xQ4uKe3yvtL
|
||||
VpPVPQQ2qxGzEhggkOs8u3NK4L6sDb8pAUOyMtEXHUQ7KuySeQuhc3Tq+e8swjDr+WIFjFhooGZb
|
||||
+Pc5YJonIygPKnptV6snuXH48YMiY1q/rWpSW3FWF1mSycNgdK9H3aUWU4aSwG1fi/2cXi4Qp5H8
|
||||
7+iw+bxMM7y5KQhwXZRK61nvHagpFKYV4V3FFTs1cCPKOVg3crt9rEljxoMwiEwXtDoZ/dCoXz0d
|
||||
CQT/DsmvE71RsQ21INU3XtAfRjHBeylVGCUkiuO5JRDKG/FUB4K1AgBS/4hdFMnv595dhZdUu1Wy
|
||||
XtKBF+7qhcA8obAiqT2MAbqsf59wOc1FulCWcjekzk2GAoLxcpK1fRHKCmTkflr3JL6XHQZ7CdAr
|
||||
IjyZB3zpaqpTdax3rqqDJ8QJMg3eZyv5kzG8yFMEYxIuQIPYdr9LUyN6qpKt1PCU4etpuezaX9Jt
|
||||
93c9rQTSWMyGg8R3iIDjWABrUGzzvM8B6iijctaW8dEKeXPR1y0D0vymuIUlPNH0zo+OUhTU70ti
|
||||
dGRSPBCqbjovOXddeAPKqyVlKPsHWyUo0OHe7DxL19HaNsOQ2fK9VbEex25kXzuue44RnVcYIQxu
|
||||
wpltayS0Vbs1cD4oFka7NRyNmLaApzxyAgcG8C9Z+ulf0kNcfw1HffuxZRXYllmaBU6qiAiXiSN9
|
||||
kaDHEzS2977xr9g6AMLq9YU8mG2Nf7J+gZ7LpmNm5Q3WEfOBoZhLRFbmmGViMPO4qGrUJI+/YzIQ
|
||||
DAgB2w2UGNUvrCNOG9r/62eDVrYcMqiiw2XGcGYF9OtwuDQimrYb8CmGhZtShJeWbAoeyMYDk1zu
|
||||
l8UfyX8vX6x1C+mqgbIL5c+UZkHIfcVoGUAfgAge+IUZ5fBbXbLgAmufL9GwdeBjVChIUOyRXSmG
|
||||
rkhWPU/KBIVT7odN36VU//xUFuZKdcwwndyr901QF9FI6Dif1AR29hf9PoRj2YLjsrGPPvQeHeUl
|
||||
pW1rVMtX6fHQZ2wHZDbrKctzGEVexTnw5c5gg9rZ4a6DRth7U3ocrIbaCxfKlaPRuMN+86GCiwNN
|
||||
03CCstY7XlbDCvyOp8FbtS1VMBA9qjWiLek/XIJjVIxYBAHPgxCb0lPo6/gZTWDUKq6pZAEc57Ff
|
||||
B+3nDFI0C/Pr1heWiWIeX/A8feEqmr9+DeeOkAL4Q3Mx/RJTv7S1MGNo5LI5te4z9hKnUs4QG1Ew
|
||||
QO94L3TXeQf3PYekMTeRWob33sb9ApX1l5vpzR3osTtlmWlwvmdl1eS640WXcI7BYezL8ryqXSnk
|
||||
U8o43HH1hhuY+NhnZY3tHT55nMbd4NqqOb5YgbirfHJtyE4QFVdYYwwS2W4ZQmWR7Y+xfQCR2wUv
|
||||
4kX4gn5Mf23efxigYKfJtdAFzKVTM58wPQqrZ76JaA6OLwA5caybulfCnNpEM70b0Yf2z1J9TuAb
|
||||
Qx9cVVaEwL/JhC705msKKScG5YCmRYXcLFz1TKujWfj3E4XYHoe2BrwlrJKpBePgO9xCN8R+gCv+
|
||||
xtQ0N21zWHfaKAR+zVtVLqZ+RHL+WOr5dDVD4lgObzivHJZVvy/i4/2CElvv9+9JPiXjPelAQ0RO
|
||||
4486KcfaMo18cTFiIg5+HkQDMsqKYrYuMibZXcZiVgn2WpjWJapBp+DhHY3gakiqPic1FHcYk7Fw
|
||||
b/fbVzUEMOxe9uaf4Ytw/UVcRYU7gTmfOXIDfKa8ISN8kjtthJzrx0C9LuRyrQc4EjiTrv7s3Z+/
|
||||
eEbbX+IMOXoctksmmdLMJCGBiw+67/Gv4EhSKxrEAgSQQyBcquJKGBwY+uN/PFPEuNB6M4qsOybJ
|
||||
ORrFEv2lEnb89ZVm/gn5dmaW+71m42eZiWeXRbfWY6Z5LWoaedN5zGHQiKlFgzd4vbkjEYHk4igC
|
||||
xG/EYgidq499e6dS2VZyNtOaY95LiKmFDm4A06YeKjNYB1wNso352HlT0ipe8O5cA+Ie+TUa2BXc
|
||||
X978YZwcq79qm4L8M0s80rQ7pyBMHFgbAXcMwAmoYh3vzvk/SKluNmwRcBC4P1/oydOpftTqH+fA
|
||||
V/aQ0Kwkbc+69yhyZOGo+aTuSM52Sxsr9XxwHRm9B0ZXRyX3TrVl6qKf+OU3ySSN8OtWDGGvzMj4
|
||||
N8xvqLDGt3OnRzMl6uHan4EbN8ydxg0mR+SFIYExQ+hTSKeggklxlfAMIV3oS7JX49tLIsY9NYz9
|
||||
OmnjRgJ6t+nytitbRUMpoKt+Cz6tstcHYe/jWDCg2SbIqZNFG0MMHWJjiJZTx6Fygm0HTTI054V8
|
||||
N9JmVppy45UBWzLNfTDBEMnxTIfYEIu29etQZ5QF1ZX/fiN/T7zfyvCzW2p2amVmp4OY0OZtPfFL
|
||||
6PIC42MPrupZp7a0fQBIAfiPjM8tF2WSWa9MfrfkVQbC18XHBHIoftNdp3IRPg4SyhJB5ZA5HC3I
|
||||
h0pT2rSh8gVo1I2Bq4gwyuTgqA8IXl836IqmrELieJMBsebHe5pmdgqf9VDBK+4STii/aYzvmPUr
|
||||
oLP9uQpqeX+DxsfxmxbAmKZ5UdziMntsM9m6iiqRB4gSOXpgCWHHOOoeGJmaYJgLp0kG+gY684QS
|
||||
7NfDhRK2nt98/CE70hshX6Z0wbJapTkwgJX8v11J/9x194Zbh4NaK9zHpYl4mWVOqXusTpXGbSAN
|
||||
NgYAxY1bPZjp+WYqGct6y2wI8fdBTEbftbWDnGbvw7FnGD3frWdNnPmlFX3a0alsg2bbNWhjaxtN
|
||||
43bg0PReoaWrBfh9o5NLP+KbcFAtiqU4pV0cVdk90sOMtfg3qZgqUOO+qTMOzPcV0H6qcP08XTX7
|
||||
B1SVVPfloPPiLf/9jVGarReXO5VGxCfar69h3qX4qORLO/rwcvd9l8X4FAd2OApxFFioKyBEyriI
|
||||
pfcR8UJ6FKaUM6kEOl7syMwyWrBOGhxKo45AyXMzTfau6WYBTRryY++g0IWvAzxA16NESi1j2dbP
|
||||
CQbL+I+2znayQcKNiy1uSr3orWN88Y/ySh0U5U2GNq5Pduq9QKd9/Q6Z5fKv4WkYbwkR3GpNAWZs
|
||||
NGYuaLxVeeov3L8YxyZ9tdzc7MNcF8u977tEQwOEUEWYc7apc0mY+6mZjAikNTRWBWpKYuj1Ra4S
|
||||
N2/j9e02g3JgIzBaB8T775Xhn51EdG6VjIzdPRq7Q9Evbg3ToDKwYNCqklSJQmdJC6w00k8HO9SY
|
||||
Vce+yoC4rrrYPjxPCZCj7Xcq+sG4ablJMAuMCrrhyQIlYV2/hqWw6yjlBN1zTFVgqeq34Xr5hWMO
|
||||
fC5QrRd3QOcCSzLMcjt/oNSFav1hs1F6kd46qm1FumVX+FtNSOl/X5Dtai2LkPDgqds5C6rfSDF4
|
||||
QGz3Hu9xPFAIuP4MnwjiIYJf8HROM5uHAnMEnRWCHuQ3+yeozdgfPT95vH8dIv7jpcIs0hPC0A5w
|
||||
qQzyYjPtH0xpdIrrl+Ds2dUSAdnw2YQFdWhD4T0IUXH+lYmgrCp0tt4L5YZpTh6rnB9Pstw5h7fc
|
||||
9JHX95jXPAvSq+XOv0TbhkILvZ9eTkD6jShM6krjPWuBqvNEUhGYtrdZmdd5axiQdLF9vk5VUyBz
|
||||
tby+S5HaFxla6k/cp10l+LFLv7KmAYd/nxTvK2PlXk6nPPJg2x5aoZo8Oa2mirnmUbk5IjxxkYle
|
||||
rrjAVYuahkweeXFXbNSxDSdQ+lEIdSImBu1GsXN0ybm2fCj3pWQVcPcnKoRyd+kqkau88S59xkvT
|
||||
tncgyIKvR5GJsebAoXfjiL67Z4it6Ve/mkFcCXAnihs8R5CFJ5amgGhB/vB7pNAt+6G36vYDsqlT
|
||||
gKb5mrc9vTZEeu0ViBKvrx8ji3TNZWL1/nsXUdPEejcsTXAvhAmFgQx/Au4BSUUuv9AcoMSqi0T0
|
||||
H3q+U4DKEx1keXi2ZV4FZhBvHqq9VL0EUu2jgsPq7mx4F4tqhYza6rcGruIBhAnNYkLOyvYpQCAk
|
||||
C6vJURsIHtAt0oKd6HieRanRmCOqfa5WuqArLcuM+ApbX4Ks74hqFinyoIJLw5ViWOF69v2BIu4/
|
||||
mHu9Legk4G/M4N5ka/2C2O2xwC0R1sjLAJMi4xyK26ntg2rvkDCYzYgYNTB5Dl8ICQ3AL5ZLTgDC
|
||||
MHfCLY/TgZgqI9wSvaYoFaVBFnXNviGiGM12Cz3CCG2xBckpAPj82WRiAhBdBibQR1jURxUneceP
|
||||
yoCwq4m0KeMYWnlS1zhz4wlZctbHkNJVbdxP4QSe+sDo+QBJopfC254p6mLwaNTZ9HLT0GYp0O9E
|
||||
X+9q1QCk8y/MB+pFUJKHFDQx/AQWjCbzMSLClwFlEBTqAKg5UWerK71pQgMZ+Ats10Zp6o9ZHr1k
|
||||
a4Uuyxy4PbYjH36Aa9h3lnGk/q0FLNV9LWq+XRXFcmMog1S9xw+ma/htqVLDNsm1Z/gXDWC8H0K1
|
||||
+vzyPSLVzYSq5YvTt7q69b+nPmv+HUCrGOqoyXzJlNf0140Kg/G7Mr2wVnQaTgXukJXUa2YHCARB
|
||||
yJ8yW/pIB+cYk5j4NSXKV57HT6X6lzuYBgAR4UtmGrrajFbD9hjf20m5pVsn8lMjVAxrxnE6b5iF
|
||||
OTX+GhurLOwQCAUfxzUoiKlslYA1RHn/3OIouM8eRO3qCE7qS+ZXXCi6qyzF/+Mg+lJqSjgdmrxQ
|
||||
mdJgYANQYrKSh4e8NQOM2d4tnDR/hl7oTG22PpD3W9wZPVh1lwOHBXFb4OYSbrTyrRA+iBDZhmN+
|
||||
s4TBzbmSa6UaXFV/JJiqpFMAj34XSUjp+hM0KBzKNSCf7h8ELVJpRMh3ObN709WxZTd79XFuORTg
|
||||
25IGFBdWdMch8ObUyby4kDNR/CYm2zmrF3eVWQKlUWJv/EvTctTd8IntpL6OEPF0j1IKrpRsd+Y+
|
||||
1v4WEi+NCs7ex1qImL/Ha2zlwOsVYVKEgX3j4h1jV8reSa9DRnwfQYm8XGzQ/31zT1GBw7/PdB3B
|
||||
UUrTKjrrc4C5QaACYVKgNJtk3b8NytOYYAmQavw0igQR3hTKQYFBV2Xxd8DhhHiYT857bqxEGJEP
|
||||
DWCLn1Ukd/6TFwXo9tNMqIBF8M1HF3kLhJN01fD0PZGp5Udhu7EnpgqYbiEOmpnAhaH9LxpIGgAA
|
||||
Pt8cHhSBaZt2ceSv2Qhd4Nwe0Yx1Bja6SUC0h1MjXCJz4yMxReGopPgWrZOwU2z/vbEkeDZIypgW
|
||||
/WaYmo1HNT18Q+6IKcJ/IdldLENAwQJG98zrTuE1jNcQgmyl7tc9ZIDYT2XWKNYzzze/GKqY+sLK
|
||||
mDsYvUvXiGpC2QXSEYaRRHsNZUYkIAOacfUMeoDba4I1Ndldm5tmMVw7fk0ZfCvkHqd9qS38xMRZ
|
||||
ZHqST9M+TtK5eG2EOWbIHbDvaPVf5El18pC/5+InyuX7rBTHpCp9kS9hSBUX53GOURS/QmnDDShz
|
||||
Lh8aKAjDWg42PRXAO62l2uXohPq97apA6PE1IP6pEkPSc4A7P9ydzpstkl4tCcC3xFmwWG7U6Cec
|
||||
N4WDfNh4HYx/sA3J6b63qFFEz/5ZgXq4zYAwpBjM22QMQa5PmNzxIQgPurYBncnptWxEKdN1EG6L
|
||||
o+jcf5Fq7sDP+13UT6HgZwGxceMWyDTCJyi7zyzcOIqzUOxg7+FC8fgv36u5ILkPBsMmRneolKGP
|
||||
jZMka0eFFoTT9SqPvIkhVdgTbHyIeXC3PBc2fPPFCJ9yyMRQ3pe+3T9xmrTYME+chROIDlR4mi/H
|
||||
KhwiTZaAB7c/ygKejxBRih3s/lZu+nJHmu80jIfGhPSBxubdVqMDdeW64CiwFPpnejfuEbhqSg34
|
||||
WrmfL8ND7JrE+jD9qsBperypEyiZahTHYLXkHUp4CUS5UCCic7LNJvkdbDtU3gpcwCoO2cNppbcI
|
||||
e61EiPYuNH+ZwQvyM79lflkHCoZLjKf3SwWfktr+bljcqx1Erdy48jc/UcTJ4+NqDh87JUfZVZH+
|
||||
RmnOCbqSSzSy4bbs4EV11Xd3IShsDroKnkbU9u0X1lTA3UgyBFHMnGhGSmdufi7yMhy+cbKK6Xij
|
||||
kQENx12L4gp+RSQ77Jq6T101rJnQwKxn+lUDTHjvZaKT5WoARojgpKqZdVtUGQeIN/ZaO39cOgiI
|
||||
Ngwk2oZTOkYi0UYl/3oGKv/s8siSFWjkJ/mdnmGtkO6maigjzSpgqveJ7OcbxVxta1Frczd33anW
|
||||
uE8v8nVBSQvDaSu60MXDL+5BfevjHJIKU4wQcJF7vnCgu6hwI9Hkfg7Q0Aq02Nn2VUu4sBOmf9ui
|
||||
/SVBrmZGz1hAWdTGeriivuTvaG7jlTNY1jQwzU1S1E9TBkpohK5LsPwzwzuYy9NjEmpg0k82Tcxw
|
||||
VF5IAp1HvBG/iA6whgx9LLQOvG+VFawSd9dUR5/wwzHsRb10Cr5jAwToqRbixoB8UsXNklgte6xj
|
||||
DvyG8JWdh5idb5rzuyXduKktD7W57vQduKYA4VQJcDHWbnICTupUVFnMyyGHeAwQDbek0xRYvdwa
|
||||
wSXzIK1Z94siPVeLA9Sw+h5q6TnEgwAiJG3r8ePkwWgzmdQdptaDodQNo6SUrlpuuymsNl+kgXqO
|
||||
hno+UB2X3UTKazJixFDokBVxFFPUUfMiZ+70YTwTruG9pzZBTg6iq8VVQxXO7Ey7jKHucqPWIycK
|
||||
B9fiF7SaN0OS5g8GprAhcZcTNn/AFAC8QMBMO79c4iyaMjh5RA19Sw1XWSwIyE4G2cJAfFbTSfSU
|
||||
AwY316tc8rU72+7OUghMU7pfInce3f3A8AU9doOaTpdLsenWnbDxYDqfBepYpkbijV4pz3UlJ046
|
||||
b/afglWMSSWAduvmw4OpUpAiJYTPzzfXWyCR6zUaYk2HucVH7dhE/3AtkHdnHscOMT7Iznk4Cy4O
|
||||
sOJ9dLO36ky2UrAW/D5Jda+PZntmVkLVFxyCHe/Uh5rBzHuEGZuvOU1d2DB4ES4exi9Yqs+Z/C9I
|
||||
1cI9jXR6br9rHL9vi01uA4OlVnyFln0L5TH7EdE2iRG04myA7aFfJQlXWmFW6crGlJb+y2wM1Z9J
|
||||
BBKUDCALfYokh4kKJ8RnEZhlIH9lzxCTGnDfRXjPAOaQ/FLRYJEZcpGlUAVDg/ZzNUCO71iSqY1S
|
||||
Yqrdwxm714KmlstTYQY1V2s8eyp+47sokIH15lM3Ffr5/m2hU9CQnvMACl7isoQEClvyE60GfU99
|
||||
On69OY9+QwFIcbw5M5MTj11VKyr4CZS/uPNPNHWQeXKgiCXS4lrN2bDzirNISuBlXwyg4/tPJgMw
|
||||
PNI7l5A+2UCN5vdus444LHHpg7NOSCWXFyhdrc3rIbxNvPZtp7nrWtYUB6zX1N1MDYxm7pMz0PZ7
|
||||
Wz0OINLmVd8ZktXOC3OOAqSaYb2KTsF5IxxcA63JyXiurkIeXUMgorHTWNe7np0skUntLU1Imj4Z
|
||||
1HmT8FejQN8M3Pw8Wn1SEAsNNnI4aTuKHS5F79syAwxxisGNo2Cjh3Lnl5YwYUgsdBeWgd9ECHYU
|
||||
ejkIsKP/aQkvCPMkZ2uMA5ZNTHEIrbr7vjTUNDbutvZsw35GS3dJckxSUplsQ5qZlolbXlMga5Au
|
||||
CnwDgOWvq/LCz30qsW/77qB7+2q4mKA6vZFvm0YmrVOoix1vX0rYL+7vajuSn/mbcN4DhFyVanXi
|
||||
buYSzx39YTKVutNbWregNlXzQTPL66chbYeTuWSrG0BbFJ42K7BJebpSVrJi3sroJSFzN5xS3ea+
|
||||
XpnXT0qk3AP8JEoim3DDbofNKaH1TqVPvxdlVg0wYmEDpUKsJXb19X+yoLHPQFt9hvV+A5r0FmK3
|
||||
3GqXO2CDXkHFlDwBaPiNIthxhOh+Jtf80dS6wDxfMdrkX0d3ioBDeECqTtgxYuJnLSwQvOSMCXdO
|
||||
0Iz8ug2sbyrA/eCnje51C4u450ULtqwQZacZ2gkZn0S1V6LASVnKGDV6fHtlEEYz22qdAJfFZ5/5
|
||||
TTPm+ITlfegtpIiEIRH0lLo3iEqYNql6JtCbwAqoIqDGeanPMpH868cakucW+4XiKd37NlR6Gkpp
|
||||
PrdoNXEBNR/nN9cM3v3IbbIjEuRX+jKffbdWRsvY5I09DqfLnq4ZJaPxmd/jjWLGS7YboG9DmWoz
|
||||
EpQ5RptMnVG1oV+9PHHPz3V0raYf1ffsH6qZ80hOkTf1OKrZmiGd8jhD9evEBxCDGdPv4iTrg3qX
|
||||
yBOoOddrZhFR9FG1tu+tJWW6QBg8kWkkBYlgIeJ1nHPhInNR0UIpTvZEWgcgriQRkhMn3rcsIoEQ
|
||||
oRq0IequC0bWti/LgPkUIfOGEPYuJx93rVo0tdmTIZSBzdeUI3Ceu34v3Oei/DDo1M+ad4lT+/FV
|
||||
ykOzZjKUBcktM6AYQqv60duJlb7GCGRgr5Ru10IINJXQsXBmFy2/isxBAYZEz01tja63gu2qi5nw
|
||||
upHpxKyXzI03AbJym+eC+0I3MNlRr7sdgQFIXOsf+iP7MK2WGLRUAREANkfmhBKurnsKxs8AUG3N
|
||||
0robplBEURLEcSim3UGFnt4FxrajzJIIMRf0bfcMbhWdVfFfzI/jADuQO7NWf/oqkf1fVkKdCoO9
|
||||
cCkfMQ8rEdhdYFvkibUhj2yHHD60NK16LRwizhsoud7Uycj4VECjVyo1Rwm8kuR5xTPI5Z8WtnYm
|
||||
0C9lRn5/C/N2Tx1WOi4V+GZJuM6WvxSteyp3rQMjuI9St02Pp5NqU+P/CldtqQQQpMyMfNzU7Gkq
|
||||
1iIgV9QhHDhj+ZWfgz1HLYC8u4///OhYa8/GmquoXAPXJM+DVz6WwkDKb6B2uyktVZ39RkOMIlnI
|
||||
/Xc/S4NH3iZnXQeo48ldDkh/o1yTcBetVTVEmLp7NQ4G+6j7RAiMkxvS0lkOMJ+MTspz6Rd049Z2
|
||||
mAfdnmiHEfRZojkC1ZMDxbfHeRA6w9ToH8QVilvrW2jDqKXNnRxw4PkDpjDStMI3UEXRGlGxZ7Fq
|
||||
ioxlccHbdkGlRirnV2KzGjT2TpVAFQjKAibEcKD9sW83nJfMBsmz5ZIXsvhn8OQz8qnbbt8XfJ8O
|
||||
8WxVeGd/h2G1erXyZGohW8+otq9R2iwq4k8FJqfFIQsTLaX42wDQkTpaG/9Y7cORjPp6XtSXsrDj
|
||||
8vrw3ITK6D6rMsAw9OvUhfNCYFdHpQGyV1yteb8Q/f1Oe0nOYU462Tv/ymnIgEy6+gINZbjpg3nD
|
||||
VHRljNbw1F0IA652eSDXbMEHHqe56yfNHyuJtOrhid4dwtF1HHWwPL2rQelM4kihsgOtSLYGXljW
|
||||
X/muOqH1pqda6HM2pSQIO3zDzHAA8d+cDkTYo7VXwkvqgjdruxwk7Gpaj/Lu74oTqllNMxhAXCLn
|
||||
CUBdcqKVSr8FADrAo5MYgjKBXFSUXNfsjugovHO82IcBJYO3m0fTjmDaPbuQ1+nvAzsamHMu5U+Y
|
||||
wAygShi8gc0CaARPJp8UZKtCYIj0r5jxv8mDz0l4r9BFeLVbzTWeX0h0URKC9raBrUM3O8W40hcM
|
||||
0MDoA1IzRCXDHGUX5jFXhyppZSjU54fFEKs1a3y7cmcXeE9mSXplQUoniZYDescRPAx1F0w8KItt
|
||||
VqtfnihVsfqXyXh6xdKRQn/V4FM7osSlu9zNLtykrGYLtjmV9tM9nVCWUex1RFoxq9t6eTE2IIGC
|
||||
bmT+FbeiOHguPistmstX3I8YipDnu+n5xmqzfvXswo1Ho3tg76PPT/x2q3yIxqgKusKOFDei8CHJ
|
||||
06kjmNf3axV9tnU7VelDmFzqHbWGa9J0jI2whoY3IttaSDDTofAqehJlur9QQx7IodA4qJcnk4KS
|
||||
+en7U+59Ii5+4RPon0pXEf/oJoPvgAc1jyaODYJGQk6lOBSaBNao+OEmSyJQ5aaJbxqqW+oHXeyQ
|
||||
R/O48E4aSoHxtJ2jeuVmFQqEEYpWfpy86LOhjyXMk2obKCCYhlxTgyCYkNeRETHXP2oMABNXtuVB
|
||||
OUFpTLkam0Jcm5DdKTRvikDmwZ9dW0FQQWwuDJ2KnMLfRxgH2OQf38mAmLzdZ1Hm4shRTXuA8Ypw
|
||||
i//viinygknKR9BAiQaY+cWHNaqe0ZOi/p5r2fFM/MgzIo2Efg0zmTmo8PodcEMTIUzht297YS+J
|
||||
JkB+R0ZlQ/nB2CdWmQ8SM9E1VdxM1KZfqRH5+JCWpwjcLPbwzCSubwzMgrcXr09gQ+8ICT27KWw+
|
||||
Pa1YrGDyyYQxIqkzZTSd2P0yilX3g7ugi8QAzjg+ZNzZsRc7MzH+TwfySSOzAXHWcX/5hVwlD95m
|
||||
7lVzl4iPgUQ+qAieYBeAIVadFS8H3jRG2SVHp9zNS6AD5w7sBkbslevYpQv2x/+YX+Ms1RRxhlus
|
||||
tzf6j1b7A72wqiF6Uhl1D0cWnfnbgV8YxzF8Q6lhtsr9hTvm3uuXWg22dg2AqcaNRiNd7VTyAvDr
|
||||
lPEYzsDjEq1kxPLDOdtSZuXe3k2S9m8oi0vkDRym4ND5mjd+AqIoxN3JCld4yHvQoqcqe6f5plGM
|
||||
6H535YPBM2jXDRgKwvZvn1m8oYXYa1DbhC+AtKjQlo+fz0gKU7dequBPUc/FkJeFqo44vZEMdLIv
|
||||
TKn8ylqkGNIgXYFshpMQSxjIO10N6eSdw7tGKwqa/tvUarEDVzepN04rBoNnUdx2akQWDDPwayon
|
||||
01lNB+f4XxyRLndeWYXhN/fyPlwBenUkIkftHTnMfuWpM/5fVRThmaWg9r34gw3wX7GorgGW77kY
|
||||
ty9AHCwlBqZ6m9yu0RvglQR0/XnZKnif8LD2OnoNYLzzy4TlqcPJEyWkCvigG60j6bdWJmQXTTrn
|
||||
LCCZcnOaoTu6bjAfDakLkgqkU6NH78/go/QJ07KKHyQveVqzeu5l6Bvfiwx9ibaDtOlH2ovF9zDL
|
||||
/0d68/wyjq47wo/8huhyxaLsjIV/IcdSs1YAFQ/mEodhxy4pq1z9nHVzCllsALiLwTl2JsYGb53S
|
||||
yML21davpqKMYlXxgBnDUGSUMYyu0/oVeqNwp/UiAR8M2wPAtbWlQ2ln13hJDqqOc59WgGQPE4B9
|
||||
0cIpxHAMsiYzcJd1K3bjQ1BgorJmNRcwj2T2zwlWjLyUPfB5XrsfmFked8zyxQlHyY9ofD6rZvWY
|
||||
fiFivgyUg9Ii8m+rWITlhGLOqhKYIMm2FaJXB3JnVWO8mopYYouc24Yr9La//fd6G79o+0vjiS4N
|
||||
U0Vs3VzUjO1gE6P79ZjZMNeP+4WwfLvfAyMvAhgTaXioheOvGr2s3ZLa7Hi+ButZIc4JSMMTz5aZ
|
||||
InrlPDlp6pLk5jqtUK+gKy/EENq0qbuUf5cfsBdA14u4JWG99e2Ln7ZKZB4LT8azIVnYmQWo/RTd
|
||||
J2Ylx+dNAm5pmZiGYKkvGyRLNG3+brLW0QTZIOxOC0CMRq456DyMkdvJTT4uyq5TiQv0P5sXr43e
|
||||
y21/uIUEkzdkl6mjoD9gMLfSnGVl4MR4FZ8oO/stmtn60/iVlU8XJwAcZjFroTFy5AAkOKlP3hnO
|
||||
uO+eW7qJwgvnZ1tlboDDrvCCt6Osmuw1NnJM56D1vbPTWR7MKN1pgxstWQECTe3ofEwjmUaUpAl5
|
||||
of5wtg4s7aO1Vi3OEsXUw8JCTlabHLMgI99MqW4kwbHc6LchpyqOmBgWBdyL7YUW798tJAlsEtzg
|
||||
IORv5I1Nox7WbcIuK8pE/dhtZFdiYdKYhbsu6RVF8g6/5Q831kBznSqvNY5hYBPSWDk444lU0Oak
|
||||
KtAwzuahFknBqrthMZiiRorXYC6V4WQx0napIh6gzC089IhdbBjI1Ivjt+cDwLwhkv0SUyVtfPbE
|
||||
W84OE21skf9pc9KR7+DY9W8pXjHUmR3/k8YZ/fSg1/NMXk5oPekh3CMvimPeI9uWP5uoA/lq9cGg
|
||||
vGAIT7BSy9T3ciW8kYmpeAEvqwshblZenUVi8Dt/9kPiLXw3w7eRXPBlVFE8n5ZfH2d1aklDX5ni
|
||||
HPtyXIjZFy+1ry/J1Y1RGuQcSU85qQ6K6CRv5pPG4BlNMkQK9usf/PSFERE5yEu/1F992dbSRokk
|
||||
WkvCUj12uzvJCt9bAVZA21PKou/z0IOg9RrCd7EAOxykcWXrL9ioNzD0c1eFEKyWlRAqtHzkN10+
|
||||
suyFI7IiJUzYDiG+n4IB5hkn7sv5dE7RjjUhUWSoerMi6cmWeOBgPHD2uS8yeidWHAYjJ6XesUvY
|
||||
glUH9F5sMipet5D6hu0lElcEft6WPP25JnvSqMV9kzsSKfXb0IcK8atuEjI4x+0xCtce+H37RyCu
|
||||
cnTApXjiMBjeagw6H15XrHH5VY2phqMwRPg+NUoAhg9JCk/dwlfQeiiHNTLXZDqb46vZ2q1PPfbu
|
||||
6eLno0iLAVhwjxbmaDHmTCUPLUKGnyV/Qst8axZdNt5wZrlwGgYSSWCI4dqwXxbONpzd+cRuO6QS
|
||||
g62QTl2AeYeKgW0VvaRDhB5iw7xbM6sQ27gMffqnLdqajr8VIvqpFRZwSe2YQfzxk7W5E0b7VdFi
|
||||
aP4aygtLQOc2vuG1c3AUP8T7j5kyz5vliY8fEaFCCE17a5w93CidkxvPQ+lEfETVT2AXXUcYWDzW
|
||||
RvWcuhELs3IbEDjYyQqpG+LNU009oa7r7U5h3a5knJHwk2aqUGAssNnF33l5uUPNqGsHVfhKCb4A
|
||||
9Ruvl9hfJVljZj+PRDbDuzs3pIIwyVScDU/AvQ5FtXJhB7jrb6oD4dcMLhi0HTybGZMsliMkAJNT
|
||||
TzAdek68sUc/+LV6eVnbVd+oYgST9NjlTRRyc2jukvvBOOGxU0jVJTSkfM9o9HyJ4epLL87wGTNY
|
||||
Rw0poeyWHFrYAPoSCuaTu1lkq4kMmwAsqMc+h3fzUTz1+ekxXbSP6NvW234b1rfvbRzCj6Del1By
|
||||
EC9P729OKOgJpr+rS083jhhrsAlT9XCB/6INUB9TC+23HyDoI7bXHSdUtoB8ETf10bymYyj7sObo
|
||||
Yd8IPbQVg9a9+FnvtA0753XIcOXZ3iGzbz7ef6k6pdokqlDqyPLKUbcbHAOc+iApMQFMD9m+LVLc
|
||||
DoELPIwZNp/2O00XF2bGFbc8SweokZlJEbXPAPksUwnuE4XXNAPgeWxj/q5Vty+TyQ06Rpb9ojdS
|
||||
OD72593mcRV4AgY7CqpvrmJbA4RPKgQf9zeg5SZlNXVXnnlsKorLf4JvAT8CQdmVto7zZAqojhBE
|
||||
4wqaUFnKS5cPduGiirzDEdDekh8H3obhamJi8wnq0V2NOlEfxo06GBpHLF2lwWKrZOMHyv/FJRzv
|
||||
3OD1cXAvDS9zhKT66NC9OAe4XHzx/VCRhhLOZpb/Y0IPUbns2U/c3CEk7WGUj3MdQgszvOA5AJpn
|
||||
wui63WcHYBJDp16adyxewNRUB/dY6S2tJye2QysQMnpVdXmfQRMpK4axzHdRIIzKv7RPjbxl+OO6
|
||||
sQHMBNCZNxmrjMwUpOa5tHBt4bK/3APsiadEr+49i09H7qJqkLeYySFlO7tL7X+4kDSMJ/L1y4FA
|
||||
FocJv2nOjP/SOIHg7E2s0S6JGuJizRThVB4mBrKNlNcYUyfF9eR9I2WGYcCGsNv3EaEo3KHvR+8S
|
||||
tBCmcuGOWq+tm39pHt48Fy2AIAZqsviL32WMJK7JUikwoqS9ZkvY9+DfpBiiz9abazweUcNpjYUM
|
||||
k1RBqRj+JXOK6uJ+3OkHXl9+An6cXlOIg3IOuU6fCGCpx3uUyyKnwYwuvV6YDRGHkjuGtck81+vk
|
||||
W61OF04ri8tGRiLWH7yLkvrEgS3ZCQ2jJB6ZKWvGF51AGNX3GQb+1QQc+UCq/tHaCflXSHrGHSb1
|
||||
zixOI2/NykGEoZei2mzWm+Pi9Vrfel2FJ4mfzl97XtkUraY2S3XnKDZgN0gyDvDGydq1SB2PGbVT
|
||||
EtvW8wgiv65L07DOShv7AMhgQKHkGrwOLwYCZtnjvGBhJDWQ0bHIgsH7IBlLqqs5D0utA1IOVPdp
|
||||
Phdg7NGTs7I5c46ZgHH75n7cJptbyUqMzqQBJ+jVCI3A5unSCdAYEoVCxDnr41qbVEwv4RBjwLXw
|
||||
+z+8xyObgf/p12BmF5NRzSSK6lLcd8em2CMaEWcTQXxTeMojBXQJF11OXXpyWJzXcTMry4qhu2R6
|
||||
Qr1UxLxI842ujFa/V7VLjsMewLRaiks9yU/yL+hsu6Ej+q8pTMOoq6gDwX5W7siQsTP6Yjh6kFNw
|
||||
68f1eJyRuX1s+hbTpCay/1wYjCAAa23B9Y7/FnjRPZApNqpPfnkO+EzaawIHaeSt7A0oTk2Vqj2T
|
||||
9yVc761jjJcAGnKpk9oa7pxzq7vV2q6p23Pn/nbHtnEeIRgt33K7D74d1tR0IJ/zu30+w20l8TPo
|
||||
9Q5COZX+UzQBK/iNr2AVz+nvbEVK5fuTZ9hGCFWySokRTaN3GRmzZwtRfNJrT8V+hUi1ip7pMdyI
|
||||
qwXevIpEUr0dZXDcUzYGnrAoleEK4mbXJqNCEsvEXNnywZqGph1YOAN2t+OgicHbZebtBmwivStu
|
||||
rPAksMe627mABtbg85A05I11nkzAQgu3WfrNJalGANRHs4hdaT+8ppPJ+v9pdiBlZWwK3+rUobeS
|
||||
hGrAlTN06Rpk3/kceE94zMYI5Qw/W2Woo/0ARRGFmjcMlT/xeK/XOjIKVmCc1kKeNZRPiAB35NFZ
|
||||
YO4MIDv3UdQA98oiTfF148bogLAkUtl0VYgTITeaXR1GPzpnsRPau6TsjaC0zefN2y8Lx+6EoOhQ
|
||||
mKew/iv8kaPeNXWgzRSRAtUWJQizdF8TiR6Ym/zy185LY1J2+KOvSbyvYOpB7JPFZUZuW7nca9Di
|
||||
K2bfZ403vEsj25t+OapBJbimPBtJsSQy823aMv6GPZug3js6NGT4/iegJW7V0OAzN37hGZYpxDf6
|
||||
+nVllk0nYo0TT0KY0B8nEEP8Mo/nIFxyUj0ymML70WlhfSS6QzWAgTA385YUeYxgVnROW/Ugrzve
|
||||
DkhRTudnm2qTiyRERe6MyNdI+bkLI1NFxAfbXFAxUypMBvYekm5shrrEKehu5Tgfr/BofGOrGX0q
|
||||
ZBe5VLz8OjjgmZEYT1jT29IEK7wF8OKe/3/3C2IzTY5B2Kn506Of4vdSq8vMwWwkwyR9Hd/ja2aG
|
||||
UPbwmz7DHXqFqVTdXrE4ic2sMybR3dNLzVQTnxBP4yGd3EOSKWC2bdpZpKER3y2EJi/B2z6PkFmE
|
||||
AlFBKFPZKE5CBz1VX33p0A8me9IcLqioBRXaRK0Jgvd/fVvPqetNj7RTeKyOdCBcxBtdOEHPIbUo
|
||||
4nsyIJX+sD9A16+crJQ12fQH81d+tmXfUuQj2ly5/AUQcdVvWA8td7kHUhM21gOf9eSetKdgseBZ
|
||||
SAAxlIESQ/lZ+Li1cHAyNGNswKRgxvbKPWpVU0MkLlkeWfQRogFfGWIuxIdgKlieil3LX7ie8Z0n
|
||||
A8IGW385ciz5khw/JIPr0949RNuOv6/CiQlqKixtJpRDWIF8x290csQll/1KVl1BQJKk8vtRZHJJ
|
||||
q9H8zNRjCs9l1sCeNHJuKGaToap+UBCGHhAn4o5iAXoqURC3hOG5sV8GSU01yDH17s9cukobgWhE
|
||||
mr9t/fCNdx7NSlsGm6H3eNK3oz8tPctG4H2OtMt7c+SwRQy6uCBsvHFI/Knp9gWxyQQx9Q2QgYjN
|
||||
1+9DOeQJb98NHP19MqNi8hbytL0oWi+uM19f9KDSTltUiUWkXWrWDxLBBR2sJATbYW8ueNWvkJh5
|
||||
XVvf/lz18Hd3SCB5Rl52kSERwgaR966/jq+VgnQorcK+SqmnRVFwTjvwFDZSgfmViY4Wolz3UuK7
|
||||
FkT9ZrCVIK76gskVf7rjyoqJboKXSwehrzLRsC2CXDDXJwlEiH2kf2hI2raHDnZnCNgB9pm4DqGF
|
||||
MERbS/vlKZdialjNydY5v2c9EigtmCD5nEUEtFDlhIxG7ly4xbJkrWMf8Cytoa9WLoBaOb2p46R7
|
||||
15RJ8BxQijqmZ+VkU3AznxiajDo3rx+CR7taYw2Konneh/i92DCQVNNVpReHveUfFqasllM+eFKT
|
||||
osOBzGIKRHG4GJ8Ac1zKkPyp+DK34zCbKGXgQ/Ogjlehxhf2JFwNFrLA7crBLBApqh5zRx4kAex2
|
||||
H1yWQErbDFHFjwlhtIrUH2ElwPn4kT0L50Vcs6A1WEjCDH/BFJiNn0zAWz8ea7ZjhnRAs0gCXqqx
|
||||
xNc8I3LHCQgAMEcQoftGtgfCLKlVUH6BEOEhGhI4dxUagNqIm/Ng3EpDsoDheKubRvJHVs4qKYrF
|
||||
yRYyQ/ma5IF/lv4HxQQhObmTaBZpPBy58MHWn/xoAtOEMIBS47rdF/8X8oQJmY5rqUOOuAo3NYrk
|
||||
EB6TIYZNiQ5d7nKTV4v0Nf1OVoNYefqmcZPUzPrOXBftjv6cWeGhu5/jnkWCMxwh9t13g6aUqk62
|
||||
0MhxDu6Fnoti+JEAdgHuqJJF0K+M/Pn3vLTE501hQC7ExaU00uSpSQCQK+4wCkcoxW/N9tUXR4gD
|
||||
Qo7FwVVaw672CMp1Fo+r8H0aNEY1nZ6tGXqjnnGQaGiI7bQVw2tJI2Tek+NL5RwE4K6MEZhxXvoA
|
||||
uxgJhU1IFtQw7exdspjnr1aigZU9OLRIxZWYJNq7tk6eyh/sy9rCFlWYQNpZnZHNefkcu1vHJ3zz
|
||||
yFQqdulrHqXnGfaEdKO/yJqDu9+FS0aj+m3E06SVzy0PW6CrV/NYy/n8dtQRcDkT0oU1UyMVUjt8
|
||||
BEk38O4zbNYWCfLQic8I2ImUcsoMzNqoQDedWaGFAln6Ag2LEibMWpxtZySp+tZCA6IRYyX0fblE
|
||||
Cb2BXhRd29ihPN6F6nVUzb7NLYmpM58qdiWK0uKHWrbcoDZDXAXVRXcjcXFP6AcpDYgzTk6A1yxf
|
||||
MHDAIu/Iu7U5skIdkYjwJVNJOR6w9rqKiO8JEdT6ltlBJ5x9uiT0xHO4Zc2NQTM3xyWUJAY4youJ
|
||||
mUjryHOgXQ7QD/C01Bg7OANCDYGvEw3Knq/5s6CbEyAOhEpzmL7iGyFEujBecLt6wK6kIbKydPhM
|
||||
LEcOMJMrM1THSyNvYkT2wCeBDgzEQl+BTCU3GGeahM4am4sERY2NgRBS/pphMNkz8vowIi2scJAY
|
||||
CnMSmTUFjqcIAO3ZAq53wyBeMTowRnV10tRapZfnTWNYsYU+jHXAgaQUa3TvXkA8kbCqMt5SwNFB
|
||||
KBifaGqv+C1lkdzSJ9pTZ03iI8v0B3nHMVHcmYDW22eab1eR3Z+x31bWFNc7XlDM2HHi9Qj5sSKp
|
||||
AQpjVG8v21IY2velk9/rLnX1lS4EvIrGULPabC5uzyNENzgjzEAWkY3BhylKLgnZlOIaCvnw84IF
|
||||
pFy9s0EnsdxyCmYOQVvX9vmJuAmPMr5/2mb5TfnR3KJmCTMxGB7OI9RQ7Y5bp+86R8ntx9KABvRd
|
||||
EkVvF8+JHuiN4SPq1rP/mYUft4kmH414gB8BSWpJDtJm7tKfBCArF3v1EjZ1N3fFVr7C2UgpwYbA
|
||||
ca+SNfCZxNqh8wEh+wOCdykcq9A1cT+AxcakOaDS9n+7DqCY+6IMLPiGpcUCkfCDDCMheSHaQuQ2
|
||||
M36qXC7ghbfEfTZTYxAX9hcGubBWA2kVN9KNRngeDIb/Z8KKPLVnvGCu3i7x2ncA/hodwS+C6rPD
|
||||
EWmAgHdni6fT+JV31hKKs4p/F6z751m03vjKgOtmEs+NmEAKbu+845TbojB+3hSZOz5YXlf7mQ/i
|
||||
ZEkKGTXxCjgWzqQs7bsktvOOsSgeYDBUTc73Yh1RYlGBvJRNH770SR66vPtwwBV7TR/tqxtDemaK
|
||||
M6JDZEaUhOWgOl8Sd0Veq1p5HvI+uwwaRECzvyqPT+VI+sbpTl8YdkcVvxTLT3v12UcTUmMSReIU
|
||||
1QB6C5nOSTIABbTrQZ6ZyeIRNcmMvg2mWoW8oWrm11d8xvyVYa9lO1g1Fb0pVSOPFA/BP/VWrm5R
|
||||
CNQ78FTsqhwy3ofsckvdwlA5NDAZba2CnnJPaD/0vm4qNDg1PCGjwIl76ApzWOyoBgbjNKP1x+gI
|
||||
BUQJP13egTdtBz/gZKXB45EcHRHrW8AWay7YTCF5z4qcKCX7tNTFkKuYCRuJkqkT1IRdWogLVK56
|
||||
mcobqXmnJUn2FowUvsL1LQ22e45ZCaBosCaYtjMGUmPSoV7/ir1zR7g1+/iEpczYL6AoPmYFSmjR
|
||||
+TMf6+lM+XSIY79acWmlaAUr+Mh/dNIcF7Rp1DcOnLng7Hgr0UtrGP090m+mysCvlkU0lhfUq7S0
|
||||
XtU7qGYf1pFJz8OOJnhJ89QlATYI45Tg4d5kC5rxX1HcHkzrtoBWEG23dSVHJgIAkojdlIqKsVdk
|
||||
JtUBPEqnmLrXLnCOLuXlnfp+CLfcCRhfVwY3Zhu4wx3JF8A7PasyB+6Oi3ockjFk1lmO66lt+ZYh
|
||||
pJfeydIzd7uQnyh6cw/RyphXGDDHlFW5YRSIcLi2BzcqP+U0nduIS9xjGRpiJc14zMbTO9rEWTrX
|
||||
9V/4magMbMt8TIRvHU55OV9TNGuc0VVkrFu5At9ktreAr4wh77Sw8cuuVwwIjLeq8zcq+htpiQIb
|
||||
lFtXhnKRHI7aPz+hXKTUvJnZFWgsoIT6cjhUoQaJAB9ZU7JJD3lLkdSamHG4l7r8nt9fgTyES/2O
|
||||
Jk/aMRQ0aUFr/deFQfccOUpCZz4KnYmgkEPRf7GuYDdD+ZQ3h8MB5r9uzoquL998HJhMvOu9MbM4
|
||||
Cu9vaBxlTIXPqQjB3g/evd9QxLf5FH0WSLDSXo53xchQJIPu7hwuUffGT3f6dJJG9tdT/jy4F5CB
|
||||
tr27l4LNFBDYlTpzm7jp/NEhwkibNx/u4mkzuv/ZsTfqBEPrZu/PjQYuNOj+mzMUJ4zs4CGF9o1c
|
||||
fVm+EbaEV6b+zB0c2dkNqQ6vTQMeWYdUZN1MjaSBbxXLutq8vDsrQun/g78/Oy05Z72Il3X35Op5
|
||||
qzThJMjxwpxjIgApdOf0wWsFjuu8DxYuabT2bYSJ/AaAa7E1r4BsFDDLinJOFnboxAuSPqXeGI4w
|
||||
d/5suN29OpjOraA1btXSAuM32Jtt3Bb3fhckFiH/x5G4F+aD1uhl6LiG9alzoVc5HRrWP8nMkGpc
|
||||
JukXB1ttwZakMVfGub4Jr3ndmxiFBs47JHNFyOd6mwUNd2mI2VfSukzCqtWiYDCrg48Cdidt4/DX
|
||||
ckcW3W8vVTyf5/jgPyXWd76YsW0heH3ApTBCk0JtwwaXcRMsjiGVjEdde2waS2qwa7EAfInNRkbr
|
||||
U+KeeR5kceJQzARpt0albYCLLhZwjhW+qrR49hfHrSsWlnu3k6Y6CRoJPqArHzf62P6ggJy7Kzy5
|
||||
dFcpkrchekJRdZni0dHxUpThPOk1nZ52viHWHn85PiKzuSpscm+JRD5QyAf8nrJuQTiWTPYE68K9
|
||||
7BpK8svd6/0wlGQzfmRmUuSJk4kbPkLTpQupgoJtKRDqe044DangemXZBD5e8aKhq+lTPuMo73BI
|
||||
Mua5JHJ7ySQLMtnNCY7VU7RU1AHU+Ck2KqpncyPU+RN4dpz6wHYnIBpJOvmgYEOpcthB/x+YTxl5
|
||||
ofs7SKzv7tuQq7SSihcDlBDLaY/AVVoRR/pwsiejfzODM25ZH6+tmNqwPytC4W0ngWKoJdDqZ3vh
|
||||
Xr39XSigf5rS2ulrAJTkVbF7uI+L4yWqnNDwfBC+7JO2k5UJ/qSAqcdy13yTHoKjmDfxdsPJclxl
|
||||
wWORdTEp8SQZn2FoaAnOuqBQM7/PANPyAuhEe0aEcqMupuExM5rNoUhkmU+f/i4mHP2oVREj8I/J
|
||||
qvgst+nRuCrqrnRbjyO7mJyOcE92/Mo8bMAtKr0D8ISBSPgdrpDAGIFPQcXY8thSx4dEaManpOt8
|
||||
XFfln0GgClsQAFA94cKZeWowA7sOqcLJct3oS0Ft3zUocgob/H509m/Fk+BTNvmXb90jiMxXG2eh
|
||||
gQtxFiZD7zNEuFi4KtDEaFaR9SjnyACU5CguH7F9ZCsOFRiqCjDEqtWKsSg5jE71OQ4uSSHuo+N0
|
||||
zV7QSJc9qoMBDTSiNy9/oB9JwF8aHqbMwI0+VCsbG/fiU8Iotp0Glo0EZadbLaDrnne+nMUjWTad
|
||||
1mSuwj+2Kj9jadhXOSsM7KPIpYfl5f22O/5pGH1lpqQf0+UljRZVGsQdMtS9mpmOU9PFp6nGwipp
|
||||
bNiyNCYkckm9F3nYKT2602jcq1bRusifS0J+B+DauASMwAu8eB6VuYstdMCCgCBSHxNWs4RGiLOr
|
||||
BmkHHubB3VuwTpvkzQSHOd9dyb3SSFTuPFiR9KRNPJBkAnfFFmSRbGw1cDgbo3N91e6q/1g+z7tO
|
||||
+8TIeiLoSNGXLQzGj4GTr9SpNKe/eFMmKci9hVFR5r47wpvaqnZle1S/mKWsQmZvXvFe5m7GwHJI
|
||||
I8EQIeanKRTWZjsDXaybctxFNsCJ3eb+hV99Bo5L6w68lZLf/50Ttq+wkF17lzLBxjy9QrXhFBbz
|
||||
yH7yLWS8/UDbnUYqBt5wlZyinDT04kpinDm8W50DR2Mn8W9DbY9YpSs5ptJQzyNI7R+xKEymqfH+
|
||||
Q6npjTLY6EbkJChBM8Tx5E+LpFKF77Cx6PLdHEBBsd3cGXX9qerAn9JmzRoVySH3U4PJB8TvHwMz
|
||||
FZxxxMWcOuskCN4k0aAoeeDfrH0/pilfvD+qtY9D2mUu2Uex/mvGvJxPApu3mOBNMeXhvcYUGS5z
|
||||
PeLyGwb403u2WHa7P2c1ov/i6nS2511Rgm1R86rez7iENbnJ9QvSSijMUO9rPcimcw6sMDYTkTHA
|
||||
/09xKMTdjRkFXTCtAR6pe1BkuNxo4WBGYOuIBryiQx9wTu2mAS9t3m0XFhOnBTAUCcVMqlkmLZSa
|
||||
HIZcwjs84KmHozRoXoZnrWTPWVJ8ADCJH3st25upJNjJ4WirYdzzhCSXc+nnSTI6B0kHLDc12V4e
|
||||
Ry/0a9k7uI2Hv3SLeVpmtbmyIWA2VheyIz6oDy0rmIV2Zp2O60W+u7qNkOfwCuAHEfiISnQoUAfP
|
||||
RSby/fKR27RV5plhLd6EbSCLSt4yNPvmXlpm978Z8U7UgFWq8zQIwDziyRGvXUSmj4Bhq69pP6qa
|
||||
tI1DWip0K5nJTzpevAPsDWFjn6hYOK48VZEUpSfxdAEotTbuONbM4940Ukh2nYQJWoAXQMaYkgoR
|
||||
2JnUFTvxVC7DZ4V2AXIeK0n4op3qB4qV1uRCh5z+5adcLiOoV7nNi8r4jcus/HKom5S4bXKGuBIB
|
||||
jkJIkaJpN0wglMNOU/QYTUsQ+tvsWSFb1kilyLY93o8eqnTio34zeT3SHfJErZjjIWyIva89nJMV
|
||||
uSh9SYB0xjFSNfL12Hy9EtCuf362Wv0oUmxNUO3NVBUqFQpMaR00fikCpX3PmhWYxBH/mvy2cGkm
|
||||
XXDe9wMSe23u5ZnZ8keKPclFSvVLSUqNOpi6Y1tOQLAF/CZVsfYDCpd9aF7iITjgPaN/MB98vim2
|
||||
HB2Qq6Us3KVlQqZDGGBSOlF+ROZX+Ml+bfSa/1+odf3UGdaDMY/GiJSiplzsnFP6xYrMTOwIeRS9
|
||||
bl9ekfZIF0CCdFSz7oe+XM5CT4UVP/wA1nqbyDTFSp/IApja1FhxqkQU+JzaiiHtG1jnGIr8ridR
|
||||
+ofvXsvoq9XVOmrA4nktentMmcbt0FY+QmGzg+cb0Os16ZeQAnBNCrSSm1yvQC5RKYDF/2zRA7Rr
|
||||
XeaTzmUTP025a4AGFAOkR4xQ5rFt3BmUPwTSKEuv2CD+eS1tTmuJkj3L7B/1VgOTiyFE3OgxJS5h
|
||||
TBta5MDz9V6vItOKHoUq/kdLWY6pZku1J+9TIrGmbXxxXuePeTMfTIEJowp4J2hIjG6BdiSs3qri
|
||||
dazv0M+ONbumKuMlQmR6OBSJq3yWTA/e7qhi0Rdica0gCvDP0/xa3uYxrwUl9R0FIO8AmKK5SXdX
|
||||
39NvKN+MsUvo0QsHvjr7Gg8AuwpZmXvjpj9v1/Al9mbS4glgMkSetvYkgf3okCDXQZYpt+qK6IZW
|
||||
HBgINpj9MdAOp1lANLA8216mBBWAoVj5/wCduLaYWRdKNFlnitaCNfyizyoo/1Dx5py+/+ieNNLc
|
||||
rH2Kxq7Ojjlzg/VzuZM90FdO6BzoeXNF3EfZeA==
|
||||
`protect end_protected
|
||||
+1367
File diff suppressed because it is too large
Load Diff
+1317
File diff suppressed because it is too large
Load Diff
+2403
File diff suppressed because it is too large
Load Diff
+418
@@ -0,0 +1,418 @@
|
||||
`protect begin_protected
|
||||
`protect version = 1
|
||||
`protect encrypt_agent = "XILINX"
|
||||
`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
|
||||
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
|
||||
`protect key_block
|
||||
IijDYFYeRdzkel5iYnZFe2NzgYX9UDO+g6PdWiHeOm5P1+m9Kt//ktx0y9l3PqUsSWKKIi5tWbDg
|
||||
OqtBZeM3zQ==
|
||||
|
||||
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`protect key_block
|
||||
TXFD8G5gE6CUfZ/9/aBQvAaQuQ9Q6vcW5KJtFkYqsiROk19a5PsS1gCxUXtSJ+Xt20njQCTMz6jx
|
||||
UaSmsNRyiV6PuCAgdQYvfeJWiNmQq7kXQnkYSjycSJyNe/xoXEYIK0mHX7J2x9ouXxNx6jQFR5Lm
|
||||
jxY8fR7N9m3PTkCqNTI=
|
||||
|
||||
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
0bdD7I2gr0nFDramUUXzPCEqtk/eE+vK1bghpNlKE+S5t5/NbqJI7gNd3XLwYh6qEIInU1StLpm1
|
||||
ZEERnCmEf4+rQBAW7x7u7nIsJjSOmPWtDc9DLn5S3e1Tg+IzLUqT0rFFh5TiwuYq9A6oIvI4ufWQ
|
||||
WwoeY/gITSdj6C0JQ3GFyIRhxG7psQKO9U4fj8El/Lb3YXG1+IGuXZsygyLPjjOU5LRXKo6kKsub
|
||||
X1PFDvdm4rWaB9AqoPLCqp654KCyKSCoufeM/jiWRTNXwf6kL56WQKDXuyAhrasBOno4KOT3c5VP
|
||||
WEHGNdGBSdU4oUFYiOmAKlCKGeUNCxMxx765QA==
|
||||
|
||||
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
ppkak8ss4yKmNiAZjxFq8nn58TDV/6CNcvQivN+uaaTC1viFh2EDUvJp8zqZ2dJOE2mTN9WJY0VD
|
||||
93fjF/bEPMptIxFj5D6ldjwJu+xdHqS9FJ9Wajnbu++DCTUtAQE+y05rqhCz8aZWKGNejsRfG8bE
|
||||
xGYNUIbFoZ9PYrDIdRcDSdZRUBadrAC+WcEM6+/HxxJq4Ly/w0BVbiEq22B0+4wVDXszrocC0mKJ
|
||||
RPXzPj9v5D5aBX2ijUGbICpT6JkVGAjlIEP7HZoc+Ooxppwgc01k8snVnPVI4IVVYOjjlTQgT/qU
|
||||
t0doYgFMU9nD5a1hefzXRkszYn9RHVZE5bl6NA==
|
||||
|
||||
`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
KtmDUKyPqH21pzMoqq9CPc/SXFhh6Oz2JrLSFRZBS3mGc7ebGc8cQjlvJpJA0WNJlGqACicdvN1t
|
||||
A7mG3V1xKtoRdR+2MhucMQ7loisN8yDj3+zqgbM5bAdlz+62WovuGfaM4EK24l8CXSfBLVGQ35JP
|
||||
2zB0abBrel1cOw3DxvSIS/5wueR9/Ul+GoLmD6yF7cV2ne7eGwNXQ2OsCqdcb9wK8gNO1YfC3kE6
|
||||
WwdUtjutDvyXnV49wmg6nCC8RAPNWbIhHiMMtpDjux6E1Rkd3xdCMDrxrupZyNQNtVmzcN8ITAn5
|
||||
BYoTBON1CKVljCmLov84lxcdcXGcSaBAtLIiAg==
|
||||
|
||||
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`protect key_block
|
||||
sjMrK19OPSOpuNhtGVc8GPvvQoA4nRSUShUtMXVan8pbxWL4SmeH0c+Lr407Kf0YXDBqUDDkheov
|
||||
bvkczAmQfT+dVPmRtr9F/s03c46gcXSPX3D/EHROl21MVjaptRm/lAFzU2JR3vIcBrSyn9KnB+G8
|
||||
cTUA3hZ8VcZWUlsE5EU=
|
||||
|
||||
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
KDe/Bg6fHbQcPjNnYiQKwKjMy4sdSqf+Gty0JJ0Cl1tXsbqDCM+FOd30mp8wMVyuqAm1Cs7QT211
|
||||
JO6FwTQoTSe1+Ag2KZe6AMFgHaNj0EL+M24h7wdNN5Wj8M9n4Zw2cVNCAcQuMAGYbxaWpNTrYMXH
|
||||
BpdQ50EQ9/kLpocWC2JhjoxshWpofJ0tpp9WlfLUPTm7TftCudU0M3dMNjnbl+Mfa3yuTHWt8aDY
|
||||
6w/HgH82FHAd70Mwbh6CrcIChQUulExaSON/uCwutX0SehA5/ooAAlnWv19O8kXTawUeKwYKQikK
|
||||
PjngB0eHiTimSxjDCZaaor8VbS4WfO6DyMwmEg==
|
||||
|
||||
`protect data_method = "AES128-CBC"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
|
||||
`protect data_block
|
||||
zdxuJWusCyClazadcRhUPxW/j8yG1KcgxLIktJUOthD2GbVjoKwh/8vvhQ2vOGd+Aet6T48PIRDT
|
||||
XHENC6aTS8AIh3g7tvRbyCoeKM9VNOXoZw9UPqe/IG/kG3m+izkQNlJZjb7mCWlXydYQfFsTWWBm
|
||||
Xd9Vd3bOc2W78ckUQYqF50FAa/i7kPwvnypdgEaL0CalUaH0UDkGfC/uaDAaPlcz6aEgJSjgjVTR
|
||||
xL0o95yf477mk7ZGcyHHb4MCEoXc93X3fU++XMdDc2OWdsVTBimlW7BjWWP+5k7rQYH0O8fGalaE
|
||||
zo/qeY+gP/xPRpacShKDYhKI3YVm8xTUTlqcLK7ab736Dr3iCE/lb3VKRV1h2EFMAhu2GaZLcq0Q
|
||||
9jt5x6ZV+jUn/kq/vN7Omc4lXRASjcfTXkD3mf1S7QbGyZIz2I28ETThG4z2amlIGcrFXk+Y0lc9
|
||||
1SEYsFnobnp5LGnbtZHUzeK0IuynhmP3KVXGnekJwOhXBkMdqv9GatTkYF+J3eC4N1o59bpFGDED
|
||||
t9QnrD0Fap7K390/iMlGtP6wzh2Gl61jyXAXaHSPywvukslSOiHacx5wBJNQmllO4khSQs5BU6+m
|
||||
UYppqlsGvAFpNAT9Y4gjvbMQ2IzZOKEvlfqdA7CTi+z3NEgxJ6KzsRY2UW4u8Nf1Y1MhpuOGvWFH
|
||||
Zdq4hXuyKzT8xpPTmel2vCKCAKh2ZPkHlFgw/IRgrdDtg6a1kCnGSdWnQ7q1FPZnClbIS1hkCE/m
|
||||
0pvHVDKe6UzsoF6gp5tydIzRJlBxm9LUtTAezJ8XhMg7Vse81/RHwWzbRua6LQauAlRjjNr7qhWw
|
||||
OnZMimF1XQAkTZ5t9p0gaumbSBgcSzc4EHQsJ+VntsVn0gmmHo5EYuNH5d8N1lLEbPdls+yZdaRJ
|
||||
wRmupx/sfemEUImkEW9YmsRxdQEnxoclPtE+nPp7wLuGBPks8lS8AOeWx5da20c5xquzwIv5YhzK
|
||||
XFjGraIDw4nG8D+DPvxGwEumVNsmPUv9ST1DMwUfUkESF67BCU2AEI8/IDT5mrn/FdaYojxbpqv0
|
||||
kjCt5nRKRqf6vx3HWsVLp7NgFiOp26dZx3/PMTXTACoaIhwYpzHnLPVcL2Aoy6rPdMqBSKPix7TV
|
||||
uLHJM85hKWTizR70WYkYaextjTYE2nZjniboVgYJHSID5+lK1LezYkOJTTzpExf6zftneLjXAOpm
|
||||
XkdbvBpcLPKcZQWHbeuIipHLhwDsWoLyMk0WAR9lkPKcUeyJfmbLpkPAkebHoSzfqhWVpCbipbIq
|
||||
wHc4GpzJMM6+hc7LOx0QRPSStXW9PGRK21vbYID+Gx16VF3YXJUhkVU9LCA5MBgradSMsZWu0976
|
||||
O3dV8YrBcH5q5DIWAzghnE/050GAVpxfwGY0tR4WUYqUtohZ5l5moUQBwQKqJMV3hB/HqlLp8Fyf
|
||||
IcVkDF8SZj6Ax3Jj8XnwLJqAkzASU3MS2FDV3/izQSb3nsBBq8GpHX2FNmpltpVBxAVuKagYou9V
|
||||
Doef+Vd9j6fHhtzdgr+FF8jTVTB8AbZs8x4XEMjf5kgsI0kLaLXAKLxRJEKyhg1OO39XUWmBZPig
|
||||
vHqTjF8j19t3Z2bCxUKnMyfm7CREPb9G3h0bW4sKfKb+M8Qb9pQcAPXLMXRIx9DTtFO2hzStCFgr
|
||||
GHKx1N4UDsNJo8N+HW2RteKWhifGReR/fQ5iEv2Uy5fMvuBGPL38V/r1nUHJUgvaWzcaL746QcHX
|
||||
6glFFpe9brmB8mttLs2ul+3MOLhrnZcbDA0qHkfxSSyH1N2s/g1nGK4KsI2VkFco+v27c8UIMO07
|
||||
aQu5wzKox5wITiSiswDUdHmHWEgh61cmVFkJ4GMnPXUXsz2gpgK5NgI83OsuR7xeoO4gU/UiBVWk
|
||||
L4d59FqESfUfrelmid5ZAO+IArB4xYXENInI2Cpm0Bum3WOfpniXDYpdy6tHDWH1ac5Pl5Kye4Md
|
||||
W/6l0VFIx984VqzBMIPst6T8/qqFzMdXn4Jvv9LYH9PFrXT/0IEL6GdCsLZ1V6RB3Y9ZkOSXFkmz
|
||||
M9aO/PBKGAdqI4aakgwl94AZhsPvAiBs/JrB/RpbLPNHDpEXtEFgm+gKl/5pSOo1CN77nCyggMXj
|
||||
/+FyIFET8k12SnEvKjA/s6YHUtzeXkhl/DC4hKcIj3b9dUcF5c85Je+/PYirG8qbhJpjijFYzvC5
|
||||
+qT1DEZ9xrEa0SWvfByiyXa+Urhp4V2QgZ0FvrNl1c4vA5unZT7aYHmAhksotcaMbmzI8ZMQ5G/X
|
||||
JEPPPtFWFy50uvs8WFzBZtW/MFlDnY5M/LRhP+kSM21XBDMwuKxVmHll522W+Q8PKZ6zbk8AzP8f
|
||||
Z+PZ/yxHy/AtwrshRtcEwyMG4gwSd8iIdRiwg+fefbUYiEbgpVuPtDJK484A9ErrNkTbLbQg7i6T
|
||||
4Ldu4U9FcyLiRN5Nuuk1R6y/oWAiWdQAyplboc9jGFIrDGFeAxielLJYWCdS0a2tUuxwJ9QNJ2pU
|
||||
2/n09RqD7veXq+ZphSexcXCUN8yOP0buKGvLGFVWRJMYbt0kKtzepD0FcOFB+Sf6gR4OuvUaQE2d
|
||||
DnWBQfIraDDANIPc6wJtE7czNJj63FKCr8P3Sg7wjh2+WK7P3lb7tmdltSRSwJ/941f7PFKHbp+P
|
||||
Ex9QXJSG95xYHPuoXaHtXuQutFhj0tMJOaXlJZM8oV4C7cHoYGXSl2WDXmpq3Byb+ZYMYqwcjYCP
|
||||
xyxMw46BSSwZalhuKUP3u/Gr+6v+AXLu0zelBkr5LwkeZxrTGWWoh57muxqssixRicTTVuEO2P7f
|
||||
B7ZRwy5vSXvFfYQhfB0gCVcKZ0dzf7ZP3ET7Li1LJIjZE0GwNovHeqFB0GRIxJxMOWhCgwV/KaAP
|
||||
n5mQJHtDJLVIz1woSEmQeo0RhI/DV3KICEaZXnjLoY/NIlPIEfECubmzz89XVXCabZFjDg8JmK+w
|
||||
FR/VOfrx7o3ZJMqEqjExLjv2d7wN0efsjTo1HYKHCIGOrX/fA1bvCKVSQnf829zfwYTIWAbuhhIL
|
||||
0Wmh6JDUwVvQtd5wsGv0SXdLsTSWIjdBMglKn2RAF9jU0Db9DBjxUFvJXV1kM0WwFGSXhcDFR/HH
|
||||
JCpxExD7V9FMPdKSikF3rpv+OfGEejQKnPCuaw5svbazUT1mQ3vdvBeKRNszOf0YeJD0P3j71r7t
|
||||
HOKD4hpKiZaNtp1uvPKnMHT1qhxXQHA7ZO7/oH9VSbZ2wUR+5rQPFHCQNkNYzn+gV9PiB2or+2ZH
|
||||
O5EZ29GecIOtu0faCe8rEFefGcWD64bZ3Y6fUBzjDWZrF//+CODYnetVBP03TgQUJjbmpvuaa9ye
|
||||
K9gw6ebhlQ+J8Wo8jG6C8bynuod+AcG5o0h+AEAOEvluouYS2Lh6zVXjxYsBDSaSeiOroQSxAlcy
|
||||
vXd50jJe/ZcIjRxs7+ba0bAkeVmhyXLT0NRuY5z1Rs7IZfhl3fPR5b9ADevMiezhVjTJtGHlF6dw
|
||||
jT30m/zzMoBUuz6NAoM35PFDNLUIPZIChuas34OlZZB7Pe5SwJNn0IzjoTD/Xf+F9fqwd3QBMztv
|
||||
6I59EzMkvZlvSuk6VcWupmAnHyeVKpVObFDPKuQoCFoWDFc+WFNWic29Ib0vLkoDDK7w6eA4Hbwu
|
||||
6hxzaxHX3W6u8AzHK9ROdYUSmY3DfT52W045eWOUgp30uES3vFw5bxV58X/+dhKcZ6EsiDsMxvKa
|
||||
h4Hw952MIgdMScyFflWXTAPJpYZ3vBBzN29GVTaJlf26LjgOYw/mfJ2pW9W4dp9HRd2Qx3UJymg/
|
||||
biSxMM4ramnbMQhOuYO8zJSJHK9tat4xn58iDUIWNMIPD2Y7adP6L5qN1BfsYrrcDGkYSBk9PKrO
|
||||
vagDj3ept/Zy3POp+uJRVimU5tqyg3ZkXNxre9Hy74UhyNh5x37jE9I0seycYHuDB5+YXlEakqiq
|
||||
BN+Pl0qp8CoBtB37IyRArCajp6PUSM/1Um4tnA1QxB5fsqJGy4e7yrsspue2N2gdXYUjekhaHo8i
|
||||
z3aLMwUyVehz6jkTFKCOgk6zMzvjq+UG8WD/obLopi5TOUsVi7JxupKxYszauG2Amb8fDHDFuzrp
|
||||
WqBmtlB050HRWA0Yl7/kNJkhUCnxYYbGNu8gHp17m88/PLpGlY2c+0xgwT3tLZxXUyXxm5ou37Ps
|
||||
5SJVgtW2Z1F/YmEjmfJt41WZCHqbnn+VWbHFryAAvzfgE2UFGGi1mY6gDw05wheg7YOMn9QkLNmG
|
||||
eYKuOBEpY2jhac2t9oFe0qJBxQVt7gyiPLxRw4o/aiglgkt12Lcsw5FLd/UilRzn6jBE1qhIfIBv
|
||||
VSEvPk5TqfCDbAdN/ZpMnnNWDtE/SPzECibPW55SXrLECX/vEZRhWYZWBeW15F5zxLSVT8cdbyDV
|
||||
qlwhTJpleh6T6yyXASlGcfAgU+j6VvXYGBvcEJVn5qXU6c/65KTb2xNO8nnUrysT1F7pNjtUXBFs
|
||||
iVUKp5Z9nlAzvP49p1ByXY6NjzVbzJ3EcVGXfsiHzALM3lJpq4EhjYGPac+FCauyh5NXAcidV8Kl
|
||||
4ou9UKKmj+3OR7WJbNTEX/wXTM7ZGwrae0Y75WLZ0oOT5CV2/jU304ba9nOTP5JLLJt0VswRL28I
|
||||
V8fkDJuK0YJ7FFOouTQGnAl+/H+FI2hFt6DwYyXCN42XT7Q0xo/NJAXIqC/PC5kC93AP4t5EYydt
|
||||
jOCtSBj41+dnVMmCQjYcVgcxLhr9oLHJ2omqV39N78cJjht98xML7P7yboRtqSQ9k6Fs+iH6lg5p
|
||||
dIiICjI9qqjSTz/Oi9CDjKlWfGFS6GVY11N17MFm1GtymT6Jj0iCVa+MRmbiYkUy/X9IH5XNebZV
|
||||
I6L/BN13RhH5i2YUMpd2dHXuKsnGGk54BtYQUC9hoTgvUyTN7PEr/Bo+DzGxtNeHopmFiPMSsxsc
|
||||
T+rs5Nb4XGSV4ieib6igW4KMzDFBkF8we8hnrxGzRkHUYTUK890RctUS2OGEeI5RJAqVQXx+AtbV
|
||||
KY6yjsOBSelZ+CPy2fAMRZv5RAzbUFscO6alTDv5L8Sa/iy7oXDKbK5j0RItL3VXKYfloDGcI9RG
|
||||
XBctDo8hjYthjj19P8sA0/dhHy6QaI0PervQzExoNatoCRJuZHfQl1/07+vnr6RUkIW538NrvQCp
|
||||
c57mahzQ1NlnPrYmG5jZpZr8mMLjLdFdN5lN4Yzv49Y8pTjx8UxZsRZUQdrv3GBo6fMGGamaUtqd
|
||||
Uu1E3NRbhwy9BHVj3dCyI0AGFuYn5jW+XaP/rR3gA5+3dSbxIMwwgVjcunJXh+isa8e3dIZue3y1
|
||||
LLnNk2kasbzMtr/3/Sw44Ca3Ti4Dt5IMeOzHefbUIzT7BPwr77zzgOi6jrCmlVeSGEHQrtbfDnDq
|
||||
QbRUqHXNtDMFZLTPeN+hfTesTUFtf22u8t4G9+2JFAysvsqlmcSSmUy4YAEl8vBkv0Vmp/FNyTGB
|
||||
WwTwaKfKvij5zTVQ20eyYbRXTIVq1p8uf5jgR1cb7igdd7SaosyzBS4Xiu6I9OEkutw02AVPyV3a
|
||||
TwCSrtaiyZtRZ2m665K9oJ4AC5fi4Bs4IPPKrppcdrt4BK30JJhcPURfF3wHCbsdIZVxOnT3LQUt
|
||||
PPP1F32ki4AbvKYgVmdbX5AtM5aytHijrg6z0xcHV/zaOTJATGJD7NQ9BZshxxt4Jlof3ycmQB80
|
||||
AIDDLWOaexum/LHpongK+yz8s5C+UzgSTRrNOQAGZNZ25dpMflZ32smelRfcLuoh1UL3COD7puu4
|
||||
+ODINP7Y6eksNWZ8xRjKvtHy4zyCP/21WM8nh3jNK/SHKqstoCtk3U6ojgqr2Vv/n5Er9h+4ckFM
|
||||
AUNJahqZVQ/DV7TtMvAnTeJTAOBd/5clj67J/KzuaGIrcH5c04cgU5KUWq/0XBnLAytq9e5roD/1
|
||||
/5KSKzt/BVEKPS0ZyeOrp9QtYAdbvh5H1yg0jnYItLx5nxeWr9m5KAhaYHVe3cJ1dduLqL/0yrWo
|
||||
eF6lugHOcx9NIkFz9Q8k9XEVD24r/UTf38GXmPokn3JV7WMv1Fih83BEyI+jjFeRbnQXCQ2PmR8a
|
||||
4WdnftbU0uL6yLeJdHEes2KQsoDDYDdB0GBJHRozBGdQOTa8UTwz8oSVYNZovaZh/viA+zms4A2i
|
||||
5OLKPiGc8Qs1g4SaFEh8BodGuorJzZFgg0vnjaE9Jw185M49R+1RbShIsuXgnG4Zj3KujCeuSZpo
|
||||
Nmpc7B9mYmfV7gS6YCwlpdJEG67ydbakxI84ECS0g3iAx5VHYE8Rii3VX0sojaHtfeOvZUDSEDZj
|
||||
1pJLXmghOnEPzCRnXJrijypkgJV8v8/8hU+bJJwYX/qnJPXzpwkS+XyHs/RxypoooUwg9Uiy0eJo
|
||||
n02X45zLbvxFoKwE5E5TTUtgE8Av6jghTKZtbWQPdZmZEauYIlc/zgN1JW9OpAkzCTVwfkBkE/D1
|
||||
UU5aLr1o8fsIkrK7xOjfzA+bRv1e/hY8f8KZ1+GZz/Ae+UHc1mMcmJE50F2SkdJxWOvneDZG2iy/
|
||||
NhqoJ9ajY7Ygo1VV9wwXKpFtyShG/HaUL+Lac1uxl62jEo/U6zdr5NUv4TOpVqUSrJBWII0IzQ6O
|
||||
X9O3uZs4ELHINz2ZKC2YwNnnV9rufoE4kgiojievisBcEOy+M+0/AfSc6Taf/6Qe7VwraoCJ5DB8
|
||||
93/vJg+sG/p4ujRvMghdMKKl/j2yhzAOMGO4J4vOC975HS3VpeuguzTkZc6Zx94vOp7gKPkZ9d/M
|
||||
ohubtb3TqwqsglzxA+fVSRtjoyTezmuFUj0BmlyO18YzbdvlwAbOOum3LsTC2bx9XAqwFQTey6q2
|
||||
xEcNzfFPsuMPseNJE2muD6N5ZoHgIj6VO/IzY4j3fM7+Ccy25DPZILDBliiyLzo3/Z2aIsVnmcJM
|
||||
TEFyCqQISziPeJZ1M5qmNthwltFBTjLGk308IBwcMKcC8/J116WaA82AA/LFxflSR6BsghTQ1KdL
|
||||
WRk1HWoqsVMr5iy/V6mWcmxOCBSsbpjDBSYjPEanGYI91B/7FkqAE5xcSwOvLSjqc1/e5jPP53Xc
|
||||
HVtHdrX73LGD0lukhaWiLxxxYn0hZPAsPZfkqBtIDv/VQYjeN/4QNrsRKtfeZhCDSkRVBhVPnPSK
|
||||
njm80Vr2WT8RtJj8sVZT1qBo2yJsyiRx/DoGNkYoKjJ9os6DNFeUb/+EBjLckr23RzEQ/sjNYh/E
|
||||
rlYOVVq7C6HqJ3t0CgS/Pppf6Gv+8UNqiJ22okphlSSgAr88XWpbzKvP1MXT2D8mzVwNGxpLp/XX
|
||||
3HkFDPRTDbEJL/QEUOHSh0XPnIa32o4URmoQBGWF7N/ru1WlcvPEvF1vAdGzGB8urDIhkFj5Gnqs
|
||||
0LC4WL1xh2YmJJz7N5FYoFG5+N4ukmkpOAeMnPsWOrDlqch5ZBRywnSml6paYti0Mtt4w8GXxsb5
|
||||
JOfzXBCl+JQ1pZMdd8rXAXhGZLjKISDFGGhB1xA+k4Z2ISqRH2Aml8ChsXMpfSaiL5GP1CDAgl5g
|
||||
3Rg7ckUc3bEeSDi4WoX4P/vhm3W8YticDv3vpZ3pFIrQpyy2/6TkelIIXOSMYLSeP0uJ/1NcQAqC
|
||||
kun/Uav3GPpPNjWi2EKUwlxSqyBlMi9cSyh7njr7Z2g1kExtktGRRp7CQZ9avFwgWMrvpxU77rTj
|
||||
gDezgWLrRA6kKYL1fPX+q+Tb0AqjvSP61VvcNBfzJjbQGwuc8sEHsN2jS7OwuUNvL/RT30AeX5WT
|
||||
frKF+Rt+qzEedzJk4eCvOcLJyfTNiuq+H3kfAak9yOo9kY5M9ZfdWEsQrLVFtoWUSyqltTh9Gk9W
|
||||
IF1fMbwomsP5FqjwMj6fwTBC59FJEAv6RtzOEB29k1b3Mt0J1/VYEyNZZBeyi2349l84awuXOgFN
|
||||
45OR6EQJmW8TUg8ZKtJBDJ40HN+3FtVTn/1LzFsWysVcmLntRE1Z+L5xAq39mjX6fYaX6eTy/KIt
|
||||
eIhgyO2jfKLDn8yQfI1OtG+AH09Go8IHKTY0h4L+Q6XCnF1Z7vZOU3aCuO6QljG4sgs8hHoUUJbo
|
||||
CMUzn4+nlr+PopbyOqEmyaC4zimSZB5fA2eOEDU6lRZjrvdXUfI+bgdWbZzBRPIrVOVNGAChsqDn
|
||||
P7PLo1JcC8EVIr5N18z4w0OxobEcGOtF1iEpy8Vc4IdLFpQdPH9QFb8PWM4bxU04GIl2hw57tt/t
|
||||
gcLInH7OdxXxi51ElAQ6lwr3HkqXE2rPGSzx76oJ2WN/QhZJ6t14S+rjqV5q5qLVULCt06Osu8/d
|
||||
tH+10yivPMJPk6STgI71UegJoYFEPxpOWH7ODwmBldiJ+u2xVcbVdQccsNO9Uc4lNM7M+2JAOfyv
|
||||
U+CaMFoZ7AvrLCuB9FseqPTI/Isvjpi6qee/ezztn5ut4oukXCljve1xcHgZmedqgw7DmfT/8+31
|
||||
yA7PtIJ4m6hNklxzPlrUxAc5cwmYRPEwebWvX54FFciUhgvvkfiMWmm0JrpdAaujtOXS3CbJntUx
|
||||
tDC1jnq0B3RP33191eCFIsCNJEgCNBitzVpC2Ct2/Y01YNHF4iFeYO+elai9a55B5wHw/SqMus1x
|
||||
kB3iDUxlWY1jk3FoHYTXAOs8EfmTAv9Ykfz5GKhAToNlR4ePzTCa0QcDVwDndUzK0iwm/OBQi7D9
|
||||
E/lP/9ZumDbVWmLWnovZBpmZBTXNkNV57rSZooM2KOYhJeVLTYVHTUtCMUcW1TSIe8AwGZdy/9CR
|
||||
mi7bSv6wAA75+Q6dxk8w7FjJNB0AxmXRXLz5hVVpfZLxiBqicJooqrBqYKgGJUyYV+oK1oIxamd/
|
||||
7ULnQqxZO1OjGKdlsbbqvu784mAbf9ohcQec8g0u14KxmH13+R56SK5CZI63Vn4+pCqkrMsQg8X3
|
||||
adj/ozj9/T1nB7B7ujIn9q3tCQU+SJw3Vb9BZojVsfTGsO8OVfm+2KKW+yH7ZhmIFmu3PdAdm97l
|
||||
0i2N3B8BSUvK0Lh2Tpnue9Bk6+Tu6WL+eba/LLVG1CCG+6FIxcf9lY+IzhUytviizjgy9QPMRVKy
|
||||
737+Rzx9VVbMp6yw6gy1F7e8TandFvuWI7tbyLiBIdiwhu1m4jg6Im1LUQTUuI/XmIee11n9qT2g
|
||||
0CxwqDFVZXvnB7YqX4n6nzlvzko5gliBbmfrNXbncamyR3LUGtAMFLtIVvAv93hv3gAxVGtlETCB
|
||||
Wil5OZzxzL3mddQWIqRWJ2QT4P5mFiiKLoxtVcnsdiIreUzVlO3ZMJ8sDj0+MQx+AXvHxek+LSz9
|
||||
vZLlI+32dU90teb+aOdWdpDSr9gi6ATsco4U/cSRTONMUyX4IbY+SJ4fq3099RbtYKmWY4JmrAdo
|
||||
4B8PP24z/r4zZ3LgdgbB9M/VngcX8/ZsSQ4bwC0kK1g5RxWexVCInJR/Eoo39CbYvK87OPeim+Ht
|
||||
YtJsCQXJJWuTaRr3RGHmV3pRzOMcX9E7nkDUubQbpZKXlf+8g0JlMcf40/cOdjyfiUaXUnHTNxgo
|
||||
5bR2D7/CCXfgguV6D0WHhMHJQGTgD6fFm13ZXhzuJ6XuglLmYhk+JP0fC4s0aEjbWemsE/O+WZCB
|
||||
P9XgPokjBRZTduYx/7Wp1K3iEaOmpte8HPqgR+BtI6Kf5KpMm2CXOyaSgiSftCXdVcAcdYzcX63l
|
||||
z7CoWxohqaYvFeq0Dxj4PlskQIm0/hJon0jk86LcTlk0vo3FPITLm61ITCDZil2qwojjw4D8DnkW
|
||||
JVH8AyTdBHf/8StY8N/tnTrChq8Am1/fcFDTOvstdtcKZSl5eNyyw4yFJqm9hFcbepW0x8jHbYTI
|
||||
a7wmX36Z1pEZhSGUyU1LZjce9D44ECa3prmAAyENKAQgbTMVcfHoeOq/iEGT9vJBIB9Z472uFjly
|
||||
nSVfpiIJhCHHvP/W6dBriNL7uH566h14nUCg0S2/a+dtWOMA7WmjyWluvnMByLDZFi7Y8VXpeDsf
|
||||
8rUPdBCO5xXMTeO47j3dGECebcgH0r7oqZR9aC8F1ngTO5PjaxF228aAg1OFgQTvbOpwKQCTyEdL
|
||||
ouIzuCaQ1Yoy2PNMfiXOO0cuHPNMfXvBP1gxhPVUGOfB6OjuQ/4ShJoWjbD1vmhRqgSEVfaUsIWc
|
||||
ooHxOdmEMv1otduMwL/zsRFvmbMYIZJddQSUE0VwH618xUQGvSZEFnZ9eFGfOWAeXeMOinGmzfRS
|
||||
CF76iyVOaNEC8z1LI78F2+EvkDw/J1L2RJ7mgEs/PXyG9I7TUqjGf60V+YL48uTvY5PXzTbpZGjY
|
||||
DrnLmRkMbasBQ5Yvg5p8wEDW3n1x90+HljQmWVLYvvPUev3UW/fUVW33lxdoGmXVkDFl7/K2IaP9
|
||||
lSlxnQSqH8jnXJiF+I5v6rHsdHzwco2SsoUI8WIAW9/RbGIJLAdJa09Urhf74XXvbrc0j8GZ1sru
|
||||
56UP7HC0ruwDZ+IVIToOxmCoIWq1ttbGqP2P6FD6T997fMtUWDWypxJe4GvHzJ1vaNPOJwmhJevT
|
||||
NtBSzyemjXI9mCIRwOm/pu/Xgg1tE+aJaJbeJcztVOzNCM/9zDts86oMHW7A2ruwMBeal/ZkfNk4
|
||||
FSHgEzj/zOY4S5Vpu7vASTA2kwdwzY8HVxRG5Bc63OuBQFdvL/NqUy23DIB1V6jxYno9BtKtDQh8
|
||||
IRDFgX7KW5c38UhbEoN2Nsam3GlCGsJ1ftJRrRL6xOEhwyQYdA14i3uAig6zG8IQcyMA7h0AZ4bt
|
||||
4KfpN3lwtAUII8zOgnquW4yfpgMCbNaKHJfgst8ISErj7FoCKWpufcu61FMexo9A7JrqCuq29w0I
|
||||
dpRR8tLaL18LcyXAVRlzGsZICQHBTkzrESAklRzjqy1Wh1RLaKTLxfE6hjStkmMGDKwj5BLo/kbx
|
||||
jWl4nUD713ZxJ3MyQWe51imqfiBfMxETdDSHXhJzEQJjHYKuT8thc+YFOBc3DaqM0sskd7AgXwij
|
||||
d7Txin3RFa2mqJdqD2h+kvfYo2lk4m0hcXSKl0xKfDdvPu87GdXn2xkYfBPx9/DlYjpdhxVcyjLM
|
||||
1fRWB2OQMLHEPtY4agkLA5nICxaZ6B6ahRTznKs3iXeUkQqoy18V43aEjDE4rJ7o5UURFrKpFerl
|
||||
gb4QSAcb3eZqjQAGwx8HcvfspFvcHNaPOEUsj0xhcpXb/D9Kjm4fsDU61dm+dhal2VVxKgwLL7ko
|
||||
1GouseClZMrXrjQwXIoXFjjRthggD6w+0QC+s7h7vEjK4hNUY5LmEM37fLdpYBmKoHzUM5upjfag
|
||||
lLwLfd9nQm8qyPH7rQnnZ63zPY2aj+3kXuo1ikOUIYtpPyTpF5kce2sOJXA7mjdtqiNYVWb0tmrk
|
||||
NnQJWNnfq5OHXl3qKTJBsZxUJQL76NA+NkH4bzNCltiT+QPN1EBr0pF6ZLslAlRhMZjLxo3FKrXu
|
||||
46KRAyqY/Iq88AtwEu1Zqt6Vw0ptR6xUlgah0mHyFlv/2khtDPpeLRcl6OneZlqEt4uBgOF+8orQ
|
||||
Ywi1Q1q3ZBCP0i6FsBAu7/y9C2p99WTUBO9R/og6myMWsmBW8ToJ6BbmmB2jFIjiZ5kmoI5GkjKG
|
||||
tO521pj75j+Aet1k2X7kLLO/f+Z+OiLtBfk7y3qk2jSCABBaxJx3sp5sLzvZ596RxKSuD/A+XpS6
|
||||
18b5J3t76SUYs6nNEj3BMSwPh+bMr1w7WBRYTmpqLMGQ/xcY2XaDEv+zkqaGsqkkFMjLII6bmk9o
|
||||
62KYSNpR+mNSyD1MA4HXSfTAvxccl82+joeESSylP0glbA7jS048AoJxDRBVEvCAvg4daNKMh63G
|
||||
bQdXfgB2oWquxRo2bKdiJ9eAnfLT9XLX9T5zd/FXLfs/fr7aIHESiz3N2b+rthG4uRxe5PrW8aDN
|
||||
v5hOhQyQLB5Row10SbnNtEMZXrR6Y0bbx0pFOeMDfRbHiJw3LaE+f/ZNWoH7+G8jExpO80OTPROf
|
||||
rduUlEKR9RFu7DMb4TYlmwKaQT7b8cd1Q75aRe0Cw3e2oMJjPdGiXCN3il01CvIZySih6ShFMJAz
|
||||
rE/bEnPixBKgMf0mWfpHwC4+TyxJG1S68J/8xD9IBQih63Q3If2c8grA4AGDN7pSunqczpxduIPp
|
||||
HFq1IOYohav5EjOFoMsv2YFvDQww51B8ibHzBqaT9jYo4a37az0YQT2JZdrwivDIYVEI/0CYiEGO
|
||||
i2DAtGRchY7ZvmukU89cBswjrt5/yMRCG4Hp3f6zY5nngv0vzcUq/10gX/3DuBtc7BdpHCVvQJSR
|
||||
8Dxj1d37w+CGD6Z1dHnstht7D9D23REpfbBr1rfAqkJOOeJDAgvHpJiyXgjVcQt2Q28K9om/brxu
|
||||
NIh38MV8OFXruMEnktT8pddILvg5LapZ5mrxh8aNrWPbbDrslaqn0U/rGvQsPf0s8nAPIm6vl72t
|
||||
klE5PyJmmTxeg0YkvL+W8YV1eMMpsvVboYWV31o5krUYhnNXv82GyRoQaORCBnQSpHCa2Ev6ro0c
|
||||
FLRSel5ssoqOnnblyGxoUkNzncNx8RMJGQBpxj2QFsre9MrjMt4OlHblmr5+On+M9WgOSHZv8Jig
|
||||
P2ctneio581o49cScwqQHXqlYXL5WzEUPSUkwfCOuewrBMTrtscfeM/2Oa47QpTL3fjnRrc8GvB0
|
||||
VEJgBoqeLxCkylkF0e1vVs4K6JGICD6mqaPgwqtv0n/qSRjt4Yf62bYuBwhOxhTPyhHLS0VSfEhB
|
||||
Ll1kVp/GkCWsekaXf30Fq62i6p7EuNN1zZahn9MFODLJsC6pb00A+uyzYGpvWiaeqfTxDuzJxPSY
|
||||
1kJBqLjYKggDunDQjnrWjb1KuU8nL9H8w94eUwli24YFRzF9sIYehtY1OLyI4Ko3jqQatqxfgIZO
|
||||
GsIOTGNdDR4uGqXkQsDoZZ9ZY/r72ZubnCtn80DgSTFAagvPeG2T7eG7ZAU+EuwLJ8BqswcUF7J0
|
||||
YZDfjEhMZBVlpIPKVd1On9Hhskwkxa3K8eurMi0nNEQ1dOG34z8NGl0KHItZ/Xoq1O5Z/x91IcCt
|
||||
JGLsMKsZUV0QhSs8evPJrYV1nXRTK2iVpCQQIwkexT+vBL4crCMHsCvs2ok1wtKZnh6pWrtVWZ31
|
||||
KZqJ+8CMjyLDApIwY7YEezfuUMQotiRCEMAIMPoGAWwc0yx3lVSOlXyRKYwUJCMkFeMHzINj6j9s
|
||||
TIlMzG1pprJ+aTPF45XhB5eA3lJenRCT7OKW1cMdcRXq6b7+D9JjXo2EWtfQtdgZltqWD/MMaYjr
|
||||
+CU9m5RO0DrySj6+HlB2yhOl4PWYb8pe193/T8euWCcjLwrNS8xtIiAxx9JLzsa4eEEEfZwL/S+3
|
||||
Gc2xOkSa6VQ5a0KTKNOlKefagQ85PrnEMQW1Kc53VVT2Ciz2L2PXq6I0vMTFAmvFgM+MZyGvRiaW
|
||||
TB6g1fLtLuum2uTWDgDssfkY6yjij6ajoqd2r3uobviJDigxLnTuiruJP3fG9f7N8njJ0HqovNsG
|
||||
e5HhMZe0lQgsKcDSuN0sWIhLNZss/YudIFUOPnN5fbc09P2k/3RlKMviihJfYaxNGb3DQDGQaWh8
|
||||
lF44IveENlu3jPiLgyJEwxBpED9+AcmIQauOqJfOPw2ut58rTxZernYJoSzCGnutf0PfUJbqScbq
|
||||
9hhu9mzuiO46Z+nqi+2OlLcMFPM24ZediDVYBynA/TIw/jeJ38Va3v5kn/0J/KN63VpJrKjoESF3
|
||||
NeHWSUmTMS+uMLOTobXqvTTyF/c2HrulkMdsCGLfpd+uY/Q1YP2VME9WZxDZD/rnk/TOHWQ6dVYR
|
||||
fheQimOZ1fT/6Tqi9AYet70UVk16LPZK9vsqOpF3xiur+xgGLjr/ndo+6bF5VRw0YyftjVuSzMNs
|
||||
AFUgG3jeQB5xO/m6DWR+WR+eS246RJqvid6YgLFaKj6MZT/or2nh6i4Lf0rMJiJd0/WCzGxl4r6l
|
||||
3I+y1RCnxokIjLAdOptfSgx8rlqb9Ujsb7OJe3CLdT2cCuhoY97iGRFxdtvbFkAtmmOILrs2VYQn
|
||||
Vm9jqYJsdGjFhdn9vB+Z9l1hr038PaPFSLSJr90aq/3aEHdjknKsah3fVIknUuFJvxPJx5xayXoT
|
||||
yqC2zC/xz5YiFpM2PfjS3O4y37uLokbqUpV1My7XqVWHNdk2Dr35nCxT9ZSVKgoC4vrlojj5nGLi
|
||||
tF43cAufD/6rA8Ntd0tnFoTL6chv+DFD+Aq+ugNCy3x7E5LBLZqGnfWxYZKisnvKJMBcXZ7+3pmn
|
||||
1SmbV1OREUCf03FBmd+6P1G4rbI/BlDCgwUJbTh9BeEX8gQZCcDiktnvyyaAkpgS+Hb8MfsM2J6o
|
||||
vk99ZSZKTEK2kci9ekr2kP771MQIXhY+ZW9GarIsdxezPWxfk196MNQOhlfvbF3wyQf0HmYhk85l
|
||||
N2kwlYOOelZZ1mJQ0/yDydFl5RwYxmmDPZEZgX5QTPOU5Gg6fh6tY4Oa11MtAjr0j9TITWI7qoN0
|
||||
1oFzni5Q6FlL8yhNCBxcIM7o3uy8DHpQCOsfMGBTrKdkHwlZptPofv6U3Ev3x4AeIkKrtF5vtdD9
|
||||
jv+GCCsItuhbpKtVceFnjMEr1xQlFlbWo5J9qBykL2tH1kne3DiAwcbV7SrYgrCUAEcjoLwYLhAf
|
||||
bhepmYNoj0cGiLWpe2RZq1CmS+d4lV2A8+zPyci8mUNmGXHX9SKojYFtIt3wBtDJlsKpxrUJ/mlT
|
||||
XQeRSdJ/V091Tdakf7LfuJX/x7vlbvAuWwoG4KA01xvVSr3TH8ZzwRp70ZmxmdAblHLv0EiTCbIX
|
||||
dpBKletdnRxAsiJm9r9m/8j44IeGdtSy0+JeVQgSJm/cqiuF4rcLITt8bUST1yWA92fPNcRTRB1J
|
||||
qiIaWvuCqmkzuXOT2rpd1rCyL/l2HxkzVkw9XsmdjuY2CRjYURFYbc6X7s2P7F+lPy/1LXYm5KH7
|
||||
kEF2O26IDEjBR/rgdm/1UMp0On8jUSeQCoNv2paXbh0BSR5Rn3+lIowB7vFCh0aoM9AFsoaxDpJ0
|
||||
8ddesFvMnefV2fW1IgTRL7eiOzzmBUZn+kVzs/JMT+qvrwW4qL97btB0gjnVFkePBKolpM/YcOYn
|
||||
UP/T2Z5yyhZAlFWMm8wH8bBLxJTkkObErEGiI/yVQP+4aGwNr2hBLc6wDnGAzma5ZGA3Ej8QY5lH
|
||||
MJKyEhpNvAhrX8RJpuqO/FSZ08J1AZ1Dt6x91qIqAcS7RFcGR18wMkqS/NKiR2OsCemrqZ4L3KVr
|
||||
e2zT8BotBKtRX7t7ykV5sLQnjdXn7PgRZAe5kfv0Y/Elhop6uOoozGaScKypi3Wx+yNrBdJM99ju
|
||||
uvUi+vXZTEl/aREHHA1ORrjubgcR6r6rnKyd9ED4d+WHzuii0DbBCFx8KF/doZFNMMtW9mCHRws3
|
||||
Ty30hPk4rqCXYS6hizRDsiUnxyJnQ7i6X25K3qLQgWvxJTiynEgQRceM5Sm/vSp2/n8f6/vFR5d4
|
||||
cYMtEQo5qlhm0P5iyNcKAfkvijnWDJTVEzwtDcdVcyr+3fbJcw4qVxJ7EvDPkJ+0b6ohnn9JCBnU
|
||||
v3N85nPtQR/Ky9myK3TYqeIkaHHKZCV2+Loc9Papo7TTEfVPrI6EclgD/p8N4ofyHaYsZgdwYQ40
|
||||
Px57GtGgjCoX57sNpb78o1ezALx7H0f5KNLFAUvSGcbgjOiBPQf/hErlDBJGGwc1wGR/x6pATFD5
|
||||
CYod+nT3XyoZfKohmWVPTdi8rZlnxI9p1SIbJOgoMEB8GN/0bGX40yW43fI+b+R3ApTOeA3aoFrP
|
||||
U7afH9Gnsd62xhlSvDGrv85vuUZi14YsaQm3X9NBqsx6Wajqt6CTEU+h/PqRWGVOWbqr97+kw4sl
|
||||
5GhpMhyF9dDtycmnK4X4EKWznMEUihAVSTO6qOVy/RBOupND2LExpyGBkVzBxmU9Bj7tVkGPLP/q
|
||||
kHXjxsaXhszVUiq/uZr6sciX/BvQ41n69lG8eZUP1Cl4dmBDCU+jcKBpVW07+8EZTmEhnjdS8riX
|
||||
PooySXi7xW2pG45rSswOoVUSehsmdzq/CFGf3eXFtSnX3JNyTpvUIAfQGtVuwtNUAy0C8A0nlY6A
|
||||
9DwRLro3x2hec9wivxLD8H39zoAwtUgY3Z5rO3d2S5jy8TPOUCM59QcvadQuU69hZAivP/Ls7Jp1
|
||||
QbiBpcDLwiFve7RlHytIxjwGIzfJup/+lidcsQrRSaXfoyMbfcM8ZhFJnJMw2iCBx9qgZBPnhwpv
|
||||
5qbCsnhBLc7cYePBoQMhoByjhWENxYo8e+5RyPq2NMkorFGHWLM/wFFBYY18x3Nqomg0iH26xGdj
|
||||
GB5utrhd7I2L5OUmAhoh30CeEnOGtzkX/DnnWND5IKhcbMWvcPwqqQhCK52P7nMZDNLyDgBzrxgX
|
||||
kWR/K0xZtw2JFUtgGskga0s2FNbXLPdQzw0f0Z2xSvzJ3/ueXF9mQIVF200g2JcFEZITPEBzfDju
|
||||
tIbiIMjy91TvQmhpms7x/4/YWa6jZKnRkTMbdZsqV+EyDfm26lu4naUEDk+pmHc7URxFbzawxCcn
|
||||
E9fh0LkHaX2ogvpNrvHw9MfDhgqD8mUL2nDAxoFN5GfK9K+H46+f0syX1p0seRVQ4nBTcgCUBjj+
|
||||
XpqvaA/+xwUSkF7wVFppdJtWp8PDXq09sD55xk/Gjl7OA9BMH8/58/r6xLalniZA++McxUHgKwzu
|
||||
YXnHJYUhJKqwB7Aw3wx16kjd2mC1YsSBzE5Cr/HN5HK4OhQ2k1oQgTrWrJJG2uXRhFoXnl7wkmA1
|
||||
9U4AomR3qoDkB5LglFSA+O5hoNpKnaQlhzt1Ai4Ihzq6DyRxNQTGqfhK1mIGzLz7y0IaA38Wf9ek
|
||||
dQ32kNviGqI77hXRm+4dekrDE0Y7NUBKMregCvY9jlHlhiyWYLSyYkzvAvFlpA1aVujBullVSr4I
|
||||
YAGnVXoQJAim3Y+VEe1ZrRWZwj3nltkYeh+1DyeoZ5vdOXVa0dB2b3zW3vsCWSpJ4qMhc4mvm/Pk
|
||||
Gx1WXKc03266MlEsRpO26C/h44H0wGb/SAnhBlmqYkmI5GtHVjEeZsMfzUMlen6wnqx/VX4IrehS
|
||||
Nw4POiQG899BmtqvIjpHQSPuhFjJ7D0ar8E32b0faOJmlv9/4oqHBvOnpsYipO37mpdeg70q6utK
|
||||
4fJDNOJ0Cv8+KTs/CF+6jVxC+AQVUIOtttfLsNXbGt7xEj65OaYUHWqtH+nPNKYxFZY8c9bkBiqQ
|
||||
fYbT7yWGaof3hAl6nFRGK5WsTLvcnk95uLmYDgBauP70++HdKaTN9VyrOWTwHB2kC8vTZbCsT4pO
|
||||
uBie89vcdk8MpEQ3XJQORLrifM/f+cxQrRUTw8fD7Gx/pEertJcCsYYEp+qxSFt4VXGFM/ku6zja
|
||||
9NlFV0dOPkCx2xTO1xHrTk/8m03Q/0bTEOv/zt+roKcyBjol5dbeMutJA8cm9oXJ6YVmiZkkXrA3
|
||||
wYSB6yjkdWAomRZCjFqNHNA0DKF0U/gNVo3EcRB0+vfzoPbF8NU9sCukhNqHtQvdjVB82ZLjSM17
|
||||
3buA4X2RYAamWJ5uvmi0nng62OXhghRYZ2JOvtCm1CXU8i0wODuPTpZwRQdjUKxWzxwSKY/prjk6
|
||||
ZvqsCcd08o4bLyQ3Fy2lMT0hwSls9F8xShftMzz7AF3XZwLBzQdc8v6CCTMP7RHpGPBrfpX4xqd/
|
||||
yi2pJGQI3uP/SVWKm3P9ieoU3LknnXt3yJv0SZqX6I5nlRmbyd6uZGxvkIQD6UsPbvtDcwCnaMCX
|
||||
asKIdM/JIn6mGvnTJW6KSO3vtNkAYKU84WW0aw+0YSwhrFg8+px7Qx9H1qvqACGeitGLFjpidHCc
|
||||
5wjOljMFbf1qwVrt4c1qCj1HK2yl5Aw/XJtO0DWx2g2EkHw8Sz4bWkKGA4v1kXa/uMbnysPWXWYe
|
||||
PlyOTaV/nX9RlOgO2vP6aRhC+n90DscwLRxG5q7TeQXa6EpUMqan+XkJr4ARKjuuMiU8at5cQLoJ
|
||||
n7w4BzG22iGG4xl7VnkBGaLvlDl8aaaQzhEtSc8adXo/m4zoKoN30firc+Wrnn0/4LQqUSG4Tg2I
|
||||
UOwQ8v+g0ljPlO6HIK1WZa2sNZMmNDe4HJbXsoKPYw6p5fKXviHkJ7NZpnbYlhyKfxTXdMdUilCI
|
||||
Wpf/NYj46DY2/mu9u9lzg8/kUYhliXy1SnBnqZY4WFLriv/MZLXjz35wiyRyLYzInBogwb+TUy2S
|
||||
u4rQKx8z40OzeR7CZnQdIUk/CaWvbeUYN37otP1H3Zi4oP6/KgaA1TistPF7Cu63EtYhM6cYm076
|
||||
NaQ78/nXEpoU2bL9MDhlCT9Y3pdkwZ6r1hMPTNHoO1c4EAqfaoS4ShQVbBBUe81Dd++0qlMgobou
|
||||
ClD7SAOQMJkCCzUo7G2qYDl12x4bd11VSdw//QH/xZxo2/2wj4s0ZlNfxbJKioTwqCjD9E5LTNhX
|
||||
GtVmppwv/7MqqMGex8JxYxpJwVKrH311egzfA3zWv/1mUkP6ik9EnmccFyBA9EY5G9DLhzscPmbE
|
||||
8v14PrXL7LsNFbS/FmYyCBqi0A8ueA2zgKvKvjyzw0KfW4cz2KyD37PZrebqvZjXe38FMhWyqGs8
|
||||
gZT1DCg8vouze5LaMnJ3Qo3mn2WJG92VbGQmOxEst86asai02J89w+2Cmkyqba4HQhPBhI4IrTaH
|
||||
bup+HvZKQkTmZJ+xJe3iga5HNUevB8hDFeqtAyyOERq6xvUQjkWQE86PjgYdYxykE+EgIgSDhpmG
|
||||
v/A/ctygZHRRwLtWMeUrBImFFjsjqleXsjP+WdirjuG+Juqk8Z+Ja8vvJ/DgFuQQb9xuir8JaH+3
|
||||
laW4yXLIKbeRYjWPTBwLpEjDk4MckyZyXpin2LNMsTe/Kmysrr2o4MjuVsJCeKvUsvKNIzuSyzDZ
|
||||
zjkfVmBfu/uehwN0V81NO/OpCKIoMcLONm/BQri3y3LFQfHR05bte1twyuqwMzIkO8tN7uYSy44X
|
||||
tMAPcZIerdgCV1zOeEHCarCz2M2pzQwQpNlzUzhd92TGd9ZOq2015r3ig/iGeHhwXV3wT3lp0qcM
|
||||
MTh/c8MAzzzgT0uXI0dl2vZt2lsWEXICa/kqdwewc+HonmJLfQGdqQsMe8SSBOOaw3Ci0hpVi7xE
|
||||
lSNX1AfR0N3Uffa2mmGT+7JLwWYd7ltQRpTsL57wRGBU5RRgtpzrRcfFMly4PCcX18gokme0zM1m
|
||||
leraUNwqxt79AysZHF0ney5jh1U+EuiehAPD2zLqYeoakWoRelzWkDuovkXkypDrCXd54DZKjfEH
|
||||
qBKro0HVrMUC40grApHCEDi00iByJOybyZdxFyo2V9ipj+8e6JGtj14b3X3shTU7qGStF8SgSKmm
|
||||
xqpcXm0dbquWrkYeRIBkhI10MMiAUCI4G2xjRW+4+uPVl68uOthyYeg3cHywienaTPJrmWfZKrpU
|
||||
TeutVZFoJ+RjC7EZxTYjt99eSL04DUa77cTWX1oj71PYQr+8LMir5lIeeZYNX+0/uUhun3/jPK4e
|
||||
WzASh083TXvCdA4Izjglvem2D86m4uvc+tzWqqfiD/1yw2f0FZw1Y0nQ15rgmEIYvFeT8lhhMxms
|
||||
8qIFVZxNgMQ+Qe+CxPqvlOq/1j8v0YLYhi13ISwH5J8fTZQRiieIpI5hVmVkzR+1RxhOBL4bqj1V
|
||||
2gcTlP26xmFS57JcB0eertCDuBoI7ySub7Qur28c6RM26h2hWsIb93dBkjS1yvFuhsPSo6uzmP1r
|
||||
OGLsMR06MyNixner/Hblc1qYzirRdVpRgQyrQf9xwnB2duAkK/kZpaWa3r2nGaxjBbDXc39dqLpA
|
||||
ha/XsVUD23c3wstK3iKD+pfw++Qu0VcEli6DnH3b6Ognko/gX/knL+thgQGGKq+MbPtiv9CtyU/i
|
||||
XMFY7U5Fwhxt9ewTRzd+pskDrFsNKTDVhtBaywO6SoF9J78XkiWGoW3pAK/4XhxjJS4mS5+CgJdj
|
||||
5TOoDXnyUk1kuMxpd/BD8xX0DLNeEyTXdVPb/pJG5WTEzQgOAmACXva9lre2o6+nXQ8/kcVMGwwB
|
||||
ytmOvyM2aYpS3NmXPbzD0tfzcCH8l/5G/50y61Va/SDcnIvrxft5kZOiW6INe/3XLg6QPCtUP7Ps
|
||||
tcZwi3z82+5B3OgL4/wB6cfp/sJvfuk3k3J7vs0QR7ZZKiey95XHlY9wdIPTVG/3I1psMwR481XX
|
||||
mvHG4ZERv19HFU+MTNs5HAXJOm7k42C/fhgQhaNBMloNMacx1BHUvWM6UfMI+4HnjJ9VGmu51J4g
|
||||
gf3KdEvM6ZOZq7dd0Yl0MQOySk0othvJW7Tk4LozZ7BukbA0+JZRynNV9v947kJo0bh8Pdemw3bC
|
||||
PXZqYzONjHGLlZzRAZ8+utGxeq8dmBJlfrcWoPj7C065JMB0ffdi9H5GpgScwsI8dDaaLdjK7Zw8
|
||||
R12UzJQTYapv57MUhmyGxiMbGNDW6It2A8WQAxF/PdkttsLkThGzIKamb3iHEG1+EN9kGBMUo4Yq
|
||||
L3uZ02J/bq/AQfwNL3sEQNlxNpui1/mn1I1v6kDbEMuXXqZTUggt/RWuwOj78LwfenDwvtc1dcVZ
|
||||
q7531X5ZuslcalyXcLQv80E3aj3EiQuFeRgPRvtgohPFUIw2RI7N5qcMD4QIkJ9AEz56TAuiDB1k
|
||||
qMO6jxgVxJw0f6qqKOnkvbL4pLAVrpUZHKKS+vmRmQlZMwGoIV3Qg9g0S1BLSKO85xAEgT4O0i+h
|
||||
CyVSzihoQlKu4MkAoIqnkPt3wMoSuOshiu7iSVQjNjiMAD84R8XuQskCVqLFONdkULZNsLQ9J9Pe
|
||||
g2nPEvHWZAm8O1bTroNgWjgrUWfWfOg9QJiy7M39NHeqc1xhmijg49U672q+9rE8VEoUoBgwMFi0
|
||||
FfXQ+DOxtsNzvgTBSFwIm0uBQb0tzUD6WHsqnZ2R2l2wj4qDxa1MJTrUIQKxd2NoWE4krrG3pk63
|
||||
XQ0u30/qzxXFLFv8tHxbmWj96PxvAiNzafIiXl+8NDGvI8Lw5ANMYCsPDix9qGewipA591Ap92PQ
|
||||
fFiBQ0HRtTz81D+nsN2S7FluddFYSvSp/zr/9eRDaUaOjN6NXpx3o3kobEId+cyCQLwE6bHOYgFk
|
||||
D97vTH2giKHQykACs+m+h66XJGRKSIR1RsT8lVsCNDf5NgCn/HSyc67VBlwLGiDeRUR+PJbsm7W9
|
||||
QrMaV5GW7U26SeO5v22McQQi/q7v4ucclcKKmwC94EIKYMf7Z3y+oPXsYAOLfHZrGAz5BS70fFpK
|
||||
o6TS4nahJzaFt3JqR+QmSzEEd958Wl75aj+o/XypHdcNKAdU/Fux733B/vDJ4DKmZPurhMpNWBeL
|
||||
0tIHlTMov+9t1tG6S7ryQUf/r2Q9bGs4avXAJU3+eZ3oShWVNbo5wXt2ONukJD91Zd3/e4UgXmLu
|
||||
qOalQc25vt88BdJW4sla72L1YojvenJAnmd+VvwPmvyrTNpsWX4Jsau0RKdMIo9AgJHMq/33Lh14
|
||||
e5x7rbSdxiFdKVTC49DKodjYxlO+lkTWKVYIFEb/XBVOUV0slfodmpR/i4fo762RQuUJfn4IpHrB
|
||||
5+GvlBbcz23dJOTOo+UhseMtWuWU9Pn8a0yeOJ9dWtDrkRkyedFOj7naFxa5nWEVrm3RiYI/LEFb
|
||||
Q1nxtp/73latiyxZOAiEx/mQDjniDdJjKFypvskbLUPTZxjRouowKqX+zAI28q4LeDZZ5mJPj3H1
|
||||
W14fbFVfgAgK7t+5N/afWnIJSU1YTLyGOBYV9IDFfYrHq2VEaWbkn4B5WhxOiIieim3COtrlDgZQ
|
||||
P3Dnelzm1Q/pETw6kwJkcrq8ID7f/MkzS+T3p63yHGiuugcltAa4QjTzSB51vA+B2zQHxy51WTLq
|
||||
OJ5lfW52CvNhdSdKYBQrrfx1t65HPMsUw6YDaGNCFNUJT2O6miLZPkF8GyFyP3LNZZcDXFVmgPze
|
||||
+Ca/v3cx+ahCzj4MZnPIsPl2WxZo9XlCk1eymKTk7erl+1MGUeA+B7V/+Fwb/6LRogF5EmCCct9K
|
||||
7lsNKyZfhaIRwkxMrVKijYNa5GBBI6AMqUjJqXrb07xHUQ81GJZzTrVIe9SsbVuEmPBKS4wM00rB
|
||||
dtm82FHe5QglOPOmYk3usKoOYR1pJr/n0TGVYYsituiuJtJKnUJMxsKLiPZ+eRizDamOSeuhX760
|
||||
/P+OWBnhX08sveuWR6ItKdMFRjZ2pXHncy3V0noy6+VrR7/cLJArYg6RgTIOZ/sYBxjdcnTwME2b
|
||||
GDylEgal7fJKwJ6YeYq7p3E/yM2hefMfpgvq6JvSYCl6dWqhS13Se+UO9yS5R0JOwnOjPpTZ/bAO
|
||||
OKWjqhCYajToP3sF7wNYrWgTCvymqNF32ji4t1MUB8fpfbMYdh+YnW84HZt6ier5PrKIPyD9z+zn
|
||||
ExWEQ/HoeOqkmCDsF7RojH+GgR9uY0MEXvzKcuHUfszt0I1DbB+Zy4QaI7g3eA/s8yKhvq21O2Wf
|
||||
ZS0J24NcJt9CXlCJt9vhizSZtlaGOlVBi54DgXrAU0EWzL9bxQiHx+9y4XzFC9srWqCCxvUgW5W2
|
||||
cSG4/oGCEnqM9bYiHO8lmiPU5xSzcLnAohMRgsMLqzrkVpcjn+GJc1Ksqc8R6A14X+EI6zCqsKEo
|
||||
RD1yBWKYrfW5SUZh4nwxwo311nB3wJPzeu57oAkD/Qkt9/6uVAMeqKOkthOXT0mHr4BmfU1ahyia
|
||||
Nsuzz46OP8tY7l1Ng+axvwrEkHh0VYhNq0jIZ37jlQPn8NOIn0Wp8Z6OwNMcgB0DK0nq2QHNg4wI
|
||||
bya8B8TqKOhdyNRAgLuwkbAo7dofKcUCe8acmyuIWHB01qSR+qP/qk8wIk2A5UqyjXVTfg2EYVet
|
||||
paWZfmRlKkm010lJMQj4rIaL340S6yoOTvtNtbkZCksN/Ix6dVcJiu4TLi6J3BcI/rrN5AV3rLY8
|
||||
+yE4p8+pRnt8R+A9n72WIushK7UFcJ4Ssnu0G4TnAqKnTm6dkbOOr5gMDjNvdoDFouSqUzPdoyql
|
||||
+VejqPb1WCGl1H8mZAHoHR/fZ83NLpdplXvI1tbXTy1vSqlDgQ3OW0nM4av40/seAb3vi+XagkFj
|
||||
MaL8b2rqRVJFSLxn7mBhGuV2cfMFjvaSp+5ttJ08f/PkDK/9E6UE9ce6MHHtB68ZGdSW3I2lakNE
|
||||
55PHiuHnFXzH+s31XsDZm+cC/Oorudi6lmuCWIL6qT0kP+BAteedRwN8jH7904qAuDvXM4Uahj+J
|
||||
edJDR+D9Wb0dpa3RSjhAoRFgfa5WfFacu4gLiQRYIeQkzGnHbn4BMgN0mrJooV7WJYXlI5qcMcMT
|
||||
q1BcvD2EKKHlvi8J0v5v+i6ftJSbric42rKkj7lxRd0ThvYHhSBdaRsPhpXxXMgfN+QC2RGK2wPx
|
||||
d8DC0DFWA4RzcgRIeGGL6qmCI63pf9zJSEh9AbfX5IjOjW1/MxG6lrc4buyiLxL6A/GrMnXT81Zk
|
||||
a9c2jFYX5kUZw2/W8hjk+yXGsAjaEfvVRi0FaDaRwdKHX+luTvd0tfMAQXOHVwDwkwIAzbKPemLT
|
||||
/pL34v1Wch3U5agrGPCqsrDFFZb4QRsQAeGt+qjabE/rVxrk2uxUvI8kHC87dHRrNz6PqEbNjB6p
|
||||
SN/URfFTNImjv5MQ6NyoAg9cSnlvYL3/R9+IFo+IfHfCXKz8+e/uqne7bxS0YzaqIz548oxGjqFz
|
||||
/dqWQhiO9MWB31PzsG3wDjMObi+VbM8kWMmQsbg8gNGsfqme1USmb3Za55tb9g+NCVNLxbZWfUFp
|
||||
WIutZNJ2op4StwbWtxLdgHbMehXe3Dw65yXAz1iV5F0Y+eEVXqLHrr+DzUGZgSvRZ6HxOzOFrw8R
|
||||
xp/wp7QfPu6Cgw38por8Ii/1p0Ba91pP545K5Tz8jd7EYGihLcdNR0rT8VucAygiZdx981AcZhbS
|
||||
tQ0Q4ldjePLfDqbu0RyWZRcsvDQHrkvRHL7XZkyb0LXwMUw2t83WYjbDGrk3qasQD14GSr16O14i
|
||||
Yhjt5DKbULWeVloGNiUKn8Jr6hoe2LEKt33AWo91lD7XSubpYe+vQNghRJ4OT1Mdptqa6uHLSlcE
|
||||
7tLvxSfnOTTwNstEVvm120zDhs1jgSE8SPvJF137jxjYZUU23iz0gDYqWPJumH7Z6Y3S43ZNiGhU
|
||||
7DUnWaHjypIcYqwlr9vipJ9f7YLjlC1yVhqkCI6Oh1dsNi0ygSJEOrsgmFOtaSmChF/+Ddsr+x3q
|
||||
JFbj0wcyD9MNMelltQuwsSor1FTFGO4Qhf7JmdqyibIZW4MRt0Q23Je7X7QOteyxaIdT/xgHLzzX
|
||||
0atz5OJ17aTfAuaSngbb76pGbev7gcByN1MfpWId9HixXVgH74BlivVDsQvyhjq/WeMHluZcepsA
|
||||
NUMp59X9QifcqUMtOJcV1fEOW2TDSkRg+JzJmv7TQaRugQs6Zi15Hqq38fjobpCapaNgrB8rzSkf
|
||||
Nzdd3ISrZwe8/WRFIQ1ZFlW7HWB+rRXY28INKWYRlLzmU9medgLWHiYotQojRKa17U2DQQ5Cnl5G
|
||||
pL4Q9JSqyRaE24Gw1i2MuumD2yDWU/iqCD1nz8eJsbcyQe8OUsSCAipW8gciEZcN4yoEprvaKagj
|
||||
0RPdCAAz3J9NlnWCpiwB26xAsE+d2GVbVEHASHZyt/rUlBOOBmfsMJ4K/cXJWq3Wgexn0SFbTBf3
|
||||
mhI1kTzGXxCHLlIOnm3V9f6Lal0GpzyC4mtJP4/pBcDT3lfCjS8nbRh55geBwBuAem9aNTCvPMx9
|
||||
HrorVvA6xlMsBSdtoQvi27zswhMIfILS2MRbnBuoKpC4LvFPROXfY4vowU4MjA/VySHj1Hj5KX65
|
||||
zJZIzYv1AVoFgguUngFJts6D8FjMkZPocSuh8IQjixFV39lcCsP2zD+F4gYrqScUFGVqbKI/WVXD
|
||||
aeuKiBHPzA4c7UxuYk+eXDrL8NSmR0D/1JzsNA43CrltBi6t1iOjn6NNLmHUfdxXV6yVVeOEI38R
|
||||
4iTUm/bHab8MJzhgvODamPOE9RLjLR2cbMXGHwC75IqaqGkAClY3GO8zv3kSvW0QMyd9Ep6pgcdW
|
||||
SSYVlWAVoZhf2Xyirk6G3lDPyHnUktJcFoHIUhiC1mGAs1FPHuGj18ItNZDCkM7yMtUBhMWDyaYx
|
||||
t8XJUzfKO9+ubwBId8Jq5X80AFh+5rhnevdNeEBs8+dAyi4BhAeDXCJQVx/idq6eUzrR3ty+docM
|
||||
7suC30YPfK1zCogdU7xBoCGiiInCuQ6KDqXpWHHHZPhpSt8ykSIWEwE94Ksf7BHfbjxWhnjChWkh
|
||||
pngTo9gcf5f6XVzNod23Gl2yjOxd2+vTO5BfCoJwEVZA1gOLBfXLrCHdY8FYzNTLnKPb6xarMYeC
|
||||
uq99ZlCL/N1bkupQrBFzo9QVvNsVEbQOG05i50P9lT/1ZijfMhSqUoz52nKnJt6eiwxoag0m7N5a
|
||||
t+c4CAJFQJEwJWgEr5ZD8nZ7c02/iSAmOE7hGAAILVd5qWokQfkOZxHhUoaIPtDoTye7SRK0ykBq
|
||||
PN7fjsrIQFkxwhxOr9KRJwenFNb2xZOB3aKB8zEGyMJ7qKFV4sfyIXim5oOLGQNGXFMjcjEKCGiE
|
||||
/N7+9cWshmS1muSvxAEXbqRU1uHMszi19n8aCOoaG9wxxPhyIsTMyFdVDPWLDq98WZSlzJOeSXh0
|
||||
ErMVbNKicY37nMotDHWBT81O3EhTbjEuFgwvGRsCrEEyZnvf6c0uK9S28glRYxvPx2UOg9FBNe9B
|
||||
RsFedR6CiFSr+7DFXjglGztpe9wuuQlS/RYxLcjN7AcbvDTgk6Wf2/Xj440txtj79eTWvhSx01vj
|
||||
0HUsuBRSVmFNMyTzHRUEc9TihHMzkfPcsbaaBBV1W2TroM9sSzpM5dCgKJ9kFxFxiInPShuiMFzU
|
||||
BusnTFj3irHB53mh+oTAlZXzeOZgoaythvBEzdmwGCK1H03lgltWCqw115f9q4KFi0nd1Qv6mqo7
|
||||
+GL/YwY7KCPomFXh87vWGUYbWyyGlwlG73e20bXs3E3iCGdZfhgNDAKeZJVHkqEKbcMd+faQ6Z7o
|
||||
8zgdlWul5f1o1AmuzVYSjVJQzV5tPfH8TIbCwfb0dkgYgThLk26meQweU5RpRhx67I9v2jdNE3ff
|
||||
Ebqc6CAF/1ItmoNEKXWN36Z/xDSlXV1fu4Pz2Pq7C7HB7LEZtmvMTbOFC2vOuyO6DAl/aTA7D3aW
|
||||
NxaYWWI+Pdp1t54aadWPv1fYTE0cydJMrcOmxpU9agDTbC8OxXbSX7GVvg4NUuyXJB8ZoLUI4pGw
|
||||
BiuKUhAgtpyczOIHiLybxLg81LTI3KefMkJ+y4AV1zm7Owz6ouqZ8Gatmpc3+UeYyjlIyZ7ZflHt
|
||||
CNjHx5pKufSCCFuYKCwzTqN4NfcY6fYM0rmdunYGd/PchaFK5o6qwiK7yboJv4K8Y21s5Ni2LmGQ
|
||||
qKYEvar6pNuemQ5NRYH2ahvgqsY0ikDweU2SGusfQXuWEJHqD4evRs5vpC5idr2mDxDSwhM/61SP
|
||||
QztsBt14ZqvqDk6IH+VrqRf11a3MGDwRpg89m7S0js52Ot9nrt+WUsr0wdDfia2g3V+xYeoybXyK
|
||||
j7/XfbffrYSelPUJHJLEX2Z3czu9rXO/aQ2pm2rVgG6zGRA8+MLtZk2MSQsOKCXFbWkBz/s5NiXe
|
||||
54LL27huT01nasvfvWV4VSgjD5OwHFVHH+IYl0q1IDm5lRRturrnGotw2afxgQOXo5qMjm6P1sGM
|
||||
KbHybLf+puGCFh86aSHDOzDPaX3IyrAe70msFMG8nk5nMB8JhBnxvbYT02fHSAjjoLesJkeC1Bmg
|
||||
pVX5m2/5jKiHogdJ/vzCvCTKAhIJVjpJo/p3kp5WcQtpn4iY/OGNXGpJdqrfEnuLsQzQUH0Okizv
|
||||
KnmRsadIXQ==
|
||||
`protect end_protected
|
||||
+2392
File diff suppressed because it is too large
Load Diff
+4522
File diff suppressed because it is too large
Load Diff
+10519
File diff suppressed because it is too large
Load Diff
+8192
File diff suppressed because it is too large
Load Diff
+20
@@ -0,0 +1,20 @@
|
||||
Radix=10;
|
||||
Coefficient_Width=16;
|
||||
CoefData=
|
||||
3
|
||||
19
|
||||
97
|
||||
366
|
||||
1052
|
||||
2321
|
||||
3999
|
||||
5485
|
||||
6082
|
||||
5485
|
||||
3999
|
||||
2321
|
||||
1052
|
||||
366
|
||||
97
|
||||
19
|
||||
3
|
||||
+20
@@ -0,0 +1,20 @@
|
||||
00000003 0 0 0 0 0 0
|
||||
00000013 0 0 0 0 1 0
|
||||
00000061 0 0 0 0 2 0
|
||||
0000016e 0 0 0 0 3 0
|
||||
0000041c 0 1 0 0 4 0
|
||||
00000911 0 1 0 0 5 0
|
||||
00000f9f 0 1 0 0 6 0
|
||||
0000156d 0 1 0 0 7 0
|
||||
000017c2 0 2 0 0 8 0
|
||||
0000156d 0 2 0 0 9 0
|
||||
00000f9f 0 2 0 0 10 0
|
||||
00000911 0 2 0 0 11 0
|
||||
0000041c 0 3 0 0 12 0
|
||||
0000016e 0 3 0 0 13 0
|
||||
00000061 0 3 0 0 14 0
|
||||
00000013 0 3 0 0 15 0
|
||||
00000003 0 4 0 0 16 0
|
||||
00000000 0 4 0 0 17 0
|
||||
00000000 0 4 0 0 18 0
|
||||
00000000 0 4 0 0 19 0
|
||||
+160
@@ -0,0 +1,160 @@
|
||||
00000000 0 0 0 0 0 0
|
||||
00000000 0 0 0 0 1 0
|
||||
00000001 0 0 0 0 2 0
|
||||
00000001 0 0 0 0 3 0
|
||||
00000001 0 0 0 0 4 0
|
||||
00000001 0 0 0 0 5 0
|
||||
00000002 0 0 0 0 6 0
|
||||
00000002 0 0 0 0 7 0
|
||||
00000002 0 0 0 0 8 0
|
||||
00000003 0 0 0 0 9 0
|
||||
00000004 0 0 0 0 10 0
|
||||
00000005 0 0 0 0 11 0
|
||||
00000006 0 0 0 0 12 0
|
||||
00000007 0 0 0 0 13 0
|
||||
00000008 0 0 0 0 14 0
|
||||
0000000a 0 0 0 0 15 0
|
||||
0000000c 0 0 0 0 16 0
|
||||
0000000e 0 0 0 0 17 0
|
||||
00000011 0 0 0 0 18 0
|
||||
00000015 0 0 0 0 19 0
|
||||
00000018 0 0 0 0 20 0
|
||||
0000001d 0 0 0 0 21 0
|
||||
00000022 0 0 0 0 22 0
|
||||
00000027 0 0 0 0 23 0
|
||||
0000002e 0 0 0 0 24 0
|
||||
00000035 0 0 0 0 25 0
|
||||
0000003d 0 0 0 0 26 0
|
||||
00000046 0 0 0 0 27 0
|
||||
00000050 0 0 0 0 28 0
|
||||
0000005b 0 0 0 0 29 0
|
||||
00000068 0 0 0 0 30 0
|
||||
00000075 0 0 0 0 31 0
|
||||
00000084 0 1 0 0 32 0
|
||||
00000093 0 1 0 0 33 0
|
||||
000000a4 0 1 0 0 34 0
|
||||
000000b6 0 1 0 0 35 0
|
||||
000000ca 0 1 0 0 36 0
|
||||
000000de 0 1 0 0 37 0
|
||||
000000f4 0 1 0 0 38 0
|
||||
0000010b 0 1 0 0 39 0
|
||||
00000122 0 1 0 0 40 0
|
||||
0000013b 0 1 0 0 41 0
|
||||
00000154 0 1 0 0 42 0
|
||||
0000016e 0 1 0 0 43 0
|
||||
00000188 0 1 0 0 44 0
|
||||
000001a3 0 1 0 0 45 0
|
||||
000001be 0 1 0 0 46 0
|
||||
000001d9 0 1 0 0 47 0
|
||||
000001f4 0 1 0 0 48 0
|
||||
0000020e 0 1 0 0 49 0
|
||||
00000228 0 1 0 0 50 0
|
||||
00000241 0 1 0 0 51 0
|
||||
0000025a 0 1 0 0 52 0
|
||||
00000271 0 1 0 0 53 0
|
||||
00000287 0 1 0 0 54 0
|
||||
0000029b 0 1 0 0 55 0
|
||||
000002ae 0 1 0 0 56 0
|
||||
000002be 0 1 0 0 57 0
|
||||
000002cd 0 1 0 0 58 0
|
||||
000002da 0 1 0 0 59 0
|
||||
000002e5 0 1 0 0 60 0
|
||||
000002ed 0 1 0 0 61 0
|
||||
000002f3 0 1 0 0 62 0
|
||||
000002f7 0 1 0 0 63 0
|
||||
000002f8 0 2 0 0 64 0
|
||||
000002f7 0 2 0 0 65 0
|
||||
000002f3 0 2 0 0 66 0
|
||||
000002ed 0 2 0 0 67 0
|
||||
000002e5 0 2 0 0 68 0
|
||||
000002da 0 2 0 0 69 0
|
||||
000002cd 0 2 0 0 70 0
|
||||
000002be 0 2 0 0 71 0
|
||||
000002ae 0 2 0 0 72 0
|
||||
0000029b 0 2 0 0 73 0
|
||||
00000287 0 2 0 0 74 0
|
||||
00000271 0 2 0 0 75 0
|
||||
0000025a 0 2 0 0 76 0
|
||||
00000241 0 2 0 0 77 0
|
||||
00000228 0 2 0 0 78 0
|
||||
0000020e 0 2 0 0 79 0
|
||||
000001f4 0 2 0 0 80 0
|
||||
000001d9 0 2 0 0 81 0
|
||||
000001be 0 2 0 0 82 0
|
||||
000001a3 0 2 0 0 83 0
|
||||
00000188 0 2 0 0 84 0
|
||||
0000016e 0 2 0 0 85 0
|
||||
00000154 0 2 0 0 86 0
|
||||
0000013b 0 2 0 0 87 0
|
||||
00000122 0 2 0 0 88 0
|
||||
0000010b 0 2 0 0 89 0
|
||||
000000f4 0 2 0 0 90 0
|
||||
000000de 0 2 0 0 91 0
|
||||
000000ca 0 2 0 0 92 0
|
||||
000000b6 0 2 0 0 93 0
|
||||
000000a4 0 2 0 0 94 0
|
||||
00000093 0 2 0 0 95 0
|
||||
00000084 0 3 0 0 96 0
|
||||
00000075 0 3 0 0 97 0
|
||||
00000068 0 3 0 0 98 0
|
||||
0000005b 0 3 0 0 99 0
|
||||
00000050 0 3 0 0 100 0
|
||||
00000046 0 3 0 0 101 0
|
||||
0000003d 0 3 0 0 102 0
|
||||
00000035 0 3 0 0 103 0
|
||||
0000002e 0 3 0 0 104 0
|
||||
00000027 0 3 0 0 105 0
|
||||
00000022 0 3 0 0 106 0
|
||||
0000001d 0 3 0 0 107 0
|
||||
00000018 0 3 0 0 108 0
|
||||
00000015 0 3 0 0 109 0
|
||||
00000011 0 3 0 0 110 0
|
||||
0000000e 0 3 0 0 111 0
|
||||
0000000c 0 3 0 0 112 0
|
||||
0000000a 0 3 0 0 113 0
|
||||
00000008 0 3 0 0 114 0
|
||||
00000007 0 3 0 0 115 0
|
||||
00000006 0 3 0 0 116 0
|
||||
00000005 0 3 0 0 117 0
|
||||
00000004 0 3 0 0 118 0
|
||||
00000003 0 3 0 0 119 0
|
||||
00000002 0 3 0 0 120 0
|
||||
00000002 0 3 0 0 121 0
|
||||
00000002 0 3 0 0 122 0
|
||||
00000001 0 3 0 0 123 0
|
||||
00000001 0 3 0 0 124 0
|
||||
00000001 0 3 0 0 125 0
|
||||
00000001 0 3 0 0 126 0
|
||||
00000000 0 3 0 0 127 0
|
||||
00000000 0 4 0 0 128 0
|
||||
00000000 0 4 0 0 129 0
|
||||
00000000 0 4 0 0 130 0
|
||||
00000000 0 4 0 0 131 0
|
||||
00000000 0 4 0 0 132 0
|
||||
00000000 0 4 0 0 133 0
|
||||
00000000 0 4 0 0 134 0
|
||||
00000000 0 4 0 0 135 0
|
||||
00000000 0 4 0 0 136 0
|
||||
00000000 0 4 0 0 137 0
|
||||
00000000 0 4 0 0 138 0
|
||||
00000000 0 4 0 0 139 0
|
||||
00000000 0 4 0 0 140 0
|
||||
00000000 0 4 0 0 141 0
|
||||
00000000 0 4 0 0 142 0
|
||||
00000000 0 4 0 0 143 0
|
||||
00000000 0 4 0 0 144 0
|
||||
00000000 0 4 0 0 145 0
|
||||
00000000 0 4 0 0 146 0
|
||||
00000000 0 4 0 0 147 0
|
||||
00000000 0 4 0 0 148 0
|
||||
00000000 0 4 0 0 149 0
|
||||
00000000 0 4 0 0 150 0
|
||||
00000000 0 4 0 0 151 0
|
||||
00000000 0 4 0 0 152 0
|
||||
00000000 0 4 0 0 153 0
|
||||
00000000 0 4 0 0 154 0
|
||||
00000000 0 4 0 0 155 0
|
||||
00000000 0 4 0 0 156 0
|
||||
00000000 0 4 0 0 157 0
|
||||
00000000 0 4 0 0 158 0
|
||||
00000000 0 4 0 0 159 0
|
||||
+132
@@ -0,0 +1,132 @@
|
||||
Radix=10;
|
||||
Coefficient_Width=16;
|
||||
CoefData=
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
2
|
||||
2
|
||||
2
|
||||
3
|
||||
4
|
||||
5
|
||||
6
|
||||
7
|
||||
8
|
||||
10
|
||||
12
|
||||
14
|
||||
17
|
||||
21
|
||||
24
|
||||
29
|
||||
34
|
||||
39
|
||||
46
|
||||
53
|
||||
61
|
||||
70
|
||||
80
|
||||
91
|
||||
104
|
||||
117
|
||||
132
|
||||
147
|
||||
164
|
||||
182
|
||||
202
|
||||
222
|
||||
244
|
||||
267
|
||||
290
|
||||
315
|
||||
340
|
||||
366
|
||||
392
|
||||
419
|
||||
446
|
||||
473
|
||||
500
|
||||
526
|
||||
552
|
||||
577
|
||||
602
|
||||
625
|
||||
647
|
||||
667
|
||||
686
|
||||
702
|
||||
717
|
||||
730
|
||||
741
|
||||
749
|
||||
755
|
||||
759
|
||||
760
|
||||
759
|
||||
755
|
||||
749
|
||||
741
|
||||
730
|
||||
717
|
||||
702
|
||||
686
|
||||
667
|
||||
647
|
||||
625
|
||||
602
|
||||
577
|
||||
552
|
||||
526
|
||||
500
|
||||
473
|
||||
446
|
||||
419
|
||||
392
|
||||
366
|
||||
340
|
||||
315
|
||||
290
|
||||
267
|
||||
244
|
||||
222
|
||||
202
|
||||
182
|
||||
164
|
||||
147
|
||||
132
|
||||
117
|
||||
104
|
||||
91
|
||||
80
|
||||
70
|
||||
61
|
||||
53
|
||||
46
|
||||
39
|
||||
34
|
||||
29
|
||||
24
|
||||
21
|
||||
17
|
||||
14
|
||||
12
|
||||
10
|
||||
8
|
||||
7
|
||||
6
|
||||
5
|
||||
4
|
||||
3
|
||||
2
|
||||
2
|
||||
2
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
+8194
File diff suppressed because it is too large
Load Diff
+2051
File diff suppressed because it is too large
Load Diff
+2048
File diff suppressed because it is too large
Load Diff
+83
@@ -0,0 +1,83 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required
|
||||
# to simulate the design for a simulator, the directory structure
|
||||
# and the generated exported files.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. Simulate Design
|
||||
|
||||
To simulate design, cd to the simulator directory and execute the script.
|
||||
|
||||
For example:-
|
||||
|
||||
% cd questa
|
||||
% ./top.sh
|
||||
|
||||
The export simulation flow requires the Xilinx pre-compiled simulation library
|
||||
components for the target simulator. These components are referred using the
|
||||
'-lib_map_path' switch. If this switch is specified, then the export simulation
|
||||
will automatically set this library path in the generated script and update,
|
||||
copy the simulator setup file(s) in the exported directory.
|
||||
|
||||
If '-lib_map_path' is not specified, then the pre-compiled simulation library
|
||||
information will not be included in the exported scripts and that may cause
|
||||
simulation errors when running this script. Alternatively, you can provide the
|
||||
library information using this switch while executing the generated script.
|
||||
|
||||
For example:-
|
||||
|
||||
% ./top.sh -lib_map_path /design/questa/clibs
|
||||
|
||||
Please refer to the generated script header 'Prerequisite' section for more details.
|
||||
|
||||
2. Directory Structure
|
||||
|
||||
By default, if the -directory switch is not specified, export_simulation will
|
||||
create the following directory structure:-
|
||||
|
||||
<current_working_directory>/export_sim/<simulator>
|
||||
|
||||
For example, if the current working directory is /tmp/test, export_simulation
|
||||
will create the following directory path:-
|
||||
|
||||
/tmp/test/export_sim/questa
|
||||
|
||||
If -directory switch is specified, export_simulation will create a simulator
|
||||
sub-directory under the specified directory path.
|
||||
|
||||
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
|
||||
command will create the following directory:-
|
||||
|
||||
/tmp/test/my_test_area/func_sim/questa
|
||||
|
||||
By default, if -simulator is not specified, export_simulation will create a
|
||||
simulator sub-directory for each simulator and export the files for each simulator
|
||||
in this sub-directory respectively.
|
||||
|
||||
IMPORTANT: Please note that the simulation library path must be specified manually
|
||||
in the generated script for the respective simulator. Please refer to the generated
|
||||
script header 'Prerequisite' section for more details.
|
||||
|
||||
3. Exported script and files
|
||||
|
||||
Export simulation will create the driver shell script, setup files and copy the
|
||||
design sources in the output directory path.
|
||||
|
||||
By default, when the -script_name switch is not specified, export_simulation will
|
||||
create the following script name:-
|
||||
|
||||
<simulation_top>.sh (Unix)
|
||||
When exporting the files for an IP using the -of_objects switch, export_simulation
|
||||
will create the following script name:-
|
||||
|
||||
<ip-name>.sh (Unix)
|
||||
Export simulation will create the setup files for the target simulator specified
|
||||
with the -simulator switch.
|
||||
|
||||
For example, if the target simulator is "ies", export_simulation will create the
|
||||
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
|
||||
file.
|
||||
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Apr 06 12:05:38 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ad9361_clk_gen.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ad9361_clk_gen.sh' script.
|
||||
|
||||
./ad9361_clk_gen.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ad9361_clk_gen.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ad9361_clk_gen.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+152
@@ -0,0 +1,152 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ad9361_clk_gen.sh
|
||||
# Simulator : Aldec Active-HDL Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Apr 06 12:05:38 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ad9361_clk_gen.sh [-help]
|
||||
# usage: ad9361_clk_gen.sh [-lib_map_path]
|
||||
# usage: ad9361_clk_gen.sh [-noclean_files]
|
||||
# usage: ad9361_clk_gen.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ad9361_clk_gen.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "ad9361_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
map_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
map_setup_file $2
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ad9361_clk_gen.sh [-help]\n\
|
||||
Usage: ad9361_clk_gen.sh [-lib_map_path]\n\
|
||||
Usage: ad9361_clk_gen.sh [-reset_run]\n\
|
||||
Usage: ad9361_clk_gen.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
vlib work
|
||||
vlib activehdl
|
||||
|
||||
vlib activehdl/xil_defaultlib
|
||||
vlib activehdl/xpm
|
||||
|
||||
vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
vmap xpm activehdl/xpm
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" \
|
||||
"../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v" \
|
||||
"../../../ip/ad9361_clk_gen/ad9361_clk_gen.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||
ad9361_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||
ad9361_clk_gen.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+17
@@ -0,0 +1,17 @@
|
||||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim -t 1ps +access +r +m+ad9361_clk_gen -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ad9361_clk_gen xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
|
||||
do {ad9361_clk_gen.udo}
|
||||
|
||||
run -all
|
||||
|
||||
endsim
|
||||
|
||||
quit -force
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Apr 06 12:05:38 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ad9361_clk_gen.sh
|
||||
|
||||
This command will launch the 'execute' function for the single-step flow. This
|
||||
function is called from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ad9361_clk_gen.sh' script.
|
||||
|
||||
./ad9361_clk_gen.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ad9361_clk_gen.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ad9361_clk_gen.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+177
@@ -0,0 +1,177 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ad9361_clk_gen.sh
|
||||
# Simulator : Cadence Incisive Enterprise Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Apr 06 12:05:38 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ad9361_clk_gen.sh [-help]
|
||||
# usage: ad9361_clk_gen.sh [-lib_map_path]
|
||||
# usage: ad9361_clk_gen.sh [-noclean_files]
|
||||
# usage: ad9361_clk_gen.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ad9361_clk_gen.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Directory path for design sources and include directories (if any) wrt this path
|
||||
ref_dir="."
|
||||
|
||||
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
|
||||
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
|
||||
ref_dir="$export_sim_ref_dir"
|
||||
fi
|
||||
|
||||
# Set the compiled library directory
|
||||
ref_lib_dir="."
|
||||
|
||||
# Command line options
|
||||
irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xil_defaultlib xpm)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="ies_lib"
|
||||
|
||||
# Script info
|
||||
echo -e "ad9361_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
execute
|
||||
}
|
||||
|
||||
# RUN_STEP: <execute>
|
||||
execute()
|
||||
{
|
||||
irun $irun_opts \
|
||||
-reflib "$ref_lib_dir/unisim:unisim" \
|
||||
-reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
|
||||
-reflib "$ref_lib_dir/secureip:secureip" \
|
||||
-reflib "$ref_lib_dir/unimacro:unimacro" \
|
||||
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
|
||||
-top xil_defaultlib.ad9361_clk_gen \
|
||||
-f run.f \
|
||||
-top glbl \
|
||||
glbl.v \
|
||||
+incdir+"$ref_dir/../../../ipstatic" \
|
||||
+incdir+"../../../ipstatic"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
else
|
||||
ref_lib_dir=$2
|
||||
fi
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Create design library directory paths
|
||||
create_lib_dir()
|
||||
{
|
||||
if [[ -e $sim_lib_dir ]]; then
|
||||
rm -rf $sim_lib_dir
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
lib_dir="$sim_lib_dir/$lib"
|
||||
if [[ ! -e $lib_dir ]]; then
|
||||
mkdir -p $lib_dir
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ad9361_clk_gen.sh [-help]\n\
|
||||
Usage: ad9361_clk_gen.sh [-lib_map_path]\n\
|
||||
Usage: ad9361_clk_gen.sh [-reset_run]\n\
|
||||
Usage: ad9361_clk_gen.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
|
||||
ad9361_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
|
||||
ad9361_clk_gen.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+15
@@ -0,0 +1,15 @@
|
||||
-makelib ies_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib ies_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
"../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v" \
|
||||
"../../../ip/ad9361_clk_gen/ad9361_clk_gen.v" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
glbl.v
|
||||
-endlib
|
||||
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Apr 06 12:05:38 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ad9361_clk_gen.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ad9361_clk_gen.sh' script.
|
||||
|
||||
./ad9361_clk_gen.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ad9361_clk_gen.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ad9361_clk_gen.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+167
@@ -0,0 +1,167 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ad9361_clk_gen.sh
|
||||
# Simulator : Mentor Graphics ModelSim Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Apr 06 12:05:38 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ad9361_clk_gen.sh [-help]
|
||||
# usage: ad9361_clk_gen.sh [-lib_map_path]
|
||||
# usage: ad9361_clk_gen.sh [-noclean_files]
|
||||
# usage: ad9361_clk_gen.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ad9361_clk_gen.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "ad9361_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
vsim -64 -c -do "do {simulate.do}" -l simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
copy_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
copy_setup_file $2
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Copy modelsim.ini file
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="/home/josh/Mentor/CompLib/2019.1.3"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
cp $src_file .
|
||||
fi
|
||||
}
|
||||
|
||||
# Create design library directory
|
||||
create_lib_dir()
|
||||
{
|
||||
lib_dir="modelsim_lib"
|
||||
if [[ -e $lib_dir ]]; then
|
||||
rm -rf $lib_dir
|
||||
fi
|
||||
|
||||
mkdir $lib_dir
|
||||
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ad9361_clk_gen.sh [-help]\n\
|
||||
Usage: ad9361_clk_gen.sh [-lib_map_path]\n\
|
||||
Usage: ad9361_clk_gen.sh [-reset_run]\n\
|
||||
Usage: ad9361_clk_gen.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
vlib modelsim_lib/work
|
||||
vlib modelsim_lib/msim
|
||||
|
||||
vlib modelsim_lib/msim/xil_defaultlib
|
||||
vlib modelsim_lib/msim/xpm
|
||||
|
||||
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
|
||||
vmap xpm modelsim_lib/msim/xpm
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ipstatic" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic" \
|
||||
"../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v" \
|
||||
"../../../ip/ad9361_clk_gen/ad9361_clk_gen.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||
ad9361_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||
ad9361_clk_gen.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
onbreak {quit -f}
|
||||
onerror {quit -f}
|
||||
|
||||
vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.ad9361_clk_gen xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
|
||||
do {ad9361_clk_gen.udo}
|
||||
|
||||
run -all
|
||||
|
||||
quit -force
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Apr 06 12:05:38 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ad9361_clk_gen.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ad9361_clk_gen.sh' script.
|
||||
|
||||
./ad9361_clk_gen.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ad9361_clk_gen.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ad9361_clk_gen.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+174
@@ -0,0 +1,174 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ad9361_clk_gen.sh
|
||||
# Simulator : Mentor Graphics Questa Advanced Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Apr 06 12:05:38 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ad9361_clk_gen.sh [-help]
|
||||
# usage: ad9361_clk_gen.sh [-lib_map_path]
|
||||
# usage: ad9361_clk_gen.sh [-noclean_files]
|
||||
# usage: ad9361_clk_gen.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ad9361_clk_gen.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "ad9361_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
elaborate
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <elaborate>
|
||||
elaborate()
|
||||
{
|
||||
source elaborate.do 2>&1 | tee -a elaborate.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
vsim -64 -c -do "do {simulate.do}" -l simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
copy_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
copy_setup_file $2
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Copy modelsim.ini file
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cmos_1t1r/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
cp $src_file .
|
||||
fi
|
||||
}
|
||||
|
||||
# Create design library directory
|
||||
create_lib_dir()
|
||||
{
|
||||
lib_dir="questa_lib"
|
||||
if [[ -e $lib_dir ]]; then
|
||||
rm -rf $lib_dir
|
||||
fi
|
||||
|
||||
mkdir $lib_dir
|
||||
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ad9361_clk_gen.sh [-help]\n\
|
||||
Usage: ad9361_clk_gen.sh [-lib_map_path]\n\
|
||||
Usage: ad9361_clk_gen.sh [-reset_run]\n\
|
||||
Usage: ad9361_clk_gen.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
vlib questa_lib/work
|
||||
vlib questa_lib/msim
|
||||
|
||||
vlib questa_lib/msim/xil_defaultlib
|
||||
vlib questa_lib/msim/xpm
|
||||
|
||||
vmap xil_defaultlib questa_lib/msim/xil_defaultlib
|
||||
vmap xpm questa_lib/msim/xpm
|
||||
|
||||
vlog -work xil_defaultlib -64 -sv "+incdir+../../../ipstatic" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic" \
|
||||
"../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v" \
|
||||
"../../../ip/ad9361_clk_gen/ad9361_clk_gen.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user