Archived
add dl814_dj_48m, with resampling
This commit is contained in:
@@ -216,7 +216,7 @@ The table below outlines the git-friendly Vivado project structure. It is import
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10. Generate Project Recreation Script
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10. Generate Project Recreation Script
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Create new script used to recreate the Vivado project via **File -> Project -> Write Tcl** with all checkbox set as default, set `Output File` to be `./projects/<engProj>/<gitProj>/project/<vivadoProj>/<vivadoProj>.tcl`.
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Create new script used to recreate the Vivado project via **File -> Project -> Write Tcl** with all checkbox set as default, set `Output File` to be `./projects/<engProj>/<gitProj>/project/<vivadoProj>.tcl`.
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11. (Optional) Archive Project
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11. (Optional) Archive Project
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@@ -228,16 +228,16 @@ The table below outlines the git-friendly Vivado project structure. It is import
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2. Source the Project Script
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2. Source the Project Script
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Open Vivado. In Tcl Console, change current working directory to `./projects/<engProj>/<gitProj>/project/<vivadoProj>/`.
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Open Vivado. In Tcl Console, change current working directory to `./projects/<engProj>/<gitProj>/project/`.
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``` tcl
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``` tcl
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cd ./projects/<engProj>/<gitProj>/project/<vivadoProj>/
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cd ./projects/<engProj>/<gitProj>/project/
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```
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```
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Make sure all files included the script header are present, then source the script.
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Make sure all files included the script header are present, then source the script.
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``` tcl
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``` tcl
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source ./projects/<engProj>/<gitProj>/project/<vivadoProj>/<vivadoProj>.tcl
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source ./<vivadoProj>.tcl
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```
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```
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> Xilinx recommends sourcing the Tcl script from the same directory in which the project was created, to maintain the relative path between the current working directory and the source files.
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> Xilinx recommends sourcing the Tcl script from the same directory in which the project was created, to maintain the relative path between the current working directory and the source files.
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@@ -60,18 +60,6 @@
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<FileSets Version="1" Minor="31">
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/../../coe/hrc_64_12_025.coe">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../coe/sweep_freq.coe">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../coe/hrc_64_12_025.coe">
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<File Path="$PPRDIR/../coe/hrc_64_12_025.coe">
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<FileInfo>
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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@@ -0,0 +1,61 @@
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# 2zynq0745_3ad9371 (xc7z100 version)
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## Timing Assertions Section
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create_clock -period 8.000 [get_ports refclk_p]
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## Physical Constraints Section
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# Clocks and Resets
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set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVDS_25 } [get_ports sysclk_p ] ;# FPGA_LOGIC_CLK_IN_1P
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set_property -dict {PACKAGE_PIN AD10 } [get_ports refclk_p ] ;# FPGA_JESD204B_CLK_IN_1P
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set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 } [get_ports sysref_p ] ;# FPGA_SYSREF_IN_1P
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# AD9528 Interface
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set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS33} [get_ports spi_csn_ad9528 ] ;# SPI_CS_9528
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set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS33} [get_ports spi_clk_ad9528 ] ;# SPI_SCK_9528
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set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports spi_mosi_ad9528 ] ;# SPI_SDI_9528
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set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS33} [get_ports spi_miso_ad9528 ] ;# SPI_SDO_9528
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set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS33} [get_ports ad9528_reset_b ] ;# AD9528_CLK_RESETB
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set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS33} [get_ports ad9528_sysref_req ] ;# AD9528_CLK_SYSREF_REQUEST
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# AD9371 Interface
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set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25 } [get_ports rx_sync_p ] ;# AD9371_1_SYNCINB0+
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set_property -dict {PACKAGE_PIN AJ25 IOSTANDARD LVDS_25 } [get_ports tx_sync_p ] ;# AD9371_1_SYNCOUTB0+
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set_property -dict {PACKAGE_PIN AH10 } [get_ports {rx_data_p[0]} ] ;# AD9371_1_SERDOUT0+
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set_property -dict {PACKAGE_PIN AJ8 } [get_ports {rx_data_p[1]} ] ;# AD9371_1_SERDOUT1+
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set_property -dict {PACKAGE_PIN AK10 } [get_ports {tx_data_p[0]} ] ;# AD9371_1_SERDIN0+
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set_property -dict {PACKAGE_PIN AK6 } [get_ports {tx_data_p[1]} ] ;# AD9371_1_SERDIN1+
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set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9371 ] ;# AD9371_1_SPI_CS
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set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports spi_clk_ad9371 ] ;# AD9371_1_SPI_CLK
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set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_mosi_ad9371 ] ;# AD9371_1_SPI_SDIN
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set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports spi_miso_ad9371 ] ;# AD9371_1_SPI_SDO
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set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports ad9371_test ] ;# AD9371_1_TEST
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set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports ad9371_reset_b ] ;# AD9371_1_RESETB
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set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports ad9371_gpint ] ;# AD9371_1_GP_INTERRUPT
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# RF Control
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set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[10]} ]
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set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[9] } ]
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set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[8] } ]
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set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[7] } ]
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set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[6] } ]
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set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[5] } ]
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set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[4] } ]
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set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[3] } ]
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set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[2] } ]
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set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[1] } ]
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set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[0] } ]
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set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS25} [get_ports hop_words_valid ]
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set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports freq_hop_switch ]
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set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports tx_gain_on ]
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set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports rx_gain_on ]
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set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports rx_gain_5bit ]
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set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports rx_gain_4bit ]
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set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS25} [get_ports rx_gain_3bit ]
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set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports tx_gain_6bit ]
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set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports tx_gain_5bit ]
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Binary file not shown.
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RADIX = 10;
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COEFDATA =
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-972,
|
||||||
|
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|
||||||
|
-1447,
|
||||||
|
-1687,
|
||||||
|
-1929,
|
||||||
|
-2172,
|
||||||
|
-2414,
|
||||||
|
-2656,
|
||||||
|
-2896,
|
||||||
|
-3133,
|
||||||
|
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|
||||||
|
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|
||||||
|
-3826,
|
||||||
|
-4048,
|
||||||
|
-4263,
|
||||||
|
-4472,
|
||||||
|
-4673,
|
||||||
|
-4866,
|
||||||
|
-5050,
|
||||||
|
-5224,
|
||||||
|
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|
||||||
|
-5539,
|
||||||
|
-5679,
|
||||||
|
-5807,
|
||||||
|
-5920,
|
||||||
|
-6020,
|
||||||
|
-6104,
|
||||||
|
-6173,
|
||||||
|
-6226,
|
||||||
|
-6262,
|
||||||
|
-6281,
|
||||||
|
-6282,
|
||||||
|
-6264,
|
||||||
|
-6228,
|
||||||
|
-6171,
|
||||||
|
-6096,
|
||||||
|
-5999,
|
||||||
|
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|
||||||
|
-5745,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
-4732,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
-1529,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
444,
|
||||||
|
985,
|
||||||
|
1545,
|
||||||
|
2123,
|
||||||
|
2717,
|
||||||
|
3328,
|
||||||
|
3955,
|
||||||
|
4597,
|
||||||
|
5253,
|
||||||
|
5921,
|
||||||
|
6603,
|
||||||
|
7295,
|
||||||
|
7998,
|
||||||
|
8711,
|
||||||
|
9432,
|
||||||
|
10160,
|
||||||
|
10895,
|
||||||
|
11635,
|
||||||
|
12379,
|
||||||
|
13126,
|
||||||
|
13875,
|
||||||
|
14624,
|
||||||
|
15374,
|
||||||
|
16121,
|
||||||
|
16866,
|
||||||
|
17607,
|
||||||
|
18342,
|
||||||
|
19071,
|
||||||
|
19793,
|
||||||
|
20505,
|
||||||
|
21208,
|
||||||
|
21900,
|
||||||
|
22579,
|
||||||
|
23245,
|
||||||
|
23896,
|
||||||
|
24532,
|
||||||
|
25151,
|
||||||
|
25752,
|
||||||
|
26334,
|
||||||
|
26896,
|
||||||
|
27438,
|
||||||
|
27957,
|
||||||
|
28455,
|
||||||
|
28928,
|
||||||
|
29377,
|
||||||
|
29801,
|
||||||
|
30200,
|
||||||
|
30571,
|
||||||
|
30915,
|
||||||
|
31232,
|
||||||
|
31520,
|
||||||
|
31779,
|
||||||
|
32009,
|
||||||
|
32209,
|
||||||
|
32379,
|
||||||
|
32518,
|
||||||
|
32627,
|
||||||
|
32704,
|
||||||
|
32751,
|
||||||
|
32767,
|
||||||
|
32751,
|
||||||
|
32704,
|
||||||
|
32627,
|
||||||
|
32518,
|
||||||
|
32379,
|
||||||
|
32209,
|
||||||
|
32009,
|
||||||
|
31779,
|
||||||
|
31520,
|
||||||
|
31232,
|
||||||
|
30915,
|
||||||
|
30571,
|
||||||
|
30200,
|
||||||
|
29801,
|
||||||
|
29377,
|
||||||
|
28928,
|
||||||
|
28455,
|
||||||
|
27957,
|
||||||
|
27438,
|
||||||
|
26896,
|
||||||
|
26334,
|
||||||
|
25752,
|
||||||
|
25151,
|
||||||
|
24532,
|
||||||
|
23896,
|
||||||
|
23245,
|
||||||
|
22579,
|
||||||
|
21900,
|
||||||
|
21208,
|
||||||
|
20505,
|
||||||
|
19793,
|
||||||
|
19071,
|
||||||
|
18342,
|
||||||
|
17607,
|
||||||
|
16866,
|
||||||
|
16121,
|
||||||
|
15374,
|
||||||
|
14624,
|
||||||
|
13875,
|
||||||
|
13126,
|
||||||
|
12379,
|
||||||
|
11635,
|
||||||
|
10895,
|
||||||
|
10160,
|
||||||
|
9432,
|
||||||
|
8711,
|
||||||
|
7998,
|
||||||
|
7295,
|
||||||
|
6603,
|
||||||
|
5921,
|
||||||
|
5253,
|
||||||
|
4597,
|
||||||
|
3955,
|
||||||
|
3328,
|
||||||
|
2717,
|
||||||
|
2123,
|
||||||
|
1545,
|
||||||
|
985,
|
||||||
|
444,
|
||||||
|
-79,
|
||||||
|
-582,
|
||||||
|
-1066,
|
||||||
|
-1529,
|
||||||
|
-1971,
|
||||||
|
-2392,
|
||||||
|
-2792,
|
||||||
|
-3170,
|
||||||
|
-3527,
|
||||||
|
-3861,
|
||||||
|
-4174,
|
||||||
|
-4464,
|
||||||
|
-4732,
|
||||||
|
-4978,
|
||||||
|
-5203,
|
||||||
|
-5405,
|
||||||
|
-5585,
|
||||||
|
-5745,
|
||||||
|
-5882,
|
||||||
|
-5999,
|
||||||
|
-6096,
|
||||||
|
-6171,
|
||||||
|
-6228,
|
||||||
|
-6264,
|
||||||
|
-6282,
|
||||||
|
-6281,
|
||||||
|
-6262,
|
||||||
|
-6226,
|
||||||
|
-6173,
|
||||||
|
-6104,
|
||||||
|
-6020,
|
||||||
|
-5920,
|
||||||
|
-5807,
|
||||||
|
-5679,
|
||||||
|
-5539,
|
||||||
|
-5387,
|
||||||
|
-5224,
|
||||||
|
-5050,
|
||||||
|
-4866,
|
||||||
|
-4673,
|
||||||
|
-4472,
|
||||||
|
-4263,
|
||||||
|
-4048,
|
||||||
|
-3826,
|
||||||
|
-3600,
|
||||||
|
-3368,
|
||||||
|
-3133,
|
||||||
|
-2896,
|
||||||
|
-2656,
|
||||||
|
-2414,
|
||||||
|
-2172,
|
||||||
|
-1929,
|
||||||
|
-1687,
|
||||||
|
-1447,
|
||||||
|
-1208,
|
||||||
|
-972,
|
||||||
|
-739,
|
||||||
|
-509,
|
||||||
|
-284,
|
||||||
|
-64,
|
||||||
|
151,
|
||||||
|
360,
|
||||||
|
563,
|
||||||
|
759,
|
||||||
|
948,
|
||||||
|
1130,
|
||||||
|
1304,
|
||||||
|
1469,
|
||||||
|
1627,
|
||||||
|
1775,
|
||||||
|
1915,
|
||||||
|
2046,
|
||||||
|
2168,
|
||||||
|
2280,
|
||||||
|
2382,
|
||||||
|
2476,
|
||||||
|
2559,
|
||||||
|
2633,
|
||||||
|
2698,
|
||||||
|
2752,
|
||||||
|
2798,
|
||||||
|
2833,
|
||||||
|
2860,
|
||||||
|
2877,
|
||||||
|
2886,
|
||||||
|
2885,
|
||||||
|
2876,
|
||||||
|
2859,
|
||||||
|
2833,
|
||||||
|
2800,
|
||||||
|
2759,
|
||||||
|
2711,
|
||||||
|
2655,
|
||||||
|
2593,
|
||||||
|
2525,
|
||||||
|
2451,
|
||||||
|
2371,
|
||||||
|
2285,
|
||||||
|
2195,
|
||||||
|
2101,
|
||||||
|
2002,
|
||||||
|
1900,
|
||||||
|
1794,
|
||||||
|
1686,
|
||||||
|
1575,
|
||||||
|
1461,
|
||||||
|
1346,
|
||||||
|
1230,
|
||||||
|
1113,
|
||||||
|
995,
|
||||||
|
877,
|
||||||
|
759,
|
||||||
|
642,
|
||||||
|
525,
|
||||||
|
410,
|
||||||
|
296,
|
||||||
|
184,
|
||||||
|
74,
|
||||||
|
-33,
|
||||||
|
-137,
|
||||||
|
-239,
|
||||||
|
-337,
|
||||||
|
-432,
|
||||||
|
-524,
|
||||||
|
-611,
|
||||||
|
-694,
|
||||||
|
-773,
|
||||||
|
-848,
|
||||||
|
-918,
|
||||||
|
-983,
|
||||||
|
-1044,
|
||||||
|
-1100,
|
||||||
|
-1151,
|
||||||
|
-1197,
|
||||||
|
-1238,
|
||||||
|
-1274,
|
||||||
|
-1306,
|
||||||
|
-1332,
|
||||||
|
-1353,
|
||||||
|
-1369,
|
||||||
|
-1381,
|
||||||
|
-1387,
|
||||||
|
-1389,
|
||||||
|
-1387,
|
||||||
|
-1380,
|
||||||
|
-1369,
|
||||||
|
-1353,
|
||||||
|
-1333,
|
||||||
|
-1310,
|
||||||
|
-1283,
|
||||||
|
-1252,
|
||||||
|
-1218,
|
||||||
|
-1181,
|
||||||
|
-1140,
|
||||||
|
-1097,
|
||||||
|
-1052,
|
||||||
|
-1004,
|
||||||
|
-954,
|
||||||
|
-902,
|
||||||
|
-848,
|
||||||
|
-793,
|
||||||
|
-736,
|
||||||
|
-679,
|
||||||
|
-621,
|
||||||
|
-562,
|
||||||
|
-502,
|
||||||
|
-443,
|
||||||
|
-383,
|
||||||
|
-324,
|
||||||
|
-265,
|
||||||
|
-207,
|
||||||
|
-150,
|
||||||
|
-93,
|
||||||
|
-38,
|
||||||
|
16,
|
||||||
|
69,
|
||||||
|
119,
|
||||||
|
169,
|
||||||
|
216,
|
||||||
|
261,
|
||||||
|
304,
|
||||||
|
345,
|
||||||
|
383,
|
||||||
|
419,
|
||||||
|
453,
|
||||||
|
484,
|
||||||
|
513,
|
||||||
|
538,
|
||||||
|
562,
|
||||||
|
582,
|
||||||
|
600,
|
||||||
|
615,
|
||||||
|
627,
|
||||||
|
637,
|
||||||
|
644,
|
||||||
|
649,
|
||||||
|
650,
|
||||||
|
650,
|
||||||
|
647,
|
||||||
|
641,
|
||||||
|
633,
|
||||||
|
623,
|
||||||
|
611,
|
||||||
|
596,
|
||||||
|
580,
|
||||||
|
562,
|
||||||
|
542,
|
||||||
|
520,
|
||||||
|
497,
|
||||||
|
473,
|
||||||
|
447,
|
||||||
|
420,
|
||||||
|
392,
|
||||||
|
363,
|
||||||
|
334,
|
||||||
|
304,
|
||||||
|
273,
|
||||||
|
242,
|
||||||
|
210,
|
||||||
|
179,
|
||||||
|
147,
|
||||||
|
116,
|
||||||
|
85,
|
||||||
|
54,
|
||||||
|
24,
|
||||||
|
-6,
|
||||||
|
-35,
|
||||||
|
-63,
|
||||||
|
-90,
|
||||||
|
-117,
|
||||||
|
-142,
|
||||||
|
-166,
|
||||||
|
-189,
|
||||||
|
-211,
|
||||||
|
-231,
|
||||||
|
-250,
|
||||||
|
-268,
|
||||||
|
-284,
|
||||||
|
-298,
|
||||||
|
-311,
|
||||||
|
-322,
|
||||||
|
-332,
|
||||||
|
-340,
|
||||||
|
-346,
|
||||||
|
-351,
|
||||||
|
-354,
|
||||||
|
-356,
|
||||||
|
-356,
|
||||||
|
-354,
|
||||||
|
-351,
|
||||||
|
-347,
|
||||||
|
-341,
|
||||||
|
-333,
|
||||||
|
-325,
|
||||||
|
-314,
|
||||||
|
-303,
|
||||||
|
-291,
|
||||||
|
-277,
|
||||||
|
-263,
|
||||||
|
-247,
|
||||||
|
-231,
|
||||||
|
-213,
|
||||||
|
-195,
|
||||||
|
-177,
|
||||||
|
-158,
|
||||||
|
-138,
|
||||||
|
-118,
|
||||||
|
-98,
|
||||||
|
-77,
|
||||||
|
-56,
|
||||||
|
-36,
|
||||||
|
-15,
|
||||||
|
5,
|
||||||
|
26,
|
||||||
|
46,
|
||||||
|
66,
|
||||||
|
85,
|
||||||
|
104,
|
||||||
|
122,
|
||||||
|
139,
|
||||||
|
156,
|
||||||
|
172,
|
||||||
|
187,
|
||||||
|
202,
|
||||||
|
215,
|
||||||
|
228,
|
||||||
|
239,
|
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|
249,
|
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|
259,
|
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|
267,
|
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|
274,
|
||||||
|
280,
|
||||||
|
285,
|
||||||
|
288,
|
||||||
|
291,
|
||||||
|
292,
|
||||||
|
292,
|
||||||
|
291,
|
||||||
|
289,
|
||||||
|
285,
|
||||||
|
281,
|
||||||
|
275,
|
||||||
|
268,
|
||||||
|
261,
|
||||||
|
252,
|
||||||
|
243,
|
||||||
|
232,
|
||||||
|
221,
|
||||||
|
209,
|
||||||
|
196,
|
||||||
|
182,
|
||||||
|
168,
|
||||||
|
153,
|
||||||
|
138,
|
||||||
|
122,
|
||||||
|
106,
|
||||||
|
89,
|
||||||
|
73,
|
||||||
|
56,
|
||||||
|
38,
|
||||||
|
21,
|
||||||
|
4,
|
||||||
|
-13,
|
||||||
|
-30,
|
||||||
|
-47;
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,258 @@
|
|||||||
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
|
-2147483647,
|
||||||
|
-2130640638,
|
||||||
|
-2113797629,
|
||||||
|
-2096954620,
|
||||||
|
-2080111611,
|
||||||
|
-2063268602,
|
||||||
|
-2046425593,
|
||||||
|
-2029582584,
|
||||||
|
-2012739575,
|
||||||
|
-1995896566,
|
||||||
|
-1979053557,
|
||||||
|
-1962210548,
|
||||||
|
-1945367539,
|
||||||
|
-1928524530,
|
||||||
|
-1911681521,
|
||||||
|
-1894838512,
|
||||||
|
-1877995503,
|
||||||
|
-1861152494,
|
||||||
|
-1844309485,
|
||||||
|
-1827466476,
|
||||||
|
-1810623467,
|
||||||
|
-1793780458,
|
||||||
|
-1776937449,
|
||||||
|
-1760094440,
|
||||||
|
-1743251431,
|
||||||
|
-1726408422,
|
||||||
|
-1709565413,
|
||||||
|
-1692722404,
|
||||||
|
-1675879395,
|
||||||
|
-1659036386,
|
||||||
|
-1642193377,
|
||||||
|
-1625350368,
|
||||||
|
-1608507359,
|
||||||
|
-1591664350,
|
||||||
|
-1574821341,
|
||||||
|
-1557978332,
|
||||||
|
-1541135323,
|
||||||
|
-1524292314,
|
||||||
|
-1507449305,
|
||||||
|
-1490606296,
|
||||||
|
-1473763287,
|
||||||
|
-1456920278,
|
||||||
|
-1440077269,
|
||||||
|
-1423234260,
|
||||||
|
-1406391251,
|
||||||
|
-1389548242,
|
||||||
|
-1372705233,
|
||||||
|
-1355862224,
|
||||||
|
-1339019215,
|
||||||
|
-1322176206,
|
||||||
|
-1305333197,
|
||||||
|
-1288490188,
|
||||||
|
-1271647179,
|
||||||
|
-1254804170,
|
||||||
|
-1237961161,
|
||||||
|
-1221118152,
|
||||||
|
-1204275143,
|
||||||
|
-1187432134,
|
||||||
|
-1170589125,
|
||||||
|
-1153746116,
|
||||||
|
-1136903107,
|
||||||
|
-1120060098,
|
||||||
|
-1103217089,
|
||||||
|
-1086374080,
|
||||||
|
-1069531071,
|
||||||
|
-1052688062,
|
||||||
|
-1035845053,
|
||||||
|
-1019002044,
|
||||||
|
-1002159035,
|
||||||
|
-985316026,
|
||||||
|
-968473017,
|
||||||
|
-951630008,
|
||||||
|
-934786999,
|
||||||
|
-917943990,
|
||||||
|
-901100981,
|
||||||
|
-884257972,
|
||||||
|
-867414963,
|
||||||
|
-850571954,
|
||||||
|
-833728945,
|
||||||
|
-816885936,
|
||||||
|
-800042927,
|
||||||
|
-783199918,
|
||||||
|
-766356909,
|
||||||
|
-749513900,
|
||||||
|
-732670891,
|
||||||
|
-715827882,
|
||||||
|
-698984873,
|
||||||
|
-682141864,
|
||||||
|
-665298855,
|
||||||
|
-648455846,
|
||||||
|
-631612837,
|
||||||
|
-614769828,
|
||||||
|
-597926819,
|
||||||
|
-581083810,
|
||||||
|
-564240801,
|
||||||
|
-547397792,
|
||||||
|
-530554783,
|
||||||
|
-513711774,
|
||||||
|
-496868765,
|
||||||
|
-480025756,
|
||||||
|
-463182747,
|
||||||
|
-446339738,
|
||||||
|
-429496729,
|
||||||
|
-412653720,
|
||||||
|
-395810711,
|
||||||
|
-378967702,
|
||||||
|
-362124693,
|
||||||
|
-345281684,
|
||||||
|
-328438675,
|
||||||
|
-311595666,
|
||||||
|
-294752657,
|
||||||
|
-277909648,
|
||||||
|
-261066639,
|
||||||
|
-244223630,
|
||||||
|
-227380621,
|
||||||
|
-210537612,
|
||||||
|
-193694603,
|
||||||
|
-176851594,
|
||||||
|
-160008585,
|
||||||
|
-143165576,
|
||||||
|
-126322567,
|
||||||
|
-109479558,
|
||||||
|
-92636549,
|
||||||
|
-75793540,
|
||||||
|
-58950531,
|
||||||
|
-42107522,
|
||||||
|
-25264513,
|
||||||
|
-8421504,
|
||||||
|
8421504,
|
||||||
|
25264513,
|
||||||
|
42107522,
|
||||||
|
58950531,
|
||||||
|
75793540,
|
||||||
|
92636549,
|
||||||
|
109479558,
|
||||||
|
126322567,
|
||||||
|
143165576,
|
||||||
|
160008585,
|
||||||
|
176851594,
|
||||||
|
193694603,
|
||||||
|
210537612,
|
||||||
|
227380621,
|
||||||
|
244223630,
|
||||||
|
261066639,
|
||||||
|
277909648,
|
||||||
|
294752657,
|
||||||
|
311595666,
|
||||||
|
328438675,
|
||||||
|
345281684,
|
||||||
|
362124693,
|
||||||
|
378967702,
|
||||||
|
395810711,
|
||||||
|
412653720,
|
||||||
|
429496729,
|
||||||
|
446339738,
|
||||||
|
463182747,
|
||||||
|
480025756,
|
||||||
|
496868765,
|
||||||
|
513711774,
|
||||||
|
530554783,
|
||||||
|
547397792,
|
||||||
|
564240801,
|
||||||
|
581083810,
|
||||||
|
597926819,
|
||||||
|
614769828,
|
||||||
|
631612837,
|
||||||
|
648455846,
|
||||||
|
665298855,
|
||||||
|
682141864,
|
||||||
|
698984873,
|
||||||
|
715827882,
|
||||||
|
732670891,
|
||||||
|
749513900,
|
||||||
|
766356909,
|
||||||
|
783199918,
|
||||||
|
800042927,
|
||||||
|
816885936,
|
||||||
|
833728945,
|
||||||
|
850571954,
|
||||||
|
867414963,
|
||||||
|
884257972,
|
||||||
|
901100981,
|
||||||
|
917943990,
|
||||||
|
934786999,
|
||||||
|
951630008,
|
||||||
|
968473017,
|
||||||
|
985316026,
|
||||||
|
1002159035,
|
||||||
|
1019002044,
|
||||||
|
1035845053,
|
||||||
|
1052688062,
|
||||||
|
1069531071,
|
||||||
|
1086374080,
|
||||||
|
1103217089,
|
||||||
|
1120060098,
|
||||||
|
1136903107,
|
||||||
|
1153746116,
|
||||||
|
1170589125,
|
||||||
|
1187432134,
|
||||||
|
1204275143,
|
||||||
|
1221118152,
|
||||||
|
1237961161,
|
||||||
|
1254804170,
|
||||||
|
1271647179,
|
||||||
|
1288490188,
|
||||||
|
1305333197,
|
||||||
|
1322176206,
|
||||||
|
1339019215,
|
||||||
|
1355862224,
|
||||||
|
1372705233,
|
||||||
|
1389548242,
|
||||||
|
1406391251,
|
||||||
|
1423234260,
|
||||||
|
1440077269,
|
||||||
|
1456920278,
|
||||||
|
1473763287,
|
||||||
|
1490606296,
|
||||||
|
1507449305,
|
||||||
|
1524292314,
|
||||||
|
1541135323,
|
||||||
|
1557978332,
|
||||||
|
1574821341,
|
||||||
|
1591664350,
|
||||||
|
1608507359,
|
||||||
|
1625350368,
|
||||||
|
1642193377,
|
||||||
|
1659036386,
|
||||||
|
1675879395,
|
||||||
|
1692722404,
|
||||||
|
1709565413,
|
||||||
|
1726408422,
|
||||||
|
1743251431,
|
||||||
|
1760094440,
|
||||||
|
1776937449,
|
||||||
|
1793780458,
|
||||||
|
1810623467,
|
||||||
|
1827466476,
|
||||||
|
1844309485,
|
||||||
|
1861152494,
|
||||||
|
1877995503,
|
||||||
|
1894838512,
|
||||||
|
1911681521,
|
||||||
|
1928524530,
|
||||||
|
1945367539,
|
||||||
|
1962210548,
|
||||||
|
1979053557,
|
||||||
|
1995896566,
|
||||||
|
2012739575,
|
||||||
|
2029582584,
|
||||||
|
2046425593,
|
||||||
|
2063268602,
|
||||||
|
2080111611,
|
||||||
|
2096954620,
|
||||||
|
2113797629,
|
||||||
|
2130640638,
|
||||||
|
2147483647;
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1 @@
|
|||||||
|
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||||
@@ -0,0 +1,71 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:cmpy:6.0
|
||||||
|
// IP Revision: 17
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
cmpy_18x8 your_instance_name (
|
||||||
|
.aclk(aclk), // input wire aclk
|
||||||
|
.s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid
|
||||||
|
.s_axis_a_tdata(s_axis_a_tdata), // input wire [47 : 0] s_axis_a_tdata
|
||||||
|
.s_axis_b_tvalid(s_axis_b_tvalid), // input wire s_axis_b_tvalid
|
||||||
|
.s_axis_b_tdata(s_axis_b_tdata), // input wire [15 : 0] s_axis_b_tdata
|
||||||
|
.m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid
|
||||||
|
.m_axis_dout_tdata(m_axis_dout_tdata) // output wire [63 : 0] m_axis_dout_tdata
|
||||||
|
);
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
// You must compile the wrapper file cmpy_18x8.v when simulating
|
||||||
|
// the core, cmpy_18x8. When compiling the wrapper file, be sure to
|
||||||
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
@@ -0,0 +1,87 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:cmpy:6.0
|
||||||
|
-- IP Revision: 17
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture header.
|
||||||
|
|
||||||
|
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||||
|
COMPONENT cmpy_18x8
|
||||||
|
PORT (
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
s_axis_a_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||||
|
s_axis_b_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||||
|
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture
|
||||||
|
-- body. Substitute your own instance name and net names.
|
||||||
|
|
||||||
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||||
|
your_instance_name : cmpy_18x8
|
||||||
|
PORT MAP (
|
||||||
|
aclk => aclk,
|
||||||
|
s_axis_a_tvalid => s_axis_a_tvalid,
|
||||||
|
s_axis_a_tdata => s_axis_a_tdata,
|
||||||
|
s_axis_b_tvalid => s_axis_b_tvalid,
|
||||||
|
s_axis_b_tdata => s_axis_b_tdata,
|
||||||
|
m_axis_dout_tvalid => m_axis_dout_tvalid,
|
||||||
|
m_axis_dout_tdata => m_axis_dout_tdata
|
||||||
|
);
|
||||||
|
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
-- You must compile the wrapper file cmpy_18x8.vhd when simulating
|
||||||
|
-- the core, cmpy_18x8. When compiling the wrapper file, be sure to
|
||||||
|
-- reference the VHDL simulation library.
|
||||||
|
|
||||||
+9282
File diff suppressed because it is too large
Load Diff
+12962
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,27 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
// Date : Fri Mar 17 22:22:44 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v
|
||||||
|
// Design : cmpy_18x8
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *)
|
||||||
|
module cmpy_18x8(aclk, s_axis_a_tvalid, s_axis_a_tdata,
|
||||||
|
s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]" */;
|
||||||
|
input aclk;
|
||||||
|
input s_axis_a_tvalid;
|
||||||
|
input [47:0]s_axis_a_tdata;
|
||||||
|
input s_axis_b_tvalid;
|
||||||
|
input [15:0]s_axis_b_tdata;
|
||||||
|
output m_axis_dout_tvalid;
|
||||||
|
output [63:0]m_axis_dout_tdata;
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,36 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
-- Date : Fri Mar 17 22:22:44 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl
|
||||||
|
-- Design : cmpy_18x8
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity cmpy_18x8 is
|
||||||
|
Port (
|
||||||
|
aclk : in STD_LOGIC;
|
||||||
|
s_axis_a_tvalid : in STD_LOGIC;
|
||||||
|
s_axis_a_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||||
|
s_axis_b_tvalid : in STD_LOGIC;
|
||||||
|
s_axis_b_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
m_axis_dout_tvalid : out STD_LOGIC;
|
||||||
|
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end cmpy_18x8;
|
||||||
|
|
||||||
|
architecture stub of cmpy_18x8 is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]";
|
||||||
|
attribute x_core_info : string;
|
||||||
|
attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
+387
@@ -0,0 +1,387 @@
|
|||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- Description:
|
||||||
|
-- This is an example testbench for the Complex Multiplier IP core.
|
||||||
|
-- The testbench has been generated by Vivado to accompany the IP core
|
||||||
|
-- instance you have generated.
|
||||||
|
--
|
||||||
|
-- This testbench is for demonstration purposes only. See note below for
|
||||||
|
-- instructions on how to use it with your core.
|
||||||
|
--
|
||||||
|
-- See the Complex Multiplier product guide for further information
|
||||||
|
-- about this core.
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- Using this testbench
|
||||||
|
--
|
||||||
|
-- This testbench instantiates your generated Complex Multiplier core
|
||||||
|
-- instance named "cmpy_18x8".
|
||||||
|
--
|
||||||
|
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||||
|
-- documentation for details.
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.numeric_std.all;
|
||||||
|
use ieee.math_real.all;
|
||||||
|
|
||||||
|
entity tb_cmpy_18x8 is
|
||||||
|
end tb_cmpy_18x8;
|
||||||
|
|
||||||
|
architecture tb of tb_cmpy_18x8 is
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Timing constants
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
constant CLOCK_PERIOD : time := 100 ns;
|
||||||
|
constant T_HOLD : time := 10 ns;
|
||||||
|
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||||
|
constant TEST_CYCLES : integer := 3000;
|
||||||
|
constant PHASE_CYCLES : integer := 1000;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- DUT input signals
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
-- General inputs
|
||||||
|
signal aclk : std_logic := '0'; -- the master clock
|
||||||
|
|
||||||
|
-- Slave channel A inputs
|
||||||
|
signal s_axis_a_tvalid : std_logic := '0'; -- TVALID for channel A
|
||||||
|
signal s_axis_a_tdata : std_logic_vector(47 downto 0) := (others => '0'); -- TDATA for channel A
|
||||||
|
|
||||||
|
-- Slave channel B inputs
|
||||||
|
signal s_axis_b_tvalid : std_logic := '0'; -- TVALID for channel B
|
||||||
|
signal s_axis_b_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- TDATA for channel B
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- DUT output signals
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
-- Master channel DOUT outputs
|
||||||
|
signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel DOUT
|
||||||
|
signal m_axis_dout_tdata : std_logic_vector(63 downto 0) := (others => '0'); -- TDATA for channel DOUT
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Aliases for AXI channel TDATA fields
|
||||||
|
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||||
|
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||||
|
-- to prevent the simulator optimizing away these signals.
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
signal s_axis_a_tdata_real : std_logic_vector(17 downto 0) := (others => '0');
|
||||||
|
signal s_axis_a_tdata_imag : std_logic_vector(17 downto 0) := (others => '0');
|
||||||
|
signal s_axis_b_tdata_real : std_logic_vector(7 downto 0) := (others => '0');
|
||||||
|
signal s_axis_b_tdata_imag : std_logic_vector(7 downto 0) := (others => '0');
|
||||||
|
signal m_axis_dout_tdata_real : std_logic_vector(26 downto 0) := (others => '0');
|
||||||
|
signal m_axis_dout_tdata_imag : std_logic_vector(26 downto 0) := (others => '0');
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Testbench signals
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
signal cycles : integer := 0; -- Clock cycle counter
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Constants, types and functions to create input data
|
||||||
|
-- Treat the complex multiplier as a mixer that is combining two
|
||||||
|
-- sinusoids exp(+/-jwt) of different frequencies and amplitudes:
|
||||||
|
-- channel A: exp(+jwt), frequency = clock / 30, amplitude = fullscale >> 3
|
||||||
|
-- channel B: exp(-jwt), frequency = clock / 32, amplitude = fullscale
|
||||||
|
-- The output of the complex multiplier is a sinusoid with a frequency
|
||||||
|
-- equal to the difference between the input frequencies.
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
constant IP_A_DEPTH : integer := 30;
|
||||||
|
constant IP_A_WIDTH : integer := 18;
|
||||||
|
constant IP_A_SHIFT : integer := 3; -- bit shift for amplitude
|
||||||
|
constant IP_B_DEPTH : integer := 32;
|
||||||
|
constant IP_B_WIDTH : integer := 8;
|
||||||
|
constant IP_B_SHIFT : integer := 0; -- no bit shift, max amplitude
|
||||||
|
type T_IP_INT_ENTRY is record
|
||||||
|
re : integer;
|
||||||
|
im : integer;
|
||||||
|
end record;
|
||||||
|
type T_IP_A_ENTRY is record
|
||||||
|
re : std_logic_vector(IP_A_WIDTH-1 downto 0);
|
||||||
|
im : std_logic_vector(IP_A_WIDTH-1 downto 0);
|
||||||
|
end record;
|
||||||
|
type T_IP_B_ENTRY is record
|
||||||
|
re : std_logic_vector(IP_B_WIDTH-1 downto 0);
|
||||||
|
im : std_logic_vector(IP_B_WIDTH-1 downto 0);
|
||||||
|
end record;
|
||||||
|
type T_IP_A_TABLE is array (0 to IP_A_DEPTH-1) of T_IP_A_ENTRY;
|
||||||
|
type T_IP_B_TABLE is array (0 to IP_B_DEPTH-1) of T_IP_B_ENTRY;
|
||||||
|
|
||||||
|
-- Common function to calculate sine and cosine values
|
||||||
|
function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is
|
||||||
|
variable result : T_IP_INT_ENTRY;
|
||||||
|
variable theta : real;
|
||||||
|
variable limited_width : integer := width - 2;
|
||||||
|
begin
|
||||||
|
if limited_width > 30 then
|
||||||
|
limited_width := 30;
|
||||||
|
end if;
|
||||||
|
theta := real(index) / real(depth) * 2.0 * MATH_PI;
|
||||||
|
result.re := integer(round(cos(theta) * real(2**limited_width-1)));
|
||||||
|
result.im := integer(round(sin(theta) * real(2**limited_width-1)));
|
||||||
|
return result;
|
||||||
|
end function create_ip_entry;
|
||||||
|
|
||||||
|
-- Use separate functions to calculate channel A and B sinusoids as they return different types
|
||||||
|
function create_ip_a_table return T_IP_A_TABLE is
|
||||||
|
variable result : T_IP_A_TABLE;
|
||||||
|
variable entry_int : T_IP_INT_ENTRY;
|
||||||
|
begin
|
||||||
|
for i in 0 to IP_A_DEPTH-1 loop
|
||||||
|
entry_int := create_ip_entry(i, IP_A_DEPTH, IP_A_WIDTH - IP_A_SHIFT);
|
||||||
|
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_A_WIDTH));
|
||||||
|
result(i).im := std_logic_vector(to_signed(entry_int.im, IP_A_WIDTH));
|
||||||
|
end loop;
|
||||||
|
return result;
|
||||||
|
end function create_ip_a_table;
|
||||||
|
|
||||||
|
function create_ip_b_table return T_IP_B_TABLE is
|
||||||
|
variable result : T_IP_B_TABLE;
|
||||||
|
variable entry_int : T_IP_INT_ENTRY;
|
||||||
|
begin
|
||||||
|
for i in 0 to IP_B_DEPTH-1 loop
|
||||||
|
entry_int := create_ip_entry(IP_B_DEPTH-1-i, IP_B_DEPTH, IP_B_WIDTH - IP_B_SHIFT); -- note rotation direction
|
||||||
|
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_B_WIDTH));
|
||||||
|
result(i).im := std_logic_vector(to_signed(entry_int.im, IP_B_WIDTH));
|
||||||
|
end loop;
|
||||||
|
return result;
|
||||||
|
end function create_ip_b_table;
|
||||||
|
|
||||||
|
-- Call the functions to create the data
|
||||||
|
constant IP_A_DATA : T_IP_A_TABLE := create_ip_a_table;
|
||||||
|
constant IP_B_DATA : T_IP_B_TABLE := create_ip_b_table;
|
||||||
|
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Instantiate the DUT
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
dut : entity work.cmpy_18x8
|
||||||
|
port map (
|
||||||
|
aclk => aclk,
|
||||||
|
s_axis_a_tvalid => s_axis_a_tvalid,
|
||||||
|
s_axis_a_tdata => s_axis_a_tdata,
|
||||||
|
s_axis_b_tvalid => s_axis_b_tvalid,
|
||||||
|
s_axis_b_tdata => s_axis_b_tdata,
|
||||||
|
m_axis_dout_tvalid => m_axis_dout_tvalid,
|
||||||
|
m_axis_dout_tdata => m_axis_dout_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Generate clock
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
clock_gen : process
|
||||||
|
begin
|
||||||
|
aclk <= '0';
|
||||||
|
wait for CLOCK_PERIOD;
|
||||||
|
loop
|
||||||
|
cycles <= cycles + 1;
|
||||||
|
aclk <= '0';
|
||||||
|
wait for CLOCK_PERIOD/2;
|
||||||
|
aclk <= '1';
|
||||||
|
wait for CLOCK_PERIOD/2;
|
||||||
|
if cycles >= TEST_CYCLES then
|
||||||
|
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||||
|
wait;
|
||||||
|
end if;
|
||||||
|
end loop;
|
||||||
|
end process clock_gen;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Generate inputs
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
stimuli : process
|
||||||
|
variable ip_a_index : integer := 0;
|
||||||
|
variable ip_b_index : integer := 0;
|
||||||
|
variable a_tvalid_nxt : std_logic := '0';
|
||||||
|
variable b_tvalid_nxt : std_logic := '0';
|
||||||
|
variable phase2_cycles : integer := 1;
|
||||||
|
variable phase2_count : integer := 0;
|
||||||
|
constant PHASE2_LIMIT : integer := 30;
|
||||||
|
begin
|
||||||
|
|
||||||
|
-- Test is stopped in clock_gen process, use endless loop here
|
||||||
|
loop
|
||||||
|
|
||||||
|
-- Drive inputs T_HOLD time after rising edge of clock
|
||||||
|
wait until rising_edge(aclk);
|
||||||
|
wait for T_HOLD;
|
||||||
|
|
||||||
|
-- Drive AXI TVALID signals to demonstrate different types of operation
|
||||||
|
case cycles is -- do different types of operation at different phases of the test
|
||||||
|
when 0 to PHASE_CYCLES * 1 - 1 =>
|
||||||
|
-- Phase 1: inputs always valid, no missing input data
|
||||||
|
a_tvalid_nxt := '1';
|
||||||
|
b_tvalid_nxt := '1';
|
||||||
|
when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
|
||||||
|
-- Phase 2: deprive channel A of valid transactions at an increasing rate
|
||||||
|
b_tvalid_nxt := '1';
|
||||||
|
if phase2_count < phase2_cycles then
|
||||||
|
a_tvalid_nxt := '0';
|
||||||
|
else
|
||||||
|
a_tvalid_nxt := '1';
|
||||||
|
end if;
|
||||||
|
phase2_count := phase2_count + 1;
|
||||||
|
if phase2_count >= PHASE2_LIMIT then
|
||||||
|
phase2_count := 0;
|
||||||
|
phase2_cycles := phase2_cycles + 1;
|
||||||
|
end if;
|
||||||
|
when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
|
||||||
|
-- Phase 3: deprive channel A of 1 out of 2 transactions, and channel B of 1 out of 3 transactions
|
||||||
|
if cycles mod 2 = 0 then
|
||||||
|
a_tvalid_nxt := '0';
|
||||||
|
else
|
||||||
|
a_tvalid_nxt := '1';
|
||||||
|
end if;
|
||||||
|
if cycles mod 3 = 0 then
|
||||||
|
b_tvalid_nxt := '0';
|
||||||
|
else
|
||||||
|
b_tvalid_nxt := '1';
|
||||||
|
end if;
|
||||||
|
when others =>
|
||||||
|
-- Test will stop imminently - do nothing
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
|
||||||
|
-- Drive handshake signals with local variable values
|
||||||
|
s_axis_a_tvalid <= a_tvalid_nxt;
|
||||||
|
s_axis_b_tvalid <= b_tvalid_nxt;
|
||||||
|
|
||||||
|
-- Drive AXI slave channel A payload
|
||||||
|
-- Drive '0's on payload signals when not valid
|
||||||
|
if a_tvalid_nxt /= '1' then
|
||||||
|
s_axis_a_tdata <= (others => '0');
|
||||||
|
else
|
||||||
|
-- TDATA: Real and imaginary components are each 18 bits wide and byte-aligned at their LSBs
|
||||||
|
s_axis_a_tdata(17 downto 0) <= IP_A_DATA(ip_a_index).re;
|
||||||
|
s_axis_a_tdata(23 downto 18) <= (others => IP_A_DATA(ip_a_index).re(17)); -- sign-extend;
|
||||||
|
s_axis_a_tdata(41 downto 24) <= IP_A_DATA(ip_a_index).im;
|
||||||
|
s_axis_a_tdata(47 downto 42) <= (others => IP_A_DATA(ip_a_index).im(17)); -- sign-extend;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- Drive AXI slave channel B payload
|
||||||
|
-- Drive '0's on payload signals when not valid
|
||||||
|
if b_tvalid_nxt /= '1' then
|
||||||
|
s_axis_b_tdata <= (others => '0');
|
||||||
|
else
|
||||||
|
-- TDATA: Real and imaginary components are each 8 bits wide and byte-aligned at their LSBs
|
||||||
|
s_axis_b_tdata(7 downto 0) <= IP_B_DATA(ip_b_index).re;
|
||||||
|
s_axis_b_tdata(15 downto 8) <= IP_B_DATA(ip_b_index).im;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- Increment input data indices
|
||||||
|
if a_tvalid_nxt = '1' then
|
||||||
|
ip_a_index := ip_a_index + 1;
|
||||||
|
if ip_a_index = IP_A_DEPTH then
|
||||||
|
ip_a_index := 0;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
if b_tvalid_nxt = '1' then
|
||||||
|
ip_b_index := ip_b_index + 1;
|
||||||
|
if ip_b_index = IP_B_DEPTH then
|
||||||
|
ip_b_index := 0;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end loop;
|
||||||
|
|
||||||
|
end process stimuli;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Check outputs
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
check_outputs : process
|
||||||
|
variable check_ok : boolean := true;
|
||||||
|
begin
|
||||||
|
|
||||||
|
-- Check outputs T_STROBE time after rising edge of clock
|
||||||
|
wait until rising_edge(aclk);
|
||||||
|
wait for T_STROBE;
|
||||||
|
|
||||||
|
-- Do not check the output payload values, as this requires the behavioral model
|
||||||
|
-- which would make this demonstration testbench unwieldy.
|
||||||
|
-- Instead, check the protocol of the DOUT channel:
|
||||||
|
-- check that the payload is valid (not X) when TVALID is high
|
||||||
|
|
||||||
|
if m_axis_dout_tvalid = '1' then
|
||||||
|
if is_x(m_axis_dout_tdata) then
|
||||||
|
report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
|
||||||
|
check_ok := false;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
|
||||||
|
assert check_ok
|
||||||
|
report "ERROR: terminating test with failures." severity failure;
|
||||||
|
|
||||||
|
end process check_outputs;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
s_axis_a_tdata_real <= s_axis_a_tdata(17 downto 0);
|
||||||
|
s_axis_a_tdata_imag <= s_axis_a_tdata(41 downto 24);
|
||||||
|
s_axis_b_tdata_real <= s_axis_b_tdata(7 downto 0);
|
||||||
|
s_axis_b_tdata_imag <= s_axis_b_tdata(15 downto 8);
|
||||||
|
m_axis_dout_tdata_real <= m_axis_dout_tdata(26 downto 0);
|
||||||
|
m_axis_dout_tdata_imag <= m_axis_dout_tdata(58 downto 32);
|
||||||
|
|
||||||
|
end tb;
|
||||||
|
|
||||||
@@ -0,0 +1,202 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:cmpy:6.0
|
||||||
|
-- IP Revision: 17
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
LIBRARY cmpy_v6_0_17;
|
||||||
|
USE cmpy_v6_0_17.cmpy_v6_0_17;
|
||||||
|
|
||||||
|
ENTITY cmpy_18x8 IS
|
||||||
|
PORT (
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
s_axis_a_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||||
|
s_axis_b_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||||
|
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END cmpy_18x8;
|
||||||
|
|
||||||
|
ARCHITECTURE cmpy_18x8_arch OF cmpy_18x8 IS
|
||||||
|
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||||
|
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cmpy_18x8_arch: ARCHITECTURE IS "yes";
|
||||||
|
COMPONENT cmpy_v6_0_17 IS
|
||||||
|
GENERIC (
|
||||||
|
C_VERBOSITY : INTEGER;
|
||||||
|
C_XDEVICEFAMILY : STRING;
|
||||||
|
C_XDEVICE : STRING;
|
||||||
|
C_A_WIDTH : INTEGER;
|
||||||
|
C_B_WIDTH : INTEGER;
|
||||||
|
C_OUT_WIDTH : INTEGER;
|
||||||
|
C_LATENCY : INTEGER;
|
||||||
|
C_MULT_TYPE : INTEGER;
|
||||||
|
C_OPTIMIZE_GOAL : INTEGER;
|
||||||
|
HAS_NEGATE : INTEGER;
|
||||||
|
SINGLE_OUTPUT : INTEGER;
|
||||||
|
ROUND : INTEGER;
|
||||||
|
USE_DSP_CASCADES : INTEGER;
|
||||||
|
C_THROTTLE_SCHEME : INTEGER;
|
||||||
|
C_HAS_ACLKEN : INTEGER;
|
||||||
|
C_HAS_ARESETN : INTEGER;
|
||||||
|
C_HAS_S_AXIS_A_TUSER : INTEGER;
|
||||||
|
C_HAS_S_AXIS_A_TLAST : INTEGER;
|
||||||
|
C_HAS_S_AXIS_B_TUSER : INTEGER;
|
||||||
|
C_HAS_S_AXIS_B_TLAST : INTEGER;
|
||||||
|
C_HAS_S_AXIS_CTRL_TUSER : INTEGER;
|
||||||
|
C_HAS_S_AXIS_CTRL_TLAST : INTEGER;
|
||||||
|
C_TLAST_RESOLUTION : INTEGER;
|
||||||
|
C_S_AXIS_A_TDATA_WIDTH : INTEGER;
|
||||||
|
C_S_AXIS_A_TUSER_WIDTH : INTEGER;
|
||||||
|
C_S_AXIS_B_TDATA_WIDTH : INTEGER;
|
||||||
|
C_S_AXIS_B_TUSER_WIDTH : INTEGER;
|
||||||
|
C_S_AXIS_CTRL_TDATA_WIDTH : INTEGER;
|
||||||
|
C_S_AXIS_CTRL_TUSER_WIDTH : INTEGER;
|
||||||
|
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
|
||||||
|
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
aclken : IN STD_LOGIC;
|
||||||
|
aresetn : IN STD_LOGIC;
|
||||||
|
s_axis_a_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_a_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
s_axis_a_tlast : IN STD_LOGIC;
|
||||||
|
s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||||
|
s_axis_b_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_b_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
s_axis_b_tlast : IN STD_LOGIC;
|
||||||
|
s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||||
|
s_axis_ctrl_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_ctrl_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_ctrl_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
s_axis_ctrl_tlast : IN STD_LOGIC;
|
||||||
|
s_axis_ctrl_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||||
|
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_dout_tready : IN STD_LOGIC;
|
||||||
|
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
m_axis_dout_tlast : OUT STD_LOGIC;
|
||||||
|
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT cmpy_v6_0_17;
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_dout_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DOUT, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 6, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||||
|
BEGIN
|
||||||
|
U0 : cmpy_v6_0_17
|
||||||
|
GENERIC MAP (
|
||||||
|
C_VERBOSITY => 0,
|
||||||
|
C_XDEVICEFAMILY => "zynq",
|
||||||
|
C_XDEVICE => "xc7z100",
|
||||||
|
C_A_WIDTH => 18,
|
||||||
|
C_B_WIDTH => 8,
|
||||||
|
C_OUT_WIDTH => 27,
|
||||||
|
C_LATENCY => 4,
|
||||||
|
C_MULT_TYPE => 0,
|
||||||
|
C_OPTIMIZE_GOAL => 0,
|
||||||
|
HAS_NEGATE => 0,
|
||||||
|
SINGLE_OUTPUT => 0,
|
||||||
|
ROUND => 0,
|
||||||
|
USE_DSP_CASCADES => 1,
|
||||||
|
C_THROTTLE_SCHEME => 3,
|
||||||
|
C_HAS_ACLKEN => 0,
|
||||||
|
C_HAS_ARESETN => 0,
|
||||||
|
C_HAS_S_AXIS_A_TUSER => 0,
|
||||||
|
C_HAS_S_AXIS_A_TLAST => 0,
|
||||||
|
C_HAS_S_AXIS_B_TUSER => 0,
|
||||||
|
C_HAS_S_AXIS_B_TLAST => 0,
|
||||||
|
C_HAS_S_AXIS_CTRL_TUSER => 0,
|
||||||
|
C_HAS_S_AXIS_CTRL_TLAST => 0,
|
||||||
|
C_TLAST_RESOLUTION => 0,
|
||||||
|
C_S_AXIS_A_TDATA_WIDTH => 48,
|
||||||
|
C_S_AXIS_A_TUSER_WIDTH => 1,
|
||||||
|
C_S_AXIS_B_TDATA_WIDTH => 16,
|
||||||
|
C_S_AXIS_B_TUSER_WIDTH => 1,
|
||||||
|
C_S_AXIS_CTRL_TDATA_WIDTH => 8,
|
||||||
|
C_S_AXIS_CTRL_TUSER_WIDTH => 1,
|
||||||
|
C_M_AXIS_DOUT_TDATA_WIDTH => 64,
|
||||||
|
C_M_AXIS_DOUT_TUSER_WIDTH => 1
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
aclk => aclk,
|
||||||
|
aclken => '1',
|
||||||
|
aresetn => '1',
|
||||||
|
s_axis_a_tvalid => s_axis_a_tvalid,
|
||||||
|
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
s_axis_a_tlast => '0',
|
||||||
|
s_axis_a_tdata => s_axis_a_tdata,
|
||||||
|
s_axis_b_tvalid => s_axis_b_tvalid,
|
||||||
|
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
s_axis_b_tlast => '0',
|
||||||
|
s_axis_b_tdata => s_axis_b_tdata,
|
||||||
|
s_axis_ctrl_tvalid => '0',
|
||||||
|
s_axis_ctrl_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
s_axis_ctrl_tlast => '0',
|
||||||
|
s_axis_ctrl_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||||
|
m_axis_dout_tvalid => m_axis_dout_tvalid,
|
||||||
|
m_axis_dout_tready => '0',
|
||||||
|
m_axis_dout_tdata => m_axis_dout_tdata
|
||||||
|
);
|
||||||
|
END cmpy_18x8_arch;
|
||||||
@@ -0,0 +1,69 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:dds_compiler:6.0
|
||||||
|
// IP Revision: 18
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
dds_32b_8b your_instance_name (
|
||||||
|
.aclk(aclk), // input wire aclk
|
||||||
|
.s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid
|
||||||
|
.s_axis_config_tdata(s_axis_config_tdata), // input wire [31 : 0] s_axis_config_tdata
|
||||||
|
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
|
||||||
|
.m_axis_data_tdata(m_axis_data_tdata) // output wire [15 : 0] m_axis_data_tdata
|
||||||
|
);
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
// You must compile the wrapper file dds_32b_8b.v when simulating
|
||||||
|
// the core, dds_32b_8b. When compiling the wrapper file, be sure to
|
||||||
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
@@ -0,0 +1,83 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
|
||||||
|
-- IP Revision: 18
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture header.
|
||||||
|
|
||||||
|
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||||
|
COMPONENT dds_32b_8b
|
||||||
|
PORT (
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
s_axis_config_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_config_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||||
|
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture
|
||||||
|
-- body. Substitute your own instance name and net names.
|
||||||
|
|
||||||
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||||
|
your_instance_name : dds_32b_8b
|
||||||
|
PORT MAP (
|
||||||
|
aclk => aclk,
|
||||||
|
s_axis_config_tvalid => s_axis_config_tvalid,
|
||||||
|
s_axis_config_tdata => s_axis_config_tdata,
|
||||||
|
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||||
|
m_axis_data_tdata => m_axis_data_tdata
|
||||||
|
);
|
||||||
|
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
-- You must compile the wrapper file dds_32b_8b.vhd when simulating
|
||||||
|
-- the core, dds_32b_8b. When compiling the wrapper file, be sure to
|
||||||
|
-- reference the VHDL simulation library.
|
||||||
|
|
||||||
+1481
File diff suppressed because it is too large
Load Diff
+1869
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,25 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
// Date : Fri Mar 17 22:22:40 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v
|
||||||
|
// Design : dds_32b_8b
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* x_core_info = "dds_compiler_v6_0_18,Vivado 2019.1.3" *)
|
||||||
|
module dds_32b_8b(aclk, s_axis_config_tvalid,
|
||||||
|
s_axis_config_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tvalid,s_axis_config_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
|
||||||
|
input aclk;
|
||||||
|
input s_axis_config_tvalid;
|
||||||
|
input [31:0]s_axis_config_tdata;
|
||||||
|
output m_axis_data_tvalid;
|
||||||
|
output [15:0]m_axis_data_tdata;
|
||||||
|
endmodule
|
||||||
+34
@@ -0,0 +1,34 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
-- Date : Fri Mar 17 22:22:40 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl
|
||||||
|
-- Design : dds_32b_8b
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity dds_32b_8b is
|
||||||
|
Port (
|
||||||
|
aclk : in STD_LOGIC;
|
||||||
|
s_axis_config_tvalid : in STD_LOGIC;
|
||||||
|
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||||
|
m_axis_data_tvalid : out STD_LOGIC;
|
||||||
|
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end dds_32b_8b;
|
||||||
|
|
||||||
|
architecture stub of dds_32b_8b is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_config_tvalid,s_axis_config_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
|
||||||
|
attribute x_core_info : string;
|
||||||
|
attribute x_core_info of stub : architecture is "dds_compiler_v6_0_18,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
+235
@@ -0,0 +1,235 @@
|
|||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- Description:
|
||||||
|
-- This is an example testbench for the DDS Compiler IP core.
|
||||||
|
-- The testbench has been generated by Vivado to accompany the IP core
|
||||||
|
-- instance you have generated.
|
||||||
|
--
|
||||||
|
-- This testbench is for demonstration purposes only. See note below for
|
||||||
|
-- instructions on how to use it with your core.
|
||||||
|
--
|
||||||
|
-- See the DDS Compiler product guide for further information
|
||||||
|
-- about this core.
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- Using this testbench
|
||||||
|
--
|
||||||
|
-- This testbench instantiates your generated DDS Compiler core
|
||||||
|
-- instance named "dds_32b_8b".
|
||||||
|
--
|
||||||
|
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||||
|
-- documentation for details.
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.numeric_std.all;
|
||||||
|
use ieee.math_real.all;
|
||||||
|
|
||||||
|
entity tb_dds_32b_8b is
|
||||||
|
end tb_dds_32b_8b;
|
||||||
|
|
||||||
|
architecture tb of tb_dds_32b_8b is
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Timing constants
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
constant CLOCK_PERIOD : time := 100 ns;
|
||||||
|
constant T_HOLD : time := 10 ns;
|
||||||
|
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- DUT input signals
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
-- General inputs
|
||||||
|
signal aclk : std_logic := '0'; -- the master clock
|
||||||
|
|
||||||
|
-- Config slave channel signals
|
||||||
|
signal s_axis_config_tvalid : std_logic := '0'; -- payload is valid
|
||||||
|
signal s_axis_config_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- data payload
|
||||||
|
|
||||||
|
-- Data master channel signals
|
||||||
|
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||||
|
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Aliases for AXI channel TDATA and TUSER fields
|
||||||
|
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||||
|
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||||
|
-- to prevent the simulator optimizing away these signals.
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
-- Config slave channel alias signals
|
||||||
|
signal s_axis_config_tdata_inc : std_logic_vector(31 downto 0) := (others => '0');
|
||||||
|
|
||||||
|
-- Data master channel alias signals
|
||||||
|
signal m_axis_data_tdata_cosine : std_logic_vector(7 downto 0) := (others => '0');
|
||||||
|
signal m_axis_data_tdata_sine : std_logic_vector(7 downto 0) := (others => '0');
|
||||||
|
|
||||||
|
|
||||||
|
signal end_of_simulation : boolean := false;
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Instantiate the DUT
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
dut : entity work.dds_32b_8b
|
||||||
|
port map (
|
||||||
|
aclk => aclk
|
||||||
|
,s_axis_config_tvalid => s_axis_config_tvalid
|
||||||
|
,s_axis_config_tdata => s_axis_config_tdata
|
||||||
|
,m_axis_data_tvalid => m_axis_data_tvalid
|
||||||
|
,m_axis_data_tdata => m_axis_data_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Generate clock
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
clock_gen : process
|
||||||
|
begin
|
||||||
|
aclk <= '0';
|
||||||
|
if (end_of_simulation) then
|
||||||
|
wait;
|
||||||
|
else
|
||||||
|
wait for CLOCK_PERIOD;
|
||||||
|
loop
|
||||||
|
aclk <= '0';
|
||||||
|
wait for CLOCK_PERIOD/2;
|
||||||
|
aclk <= '1';
|
||||||
|
wait for CLOCK_PERIOD/2;
|
||||||
|
end loop;
|
||||||
|
end if;
|
||||||
|
end process clock_gen;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Generate inputs
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
stimuli : process
|
||||||
|
begin
|
||||||
|
|
||||||
|
-- Drive inputs T_HOLD time after rising edge of clock
|
||||||
|
wait until rising_edge(aclk);
|
||||||
|
wait for T_HOLD;
|
||||||
|
|
||||||
|
-- Program the core with the initial configuration.
|
||||||
|
-- The phase increment value here is derived from the output frequency value set in the CORE Generator GUI.
|
||||||
|
s_axis_config_tvalid <= '1';
|
||||||
|
s_axis_config_tdata <= (others => '0'); -- set unused TDATA bits to zero
|
||||||
|
s_axis_config_tdata(31 downto 0) <= "00000000000000010101010101010101"; -- phase increment
|
||||||
|
wait for CLOCK_PERIOD;
|
||||||
|
s_axis_config_tvalid <= '0';
|
||||||
|
|
||||||
|
-- Run for long enough to produce 5 periods of outputs
|
||||||
|
wait for CLOCK_PERIOD * 245761;
|
||||||
|
|
||||||
|
-- Configure the core with a different configuration:
|
||||||
|
-- set phase increment to half of its current value
|
||||||
|
s_axis_config_tvalid <= '1';
|
||||||
|
s_axis_config_tdata <= (others => '0'); -- set unused TDATA bits to zero
|
||||||
|
s_axis_config_tdata(31 downto 0) <= "00000000000000001010101010101010"; -- current phase increment / 2
|
||||||
|
wait for CLOCK_PERIOD;
|
||||||
|
s_axis_config_tvalid <= '0';
|
||||||
|
|
||||||
|
-- Run for long enough to produce 5 periods of outputs
|
||||||
|
wait for CLOCK_PERIOD * 491522;
|
||||||
|
|
||||||
|
-- End of test
|
||||||
|
end_of_simulation <= true;
|
||||||
|
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||||
|
wait;
|
||||||
|
|
||||||
|
end process stimuli;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Check outputs
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
check_outputs : process
|
||||||
|
variable check_ok : boolean := true;
|
||||||
|
begin
|
||||||
|
|
||||||
|
-- Check outputs T_STROBE time after rising edge of clock
|
||||||
|
wait until rising_edge(aclk);
|
||||||
|
wait for T_STROBE;
|
||||||
|
|
||||||
|
-- Do not check the output payload values, as this requires the behavioral model
|
||||||
|
-- which would make this demonstration testbench unwieldy.
|
||||||
|
-- Instead, check the protocol of the data master channel:
|
||||||
|
-- check that the payload is valid (not X) when TVALID is high
|
||||||
|
|
||||||
|
if m_axis_data_tvalid = '1' then
|
||||||
|
if is_x(m_axis_data_tdata) then
|
||||||
|
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
|
||||||
|
check_ok := false;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
|
||||||
|
assert check_ok
|
||||||
|
report "ERROR: terminating test with failures." severity failure;
|
||||||
|
|
||||||
|
end process check_outputs;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
-- Config slave channel alias signals
|
||||||
|
s_axis_config_tdata_inc <= s_axis_config_tdata(31 downto 0);
|
||||||
|
|
||||||
|
-- Data master channel alias signals: update these only when they are valid
|
||||||
|
m_axis_data_tdata_cosine <= m_axis_data_tdata(7 downto 0) when m_axis_data_tvalid = '1';
|
||||||
|
m_axis_data_tdata_sine <= m_axis_data_tdata(15 downto 8) when m_axis_data_tvalid = '1';
|
||||||
|
|
||||||
|
end tb;
|
||||||
|
|
||||||
@@ -0,0 +1,232 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
|
||||||
|
-- IP Revision: 18
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
LIBRARY dds_compiler_v6_0_18;
|
||||||
|
USE dds_compiler_v6_0_18.dds_compiler_v6_0_18;
|
||||||
|
|
||||||
|
ENTITY dds_32b_8b IS
|
||||||
|
PORT (
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
s_axis_config_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_config_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||||
|
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END dds_32b_8b;
|
||||||
|
|
||||||
|
ARCHITECTURE dds_32b_8b_arch OF dds_32b_8b IS
|
||||||
|
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||||
|
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dds_32b_8b_arch: ARCHITECTURE IS "yes";
|
||||||
|
COMPONENT dds_compiler_v6_0_18 IS
|
||||||
|
GENERIC (
|
||||||
|
C_XDEVICEFAMILY : STRING;
|
||||||
|
C_MODE_OF_OPERATION : INTEGER;
|
||||||
|
C_MODULUS : INTEGER;
|
||||||
|
C_ACCUMULATOR_WIDTH : INTEGER;
|
||||||
|
C_CHANNELS : INTEGER;
|
||||||
|
C_HAS_PHASE_OUT : INTEGER;
|
||||||
|
C_HAS_PHASEGEN : INTEGER;
|
||||||
|
C_HAS_SINCOS : INTEGER;
|
||||||
|
C_LATENCY : INTEGER;
|
||||||
|
C_MEM_TYPE : INTEGER;
|
||||||
|
C_NEGATIVE_COSINE : INTEGER;
|
||||||
|
C_NEGATIVE_SINE : INTEGER;
|
||||||
|
C_NOISE_SHAPING : INTEGER;
|
||||||
|
C_OUTPUTS_REQUIRED : INTEGER;
|
||||||
|
C_OUTPUT_FORM : INTEGER;
|
||||||
|
C_OUTPUT_WIDTH : INTEGER;
|
||||||
|
C_PHASE_ANGLE_WIDTH : INTEGER;
|
||||||
|
C_PHASE_INCREMENT : INTEGER;
|
||||||
|
C_PHASE_INCREMENT_VALUE : STRING;
|
||||||
|
C_RESYNC : INTEGER;
|
||||||
|
C_PHASE_OFFSET : INTEGER;
|
||||||
|
C_PHASE_OFFSET_VALUE : STRING;
|
||||||
|
C_OPTIMISE_GOAL : INTEGER;
|
||||||
|
C_USE_DSP48 : INTEGER;
|
||||||
|
C_POR_MODE : INTEGER;
|
||||||
|
C_AMPLITUDE : INTEGER;
|
||||||
|
C_HAS_ACLKEN : INTEGER;
|
||||||
|
C_HAS_ARESETN : INTEGER;
|
||||||
|
C_HAS_TLAST : INTEGER;
|
||||||
|
C_HAS_TREADY : INTEGER;
|
||||||
|
C_HAS_S_PHASE : INTEGER;
|
||||||
|
C_S_PHASE_TDATA_WIDTH : INTEGER;
|
||||||
|
C_S_PHASE_HAS_TUSER : INTEGER;
|
||||||
|
C_S_PHASE_TUSER_WIDTH : INTEGER;
|
||||||
|
C_HAS_S_CONFIG : INTEGER;
|
||||||
|
C_S_CONFIG_SYNC_MODE : INTEGER;
|
||||||
|
C_S_CONFIG_TDATA_WIDTH : INTEGER;
|
||||||
|
C_HAS_M_DATA : INTEGER;
|
||||||
|
C_M_DATA_TDATA_WIDTH : INTEGER;
|
||||||
|
C_M_DATA_HAS_TUSER : INTEGER;
|
||||||
|
C_M_DATA_TUSER_WIDTH : INTEGER;
|
||||||
|
C_HAS_M_PHASE : INTEGER;
|
||||||
|
C_M_PHASE_TDATA_WIDTH : INTEGER;
|
||||||
|
C_M_PHASE_HAS_TUSER : INTEGER;
|
||||||
|
C_M_PHASE_TUSER_WIDTH : INTEGER;
|
||||||
|
C_DEBUG_INTERFACE : INTEGER;
|
||||||
|
C_CHAN_WIDTH : INTEGER
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
aclken : IN STD_LOGIC;
|
||||||
|
aresetn : IN STD_LOGIC;
|
||||||
|
s_axis_phase_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_phase_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
s_axis_phase_tlast : IN STD_LOGIC;
|
||||||
|
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
s_axis_config_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_config_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_config_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||||
|
s_axis_config_tlast : IN STD_LOGIC;
|
||||||
|
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_data_tready : IN STD_LOGIC;
|
||||||
|
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||||
|
m_axis_data_tlast : OUT STD_LOGIC;
|
||||||
|
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
m_axis_phase_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_phase_tready : IN STD_LOGIC;
|
||||||
|
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
m_axis_phase_tlast : OUT STD_LOGIC;
|
||||||
|
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
event_pinc_invalid : OUT STD_LOGIC;
|
||||||
|
event_poff_invalid : OUT STD_LOGIC;
|
||||||
|
event_phase_in_invalid : OUT STD_LOGIC;
|
||||||
|
event_s_phase_tlast_missing : OUT STD_LOGIC;
|
||||||
|
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
|
||||||
|
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
|
||||||
|
event_s_config_tlast_missing : OUT STD_LOGIC;
|
||||||
|
event_s_config_tlast_unexpected : OUT STD_LOGIC
|
||||||
|
);
|
||||||
|
END COMPONENT dds_compiler_v6_0_18;
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TDATA";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_config_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_CONFIG, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TVALID";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||||
|
BEGIN
|
||||||
|
U0 : dds_compiler_v6_0_18
|
||||||
|
GENERIC MAP (
|
||||||
|
C_XDEVICEFAMILY => "zynq",
|
||||||
|
C_MODE_OF_OPERATION => 0,
|
||||||
|
C_MODULUS => 9,
|
||||||
|
C_ACCUMULATOR_WIDTH => 32,
|
||||||
|
C_CHANNELS => 1,
|
||||||
|
C_HAS_PHASE_OUT => 0,
|
||||||
|
C_HAS_PHASEGEN => 1,
|
||||||
|
C_HAS_SINCOS => 1,
|
||||||
|
C_LATENCY => 3,
|
||||||
|
C_MEM_TYPE => 1,
|
||||||
|
C_NEGATIVE_COSINE => 0,
|
||||||
|
C_NEGATIVE_SINE => 0,
|
||||||
|
C_NOISE_SHAPING => 0,
|
||||||
|
C_OUTPUTS_REQUIRED => 2,
|
||||||
|
C_OUTPUT_FORM => 0,
|
||||||
|
C_OUTPUT_WIDTH => 8,
|
||||||
|
C_PHASE_ANGLE_WIDTH => 8,
|
||||||
|
C_PHASE_INCREMENT => 1,
|
||||||
|
C_PHASE_INCREMENT_VALUE => "10101010101010101,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
|
||||||
|
C_RESYNC => 0,
|
||||||
|
C_PHASE_OFFSET => 0,
|
||||||
|
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
|
||||||
|
C_OPTIMISE_GOAL => 0,
|
||||||
|
C_USE_DSP48 => 0,
|
||||||
|
C_POR_MODE => 0,
|
||||||
|
C_AMPLITUDE => 0,
|
||||||
|
C_HAS_ACLKEN => 0,
|
||||||
|
C_HAS_ARESETN => 0,
|
||||||
|
C_HAS_TLAST => 0,
|
||||||
|
C_HAS_TREADY => 0,
|
||||||
|
C_HAS_S_PHASE => 0,
|
||||||
|
C_S_PHASE_TDATA_WIDTH => 1,
|
||||||
|
C_S_PHASE_HAS_TUSER => 0,
|
||||||
|
C_S_PHASE_TUSER_WIDTH => 1,
|
||||||
|
C_HAS_S_CONFIG => 1,
|
||||||
|
C_S_CONFIG_SYNC_MODE => 0,
|
||||||
|
C_S_CONFIG_TDATA_WIDTH => 32,
|
||||||
|
C_HAS_M_DATA => 1,
|
||||||
|
C_M_DATA_TDATA_WIDTH => 16,
|
||||||
|
C_M_DATA_HAS_TUSER => 0,
|
||||||
|
C_M_DATA_TUSER_WIDTH => 1,
|
||||||
|
C_HAS_M_PHASE => 0,
|
||||||
|
C_M_PHASE_TDATA_WIDTH => 1,
|
||||||
|
C_M_PHASE_HAS_TUSER => 0,
|
||||||
|
C_M_PHASE_TUSER_WIDTH => 1,
|
||||||
|
C_DEBUG_INTERFACE => 0,
|
||||||
|
C_CHAN_WIDTH => 1
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
aclk => aclk,
|
||||||
|
aclken => '1',
|
||||||
|
aresetn => '1',
|
||||||
|
s_axis_phase_tvalid => '0',
|
||||||
|
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
s_axis_phase_tlast => '0',
|
||||||
|
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
s_axis_config_tvalid => s_axis_config_tvalid,
|
||||||
|
s_axis_config_tdata => s_axis_config_tdata,
|
||||||
|
s_axis_config_tlast => '0',
|
||||||
|
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||||
|
m_axis_data_tready => '0',
|
||||||
|
m_axis_data_tdata => m_axis_data_tdata,
|
||||||
|
m_axis_phase_tready => '0'
|
||||||
|
);
|
||||||
|
END dds_32b_8b_arch;
|
||||||
+75
@@ -0,0 +1,75 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||||
|
// IP Revision: 4
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
fifo_48m_to_122p88m your_instance_name (
|
||||||
|
.wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy
|
||||||
|
.rd_rst_busy(rd_rst_busy), // output wire rd_rst_busy
|
||||||
|
.m_aclk(m_aclk), // input wire m_aclk
|
||||||
|
.s_aclk(s_aclk), // input wire s_aclk
|
||||||
|
.s_aresetn(s_aresetn), // input wire s_aresetn
|
||||||
|
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
|
||||||
|
.s_axis_tready(s_axis_tready), // output wire s_axis_tready
|
||||||
|
.s_axis_tdata(s_axis_tdata), // input wire [15 : 0] s_axis_tdata
|
||||||
|
.m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid
|
||||||
|
.m_axis_tready(m_axis_tready), // input wire m_axis_tready
|
||||||
|
.m_axis_tdata(m_axis_tdata) // output wire [15 : 0] m_axis_tdata
|
||||||
|
);
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
// You must compile the wrapper file fifo_48m_to_122p88m.v when simulating
|
||||||
|
// the core, fifo_48m_to_122p88m. When compiling the wrapper file, be sure to
|
||||||
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
+95
@@ -0,0 +1,95 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||||
|
-- IP Revision: 4
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture header.
|
||||||
|
|
||||||
|
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||||
|
COMPONENT fifo_48m_to_122p88m
|
||||||
|
PORT (
|
||||||
|
wr_rst_busy : OUT STD_LOGIC;
|
||||||
|
rd_rst_busy : OUT STD_LOGIC;
|
||||||
|
m_aclk : IN STD_LOGIC;
|
||||||
|
s_aclk : IN STD_LOGIC;
|
||||||
|
s_aresetn : IN STD_LOGIC;
|
||||||
|
s_axis_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||||
|
m_axis_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_tready : IN STD_LOGIC;
|
||||||
|
m_axis_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture
|
||||||
|
-- body. Substitute your own instance name and net names.
|
||||||
|
|
||||||
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||||
|
your_instance_name : fifo_48m_to_122p88m
|
||||||
|
PORT MAP (
|
||||||
|
wr_rst_busy => wr_rst_busy,
|
||||||
|
rd_rst_busy => rd_rst_busy,
|
||||||
|
m_aclk => m_aclk,
|
||||||
|
s_aclk => s_aclk,
|
||||||
|
s_aresetn => s_aresetn,
|
||||||
|
s_axis_tvalid => s_axis_tvalid,
|
||||||
|
s_axis_tready => s_axis_tready,
|
||||||
|
s_axis_tdata => s_axis_tdata,
|
||||||
|
m_axis_tvalid => m_axis_tvalid,
|
||||||
|
m_axis_tready => m_axis_tready,
|
||||||
|
m_axis_tdata => m_axis_tdata
|
||||||
|
);
|
||||||
|
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
-- You must compile the wrapper file fifo_48m_to_122p88m.vhd when simulating
|
||||||
|
-- the core, fifo_48m_to_122p88m. When compiling the wrapper file, be sure to
|
||||||
|
-- reference the VHDL simulation library.
|
||||||
|
|
||||||
+4024
File diff suppressed because it is too large
Load Diff
+4868
File diff suppressed because it is too large
Load Diff
+32
@@ -0,0 +1,32 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
// Date : Tue Mar 21 16:19:06 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// d:/vivado-git/projects/datalink_814/dl814_dj_48m/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_stub.v
|
||||||
|
// Design : fifo_48m_to_122p88m
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *)
|
||||||
|
module fifo_48m_to_122p88m(wr_rst_busy, rd_rst_busy, m_aclk, s_aclk,
|
||||||
|
s_aresetn, s_axis_tvalid, s_axis_tready, s_axis_tdata, m_axis_tvalid, m_axis_tready,
|
||||||
|
m_axis_tdata)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="wr_rst_busy,rd_rst_busy,m_aclk,s_aclk,s_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[15:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[15:0]" */;
|
||||||
|
output wr_rst_busy;
|
||||||
|
output rd_rst_busy;
|
||||||
|
input m_aclk;
|
||||||
|
input s_aclk;
|
||||||
|
input s_aresetn;
|
||||||
|
input s_axis_tvalid;
|
||||||
|
output s_axis_tready;
|
||||||
|
input [15:0]s_axis_tdata;
|
||||||
|
output m_axis_tvalid;
|
||||||
|
input m_axis_tready;
|
||||||
|
output [15:0]m_axis_tdata;
|
||||||
|
endmodule
|
||||||
+40
@@ -0,0 +1,40 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
-- Date : Tue Mar 21 16:19:06 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- d:/vivado-git/projects/datalink_814/dl814_dj_48m/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_stub.vhdl
|
||||||
|
-- Design : fifo_48m_to_122p88m
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity fifo_48m_to_122p88m is
|
||||||
|
Port (
|
||||||
|
wr_rst_busy : out STD_LOGIC;
|
||||||
|
rd_rst_busy : out STD_LOGIC;
|
||||||
|
m_aclk : in STD_LOGIC;
|
||||||
|
s_aclk : in STD_LOGIC;
|
||||||
|
s_aresetn : in STD_LOGIC;
|
||||||
|
s_axis_tvalid : in STD_LOGIC;
|
||||||
|
s_axis_tready : out STD_LOGIC;
|
||||||
|
s_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
m_axis_tvalid : out STD_LOGIC;
|
||||||
|
m_axis_tready : in STD_LOGIC;
|
||||||
|
m_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end fifo_48m_to_122p88m;
|
||||||
|
|
||||||
|
architecture stub of fifo_48m_to_122p88m is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "wr_rst_busy,rd_rst_busy,m_aclk,s_aclk,s_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[15:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[15:0]";
|
||||||
|
attribute x_core_info : string;
|
||||||
|
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
+532
@@ -0,0 +1,532 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||||
|
// IP Revision: 4
|
||||||
|
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module fifo_48m_to_122p88m (
|
||||||
|
wr_rst_busy,
|
||||||
|
rd_rst_busy,
|
||||||
|
m_aclk,
|
||||||
|
s_aclk,
|
||||||
|
s_aresetn,
|
||||||
|
s_axis_tvalid,
|
||||||
|
s_axis_tready,
|
||||||
|
s_axis_tdata,
|
||||||
|
m_axis_tvalid,
|
||||||
|
m_axis_tready,
|
||||||
|
m_axis_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
output wire wr_rst_busy;
|
||||||
|
output wire rd_rst_busy;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME master_aclk, ASSOCIATED_BUSIF M_AXIS:M_AXI, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 master_aclk CLK" *)
|
||||||
|
input wire m_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slave_aclk, ASSOCIATED_BUSIF S_AXIS:S_AXI, ASSOCIATED_RESET s_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 slave_aclk CLK" *)
|
||||||
|
input wire s_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slave_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 slave_aresetn RST" *)
|
||||||
|
input wire s_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
|
||||||
|
input wire s_axis_tvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
|
||||||
|
output wire s_axis_tready;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
|
||||||
|
input wire [15 : 0] s_axis_tdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
|
||||||
|
output wire m_axis_tvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
|
||||||
|
input wire m_axis_tready;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
|
||||||
|
output wire [15 : 0] m_axis_tdata;
|
||||||
|
|
||||||
|
fifo_generator_v13_2_4 #(
|
||||||
|
.C_COMMON_CLOCK(0),
|
||||||
|
.C_SELECT_XPM(0),
|
||||||
|
.C_COUNT_TYPE(0),
|
||||||
|
.C_DATA_COUNT_WIDTH(10),
|
||||||
|
.C_DEFAULT_VALUE("BlankString"),
|
||||||
|
.C_DIN_WIDTH(18),
|
||||||
|
.C_DOUT_RST_VAL("0"),
|
||||||
|
.C_DOUT_WIDTH(18),
|
||||||
|
.C_ENABLE_RLOCS(0),
|
||||||
|
.C_FAMILY("zynq"),
|
||||||
|
.C_FULL_FLAGS_RST_VAL(1),
|
||||||
|
.C_HAS_ALMOST_EMPTY(0),
|
||||||
|
.C_HAS_ALMOST_FULL(0),
|
||||||
|
.C_HAS_BACKUP(0),
|
||||||
|
.C_HAS_DATA_COUNT(0),
|
||||||
|
.C_HAS_INT_CLK(0),
|
||||||
|
.C_HAS_MEMINIT_FILE(0),
|
||||||
|
.C_HAS_OVERFLOW(0),
|
||||||
|
.C_HAS_RD_DATA_COUNT(0),
|
||||||
|
.C_HAS_RD_RST(0),
|
||||||
|
.C_HAS_RST(1),
|
||||||
|
.C_HAS_SRST(0),
|
||||||
|
.C_HAS_UNDERFLOW(0),
|
||||||
|
.C_HAS_VALID(0),
|
||||||
|
.C_HAS_WR_ACK(0),
|
||||||
|
.C_HAS_WR_DATA_COUNT(0),
|
||||||
|
.C_HAS_WR_RST(0),
|
||||||
|
.C_IMPLEMENTATION_TYPE(0),
|
||||||
|
.C_INIT_WR_PNTR_VAL(0),
|
||||||
|
.C_MEMORY_TYPE(1),
|
||||||
|
.C_MIF_FILE_NAME("BlankString"),
|
||||||
|
.C_OPTIMIZATION_MODE(0),
|
||||||
|
.C_OVERFLOW_LOW(0),
|
||||||
|
.C_PRELOAD_LATENCY(1),
|
||||||
|
.C_PRELOAD_REGS(0),
|
||||||
|
.C_PRIM_FIFO_TYPE("4kx4"),
|
||||||
|
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
|
||||||
|
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
|
||||||
|
.C_PROG_EMPTY_TYPE(0),
|
||||||
|
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
|
||||||
|
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
|
||||||
|
.C_PROG_FULL_TYPE(0),
|
||||||
|
.C_RD_DATA_COUNT_WIDTH(10),
|
||||||
|
.C_RD_DEPTH(1024),
|
||||||
|
.C_RD_FREQ(1),
|
||||||
|
.C_RD_PNTR_WIDTH(10),
|
||||||
|
.C_UNDERFLOW_LOW(0),
|
||||||
|
.C_USE_DOUT_RST(1),
|
||||||
|
.C_USE_ECC(0),
|
||||||
|
.C_USE_EMBEDDED_REG(0),
|
||||||
|
.C_USE_PIPELINE_REG(0),
|
||||||
|
.C_POWER_SAVING_MODE(0),
|
||||||
|
.C_USE_FIFO16_FLAGS(0),
|
||||||
|
.C_USE_FWFT_DATA_COUNT(0),
|
||||||
|
.C_VALID_LOW(0),
|
||||||
|
.C_WR_ACK_LOW(0),
|
||||||
|
.C_WR_DATA_COUNT_WIDTH(10),
|
||||||
|
.C_WR_DEPTH(1024),
|
||||||
|
.C_WR_FREQ(1),
|
||||||
|
.C_WR_PNTR_WIDTH(10),
|
||||||
|
.C_WR_RESPONSE_LATENCY(1),
|
||||||
|
.C_MSGON_VAL(1),
|
||||||
|
.C_ENABLE_RST_SYNC(1),
|
||||||
|
.C_EN_SAFETY_CKT(1),
|
||||||
|
.C_ERROR_INJECTION_TYPE(0),
|
||||||
|
.C_SYNCHRONIZER_STAGE(2),
|
||||||
|
.C_INTERFACE_TYPE(1),
|
||||||
|
.C_AXI_TYPE(1),
|
||||||
|
.C_HAS_AXI_WR_CHANNEL(1),
|
||||||
|
.C_HAS_AXI_RD_CHANNEL(1),
|
||||||
|
.C_HAS_SLAVE_CE(0),
|
||||||
|
.C_HAS_MASTER_CE(0),
|
||||||
|
.C_ADD_NGC_CONSTRAINT(0),
|
||||||
|
.C_USE_COMMON_OVERFLOW(0),
|
||||||
|
.C_USE_COMMON_UNDERFLOW(0),
|
||||||
|
.C_USE_DEFAULT_SETTINGS(0),
|
||||||
|
.C_AXI_ID_WIDTH(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(32),
|
||||||
|
.C_AXI_DATA_WIDTH(64),
|
||||||
|
.C_AXI_LEN_WIDTH(8),
|
||||||
|
.C_AXI_LOCK_WIDTH(1),
|
||||||
|
.C_HAS_AXI_ID(0),
|
||||||
|
.C_HAS_AXI_AWUSER(0),
|
||||||
|
.C_HAS_AXI_WUSER(0),
|
||||||
|
.C_HAS_AXI_BUSER(0),
|
||||||
|
.C_HAS_AXI_ARUSER(0),
|
||||||
|
.C_HAS_AXI_RUSER(0),
|
||||||
|
.C_AXI_ARUSER_WIDTH(1),
|
||||||
|
.C_AXI_AWUSER_WIDTH(1),
|
||||||
|
.C_AXI_WUSER_WIDTH(1),
|
||||||
|
.C_AXI_BUSER_WIDTH(1),
|
||||||
|
.C_AXI_RUSER_WIDTH(1),
|
||||||
|
.C_HAS_AXIS_TDATA(1),
|
||||||
|
.C_HAS_AXIS_TID(0),
|
||||||
|
.C_HAS_AXIS_TDEST(0),
|
||||||
|
.C_HAS_AXIS_TUSER(0),
|
||||||
|
.C_HAS_AXIS_TREADY(1),
|
||||||
|
.C_HAS_AXIS_TLAST(0),
|
||||||
|
.C_HAS_AXIS_TSTRB(0),
|
||||||
|
.C_HAS_AXIS_TKEEP(0),
|
||||||
|
.C_AXIS_TDATA_WIDTH(16),
|
||||||
|
.C_AXIS_TID_WIDTH(1),
|
||||||
|
.C_AXIS_TDEST_WIDTH(1),
|
||||||
|
.C_AXIS_TUSER_WIDTH(1),
|
||||||
|
.C_AXIS_TSTRB_WIDTH(2),
|
||||||
|
.C_AXIS_TKEEP_WIDTH(2),
|
||||||
|
.C_WACH_TYPE(0),
|
||||||
|
.C_WDCH_TYPE(0),
|
||||||
|
.C_WRCH_TYPE(0),
|
||||||
|
.C_RACH_TYPE(0),
|
||||||
|
.C_RDCH_TYPE(0),
|
||||||
|
.C_AXIS_TYPE(0),
|
||||||
|
.C_IMPLEMENTATION_TYPE_WACH(12),
|
||||||
|
.C_IMPLEMENTATION_TYPE_WDCH(11),
|
||||||
|
.C_IMPLEMENTATION_TYPE_WRCH(12),
|
||||||
|
.C_IMPLEMENTATION_TYPE_RACH(12),
|
||||||
|
.C_IMPLEMENTATION_TYPE_RDCH(11),
|
||||||
|
.C_IMPLEMENTATION_TYPE_AXIS(12),
|
||||||
|
.C_APPLICATION_TYPE_WACH(0),
|
||||||
|
.C_APPLICATION_TYPE_WDCH(0),
|
||||||
|
.C_APPLICATION_TYPE_WRCH(0),
|
||||||
|
.C_APPLICATION_TYPE_RACH(0),
|
||||||
|
.C_APPLICATION_TYPE_RDCH(0),
|
||||||
|
.C_APPLICATION_TYPE_AXIS(0),
|
||||||
|
.C_PRIM_FIFO_TYPE_WACH("512x36"),
|
||||||
|
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
|
||||||
|
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
|
||||||
|
.C_PRIM_FIFO_TYPE_RACH("512x36"),
|
||||||
|
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
|
||||||
|
.C_PRIM_FIFO_TYPE_AXIS("512x36"),
|
||||||
|
.C_USE_ECC_WACH(0),
|
||||||
|
.C_USE_ECC_WDCH(0),
|
||||||
|
.C_USE_ECC_WRCH(0),
|
||||||
|
.C_USE_ECC_RACH(0),
|
||||||
|
.C_USE_ECC_RDCH(0),
|
||||||
|
.C_USE_ECC_AXIS(0),
|
||||||
|
.C_ERROR_INJECTION_TYPE_WACH(0),
|
||||||
|
.C_ERROR_INJECTION_TYPE_WDCH(0),
|
||||||
|
.C_ERROR_INJECTION_TYPE_WRCH(0),
|
||||||
|
.C_ERROR_INJECTION_TYPE_RACH(0),
|
||||||
|
.C_ERROR_INJECTION_TYPE_RDCH(0),
|
||||||
|
.C_ERROR_INJECTION_TYPE_AXIS(0),
|
||||||
|
.C_DIN_WIDTH_WACH(32),
|
||||||
|
.C_DIN_WIDTH_WDCH(64),
|
||||||
|
.C_DIN_WIDTH_WRCH(2),
|
||||||
|
.C_DIN_WIDTH_RACH(32),
|
||||||
|
.C_DIN_WIDTH_RDCH(64),
|
||||||
|
.C_DIN_WIDTH_AXIS(16),
|
||||||
|
.C_WR_DEPTH_WACH(16),
|
||||||
|
.C_WR_DEPTH_WDCH(1024),
|
||||||
|
.C_WR_DEPTH_WRCH(16),
|
||||||
|
.C_WR_DEPTH_RACH(16),
|
||||||
|
.C_WR_DEPTH_RDCH(1024),
|
||||||
|
.C_WR_DEPTH_AXIS(16),
|
||||||
|
.C_WR_PNTR_WIDTH_WACH(4),
|
||||||
|
.C_WR_PNTR_WIDTH_WDCH(10),
|
||||||
|
.C_WR_PNTR_WIDTH_WRCH(4),
|
||||||
|
.C_WR_PNTR_WIDTH_RACH(4),
|
||||||
|
.C_WR_PNTR_WIDTH_RDCH(10),
|
||||||
|
.C_WR_PNTR_WIDTH_AXIS(4),
|
||||||
|
.C_HAS_DATA_COUNTS_WACH(0),
|
||||||
|
.C_HAS_DATA_COUNTS_WDCH(0),
|
||||||
|
.C_HAS_DATA_COUNTS_WRCH(0),
|
||||||
|
.C_HAS_DATA_COUNTS_RACH(0),
|
||||||
|
.C_HAS_DATA_COUNTS_RDCH(0),
|
||||||
|
.C_HAS_DATA_COUNTS_AXIS(0),
|
||||||
|
.C_HAS_PROG_FLAGS_WACH(0),
|
||||||
|
.C_HAS_PROG_FLAGS_WDCH(0),
|
||||||
|
.C_HAS_PROG_FLAGS_WRCH(0),
|
||||||
|
.C_HAS_PROG_FLAGS_RACH(0),
|
||||||
|
.C_HAS_PROG_FLAGS_RDCH(0),
|
||||||
|
.C_HAS_PROG_FLAGS_AXIS(0),
|
||||||
|
.C_PROG_FULL_TYPE_WACH(0),
|
||||||
|
.C_PROG_FULL_TYPE_WDCH(0),
|
||||||
|
.C_PROG_FULL_TYPE_WRCH(0),
|
||||||
|
.C_PROG_FULL_TYPE_RACH(0),
|
||||||
|
.C_PROG_FULL_TYPE_RDCH(0),
|
||||||
|
.C_PROG_FULL_TYPE_AXIS(0),
|
||||||
|
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),
|
||||||
|
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
|
||||||
|
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
|
||||||
|
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
|
||||||
|
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
|
||||||
|
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(15),
|
||||||
|
.C_PROG_EMPTY_TYPE_WACH(0),
|
||||||
|
.C_PROG_EMPTY_TYPE_WDCH(0),
|
||||||
|
.C_PROG_EMPTY_TYPE_WRCH(0),
|
||||||
|
.C_PROG_EMPTY_TYPE_RACH(0),
|
||||||
|
.C_PROG_EMPTY_TYPE_RDCH(0),
|
||||||
|
.C_PROG_EMPTY_TYPE_AXIS(0),
|
||||||
|
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),
|
||||||
|
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1021),
|
||||||
|
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),
|
||||||
|
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),
|
||||||
|
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1021),
|
||||||
|
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(13),
|
||||||
|
.C_REG_SLICE_MODE_WACH(0),
|
||||||
|
.C_REG_SLICE_MODE_WDCH(0),
|
||||||
|
.C_REG_SLICE_MODE_WRCH(0),
|
||||||
|
.C_REG_SLICE_MODE_RACH(0),
|
||||||
|
.C_REG_SLICE_MODE_RDCH(0),
|
||||||
|
.C_REG_SLICE_MODE_AXIS(0)
|
||||||
|
) inst (
|
||||||
|
.backup(1'D0),
|
||||||
|
.backup_marker(1'D0),
|
||||||
|
.clk(1'D0),
|
||||||
|
.rst(1'D0),
|
||||||
|
.srst(1'D0),
|
||||||
|
.wr_clk(1'D0),
|
||||||
|
.wr_rst(1'D0),
|
||||||
|
.rd_clk(1'D0),
|
||||||
|
.rd_rst(1'D0),
|
||||||
|
.din(18'B0),
|
||||||
|
.wr_en(1'D0),
|
||||||
|
.rd_en(1'D0),
|
||||||
|
.prog_empty_thresh(10'B0),
|
||||||
|
.prog_empty_thresh_assert(10'B0),
|
||||||
|
.prog_empty_thresh_negate(10'B0),
|
||||||
|
.prog_full_thresh(10'B0),
|
||||||
|
.prog_full_thresh_assert(10'B0),
|
||||||
|
.prog_full_thresh_negate(10'B0),
|
||||||
|
.int_clk(1'D0),
|
||||||
|
.injectdbiterr(1'D0),
|
||||||
|
.injectsbiterr(1'D0),
|
||||||
|
.sleep(1'D0),
|
||||||
|
.dout(),
|
||||||
|
.full(),
|
||||||
|
.almost_full(),
|
||||||
|
.wr_ack(),
|
||||||
|
.overflow(),
|
||||||
|
.empty(),
|
||||||
|
.almost_empty(),
|
||||||
|
.valid(),
|
||||||
|
.underflow(),
|
||||||
|
.data_count(),
|
||||||
|
.rd_data_count(),
|
||||||
|
.wr_data_count(),
|
||||||
|
.prog_full(),
|
||||||
|
.prog_empty(),
|
||||||
|
.sbiterr(),
|
||||||
|
.dbiterr(),
|
||||||
|
.wr_rst_busy(wr_rst_busy),
|
||||||
|
.rd_rst_busy(rd_rst_busy),
|
||||||
|
.m_aclk(m_aclk),
|
||||||
|
.s_aclk(s_aclk),
|
||||||
|
.s_aresetn(s_aresetn),
|
||||||
|
.m_aclk_en(1'D0),
|
||||||
|
.s_aclk_en(1'D0),
|
||||||
|
.s_axi_awid(1'B0),
|
||||||
|
.s_axi_awaddr(32'B0),
|
||||||
|
.s_axi_awlen(8'B0),
|
||||||
|
.s_axi_awsize(3'B0),
|
||||||
|
.s_axi_awburst(2'B0),
|
||||||
|
.s_axi_awlock(1'B0),
|
||||||
|
.s_axi_awcache(4'B0),
|
||||||
|
.s_axi_awprot(3'B0),
|
||||||
|
.s_axi_awqos(4'B0),
|
||||||
|
.s_axi_awregion(4'B0),
|
||||||
|
.s_axi_awuser(1'B0),
|
||||||
|
.s_axi_awvalid(1'D0),
|
||||||
|
.s_axi_awready(),
|
||||||
|
.s_axi_wid(1'B0),
|
||||||
|
.s_axi_wdata(64'B0),
|
||||||
|
.s_axi_wstrb(8'B0),
|
||||||
|
.s_axi_wlast(1'D0),
|
||||||
|
.s_axi_wuser(1'B0),
|
||||||
|
.s_axi_wvalid(1'D0),
|
||||||
|
.s_axi_wready(),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(),
|
||||||
|
.s_axi_buser(),
|
||||||
|
.s_axi_bvalid(),
|
||||||
|
.s_axi_bready(1'D0),
|
||||||
|
.m_axi_awid(),
|
||||||
|
.m_axi_awaddr(),
|
||||||
|
.m_axi_awlen(),
|
||||||
|
.m_axi_awsize(),
|
||||||
|
.m_axi_awburst(),
|
||||||
|
.m_axi_awlock(),
|
||||||
|
.m_axi_awcache(),
|
||||||
|
.m_axi_awprot(),
|
||||||
|
.m_axi_awqos(),
|
||||||
|
.m_axi_awregion(),
|
||||||
|
.m_axi_awuser(),
|
||||||
|
.m_axi_awvalid(),
|
||||||
|
.m_axi_awready(1'D0),
|
||||||
|
.m_axi_wid(),
|
||||||
|
.m_axi_wdata(),
|
||||||
|
.m_axi_wstrb(),
|
||||||
|
.m_axi_wlast(),
|
||||||
|
.m_axi_wuser(),
|
||||||
|
.m_axi_wvalid(),
|
||||||
|
.m_axi_wready(1'D0),
|
||||||
|
.m_axi_bid(1'B0),
|
||||||
|
.m_axi_bresp(2'B0),
|
||||||
|
.m_axi_buser(1'B0),
|
||||||
|
.m_axi_bvalid(1'D0),
|
||||||
|
.m_axi_bready(),
|
||||||
|
.s_axi_arid(1'B0),
|
||||||
|
.s_axi_araddr(32'B0),
|
||||||
|
.s_axi_arlen(8'B0),
|
||||||
|
.s_axi_arsize(3'B0),
|
||||||
|
.s_axi_arburst(2'B0),
|
||||||
|
.s_axi_arlock(1'B0),
|
||||||
|
.s_axi_arcache(4'B0),
|
||||||
|
.s_axi_arprot(3'B0),
|
||||||
|
.s_axi_arqos(4'B0),
|
||||||
|
.s_axi_arregion(4'B0),
|
||||||
|
.s_axi_aruser(1'B0),
|
||||||
|
.s_axi_arvalid(1'D0),
|
||||||
|
.s_axi_arready(),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(),
|
||||||
|
.s_axi_rresp(),
|
||||||
|
.s_axi_rlast(),
|
||||||
|
.s_axi_ruser(),
|
||||||
|
.s_axi_rvalid(),
|
||||||
|
.s_axi_rready(1'D0),
|
||||||
|
.m_axi_arid(),
|
||||||
|
.m_axi_araddr(),
|
||||||
|
.m_axi_arlen(),
|
||||||
|
.m_axi_arsize(),
|
||||||
|
.m_axi_arburst(),
|
||||||
|
.m_axi_arlock(),
|
||||||
|
.m_axi_arcache(),
|
||||||
|
.m_axi_arprot(),
|
||||||
|
.m_axi_arqos(),
|
||||||
|
.m_axi_arregion(),
|
||||||
|
.m_axi_aruser(),
|
||||||
|
.m_axi_arvalid(),
|
||||||
|
.m_axi_arready(1'D0),
|
||||||
|
.m_axi_rid(1'B0),
|
||||||
|
.m_axi_rdata(64'B0),
|
||||||
|
.m_axi_rresp(2'B0),
|
||||||
|
.m_axi_rlast(1'D0),
|
||||||
|
.m_axi_ruser(1'B0),
|
||||||
|
.m_axi_rvalid(1'D0),
|
||||||
|
.m_axi_rready(),
|
||||||
|
.s_axis_tvalid(s_axis_tvalid),
|
||||||
|
.s_axis_tready(s_axis_tready),
|
||||||
|
.s_axis_tdata(s_axis_tdata),
|
||||||
|
.s_axis_tstrb(2'B0),
|
||||||
|
.s_axis_tkeep(2'B0),
|
||||||
|
.s_axis_tlast(1'D0),
|
||||||
|
.s_axis_tid(1'B0),
|
||||||
|
.s_axis_tdest(1'B0),
|
||||||
|
.s_axis_tuser(1'B0),
|
||||||
|
.m_axis_tvalid(m_axis_tvalid),
|
||||||
|
.m_axis_tready(m_axis_tready),
|
||||||
|
.m_axis_tdata(m_axis_tdata),
|
||||||
|
.m_axis_tstrb(),
|
||||||
|
.m_axis_tkeep(),
|
||||||
|
.m_axis_tlast(),
|
||||||
|
.m_axis_tid(),
|
||||||
|
.m_axis_tdest(),
|
||||||
|
.m_axis_tuser(),
|
||||||
|
.axi_aw_injectsbiterr(1'D0),
|
||||||
|
.axi_aw_injectdbiterr(1'D0),
|
||||||
|
.axi_aw_prog_full_thresh(4'B0),
|
||||||
|
.axi_aw_prog_empty_thresh(4'B0),
|
||||||
|
.axi_aw_data_count(),
|
||||||
|
.axi_aw_wr_data_count(),
|
||||||
|
.axi_aw_rd_data_count(),
|
||||||
|
.axi_aw_sbiterr(),
|
||||||
|
.axi_aw_dbiterr(),
|
||||||
|
.axi_aw_overflow(),
|
||||||
|
.axi_aw_underflow(),
|
||||||
|
.axi_aw_prog_full(),
|
||||||
|
.axi_aw_prog_empty(),
|
||||||
|
.axi_w_injectsbiterr(1'D0),
|
||||||
|
.axi_w_injectdbiterr(1'D0),
|
||||||
|
.axi_w_prog_full_thresh(10'B0),
|
||||||
|
.axi_w_prog_empty_thresh(10'B0),
|
||||||
|
.axi_w_data_count(),
|
||||||
|
.axi_w_wr_data_count(),
|
||||||
|
.axi_w_rd_data_count(),
|
||||||
|
.axi_w_sbiterr(),
|
||||||
|
.axi_w_dbiterr(),
|
||||||
|
.axi_w_overflow(),
|
||||||
|
.axi_w_underflow(),
|
||||||
|
.axi_w_prog_full(),
|
||||||
|
.axi_w_prog_empty(),
|
||||||
|
.axi_b_injectsbiterr(1'D0),
|
||||||
|
.axi_b_injectdbiterr(1'D0),
|
||||||
|
.axi_b_prog_full_thresh(4'B0),
|
||||||
|
.axi_b_prog_empty_thresh(4'B0),
|
||||||
|
.axi_b_data_count(),
|
||||||
|
.axi_b_wr_data_count(),
|
||||||
|
.axi_b_rd_data_count(),
|
||||||
|
.axi_b_sbiterr(),
|
||||||
|
.axi_b_dbiterr(),
|
||||||
|
.axi_b_overflow(),
|
||||||
|
.axi_b_underflow(),
|
||||||
|
.axi_b_prog_full(),
|
||||||
|
.axi_b_prog_empty(),
|
||||||
|
.axi_ar_injectsbiterr(1'D0),
|
||||||
|
.axi_ar_injectdbiterr(1'D0),
|
||||||
|
.axi_ar_prog_full_thresh(4'B0),
|
||||||
|
.axi_ar_prog_empty_thresh(4'B0),
|
||||||
|
.axi_ar_data_count(),
|
||||||
|
.axi_ar_wr_data_count(),
|
||||||
|
.axi_ar_rd_data_count(),
|
||||||
|
.axi_ar_sbiterr(),
|
||||||
|
.axi_ar_dbiterr(),
|
||||||
|
.axi_ar_overflow(),
|
||||||
|
.axi_ar_underflow(),
|
||||||
|
.axi_ar_prog_full(),
|
||||||
|
.axi_ar_prog_empty(),
|
||||||
|
.axi_r_injectsbiterr(1'D0),
|
||||||
|
.axi_r_injectdbiterr(1'D0),
|
||||||
|
.axi_r_prog_full_thresh(10'B0),
|
||||||
|
.axi_r_prog_empty_thresh(10'B0),
|
||||||
|
.axi_r_data_count(),
|
||||||
|
.axi_r_wr_data_count(),
|
||||||
|
.axi_r_rd_data_count(),
|
||||||
|
.axi_r_sbiterr(),
|
||||||
|
.axi_r_dbiterr(),
|
||||||
|
.axi_r_overflow(),
|
||||||
|
.axi_r_underflow(),
|
||||||
|
.axi_r_prog_full(),
|
||||||
|
.axi_r_prog_empty(),
|
||||||
|
.axis_injectsbiterr(1'D0),
|
||||||
|
.axis_injectdbiterr(1'D0),
|
||||||
|
.axis_prog_full_thresh(4'B0),
|
||||||
|
.axis_prog_empty_thresh(4'B0),
|
||||||
|
.axis_data_count(),
|
||||||
|
.axis_wr_data_count(),
|
||||||
|
.axis_rd_data_count(),
|
||||||
|
.axis_sbiterr(),
|
||||||
|
.axis_dbiterr(),
|
||||||
|
.axis_overflow(),
|
||||||
|
.axis_underflow(),
|
||||||
|
.axis_prog_full(),
|
||||||
|
.axis_prog_empty()
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,67 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||||
|
// IP Revision: 3
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
hop_rom your_instance_name (
|
||||||
|
.clka(clka), // input wire clka
|
||||||
|
.addra(addra), // input wire [7 : 0] addra
|
||||||
|
.douta(douta) // output wire [31 : 0] douta
|
||||||
|
);
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
// You must compile the wrapper file hop_rom.v when simulating
|
||||||
|
// the core, hop_rom. When compiling the wrapper file, be sure to
|
||||||
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
@@ -0,0 +1,79 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||||
|
-- IP Revision: 3
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture header.
|
||||||
|
|
||||||
|
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||||
|
COMPONENT hop_rom
|
||||||
|
PORT (
|
||||||
|
clka : IN STD_LOGIC;
|
||||||
|
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||||
|
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture
|
||||||
|
-- body. Substitute your own instance name and net names.
|
||||||
|
|
||||||
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||||
|
your_instance_name : hop_rom
|
||||||
|
PORT MAP (
|
||||||
|
clka => clka,
|
||||||
|
addra => addra,
|
||||||
|
douta => douta
|
||||||
|
);
|
||||||
|
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
-- You must compile the wrapper file hop_rom.vhd when simulating
|
||||||
|
-- the core, hop_rom. When compiling the wrapper file, be sure to
|
||||||
|
-- reference the VHDL simulation library.
|
||||||
|
|
||||||
+1006
File diff suppressed because it is too large
Load Diff
+1222
File diff suppressed because it is too large
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|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
// Date : Fri Mar 17 22:23:06 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v
|
||||||
|
// Design : hop_rom
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||||
|
module hop_rom(clka, addra, douta)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clka,addra[7:0],douta[31:0]" */;
|
||||||
|
input clka;
|
||||||
|
input [7:0]addra;
|
||||||
|
output [31:0]douta;
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,32 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
-- Date : Fri Mar 17 22:23:06 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl
|
||||||
|
-- Design : hop_rom
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity hop_rom is
|
||||||
|
Port (
|
||||||
|
clka : in STD_LOGIC;
|
||||||
|
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||||
|
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end hop_rom;
|
||||||
|
|
||||||
|
architecture stub of hop_rom is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "clka,addra[7:0],douta[31:0]";
|
||||||
|
attribute x_core_info : string;
|
||||||
|
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
@@ -0,0 +1,211 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||||
|
// IP Revision: 3
|
||||||
|
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module hop_rom (
|
||||||
|
clka,
|
||||||
|
addra,
|
||||||
|
douta
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
|
||||||
|
input wire clka;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
|
||||||
|
input wire [7 : 0] addra;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
|
||||||
|
output wire [31 : 0] douta;
|
||||||
|
|
||||||
|
blk_mem_gen_v8_4_3 #(
|
||||||
|
.C_FAMILY("zynq"),
|
||||||
|
.C_XDEVICEFAMILY("zynq"),
|
||||||
|
.C_ELABORATION_DIR("./"),
|
||||||
|
.C_INTERFACE_TYPE(0),
|
||||||
|
.C_AXI_TYPE(1),
|
||||||
|
.C_AXI_SLAVE_TYPE(0),
|
||||||
|
.C_USE_BRAM_BLOCK(0),
|
||||||
|
.C_ENABLE_32BIT_ADDRESS(0),
|
||||||
|
.C_CTRL_ECC_ALGO("NONE"),
|
||||||
|
.C_HAS_AXI_ID(0),
|
||||||
|
.C_AXI_ID_WIDTH(4),
|
||||||
|
.C_MEM_TYPE(3),
|
||||||
|
.C_BYTE_SIZE(9),
|
||||||
|
.C_ALGORITHM(1),
|
||||||
|
.C_PRIM_TYPE(1),
|
||||||
|
.C_LOAD_INIT_FILE(1),
|
||||||
|
.C_INIT_FILE_NAME("hop_rom.mif"),
|
||||||
|
.C_INIT_FILE("hop_rom.mem"),
|
||||||
|
.C_USE_DEFAULT_DATA(0),
|
||||||
|
.C_DEFAULT_DATA("0"),
|
||||||
|
.C_HAS_RSTA(0),
|
||||||
|
.C_RST_PRIORITY_A("CE"),
|
||||||
|
.C_RSTRAM_A(0),
|
||||||
|
.C_INITA_VAL("0"),
|
||||||
|
.C_HAS_ENA(0),
|
||||||
|
.C_HAS_REGCEA(0),
|
||||||
|
.C_USE_BYTE_WEA(0),
|
||||||
|
.C_WEA_WIDTH(1),
|
||||||
|
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||||
|
.C_WRITE_WIDTH_A(32),
|
||||||
|
.C_READ_WIDTH_A(32),
|
||||||
|
.C_WRITE_DEPTH_A(256),
|
||||||
|
.C_READ_DEPTH_A(256),
|
||||||
|
.C_ADDRA_WIDTH(8),
|
||||||
|
.C_HAS_RSTB(0),
|
||||||
|
.C_RST_PRIORITY_B("CE"),
|
||||||
|
.C_RSTRAM_B(0),
|
||||||
|
.C_INITB_VAL("0"),
|
||||||
|
.C_HAS_ENB(0),
|
||||||
|
.C_HAS_REGCEB(0),
|
||||||
|
.C_USE_BYTE_WEB(0),
|
||||||
|
.C_WEB_WIDTH(1),
|
||||||
|
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||||
|
.C_WRITE_WIDTH_B(32),
|
||||||
|
.C_READ_WIDTH_B(32),
|
||||||
|
.C_WRITE_DEPTH_B(256),
|
||||||
|
.C_READ_DEPTH_B(256),
|
||||||
|
.C_ADDRB_WIDTH(8),
|
||||||
|
.C_HAS_MEM_OUTPUT_REGS_A(1),
|
||||||
|
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
||||||
|
.C_HAS_MUX_OUTPUT_REGS_A(1),
|
||||||
|
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
||||||
|
.C_MUX_PIPELINE_STAGES(0),
|
||||||
|
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
||||||
|
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
||||||
|
.C_USE_SOFTECC(0),
|
||||||
|
.C_USE_ECC(0),
|
||||||
|
.C_EN_ECC_PIPE(0),
|
||||||
|
.C_READ_LATENCY_A(1),
|
||||||
|
.C_READ_LATENCY_B(1),
|
||||||
|
.C_HAS_INJECTERR(0),
|
||||||
|
.C_SIM_COLLISION_CHECK("ALL"),
|
||||||
|
.C_COMMON_CLK(0),
|
||||||
|
.C_DISABLE_WARN_BHV_COLL(0),
|
||||||
|
.C_EN_SLEEP_PIN(0),
|
||||||
|
.C_USE_URAM(0),
|
||||||
|
.C_EN_RDADDRA_CHG(0),
|
||||||
|
.C_EN_RDADDRB_CHG(0),
|
||||||
|
.C_EN_DEEPSLEEP_PIN(0),
|
||||||
|
.C_EN_SHUTDOWN_PIN(0),
|
||||||
|
.C_EN_SAFETY_CKT(0),
|
||||||
|
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||||
|
.C_COUNT_36K_BRAM("0"),
|
||||||
|
.C_COUNT_18K_BRAM("1"),
|
||||||
|
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.375199 mW")
|
||||||
|
) inst (
|
||||||
|
.clka(clka),
|
||||||
|
.rsta(1'D0),
|
||||||
|
.ena(1'D0),
|
||||||
|
.regcea(1'D0),
|
||||||
|
.wea(1'B0),
|
||||||
|
.addra(addra),
|
||||||
|
.dina(32'B0),
|
||||||
|
.douta(douta),
|
||||||
|
.clkb(1'D0),
|
||||||
|
.rstb(1'D0),
|
||||||
|
.enb(1'D0),
|
||||||
|
.regceb(1'D0),
|
||||||
|
.web(1'B0),
|
||||||
|
.addrb(8'B0),
|
||||||
|
.dinb(32'B0),
|
||||||
|
.doutb(),
|
||||||
|
.injectsbiterr(1'D0),
|
||||||
|
.injectdbiterr(1'D0),
|
||||||
|
.eccpipece(1'D0),
|
||||||
|
.sbiterr(),
|
||||||
|
.dbiterr(),
|
||||||
|
.rdaddrecc(),
|
||||||
|
.sleep(1'D0),
|
||||||
|
.deepsleep(1'D0),
|
||||||
|
.shutdown(1'D0),
|
||||||
|
.rsta_busy(),
|
||||||
|
.rstb_busy(),
|
||||||
|
.s_aclk(1'H0),
|
||||||
|
.s_aresetn(1'D0),
|
||||||
|
.s_axi_awid(4'B0),
|
||||||
|
.s_axi_awaddr(32'B0),
|
||||||
|
.s_axi_awlen(8'B0),
|
||||||
|
.s_axi_awsize(3'B0),
|
||||||
|
.s_axi_awburst(2'B0),
|
||||||
|
.s_axi_awvalid(1'D0),
|
||||||
|
.s_axi_awready(),
|
||||||
|
.s_axi_wdata(32'B0),
|
||||||
|
.s_axi_wstrb(1'B0),
|
||||||
|
.s_axi_wlast(1'D0),
|
||||||
|
.s_axi_wvalid(1'D0),
|
||||||
|
.s_axi_wready(),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(),
|
||||||
|
.s_axi_bvalid(),
|
||||||
|
.s_axi_bready(1'D0),
|
||||||
|
.s_axi_arid(4'B0),
|
||||||
|
.s_axi_araddr(32'B0),
|
||||||
|
.s_axi_arlen(8'B0),
|
||||||
|
.s_axi_arsize(3'B0),
|
||||||
|
.s_axi_arburst(2'B0),
|
||||||
|
.s_axi_arvalid(1'D0),
|
||||||
|
.s_axi_arready(),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(),
|
||||||
|
.s_axi_rresp(),
|
||||||
|
.s_axi_rlast(),
|
||||||
|
.s_axi_rvalid(),
|
||||||
|
.s_axi_rready(1'D0),
|
||||||
|
.s_axi_injectsbiterr(1'D0),
|
||||||
|
.s_axi_injectdbiterr(1'D0),
|
||||||
|
.s_axi_sbiterr(),
|
||||||
|
.s_axi_dbiterr(),
|
||||||
|
.s_axi_rdaddrecc()
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
+261
@@ -0,0 +1,261 @@
|
|||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- Description:
|
||||||
|
-- This is an example testbench for the FIR Compiler IP core.
|
||||||
|
-- The testbench has been generated by Vivado to accompany the IP core
|
||||||
|
-- instance you have generated.
|
||||||
|
--
|
||||||
|
-- This testbench is for demonstration purposes only. See note below for
|
||||||
|
-- instructions on how to use it with your core.
|
||||||
|
--
|
||||||
|
-- See the FIR Compiler product guide for further information
|
||||||
|
-- about this core.
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- Using this testbench
|
||||||
|
--
|
||||||
|
-- This testbench instantiates your generated FIR Compiler core
|
||||||
|
-- instance named "hrc_64_12_025".
|
||||||
|
--
|
||||||
|
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||||
|
-- documentation for details.
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.numeric_std.all;
|
||||||
|
|
||||||
|
entity tb_hrc_64_12_025 is
|
||||||
|
end tb_hrc_64_12_025;
|
||||||
|
|
||||||
|
architecture tb of tb_hrc_64_12_025 is
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Timing constants
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
constant CLOCK_PERIOD : time := 100 ns;
|
||||||
|
constant T_HOLD : time := 10 ns;
|
||||||
|
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- DUT signals
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
-- General signals
|
||||||
|
signal aclk : std_logic := '0'; -- the master clock
|
||||||
|
|
||||||
|
-- Data slave channel signals
|
||||||
|
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||||
|
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
|
||||||
|
signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
|
||||||
|
|
||||||
|
-- Data master channel signals
|
||||||
|
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||||
|
signal m_axis_data_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Aliases for AXI channel TDATA and TUSER fields
|
||||||
|
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||||
|
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||||
|
-- to prevent the simulator optimizing away these signals.
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
-- Data slave channel alias signals
|
||||||
|
signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0');
|
||||||
|
|
||||||
|
-- Data master channel alias signals
|
||||||
|
signal m_axis_data_tdata_data : std_logic_vector(17 downto 0) := (others => '0');
|
||||||
|
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Instantiate the DUT
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
dut : entity work.hrc_64_12_025
|
||||||
|
port map (
|
||||||
|
aclk => aclk,
|
||||||
|
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||||
|
s_axis_data_tready => s_axis_data_tready,
|
||||||
|
s_axis_data_tdata => s_axis_data_tdata,
|
||||||
|
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||||
|
m_axis_data_tdata => m_axis_data_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Generate clock
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
clock_gen : process
|
||||||
|
begin
|
||||||
|
aclk <= '0';
|
||||||
|
wait for CLOCK_PERIOD;
|
||||||
|
loop
|
||||||
|
aclk <= '0';
|
||||||
|
wait for CLOCK_PERIOD/2;
|
||||||
|
aclk <= '1';
|
||||||
|
wait for CLOCK_PERIOD/2;
|
||||||
|
end loop;
|
||||||
|
end process clock_gen;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Generate inputs
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
stimuli : process
|
||||||
|
|
||||||
|
-- Procedure to drive a number of input samples with specific data
|
||||||
|
-- data is the data value to drive on the tdata signal
|
||||||
|
-- samples is the number of zero-data input samples to drive
|
||||||
|
procedure drive_data ( data : std_logic_vector(7 downto 0);
|
||||||
|
samples : natural := 1 ) is
|
||||||
|
variable ip_count : integer := 0;
|
||||||
|
begin
|
||||||
|
ip_count := 0;
|
||||||
|
loop
|
||||||
|
s_axis_data_tvalid <= '1';
|
||||||
|
s_axis_data_tdata <= data;
|
||||||
|
loop
|
||||||
|
wait until rising_edge(aclk);
|
||||||
|
exit when s_axis_data_tready = '1';
|
||||||
|
end loop;
|
||||||
|
ip_count := ip_count + 1;
|
||||||
|
wait for T_HOLD;
|
||||||
|
-- Input rate is 1 input each 64 clock cycles: drive valid inputs at this rate
|
||||||
|
s_axis_data_tvalid <= '0';
|
||||||
|
wait for CLOCK_PERIOD * 63;
|
||||||
|
exit when ip_count >= samples;
|
||||||
|
end loop;
|
||||||
|
end procedure drive_data;
|
||||||
|
|
||||||
|
-- Procedure to drive a number of zero-data input samples
|
||||||
|
-- samples is the number of zero-data input samples to drive
|
||||||
|
procedure drive_zeros ( samples : natural := 1 ) is
|
||||||
|
begin
|
||||||
|
drive_data((others => '0'), samples);
|
||||||
|
end procedure drive_zeros;
|
||||||
|
|
||||||
|
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
|
||||||
|
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
|
||||||
|
procedure drive_impulse ( samples : natural := 901 ) is
|
||||||
|
variable impulse : std_logic_vector(7 downto 0);
|
||||||
|
begin
|
||||||
|
impulse := (others => '0'); -- initialize unused bits to zero
|
||||||
|
impulse(1 downto 0) := "01";
|
||||||
|
drive_data(impulse);
|
||||||
|
if samples > 1 then
|
||||||
|
drive_zeros(samples-1);
|
||||||
|
end if;
|
||||||
|
end procedure drive_impulse;
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
-- Drive inputs T_HOLD time after rising edge of clock
|
||||||
|
wait until rising_edge(aclk);
|
||||||
|
wait for T_HOLD;
|
||||||
|
|
||||||
|
-- Drive a single impulse and let the impulse response emerge
|
||||||
|
drive_impulse;
|
||||||
|
|
||||||
|
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
|
||||||
|
drive_impulse(2); -- start of impulse; data is now zero
|
||||||
|
s_axis_data_tvalid <= '0';
|
||||||
|
wait for CLOCK_PERIOD * 320; -- provide no data for 5 input samples worth
|
||||||
|
drive_zeros(2); -- 2 normal input samples
|
||||||
|
s_axis_data_tvalid <= '1';
|
||||||
|
wait for CLOCK_PERIOD * 320; -- provide data as fast as the core can accept it for 5 input samples worth
|
||||||
|
drive_zeros(892); -- back to normal operation
|
||||||
|
|
||||||
|
-- End of test
|
||||||
|
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||||
|
wait;
|
||||||
|
|
||||||
|
end process stimuli;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Check outputs
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
check_outputs : process
|
||||||
|
variable check_ok : boolean := true;
|
||||||
|
begin
|
||||||
|
|
||||||
|
-- Check outputs T_STROBE time after rising edge of clock
|
||||||
|
wait until rising_edge(aclk);
|
||||||
|
wait for T_STROBE;
|
||||||
|
|
||||||
|
-- Do not check the output payload values, as this requires the behavioral model
|
||||||
|
-- which would make this demonstration testbench unwieldy.
|
||||||
|
-- Instead, check the protocol of the master DATA channel:
|
||||||
|
-- check that the payload is valid (not X) when TVALID is high
|
||||||
|
|
||||||
|
if m_axis_data_tvalid = '1' then
|
||||||
|
if is_x(m_axis_data_tdata) then
|
||||||
|
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
|
||||||
|
check_ok := false;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
|
||||||
|
assert check_ok
|
||||||
|
report "ERROR: terminating test with failures." severity failure;
|
||||||
|
|
||||||
|
end process check_outputs;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
-- Data slave channel alias signals
|
||||||
|
s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0);
|
||||||
|
|
||||||
|
-- Data master channel alias signals: update these only when they are valid
|
||||||
|
m_axis_data_tdata_data <= m_axis_data_tdata(17 downto 0) when m_axis_data_tvalid = '1';
|
||||||
|
|
||||||
|
end tb;
|
||||||
+70
@@ -0,0 +1,70 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||||
|
// IP Revision: 12
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
hrc_64_12_025 your_instance_name (
|
||||||
|
.aclk(aclk), // input wire aclk
|
||||||
|
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
|
||||||
|
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
|
||||||
|
.s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata
|
||||||
|
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
|
||||||
|
.m_axis_data_tdata(m_axis_data_tdata) // output wire [23 : 0] m_axis_data_tdata
|
||||||
|
);
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
// You must compile the wrapper file hrc_64_12_025.v when simulating
|
||||||
|
// the core, hrc_64_12_025. When compiling the wrapper file, be sure to
|
||||||
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
+85
@@ -0,0 +1,85 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||||
|
-- IP Revision: 12
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture header.
|
||||||
|
|
||||||
|
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||||
|
COMPONENT hrc_64_12_025
|
||||||
|
PORT (
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
s_axis_data_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_data_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||||
|
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture
|
||||||
|
-- body. Substitute your own instance name and net names.
|
||||||
|
|
||||||
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||||
|
your_instance_name : hrc_64_12_025
|
||||||
|
PORT MAP (
|
||||||
|
aclk => aclk,
|
||||||
|
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||||
|
s_axis_data_tready => s_axis_data_tready,
|
||||||
|
s_axis_data_tdata => s_axis_data_tdata,
|
||||||
|
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||||
|
m_axis_data_tdata => m_axis_data_tdata
|
||||||
|
);
|
||||||
|
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
-- You must compile the wrapper file hrc_64_12_025.vhd when simulating
|
||||||
|
-- the core, hrc_64_12_025. When compiling the wrapper file, be sure to
|
||||||
|
-- reference the VHDL simulation library.
|
||||||
|
|
||||||
+5518
File diff suppressed because it is too large
Load Diff
+7480
File diff suppressed because it is too large
Load Diff
+26
@@ -0,0 +1,26 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
// Date : Fri Mar 17 22:22:50 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.v
|
||||||
|
// Design : hrc_64_12_025
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
|
||||||
|
module hrc_64_12_025(aclk, s_axis_data_tvalid, s_axis_data_tready,
|
||||||
|
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
|
||||||
|
input aclk;
|
||||||
|
input s_axis_data_tvalid;
|
||||||
|
output s_axis_data_tready;
|
||||||
|
input [7:0]s_axis_data_tdata;
|
||||||
|
output m_axis_data_tvalid;
|
||||||
|
output [23:0]m_axis_data_tdata;
|
||||||
|
endmodule
|
||||||
+35
@@ -0,0 +1,35 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
-- Date : Fri Mar 17 22:22:50 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.vhdl
|
||||||
|
-- Design : hrc_64_12_025
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity hrc_64_12_025 is
|
||||||
|
Port (
|
||||||
|
aclk : in STD_LOGIC;
|
||||||
|
s_axis_data_tvalid : in STD_LOGIC;
|
||||||
|
s_axis_data_tready : out STD_LOGIC;
|
||||||
|
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||||
|
m_axis_data_tvalid : out STD_LOGIC;
|
||||||
|
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end hrc_64_12_025;
|
||||||
|
|
||||||
|
architecture stub of hrc_64_12_025 is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]";
|
||||||
|
attribute x_core_info : string;
|
||||||
|
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
+281
@@ -0,0 +1,281 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||||
|
-- IP Revision: 12
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
LIBRARY fir_compiler_v7_2_12;
|
||||||
|
USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
|
||||||
|
|
||||||
|
ENTITY hrc_64_12_025 IS
|
||||||
|
PORT (
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
s_axis_data_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_data_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||||
|
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END hrc_64_12_025;
|
||||||
|
|
||||||
|
ARCHITECTURE hrc_64_12_025_arch OF hrc_64_12_025 IS
|
||||||
|
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||||
|
ATTRIBUTE DowngradeIPIdentifiedWarnings OF hrc_64_12_025_arch: ARCHITECTURE IS "yes";
|
||||||
|
COMPONENT fir_compiler_v7_2_12 IS
|
||||||
|
GENERIC (
|
||||||
|
C_XDEVICEFAMILY : STRING;
|
||||||
|
C_ELABORATION_DIR : STRING;
|
||||||
|
C_COMPONENT_NAME : STRING;
|
||||||
|
C_COEF_FILE : STRING;
|
||||||
|
C_COEF_FILE_LINES : INTEGER;
|
||||||
|
C_FILTER_TYPE : INTEGER;
|
||||||
|
C_INTERP_RATE : INTEGER;
|
||||||
|
C_DECIM_RATE : INTEGER;
|
||||||
|
C_ZERO_PACKING_FACTOR : INTEGER;
|
||||||
|
C_SYMMETRY : INTEGER;
|
||||||
|
C_NUM_FILTS : INTEGER;
|
||||||
|
C_NUM_TAPS : INTEGER;
|
||||||
|
C_NUM_CHANNELS : INTEGER;
|
||||||
|
C_CHANNEL_PATTERN : STRING;
|
||||||
|
C_ROUND_MODE : INTEGER;
|
||||||
|
C_COEF_RELOAD : INTEGER;
|
||||||
|
C_NUM_RELOAD_SLOTS : INTEGER;
|
||||||
|
C_COL_MODE : INTEGER;
|
||||||
|
C_COL_PIPE_LEN : INTEGER;
|
||||||
|
C_COL_CONFIG : STRING;
|
||||||
|
C_OPTIMIZATION : INTEGER;
|
||||||
|
C_DATA_PATH_WIDTHS : STRING;
|
||||||
|
C_DATA_IP_PATH_WIDTHS : STRING;
|
||||||
|
C_DATA_PX_PATH_WIDTHS : STRING;
|
||||||
|
C_DATA_WIDTH : INTEGER;
|
||||||
|
C_COEF_PATH_WIDTHS : STRING;
|
||||||
|
C_COEF_WIDTH : INTEGER;
|
||||||
|
C_DATA_PATH_SRC : STRING;
|
||||||
|
C_COEF_PATH_SRC : STRING;
|
||||||
|
C_PX_PATH_SRC : STRING;
|
||||||
|
C_DATA_PATH_SIGN : STRING;
|
||||||
|
C_COEF_PATH_SIGN : STRING;
|
||||||
|
C_ACCUM_PATH_WIDTHS : STRING;
|
||||||
|
C_OUTPUT_WIDTH : INTEGER;
|
||||||
|
C_OUTPUT_PATH_WIDTHS : STRING;
|
||||||
|
C_ACCUM_OP_PATH_WIDTHS : STRING;
|
||||||
|
C_EXT_MULT_CNFG : STRING;
|
||||||
|
C_DATA_PATH_PSAMP_SRC : STRING;
|
||||||
|
C_OP_PATH_PSAMP_SRC : STRING;
|
||||||
|
C_NUM_MADDS : INTEGER;
|
||||||
|
C_OPT_MADDS : STRING;
|
||||||
|
C_OVERSAMPLING_RATE : INTEGER;
|
||||||
|
C_INPUT_RATE : INTEGER;
|
||||||
|
C_OUTPUT_RATE : INTEGER;
|
||||||
|
C_DATA_MEMTYPE : INTEGER;
|
||||||
|
C_COEF_MEMTYPE : INTEGER;
|
||||||
|
C_IPBUFF_MEMTYPE : INTEGER;
|
||||||
|
C_OPBUFF_MEMTYPE : INTEGER;
|
||||||
|
C_DATAPATH_MEMTYPE : INTEGER;
|
||||||
|
C_MEM_ARRANGEMENT : INTEGER;
|
||||||
|
C_DATA_MEM_PACKING : INTEGER;
|
||||||
|
C_COEF_MEM_PACKING : INTEGER;
|
||||||
|
C_FILTS_PACKED : INTEGER;
|
||||||
|
C_LATENCY : INTEGER;
|
||||||
|
C_HAS_ARESETn : INTEGER;
|
||||||
|
C_HAS_ACLKEN : INTEGER;
|
||||||
|
C_DATA_HAS_TLAST : INTEGER;
|
||||||
|
C_S_DATA_HAS_FIFO : INTEGER;
|
||||||
|
C_S_DATA_HAS_TUSER : INTEGER;
|
||||||
|
C_S_DATA_TDATA_WIDTH : INTEGER;
|
||||||
|
C_S_DATA_TUSER_WIDTH : INTEGER;
|
||||||
|
C_M_DATA_HAS_TREADY : INTEGER;
|
||||||
|
C_M_DATA_HAS_TUSER : INTEGER;
|
||||||
|
C_M_DATA_TDATA_WIDTH : INTEGER;
|
||||||
|
C_M_DATA_TUSER_WIDTH : INTEGER;
|
||||||
|
C_HAS_CONFIG_CHANNEL : INTEGER;
|
||||||
|
C_CONFIG_SYNC_MODE : INTEGER;
|
||||||
|
C_CONFIG_PACKET_SIZE : INTEGER;
|
||||||
|
C_CONFIG_TDATA_WIDTH : INTEGER;
|
||||||
|
C_RELOAD_TDATA_WIDTH : INTEGER
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
aresetn : IN STD_LOGIC;
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
aclken : IN STD_LOGIC;
|
||||||
|
s_axis_data_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_data_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_data_tlast : IN STD_LOGIC;
|
||||||
|
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||||
|
s_axis_config_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_config_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_config_tlast : IN STD_LOGIC;
|
||||||
|
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
s_axis_reload_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_reload_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_reload_tlast : IN STD_LOGIC;
|
||||||
|
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_data_tready : IN STD_LOGIC;
|
||||||
|
m_axis_data_tlast : OUT STD_LOGIC;
|
||||||
|
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||||
|
event_s_data_tlast_missing : OUT STD_LOGIC;
|
||||||
|
event_s_data_tlast_unexpected : OUT STD_LOGIC;
|
||||||
|
event_s_data_chanid_incorrect : OUT STD_LOGIC;
|
||||||
|
event_s_config_tlast_missing : OUT STD_LOGIC;
|
||||||
|
event_s_config_tlast_unexpected : OUT STD_LOGIC;
|
||||||
|
event_s_reload_tlast_missing : OUT STD_LOGIC;
|
||||||
|
event_s_reload_tlast_unexpected : OUT STD_LOGIC
|
||||||
|
);
|
||||||
|
END COMPONENT fir_compiler_v7_2_12;
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||||
|
BEGIN
|
||||||
|
U0 : fir_compiler_v7_2_12
|
||||||
|
GENERIC MAP (
|
||||||
|
C_XDEVICEFAMILY => "zynq",
|
||||||
|
C_ELABORATION_DIR => "./",
|
||||||
|
C_COMPONENT_NAME => "hrc_64_12_025",
|
||||||
|
C_COEF_FILE => "hrc_64_12_025.mif",
|
||||||
|
C_COEF_FILE_LINES => 448,
|
||||||
|
C_FILTER_TYPE => 2,
|
||||||
|
C_INTERP_RATE => 64,
|
||||||
|
C_DECIM_RATE => 1,
|
||||||
|
C_ZERO_PACKING_FACTOR => 1,
|
||||||
|
C_SYMMETRY => 1,
|
||||||
|
C_NUM_FILTS => 1,
|
||||||
|
C_NUM_TAPS => 769,
|
||||||
|
C_NUM_CHANNELS => 1,
|
||||||
|
C_CHANNEL_PATTERN => "fixed",
|
||||||
|
C_ROUND_MODE => 0,
|
||||||
|
C_COEF_RELOAD => 0,
|
||||||
|
C_NUM_RELOAD_SLOTS => 1,
|
||||||
|
C_COL_MODE => 1,
|
||||||
|
C_COL_PIPE_LEN => 4,
|
||||||
|
C_COL_CONFIG => "7",
|
||||||
|
C_OPTIMIZATION => 0,
|
||||||
|
C_DATA_PATH_WIDTHS => "2",
|
||||||
|
C_DATA_IP_PATH_WIDTHS => "2",
|
||||||
|
C_DATA_PX_PATH_WIDTHS => "2",
|
||||||
|
C_DATA_WIDTH => 2,
|
||||||
|
C_COEF_PATH_WIDTHS => "17",
|
||||||
|
C_COEF_WIDTH => 16,
|
||||||
|
C_DATA_PATH_SRC => "0",
|
||||||
|
C_COEF_PATH_SRC => "0",
|
||||||
|
C_PX_PATH_SRC => "0",
|
||||||
|
C_DATA_PATH_SIGN => "0",
|
||||||
|
C_COEF_PATH_SIGN => "0",
|
||||||
|
C_ACCUM_PATH_WIDTHS => "19",
|
||||||
|
C_OUTPUT_WIDTH => 18,
|
||||||
|
C_OUTPUT_PATH_WIDTHS => "18",
|
||||||
|
C_ACCUM_OP_PATH_WIDTHS => "18",
|
||||||
|
C_EXT_MULT_CNFG => "none",
|
||||||
|
C_DATA_PATH_PSAMP_SRC => "0",
|
||||||
|
C_OP_PATH_PSAMP_SRC => "0",
|
||||||
|
C_NUM_MADDS => 7,
|
||||||
|
C_OPT_MADDS => "none",
|
||||||
|
C_OVERSAMPLING_RATE => 1,
|
||||||
|
C_INPUT_RATE => 64,
|
||||||
|
C_OUTPUT_RATE => 1,
|
||||||
|
C_DATA_MEMTYPE => 0,
|
||||||
|
C_COEF_MEMTYPE => 2,
|
||||||
|
C_IPBUFF_MEMTYPE => 0,
|
||||||
|
C_OPBUFF_MEMTYPE => 2,
|
||||||
|
C_DATAPATH_MEMTYPE => 0,
|
||||||
|
C_MEM_ARRANGEMENT => 1,
|
||||||
|
C_DATA_MEM_PACKING => 0,
|
||||||
|
C_COEF_MEM_PACKING => 0,
|
||||||
|
C_FILTS_PACKED => 0,
|
||||||
|
C_LATENCY => 17,
|
||||||
|
C_HAS_ARESETn => 0,
|
||||||
|
C_HAS_ACLKEN => 0,
|
||||||
|
C_DATA_HAS_TLAST => 0,
|
||||||
|
C_S_DATA_HAS_FIFO => 0,
|
||||||
|
C_S_DATA_HAS_TUSER => 0,
|
||||||
|
C_S_DATA_TDATA_WIDTH => 8,
|
||||||
|
C_S_DATA_TUSER_WIDTH => 1,
|
||||||
|
C_M_DATA_HAS_TREADY => 0,
|
||||||
|
C_M_DATA_HAS_TUSER => 0,
|
||||||
|
C_M_DATA_TDATA_WIDTH => 24,
|
||||||
|
C_M_DATA_TUSER_WIDTH => 1,
|
||||||
|
C_HAS_CONFIG_CHANNEL => 0,
|
||||||
|
C_CONFIG_SYNC_MODE => 0,
|
||||||
|
C_CONFIG_PACKET_SIZE => 0,
|
||||||
|
C_CONFIG_TDATA_WIDTH => 1,
|
||||||
|
C_RELOAD_TDATA_WIDTH => 1
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
aresetn => '1',
|
||||||
|
aclk => aclk,
|
||||||
|
aclken => '1',
|
||||||
|
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||||
|
s_axis_data_tready => s_axis_data_tready,
|
||||||
|
s_axis_data_tlast => '0',
|
||||||
|
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
s_axis_data_tdata => s_axis_data_tdata,
|
||||||
|
s_axis_config_tvalid => '0',
|
||||||
|
s_axis_config_tlast => '0',
|
||||||
|
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
s_axis_reload_tvalid => '0',
|
||||||
|
s_axis_reload_tlast => '0',
|
||||||
|
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||||
|
m_axis_data_tready => '1',
|
||||||
|
m_axis_data_tdata => m_axis_data_tdata
|
||||||
|
);
|
||||||
|
END hrc_64_12_025_arch;
|
||||||
+74
@@ -0,0 +1,74 @@
|
|||||||
|
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
|
||||||
|
ila_ctrl_signal your_instance_name (
|
||||||
|
.clk(clk), // input wire clk
|
||||||
|
|
||||||
|
|
||||||
|
.probe0(probe0), // input wire [0:0] probe0
|
||||||
|
.probe1(probe1), // input wire [0:0] probe1
|
||||||
|
.probe2(probe2), // input wire [0:0] probe2
|
||||||
|
.probe3(probe3), // input wire [0:0] probe3
|
||||||
|
.probe4(probe4), // input wire [0:0] probe4
|
||||||
|
.probe5(probe5) // input wire [0:0] probe5
|
||||||
|
);
|
||||||
|
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
// You must compile the wrapper file ila_ctrl_signal when simulating
|
||||||
|
// the core, ila_ctrl_signal. When compiling the wrapper file, be sure to
|
||||||
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
|
|
||||||
+43377
File diff suppressed because one or more lines are too long
+71520
File diff suppressed because one or more lines are too long
+26
@@ -0,0 +1,26 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
// Date : Fri Mar 17 22:23:33 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/ila_ctrl_signal_synth_1/ila_ctrl_signal_stub.v
|
||||||
|
// Design : ila_ctrl_signal
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||||
|
module ila_ctrl_signal(clk, probe0, probe1, probe2, probe3, probe4, probe5)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0]" */;
|
||||||
|
input clk;
|
||||||
|
input [0:0]probe0;
|
||||||
|
input [0:0]probe1;
|
||||||
|
input [0:0]probe2;
|
||||||
|
input [0:0]probe3;
|
||||||
|
input [0:0]probe4;
|
||||||
|
input [0:0]probe5;
|
||||||
|
endmodule
|
||||||
+36
@@ -0,0 +1,36 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
-- Date : Fri Mar 17 22:23:33 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/ila_ctrl_signal_synth_1/ila_ctrl_signal_stub.vhdl
|
||||||
|
-- Design : ila_ctrl_signal
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity ila_ctrl_signal is
|
||||||
|
Port (
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end ila_ctrl_signal;
|
||||||
|
|
||||||
|
architecture stub of ila_ctrl_signal is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0]";
|
||||||
|
attribute X_CORE_INFO : string;
|
||||||
|
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
+72
@@ -0,0 +1,72 @@
|
|||||||
|
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
module ila_ctrl_signal (
|
||||||
|
clk,
|
||||||
|
|
||||||
|
|
||||||
|
probe0,
|
||||||
|
probe1,
|
||||||
|
probe2,
|
||||||
|
probe3,
|
||||||
|
probe4,
|
||||||
|
probe5
|
||||||
|
);
|
||||||
|
|
||||||
|
input clk;
|
||||||
|
|
||||||
|
|
||||||
|
input [0 : 0] probe0;
|
||||||
|
input [0 : 0] probe1;
|
||||||
|
input [0 : 0] probe2;
|
||||||
|
input [0 : 0] probe3;
|
||||||
|
input [0 : 0] probe4;
|
||||||
|
input [0 : 0] probe5;
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,76 @@
|
|||||||
|
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
|
||||||
|
ila_tx_rx your_instance_name (
|
||||||
|
.clk(clk), // input wire clk
|
||||||
|
|
||||||
|
|
||||||
|
.probe0(probe0), // input wire [15:0] probe0
|
||||||
|
.probe1(probe1), // input wire [15:0] probe1
|
||||||
|
.probe2(probe2), // input wire [15:0] probe2
|
||||||
|
.probe3(probe3), // input wire [15:0] probe3
|
||||||
|
.probe4(probe4), // input wire [15:0] probe4
|
||||||
|
.probe5(probe5), // input wire [15:0] probe5
|
||||||
|
.probe6(probe6), // input wire [0:0] probe6
|
||||||
|
.probe7(probe7) // input wire [0:0] probe7
|
||||||
|
);
|
||||||
|
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
// You must compile the wrapper file ila_tx_rx when simulating
|
||||||
|
// the core, ila_tx_rx. When compiling the wrapper file, be sure to
|
||||||
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
|
|
||||||
+238512
File diff suppressed because one or more lines are too long
+282094
File diff suppressed because one or more lines are too long
@@ -0,0 +1,29 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
// Date : Fri Mar 17 22:27:10 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/ila_tx_rx_synth_1/ila_tx_rx_stub.v
|
||||||
|
// Design : ila_tx_rx
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||||
|
module ila_tx_rx(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||||
|
probe6, probe7)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[15:0],probe1[15:0],probe2[15:0],probe3[15:0],probe4[15:0],probe5[15:0],probe6[0:0],probe7[0:0]" */;
|
||||||
|
input clk;
|
||||||
|
input [15:0]probe0;
|
||||||
|
input [15:0]probe1;
|
||||||
|
input [15:0]probe2;
|
||||||
|
input [15:0]probe3;
|
||||||
|
input [15:0]probe4;
|
||||||
|
input [15:0]probe5;
|
||||||
|
input [0:0]probe6;
|
||||||
|
input [0:0]probe7;
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,38 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
-- Date : Fri Mar 17 22:27:10 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/ila_tx_rx_synth_1/ila_tx_rx_stub.vhdl
|
||||||
|
-- Design : ila_tx_rx
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity ila_tx_rx is
|
||||||
|
Port (
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
probe0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
probe1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
probe2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
probe3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
probe4 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
probe5 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe7 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end ila_tx_rx;
|
||||||
|
|
||||||
|
architecture stub of ila_tx_rx is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "clk,probe0[15:0],probe1[15:0],probe2[15:0],probe3[15:0],probe4[15:0],probe5[15:0],probe6[0:0],probe7[0:0]";
|
||||||
|
attribute X_CORE_INFO : string;
|
||||||
|
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
@@ -0,0 +1,76 @@
|
|||||||
|
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
module ila_tx_rx (
|
||||||
|
clk,
|
||||||
|
|
||||||
|
|
||||||
|
probe0,
|
||||||
|
probe1,
|
||||||
|
probe2,
|
||||||
|
probe3,
|
||||||
|
probe4,
|
||||||
|
probe5,
|
||||||
|
probe6,
|
||||||
|
probe7
|
||||||
|
);
|
||||||
|
|
||||||
|
input clk;
|
||||||
|
|
||||||
|
|
||||||
|
input [15 : 0] probe0;
|
||||||
|
input [15 : 0] probe1;
|
||||||
|
input [15 : 0] probe2;
|
||||||
|
input [15 : 0] probe3;
|
||||||
|
input [15 : 0] probe4;
|
||||||
|
input [15 : 0] probe5;
|
||||||
|
input [0 : 0] probe6;
|
||||||
|
input [0 : 0] probe7;
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
+261
@@ -0,0 +1,261 @@
|
|||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- Description:
|
||||||
|
-- This is an example testbench for the FIR Compiler IP core.
|
||||||
|
-- The testbench has been generated by Vivado to accompany the IP core
|
||||||
|
-- instance you have generated.
|
||||||
|
--
|
||||||
|
-- This testbench is for demonstration purposes only. See note below for
|
||||||
|
-- instructions on how to use it with your core.
|
||||||
|
--
|
||||||
|
-- See the FIR Compiler product guide for further information
|
||||||
|
-- about this core.
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- Using this testbench
|
||||||
|
--
|
||||||
|
-- This testbench instantiates your generated FIR Compiler core
|
||||||
|
-- instance named "lpf_125k".
|
||||||
|
--
|
||||||
|
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||||
|
-- documentation for details.
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.numeric_std.all;
|
||||||
|
|
||||||
|
entity tb_lpf_125k is
|
||||||
|
end tb_lpf_125k;
|
||||||
|
|
||||||
|
architecture tb of tb_lpf_125k is
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Timing constants
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
constant CLOCK_PERIOD : time := 100 ns;
|
||||||
|
constant T_HOLD : time := 10 ns;
|
||||||
|
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- DUT signals
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
-- General signals
|
||||||
|
signal aclk : std_logic := '0'; -- the master clock
|
||||||
|
|
||||||
|
-- Data slave channel signals
|
||||||
|
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||||
|
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
|
||||||
|
signal s_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
|
||||||
|
|
||||||
|
-- Data master channel signals
|
||||||
|
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||||
|
signal m_axis_data_tdata : std_logic_vector(39 downto 0) := (others => '0'); -- data payload
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Aliases for AXI channel TDATA and TUSER fields
|
||||||
|
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||||
|
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||||
|
-- to prevent the simulator optimizing away these signals.
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
-- Data slave channel alias signals
|
||||||
|
signal s_axis_data_tdata_data : std_logic_vector(15 downto 0) := (others => '0');
|
||||||
|
|
||||||
|
-- Data master channel alias signals
|
||||||
|
signal m_axis_data_tdata_data : std_logic_vector(32 downto 0) := (others => '0');
|
||||||
|
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Instantiate the DUT
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
dut : entity work.lpf_125k
|
||||||
|
port map (
|
||||||
|
aclk => aclk,
|
||||||
|
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||||
|
s_axis_data_tready => s_axis_data_tready,
|
||||||
|
s_axis_data_tdata => s_axis_data_tdata,
|
||||||
|
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||||
|
m_axis_data_tdata => m_axis_data_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Generate clock
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
clock_gen : process
|
||||||
|
begin
|
||||||
|
aclk <= '0';
|
||||||
|
wait for CLOCK_PERIOD;
|
||||||
|
loop
|
||||||
|
aclk <= '0';
|
||||||
|
wait for CLOCK_PERIOD/2;
|
||||||
|
aclk <= '1';
|
||||||
|
wait for CLOCK_PERIOD/2;
|
||||||
|
end loop;
|
||||||
|
end process clock_gen;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Generate inputs
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
stimuli : process
|
||||||
|
|
||||||
|
-- Procedure to drive a number of input samples with specific data
|
||||||
|
-- data is the data value to drive on the tdata signal
|
||||||
|
-- samples is the number of zero-data input samples to drive
|
||||||
|
procedure drive_data ( data : std_logic_vector(15 downto 0);
|
||||||
|
samples : natural := 1 ) is
|
||||||
|
variable ip_count : integer := 0;
|
||||||
|
begin
|
||||||
|
ip_count := 0;
|
||||||
|
loop
|
||||||
|
s_axis_data_tvalid <= '1';
|
||||||
|
s_axis_data_tdata <= data;
|
||||||
|
loop
|
||||||
|
wait until rising_edge(aclk);
|
||||||
|
exit when s_axis_data_tready = '1';
|
||||||
|
end loop;
|
||||||
|
ip_count := ip_count + 1;
|
||||||
|
wait for T_HOLD;
|
||||||
|
-- Input rate is 1 input each 2 clock cycles: drive valid inputs at this rate
|
||||||
|
s_axis_data_tvalid <= '0';
|
||||||
|
wait for CLOCK_PERIOD * 1;
|
||||||
|
exit when ip_count >= samples;
|
||||||
|
end loop;
|
||||||
|
end procedure drive_data;
|
||||||
|
|
||||||
|
-- Procedure to drive a number of zero-data input samples
|
||||||
|
-- samples is the number of zero-data input samples to drive
|
||||||
|
procedure drive_zeros ( samples : natural := 1 ) is
|
||||||
|
begin
|
||||||
|
drive_data((others => '0'), samples);
|
||||||
|
end procedure drive_zeros;
|
||||||
|
|
||||||
|
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
|
||||||
|
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
|
||||||
|
procedure drive_impulse ( samples : natural := 1104 ) is
|
||||||
|
variable impulse : std_logic_vector(15 downto 0);
|
||||||
|
begin
|
||||||
|
impulse := (others => '0'); -- initialize unused bits to zero
|
||||||
|
impulse(15 downto 0) := "0100000000000000";
|
||||||
|
drive_data(impulse);
|
||||||
|
if samples > 1 then
|
||||||
|
drive_zeros(samples-1);
|
||||||
|
end if;
|
||||||
|
end procedure drive_impulse;
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
-- Drive inputs T_HOLD time after rising edge of clock
|
||||||
|
wait until rising_edge(aclk);
|
||||||
|
wait for T_HOLD;
|
||||||
|
|
||||||
|
-- Drive a single impulse and let the impulse response emerge
|
||||||
|
drive_impulse;
|
||||||
|
|
||||||
|
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
|
||||||
|
drive_impulse(2); -- start of impulse; data is now zero
|
||||||
|
s_axis_data_tvalid <= '0';
|
||||||
|
wait for CLOCK_PERIOD * 10; -- provide no data for 5 input samples worth
|
||||||
|
drive_zeros(2); -- 2 normal input samples
|
||||||
|
s_axis_data_tvalid <= '1';
|
||||||
|
wait for CLOCK_PERIOD * 10; -- provide data as fast as the core can accept it for 5 input samples worth
|
||||||
|
drive_zeros(1095); -- back to normal operation
|
||||||
|
|
||||||
|
-- End of test
|
||||||
|
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||||
|
wait;
|
||||||
|
|
||||||
|
end process stimuli;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Check outputs
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
check_outputs : process
|
||||||
|
variable check_ok : boolean := true;
|
||||||
|
begin
|
||||||
|
|
||||||
|
-- Check outputs T_STROBE time after rising edge of clock
|
||||||
|
wait until rising_edge(aclk);
|
||||||
|
wait for T_STROBE;
|
||||||
|
|
||||||
|
-- Do not check the output payload values, as this requires the behavioral model
|
||||||
|
-- which would make this demonstration testbench unwieldy.
|
||||||
|
-- Instead, check the protocol of the master DATA channel:
|
||||||
|
-- check that the payload is valid (not X) when TVALID is high
|
||||||
|
|
||||||
|
if m_axis_data_tvalid = '1' then
|
||||||
|
if is_x(m_axis_data_tdata) then
|
||||||
|
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
|
||||||
|
check_ok := false;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
|
||||||
|
assert check_ok
|
||||||
|
report "ERROR: terminating test with failures." severity failure;
|
||||||
|
|
||||||
|
end process check_outputs;
|
||||||
|
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
|
||||||
|
-- Data slave channel alias signals
|
||||||
|
s_axis_data_tdata_data <= s_axis_data_tdata(15 downto 0);
|
||||||
|
|
||||||
|
-- Data master channel alias signals: update these only when they are valid
|
||||||
|
m_axis_data_tdata_data <= m_axis_data_tdata(32 downto 0) when m_axis_data_tvalid = '1';
|
||||||
|
|
||||||
|
end tb;
|
||||||
@@ -0,0 +1,70 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||||
|
// IP Revision: 12
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
lpf_125k your_instance_name (
|
||||||
|
.aclk(aclk), // input wire aclk
|
||||||
|
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
|
||||||
|
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
|
||||||
|
.s_axis_data_tdata(s_axis_data_tdata), // input wire [15 : 0] s_axis_data_tdata
|
||||||
|
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
|
||||||
|
.m_axis_data_tdata(m_axis_data_tdata) // output wire [39 : 0] m_axis_data_tdata
|
||||||
|
);
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
// You must compile the wrapper file lpf_125k.v when simulating
|
||||||
|
// the core, lpf_125k. When compiling the wrapper file, be sure to
|
||||||
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
@@ -0,0 +1,85 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||||
|
-- IP Revision: 12
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture header.
|
||||||
|
|
||||||
|
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||||
|
COMPONENT lpf_125k
|
||||||
|
PORT (
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
s_axis_data_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_data_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||||
|
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture
|
||||||
|
-- body. Substitute your own instance name and net names.
|
||||||
|
|
||||||
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||||
|
your_instance_name : lpf_125k
|
||||||
|
PORT MAP (
|
||||||
|
aclk => aclk,
|
||||||
|
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||||
|
s_axis_data_tready => s_axis_data_tready,
|
||||||
|
s_axis_data_tdata => s_axis_data_tdata,
|
||||||
|
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||||
|
m_axis_data_tdata => m_axis_data_tdata
|
||||||
|
);
|
||||||
|
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
-- You must compile the wrapper file lpf_125k.vhd when simulating
|
||||||
|
-- the core, lpf_125k. When compiling the wrapper file, be sure to
|
||||||
|
-- reference the VHDL simulation library.
|
||||||
|
|
||||||
+13382
File diff suppressed because it is too large
Load Diff
+17463
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,26 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
// Date : Tue Mar 21 16:04:39 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// d:/vivado-git/projects/datalink_814/dl814_dj_48m/ip/lpf_125k/lpf_125k_stub.v
|
||||||
|
// Design : lpf_125k
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
|
||||||
|
module lpf_125k(aclk, s_axis_data_tvalid, s_axis_data_tready,
|
||||||
|
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[39:0]" */;
|
||||||
|
input aclk;
|
||||||
|
input s_axis_data_tvalid;
|
||||||
|
output s_axis_data_tready;
|
||||||
|
input [15:0]s_axis_data_tdata;
|
||||||
|
output m_axis_data_tvalid;
|
||||||
|
output [39:0]m_axis_data_tdata;
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,35 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
-- Date : Tue Mar 21 16:04:39 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- d:/vivado-git/projects/datalink_814/dl814_dj_48m/ip/lpf_125k/lpf_125k_stub.vhdl
|
||||||
|
-- Design : lpf_125k
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity lpf_125k is
|
||||||
|
Port (
|
||||||
|
aclk : in STD_LOGIC;
|
||||||
|
s_axis_data_tvalid : in STD_LOGIC;
|
||||||
|
s_axis_data_tready : out STD_LOGIC;
|
||||||
|
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
m_axis_data_tvalid : out STD_LOGIC;
|
||||||
|
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 39 downto 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end lpf_125k;
|
||||||
|
|
||||||
|
architecture stub of lpf_125k is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[39:0]";
|
||||||
|
attribute x_core_info : string;
|
||||||
|
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
@@ -0,0 +1,281 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||||
|
-- IP Revision: 12
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
LIBRARY fir_compiler_v7_2_12;
|
||||||
|
USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
|
||||||
|
|
||||||
|
ENTITY lpf_125k IS
|
||||||
|
PORT (
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
s_axis_data_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_data_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||||
|
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END lpf_125k;
|
||||||
|
|
||||||
|
ARCHITECTURE lpf_125k_arch OF lpf_125k IS
|
||||||
|
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||||
|
ATTRIBUTE DowngradeIPIdentifiedWarnings OF lpf_125k_arch: ARCHITECTURE IS "yes";
|
||||||
|
COMPONENT fir_compiler_v7_2_12 IS
|
||||||
|
GENERIC (
|
||||||
|
C_XDEVICEFAMILY : STRING;
|
||||||
|
C_ELABORATION_DIR : STRING;
|
||||||
|
C_COMPONENT_NAME : STRING;
|
||||||
|
C_COEF_FILE : STRING;
|
||||||
|
C_COEF_FILE_LINES : INTEGER;
|
||||||
|
C_FILTER_TYPE : INTEGER;
|
||||||
|
C_INTERP_RATE : INTEGER;
|
||||||
|
C_DECIM_RATE : INTEGER;
|
||||||
|
C_ZERO_PACKING_FACTOR : INTEGER;
|
||||||
|
C_SYMMETRY : INTEGER;
|
||||||
|
C_NUM_FILTS : INTEGER;
|
||||||
|
C_NUM_TAPS : INTEGER;
|
||||||
|
C_NUM_CHANNELS : INTEGER;
|
||||||
|
C_CHANNEL_PATTERN : STRING;
|
||||||
|
C_ROUND_MODE : INTEGER;
|
||||||
|
C_COEF_RELOAD : INTEGER;
|
||||||
|
C_NUM_RELOAD_SLOTS : INTEGER;
|
||||||
|
C_COL_MODE : INTEGER;
|
||||||
|
C_COL_PIPE_LEN : INTEGER;
|
||||||
|
C_COL_CONFIG : STRING;
|
||||||
|
C_OPTIMIZATION : INTEGER;
|
||||||
|
C_DATA_PATH_WIDTHS : STRING;
|
||||||
|
C_DATA_IP_PATH_WIDTHS : STRING;
|
||||||
|
C_DATA_PX_PATH_WIDTHS : STRING;
|
||||||
|
C_DATA_WIDTH : INTEGER;
|
||||||
|
C_COEF_PATH_WIDTHS : STRING;
|
||||||
|
C_COEF_WIDTH : INTEGER;
|
||||||
|
C_DATA_PATH_SRC : STRING;
|
||||||
|
C_COEF_PATH_SRC : STRING;
|
||||||
|
C_PX_PATH_SRC : STRING;
|
||||||
|
C_DATA_PATH_SIGN : STRING;
|
||||||
|
C_COEF_PATH_SIGN : STRING;
|
||||||
|
C_ACCUM_PATH_WIDTHS : STRING;
|
||||||
|
C_OUTPUT_WIDTH : INTEGER;
|
||||||
|
C_OUTPUT_PATH_WIDTHS : STRING;
|
||||||
|
C_ACCUM_OP_PATH_WIDTHS : STRING;
|
||||||
|
C_EXT_MULT_CNFG : STRING;
|
||||||
|
C_DATA_PATH_PSAMP_SRC : STRING;
|
||||||
|
C_OP_PATH_PSAMP_SRC : STRING;
|
||||||
|
C_NUM_MADDS : INTEGER;
|
||||||
|
C_OPT_MADDS : STRING;
|
||||||
|
C_OVERSAMPLING_RATE : INTEGER;
|
||||||
|
C_INPUT_RATE : INTEGER;
|
||||||
|
C_OUTPUT_RATE : INTEGER;
|
||||||
|
C_DATA_MEMTYPE : INTEGER;
|
||||||
|
C_COEF_MEMTYPE : INTEGER;
|
||||||
|
C_IPBUFF_MEMTYPE : INTEGER;
|
||||||
|
C_OPBUFF_MEMTYPE : INTEGER;
|
||||||
|
C_DATAPATH_MEMTYPE : INTEGER;
|
||||||
|
C_MEM_ARRANGEMENT : INTEGER;
|
||||||
|
C_DATA_MEM_PACKING : INTEGER;
|
||||||
|
C_COEF_MEM_PACKING : INTEGER;
|
||||||
|
C_FILTS_PACKED : INTEGER;
|
||||||
|
C_LATENCY : INTEGER;
|
||||||
|
C_HAS_ARESETn : INTEGER;
|
||||||
|
C_HAS_ACLKEN : INTEGER;
|
||||||
|
C_DATA_HAS_TLAST : INTEGER;
|
||||||
|
C_S_DATA_HAS_FIFO : INTEGER;
|
||||||
|
C_S_DATA_HAS_TUSER : INTEGER;
|
||||||
|
C_S_DATA_TDATA_WIDTH : INTEGER;
|
||||||
|
C_S_DATA_TUSER_WIDTH : INTEGER;
|
||||||
|
C_M_DATA_HAS_TREADY : INTEGER;
|
||||||
|
C_M_DATA_HAS_TUSER : INTEGER;
|
||||||
|
C_M_DATA_TDATA_WIDTH : INTEGER;
|
||||||
|
C_M_DATA_TUSER_WIDTH : INTEGER;
|
||||||
|
C_HAS_CONFIG_CHANNEL : INTEGER;
|
||||||
|
C_CONFIG_SYNC_MODE : INTEGER;
|
||||||
|
C_CONFIG_PACKET_SIZE : INTEGER;
|
||||||
|
C_CONFIG_TDATA_WIDTH : INTEGER;
|
||||||
|
C_RELOAD_TDATA_WIDTH : INTEGER
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
aresetn : IN STD_LOGIC;
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
aclken : IN STD_LOGIC;
|
||||||
|
s_axis_data_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_data_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_data_tlast : IN STD_LOGIC;
|
||||||
|
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||||
|
s_axis_config_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_config_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_config_tlast : IN STD_LOGIC;
|
||||||
|
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
s_axis_reload_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_reload_tready : OUT STD_LOGIC;
|
||||||
|
s_axis_reload_tlast : IN STD_LOGIC;
|
||||||
|
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_data_tready : IN STD_LOGIC;
|
||||||
|
m_axis_data_tlast : OUT STD_LOGIC;
|
||||||
|
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||||
|
event_s_data_tlast_missing : OUT STD_LOGIC;
|
||||||
|
event_s_data_tlast_unexpected : OUT STD_LOGIC;
|
||||||
|
event_s_data_chanid_incorrect : OUT STD_LOGIC;
|
||||||
|
event_s_config_tlast_missing : OUT STD_LOGIC;
|
||||||
|
event_s_config_tlast_unexpected : OUT STD_LOGIC;
|
||||||
|
event_s_reload_tlast_missing : OUT STD_LOGIC;
|
||||||
|
event_s_reload_tlast_unexpected : OUT STD_LOGIC
|
||||||
|
);
|
||||||
|
END COMPONENT fir_compiler_v7_2_12;
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 5, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||||
|
BEGIN
|
||||||
|
U0 : fir_compiler_v7_2_12
|
||||||
|
GENERIC MAP (
|
||||||
|
C_XDEVICEFAMILY => "zynq",
|
||||||
|
C_ELABORATION_DIR => "./",
|
||||||
|
C_COMPONENT_NAME => "lpf_125k",
|
||||||
|
C_COEF_FILE => "lpf_125k.mif",
|
||||||
|
C_COEF_FILE_LINES => 1088,
|
||||||
|
C_FILTER_TYPE => 2,
|
||||||
|
C_INTERP_RATE => 64,
|
||||||
|
C_DECIM_RATE => 25,
|
||||||
|
C_ZERO_PACKING_FACTOR => 1,
|
||||||
|
C_SYMMETRY => 0,
|
||||||
|
C_NUM_FILTS => 1,
|
||||||
|
C_NUM_TAPS => 1025,
|
||||||
|
C_NUM_CHANNELS => 1,
|
||||||
|
C_CHANNEL_PATTERN => "fixed",
|
||||||
|
C_ROUND_MODE => 0,
|
||||||
|
C_COEF_RELOAD => 0,
|
||||||
|
C_NUM_RELOAD_SLOTS => 1,
|
||||||
|
C_COL_MODE => 1,
|
||||||
|
C_COL_PIPE_LEN => 4,
|
||||||
|
C_COL_CONFIG => "17",
|
||||||
|
C_OPTIMIZATION => 0,
|
||||||
|
C_DATA_PATH_WIDTHS => "16",
|
||||||
|
C_DATA_IP_PATH_WIDTHS => "16",
|
||||||
|
C_DATA_PX_PATH_WIDTHS => "16",
|
||||||
|
C_DATA_WIDTH => 16,
|
||||||
|
C_COEF_PATH_WIDTHS => "16",
|
||||||
|
C_COEF_WIDTH => 16,
|
||||||
|
C_DATA_PATH_SRC => "0",
|
||||||
|
C_COEF_PATH_SRC => "0",
|
||||||
|
C_PX_PATH_SRC => "0",
|
||||||
|
C_DATA_PATH_SIGN => "0",
|
||||||
|
C_COEF_PATH_SIGN => "0",
|
||||||
|
C_ACCUM_PATH_WIDTHS => "33",
|
||||||
|
C_OUTPUT_WIDTH => 33,
|
||||||
|
C_OUTPUT_PATH_WIDTHS => "33",
|
||||||
|
C_ACCUM_OP_PATH_WIDTHS => "33",
|
||||||
|
C_EXT_MULT_CNFG => "none",
|
||||||
|
C_DATA_PATH_PSAMP_SRC => "0",
|
||||||
|
C_OP_PATH_PSAMP_SRC => "0",
|
||||||
|
C_NUM_MADDS => 17,
|
||||||
|
C_OPT_MADDS => "none",
|
||||||
|
C_OVERSAMPLING_RATE => 1,
|
||||||
|
C_INPUT_RATE => 2,
|
||||||
|
C_OUTPUT_RATE => 1,
|
||||||
|
C_DATA_MEMTYPE => 0,
|
||||||
|
C_COEF_MEMTYPE => 2,
|
||||||
|
C_IPBUFF_MEMTYPE => 0,
|
||||||
|
C_OPBUFF_MEMTYPE => 0,
|
||||||
|
C_DATAPATH_MEMTYPE => 0,
|
||||||
|
C_MEM_ARRANGEMENT => 2,
|
||||||
|
C_DATA_MEM_PACKING => 0,
|
||||||
|
C_COEF_MEM_PACKING => 0,
|
||||||
|
C_FILTS_PACKED => 0,
|
||||||
|
C_LATENCY => 23,
|
||||||
|
C_HAS_ARESETn => 0,
|
||||||
|
C_HAS_ACLKEN => 0,
|
||||||
|
C_DATA_HAS_TLAST => 0,
|
||||||
|
C_S_DATA_HAS_FIFO => 0,
|
||||||
|
C_S_DATA_HAS_TUSER => 0,
|
||||||
|
C_S_DATA_TDATA_WIDTH => 16,
|
||||||
|
C_S_DATA_TUSER_WIDTH => 1,
|
||||||
|
C_M_DATA_HAS_TREADY => 0,
|
||||||
|
C_M_DATA_HAS_TUSER => 0,
|
||||||
|
C_M_DATA_TDATA_WIDTH => 40,
|
||||||
|
C_M_DATA_TUSER_WIDTH => 1,
|
||||||
|
C_HAS_CONFIG_CHANNEL => 0,
|
||||||
|
C_CONFIG_SYNC_MODE => 0,
|
||||||
|
C_CONFIG_PACKET_SIZE => 0,
|
||||||
|
C_CONFIG_TDATA_WIDTH => 1,
|
||||||
|
C_RELOAD_TDATA_WIDTH => 1
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
aresetn => '1',
|
||||||
|
aclk => aclk,
|
||||||
|
aclken => '1',
|
||||||
|
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||||
|
s_axis_data_tready => s_axis_data_tready,
|
||||||
|
s_axis_data_tlast => '0',
|
||||||
|
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
s_axis_data_tdata => s_axis_data_tdata,
|
||||||
|
s_axis_config_tvalid => '0',
|
||||||
|
s_axis_config_tlast => '0',
|
||||||
|
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
s_axis_reload_tvalid => '0',
|
||||||
|
s_axis_reload_tlast => '0',
|
||||||
|
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||||
|
m_axis_data_tready => '1',
|
||||||
|
m_axis_data_tdata => m_axis_data_tdata
|
||||||
|
);
|
||||||
|
END lpf_125k_arch;
|
||||||
@@ -0,0 +1,92 @@
|
|||||||
|
|
||||||
|
// file: sig_clk_gen.v
|
||||||
|
//
|
||||||
|
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// User entered comments
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// None
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||||
|
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// clk_out1____48.000______0.000______50.0______172.739____111.288
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// __primary__________122.88____________0.010
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
(* CORE_GENERATION_INFO = "sig_clk_gen,clk_wiz_v6_0_3_0_0,{component_name=sig_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=8.138,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||||
|
|
||||||
|
module sig_clk_gen
|
||||||
|
(
|
||||||
|
// Clock out ports
|
||||||
|
output clk_out1,
|
||||||
|
// Status and control signals
|
||||||
|
input reset,
|
||||||
|
output locked,
|
||||||
|
// Clock in ports
|
||||||
|
input clk_in1
|
||||||
|
);
|
||||||
|
|
||||||
|
sig_clk_gen_clk_wiz inst
|
||||||
|
(
|
||||||
|
// Clock out ports
|
||||||
|
.clk_out1(clk_out1),
|
||||||
|
// Status and control signals
|
||||||
|
.reset(reset),
|
||||||
|
.locked(locked),
|
||||||
|
// Clock in ports
|
||||||
|
.clk_in1(clk_in1)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,80 @@
|
|||||||
|
|
||||||
|
//
|
||||||
|
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// User entered comments
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// None
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||||
|
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// clk_out1____48.000______0.000______50.0______172.739____111.288
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// __primary__________122.88____________0.010
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
|
||||||
|
sig_clk_gen instance_name
|
||||||
|
(
|
||||||
|
// Clock out ports
|
||||||
|
.clk_out1(clk_out1), // output clk_out1
|
||||||
|
// Status and control signals
|
||||||
|
.reset(reset), // input reset
|
||||||
|
.locked(locked), // output locked
|
||||||
|
// Clock in ports
|
||||||
|
.clk_in1(clk_in1)); // input clk_in1
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
+204
@@ -0,0 +1,204 @@
|
|||||||
|
|
||||||
|
// file: sig_clk_gen.v
|
||||||
|
//
|
||||||
|
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// User entered comments
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// None
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||||
|
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// clk_out1____48.000______0.000______50.0______172.739____111.288
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// __primary__________122.88____________0.010
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module sig_clk_gen_clk_wiz
|
||||||
|
|
||||||
|
(// Clock in ports
|
||||||
|
// Clock out ports
|
||||||
|
output clk_out1,
|
||||||
|
// Status and control signals
|
||||||
|
input reset,
|
||||||
|
output locked,
|
||||||
|
input clk_in1
|
||||||
|
);
|
||||||
|
// Input buffering
|
||||||
|
//------------------------------------
|
||||||
|
wire clk_in1_sig_clk_gen;
|
||||||
|
wire clk_in2_sig_clk_gen;
|
||||||
|
BUFG clkin1_bufg
|
||||||
|
(.O (clk_in1_sig_clk_gen),
|
||||||
|
.I (clk_in1));
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
// Clocking PRIMITIVE
|
||||||
|
//------------------------------------
|
||||||
|
|
||||||
|
// Instantiation of the MMCM PRIMITIVE
|
||||||
|
// * Unused inputs are tied off
|
||||||
|
// * Unused outputs are labeled unused
|
||||||
|
|
||||||
|
wire clk_out1_sig_clk_gen;
|
||||||
|
wire clk_out2_sig_clk_gen;
|
||||||
|
wire clk_out3_sig_clk_gen;
|
||||||
|
wire clk_out4_sig_clk_gen;
|
||||||
|
wire clk_out5_sig_clk_gen;
|
||||||
|
wire clk_out6_sig_clk_gen;
|
||||||
|
wire clk_out7_sig_clk_gen;
|
||||||
|
|
||||||
|
wire [15:0] do_unused;
|
||||||
|
wire drdy_unused;
|
||||||
|
wire psdone_unused;
|
||||||
|
wire locked_int;
|
||||||
|
wire clkfbout_sig_clk_gen;
|
||||||
|
wire clkfbout_buf_sig_clk_gen;
|
||||||
|
wire clkfboutb_unused;
|
||||||
|
wire clkout0b_unused;
|
||||||
|
wire clkout1_unused;
|
||||||
|
wire clkout1b_unused;
|
||||||
|
wire clkout2_unused;
|
||||||
|
wire clkout2b_unused;
|
||||||
|
wire clkout3_unused;
|
||||||
|
wire clkout3b_unused;
|
||||||
|
wire clkout4_unused;
|
||||||
|
wire clkout5_unused;
|
||||||
|
wire clkout6_unused;
|
||||||
|
wire clkfbstopped_unused;
|
||||||
|
wire clkinstopped_unused;
|
||||||
|
wire reset_high;
|
||||||
|
|
||||||
|
MMCME2_ADV
|
||||||
|
#(.BANDWIDTH ("OPTIMIZED"),
|
||||||
|
.CLKOUT4_CASCADE ("FALSE"),
|
||||||
|
.COMPENSATION ("ZHOLD"),
|
||||||
|
.STARTUP_WAIT ("FALSE"),
|
||||||
|
.DIVCLK_DIVIDE (2),
|
||||||
|
.CLKFBOUT_MULT_F (15.625),
|
||||||
|
.CLKFBOUT_PHASE (0.000),
|
||||||
|
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||||
|
.CLKOUT0_DIVIDE_F (20.000),
|
||||||
|
.CLKOUT0_PHASE (0.000),
|
||||||
|
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||||
|
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||||
|
.CLKIN1_PERIOD (8.138))
|
||||||
|
mmcm_adv_inst
|
||||||
|
// Output clocks
|
||||||
|
(
|
||||||
|
.CLKFBOUT (clkfbout_sig_clk_gen),
|
||||||
|
.CLKFBOUTB (clkfboutb_unused),
|
||||||
|
.CLKOUT0 (clk_out1_sig_clk_gen),
|
||||||
|
.CLKOUT0B (clkout0b_unused),
|
||||||
|
.CLKOUT1 (clkout1_unused),
|
||||||
|
.CLKOUT1B (clkout1b_unused),
|
||||||
|
.CLKOUT2 (clkout2_unused),
|
||||||
|
.CLKOUT2B (clkout2b_unused),
|
||||||
|
.CLKOUT3 (clkout3_unused),
|
||||||
|
.CLKOUT3B (clkout3b_unused),
|
||||||
|
.CLKOUT4 (clkout4_unused),
|
||||||
|
.CLKOUT5 (clkout5_unused),
|
||||||
|
.CLKOUT6 (clkout6_unused),
|
||||||
|
// Input clock control
|
||||||
|
.CLKFBIN (clkfbout_buf_sig_clk_gen),
|
||||||
|
.CLKIN1 (clk_in1_sig_clk_gen),
|
||||||
|
.CLKIN2 (1'b0),
|
||||||
|
// Tied to always select the primary input clock
|
||||||
|
.CLKINSEL (1'b1),
|
||||||
|
// Ports for dynamic reconfiguration
|
||||||
|
.DADDR (7'h0),
|
||||||
|
.DCLK (1'b0),
|
||||||
|
.DEN (1'b0),
|
||||||
|
.DI (16'h0),
|
||||||
|
.DO (do_unused),
|
||||||
|
.DRDY (drdy_unused),
|
||||||
|
.DWE (1'b0),
|
||||||
|
// Ports for dynamic phase shift
|
||||||
|
.PSCLK (1'b0),
|
||||||
|
.PSEN (1'b0),
|
||||||
|
.PSINCDEC (1'b0),
|
||||||
|
.PSDONE (psdone_unused),
|
||||||
|
// Other control and status signals
|
||||||
|
.LOCKED (locked_int),
|
||||||
|
.CLKINSTOPPED (clkinstopped_unused),
|
||||||
|
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||||
|
.PWRDWN (1'b0),
|
||||||
|
.RST (reset_high));
|
||||||
|
assign reset_high = reset;
|
||||||
|
|
||||||
|
assign locked = locked_int;
|
||||||
|
// Clock Monitor clock assigning
|
||||||
|
//--------------------------------------
|
||||||
|
// Output buffering
|
||||||
|
//-----------------------------------
|
||||||
|
|
||||||
|
BUFG clkf_buf
|
||||||
|
(.O (clkfbout_buf_sig_clk_gen),
|
||||||
|
.I (clkfbout_sig_clk_gen));
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
BUFG clkout1_buf
|
||||||
|
(.O (clk_out1),
|
||||||
|
.I (clk_out1_sig_clk_gen));
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
+240
@@ -0,0 +1,240 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
// Date : Tue Mar 21 14:52:21 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode funcsim
|
||||||
|
// D:/vivado-git/projects/datalink_814/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/sig_clk_gen_synth_1/sig_clk_gen_sim_netlist.v
|
||||||
|
// Design : sig_clk_gen
|
||||||
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
(* NotValidForBitStream *)
|
||||||
|
module sig_clk_gen
|
||||||
|
(clk_out1,
|
||||||
|
reset,
|
||||||
|
locked,
|
||||||
|
clk_in1);
|
||||||
|
output clk_out1;
|
||||||
|
input reset;
|
||||||
|
output locked;
|
||||||
|
input clk_in1;
|
||||||
|
|
||||||
|
wire clk_in1;
|
||||||
|
wire clk_out1;
|
||||||
|
wire locked;
|
||||||
|
wire reset;
|
||||||
|
|
||||||
|
sig_clk_gen_sig_clk_gen_clk_wiz inst
|
||||||
|
(.clk_in1(clk_in1),
|
||||||
|
.clk_out1(clk_out1),
|
||||||
|
.locked(locked),
|
||||||
|
.reset(reset));
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
(* ORIG_REF_NAME = "sig_clk_gen_clk_wiz" *)
|
||||||
|
module sig_clk_gen_sig_clk_gen_clk_wiz
|
||||||
|
(clk_out1,
|
||||||
|
reset,
|
||||||
|
locked,
|
||||||
|
clk_in1);
|
||||||
|
output clk_out1;
|
||||||
|
input reset;
|
||||||
|
output locked;
|
||||||
|
input clk_in1;
|
||||||
|
|
||||||
|
wire clk_in1;
|
||||||
|
wire clk_in1_sig_clk_gen;
|
||||||
|
wire clk_out1;
|
||||||
|
wire clk_out1_sig_clk_gen;
|
||||||
|
wire clkfbout_buf_sig_clk_gen;
|
||||||
|
wire clkfbout_sig_clk_gen;
|
||||||
|
wire locked;
|
||||||
|
wire reset;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
|
||||||
|
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
|
||||||
|
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
|
||||||
|
|
||||||
|
(* BOX_TYPE = "PRIMITIVE" *)
|
||||||
|
BUFG clkf_buf
|
||||||
|
(.I(clkfbout_sig_clk_gen),
|
||||||
|
.O(clkfbout_buf_sig_clk_gen));
|
||||||
|
(* BOX_TYPE = "PRIMITIVE" *)
|
||||||
|
BUFG clkin1_bufg
|
||||||
|
(.I(clk_in1),
|
||||||
|
.O(clk_in1_sig_clk_gen));
|
||||||
|
(* BOX_TYPE = "PRIMITIVE" *)
|
||||||
|
BUFG clkout1_buf
|
||||||
|
(.I(clk_out1_sig_clk_gen),
|
||||||
|
.O(clk_out1));
|
||||||
|
(* BOX_TYPE = "PRIMITIVE" *)
|
||||||
|
MMCME2_ADV #(
|
||||||
|
.BANDWIDTH("OPTIMIZED"),
|
||||||
|
.CLKFBOUT_MULT_F(15.625000),
|
||||||
|
.CLKFBOUT_PHASE(0.000000),
|
||||||
|
.CLKFBOUT_USE_FINE_PS("FALSE"),
|
||||||
|
.CLKIN1_PERIOD(8.138000),
|
||||||
|
.CLKIN2_PERIOD(0.000000),
|
||||||
|
.CLKOUT0_DIVIDE_F(20.000000),
|
||||||
|
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT0_PHASE(0.000000),
|
||||||
|
.CLKOUT0_USE_FINE_PS("FALSE"),
|
||||||
|
.CLKOUT1_DIVIDE(1),
|
||||||
|
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT1_PHASE(0.000000),
|
||||||
|
.CLKOUT1_USE_FINE_PS("FALSE"),
|
||||||
|
.CLKOUT2_DIVIDE(1),
|
||||||
|
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT2_PHASE(0.000000),
|
||||||
|
.CLKOUT2_USE_FINE_PS("FALSE"),
|
||||||
|
.CLKOUT3_DIVIDE(1),
|
||||||
|
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT3_PHASE(0.000000),
|
||||||
|
.CLKOUT3_USE_FINE_PS("FALSE"),
|
||||||
|
.CLKOUT4_CASCADE("FALSE"),
|
||||||
|
.CLKOUT4_DIVIDE(1),
|
||||||
|
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT4_PHASE(0.000000),
|
||||||
|
.CLKOUT4_USE_FINE_PS("FALSE"),
|
||||||
|
.CLKOUT5_DIVIDE(1),
|
||||||
|
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT5_PHASE(0.000000),
|
||||||
|
.CLKOUT5_USE_FINE_PS("FALSE"),
|
||||||
|
.CLKOUT6_DIVIDE(1),
|
||||||
|
.CLKOUT6_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT6_PHASE(0.000000),
|
||||||
|
.CLKOUT6_USE_FINE_PS("FALSE"),
|
||||||
|
.COMPENSATION("BUF_IN"),
|
||||||
|
.DIVCLK_DIVIDE(2),
|
||||||
|
.IS_CLKINSEL_INVERTED(1'b0),
|
||||||
|
.IS_PSEN_INVERTED(1'b0),
|
||||||
|
.IS_PSINCDEC_INVERTED(1'b0),
|
||||||
|
.IS_PWRDWN_INVERTED(1'b0),
|
||||||
|
.IS_RST_INVERTED(1'b0),
|
||||||
|
.REF_JITTER1(0.010000),
|
||||||
|
.REF_JITTER2(0.010000),
|
||||||
|
.SS_EN("FALSE"),
|
||||||
|
.SS_MODE("CENTER_HIGH"),
|
||||||
|
.SS_MOD_PERIOD(10000),
|
||||||
|
.STARTUP_WAIT("FALSE"))
|
||||||
|
mmcm_adv_inst
|
||||||
|
(.CLKFBIN(clkfbout_buf_sig_clk_gen),
|
||||||
|
.CLKFBOUT(clkfbout_sig_clk_gen),
|
||||||
|
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
|
||||||
|
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
|
||||||
|
.CLKIN1(clk_in1_sig_clk_gen),
|
||||||
|
.CLKIN2(1'b0),
|
||||||
|
.CLKINSEL(1'b1),
|
||||||
|
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
|
||||||
|
.CLKOUT0(clk_out1_sig_clk_gen),
|
||||||
|
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
|
||||||
|
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
|
||||||
|
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
|
||||||
|
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
|
||||||
|
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
|
||||||
|
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
|
||||||
|
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
|
||||||
|
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
|
||||||
|
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
|
||||||
|
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
|
||||||
|
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.DCLK(1'b0),
|
||||||
|
.DEN(1'b0),
|
||||||
|
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
|
||||||
|
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
|
||||||
|
.DWE(1'b0),
|
||||||
|
.LOCKED(locked),
|
||||||
|
.PSCLK(1'b0),
|
||||||
|
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
|
||||||
|
.PSEN(1'b0),
|
||||||
|
.PSINCDEC(1'b0),
|
||||||
|
.PWRDWN(1'b0),
|
||||||
|
.RST(reset));
|
||||||
|
endmodule
|
||||||
|
`ifndef GLBL
|
||||||
|
`define GLBL
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module glbl ();
|
||||||
|
|
||||||
|
parameter ROC_WIDTH = 100000;
|
||||||
|
parameter TOC_WIDTH = 0;
|
||||||
|
|
||||||
|
//-------- STARTUP Globals --------------
|
||||||
|
wire GSR;
|
||||||
|
wire GTS;
|
||||||
|
wire GWE;
|
||||||
|
wire PRLD;
|
||||||
|
tri1 p_up_tmp;
|
||||||
|
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||||
|
|
||||||
|
wire PROGB_GLBL;
|
||||||
|
wire CCLKO_GLBL;
|
||||||
|
wire FCSBO_GLBL;
|
||||||
|
wire [3:0] DO_GLBL;
|
||||||
|
wire [3:0] DI_GLBL;
|
||||||
|
|
||||||
|
reg GSR_int;
|
||||||
|
reg GTS_int;
|
||||||
|
reg PRLD_int;
|
||||||
|
|
||||||
|
//-------- JTAG Globals --------------
|
||||||
|
wire JTAG_TDO_GLBL;
|
||||||
|
wire JTAG_TCK_GLBL;
|
||||||
|
wire JTAG_TDI_GLBL;
|
||||||
|
wire JTAG_TMS_GLBL;
|
||||||
|
wire JTAG_TRST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_CAPTURE_GLBL;
|
||||||
|
reg JTAG_RESET_GLBL;
|
||||||
|
reg JTAG_SHIFT_GLBL;
|
||||||
|
reg JTAG_UPDATE_GLBL;
|
||||||
|
reg JTAG_RUNTEST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_SEL1_GLBL = 0;
|
||||||
|
reg JTAG_SEL2_GLBL = 0 ;
|
||||||
|
reg JTAG_SEL3_GLBL = 0;
|
||||||
|
reg JTAG_SEL4_GLBL = 0;
|
||||||
|
|
||||||
|
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||||
|
|
||||||
|
assign (strong1, weak0) GSR = GSR_int;
|
||||||
|
assign (strong1, weak0) GTS = GTS_int;
|
||||||
|
assign (weak1, weak0) PRLD = PRLD_int;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GSR_int = 1'b1;
|
||||||
|
PRLD_int = 1'b1;
|
||||||
|
#(ROC_WIDTH)
|
||||||
|
GSR_int = 1'b0;
|
||||||
|
PRLD_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GTS_int = 1'b1;
|
||||||
|
#(TOC_WIDTH)
|
||||||
|
GTS_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
+181
@@ -0,0 +1,181 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
-- Date : Tue Mar 21 14:52:21 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode funcsim
|
||||||
|
-- D:/vivado-git/projects/datalink_814/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/sig_clk_gen_synth_1/sig_clk_gen_sim_netlist.vhdl
|
||||||
|
-- Design : sig_clk_gen
|
||||||
|
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||||
|
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
library UNISIM;
|
||||||
|
use UNISIM.VCOMPONENTS.ALL;
|
||||||
|
entity sig_clk_gen_sig_clk_gen_clk_wiz is
|
||||||
|
port (
|
||||||
|
clk_out1 : out STD_LOGIC;
|
||||||
|
reset : in STD_LOGIC;
|
||||||
|
locked : out STD_LOGIC;
|
||||||
|
clk_in1 : in STD_LOGIC
|
||||||
|
);
|
||||||
|
attribute ORIG_REF_NAME : string;
|
||||||
|
attribute ORIG_REF_NAME of sig_clk_gen_sig_clk_gen_clk_wiz : entity is "sig_clk_gen_clk_wiz";
|
||||||
|
end sig_clk_gen_sig_clk_gen_clk_wiz;
|
||||||
|
|
||||||
|
architecture STRUCTURE of sig_clk_gen_sig_clk_gen_clk_wiz is
|
||||||
|
signal clk_in1_sig_clk_gen : STD_LOGIC;
|
||||||
|
signal clk_out1_sig_clk_gen : STD_LOGIC;
|
||||||
|
signal clkfbout_buf_sig_clk_gen : STD_LOGIC;
|
||||||
|
signal clkfbout_sig_clk_gen : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||||
|
attribute BOX_TYPE : string;
|
||||||
|
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
|
||||||
|
attribute BOX_TYPE of clkin1_bufg : label is "PRIMITIVE";
|
||||||
|
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
|
||||||
|
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
|
||||||
|
begin
|
||||||
|
clkf_buf: unisim.vcomponents.BUFG
|
||||||
|
port map (
|
||||||
|
I => clkfbout_sig_clk_gen,
|
||||||
|
O => clkfbout_buf_sig_clk_gen
|
||||||
|
);
|
||||||
|
clkin1_bufg: unisim.vcomponents.BUFG
|
||||||
|
port map (
|
||||||
|
I => clk_in1,
|
||||||
|
O => clk_in1_sig_clk_gen
|
||||||
|
);
|
||||||
|
clkout1_buf: unisim.vcomponents.BUFG
|
||||||
|
port map (
|
||||||
|
I => clk_out1_sig_clk_gen,
|
||||||
|
O => clk_out1
|
||||||
|
);
|
||||||
|
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
|
||||||
|
generic map(
|
||||||
|
BANDWIDTH => "OPTIMIZED",
|
||||||
|
CLKFBOUT_MULT_F => 15.625000,
|
||||||
|
CLKFBOUT_PHASE => 0.000000,
|
||||||
|
CLKFBOUT_USE_FINE_PS => false,
|
||||||
|
CLKIN1_PERIOD => 8.138000,
|
||||||
|
CLKIN2_PERIOD => 0.000000,
|
||||||
|
CLKOUT0_DIVIDE_F => 20.000000,
|
||||||
|
CLKOUT0_DUTY_CYCLE => 0.500000,
|
||||||
|
CLKOUT0_PHASE => 0.000000,
|
||||||
|
CLKOUT0_USE_FINE_PS => false,
|
||||||
|
CLKOUT1_DIVIDE => 1,
|
||||||
|
CLKOUT1_DUTY_CYCLE => 0.500000,
|
||||||
|
CLKOUT1_PHASE => 0.000000,
|
||||||
|
CLKOUT1_USE_FINE_PS => false,
|
||||||
|
CLKOUT2_DIVIDE => 1,
|
||||||
|
CLKOUT2_DUTY_CYCLE => 0.500000,
|
||||||
|
CLKOUT2_PHASE => 0.000000,
|
||||||
|
CLKOUT2_USE_FINE_PS => false,
|
||||||
|
CLKOUT3_DIVIDE => 1,
|
||||||
|
CLKOUT3_DUTY_CYCLE => 0.500000,
|
||||||
|
CLKOUT3_PHASE => 0.000000,
|
||||||
|
CLKOUT3_USE_FINE_PS => false,
|
||||||
|
CLKOUT4_CASCADE => false,
|
||||||
|
CLKOUT4_DIVIDE => 1,
|
||||||
|
CLKOUT4_DUTY_CYCLE => 0.500000,
|
||||||
|
CLKOUT4_PHASE => 0.000000,
|
||||||
|
CLKOUT4_USE_FINE_PS => false,
|
||||||
|
CLKOUT5_DIVIDE => 1,
|
||||||
|
CLKOUT5_DUTY_CYCLE => 0.500000,
|
||||||
|
CLKOUT5_PHASE => 0.000000,
|
||||||
|
CLKOUT5_USE_FINE_PS => false,
|
||||||
|
CLKOUT6_DIVIDE => 1,
|
||||||
|
CLKOUT6_DUTY_CYCLE => 0.500000,
|
||||||
|
CLKOUT6_PHASE => 0.000000,
|
||||||
|
CLKOUT6_USE_FINE_PS => false,
|
||||||
|
COMPENSATION => "BUF_IN",
|
||||||
|
DIVCLK_DIVIDE => 2,
|
||||||
|
IS_CLKINSEL_INVERTED => '0',
|
||||||
|
IS_PSEN_INVERTED => '0',
|
||||||
|
IS_PSINCDEC_INVERTED => '0',
|
||||||
|
IS_PWRDWN_INVERTED => '0',
|
||||||
|
IS_RST_INVERTED => '0',
|
||||||
|
REF_JITTER1 => 0.010000,
|
||||||
|
REF_JITTER2 => 0.010000,
|
||||||
|
SS_EN => "FALSE",
|
||||||
|
SS_MODE => "CENTER_HIGH",
|
||||||
|
SS_MOD_PERIOD => 10000,
|
||||||
|
STARTUP_WAIT => false
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
CLKFBIN => clkfbout_buf_sig_clk_gen,
|
||||||
|
CLKFBOUT => clkfbout_sig_clk_gen,
|
||||||
|
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
|
||||||
|
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
|
||||||
|
CLKIN1 => clk_in1_sig_clk_gen,
|
||||||
|
CLKIN2 => '0',
|
||||||
|
CLKINSEL => '1',
|
||||||
|
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
|
||||||
|
CLKOUT0 => clk_out1_sig_clk_gen,
|
||||||
|
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
|
||||||
|
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
|
||||||
|
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
|
||||||
|
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
|
||||||
|
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
|
||||||
|
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
|
||||||
|
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
|
||||||
|
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
|
||||||
|
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
|
||||||
|
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
|
||||||
|
DADDR(6 downto 0) => B"0000000",
|
||||||
|
DCLK => '0',
|
||||||
|
DEN => '0',
|
||||||
|
DI(15 downto 0) => B"0000000000000000",
|
||||||
|
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
|
||||||
|
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
|
||||||
|
DWE => '0',
|
||||||
|
LOCKED => locked,
|
||||||
|
PSCLK => '0',
|
||||||
|
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
|
||||||
|
PSEN => '0',
|
||||||
|
PSINCDEC => '0',
|
||||||
|
PWRDWN => '0',
|
||||||
|
RST => reset
|
||||||
|
);
|
||||||
|
end STRUCTURE;
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
library UNISIM;
|
||||||
|
use UNISIM.VCOMPONENTS.ALL;
|
||||||
|
entity sig_clk_gen is
|
||||||
|
port (
|
||||||
|
clk_out1 : out STD_LOGIC;
|
||||||
|
reset : in STD_LOGIC;
|
||||||
|
locked : out STD_LOGIC;
|
||||||
|
clk_in1 : in STD_LOGIC
|
||||||
|
);
|
||||||
|
attribute NotValidForBitStream : boolean;
|
||||||
|
attribute NotValidForBitStream of sig_clk_gen : entity is true;
|
||||||
|
end sig_clk_gen;
|
||||||
|
|
||||||
|
architecture STRUCTURE of sig_clk_gen is
|
||||||
|
begin
|
||||||
|
inst: entity work.sig_clk_gen_sig_clk_gen_clk_wiz
|
||||||
|
port map (
|
||||||
|
clk_in1 => clk_in1,
|
||||||
|
clk_out1 => clk_out1,
|
||||||
|
locked => locked,
|
||||||
|
reset => reset
|
||||||
|
);
|
||||||
|
end STRUCTURE;
|
||||||
@@ -0,0 +1,22 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
// Date : Tue Mar 21 14:52:21 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// D:/vivado-git/projects/datalink_814/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/sig_clk_gen_synth_1/sig_clk_gen_stub.v
|
||||||
|
// Design : sig_clk_gen
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
module sig_clk_gen(clk_out1, reset, locked, clk_in1)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clk_out1,reset,locked,clk_in1" */;
|
||||||
|
output clk_out1;
|
||||||
|
input reset;
|
||||||
|
output locked;
|
||||||
|
input clk_in1;
|
||||||
|
endmodule
|
||||||
+31
@@ -0,0 +1,31 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
-- Date : Tue Mar 21 14:52:21 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- D:/vivado-git/projects/datalink_814/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/sig_clk_gen_synth_1/sig_clk_gen_stub.vhdl
|
||||||
|
-- Design : sig_clk_gen
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity sig_clk_gen is
|
||||||
|
Port (
|
||||||
|
clk_out1 : out STD_LOGIC;
|
||||||
|
reset : in STD_LOGIC;
|
||||||
|
locked : out STD_LOGIC;
|
||||||
|
clk_in1 : in STD_LOGIC
|
||||||
|
);
|
||||||
|
|
||||||
|
end sig_clk_gen;
|
||||||
|
|
||||||
|
architecture stub of sig_clk_gen is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
+68
@@ -0,0 +1,68 @@
|
|||||||
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
module vio_manual_ctrl (
|
||||||
|
clk,
|
||||||
|
|
||||||
|
probe_out0,
|
||||||
|
probe_out1,
|
||||||
|
probe_out2,
|
||||||
|
probe_out3,
|
||||||
|
probe_out4
|
||||||
|
);
|
||||||
|
|
||||||
|
input clk;
|
||||||
|
|
||||||
|
output reg [1 : 0] probe_out0 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out1 = 'h0 ;
|
||||||
|
output reg [31 : 0] probe_out2 = 'h00000000 ;
|
||||||
|
output reg [1 : 0] probe_out3 = 'h3 ;
|
||||||
|
output reg [3 : 0] probe_out4 = 'h0 ;
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
+70
@@ -0,0 +1,70 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||||
|
// IP Revision: 20
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
vio_manual_ctrl your_instance_name (
|
||||||
|
.clk(clk), // input wire clk
|
||||||
|
.probe_out0(probe_out0), // output wire [1 : 0] probe_out0
|
||||||
|
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
|
||||||
|
.probe_out2(probe_out2), // output wire [31 : 0] probe_out2
|
||||||
|
.probe_out3(probe_out3), // output wire [1 : 0] probe_out3
|
||||||
|
.probe_out4(probe_out4) // output wire [3 : 0] probe_out4
|
||||||
|
);
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
// You must compile the wrapper file vio_manual_ctrl.v when simulating
|
||||||
|
// the core, vio_manual_ctrl. When compiling the wrapper file, be sure to
|
||||||
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
+85
@@ -0,0 +1,85 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||||
|
-- IP Revision: 20
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture header.
|
||||||
|
|
||||||
|
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||||
|
COMPONENT vio_manual_ctrl
|
||||||
|
PORT (
|
||||||
|
clk : IN STD_LOGIC;
|
||||||
|
probe_out0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||||
|
probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture
|
||||||
|
-- body. Substitute your own instance name and net names.
|
||||||
|
|
||||||
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||||
|
your_instance_name : vio_manual_ctrl
|
||||||
|
PORT MAP (
|
||||||
|
clk => clk,
|
||||||
|
probe_out0 => probe_out0,
|
||||||
|
probe_out1 => probe_out1,
|
||||||
|
probe_out2 => probe_out2,
|
||||||
|
probe_out3 => probe_out3,
|
||||||
|
probe_out4 => probe_out4
|
||||||
|
);
|
||||||
|
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
-- You must compile the wrapper file vio_manual_ctrl.vhd when simulating
|
||||||
|
-- the core, vio_manual_ctrl. When compiling the wrapper file, be sure to
|
||||||
|
-- reference the VHDL simulation library.
|
||||||
|
|
||||||
+9034
File diff suppressed because one or more lines are too long
+13218
File diff suppressed because it is too large
Load Diff
+26
@@ -0,0 +1,26 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
// Date : Fri Mar 17 22:22:39 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
|
||||||
|
// Design : vio_manual_ctrl
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||||
|
module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2,
|
||||||
|
probe_out3, probe_out4)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
|
||||||
|
input clk;
|
||||||
|
output [1:0]probe_out0;
|
||||||
|
output [0:0]probe_out1;
|
||||||
|
output [31:0]probe_out2;
|
||||||
|
output [1:0]probe_out3;
|
||||||
|
output [3:0]probe_out4;
|
||||||
|
endmodule
|
||||||
+35
@@ -0,0 +1,35 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
-- Date : Fri Mar 17 22:22:39 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
|
||||||
|
-- Design : vio_manual_ctrl
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity vio_manual_ctrl is
|
||||||
|
Port (
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
|
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||||
|
probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
|
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end vio_manual_ctrl;
|
||||||
|
|
||||||
|
architecture stub of vio_manual_ctrl is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
|
||||||
|
attribute X_CORE_INFO : string;
|
||||||
|
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
+76
@@ -0,0 +1,76 @@
|
|||||||
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
module vio_rf_control (
|
||||||
|
clk,
|
||||||
|
|
||||||
|
probe_out0,
|
||||||
|
probe_out1,
|
||||||
|
probe_out2,
|
||||||
|
probe_out3,
|
||||||
|
probe_out4,
|
||||||
|
probe_out5,
|
||||||
|
probe_out6,
|
||||||
|
probe_out7,
|
||||||
|
probe_out8
|
||||||
|
);
|
||||||
|
|
||||||
|
input clk;
|
||||||
|
|
||||||
|
output reg [0 : 0] probe_out0 = 'h0 ;
|
||||||
|
output reg [1 : 0] probe_out1 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out2 = 'h0 ;
|
||||||
|
output reg [5 : 0] probe_out3 = 'h08 ;
|
||||||
|
output reg [5 : 0] probe_out4 = 'h38 ;
|
||||||
|
output reg [10 : 0] probe_out5 = 'h3E8 ;
|
||||||
|
output reg [0 : 0] probe_out6 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out7 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out8 = 'h0 ;
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
+74
@@ -0,0 +1,74 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||||
|
// IP Revision: 20
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
vio_rf_control your_instance_name (
|
||||||
|
.clk(clk), // input wire clk
|
||||||
|
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
|
||||||
|
.probe_out1(probe_out1), // output wire [1 : 0] probe_out1
|
||||||
|
.probe_out2(probe_out2), // output wire [0 : 0] probe_out2
|
||||||
|
.probe_out3(probe_out3), // output wire [5 : 0] probe_out3
|
||||||
|
.probe_out4(probe_out4), // output wire [5 : 0] probe_out4
|
||||||
|
.probe_out5(probe_out5), // output wire [10 : 0] probe_out5
|
||||||
|
.probe_out6(probe_out6), // output wire [0 : 0] probe_out6
|
||||||
|
.probe_out7(probe_out7), // output wire [0 : 0] probe_out7
|
||||||
|
.probe_out8(probe_out8) // output wire [0 : 0] probe_out8
|
||||||
|
);
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
// You must compile the wrapper file vio_rf_control.v when simulating
|
||||||
|
// the core, vio_rf_control. When compiling the wrapper file, be sure to
|
||||||
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
+93
@@ -0,0 +1,93 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||||
|
-- IP Revision: 20
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture header.
|
||||||
|
|
||||||
|
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||||
|
COMPONENT vio_rf_control
|
||||||
|
PORT (
|
||||||
|
clk : IN STD_LOGIC;
|
||||||
|
probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out3 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||||
|
probe_out4 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||||
|
probe_out5 : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||||
|
probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture
|
||||||
|
-- body. Substitute your own instance name and net names.
|
||||||
|
|
||||||
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||||
|
your_instance_name : vio_rf_control
|
||||||
|
PORT MAP (
|
||||||
|
clk => clk,
|
||||||
|
probe_out0 => probe_out0,
|
||||||
|
probe_out1 => probe_out1,
|
||||||
|
probe_out2 => probe_out2,
|
||||||
|
probe_out3 => probe_out3,
|
||||||
|
probe_out4 => probe_out4,
|
||||||
|
probe_out5 => probe_out5,
|
||||||
|
probe_out6 => probe_out6,
|
||||||
|
probe_out7 => probe_out7,
|
||||||
|
probe_out8 => probe_out8
|
||||||
|
);
|
||||||
|
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
-- You must compile the wrapper file vio_rf_control.vhd when simulating
|
||||||
|
-- the core, vio_rf_control. When compiling the wrapper file, be sure to
|
||||||
|
-- reference the VHDL simulation library.
|
||||||
|
|
||||||
+8719
File diff suppressed because one or more lines are too long
+12753
File diff suppressed because it is too large
Load Diff
+30
@@ -0,0 +1,30 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
// Date : Fri Mar 17 22:22:40 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v
|
||||||
|
// Design : vio_rf_control
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||||
|
module vio_rf_control(clk, probe_out0, probe_out1, probe_out2,
|
||||||
|
probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]" */;
|
||||||
|
input clk;
|
||||||
|
output [0:0]probe_out0;
|
||||||
|
output [1:0]probe_out1;
|
||||||
|
output [0:0]probe_out2;
|
||||||
|
output [5:0]probe_out3;
|
||||||
|
output [5:0]probe_out4;
|
||||||
|
output [10:0]probe_out5;
|
||||||
|
output [0:0]probe_out6;
|
||||||
|
output [0:0]probe_out7;
|
||||||
|
output [0:0]probe_out8;
|
||||||
|
endmodule
|
||||||
+39
@@ -0,0 +1,39 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||||
|
-- Date : Fri Mar 17 22:22:40 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl
|
||||||
|
-- Design : vio_rf_control
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity vio_rf_control is
|
||||||
|
Port (
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
|
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||||
|
probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||||
|
probe_out5 : out STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||||
|
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end vio_rf_control;
|
||||||
|
|
||||||
|
architecture stub of vio_rf_control is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]";
|
||||||
|
attribute X_CORE_INFO : string;
|
||||||
|
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
+3821
File diff suppressed because it is too large
Load Diff
+12017
File diff suppressed because it is too large
Load Diff
+27417
File diff suppressed because it is too large
Load Diff
+7759
File diff suppressed because it is too large
Load Diff
+18807
File diff suppressed because it is too large
Load Diff
+55945
File diff suppressed because it is too large
Load Diff
+17045
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user