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Optimize project dir structure, add dl814_k7 proj.

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This commit is contained in:
josh
2023-03-19 10:31:23 +08:00
parent 5965eba577
commit 454606fac2
3718 changed files with 7735502 additions and 134 deletions
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modules/xc7k410tffg900-2/ad9361_mapping/.gitignore
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# ---------------------------- Vivado & SDK common -----------------------------
# ignore the vivado project
project/*
# folders (and all of their contents) that should always be ignored,
# anywhere in the repo
.Xil/
# file patterns that should always be ignored (journal files, log
# files, dump files that are created upon Vivado/SDK errors)
*.jou
*.log
*.backup.jou
*.backup.log
*.upgrade_log
*.dmp
vivado_pid*
*~
# ------------------------------ Vivado Specific -------------------------------
# preserve hardware manager projects and sources
!project/*.hw/
# preserve design run results
!project/*.runs/
project/*.runs/*
!project/*.runs/impl_*/
project/*.runs/impl_*/*
!project/*.runs/impl_*/*.bit
!project/*.runs/impl_*/*.ltx
# -------------------------------- SDK Specific --------------------------------
!project/*.sdk/
# exclude some obscure hidden SDK folders
project/*.sdk/.metadata/
project/*.sdk/.sdk/
project/*.sdk/RemoteSystemsTempFiles/
project/*.sdk/webtalk/
# hw_platform : exclude the entire hw_platform folder, as everything can be
# generated from the .hdf file. Make sure to include the bitstream in the .hdf
# file when exporting from Vivado!
project/*.sdk/*_hw_platform_*/
# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
# Makefile, the ps7_cortexa9_0 lib files are regenerated automatically
project/*.sdk/*_bsp/*
!project/*.sdk/*_bsp/*.cproject
!project/*.sdk/*_bsp/*.project
!project/*.sdk/*_bsp/*.sdkproject
!project/*.sdk/*_bsp/system.mss
!project/*.sdk/*_bsp/Makefile
# Application: ignored file patterns, exclude Debug & Release folders
project/*.sdk/**/*.o
project/*.sdk/**/*.d
project/*.sdk/**/*.a
project/*.sdk/*/Debug/
project/*.sdk/*/Release/
# REF: https://support.xilinx.com/s/question/0D52E00006iHpHzSAK/which-files-and-folders-of-an-sdk-project-should-be-checked-into-git-and-which-ones-should-be-ignored?language=en_US
modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.tcl
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#*****************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# ad9361_mapping.tcl: Tcl script for re-creating project 'ad9361_mapping'
#
# Generated by Vivado on Sat Mar 18 23:27:17 +0800 2023
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
# 1. This project restoration tcl script (ad9361_mapping.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
# <none>
#
# 3. The following remote source files that were added to the original project:-
#
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_single.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_lvds_dual.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_single.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_lvds_dual.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_rx_map_cmos_dual.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_tx_map_cmos_dual.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_tx_map_lvds_dual.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_rx_map_lvds_dual.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_tx_map_cmos_single.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_rx_map_cmos_single.v"
#
#*****************************************************************************************
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
# Set the project name
set _xil_proj_name_ "ad9361_mapping"
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
set _xil_proj_name_ $::user_project_name
}
variable script_file
set script_file "ad9361_mapping.tcl"
# Help information for this script
proc print_help {} {
variable script_file
puts "\nDescription:"
puts "Recreate a Vivado project from this script. The created project will be"
puts "functionally equivalent to the original project for which this script was"
puts "generated. The script contains commands for creating a project, filesets,"
puts "runs, adding/importing sources and setting properties on various objects.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
puts "$script_file -tclargs \[--project_name <name>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
puts "\[--project_name <name>\] Create project with the specified name. Default"
puts " name is the name of the project from where this"
puts " script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
if { $::argc > 0 } {
for {set i 0} {$i < $::argc} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
"--help" { print_help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
}
# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/project"]"
# Create project
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7k410tffg900-2
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
# Set project properties
set obj [current_project]
set_property -name "compxlib.modelsim_compiled_library_dir" -value "C:/Mentor/CompLib/2019.1.3" -objects $obj
set_property -name "corecontainer.enable" -value "1" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj
set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj
set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj
set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj
set_property -name "dsa.emu_dir" -value "emu" -objects $obj
set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj
set_property -name "dsa.flash_offset_address" -value "0" -objects $obj
set_property -name "dsa.flash_size" -value "1024" -objects $obj
set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj
set_property -name "dsa.host_interface" -value "pcie" -objects $obj
set_property -name "dsa.num_compute_units" -value "60" -objects $obj
set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj
set_property -name "dsa.vendor" -value "xilinx" -objects $obj
set_property -name "dsa.version" -value "0.0" -objects $obj
set_property -name "enable_core_container" -value "1" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "part" -value "xc7k410tffg900-2" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "1" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "1" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "1" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "1" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "1" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "1" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "1" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
[file normalize "${origin_dir}/ip/ad9361_fifo/ad9361_fifo.xci"] \
[file normalize "${origin_dir}/rtl/ad9361_rx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/rtl/ad9361_rx_map_cmos_single.v"] \
[file normalize "${origin_dir}/rtl/ad9361_rx_map_lvds_dual.v"] \
[file normalize "${origin_dir}/rtl/ad9361_tx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/rtl/ad9361_tx_map_cmos_single.v"] \
[file normalize "${origin_dir}/rtl/ad9361_tx_map_lvds_dual.v"] \
]
add_files -norecurse -fileset $obj $files
# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/ip/ad9361_fifo/ad9361_fifo.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
# Set 'sources_1' fileset file properties for local files
# None
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "ad9361_rx_map_cmos_dual" -objects $obj
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
create_fileset -constrset constrs_1
}
# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]
# Empty (no sources present)
# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
set_property -name "target_part" -value "xc7k410tffg900-2" -objects $obj
# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
create_fileset -simset sim_1
}
# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
set files [list \
[file normalize "${origin_dir}/testbenches/tb_ad9361_rx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/testbenches/tb_ad9361_tx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/testbenches/tb_ad9361_tx_map_lvds_dual.v"] \
[file normalize "${origin_dir}/testbenches/tb_ad9361_rx_map_lvds_dual.v"] \
[file normalize "${origin_dir}/testbenches/tb_ad9361_tx_map_cmos_single.v"] \
[file normalize "${origin_dir}/testbenches/tb_ad9361_rx_map_cmos_single.v"] \
]
add_files -norecurse -fileset $obj $files
# Set 'sim_1' fileset file properties for remote files
# None
# Set 'sim_1' fileset file properties for local files
# None
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "top" -value "tb_ad9361_rx_map_cmos_dual" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
# Set 'utils_1' fileset object
set obj [get_filesets utils_1]
# Empty (no sources present)
# Set 'utils_1' fileset properties
set obj [get_filesets utils_1]
# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part xc7k410tffg900-2 -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
} else {
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
set_property flow "Vivado Synthesis 2019" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Synthesis Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'synth_1_synth_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
}
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
if { $obj != "" } {
}
set obj [get_runs synth_1]
set_property -name "part" -value "xc7k410tffg900-2" -objects $obj
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
# set the current synth run
current_run -synthesis [get_runs synth_1]
# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
create_run -name impl_1 -part xc7k410tffg900-2 -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
} else {
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
set_property flow "Vivado Implementation 2019" [get_runs impl_1]
}
set obj [get_runs impl_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Implementation Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
}
# Create 'impl_1_opt_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
if { $obj != "" } {
}
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
}
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
}
# Create 'impl_1_place_report_io_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
if { $obj != "" } {
}
# Create 'impl_1_place_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
if { $obj != "" } {
}
# Create 'impl_1_place_report_control_sets_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
if { $obj != "" } {
set_property -name "options.verbose" -value "1" -objects $obj
}
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
}
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
}
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
}
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
}
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
}
# Create 'impl_1_route_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
if { $obj != "" } {
}
# Create 'impl_1_route_report_methodology_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
if { $obj != "" } {
}
# Create 'impl_1_route_report_power_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
if { $obj != "" } {
}
# Create 'impl_1_route_report_route_status_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
if { $obj != "" } {
}
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
if { $obj != "" } {
set_property -name "options.max_paths" -value "10" -objects $obj
}
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
if { $obj != "" } {
}
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
if { $obj != "" } {
}
# Create 'impl_1_route_report_bus_skew_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
if { $obj != "" } {
set_property -name "options.warn_on_violation" -value "1" -objects $obj
}
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.warn_on_violation" -value "1" -objects $obj
}
# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
if { $obj != "" } {
set_property -name "options.warn_on_violation" -value "1" -objects $obj
}
set obj [get_runs impl_1]
set_property -name "part" -value "xc7k410tffg900-2" -objects $obj
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
# set the current impl run
current_run -implementation [get_runs impl_1]
puts "INFO: Project created:${_xil_proj_name_}"
# Create 'drc_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} {
create_dashboard_gadget -name {drc_1} -type drc
}
set obj [get_dashboard_gadgets [ list "drc_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
# Create 'methodology_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} {
create_dashboard_gadget -name {methodology_1} -type methodology
}
set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
# Create 'power_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} {
create_dashboard_gadget -name {power_1} -type power
}
set obj [get_dashboard_gadgets [ list "power_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
# Create 'timing_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} {
create_dashboard_gadget -name {timing_1} -type timing
}
set obj [get_dashboard_gadgets [ list "timing_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
# Create 'utilization_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} {
create_dashboard_gadget -name {utilization_1} -type utilization
}
set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
set_property -name "run.step" -value "synth_design" -objects $obj
set_property -name "run.type" -value "synthesis" -objects $obj
# Create 'utilization_2' gadget (if not found)
if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} {
create_dashboard_gadget -name {utilization_2} -type utilization
}
set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
move_dashboard_gadget -name {utilization_1} -row 0 -col 0
move_dashboard_gadget -name {power_1} -row 1 -col 0
move_dashboard_gadget -name {drc_1} -row 2 -col 0
move_dashboard_gadget -name {timing_1} -row 0 -col 1
move_dashboard_gadget -name {utilization_2} -row 1 -col 1
move_dashboard_gadget -name {methodology_1} -row 2 -col 1
modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo.xcix
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modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/README.txt
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo/ad9361_fifo.veo
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// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
// IP Revision: 4
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
ad9361_fifo your_instance_name (
.rst(rst), // input wire rst
.wr_clk(wr_clk), // input wire wr_clk
.rd_clk(rd_clk), // input wire rd_clk
.din(din), // input wire [11 : 0] din
.wr_en(wr_en), // input wire wr_en
.rd_en(rd_en), // input wire rd_en
.dout(dout), // output wire [11 : 0] dout
.full(full), // output wire full
.empty(empty) // output wire empty
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file ad9361_fifo.v when simulating
// the core, ad9361_fifo. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo/ad9361_fifo.vho
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-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
-- IP Revision: 4
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT ad9361_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : ad9361_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file ad9361_fifo.vhd when simulating
-- the core, ad9361_fifo. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo/ad9361_fifo_sim_netlist.v
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modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo/ad9361_fifo_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 22:56:31 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_stub.v
// Design : ad9361_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *)
module ad9361_fifo(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[11:0],wr_en,rd_en,dout[11:0],full,empty" */;
input rst;
input wr_clk;
input rd_clk;
input [11:0]din;
input wr_en;
input rd_en;
output [11:0]dout;
output full;
output empty;
endmodule
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo/ad9361_fifo_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 22:56:31 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_stub.vhdl
-- Design : ad9361_fifo
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ad9361_fifo is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end ad9361_fifo;
architecture stub of ad9361_fifo is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[11:0],wr_en,rd_en,dout[11:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3";
begin
end;
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo/sim/ad9361_fifo.v
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// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module ad9361_fifo (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input wire rst;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
input wire wr_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
input wire rd_clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [11 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [11 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
fifo_generator_v13_2_4 #(
.C_COMMON_CLOCK(0),
.C_SELECT_XPM(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(4),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(12),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(12),
.C_ENABLE_RLOCS(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(13),
.C_PROG_FULL_THRESH_NEGATE_VAL(12),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_EN_SAFETY_CKT(0),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(3),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(1),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(rst),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(1'D0),
.rd_clk(rd_clk),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(4'B0),
.prog_empty_thresh_assert(4'B0),
.prog_empty_thresh_negate(4'B0),
.prog_full_thresh(4'B0),
.prog_full_thresh_assert(4'B0),
.prog_full_thresh_negate(4'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.v
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################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sat Mar 18 22:56:02 +0800 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_fifo.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_fifo.sh' script.
./ad9361_fifo.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_fifo.sh -noclean_files
For more information on the script, please type './ad9361_fifo.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
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#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_fifo.sh
# Simulator : Aldec Active-HDL Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sat Mar 18 22:56:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_fifo.sh [-help]
# usage: ad9361_fifo.sh [-lib_map_path]
# usage: ad9361_fifo.sh [-noclean_files]
# usage: ad9361_fifo.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'ad9361_fifo.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Script info
echo -e "ad9361_fifo.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
simulate
}
# RUN_STEP: <compile>
compile()
{
# Compile design files
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
runvsimsa -l simulate.log -do "do {simulate.do}"
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
map_setup_file $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
map_setup_file $2
esac
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Map library.cfg file
map_setup_file()
{
file="library.cfg"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
if [[ ($1 != "" && -e $1) ]]; then
lib_map_path="$1"
else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
vmap -link $lib_map_path
fi
fi
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_fifo.sh [-help]\n\
Usage: ad9361_fifo.sh [-lib_map_path]\n\
Usage: ad9361_fifo.sh [-reset_run]\n\
Usage: ad9361_fifo.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/activehdl/ad9361_fifo.udo
View File
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/activehdl/compile.do
+33
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@@ -0,0 +1,33 @@
vlib work
vlib activehdl
vlib activehdl/xil_defaultlib
vlib activehdl/xpm
vlib activehdl/fifo_generator_v13_2_4
vmap xil_defaultlib activehdl/xil_defaultlib
vmap xpm activehdl/xpm
vmap fifo_generator_v13_2_4 activehdl/fifo_generator_v13_2_4
vlog -work xil_defaultlib -sv2k12 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work fifo_generator_v13_2_4 -v2k5 \
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_2_4 -93 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
vlog -work fifo_generator_v13_2_4 -v2k5 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
vlog -work xil_defaultlib -v2k5 \
"../../../ip/ad9361_fifo/sim/ad9361_fifo.v" \
vlog -work xil_defaultlib \
"glbl.v"
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/activehdl/file_info.txt
+8
View File
@@ -0,0 +1,8 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
ad9361_fifo.v,verilog,xil_defaultlib,../../../ip/ad9361_fifo/sim/ad9361_fifo.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/activehdl/glbl.v
+71
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@@ -0,0 +1,71 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/activehdl/simulate.do
+17
View File
@@ -0,0 +1,17 @@
onbreak {quit -force}
onerror {quit -force}
asim -t 1ps +access +r +m+ad9361_fifo -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ad9361_fifo xil_defaultlib.glbl
do {wave.do}
view wave
view structure
do {ad9361_fifo.udo}
run -all
endsim
quit -force
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/activehdl/wave.do
+2
View File
@@ -0,0 +1,2 @@
add wave *
add wave /glbl/GSR
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/ies/README.txt
+48
View File
@@ -0,0 +1,48 @@
################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sat Mar 18 22:56:02 +0800 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_fifo.sh
This command will launch the 'execute' function for the single-step flow. This
function is called from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_fifo.sh' script.
./ad9361_fifo.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_fifo.sh -noclean_files
For more information on the script, please type './ad9361_fifo.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/ies/ad9361_fifo.sh
+175
View File
@@ -0,0 +1,175 @@
#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_fifo.sh
# Simulator : Cadence Incisive Enterprise Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sat Mar 18 22:56:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_fifo.sh [-help]
# usage: ad9361_fifo.sh [-lib_map_path]
# usage: ad9361_fifo.sh [-noclean_files]
# usage: ad9361_fifo.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'ad9361_fifo.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Directory path for design sources and include directories (if any) wrt this path
ref_dir="."
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
ref_dir="$export_sim_ref_dir"
fi
# Set the compiled library directory
ref_lib_dir="."
# Command line options
irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
# Design libraries
design_libs=(xil_defaultlib xpm fifo_generator_v13_2_4)
# Simulation root library directory
sim_lib_dir="ies_lib"
# Script info
echo -e "ad9361_fifo.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
execute
}
# RUN_STEP: <execute>
execute()
{
irun $irun_opts \
-reflib "$ref_lib_dir/unisim:unisim" \
-reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
-reflib "$ref_lib_dir/secureip:secureip" \
-reflib "$ref_lib_dir/unimacro:unimacro" \
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
-top xil_defaultlib.ad9361_fifo \
-f run.f \
-top glbl \
glbl.v
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
else
ref_lib_dir=$2
fi
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
esac
create_lib_dir
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Create design library directory paths
create_lib_dir()
{
if [[ -e $sim_lib_dir ]]; then
rm -rf $sim_lib_dir
fi
for (( i=0; i<${#design_libs[*]}; i++ )); do
lib="${design_libs[i]}"
lib_dir="$sim_lib_dir/$lib"
if [[ ! -e $lib_dir ]]; then
mkdir -p $lib_dir
fi
done
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
create_lib_dir
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_fifo.sh [-help]\n\
Usage: ad9361_fifo.sh [-lib_map_path]\n\
Usage: ad9361_fifo.sh [-reset_run]\n\
Usage: ad9361_fifo.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/ies/file_info.txt
+8
View File
@@ -0,0 +1,8 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
ad9361_fifo.v,verilog,xil_defaultlib,../../../ip/ad9361_fifo/sim/ad9361_fifo.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/ies/glbl.v
+71
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@@ -0,0 +1,71 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/ies/run.f
+23
View File
@@ -0,0 +1,23 @@
-makelib ies_lib/xil_defaultlib -sv \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-endlib
-makelib ies_lib/xpm \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
-endlib
-makelib ies_lib/fifo_generator_v13_2_4 \
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
-endlib
-makelib ies_lib/fifo_generator_v13_2_4 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
-endlib
-makelib ies_lib/fifo_generator_v13_2_4 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
-endlib
-makelib ies_lib/xil_defaultlib \
"../../../ip/ad9361_fifo/sim/ad9361_fifo.v" \
-endlib
-makelib ies_lib/xil_defaultlib \
glbl.v
-endlib
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/modelsim/README.txt
+49
View File
@@ -0,0 +1,49 @@
################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sat Mar 18 22:56:02 +0800 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_fifo.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_fifo.sh' script.
./ad9361_fifo.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_fifo.sh -noclean_files
For more information on the script, please type './ad9361_fifo.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/modelsim/ad9361_fifo.sh
+167
View File
@@ -0,0 +1,167 @@
#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_fifo.sh
# Simulator : Mentor Graphics ModelSim Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sat Mar 18 22:56:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_fifo.sh [-help]
# usage: ad9361_fifo.sh [-lib_map_path]
# usage: ad9361_fifo.sh [-noclean_files]
# usage: ad9361_fifo.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'ad9361_fifo.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Script info
echo -e "ad9361_fifo.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
simulate
}
# RUN_STEP: <compile>
compile()
{
# Compile design files
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
vsim -64 -c -do "do {simulate.do}" -l simulate.log
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
copy_setup_file $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
copy_setup_file $2
esac
create_lib_dir
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Copy modelsim.ini file
copy_setup_file()
{
file="modelsim.ini"
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
lib_map_path="C:/Mentor/CompLib/2019.1.3"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
cp $src_file .
fi
}
# Create design library directory
create_lib_dir()
{
lib_dir="modelsim_lib"
if [[ -e $lib_dir ]]; then
rm -rf $lib_dir
fi
mkdir $lib_dir
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
create_lib_dir
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_fifo.sh [-help]\n\
Usage: ad9361_fifo.sh [-lib_map_path]\n\
Usage: ad9361_fifo.sh [-reset_run]\n\
Usage: ad9361_fifo.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/modelsim/ad9361_fifo.udo
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modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/modelsim/compile.do
+14
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vlib modelsim_lib/work
vlib modelsim_lib/msim
vlib modelsim_lib/msim/xil_defaultlib
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
vlog -work xil_defaultlib -64 -incr \
"../../../ip/ad9361_fifo/sim/ad9361_fifo.v" \
vlog -work xil_defaultlib \
"glbl.v"
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/modelsim/file_info.txt
+2
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@@ -0,0 +1,2 @@
ad9361_fifo.v,verilog,xil_defaultlib,../../../ip/ad9361_fifo/sim/ad9361_fifo.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/modelsim/glbl.v
+71
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@@ -0,0 +1,71 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/modelsim/modelsim.ini
+2590
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File diff suppressed because it is too large Load Diff
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/modelsim/simulate.do
+16
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@@ -0,0 +1,16 @@
onbreak {quit -f}
onerror {quit -f}
vsim -voptargs="+acc" -t 1ps -L fifo_generator_v13_2_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.ad9361_fifo xil_defaultlib.glbl
do {wave.do}
view wave
view structure
view signals
do {ad9361_fifo.udo}
run -all
quit -force
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/modelsim/wave.do
+2
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@@ -0,0 +1,2 @@
add wave *
add wave /glbl/GSR
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/questa/README.txt
+49
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@@ -0,0 +1,49 @@
################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sat Mar 18 22:56:02 +0800 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_fifo.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_fifo.sh' script.
./ad9361_fifo.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_fifo.sh -noclean_files
For more information on the script, please type './ad9361_fifo.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/questa/ad9361_fifo.sh
+175
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@@ -0,0 +1,175 @@
#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_fifo.sh
# Simulator : Mentor Graphics Questa Advanced Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sat Mar 18 22:56:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_fifo.sh [-help]
# usage: ad9361_fifo.sh [-lib_map_path]
# usage: ad9361_fifo.sh [-noclean_files]
# usage: ad9361_fifo.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'ad9361_fifo.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Script info
echo -e "ad9361_fifo.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
elaborate
simulate
}
# RUN_STEP: <compile>
compile()
{
# Compile design files
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <elaborate>
elaborate()
{
source elaborate.do 2>&1 | tee -a elaborate.log
}
# RUN_STEP: <simulate>
simulate()
{
vsim -64 -c -do "do {simulate.do}" -l simulate.log
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
copy_setup_file $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
copy_setup_file $2
esac
create_lib_dir
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Copy modelsim.ini file
copy_setup_file()
{
file="modelsim.ini"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
if [[ ($1 != "" && -e $1) ]]; then
lib_map_path="$1"
else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
cp $src_file .
fi
}
# Create design library directory
create_lib_dir()
{
lib_dir="questa_lib"
if [[ -e $lib_dir ]]; then
rm -rf $lib_dir
fi
mkdir $lib_dir
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
create_lib_dir
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_fifo.sh [-help]\n\
Usage: ad9361_fifo.sh [-lib_map_path]\n\
Usage: ad9361_fifo.sh [-reset_run]\n\
Usage: ad9361_fifo.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/questa/ad9361_fifo.udo
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modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/questa/compile.do
+33
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@@ -0,0 +1,33 @@
vlib questa_lib/work
vlib questa_lib/msim
vlib questa_lib/msim/xil_defaultlib
vlib questa_lib/msim/xpm
vlib questa_lib/msim/fifo_generator_v13_2_4
vmap xil_defaultlib questa_lib/msim/xil_defaultlib
vmap xpm questa_lib/msim/xpm
vmap fifo_generator_v13_2_4 questa_lib/msim/fifo_generator_v13_2_4
vlog -work xil_defaultlib -64 -sv \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -64 -93 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work fifo_generator_v13_2_4 -64 \
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_2_4 -64 -93 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
vlog -work fifo_generator_v13_2_4 -64 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
vlog -work xil_defaultlib -64 \
"../../../ip/ad9361_fifo/sim/ad9361_fifo.v" \
vlog -work xil_defaultlib \
"glbl.v"
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/questa/elaborate.do
+1
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@@ -0,0 +1 @@
vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ad9361_fifo xil_defaultlib.glbl -o ad9361_fifo_opt
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/questa/file_info.txt
+8
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@@ -0,0 +1,8 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
ad9361_fifo.v,verilog,xil_defaultlib,../../../ip/ad9361_fifo/sim/ad9361_fifo.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/questa/glbl.v
+71
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@@ -0,0 +1,71 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/questa/simulate.do
+16
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@@ -0,0 +1,16 @@
onbreak {quit -f}
onerror {quit -f}
vsim -t 1ps -lib xil_defaultlib ad9361_fifo_opt
do {wave.do}
view wave
view structure
view signals
do {ad9361_fifo.udo}
run -all
quit -force
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/questa/wave.do
+2
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@@ -0,0 +1,2 @@
add wave *
add wave /glbl/GSR
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/riviera/README.txt
+49
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@@ -0,0 +1,49 @@
################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sat Mar 18 22:56:02 +0800 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_fifo.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_fifo.sh' script.
./ad9361_fifo.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_fifo.sh -noclean_files
For more information on the script, please type './ad9361_fifo.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/riviera/ad9361_fifo.sh
+154
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#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_fifo.sh
# Simulator : Aldec Riviera-PRO Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sat Mar 18 22:56:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_fifo.sh [-help]
# usage: ad9361_fifo.sh [-lib_map_path]
# usage: ad9361_fifo.sh [-noclean_files]
# usage: ad9361_fifo.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'ad9361_fifo.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Script info
echo -e "ad9361_fifo.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
simulate
}
# RUN_STEP: <compile>
compile()
{
# Compile design files
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
runvsimsa -l simulate.log -do "do {simulate.do}"
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
map_setup_file $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
map_setup_file $2
esac
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Map library.cfg file
map_setup_file()
{
file="library.cfg"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
if [[ ($1 != "" && -e $1) ]]; then
lib_map_path="$1"
else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
vmap -link $lib_map_path
fi
fi
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_fifo.sh [-help]\n\
Usage: ad9361_fifo.sh [-lib_map_path]\n\
Usage: ad9361_fifo.sh [-reset_run]\n\
Usage: ad9361_fifo.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/riviera/ad9361_fifo.udo
View File
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/riviera/compile.do
+33
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@@ -0,0 +1,33 @@
vlib work
vlib riviera
vlib riviera/xil_defaultlib
vlib riviera/xpm
vlib riviera/fifo_generator_v13_2_4
vmap xil_defaultlib riviera/xil_defaultlib
vmap xpm riviera/xpm
vmap fifo_generator_v13_2_4 riviera/fifo_generator_v13_2_4
vlog -work xil_defaultlib -sv2k12 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work fifo_generator_v13_2_4 -v2k5 \
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_2_4 -93 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
vlog -work fifo_generator_v13_2_4 -v2k5 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
vlog -work xil_defaultlib -v2k5 \
"../../../ip/ad9361_fifo/sim/ad9361_fifo.v" \
vlog -work xil_defaultlib \
"glbl.v"
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/riviera/file_info.txt
+8
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@@ -0,0 +1,8 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
ad9361_fifo.v,verilog,xil_defaultlib,../../../ip/ad9361_fifo/sim/ad9361_fifo.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/riviera/glbl.v
+71
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@@ -0,0 +1,71 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/riviera/simulate.do
+17
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@@ -0,0 +1,17 @@
onbreak {quit -force}
onerror {quit -force}
asim -t 1ps +access +r +m+ad9361_fifo -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ad9361_fifo xil_defaultlib.glbl
do {wave.do}
view wave
view structure
do {ad9361_fifo.udo}
run -all
endsim
quit -force
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/riviera/wave.do
+2
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@@ -0,0 +1,2 @@
add wave *
add wave /glbl/GSR
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/vcs/README.txt
+49
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@@ -0,0 +1,49 @@
################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sat Mar 18 22:56:02 +0800 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_fifo.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_fifo.sh' script.
./ad9361_fifo.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_fifo.sh -noclean_files
For more information on the script, please type './ad9361_fifo.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/vcs/ad9361_fifo.sh
+241
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@@ -0,0 +1,241 @@
#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_fifo.sh
# Simulator : Synopsys Verilog Compiler Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sat Mar 18 22:56:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_fifo.sh [-help]
# usage: ad9361_fifo.sh [-lib_map_path]
# usage: ad9361_fifo.sh [-noclean_files]
# usage: ad9361_fifo.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'ad9361_fifo.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Directory path for design sources and include directories (if any) wrt this path
ref_dir="."
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
ref_dir="$export_sim_ref_dir"
fi
# Command line options
vlogan_opts="-full64"
vhdlan_opts="-full64"
vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
vcs_sim_opts="-ucli -licqueue -l simulate.log"
# Design libraries
design_libs=(xil_defaultlib xpm fifo_generator_v13_2_4)
# Simulation root library directory
sim_lib_dir="vcs_lib"
# Script info
echo -e "ad9361_fifo.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
elaborate
simulate
}
# RUN_STEP: <compile>
compile()
{
# Compile design files
vlogan -work xil_defaultlib $vlogan_opts -sverilog \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
2>&1 | tee -a vlogan.log
vhdlan -work xpm $vhdlan_opts \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
2>&1 | tee -a vhdlan.log
vlogan -work fifo_generator_v13_2_4 $vlogan_opts +v2k \
"$ref_dir/../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
2>&1 | tee -a vlogan.log
vhdlan -work fifo_generator_v13_2_4 $vhdlan_opts \
"$ref_dir/../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
2>&1 | tee -a vhdlan.log
vlogan -work fifo_generator_v13_2_4 $vlogan_opts +v2k \
"$ref_dir/../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
2>&1 | tee -a vlogan.log
vlogan -work xil_defaultlib $vlogan_opts +v2k \
"$ref_dir/../../../ip/ad9361_fifo/sim/ad9361_fifo.v" \
2>&1 | tee -a vlogan.log
vlogan -work xil_defaultlib $vlogan_opts +v2k \
glbl.v \
2>&1 | tee -a vlogan.log
}
# RUN_STEP: <elaborate>
elaborate()
{
vcs $vcs_elab_opts xil_defaultlib.ad9361_fifo xil_defaultlib.glbl -o ad9361_fifo_simv
}
# RUN_STEP: <simulate>
simulate()
{
./ad9361_fifo_simv $vcs_sim_opts -do simulate.do
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
create_lib_mappings $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
create_lib_mappings $2
esac
create_lib_dir
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Define design library mappings
create_lib_mappings()
{
file="synopsys_sim.setup"
if [[ -e $file ]]; then
if [[ ($1 == "") ]]; then
return
else
rm -rf $file
fi
fi
touch $file
lib_map_path=""
if [[ ($1 != "") ]]; then
lib_map_path="$1"
fi
for (( i=0; i<${#design_libs[*]}; i++ )); do
lib="${design_libs[i]}"
mapping="$lib:$sim_lib_dir/$lib"
echo $mapping >> $file
done
if [[ ($lib_map_path != "") ]]; then
incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
echo $incl_ref >> $file
fi
}
# Create design library directory paths
create_lib_dir()
{
if [[ -e $sim_lib_dir ]]; then
rm -rf $sim_lib_dir
fi
for (( i=0; i<${#design_libs[*]}; i++ )); do
lib="${design_libs[i]}"
lib_dir="$sim_lib_dir/$lib"
if [[ ! -e $lib_dir ]]; then
mkdir -p $lib_dir
fi
done
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(ucli.key ad9361_fifo_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ad9361_fifo_simv.daidir)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
create_lib_dir
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_fifo.sh [-help]\n\
Usage: ad9361_fifo.sh [-lib_map_path]\n\
Usage: ad9361_fifo.sh [-reset_run]\n\
Usage: ad9361_fifo.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/vcs/file_info.txt
+8
View File
@@ -0,0 +1,8 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
ad9361_fifo.v,verilog,xil_defaultlib,../../../ip/ad9361_fifo/sim/ad9361_fifo.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/vcs/glbl.v
+71
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@@ -0,0 +1,71 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/vcs/simulate.do
+2
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@@ -0,0 +1,2 @@
run
quit
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xcelium/README.txt
+48
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@@ -0,0 +1,48 @@
################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sat Mar 18 22:56:02 +0800 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_fifo.sh
This command will launch the 'execute' function for the single-step flow. This
function is called from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_fifo.sh' script.
./ad9361_fifo.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_fifo.sh -noclean_files
For more information on the script, please type './ad9361_fifo.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xcelium/ad9361_fifo.sh
+175
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@@ -0,0 +1,175 @@
#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_fifo.sh
# Simulator : Cadence Xcelium Parallel Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sat Mar 18 22:56:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_fifo.sh [-help]
# usage: ad9361_fifo.sh [-lib_map_path]
# usage: ad9361_fifo.sh [-noclean_files]
# usage: ad9361_fifo.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'ad9361_fifo.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Directory path for design sources and include directories (if any) wrt this path
ref_dir="."
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
ref_dir="$export_sim_ref_dir"
fi
# Set the compiled library directory
ref_lib_dir="."
# Command line options
xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
# Design libraries
design_libs=(xil_defaultlib xpm fifo_generator_v13_2_4)
# Simulation root library directory
sim_lib_dir="xcelium_lib"
# Script info
echo -e "ad9361_fifo.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
execute
}
# RUN_STEP: <execute>
execute()
{
xrun $xrun_opts \
-reflib "$ref_lib_dir/unisim:unisim" \
-reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
-reflib "$ref_lib_dir/secureip:secureip" \
-reflib "$ref_lib_dir/unimacro:unimacro" \
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
-top xil_defaultlib.ad9361_fifo \
-f run.f \
-top glbl \
glbl.v
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
else
ref_lib_dir=$2
fi
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
esac
create_lib_dir
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Create design library directory paths
create_lib_dir()
{
if [[ -e $sim_lib_dir ]]; then
rm -rf $sim_lib_dir
fi
for (( i=0; i<${#design_libs[*]}; i++ )); do
lib="${design_libs[i]}"
lib_dir="$sim_lib_dir/$lib"
if [[ ! -e $lib_dir ]]; then
mkdir -p $lib_dir
fi
done
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
create_lib_dir
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_fifo.sh [-help]\n\
Usage: ad9361_fifo.sh [-lib_map_path]\n\
Usage: ad9361_fifo.sh [-reset_run]\n\
Usage: ad9361_fifo.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xcelium/file_info.txt
+8
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@@ -0,0 +1,8 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
ad9361_fifo.v,verilog,xil_defaultlib,../../../ip/ad9361_fifo/sim/ad9361_fifo.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xcelium/glbl.v
+71
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@@ -0,0 +1,71 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xcelium/run.f
+23
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@@ -0,0 +1,23 @@
-makelib xcelium_lib/xil_defaultlib -sv \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-endlib
-makelib xcelium_lib/xpm \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
-endlib
-makelib xcelium_lib/fifo_generator_v13_2_4 \
"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
-endlib
-makelib xcelium_lib/fifo_generator_v13_2_4 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
-endlib
-makelib xcelium_lib/fifo_generator_v13_2_4 \
"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
-endlib
-makelib xcelium_lib/xil_defaultlib \
"../../../ip/ad9361_fifo/sim/ad9361_fifo.v" \
-endlib
-makelib xcelium_lib/xil_defaultlib \
glbl.v
-endlib
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xsim/README.txt
+49
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@@ -0,0 +1,49 @@
################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sat Mar 18 22:56:02 +0800 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_fifo.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_fifo.sh' script.
./ad9361_fifo.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_fifo.sh -noclean_files
For more information on the script, please type './ad9361_fifo.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xsim/ad9361_fifo.sh
+214
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@@ -0,0 +1,214 @@
#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_fifo.sh
# Simulator : Xilinx Vivado Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sat Mar 18 22:56:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_fifo.sh [-help]
# usage: ad9361_fifo.sh [-lib_map_path]
# usage: ad9361_fifo.sh [-noclean_files]
# usage: ad9361_fifo.sh [-reset_run]
#
#*********************************************************************************************************
# Command line options
xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0
xvlog_opts="--relax"
xvhdl_opts="--relax"
# Script info
echo -e "ad9361_fifo.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
elaborate
simulate
}
# RUN_STEP: <compile>
compile()
{
# Compile design files
xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log
}
# RUN_STEP: <elaborate>
elaborate()
{
xelab --relax --debug typical --mt auto -L fifo_generator_v13_2_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ad9361_fifo xil_defaultlib.ad9361_fifo xil_defaultlib.glbl -log elaborate.log
}
# RUN_STEP: <simulate>
simulate()
{
xsim ad9361_fifo -key {Behavioral:sim_1:Functional:ad9361_fifo} -tclbatch cmd.tcl -log simulate.log
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
copy_setup_file $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
copy_setup_file $2
esac
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Copy xsim.ini file
copy_setup_file()
{
file="xsim.ini"
lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim"
if [[ ($1 != "") ]]; then
lib_map_path="$1"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
cp $src_file .
fi
# Map local design libraries to xsim.ini
map_local_libs
fi
}
# Map local design libraries
map_local_libs()
{
updated_mappings=()
local_mappings=()
# Local design libraries
local_libs=()
if [[ 0 == ${#local_libs[@]} ]]; then
return
fi
file="xsim.ini"
file_backup="xsim.ini.bak"
if [[ -e $file ]]; then
rm -f $file_backup
# Create a backup copy of the xsim.ini file
cp $file $file_backup
# Read libraries from backup file and search in local library collection
while read -r line
do
IN=$line
# Split mapping entry with '=' delimiter to fetch library name and mapping
read lib_name mapping <<<$(IFS="="; echo $IN)
# If local library found, then construct the local mapping and add to local mapping collection
if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
line="$lib_name=xsim.dir/$lib_name"
local_mappings+=("$lib_name")
fi
# Add to updated library mapping collection
updated_mappings+=("$line")
done < "$file_backup"
# Append local libraries not found originally from xsim.ini
for (( i=0; i<${#local_libs[*]}; i++ )); do
lib_name="${local_libs[i]}"
if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
line="$lib_name=xsim.dir/$lib_name"
updated_mappings+=("$line")
fi
done
# Write updated mappings in xsim.ini
rm -f $file
for (( i=0; i<${#updated_mappings[*]}; i++ )); do
lib_name="${updated_mappings[i]}"
echo $lib_name >> $file
done
else
for (( i=0; i<${#local_libs[*]}; i++ )); do
lib_name="${local_libs[i]}"
mapping="$lib_name=xsim.dir/$lib_name"
echo $mapping >> $file
done
fi
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ad9361_fifo.wdb xsim.dir)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_fifo.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_fifo.sh [-help]\n\
Usage: ad9361_fifo.sh [-lib_map_path]\n\
Usage: ad9361_fifo.sh [-reset_run]\n\
Usage: ad9361_fifo.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xsim/cmd.tcl
+12
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@@ -0,0 +1,12 @@
set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run -all
quit
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xsim/elab.opt
+1
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@@ -0,0 +1 @@
--relax --debug typical --mt auto -L fifo_generator_v13_2_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ad9361_fifo xil_defaultlib.ad9361_fifo xil_defaultlib.glbl -log elaborate.log
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xsim/file_info.txt
+2
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@@ -0,0 +1,2 @@
ad9361_fifo.v,verilog,xil_defaultlib,../../../ip/ad9361_fifo/sim/ad9361_fifo.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xsim/glbl.v
+71
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@@ -0,0 +1,71 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xsim/vhdl.prj
+2
View File
@@ -0,0 +1,2 @@
nosort
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xsim/vlog.prj
+6
View File
@@ -0,0 +1,6 @@
verilog xil_defaultlib \
"../../../ip/ad9361_fifo/sim/ad9361_fifo.v" \
verilog xil_defaultlib "glbl.v"
nosort
modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/sim_scripts/ad9361_fifo/xsim/xsim.ini
+430
View File
@@ -0,0 +1,430 @@
std=$RDI_DATADIR/xsim/vhdl/std
ieee=$RDI_DATADIR/xsim/vhdl/ieee
ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
vl=$RDI_DATADIR/xsim/vhdl/vl
synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
secureip=$RDI_DATADIR/xsim/verilog/secureip
unisim=$RDI_DATADIR/xsim/vhdl/unisim
unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
unifast=$RDI_DATADIR/xsim/vhdl/unifast
unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6
bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0
g709_rs_decoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_8
xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
mipi_dphy_v4_1_4=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_4
iomodule_v3_1_4=$RDI_DATADIR/xsim/ip/iomodule_v3_1_4
ieee802d3_50g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_11
common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
lte_fft_v2_1_0=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_0
ieee802d3_50g_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_1
convolution_v9_0_14=$RDI_DATADIR/xsim/ip/convolution_v9_0_14
gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
v_cfa_v7_0_14=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_14
axi4svideo_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_10
pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11
v_vscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_13
xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6
gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
ethernet_1_10_25g_v2_2_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_2_3
zynq_ultra_ps_e_v3_3_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_0
v_cresample_v4_0_14=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_14
v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9
v_scenechange_v1_0_1=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_1
hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0
ahblite_axi_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_14
tri_mode_ethernet_mac_v9_0_14=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_14
blk_mem_gen_v8_4_3=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_3
noc_mc_ddr4_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr4_phy_v1_0_0
axi_data_fifo_v2_1_18=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_18
axi_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_5
ethernet_1_10_25g_v2_0_5=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_5
compact_gt_v1_0_5=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_5
axi_gpio_v2_0_21=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_21
qdma_v3_0_2=$RDI_DATADIR/xsim/ip/qdma_v3_0_2
viterbi_v9_1_11=$RDI_DATADIR/xsim/ip/viterbi_v9_1_11
sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2
ba317=$RDI_DATADIR/xsim/ip/ba317
xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4
fifo_generator_v13_2_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_4
axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14
vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0
axi_emc_v3_0_19=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_19
cmac_v2_5_1=$RDI_DATADIR/xsim/ip/cmac_v2_5_1
floating_point_v7_1_8=$RDI_DATADIR/xsim/ip/floating_point_v7_1_8
xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6
vid_phy_controller_v2_2_3=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_3
common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
axi_firewall_v1_0_7=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_7
util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1
axis_accelerator_adapter_v2_1_15=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_15
tmr_comparator_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_2
sd_fec_v1_0_2=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_2
tmr_manager_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_4
tsn_temac_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_4
usxgmii_v1_0_5=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_5
lte_dl_channel_encoder_v4_0_0=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_0
ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
lte_3gpp_mimo_decoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_15
v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0
axi4stream_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_5
cmac_usplus_v2_4_5=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_5
etrnic_v1_1_2=$RDI_DATADIR/xsim/ip/etrnic_v1_1_2
floating_point_v7_0_16=$RDI_DATADIR/xsim/ip/floating_point_v7_0_16
axi_dma_v7_1_20=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_20
jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
axi_traffic_gen_v3_0_5=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_5
emb_mem_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_1
axi_amm_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_9
axi_datamover_v5_1_21=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_21
v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10
jesd204_v7_2_6=$RDI_DATADIR/xsim/ip/jesd204_v7_2_6
v_letterbox_v1_0_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_13
interlaken_v2_4_3=$RDI_DATADIR/xsim/ip/interlaken_v2_4_3
uhdsdi_gt_v2_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_0
axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7
rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3
audio_formatter_v1_0_1=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_1
lte_3gpp_channel_estimator_v2_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_16
v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13
g709_fec_v2_3_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_5
xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6
axi_chip2chip_v5_0_6=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_6
fc32_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_11
v_mix_v3_0_3=$RDI_DATADIR/xsim/ip/v_mix_v3_0_3
multi_channel_25g_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_5
in_system_ibert_v1_0_9=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_9
ethernet_1_10_25g_v2_1_4=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_4
axis_broadcaster_v1_1_18=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_18
axis_combiner_v1_1_17=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_17
axi_apb_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_15
displayport_v9_0_1=$RDI_DATADIR/xsim/ip/displayport_v9_0_1
clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2
hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1
axi_register_slice_v2_1_19=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_19
vid_phy_controller_v2_1_5=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_5
picxo=$RDI_DATADIR/xsim/ip/picxo
usxgmii_v1_1_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_0
v_vcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_13
bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0
prc_v1_3_2=$RDI_DATADIR/xsim/ip/prc_v1_3_2
axi_usb2_device_v5_0_20=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_20
lte_3gpp_mimo_encoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_14
l_ethernet_v2_5_2=$RDI_DATADIR/xsim/ip/l_ethernet_v2_5_2
xdma_v4_1_3=$RDI_DATADIR/xsim/ip/xdma_v4_1_3
axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0
c_counter_binary_v12_0_13=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_13
noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0
xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17
c_accum_v12_0_13=$RDI_DATADIR/xsim/ip/c_accum_v12_0_13
xbip_multadd_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_14
axi_uartlite_v2_0_23=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_23
noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13
i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3
pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8
mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10
c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6
sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14
fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6
quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6
microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1
lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12
dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18
me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0
gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6
axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20
nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0
tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3
axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0
axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23
v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0
v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0
canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1
gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6
lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2
ieee802d3_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_5
ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6
high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1
xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6
fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1
tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2
hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0
axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20
flexo_100g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_11
v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7
xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6
fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10
ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15
axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19
noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0
duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15
dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13
mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0
ieee802d3_200g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_7
sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0
sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11
v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1
axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22
ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13
switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7
rama_v1_1_2_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_2_lib
v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13
emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1
hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3
axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1
hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0
rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1
axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17
proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13
pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0
v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16
pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12
xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17
axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19
audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0
lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13
v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15
axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18
xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0
emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5
axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18
xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9
pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8
fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12
div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15
mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16
v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11
xxv_ethernet_v2_5_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_3
xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2
ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1
axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0
smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib
axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19
xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6
tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6
mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1
axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1
util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1
rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7
v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0
dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0
pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2
axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21
high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1
axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3
sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2
gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7
xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2
high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1
axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5
axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16
v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13
v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0
axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17
axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21
axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0
vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13
advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0
ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2
interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4
axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
cpri_v8_10_3=$RDI_DATADIR/xsim/ip/cpri_v8_10_3
c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6
v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0
stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1
ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0
lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0
axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22
g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6
blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6
tmr_sem_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_9
fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6
axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7
axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20
xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20
rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15
axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3
tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15
axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21
noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2
v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13
shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0
lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18
gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11
amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5
mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21
videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5
audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0
cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1
i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3
v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0
v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5
remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4
hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3
etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3
xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2
ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2
xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6
cmac_usplus_v2_5_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_3
jesd204c_v4_1_1=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_1
debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3
v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2
v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9
mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4
lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15
axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19
xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0
axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7
cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17
cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5
ieee802d3_400g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_7
xxv_ethernet_v2_4_5=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_5
axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11
tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18
v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13
dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16
axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16
processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7
g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18
rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16
c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13
displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11
v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0
v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12
sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12
xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6
ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7
oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0
c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13
v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15
zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5
cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14
c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6
axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0
pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7
timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4
lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16
zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3
v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5
bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0
pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0
tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15
polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3
rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6
xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6
v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15
ernic_v1_0_1=$RDI_DATADIR/xsim/ip/ernic_v1_0_1
high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3
mailbox_v2_1_11=$RDI_DATADIR/xsim/ip/mailbox_v2_1_11
video_frame_crc_v1_0_1=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_1
axi_sg_v4_1_12=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_12
ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0
lmb_bram_if_cntlr_v4_0_16=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_16
l_ethernet_v2_4_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_4_3
dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1
rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0
axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6
v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0
stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0
lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3
pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4
lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9
axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17
cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15
axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19
axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19
axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16
mult_gen_v12_0_15=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_15
spdif_v2_0_21=$RDI_DATADIR/xsim/ip/spdif_v2_0_21
v_hscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_13
ethernet_1_10_25g_v2_3_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_3_3
xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6
axi_quad_spi_v3_2_18=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_18
axi_bram_ctrl_v4_1_1=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_1
axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
axi_protocol_checker_v2_0_5=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_5
axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7
ieee802d3_25g_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_13
aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
xtlm=$RDI_DATADIR/xsim/ip/xtlm
iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
ieee802d3_clause74_fec_v1_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_4
xlconcat_v2_1_3=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_3
perf_axi_tg_v1_0_8=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_8
axi_crossbar_v2_1_20=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_20
tsn_endpoint_ethernet_mac_block_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_4
v_ycrcb2rgb_v7_1_13=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_13
xhmc_v1_0_9=$RDI_DATADIR/xsim/ip/xhmc_v1_0_9
dp_videoaxi4s_bridge_v1_0_0=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_0
lte_ul_channel_decoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_16
soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0
pr_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_1
sync_ip=$RDI_DATADIR/xsim/ip/sync_ip
v_frmbuf_rd_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_2
c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6
cmac_usplus_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_6_2
axi_mcdma_v1_0_5=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_5
c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6
g709_fec_v2_4_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_1
lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0
ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4
v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0
l_ethernet_v2_3_5=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_5
microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6
v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1
ldpc_v2_0_3=$RDI_DATADIR/xsim/ip/ldpc_v2_0_3
xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6
xpm=$RDI_DATADIR/xsim/ip/xpm
srio_gen2_v4_1_6=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_6
g975_efec_i4_v1_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_17
noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0
roe_framer_v2_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v2_0_1
xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10
generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0
ten_gig_eth_pcs_pma_v6_0_15=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_15
can_v5_0_22=$RDI_DATADIR/xsim/ip/can_v5_0_22
av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0
fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1
lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
axis_dwidth_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_18
lte_rach_detector_v3_1_5=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_5
xxv_ethernet_v3_0_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_0_3
axi_iic_v2_0_22=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_22
axi_pcie_v2_9_1=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_1
util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4
sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0
v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0
v_tpg_v7_0_13=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_13
sd_fec_v1_1_3=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_3
xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6
lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2
v_multi_scaler_v1_0_1=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_1
axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0
advanced_io_wizard_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_0
mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8
axi_pcie3_v3_0_9=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_9
axi_vfifo_ctrl_v2_0_21=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_21
xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/18e48aa99774dd44/18e48aa99774dd44.xci
+206
View File
@@ -0,0 +1,206 @@
<?xml version="1.0" encoding="UTF-8"?>
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</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/18e48aa99774dd44/ad9361_fifo.dcp
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modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/18e48aa99774dd44/ad9361_fifo_sim_netlist.v
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modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/18e48aa99774dd44/ad9361_fifo_sim_netlist.vhdl
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modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/18e48aa99774dd44/ad9361_fifo_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 22:56:31 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ad9361_fifo_stub.v
// Design : ad9361_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[11:0],wr_en,rd_en,dout[11:0],full,empty" */;
input rst;
input wr_clk;
input rd_clk;
input [11:0]din;
input wr_en;
input rd_en;
output [11:0]dout;
output full;
output empty;
endmodule
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/18e48aa99774dd44/ad9361_fifo_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 22:56:31 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ad9361_fifo_stub.vhdl
-- Design : ad9361_fifo
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[11:0],wr_en,rd_en,dout[11:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3";
begin
end;
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf
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modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml
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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sat Mar 18 22:56:45 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="78ee36b7e6b74e44bb938e7645a78260" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AddExistingIPHandler" value="1" type="JavaHandler"/>
<property name="ManageCompositeTargets" value="2" type="JavaHandler"/>
<property name="NewIPLocationHandler" value="3" type="JavaHandler"/>
<property name="OpenIPLocationHandler" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="2" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="1" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="13" type="GuiHandlerData"/>
<property name="FPGAChooser_FPGA_TABLE" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="4" type="GuiHandlerData"/>
<property name="GettingStartedView_MANAGE_IP" value="4" type="GuiHandlerData"/>
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="3" type="GuiHandlerData"/>
<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
<property name="NewIPProjectWizard_PART" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_EXISTING_IP" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_IP_LOCATION" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="1" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="1" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="1" type="GuiHandlerData"/>
<property name="SrcMenu_IP_DOCUMENTATION" value="1" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="49" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="32" type="TclMode"/>
</item>
</section>
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modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.hw/managed_ip_project.lpr
+6
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_1.xml
+8
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="ad9361_fifo_synth_1" LaunchDir="D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/.Vivado_Synthesis.queue.rst
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modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/.vivado.begin.rst
+5
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@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="18168" HostCore="20" HostMemory="068448337920">
</Process>
</ProcessHandle>
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/.vivado.end.rst
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modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ISEWrap.js
+270
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@@ -0,0 +1,270 @@
//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var wbemFlagReturnImmediately = 0x10;
var wbemFlagForwardOnly = 0x20;
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
var NOC = 0;
var NOLP = 0;
var TPM = 0;
var cpuInfos = new Enumerator(processor);
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
var cpuInfo = cpuInfos.item();
NOC += cpuInfo.NumberOfCores;
NOLP += cpuInfo.NumberOfLogicalProcessors;
}
var csInfos = new Enumerator(computerSystem);
for(;!csInfos.atEnd(); csInfos.moveNext()) {
var csInfo = csInfos.item();
TPM += csInfo.TotalPhysicalMemory;
}
var ISEHOSTCORE = NOLP
var ISEMEMTOTAL = TPM
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\" HostCore=\"" + ISEHOSTCORE +
"\" HostMemory=\"" + ISEMEMTOTAL +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ISEWrap.sh
+67
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@@ -0,0 +1,67 @@
#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
if [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/__synthesis_is_complete__
View File
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo.dcp
BIN
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Binary file not shown.
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo.tcl
+157
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@@ -0,0 +1,157 @@
#
# Synthesis run script generated by Vivado
#
set TIME_start [clock seconds]
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
set_param project.vivado.isBlockSynthRun true
set_msg_config -msgmgr_mode ooc_run
create_project -in_memory -part xc7k410tffg900-2
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
set_property parent.project_path D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.xpr [current_project]
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_ip -quiet D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci
set_property used_in_implementation false [get_files -all d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xdc]
set_property used_in_implementation false [get_files -all d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo_clocks.xdc]
set_property used_in_implementation false [get_files -all d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo_ooc.xdc]
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc]
set_param ips.enableIPCacheLiteLoad 1
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1 -new_name ad9361_fifo -ip [get_ips ad9361_fifo]]
if { $cached_ip eq {} } {
close [open __synthesis_is_running__ w]
synth_design -top ad9361_fifo -part xc7k410tffg900-2 -mode out_of_context
#---------------------------------------------------------
# Generate Checkpoint/Stub/Simulation Files For IP Cache
#---------------------------------------------------------
# disable binary constraint mode for IPCache checkpoints
set_param constraints.enableBinaryConstraints false
catch {
write_checkpoint -force -noxdef -rename_prefix ad9361_fifo_ ad9361_fifo.dcp
set ipCachedFiles {}
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ad9361_fifo_stub.v
lappend ipCachedFiles ad9361_fifo_stub.v
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ad9361_fifo_stub.vhdl
lappend ipCachedFiles ad9361_fifo_stub.vhdl
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ad9361_fifo_sim_netlist.v
lappend ipCachedFiles ad9361_fifo_sim_netlist.v
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ad9361_fifo_sim_netlist.vhdl
lappend ipCachedFiles ad9361_fifo_sim_netlist.vhdl
set TIME_taken [expr [clock seconds] - $TIME_start]
config_ip_cache -add -dcp ad9361_fifo.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips ad9361_fifo]
}
rename_ref -prefix_all ad9361_fifo_
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef ad9361_fifo.dcp
create_report "ad9361_fifo_synth_1_synth_report_utilization_0" "report_utilization -file ad9361_fifo_utilization_synth.rpt -pb ad9361_fifo_utilization_synth.pb"
if { [catch {
write_verilog -force -mode synth_stub D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode synth_stub D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_verilog -force -mode funcsim D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode funcsim D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
} else {
}; # end if cached_ip
add_files D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_stub.v -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci]
add_files D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_stub.vhdl -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci]
add_files D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_sim_netlist.v -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci]
add_files D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci]
add_files D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo.dcp -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci]
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo]} {
catch {
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_sim_netlist.v D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo
}
}
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo]} {
catch {
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_sim_netlist.vhdl D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo
}
}
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo]} {
catch {
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_stub.v D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo
}
}
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo]} {
catch {
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_stub.vhdl D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ip_user_files/ip/ad9361_fifo
}
}
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo.vds
+729
View File
@@ -0,0 +1,729 @@
#-----------------------------------------------------------
# Vivado v2019.1.3 (64-bit)
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
# Start of session at: Sat Mar 18 22:56:04 2023
# Process ID: 33028
# Current directory: D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1
# Command line: vivado.exe -log ad9361_fifo.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ad9361_fifo.tcl
# Log file: D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo.vds
# Journal file: D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1\vivado.jou
#-----------------------------------------------------------
Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
source ad9361_fifo.tcl -notrace
Command: synth_design -top ad9361_fifo -part xc7k410tffg900-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
INFO: [Device 21-403] Loading part xc7k410tffg900-2
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 33504
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 885.820 ; gain = 177.672
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'ad9361_fifo' [d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/synth/ad9361_fifo.vhd:73]
Parameter C_COMMON_CLOCK bound to: 0 - type: integer
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COUNT_TYPE bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 4 - type: integer
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
Parameter C_DIN_WIDTH bound to: 12 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
Parameter C_DOUT_WIDTH bound to: 12 - type: integer
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_FAMILY bound to: kintex7 - type: string
Parameter C_FULL_FLAGS_RST_VAL bound to: 1 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_HAS_BACKUP bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_RD_RST bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_WR_RST bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 2 - type: integer
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 1 - type: integer
Parameter C_PRELOAD_REGS bound to: 0 - type: integer
Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 2 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 3 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 13 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 12 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 4 - type: integer
Parameter C_RD_DEPTH bound to: 16 - type: integer
Parameter C_RD_FREQ bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 4 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 1 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 4 - type: integer
Parameter C_WR_DEPTH bound to: 16 - type: integer
Parameter C_WR_FREQ bound to: 1 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 4 - type: integer
Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 1 - type: integer
Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer
Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer
Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer
Parameter C_HAS_MASTER_CE bound to: 0 - type: integer
Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer
Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer
Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer
Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer
Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer
Parameter C_HAS_AXIS_TID bound to: 0 - type: integer
Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer
Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer
Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer
Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer
Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer
Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer
Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer
Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer
Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer
Parameter C_WACH_TYPE bound to: 0 - type: integer
Parameter C_WDCH_TYPE bound to: 0 - type: integer
Parameter C_WRCH_TYPE bound to: 0 - type: integer
Parameter C_RACH_TYPE bound to: 0 - type: integer
Parameter C_RDCH_TYPE bound to: 0 - type: integer
Parameter C_AXIS_TYPE bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer
Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string
Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string
Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string
Parameter C_USE_ECC_WACH bound to: 0 - type: integer
Parameter C_USE_ECC_WDCH bound to: 0 - type: integer
Parameter C_USE_ECC_WRCH bound to: 0 - type: integer
Parameter C_USE_ECC_RACH bound to: 0 - type: integer
Parameter C_USE_ECC_RDCH bound to: 0 - type: integer
Parameter C_USE_ECC_AXIS bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer
Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer
Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer
Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer
Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer
Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer
Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer
Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer
INFO: [Synth 8-3491] module 'fifo_generator_v13_2_4' declared at 'd:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38586' bound to instance 'U0' of component 'fifo_generator_v13_2_4' [d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/synth/ad9361_fifo.vhd:543]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175]
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1226]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (1#1) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153]
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:205]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (2#1) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (7#1) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
INFO: [Synth 8-256] done synthesizing module 'ad9361_fifo' (21#1) [d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/synth/ad9361_fifo.vhd:73]
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_RST
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SRST
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SAFETY_CKT_WR_RST
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[3]
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[2]
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[1]
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[0]
WARNING: [Synth 8-3331] design wr_bin_cntr has unconnected port SRST
WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_EN_INTO_LOGIC
WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_RST_INTO_LOGIC
WARNING: [Synth 8-3331] design wr_logic has unconnected port RD_EN
WARNING: [Synth 8-3331] design wr_logic has unconnected port SRST_FULL_FF
WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_RST_BUSY
WARNING: [Synth 8-3331] design wr_logic has unconnected port EMPTY
WARNING: [Synth 8-3331] design wr_logic has unconnected port RAM_RD_EN
WARNING: [Synth 8-3331] design wr_logic has unconnected port ALMOST_EMPTY
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[3]
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[2]
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[1]
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[0]
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[3]
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[2]
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[1]
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[0]
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[3]
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[2]
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[1]
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[0]
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SRST
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SAFETY_CKT_RD_RST
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[3]
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[2]
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[1]
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[0]
WARNING: [Synth 8-3331] design rd_bin_cntr has unconnected port SRST
WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_EN_INTO_LOGIC
WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_RST_INTO_LOGIC
WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_RST_BUSY
WARNING: [Synth 8-3331] design rd_logic has unconnected port RAM_WR_EN
WARNING: [Synth 8-3331] design rd_logic has unconnected port RST_FULL_FF
WARNING: [Synth 8-3331] design rd_logic has unconnected port ALMOST_FULL_FB
WARNING: [Synth 8-3331] design rd_logic has unconnected port FULL
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[3]
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[2]
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[1]
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[0]
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[3]
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[2]
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[1]
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[0]
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[3]
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[2]
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[1]
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[0]
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[3]
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[2]
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[1]
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[0]
WARNING: [Synth 8-3331] design clk_x_pntrs has unconnected port WR_RST
WARNING: [Synth 8-3331] design clk_x_pntrs has unconnected port RD_RST
WARNING: [Synth 8-3331] design dmem has unconnected port SRST
WARNING: [Synth 8-3331] design memory has unconnected port RAM_REGOUT_EN
WARNING: [Synth 8-3331] design memory has unconnected port FAB_REGOUT_EN
WARNING: [Synth 8-3331] design memory has unconnected port SFT_RST
WARNING: [Synth 8-3331] design memory has unconnected port SRST
WARNING: [Synth 8-3331] design memory has unconnected port SAFETY_CKT_RD_RST
WARNING: [Synth 8-3331] design memory has unconnected port SLEEP
WARNING: [Synth 8-3331] design memory has unconnected port INJECTDBITERR
WARNING: [Synth 8-3331] design memory has unconnected port INJECTSBITERR
WARNING: [Synth 8-3331] design output_blk has unconnected port ALMOST_FULL_I
WARNING: [Synth 8-3331] design output_blk has unconnected port PROG_FULL_I
WARNING: [Synth 8-3331] design output_blk has unconnected port ALMOST_EMPTY_I
WARNING: [Synth 8-3331] design output_blk has unconnected port PROG_EMPTY_I
WARNING: [Synth 8-3331] design output_blk has unconnected port WR_ACK_I
WARNING: [Synth 8-3331] design output_blk has unconnected port VALID_I
WARNING: [Synth 8-3331] design output_blk has unconnected port OVERFLOW_I
WARNING: [Synth 8-3331] design output_blk has unconnected port UNDERFLOW_I
WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[4]
WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[3]
WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[2]
WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[1]
WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[0]
WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[4]
WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[3]
WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[2]
WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[1]
WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[0]
WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[4]
WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[3]
WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[2]
WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[1]
WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[0]
WARNING: [Synth 8-3331] design output_blk has unconnected port SBITERR_I
WARNING: [Synth 8-3331] design output_blk has unconnected port DBITERR_I
WARNING: [Synth 8-3331] design input_blk has unconnected port CLK
WARNING: [Synth 8-3331] design input_blk has unconnected port INT_CLK
WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[3]
WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[2]
WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[1]
WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[0]
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1055.152 ; gain = 347.004
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1055.152 ; gain = 347.004
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1055.152 ; gain = 347.004
---------------------------------------------------------------------------------
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo_ooc.xdc] for cell 'U0'
Finished Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo_ooc.xdc] for cell 'U0'
Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xdc] for cell 'U0'
Finished Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xdc] for cell 'U0'
Parsing XDC File [D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/dont_touch.xdc]
Finished Parsing XDC File [D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/dont_touch.xdc]
Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo_clocks.xdc] for cell 'U0'
Finished Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo_clocks.xdc] for cell 'U0'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ad9361_fifo_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/ad9361_fifo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ad9361_fifo_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/ad9361_fifo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ad9361_fifo_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/ad9361_fifo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ad9361_fifo_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/ad9361_fifo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1080.531 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1091.410 ; gain = 10.879
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k410tffg900-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/dont_touch.xdc, line 9).
Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint, line ).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 2
+---XORs :
2 Input 4 Bit XORs := 2
2 Input 1 Bit XORs := 22
+---Registers :
12 Bit Registers := 1
5 Bit Registers := 2
4 Bit Registers := 16
2 Bit Registers := 3
1 Bit Registers := 10
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module xpm_cdc_async_rst
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module xpm_cdc_single
Detailed RTL Component Info :
+---Registers :
5 Bit Registers := 1
Module reset_blk_ramfifo
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 6
Module dmem
Detailed RTL Component Info :
+---Registers :
12 Bit Registers := 1
Module xpm_cdc_gray
Detailed RTL Component Info :
+---XORs :
2 Input 4 Bit XORs := 1
2 Input 1 Bit XORs := 3
+---Registers :
4 Bit Registers := 5
Module rd_bin_cntr
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 2
Module compare
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
Module rd_status_flags_as
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module wr_bin_cntr
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 3
Module wr_status_flags_as
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 1540 (col length:140)
BRAMs: 1590 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-------------------------------------------------------------------------------+----------------+----------------------+--------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-------------------------------------------------------------------------------+----------------+----------------------+--------------+
|U0 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 12 | RAM32M x 2 |
+------------+-------------------------------------------------------------------------------+----------------+----------------------+--------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:18 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:18 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-------------------------------------------------------------------------------+----------------+----------------------+--------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-------------------------------------------------------------------------------+----------------+----------------------+--------------+
|U0 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 12 | RAM32M x 2 |
+------------+-------------------------------------------------------------------------------+----------------+----------------------+--------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:18 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:19 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:19 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:19 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:19 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:19 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:19 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |LUT1 | 2|
|2 |LUT2 | 14|
|3 |LUT3 | 5|
|4 |LUT4 | 9|
|5 |LUT5 | 1|
|6 |LUT6 | 4|
|7 |RAM32M | 2|
|8 |FDCE | 35|
|9 |FDPE | 17|
|10 |FDRE | 50|
+------+-------+------+
Report Instance Areas:
+------+-------------------------------------------------------------------------------------+-----------------------------+------+
| |Instance |Module |Cells |
+------+-------------------------------------------------------------------------------------+-----------------------------+------+
|1 |top | | 139|
|2 | U0 |fifo_generator_v13_2_4 | 139|
|3 | inst_fifo_gen |fifo_generator_v13_2_4_synth | 139|
|4 | \gconvfifo.rf |fifo_generator_top | 139|
|5 | \grf.rf |fifo_generator_ramfifo | 139|
|6 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs | 53|
|7 | wr_pntr_cdc_inst |xpm_cdc_gray__2 | 26|
|8 | rd_pntr_cdc_inst |xpm_cdc_gray | 26|
|9 | \gntv_or_sync_fifo.gl0.rd |rd_logic | 20|
|10 | \gras.rsts |rd_status_flags_as | 3|
|11 | rpntr |rd_bin_cntr | 17|
|12 | \gntv_or_sync_fifo.gl0.wr |wr_logic | 22|
|13 | \gwas.wsts |wr_status_flags_as | 4|
|14 | wpntr |wr_bin_cntr | 18|
|15 | \gntv_or_sync_fifo.mem |memory | 14|
|16 | \gdm.dm_gen.dm |dmem | 14|
|17 | rstblk |reset_blk_ramfifo | 30|
|18 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst |xpm_cdc_async_rst__2 | 2|
|19 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst |xpm_cdc_async_rst | 2|
|20 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd |xpm_cdc_single__2 | 5|
|21 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr |xpm_cdc_single | 5|
+------+-------------------------------------------------------------------------------------+-----------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:19 . Memory (MB): peak = 1091.410 ; gain = 383.262
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 439 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:03 ; elapsed = 00:00:17 . Memory (MB): peak = 1091.410 ; gain = 347.004
Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:19 . Memory (MB): peak = 1091.410 ; gain = 383.262
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1100.551 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 2 instances were transformed.
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 2 instances
INFO: [Common 17-83] Releasing license: Synthesis
28 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:24 . Memory (MB): peak = 1100.551 ; gain = 712.836
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1100.551 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo.dcp' has been generated.
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ad9361_fifo, cache-ID = 18e48aa99774dd44
INFO: [Coretcl 2-1174] Renamed 20 cell refs.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1100.551 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file ad9361_fifo_utilization_synth.rpt -pb ad9361_fifo_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sat Mar 18 22:56:31 2023...
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_sim_netlist.v
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modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_sim_netlist.vhdl
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modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 22:56:31 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_stub.v
// Design : ad9361_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *)
module ad9361_fifo(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[11:0],wr_en,rd_en,dout[11:0],full,empty" */;
input rst;
input wr_clk;
input rd_clk;
input [11:0]din;
input wr_en;
input rd_en;
output [11:0]dout;
output full;
output empty;
endmodule
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 22:56:31 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_stub.vhdl
-- Design : ad9361_fifo
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ad9361_fifo is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end ad9361_fifo;
architecture stub of ad9361_fifo is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[11:0],wr_en,rd_en,dout[11:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3";
begin
end;
modules/xc7k410tffg900-2/ad9361_mapping/ip/managed_ip_project/managed_ip_project.runs/ad9361_fifo_synth_1/ad9361_fifo_utilization_synth.pb
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