Optimize project dir structure, add dl814_k7 proj.

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/README.txt

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+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8/cmpy_18x8.veo

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+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:cmpy:6.0
+// IP Revision: 17
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+cmpy_18x8 your_instance_name (
+  .aclk(aclk),                              // input wire aclk
+  .s_axis_a_tvalid(s_axis_a_tvalid),        // input wire s_axis_a_tvalid
+  .s_axis_a_tdata(s_axis_a_tdata),          // input wire [47 : 0] s_axis_a_tdata
+  .s_axis_b_tvalid(s_axis_b_tvalid),        // input wire s_axis_b_tvalid
+  .s_axis_b_tdata(s_axis_b_tdata),          // input wire [15 : 0] s_axis_b_tdata
+  .m_axis_dout_tvalid(m_axis_dout_tvalid),  // output wire m_axis_dout_tvalid
+  .m_axis_dout_tdata(m_axis_dout_tdata)    // output wire [63 : 0] m_axis_dout_tdata
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file cmpy_18x8.v when simulating
+// the core, cmpy_18x8. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8/cmpy_18x8.vho

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+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:cmpy:6.0
+-- IP Revision: 17
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT cmpy_18x8
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_a_tvalid : IN STD_LOGIC;
+    s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+    s_axis_b_tvalid : IN STD_LOGIC;
+    s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    m_axis_dout_tvalid : OUT STD_LOGIC;
+    m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : cmpy_18x8
+  PORT MAP (
+    aclk => aclk,
+    s_axis_a_tvalid => s_axis_a_tvalid,
+    s_axis_a_tdata => s_axis_a_tdata,
+    s_axis_b_tvalid => s_axis_b_tvalid,
+    s_axis_b_tdata => s_axis_b_tdata,
+    m_axis_dout_tvalid => m_axis_dout_tvalid,
+    m_axis_dout_tdata => m_axis_dout_tdata
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file cmpy_18x8.vhd when simulating
+-- the core, cmpy_18x8. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8/cmpy_18x8_stub.v

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+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:15:41 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v
+// Design      : cmpy_18x8
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *)
+module cmpy_18x8(aclk, s_axis_a_tvalid, s_axis_a_tdata, 
+  s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
+/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]" */;
+  input aclk;
+  input s_axis_a_tvalid;
+  input [47:0]s_axis_a_tdata;
+  input s_axis_b_tvalid;
+  input [15:0]s_axis_b_tdata;
+  output m_axis_dout_tvalid;
+  output [63:0]m_axis_dout_tdata;
+endmodule

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8/cmpy_18x8_stub.vhdl

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+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:15:41 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl
+-- Design      : cmpy_18x8
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity cmpy_18x8 is
+  Port ( 
+    aclk : in STD_LOGIC;
+    s_axis_a_tvalid : in STD_LOGIC;
+    s_axis_a_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
+    s_axis_b_tvalid : in STD_LOGIC;
+    s_axis_b_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    m_axis_dout_tvalid : out STD_LOGIC;
+    m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 )
+  );
+
+end cmpy_18x8;
+
+architecture stub of cmpy_18x8 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3";
+begin
+end;

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8/demo_tb/tb_cmpy_18x8.vhd

@@ -0,0 +1,387 @@
+--------------------------------------------------------------------------------
+-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+-- Description:
+-- This is an example testbench for the Complex Multiplier IP core.
+-- The testbench has been generated by Vivado to accompany the IP core
+-- instance you have generated.
+--
+-- This testbench is for demonstration purposes only.  See note below for
+-- instructions on how to use it with your core.
+--
+-- See the Complex Multiplier product guide for further information
+-- about this core.
+--
+--------------------------------------------------------------------------------
+-- Using this testbench
+--
+-- This testbench instantiates your generated Complex Multiplier core
+-- instance named "cmpy_18x8".
+--
+-- Use Vivado's Run Simulation flow to run this testbench.  See the Vivado
+-- documentation for details.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity tb_cmpy_18x8 is
+end tb_cmpy_18x8;
+
+architecture tb of tb_cmpy_18x8 is
+
+  -----------------------------------------------------------------------
+  -- Timing constants
+  -----------------------------------------------------------------------
+  constant CLOCK_PERIOD : time := 100 ns;
+  constant T_HOLD       : time := 10 ns;
+  constant T_STROBE     : time := CLOCK_PERIOD - (1 ns);
+  constant TEST_CYCLES  : integer := 3000;
+  constant PHASE_CYCLES : integer := 1000;
+
+  -----------------------------------------------------------------------
+  -- DUT input signals
+  -----------------------------------------------------------------------
+
+  -- General inputs
+  signal aclk               : std_logic := '0';  -- the master clock
+
+  -- Slave channel A inputs
+  signal s_axis_a_tvalid    : std_logic := '0';  -- TVALID for channel A
+  signal s_axis_a_tdata     : std_logic_vector(47 downto 0) := (others => '0');  -- TDATA for channel A
+
+  -- Slave channel B inputs
+  signal s_axis_b_tvalid    : std_logic := '0';  -- TVALID for channel B
+  signal s_axis_b_tdata     : std_logic_vector(15 downto 0) := (others => '0');  -- TDATA for channel B
+
+  -----------------------------------------------------------------------
+  -- DUT output signals
+  -----------------------------------------------------------------------
+
+  -- Master channel DOUT outputs
+  signal m_axis_dout_tvalid : std_logic := '0';  -- TVALID for channel DOUT
+  signal m_axis_dout_tdata  : std_logic_vector(63 downto 0) := (others => '0');  -- TDATA for channel DOUT
+
+  -----------------------------------------------------------------------
+  -- Aliases for AXI channel TDATA fields
+  -- These are a convenience for viewing data in a simulator waveform viewer.
+  -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
+  -- to prevent the simulator optimizing away these signals.
+  -----------------------------------------------------------------------
+  signal s_axis_a_tdata_real     : std_logic_vector(17 downto 0) := (others => '0');
+  signal s_axis_a_tdata_imag     : std_logic_vector(17 downto 0) := (others => '0');
+  signal s_axis_b_tdata_real     : std_logic_vector(7 downto 0) := (others => '0');
+  signal s_axis_b_tdata_imag     : std_logic_vector(7 downto 0) := (others => '0');
+  signal m_axis_dout_tdata_real  : std_logic_vector(26 downto 0) := (others => '0');
+  signal m_axis_dout_tdata_imag  : std_logic_vector(26 downto 0) := (others => '0');
+
+  -----------------------------------------------------------------------
+  -- Testbench signals
+  -----------------------------------------------------------------------
+
+  signal cycles       : integer   := 0;    -- Clock cycle counter
+
+  -----------------------------------------------------------------------
+  -- Constants, types and functions to create input data
+  -- Treat the complex multiplier as a mixer that is combining two
+  -- sinusoids exp(+/-jwt) of different frequencies and amplitudes:
+  --   channel A: exp(+jwt), frequency = clock / 30, amplitude = fullscale >> 3
+  --   channel B: exp(-jwt), frequency = clock / 32, amplitude = fullscale
+  -- The output of the complex multiplier is a sinusoid with a frequency
+  -- equal to the difference between the input frequencies.
+  -----------------------------------------------------------------------
+
+  constant IP_A_DEPTH : integer := 30;
+  constant IP_A_WIDTH : integer := 18;
+  constant IP_A_SHIFT : integer := 3;  -- bit shift for amplitude
+  constant IP_B_DEPTH : integer := 32;
+  constant IP_B_WIDTH : integer := 8;
+  constant IP_B_SHIFT : integer := 0;  -- no bit shift, max amplitude
+  type T_IP_INT_ENTRY is record
+    re : integer;
+    im : integer;
+  end record;
+  type T_IP_A_ENTRY is record
+    re : std_logic_vector(IP_A_WIDTH-1 downto 0);
+    im : std_logic_vector(IP_A_WIDTH-1 downto 0);
+  end record;
+  type T_IP_B_ENTRY is record
+    re : std_logic_vector(IP_B_WIDTH-1 downto 0);
+    im : std_logic_vector(IP_B_WIDTH-1 downto 0);
+  end record;
+  type T_IP_A_TABLE is array (0 to IP_A_DEPTH-1) of T_IP_A_ENTRY;
+  type T_IP_B_TABLE is array (0 to IP_B_DEPTH-1) of T_IP_B_ENTRY;
+
+  -- Common function to calculate sine and cosine values
+  function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is
+    variable result : T_IP_INT_ENTRY;
+    variable theta : real;
+    variable limited_width : integer := width - 2;
+  begin
+    if limited_width > 30 then
+      limited_width := 30;
+    end if;
+    theta := real(index) / real(depth) * 2.0 * MATH_PI;
+    result.re := integer(round(cos(theta) * real(2**limited_width-1)));
+    result.im := integer(round(sin(theta) * real(2**limited_width-1)));
+    return result;
+  end function create_ip_entry;
+
+  -- Use separate functions to calculate channel A and B sinusoids as they return different types
+  function create_ip_a_table return T_IP_A_TABLE is
+    variable result : T_IP_A_TABLE;
+    variable entry_int : T_IP_INT_ENTRY;
+  begin
+    for i in 0 to IP_A_DEPTH-1 loop
+      entry_int := create_ip_entry(i, IP_A_DEPTH, IP_A_WIDTH - IP_A_SHIFT);
+      result(i).re := std_logic_vector(to_signed(entry_int.re, IP_A_WIDTH));
+      result(i).im := std_logic_vector(to_signed(entry_int.im, IP_A_WIDTH));
+    end loop;
+    return result;
+  end function create_ip_a_table;
+
+  function create_ip_b_table return T_IP_B_TABLE is
+    variable result : T_IP_B_TABLE;
+    variable entry_int : T_IP_INT_ENTRY;
+  begin
+    for i in 0 to IP_B_DEPTH-1 loop
+      entry_int := create_ip_entry(IP_B_DEPTH-1-i, IP_B_DEPTH, IP_B_WIDTH - IP_B_SHIFT);  -- note rotation direction
+      result(i).re := std_logic_vector(to_signed(entry_int.re, IP_B_WIDTH));
+      result(i).im := std_logic_vector(to_signed(entry_int.im, IP_B_WIDTH));
+    end loop;
+    return result;
+  end function create_ip_b_table;
+
+  -- Call the functions to create the data
+  constant IP_A_DATA : T_IP_A_TABLE := create_ip_a_table;
+  constant IP_B_DATA : T_IP_B_TABLE := create_ip_b_table;
+
+
+begin
+
+  -----------------------------------------------------------------------
+  -- Instantiate the DUT
+  -----------------------------------------------------------------------
+
+  dut : entity work.cmpy_18x8
+    port map (
+      aclk                => aclk,
+      s_axis_a_tvalid     => s_axis_a_tvalid,
+      s_axis_a_tdata      => s_axis_a_tdata,
+      s_axis_b_tvalid     => s_axis_b_tvalid,
+      s_axis_b_tdata      => s_axis_b_tdata,
+      m_axis_dout_tvalid  => m_axis_dout_tvalid,
+      m_axis_dout_tdata   => m_axis_dout_tdata
+      );
+
+  -----------------------------------------------------------------------
+  -- Generate clock
+  -----------------------------------------------------------------------
+
+  clock_gen : process
+  begin
+    aclk <= '0';
+    wait for CLOCK_PERIOD;
+    loop
+      cycles <= cycles + 1;
+      aclk <= '0';
+      wait for CLOCK_PERIOD/2;
+      aclk <= '1';
+      wait for CLOCK_PERIOD/2;
+      if cycles >= TEST_CYCLES then
+        report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
+        wait;
+      end if;
+    end loop;
+  end process clock_gen;
+
+  -----------------------------------------------------------------------
+  -- Generate inputs
+  -----------------------------------------------------------------------
+
+  stimuli : process
+    variable ip_a_index       : integer   := 0;
+    variable ip_b_index       : integer   := 0;
+    variable a_tvalid_nxt     : std_logic := '0';
+    variable b_tvalid_nxt     : std_logic := '0';
+    variable phase2_cycles : integer := 1;
+    variable phase2_count  : integer := 0;
+    constant PHASE2_LIMIT  : integer := 30;
+  begin
+
+    -- Test is stopped in clock_gen process, use endless loop here
+    loop
+
+      -- Drive inputs T_HOLD time after rising edge of clock
+      wait until rising_edge(aclk);
+      wait for T_HOLD;
+
+      -- Drive AXI TVALID signals to demonstrate different types of operation
+      case cycles is  -- do different types of operation at different phases of the test
+        when 0 to PHASE_CYCLES * 1 - 1 =>
+          -- Phase 1: inputs always valid, no missing input data
+          a_tvalid_nxt    := '1';
+          b_tvalid_nxt    := '1';
+        when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
+          -- Phase 2: deprive channel A of valid transactions at an increasing rate
+          b_tvalid_nxt    := '1';
+          if phase2_count < phase2_cycles then
+            a_tvalid_nxt := '0';
+          else
+            a_tvalid_nxt := '1';
+          end if;
+          phase2_count := phase2_count + 1;
+          if phase2_count >= PHASE2_LIMIT then
+            phase2_count  := 0;
+            phase2_cycles := phase2_cycles + 1;
+          end if;
+        when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
+          -- Phase 3: deprive channel A of 1 out of 2 transactions, and channel B of 1 out of 3 transactions
+          if cycles mod 2 = 0 then
+            a_tvalid_nxt := '0';
+          else
+            a_tvalid_nxt := '1';
+          end if;
+          if cycles mod 3 = 0 then
+            b_tvalid_nxt := '0';
+          else
+            b_tvalid_nxt := '1';
+          end if;
+        when others =>
+          -- Test will stop imminently - do nothing
+          null;
+      end case;
+
+      -- Drive handshake signals with local variable values
+      s_axis_a_tvalid <= a_tvalid_nxt;
+      s_axis_b_tvalid <= b_tvalid_nxt;
+
+      -- Drive AXI slave channel A payload
+      -- Drive '0's on payload signals when not valid
+      if a_tvalid_nxt /= '1' then
+        s_axis_a_tdata <= (others => '0');
+      else
+        -- TDATA: Real and imaginary components are each 18 bits wide and byte-aligned at their LSBs
+        s_axis_a_tdata(17 downto 0) <= IP_A_DATA(ip_a_index).re;
+        s_axis_a_tdata(23 downto 18) <= (others => IP_A_DATA(ip_a_index).re(17));  -- sign-extend;
+        s_axis_a_tdata(41 downto 24) <= IP_A_DATA(ip_a_index).im;
+        s_axis_a_tdata(47 downto 42) <= (others => IP_A_DATA(ip_a_index).im(17));  -- sign-extend;
+      end if;
+
+      -- Drive AXI slave channel B payload
+      -- Drive '0's on payload signals when not valid
+      if b_tvalid_nxt /= '1' then
+        s_axis_b_tdata <= (others => '0');
+      else
+        -- TDATA: Real and imaginary components are each 8 bits wide and byte-aligned at their LSBs
+        s_axis_b_tdata(7 downto 0) <= IP_B_DATA(ip_b_index).re;
+        s_axis_b_tdata(15 downto 8) <= IP_B_DATA(ip_b_index).im;
+      end if;
+
+      -- Increment input data indices
+      if a_tvalid_nxt = '1' then
+        ip_a_index := ip_a_index + 1;
+        if ip_a_index = IP_A_DEPTH then
+          ip_a_index := 0;
+        end if;
+      end if;
+      if b_tvalid_nxt = '1' then
+        ip_b_index := ip_b_index + 1;
+        if ip_b_index = IP_B_DEPTH then
+          ip_b_index := 0;
+        end if;
+      end if;
+
+    end loop;
+
+  end process stimuli;
+
+  -----------------------------------------------------------------------
+  -- Check outputs
+  -----------------------------------------------------------------------
+
+  check_outputs : process
+    variable check_ok : boolean := true;
+  begin
+
+    -- Check outputs T_STROBE time after rising edge of clock
+    wait until rising_edge(aclk);
+    wait for T_STROBE;
+
+    -- Do not check the output payload values, as this requires the behavioral model
+    -- which would make this demonstration testbench unwieldy.
+    -- Instead, check the protocol of the DOUT channel:
+    -- check that the payload is valid (not X) when TVALID is high
+
+    if m_axis_dout_tvalid = '1' then
+      if is_x(m_axis_dout_tdata) then
+        report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
+        check_ok := false;
+      end if;
+
+    end if;
+
+    assert check_ok
+      report "ERROR: terminating test with failures." severity failure;
+
+  end process check_outputs;
+
+  -----------------------------------------------------------------------
+  -- Assign TDATA fields to aliases, for easy simulator waveform viewing
+  -----------------------------------------------------------------------
+
+  s_axis_a_tdata_real     <= s_axis_a_tdata(17 downto 0);
+  s_axis_a_tdata_imag     <= s_axis_a_tdata(41 downto 24);
+  s_axis_b_tdata_real     <= s_axis_b_tdata(7 downto 0);
+  s_axis_b_tdata_imag     <= s_axis_b_tdata(15 downto 8);
+  m_axis_dout_tdata_real  <= m_axis_dout_tdata(26 downto 0);
+  m_axis_dout_tdata_imag  <= m_axis_dout_tdata(58 downto 32);
+
+end tb;
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8/sim/cmpy_18x8.vhd

@@ -0,0 +1,202 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:cmpy:6.0
+-- IP Revision: 17
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY cmpy_v6_0_17;
+USE cmpy_v6_0_17.cmpy_v6_0_17;
+
+ENTITY cmpy_18x8 IS
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_a_tvalid : IN STD_LOGIC;
+    s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+    s_axis_b_tvalid : IN STD_LOGIC;
+    s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    m_axis_dout_tvalid : OUT STD_LOGIC;
+    m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+  );
+END cmpy_18x8;
+
+ARCHITECTURE cmpy_18x8_arch OF cmpy_18x8 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF cmpy_18x8_arch: ARCHITECTURE IS "yes";
+  COMPONENT cmpy_v6_0_17 IS
+    GENERIC (
+      C_VERBOSITY : INTEGER;
+      C_XDEVICEFAMILY : STRING;
+      C_XDEVICE : STRING;
+      C_A_WIDTH : INTEGER;
+      C_B_WIDTH : INTEGER;
+      C_OUT_WIDTH : INTEGER;
+      C_LATENCY : INTEGER;
+      C_MULT_TYPE : INTEGER;
+      C_OPTIMIZE_GOAL : INTEGER;
+      HAS_NEGATE : INTEGER;
+      SINGLE_OUTPUT : INTEGER;
+      ROUND : INTEGER;
+      USE_DSP_CASCADES : INTEGER;
+      C_THROTTLE_SCHEME : INTEGER;
+      C_HAS_ACLKEN : INTEGER;
+      C_HAS_ARESETN : INTEGER;
+      C_HAS_S_AXIS_A_TUSER : INTEGER;
+      C_HAS_S_AXIS_A_TLAST : INTEGER;
+      C_HAS_S_AXIS_B_TUSER : INTEGER;
+      C_HAS_S_AXIS_B_TLAST : INTEGER;
+      C_HAS_S_AXIS_CTRL_TUSER : INTEGER;
+      C_HAS_S_AXIS_CTRL_TLAST : INTEGER;
+      C_TLAST_RESOLUTION : INTEGER;
+      C_S_AXIS_A_TDATA_WIDTH : INTEGER;
+      C_S_AXIS_A_TUSER_WIDTH : INTEGER;
+      C_S_AXIS_B_TDATA_WIDTH : INTEGER;
+      C_S_AXIS_B_TUSER_WIDTH : INTEGER;
+      C_S_AXIS_CTRL_TDATA_WIDTH : INTEGER;
+      C_S_AXIS_CTRL_TUSER_WIDTH : INTEGER;
+      C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
+      C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
+    );
+    PORT (
+      aclk : IN STD_LOGIC;
+      aclken : IN STD_LOGIC;
+      aresetn : IN STD_LOGIC;
+      s_axis_a_tvalid : IN STD_LOGIC;
+      s_axis_a_tready : OUT STD_LOGIC;
+      s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_a_tlast : IN STD_LOGIC;
+      s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+      s_axis_b_tvalid : IN STD_LOGIC;
+      s_axis_b_tready : OUT STD_LOGIC;
+      s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_b_tlast : IN STD_LOGIC;
+      s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      s_axis_ctrl_tvalid : IN STD_LOGIC;
+      s_axis_ctrl_tready : OUT STD_LOGIC;
+      s_axis_ctrl_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_ctrl_tlast : IN STD_LOGIC;
+      s_axis_ctrl_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      m_axis_dout_tvalid : OUT STD_LOGIC;
+      m_axis_dout_tready : IN STD_LOGIC;
+      m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_dout_tlast : OUT STD_LOGIC;
+      m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+    );
+  END COMPONENT cmpy_v6_0_17;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_dout_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DOUT, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 6, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
+BEGIN
+  U0 : cmpy_v6_0_17
+    GENERIC MAP (
+      C_VERBOSITY => 0,
+      C_XDEVICEFAMILY => "kintex7",
+      C_XDEVICE => "xc7k410t",
+      C_A_WIDTH => 18,
+      C_B_WIDTH => 8,
+      C_OUT_WIDTH => 27,
+      C_LATENCY => 6,
+      C_MULT_TYPE => 1,
+      C_OPTIMIZE_GOAL => 0,
+      HAS_NEGATE => 0,
+      SINGLE_OUTPUT => 0,
+      ROUND => 0,
+      USE_DSP_CASCADES => 1,
+      C_THROTTLE_SCHEME => 3,
+      C_HAS_ACLKEN => 0,
+      C_HAS_ARESETN => 0,
+      C_HAS_S_AXIS_A_TUSER => 0,
+      C_HAS_S_AXIS_A_TLAST => 0,
+      C_HAS_S_AXIS_B_TUSER => 0,
+      C_HAS_S_AXIS_B_TLAST => 0,
+      C_HAS_S_AXIS_CTRL_TUSER => 0,
+      C_HAS_S_AXIS_CTRL_TLAST => 0,
+      C_TLAST_RESOLUTION => 0,
+      C_S_AXIS_A_TDATA_WIDTH => 48,
+      C_S_AXIS_A_TUSER_WIDTH => 1,
+      C_S_AXIS_B_TDATA_WIDTH => 16,
+      C_S_AXIS_B_TUSER_WIDTH => 1,
+      C_S_AXIS_CTRL_TDATA_WIDTH => 8,
+      C_S_AXIS_CTRL_TUSER_WIDTH => 1,
+      C_M_AXIS_DOUT_TDATA_WIDTH => 64,
+      C_M_AXIS_DOUT_TUSER_WIDTH => 1
+    )
+    PORT MAP (
+      aclk => aclk,
+      aclken => '1',
+      aresetn => '1',
+      s_axis_a_tvalid => s_axis_a_tvalid,
+      s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_a_tlast => '0',
+      s_axis_a_tdata => s_axis_a_tdata,
+      s_axis_b_tvalid => s_axis_b_tvalid,
+      s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_b_tlast => '0',
+      s_axis_b_tdata => s_axis_b_tdata,
+      s_axis_ctrl_tvalid => '0',
+      s_axis_ctrl_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_ctrl_tlast => '0',
+      s_axis_ctrl_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      m_axis_dout_tvalid => m_axis_dout_tvalid,
+      m_axis_dout_tready => '0',
+      m_axis_dout_tdata => m_axis_dout_tdata
+    );
+END cmpy_18x8_arch;

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b/dds_32b_8b.veo

@@ -0,0 +1,69 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:dds_compiler:6.0
+// IP Revision: 18
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+dds_32b_8b your_instance_name (
+  .aclk(aclk),                                  // input wire aclk
+  .s_axis_config_tvalid(s_axis_config_tvalid),  // input wire s_axis_config_tvalid
+  .s_axis_config_tdata(s_axis_config_tdata),    // input wire [31 : 0] s_axis_config_tdata
+  .m_axis_data_tvalid(m_axis_data_tvalid),      // output wire m_axis_data_tvalid
+  .m_axis_data_tdata(m_axis_data_tdata)        // output wire [15 : 0] m_axis_data_tdata
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file dds_32b_8b.v when simulating
+// the core, dds_32b_8b. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b/dds_32b_8b.vho

@@ -0,0 +1,83 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
+-- IP Revision: 18
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT dds_32b_8b
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_config_tvalid : IN STD_LOGIC;
+    s_axis_config_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axis_data_tvalid : OUT STD_LOGIC;
+    m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : dds_32b_8b
+  PORT MAP (
+    aclk => aclk,
+    s_axis_config_tvalid => s_axis_config_tvalid,
+    s_axis_config_tdata => s_axis_config_tdata,
+    m_axis_data_tvalid => m_axis_data_tvalid,
+    m_axis_data_tdata => m_axis_data_tdata
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file dds_32b_8b.vhd when simulating
+-- the core, dds_32b_8b. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b/dds_32b_8b_stub.v

@@ -0,0 +1,25 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:15:37 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v
+// Design      : dds_32b_8b
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "dds_compiler_v6_0_18,Vivado 2019.1.3" *)
+module dds_32b_8b(aclk, s_axis_config_tvalid, 
+  s_axis_config_tdata, m_axis_data_tvalid, m_axis_data_tdata)
+/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tvalid,s_axis_config_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
+  input aclk;
+  input s_axis_config_tvalid;
+  input [31:0]s_axis_config_tdata;
+  output m_axis_data_tvalid;
+  output [15:0]m_axis_data_tdata;
+endmodule

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b/dds_32b_8b_stub.vhdl

@@ -0,0 +1,34 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:15:37 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl
+-- Design      : dds_32b_8b
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity dds_32b_8b is
+  Port ( 
+    aclk : in STD_LOGIC;
+    s_axis_config_tvalid : in STD_LOGIC;
+    s_axis_config_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_axis_data_tvalid : out STD_LOGIC;
+    m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
+  );
+
+end dds_32b_8b;
+
+architecture stub of dds_32b_8b is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_config_tvalid,s_axis_config_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "dds_compiler_v6_0_18,Vivado 2019.1.3";
+begin
+end;

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b/demo_tb/tb_dds_32b_8b.vhd

@@ -0,0 +1,235 @@
+--------------------------------------------------------------------------------
+-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+-- Description:
+-- This is an example testbench for the DDS Compiler IP core.
+-- The testbench has been generated by Vivado to accompany the IP core
+-- instance you have generated.
+--
+-- This testbench is for demonstration purposes only.  See note below for
+-- instructions on how to use it with your core.
+--
+-- See the DDS Compiler product guide for further information
+-- about this core.
+--
+--------------------------------------------------------------------------------
+-- Using this testbench
+--
+-- This testbench instantiates your generated DDS Compiler core
+-- instance named "dds_32b_8b".
+--
+-- Use Vivado's Run Simulation flow to run this testbench.  See the Vivado
+-- documentation for details.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity tb_dds_32b_8b is
+end tb_dds_32b_8b;
+
+architecture tb of tb_dds_32b_8b is
+
+  -----------------------------------------------------------------------
+  -- Timing constants
+  -----------------------------------------------------------------------
+  constant CLOCK_PERIOD : time := 100 ns;
+  constant T_HOLD       : time := 10 ns;
+  constant T_STROBE     : time := CLOCK_PERIOD - (1 ns);
+
+  -----------------------------------------------------------------------
+  -- DUT input signals
+  -----------------------------------------------------------------------
+
+  -- General inputs
+  signal aclk                            : std_logic := '0';  -- the master clock
+
+  -- Config slave channel signals
+  signal s_axis_config_tvalid            : std_logic := '0';  -- payload is valid
+  signal s_axis_config_tdata             : std_logic_vector(31 downto 0) := (others => '0');  -- data payload
+
+  -- Data master channel signals
+  signal m_axis_data_tvalid              : std_logic := '0';  -- payload is valid
+  signal m_axis_data_tdata               : std_logic_vector(15 downto 0) := (others => '0');  -- data payload
+
+  -----------------------------------------------------------------------
+  -- Aliases for AXI channel TDATA and TUSER fields
+  -- These are a convenience for viewing data in a simulator waveform viewer.
+  -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
+  -- to prevent the simulator optimizing away these signals.
+  -----------------------------------------------------------------------
+
+  -- Config slave channel alias signals
+  signal s_axis_config_tdata_inc       : std_logic_vector(31 downto 0) := (others => '0');
+
+  -- Data master channel alias signals
+  signal m_axis_data_tdata_cosine      : std_logic_vector(7 downto 0) := (others => '0');
+  signal m_axis_data_tdata_sine        : std_logic_vector(7 downto 0) := (others => '0');
+
+
+  signal end_of_simulation : boolean := false;
+     
+begin
+
+  -----------------------------------------------------------------------
+  -- Instantiate the DUT
+  -----------------------------------------------------------------------
+
+  dut : entity work.dds_32b_8b
+    port map (
+      aclk                            => aclk
+      ,s_axis_config_tvalid            => s_axis_config_tvalid
+      ,s_axis_config_tdata             => s_axis_config_tdata
+      ,m_axis_data_tvalid              => m_axis_data_tvalid
+      ,m_axis_data_tdata               => m_axis_data_tdata
+      );
+
+  -----------------------------------------------------------------------
+  -- Generate clock
+  -----------------------------------------------------------------------
+
+  clock_gen : process
+  begin
+    aclk <= '0';
+    if (end_of_simulation) then
+      wait;
+    else
+      wait for CLOCK_PERIOD;
+      loop
+        aclk <= '0';
+        wait for CLOCK_PERIOD/2;
+        aclk <= '1';
+        wait for CLOCK_PERIOD/2;
+      end loop;
+    end if;
+  end process clock_gen;
+
+  -----------------------------------------------------------------------
+  -- Generate inputs
+  -----------------------------------------------------------------------
+
+  stimuli : process
+  begin
+
+    -- Drive inputs T_HOLD time after rising edge of clock
+    wait until rising_edge(aclk);
+    wait for T_HOLD;
+
+    -- Program the core with the initial configuration.
+    -- The phase increment value here is derived from the output frequency value set in the CORE Generator GUI.
+    s_axis_config_tvalid <= '1';
+    s_axis_config_tdata <= (others => '0');  -- set unused TDATA bits to zero
+    s_axis_config_tdata(31 downto 0) <= "00000000000000000000000000000000";  -- phase increment
+    wait for CLOCK_PERIOD;
+    s_axis_config_tvalid <= '0';
+
+    -- Run for long enough to produce 5 periods of outputs
+    wait for CLOCK_PERIOD * 5;
+
+    -- Configure the core with a different configuration:
+    --   set phase increment to half of its current value
+    s_axis_config_tvalid <= '1';
+    s_axis_config_tdata <= (others => '0');  -- set unused TDATA bits to zero
+    s_axis_config_tdata(31 downto 0) <= "00000000000000000000000000000000";  -- current phase increment / 2
+    wait for CLOCK_PERIOD;
+    s_axis_config_tvalid <= '0';
+
+    -- Run for long enough to produce 5 periods of outputs
+    wait for CLOCK_PERIOD * 10;
+
+    -- End of test
+    end_of_simulation <= true;           
+    report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
+    wait;
+
+  end process stimuli;
+
+  -----------------------------------------------------------------------
+  -- Check outputs
+  -----------------------------------------------------------------------
+
+  check_outputs : process
+    variable check_ok : boolean := true;
+  begin
+
+    -- Check outputs T_STROBE time after rising edge of clock
+    wait until rising_edge(aclk);
+    wait for T_STROBE;
+
+    -- Do not check the output payload values, as this requires the behavioral model
+    -- which would make this demonstration testbench unwieldy.
+    -- Instead, check the protocol of the data master channel:
+    -- check that the payload is valid (not X) when TVALID is high
+
+    if m_axis_data_tvalid = '1' then
+      if is_x(m_axis_data_tdata) then
+        report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
+        check_ok := false;
+      end if;
+
+    end if;
+
+    assert check_ok
+      report "ERROR: terminating test with failures." severity failure;
+
+  end process check_outputs;
+
+  -----------------------------------------------------------------------
+  -- Assign TDATA fields to aliases, for easy simulator waveform viewing
+  -----------------------------------------------------------------------
+
+  -- Config slave channel alias signals
+  s_axis_config_tdata_inc       <= s_axis_config_tdata(31 downto 0);
+
+  -- Data master channel alias signals: update these only when they are valid
+  m_axis_data_tdata_cosine      <= m_axis_data_tdata(7 downto 0) when m_axis_data_tvalid = '1';
+  m_axis_data_tdata_sine        <= m_axis_data_tdata(15 downto 8) when m_axis_data_tvalid = '1';
+
+end tb;
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b/sim/dds_32b_8b.vhd

@@ -0,0 +1,232 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
+-- IP Revision: 18
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY dds_compiler_v6_0_18;
+USE dds_compiler_v6_0_18.dds_compiler_v6_0_18;
+
+ENTITY dds_32b_8b IS
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_config_tvalid : IN STD_LOGIC;
+    s_axis_config_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axis_data_tvalid : OUT STD_LOGIC;
+    m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+  );
+END dds_32b_8b;
+
+ARCHITECTURE dds_32b_8b_arch OF dds_32b_8b IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF dds_32b_8b_arch: ARCHITECTURE IS "yes";
+  COMPONENT dds_compiler_v6_0_18 IS
+    GENERIC (
+      C_XDEVICEFAMILY : STRING;
+      C_MODE_OF_OPERATION : INTEGER;
+      C_MODULUS : INTEGER;
+      C_ACCUMULATOR_WIDTH : INTEGER;
+      C_CHANNELS : INTEGER;
+      C_HAS_PHASE_OUT : INTEGER;
+      C_HAS_PHASEGEN : INTEGER;
+      C_HAS_SINCOS : INTEGER;
+      C_LATENCY : INTEGER;
+      C_MEM_TYPE : INTEGER;
+      C_NEGATIVE_COSINE : INTEGER;
+      C_NEGATIVE_SINE : INTEGER;
+      C_NOISE_SHAPING : INTEGER;
+      C_OUTPUTS_REQUIRED : INTEGER;
+      C_OUTPUT_FORM : INTEGER;
+      C_OUTPUT_WIDTH : INTEGER;
+      C_PHASE_ANGLE_WIDTH : INTEGER;
+      C_PHASE_INCREMENT : INTEGER;
+      C_PHASE_INCREMENT_VALUE : STRING;
+      C_RESYNC : INTEGER;
+      C_PHASE_OFFSET : INTEGER;
+      C_PHASE_OFFSET_VALUE : STRING;
+      C_OPTIMISE_GOAL : INTEGER;
+      C_USE_DSP48 : INTEGER;
+      C_POR_MODE : INTEGER;
+      C_AMPLITUDE : INTEGER;
+      C_HAS_ACLKEN : INTEGER;
+      C_HAS_ARESETN : INTEGER;
+      C_HAS_TLAST : INTEGER;
+      C_HAS_TREADY : INTEGER;
+      C_HAS_S_PHASE : INTEGER;
+      C_S_PHASE_TDATA_WIDTH : INTEGER;
+      C_S_PHASE_HAS_TUSER : INTEGER;
+      C_S_PHASE_TUSER_WIDTH : INTEGER;
+      C_HAS_S_CONFIG : INTEGER;
+      C_S_CONFIG_SYNC_MODE : INTEGER;
+      C_S_CONFIG_TDATA_WIDTH : INTEGER;
+      C_HAS_M_DATA : INTEGER;
+      C_M_DATA_TDATA_WIDTH : INTEGER;
+      C_M_DATA_HAS_TUSER : INTEGER;
+      C_M_DATA_TUSER_WIDTH : INTEGER;
+      C_HAS_M_PHASE : INTEGER;
+      C_M_PHASE_TDATA_WIDTH : INTEGER;
+      C_M_PHASE_HAS_TUSER : INTEGER;
+      C_M_PHASE_TUSER_WIDTH : INTEGER;
+      C_DEBUG_INTERFACE : INTEGER;
+      C_CHAN_WIDTH : INTEGER
+    );
+    PORT (
+      aclk : IN STD_LOGIC;
+      aclken : IN STD_LOGIC;
+      aresetn : IN STD_LOGIC;
+      s_axis_phase_tvalid : IN STD_LOGIC;
+      s_axis_phase_tready : OUT STD_LOGIC;
+      s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_phase_tlast : IN STD_LOGIC;
+      s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_config_tvalid : IN STD_LOGIC;
+      s_axis_config_tready : OUT STD_LOGIC;
+      s_axis_config_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axis_config_tlast : IN STD_LOGIC;
+      m_axis_data_tvalid : OUT STD_LOGIC;
+      m_axis_data_tready : IN STD_LOGIC;
+      m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+      m_axis_data_tlast : OUT STD_LOGIC;
+      m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_phase_tvalid : OUT STD_LOGIC;
+      m_axis_phase_tready : IN STD_LOGIC;
+      m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_phase_tlast : OUT STD_LOGIC;
+      m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      event_pinc_invalid : OUT STD_LOGIC;
+      event_poff_invalid : OUT STD_LOGIC;
+      event_phase_in_invalid : OUT STD_LOGIC;
+      event_s_phase_tlast_missing : OUT STD_LOGIC;
+      event_s_phase_tlast_unexpected : OUT STD_LOGIC;
+      event_s_phase_chanid_incorrect : OUT STD_LOGIC;
+      event_s_config_tlast_missing : OUT STD_LOGIC;
+      event_s_config_tlast_unexpected : OUT STD_LOGIC
+    );
+  END COMPONENT dds_compiler_v6_0_18;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_config_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_CONFIG, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
+BEGIN
+  U0 : dds_compiler_v6_0_18
+    GENERIC MAP (
+      C_XDEVICEFAMILY => "kintex7",
+      C_MODE_OF_OPERATION => 0,
+      C_MODULUS => 9,
+      C_ACCUMULATOR_WIDTH => 32,
+      C_CHANNELS => 1,
+      C_HAS_PHASE_OUT => 0,
+      C_HAS_PHASEGEN => 1,
+      C_HAS_SINCOS => 1,
+      C_LATENCY => 3,
+      C_MEM_TYPE => 1,
+      C_NEGATIVE_COSINE => 0,
+      C_NEGATIVE_SINE => 0,
+      C_NOISE_SHAPING => 0,
+      C_OUTPUTS_REQUIRED => 2,
+      C_OUTPUT_FORM => 0,
+      C_OUTPUT_WIDTH => 8,
+      C_PHASE_ANGLE_WIDTH => 8,
+      C_PHASE_INCREMENT => 1,
+      C_PHASE_INCREMENT_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
+      C_RESYNC => 0,
+      C_PHASE_OFFSET => 0,
+      C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
+      C_OPTIMISE_GOAL => 0,
+      C_USE_DSP48 => 0,
+      C_POR_MODE => 0,
+      C_AMPLITUDE => 0,
+      C_HAS_ACLKEN => 0,
+      C_HAS_ARESETN => 0,
+      C_HAS_TLAST => 0,
+      C_HAS_TREADY => 0,
+      C_HAS_S_PHASE => 0,
+      C_S_PHASE_TDATA_WIDTH => 1,
+      C_S_PHASE_HAS_TUSER => 0,
+      C_S_PHASE_TUSER_WIDTH => 1,
+      C_HAS_S_CONFIG => 1,
+      C_S_CONFIG_SYNC_MODE => 0,
+      C_S_CONFIG_TDATA_WIDTH => 32,
+      C_HAS_M_DATA => 1,
+      C_M_DATA_TDATA_WIDTH => 16,
+      C_M_DATA_HAS_TUSER => 0,
+      C_M_DATA_TUSER_WIDTH => 1,
+      C_HAS_M_PHASE => 0,
+      C_M_PHASE_TDATA_WIDTH => 1,
+      C_M_PHASE_HAS_TUSER => 0,
+      C_M_PHASE_TUSER_WIDTH => 1,
+      C_DEBUG_INTERFACE => 0,
+      C_CHAN_WIDTH => 1
+    )
+    PORT MAP (
+      aclk => aclk,
+      aclken => '1',
+      aresetn => '1',
+      s_axis_phase_tvalid => '0',
+      s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_phase_tlast => '0',
+      s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_config_tvalid => s_axis_config_tvalid,
+      s_axis_config_tdata => s_axis_config_tdata,
+      s_axis_config_tlast => '0',
+      m_axis_data_tvalid => m_axis_data_tvalid,
+      m_axis_data_tready => '0',
+      m_axis_data_tdata => m_axis_data_tdata,
+      m_axis_phase_tready => '0'
+    );
+END dds_32b_8b_arch;

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom/hop_rom.veo

@@ -0,0 +1,67 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 3
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+hop_rom your_instance_name (
+  .clka(clka),    // input wire clka
+  .addra(addra),  // input wire [7 : 0] addra
+  .douta(douta)  // output wire [31 : 0] douta
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file hop_rom.v when simulating
+// the core, hop_rom. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom/hop_rom.vho

@@ -0,0 +1,79 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+-- IP Revision: 3
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT hop_rom
+  PORT (
+    clka : IN STD_LOGIC;
+    addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : hop_rom
+  PORT MAP (
+    clka => clka,
+    addra => addra,
+    douta => douta
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file hop_rom.vhd when simulating
+-- the core, hop_rom. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom/hop_rom_sim_netlist.v

@@ -0,0 +1,749 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:15:57 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.v
+// Design      : hop_rom
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "hop_rom,blk_mem_gen_v8_4_3,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) 
+(* NotValidForBitStream *)
+module hop_rom
+   (clka,
+    addra,
+    douta);
+  (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka;
+  (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [7:0]addra;
+  (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta;
+
+  wire [7:0]addra;
+  wire clka;
+  wire [31:0]douta;
+  wire NLW_U0_dbiterr_UNCONNECTED;
+  wire NLW_U0_rsta_busy_UNCONNECTED;
+  wire NLW_U0_rstb_busy_UNCONNECTED;
+  wire NLW_U0_s_axi_arready_UNCONNECTED;
+  wire NLW_U0_s_axi_awready_UNCONNECTED;
+  wire NLW_U0_s_axi_bvalid_UNCONNECTED;
+  wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
+  wire NLW_U0_s_axi_rlast_UNCONNECTED;
+  wire NLW_U0_s_axi_rvalid_UNCONNECTED;
+  wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
+  wire NLW_U0_s_axi_wready_UNCONNECTED;
+  wire NLW_U0_sbiterr_UNCONNECTED;
+  wire [31:0]NLW_U0_doutb_UNCONNECTED;
+  wire [7:0]NLW_U0_rdaddrecc_UNCONNECTED;
+  wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
+  wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
+  wire [7:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
+  wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED;
+  wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
+  wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
+
+  (* C_ADDRA_WIDTH = "8" *) 
+  (* C_ADDRB_WIDTH = "8" *) 
+  (* C_ALGORITHM = "1" *) 
+  (* C_AXI_ID_WIDTH = "4" *) 
+  (* C_AXI_SLAVE_TYPE = "0" *) 
+  (* C_AXI_TYPE = "1" *) 
+  (* C_BYTE_SIZE = "9" *) 
+  (* C_COMMON_CLK = "0" *) 
+  (* C_COUNT_18K_BRAM = "1" *) 
+  (* C_COUNT_36K_BRAM = "0" *) 
+  (* C_CTRL_ECC_ALGO = "NONE" *) 
+  (* C_DEFAULT_DATA = "0" *) 
+  (* C_DISABLE_WARN_BHV_COLL = "0" *) 
+  (* C_DISABLE_WARN_BHV_RANGE = "0" *) 
+  (* C_ELABORATION_DIR = "./" *) 
+  (* C_ENABLE_32BIT_ADDRESS = "0" *) 
+  (* C_EN_DEEPSLEEP_PIN = "0" *) 
+  (* C_EN_ECC_PIPE = "0" *) 
+  (* C_EN_RDADDRA_CHG = "0" *) 
+  (* C_EN_RDADDRB_CHG = "0" *) 
+  (* C_EN_SAFETY_CKT = "0" *) 
+  (* C_EN_SHUTDOWN_PIN = "0" *) 
+  (* C_EN_SLEEP_PIN = "0" *) 
+  (* C_EST_POWER_SUMMARY = "Estimated Power for IP     :     3.375199 mW" *) 
+  (* C_FAMILY = "kintex7" *) 
+  (* C_HAS_AXI_ID = "0" *) 
+  (* C_HAS_ENA = "0" *) 
+  (* C_HAS_ENB = "0" *) 
+  (* C_HAS_INJECTERR = "0" *) 
+  (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) 
+  (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) 
+  (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) 
+  (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) 
+  (* C_HAS_REGCEA = "0" *) 
+  (* C_HAS_REGCEB = "0" *) 
+  (* C_HAS_RSTA = "0" *) 
+  (* C_HAS_RSTB = "0" *) 
+  (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) 
+  (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) 
+  (* C_INITA_VAL = "0" *) 
+  (* C_INITB_VAL = "0" *) 
+  (* C_INIT_FILE = "hop_rom.mem" *) 
+  (* C_INIT_FILE_NAME = "hop_rom.mif" *) 
+  (* C_INTERFACE_TYPE = "0" *) 
+  (* C_LOAD_INIT_FILE = "1" *) 
+  (* C_MEM_TYPE = "3" *) 
+  (* C_MUX_PIPELINE_STAGES = "0" *) 
+  (* C_PRIM_TYPE = "1" *) 
+  (* C_READ_DEPTH_A = "256" *) 
+  (* C_READ_DEPTH_B = "256" *) 
+  (* C_READ_LATENCY_A = "1" *) 
+  (* C_READ_LATENCY_B = "1" *) 
+  (* C_READ_WIDTH_A = "32" *) 
+  (* C_READ_WIDTH_B = "32" *) 
+  (* C_RSTRAM_A = "0" *) 
+  (* C_RSTRAM_B = "0" *) 
+  (* C_RST_PRIORITY_A = "CE" *) 
+  (* C_RST_PRIORITY_B = "CE" *) 
+  (* C_SIM_COLLISION_CHECK = "ALL" *) 
+  (* C_USE_BRAM_BLOCK = "0" *) 
+  (* C_USE_BYTE_WEA = "0" *) 
+  (* C_USE_BYTE_WEB = "0" *) 
+  (* C_USE_DEFAULT_DATA = "0" *) 
+  (* C_USE_ECC = "0" *) 
+  (* C_USE_SOFTECC = "0" *) 
+  (* C_USE_URAM = "0" *) 
+  (* C_WEA_WIDTH = "1" *) 
+  (* C_WEB_WIDTH = "1" *) 
+  (* C_WRITE_DEPTH_A = "256" *) 
+  (* C_WRITE_DEPTH_B = "256" *) 
+  (* C_WRITE_MODE_A = "WRITE_FIRST" *) 
+  (* C_WRITE_MODE_B = "WRITE_FIRST" *) 
+  (* C_WRITE_WIDTH_A = "32" *) 
+  (* C_WRITE_WIDTH_B = "32" *) 
+  (* C_XDEVICEFAMILY = "kintex7" *) 
+  (* downgradeipidentifiedwarnings = "yes" *) 
+  hop_rom_blk_mem_gen_v8_4_3 U0
+       (.addra(addra),
+        .addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .clka(clka),
+        .clkb(1'b0),
+        .dbiterr(NLW_U0_dbiterr_UNCONNECTED),
+        .deepsleep(1'b0),
+        .dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .douta(douta),
+        .doutb(NLW_U0_doutb_UNCONNECTED[31:0]),
+        .eccpipece(1'b0),
+        .ena(1'b0),
+        .enb(1'b0),
+        .injectdbiterr(1'b0),
+        .injectsbiterr(1'b0),
+        .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[7:0]),
+        .regcea(1'b0),
+        .regceb(1'b0),
+        .rsta(1'b0),
+        .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
+        .rstb(1'b0),
+        .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
+        .s_aclk(1'b0),
+        .s_aresetn(1'b0),
+        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_arburst({1'b0,1'b0}),
+        .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
+        .s_axi_arsize({1'b0,1'b0,1'b0}),
+        .s_axi_arvalid(1'b0),
+        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_awburst({1'b0,1'b0}),
+        .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
+        .s_axi_awsize({1'b0,1'b0,1'b0}),
+        .s_axi_awvalid(1'b0),
+        .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
+        .s_axi_bready(1'b0),
+        .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
+        .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
+        .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
+        .s_axi_injectdbiterr(1'b0),
+        .s_axi_injectsbiterr(1'b0),
+        .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[7:0]),
+        .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]),
+        .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
+        .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
+        .s_axi_rready(1'b0),
+        .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
+        .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
+        .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
+        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_wlast(1'b0),
+        .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
+        .s_axi_wstrb(1'b0),
+        .s_axi_wvalid(1'b0),
+        .sbiterr(NLW_U0_sbiterr_UNCONNECTED),
+        .shutdown(1'b0),
+        .sleep(1'b0),
+        .wea(1'b0),
+        .web(1'b0));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) 
+module hop_rom_blk_mem_gen_generic_cstr
+   (douta,
+    clka,
+    addra);
+  output [31:0]douta;
+  input clka;
+  input [7:0]addra;
+
+  wire [7:0]addra;
+  wire clka;
+  wire [31:0]douta;
+
+  hop_rom_blk_mem_gen_prim_width \ramloop[0].ram.r 
+       (.addra(addra),
+        .clka(clka),
+        .douta(douta));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) 
+module hop_rom_blk_mem_gen_prim_width
+   (douta,
+    clka,
+    addra);
+  output [31:0]douta;
+  input clka;
+  input [7:0]addra;
+
+  wire [7:0]addra;
+  wire clka;
+  wire [31:0]douta;
+
+  hop_rom_blk_mem_gen_prim_wrapper_init \prim_init.ram 
+       (.addra(addra),
+        .clka(clka),
+        .douta(douta));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) 
+module hop_rom_blk_mem_gen_prim_wrapper_init
+   (douta,
+    clka,
+    addra);
+  output [31:0]douta;
+  input clka;
+  input [7:0]addra;
+
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 ;
+  wire [7:0]addra;
+  wire clka;
+  wire [31:0]douta;
+
+  (* box_type = "PRIMITIVE" *) 
+  RAMB18E1 #(
+    .DOA_REG(0),
+    .DOB_REG(0),
+    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_00(256'h8707070886060607850505068404040583030304820202038101010280000001),
+    .INIT_01(256'h8F0F0F108E0E0E0F8D0D0D0E8C0C0C0D8B0B0B0C8A0A0A0B8909090A88080809),
+    .INIT_02(256'h9717171896161617951515169414141593131314921212139111111290101011),
+    .INIT_03(256'h9F1F1F209E1E1E1F9D1D1D1E9C1C1C1D9B1B1B1C9A1A1A1B9919191A98181819),
+    .INIT_04(256'hA7272728A6262627A5252526A4242425A3232324A2222223A1212122A0202021),
+    .INIT_05(256'hAF2F2F30AE2E2E2FAD2D2D2EAC2C2C2DAB2B2B2CAA2A2A2BA929292AA8282829),
+    .INIT_06(256'hB7373738B6363637B5353536B4343435B3333334B2323233B1313132B0303031),
+    .INIT_07(256'hBF3F3F40BE3E3E3FBD3D3D3EBC3C3C3DBB3B3B3CBA3A3A3BB939393AB8383839),
+    .INIT_08(256'hC7474748C6464647C5454546C4444445C3434344C2424243C1414142C0404041),
+    .INIT_09(256'hCF4F4F50CE4E4E4FCD4D4D4ECC4C4C4DCB4B4B4CCA4A4A4BC949494AC8484849),
+    .INIT_0A(256'hD7575758D6565657D5555556D4545455D3535354D2525253D1515152D0505051),
+    .INIT_0B(256'hDF5F5F60DE5E5E5FDD5D5D5EDC5C5C5DDB5B5B5CDA5A5A5BD959595AD8585859),
+    .INIT_0C(256'hE7676768E6666667E5656566E4646465E3636364E2626263E1616162E0606061),
+    .INIT_0D(256'hEF6F6F70EE6E6E6FED6D6D6EEC6C6C6DEB6B6B6CEA6A6A6BE969696AE8686869),
+    .INIT_0E(256'hF7777778F6767677F5757576F4747475F3737374F2727273F1717172F0707071),
+    .INIT_0F(256'hFF7F7F80FE7E7E7FFD7D7D7EFC7C7C7DFB7B7B7CFA7A7A7BF979797AF8787879),
+    .INIT_10(256'h0787878706868686058585850484848403838383028282820181818100808080),
+    .INIT_11(256'h0F8F8F8F0E8E8E8E0D8D8D8D0C8C8C8C0B8B8B8B0A8A8A8A0989898908888888),
+    .INIT_12(256'h1797979716969696159595951494949413939393129292921191919110909090),
+    .INIT_13(256'h1F9F9F9F1E9E9E9E1D9D9D9D1C9C9C9C1B9B9B9B1A9A9A9A1999999918989898),
+    .INIT_14(256'h27A7A7A726A6A6A625A5A5A524A4A4A423A3A3A322A2A2A221A1A1A120A0A0A0),
+    .INIT_15(256'h2FAFAFAF2EAEAEAE2DADADAD2CACACAC2BABABAB2AAAAAAA29A9A9A928A8A8A8),
+    .INIT_16(256'h37B7B7B736B6B6B635B5B5B534B4B4B433B3B3B332B2B2B231B1B1B130B0B0B0),
+    .INIT_17(256'h3FBFBFBF3EBEBEBE3DBDBDBD3CBCBCBC3BBBBBBB3ABABABA39B9B9B938B8B8B8),
+    .INIT_18(256'h47C7C7C746C6C6C645C5C5C544C4C4C443C3C3C342C2C2C241C1C1C140C0C0C0),
+    .INIT_19(256'h4FCFCFCF4ECECECE4DCDCDCD4CCCCCCC4BCBCBCB4ACACACA49C9C9C948C8C8C8),
+    .INIT_1A(256'h57D7D7D756D6D6D655D5D5D554D4D4D453D3D3D352D2D2D251D1D1D150D0D0D0),
+    .INIT_1B(256'h5FDFDFDF5EDEDEDE5DDDDDDD5CDCDCDC5BDBDBDB5ADADADA59D9D9D958D8D8D8),
+    .INIT_1C(256'h67E7E7E766E6E6E665E5E5E564E4E4E463E3E3E362E2E2E261E1E1E160E0E0E0),
+    .INIT_1D(256'h6FEFEFEF6EEEEEEE6DEDEDED6CECECEC6BEBEBEB6AEAEAEA69E9E9E968E8E8E8),
+    .INIT_1E(256'h77F7F7F776F6F6F675F5F5F574F4F4F473F3F3F372F2F2F271F1F1F170F0F0F0),
+    .INIT_1F(256'h7FFFFFFF7EFEFEFE7DFDFDFD7CFCFCFC7BFBFBFB7AFAFAFA79F9F9F978F8F8F8),
+    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_A(18'h00000),
+    .INIT_B(18'h00000),
+    .INIT_FILE("NONE"),
+    .IS_CLKARDCLK_INVERTED(1'b0),
+    .IS_CLKBWRCLK_INVERTED(1'b0),
+    .IS_ENARDEN_INVERTED(1'b0),
+    .IS_ENBWREN_INVERTED(1'b0),
+    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+    .IS_RSTRAMB_INVERTED(1'b0),
+    .IS_RSTREGARSTREG_INVERTED(1'b0),
+    .IS_RSTREGB_INVERTED(1'b0),
+    .RAM_MODE("TDP"),
+    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
+    .READ_WIDTH_A(18),
+    .READ_WIDTH_B(18),
+    .RSTREG_PRIORITY_A("REGCE"),
+    .RSTREG_PRIORITY_B("REGCE"),
+    .SIM_COLLISION_CHECK("ALL"),
+    .SIM_DEVICE("7SERIES"),
+    .SRVAL_A(18'h00000),
+    .SRVAL_B(18'h00000),
+    .WRITE_MODE_A("WRITE_FIRST"),
+    .WRITE_MODE_B("WRITE_FIRST"),
+    .WRITE_WIDTH_A(18),
+    .WRITE_WIDTH_B(18)) 
+    \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram 
+       (.ADDRARDADDR({1'b0,addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .ADDRBWRADDR({1'b0,addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
+        .CLKARDCLK(clka),
+        .CLKBWRCLK(clka),
+        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DIPADIP({1'b0,1'b0}),
+        .DIPBDIP({1'b0,1'b0}),
+        .DOADO(douta[15:0]),
+        .DOBDO(douta[31:16]),
+        .DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 }),
+        .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 }),
+        .ENARDEN(1'b1),
+        .ENBWREN(1'b1),
+        .REGCEAREGCE(1'b0),
+        .REGCEB(1'b0),
+        .RSTRAMARSTRAM(1'b0),
+        .RSTRAMB(1'b0),
+        .RSTREGARSTREG(1'b0),
+        .RSTREGB(1'b0),
+        .WEA({1'b0,1'b0}),
+        .WEBWE({1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_top" *) 
+module hop_rom_blk_mem_gen_top
+   (douta,
+    clka,
+    addra);
+  output [31:0]douta;
+  input clka;
+  input [7:0]addra;
+
+  wire [7:0]addra;
+  wire clka;
+  wire [31:0]douta;
+
+  hop_rom_blk_mem_gen_generic_cstr \valid.cstr 
+       (.addra(addra),
+        .clka(clka),
+        .douta(douta));
+endmodule
+
+(* C_ADDRA_WIDTH = "8" *) (* C_ADDRB_WIDTH = "8" *) (* C_ALGORITHM = "1" *) 
+(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) 
+(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *) 
+(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) 
+(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) 
+(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) 
+(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) 
+(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP     :     3.375199 mW" *) 
+(* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *) 
+(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) 
+(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) 
+(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) 
+(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) 
+(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "hop_rom.mem" *) 
+(* C_INIT_FILE_NAME = "hop_rom.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *) 
+(* C_MEM_TYPE = "3" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) 
+(* C_READ_DEPTH_A = "256" *) (* C_READ_DEPTH_B = "256" *) (* C_READ_LATENCY_A = "1" *) 
+(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "32" *) (* C_READ_WIDTH_B = "32" *) 
+(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) 
+(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) 
+(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) 
+(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) 
+(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "256" *) 
+(* C_WRITE_DEPTH_B = "256" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) 
+(* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *) (* C_XDEVICEFAMILY = "kintex7" *) 
+(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3" *) (* downgradeipidentifiedwarnings = "yes" *) 
+module hop_rom_blk_mem_gen_v8_4_3
+   (clka,
+    rsta,
+    ena,
+    regcea,
+    wea,
+    addra,
+    dina,
+    douta,
+    clkb,
+    rstb,
+    enb,
+    regceb,
+    web,
+    addrb,
+    dinb,
+    doutb,
+    injectsbiterr,
+    injectdbiterr,
+    eccpipece,
+    sbiterr,
+    dbiterr,
+    rdaddrecc,
+    sleep,
+    deepsleep,
+    shutdown,
+    rsta_busy,
+    rstb_busy,
+    s_aclk,
+    s_aresetn,
+    s_axi_awid,
+    s_axi_awaddr,
+    s_axi_awlen,
+    s_axi_awsize,
+    s_axi_awburst,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wlast,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bid,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_arid,
+    s_axi_araddr,
+    s_axi_arlen,
+    s_axi_arsize,
+    s_axi_arburst,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rid,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rlast,
+    s_axi_rvalid,
+    s_axi_rready,
+    s_axi_injectsbiterr,
+    s_axi_injectdbiterr,
+    s_axi_sbiterr,
+    s_axi_dbiterr,
+    s_axi_rdaddrecc);
+  input clka;
+  input rsta;
+  input ena;
+  input regcea;
+  input [0:0]wea;
+  input [7:0]addra;
+  input [31:0]dina;
+  output [31:0]douta;
+  input clkb;
+  input rstb;
+  input enb;
+  input regceb;
+  input [0:0]web;
+  input [7:0]addrb;
+  input [31:0]dinb;
+  output [31:0]doutb;
+  input injectsbiterr;
+  input injectdbiterr;
+  input eccpipece;
+  output sbiterr;
+  output dbiterr;
+  output [7:0]rdaddrecc;
+  input sleep;
+  input deepsleep;
+  input shutdown;
+  output rsta_busy;
+  output rstb_busy;
+  input s_aclk;
+  input s_aresetn;
+  input [3:0]s_axi_awid;
+  input [31:0]s_axi_awaddr;
+  input [7:0]s_axi_awlen;
+  input [2:0]s_axi_awsize;
+  input [1:0]s_axi_awburst;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [0:0]s_axi_wstrb;
+  input s_axi_wlast;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [3:0]s_axi_bid;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [3:0]s_axi_arid;
+  input [31:0]s_axi_araddr;
+  input [7:0]s_axi_arlen;
+  input [2:0]s_axi_arsize;
+  input [1:0]s_axi_arburst;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [3:0]s_axi_rid;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rlast;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input s_axi_injectsbiterr;
+  input s_axi_injectdbiterr;
+  output s_axi_sbiterr;
+  output s_axi_dbiterr;
+  output [7:0]s_axi_rdaddrecc;
+
+  wire \<const0> ;
+  wire [7:0]addra;
+  wire clka;
+  wire [31:0]douta;
+
+  assign dbiterr = \<const0> ;
+  assign doutb[31] = \<const0> ;
+  assign doutb[30] = \<const0> ;
+  assign doutb[29] = \<const0> ;
+  assign doutb[28] = \<const0> ;
+  assign doutb[27] = \<const0> ;
+  assign doutb[26] = \<const0> ;
+  assign doutb[25] = \<const0> ;
+  assign doutb[24] = \<const0> ;
+  assign doutb[23] = \<const0> ;
+  assign doutb[22] = \<const0> ;
+  assign doutb[21] = \<const0> ;
+  assign doutb[20] = \<const0> ;
+  assign doutb[19] = \<const0> ;
+  assign doutb[18] = \<const0> ;
+  assign doutb[17] = \<const0> ;
+  assign doutb[16] = \<const0> ;
+  assign doutb[15] = \<const0> ;
+  assign doutb[14] = \<const0> ;
+  assign doutb[13] = \<const0> ;
+  assign doutb[12] = \<const0> ;
+  assign doutb[11] = \<const0> ;
+  assign doutb[10] = \<const0> ;
+  assign doutb[9] = \<const0> ;
+  assign doutb[8] = \<const0> ;
+  assign doutb[7] = \<const0> ;
+  assign doutb[6] = \<const0> ;
+  assign doutb[5] = \<const0> ;
+  assign doutb[4] = \<const0> ;
+  assign doutb[3] = \<const0> ;
+  assign doutb[2] = \<const0> ;
+  assign doutb[1] = \<const0> ;
+  assign doutb[0] = \<const0> ;
+  assign rdaddrecc[7] = \<const0> ;
+  assign rdaddrecc[6] = \<const0> ;
+  assign rdaddrecc[5] = \<const0> ;
+  assign rdaddrecc[4] = \<const0> ;
+  assign rdaddrecc[3] = \<const0> ;
+  assign rdaddrecc[2] = \<const0> ;
+  assign rdaddrecc[1] = \<const0> ;
+  assign rdaddrecc[0] = \<const0> ;
+  assign rsta_busy = \<const0> ;
+  assign rstb_busy = \<const0> ;
+  assign s_axi_arready = \<const0> ;
+  assign s_axi_awready = \<const0> ;
+  assign s_axi_bid[3] = \<const0> ;
+  assign s_axi_bid[2] = \<const0> ;
+  assign s_axi_bid[1] = \<const0> ;
+  assign s_axi_bid[0] = \<const0> ;
+  assign s_axi_bresp[1] = \<const0> ;
+  assign s_axi_bresp[0] = \<const0> ;
+  assign s_axi_bvalid = \<const0> ;
+  assign s_axi_dbiterr = \<const0> ;
+  assign s_axi_rdaddrecc[7] = \<const0> ;
+  assign s_axi_rdaddrecc[6] = \<const0> ;
+  assign s_axi_rdaddrecc[5] = \<const0> ;
+  assign s_axi_rdaddrecc[4] = \<const0> ;
+  assign s_axi_rdaddrecc[3] = \<const0> ;
+  assign s_axi_rdaddrecc[2] = \<const0> ;
+  assign s_axi_rdaddrecc[1] = \<const0> ;
+  assign s_axi_rdaddrecc[0] = \<const0> ;
+  assign s_axi_rdata[31] = \<const0> ;
+  assign s_axi_rdata[30] = \<const0> ;
+  assign s_axi_rdata[29] = \<const0> ;
+  assign s_axi_rdata[28] = \<const0> ;
+  assign s_axi_rdata[27] = \<const0> ;
+  assign s_axi_rdata[26] = \<const0> ;
+  assign s_axi_rdata[25] = \<const0> ;
+  assign s_axi_rdata[24] = \<const0> ;
+  assign s_axi_rdata[23] = \<const0> ;
+  assign s_axi_rdata[22] = \<const0> ;
+  assign s_axi_rdata[21] = \<const0> ;
+  assign s_axi_rdata[20] = \<const0> ;
+  assign s_axi_rdata[19] = \<const0> ;
+  assign s_axi_rdata[18] = \<const0> ;
+  assign s_axi_rdata[17] = \<const0> ;
+  assign s_axi_rdata[16] = \<const0> ;
+  assign s_axi_rdata[15] = \<const0> ;
+  assign s_axi_rdata[14] = \<const0> ;
+  assign s_axi_rdata[13] = \<const0> ;
+  assign s_axi_rdata[12] = \<const0> ;
+  assign s_axi_rdata[11] = \<const0> ;
+  assign s_axi_rdata[10] = \<const0> ;
+  assign s_axi_rdata[9] = \<const0> ;
+  assign s_axi_rdata[8] = \<const0> ;
+  assign s_axi_rdata[7] = \<const0> ;
+  assign s_axi_rdata[6] = \<const0> ;
+  assign s_axi_rdata[5] = \<const0> ;
+  assign s_axi_rdata[4] = \<const0> ;
+  assign s_axi_rdata[3] = \<const0> ;
+  assign s_axi_rdata[2] = \<const0> ;
+  assign s_axi_rdata[1] = \<const0> ;
+  assign s_axi_rdata[0] = \<const0> ;
+  assign s_axi_rid[3] = \<const0> ;
+  assign s_axi_rid[2] = \<const0> ;
+  assign s_axi_rid[1] = \<const0> ;
+  assign s_axi_rid[0] = \<const0> ;
+  assign s_axi_rlast = \<const0> ;
+  assign s_axi_rresp[1] = \<const0> ;
+  assign s_axi_rresp[0] = \<const0> ;
+  assign s_axi_rvalid = \<const0> ;
+  assign s_axi_sbiterr = \<const0> ;
+  assign s_axi_wready = \<const0> ;
+  assign sbiterr = \<const0> ;
+  GND GND
+       (.G(\<const0> ));
+  hop_rom_blk_mem_gen_v8_4_3_synth inst_blk_mem_gen
+       (.addra(addra),
+        .clka(clka),
+        .douta(douta));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3_synth" *) 
+module hop_rom_blk_mem_gen_v8_4_3_synth
+   (douta,
+    clka,
+    addra);
+  output [31:0]douta;
+  input clka;
+  input [7:0]addra;
+
+  wire [7:0]addra;
+  wire clka;
+  wire [31:0]douta;
+
+  hop_rom_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen 
+       (.addra(addra),
+        .clka(clka),
+        .douta(douta));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom/hop_rom_sim_netlist.vhdl

@@ -0,0 +1,869 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:15:57 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode funcsim
+--               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.vhdl
+-- Design      : hop_rom
+-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+--               synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity hop_rom_blk_mem_gen_prim_wrapper_init is
+  port (
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    clka : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
+end hop_rom_blk_mem_gen_prim_wrapper_init;
+
+architecture STRUCTURE of hop_rom_blk_mem_gen_prim_wrapper_init is
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
+  attribute box_type : string;
+  attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
+begin
+\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
+    generic map(
+      DOA_REG => 0,
+      DOB_REG => 0,
+      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_00 => X"8707070886060607850505068404040583030304820202038101010280000001",
+      INIT_01 => X"8F0F0F108E0E0E0F8D0D0D0E8C0C0C0D8B0B0B0C8A0A0A0B8909090A88080809",
+      INIT_02 => X"9717171896161617951515169414141593131314921212139111111290101011",
+      INIT_03 => X"9F1F1F209E1E1E1F9D1D1D1E9C1C1C1D9B1B1B1C9A1A1A1B9919191A98181819",
+      INIT_04 => X"A7272728A6262627A5252526A4242425A3232324A2222223A1212122A0202021",
+      INIT_05 => X"AF2F2F30AE2E2E2FAD2D2D2EAC2C2C2DAB2B2B2CAA2A2A2BA929292AA8282829",
+      INIT_06 => X"B7373738B6363637B5353536B4343435B3333334B2323233B1313132B0303031",
+      INIT_07 => X"BF3F3F40BE3E3E3FBD3D3D3EBC3C3C3DBB3B3B3CBA3A3A3BB939393AB8383839",
+      INIT_08 => X"C7474748C6464647C5454546C4444445C3434344C2424243C1414142C0404041",
+      INIT_09 => X"CF4F4F50CE4E4E4FCD4D4D4ECC4C4C4DCB4B4B4CCA4A4A4BC949494AC8484849",
+      INIT_0A => X"D7575758D6565657D5555556D4545455D3535354D2525253D1515152D0505051",
+      INIT_0B => X"DF5F5F60DE5E5E5FDD5D5D5EDC5C5C5DDB5B5B5CDA5A5A5BD959595AD8585859",
+      INIT_0C => X"E7676768E6666667E5656566E4646465E3636364E2626263E1616162E0606061",
+      INIT_0D => X"EF6F6F70EE6E6E6FED6D6D6EEC6C6C6DEB6B6B6CEA6A6A6BE969696AE8686869",
+      INIT_0E => X"F7777778F6767677F5757576F4747475F3737374F2727273F1717172F0707071",
+      INIT_0F => X"FF7F7F80FE7E7E7FFD7D7D7EFC7C7C7DFB7B7B7CFA7A7A7BF979797AF8787879",
+      INIT_10 => X"0787878706868686058585850484848403838383028282820181818100808080",
+      INIT_11 => X"0F8F8F8F0E8E8E8E0D8D8D8D0C8C8C8C0B8B8B8B0A8A8A8A0989898908888888",
+      INIT_12 => X"1797979716969696159595951494949413939393129292921191919110909090",
+      INIT_13 => X"1F9F9F9F1E9E9E9E1D9D9D9D1C9C9C9C1B9B9B9B1A9A9A9A1999999918989898",
+      INIT_14 => X"27A7A7A726A6A6A625A5A5A524A4A4A423A3A3A322A2A2A221A1A1A120A0A0A0",
+      INIT_15 => X"2FAFAFAF2EAEAEAE2DADADAD2CACACAC2BABABAB2AAAAAAA29A9A9A928A8A8A8",
+      INIT_16 => X"37B7B7B736B6B6B635B5B5B534B4B4B433B3B3B332B2B2B231B1B1B130B0B0B0",
+      INIT_17 => X"3FBFBFBF3EBEBEBE3DBDBDBD3CBCBCBC3BBBBBBB3ABABABA39B9B9B938B8B8B8",
+      INIT_18 => X"47C7C7C746C6C6C645C5C5C544C4C4C443C3C3C342C2C2C241C1C1C140C0C0C0",
+      INIT_19 => X"4FCFCFCF4ECECECE4DCDCDCD4CCCCCCC4BCBCBCB4ACACACA49C9C9C948C8C8C8",
+      INIT_1A => X"57D7D7D756D6D6D655D5D5D554D4D4D453D3D3D352D2D2D251D1D1D150D0D0D0",
+      INIT_1B => X"5FDFDFDF5EDEDEDE5DDDDDDD5CDCDCDC5BDBDBDB5ADADADA59D9D9D958D8D8D8",
+      INIT_1C => X"67E7E7E766E6E6E665E5E5E564E4E4E463E3E3E362E2E2E261E1E1E160E0E0E0",
+      INIT_1D => X"6FEFEFEF6EEEEEEE6DEDEDED6CECECEC6BEBEBEB6AEAEAEA69E9E9E968E8E8E8",
+      INIT_1E => X"77F7F7F776F6F6F675F5F5F574F4F4F473F3F3F372F2F2F271F1F1F170F0F0F0",
+      INIT_1F => X"7FFFFFFF7EFEFEFE7DFDFDFD7CFCFCFC7BFBFBFB7AFAFAFA79F9F9F978F8F8F8",
+      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_A => X"00000",
+      INIT_B => X"00000",
+      INIT_FILE => "NONE",
+      IS_CLKARDCLK_INVERTED => '0',
+      IS_CLKBWRCLK_INVERTED => '0',
+      IS_ENARDEN_INVERTED => '0',
+      IS_ENBWREN_INVERTED => '0',
+      IS_RSTRAMARSTRAM_INVERTED => '0',
+      IS_RSTRAMB_INVERTED => '0',
+      IS_RSTREGARSTREG_INVERTED => '0',
+      IS_RSTREGB_INVERTED => '0',
+      RAM_MODE => "TDP",
+      RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
+      READ_WIDTH_A => 18,
+      READ_WIDTH_B => 18,
+      RSTREG_PRIORITY_A => "REGCE",
+      RSTREG_PRIORITY_B => "REGCE",
+      SIM_COLLISION_CHECK => "ALL",
+      SIM_DEVICE => "7SERIES",
+      SRVAL_A => X"00000",
+      SRVAL_B => X"00000",
+      WRITE_MODE_A => "WRITE_FIRST",
+      WRITE_MODE_B => "WRITE_FIRST",
+      WRITE_WIDTH_A => 18,
+      WRITE_WIDTH_B => 18
+    )
+        port map (
+      ADDRARDADDR(13) => '0',
+      ADDRARDADDR(12 downto 5) => addra(7 downto 0),
+      ADDRARDADDR(4 downto 0) => B"00000",
+      ADDRBWRADDR(13) => '0',
+      ADDRBWRADDR(12 downto 5) => addra(7 downto 0),
+      ADDRBWRADDR(4 downto 0) => B"10000",
+      CLKARDCLK => clka,
+      CLKBWRCLK => clka,
+      DIADI(15 downto 0) => B"0000000000000000",
+      DIBDI(15 downto 0) => B"0000000000000000",
+      DIPADIP(1 downto 0) => B"00",
+      DIPBDIP(1 downto 0) => B"00",
+      DOADO(15 downto 0) => douta(15 downto 0),
+      DOBDO(15 downto 0) => douta(31 downto 16),
+      DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\,
+      DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\,
+      DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\,
+      DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\,
+      ENARDEN => '1',
+      ENBWREN => '1',
+      REGCEAREGCE => '0',
+      REGCEB => '0',
+      RSTRAMARSTRAM => '0',
+      RSTRAMB => '0',
+      RSTREGARSTREG => '0',
+      RSTREGB => '0',
+      WEA(1 downto 0) => B"00",
+      WEBWE(3 downto 0) => B"0000"
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity hop_rom_blk_mem_gen_prim_width is
+  port (
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    clka : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
+end hop_rom_blk_mem_gen_prim_width;
+
+architecture STRUCTURE of hop_rom_blk_mem_gen_prim_width is
+begin
+\prim_init.ram\: entity work.hop_rom_blk_mem_gen_prim_wrapper_init
+     port map (
+      addra(7 downto 0) => addra(7 downto 0),
+      clka => clka,
+      douta(31 downto 0) => douta(31 downto 0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity hop_rom_blk_mem_gen_generic_cstr is
+  port (
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    clka : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
+end hop_rom_blk_mem_gen_generic_cstr;
+
+architecture STRUCTURE of hop_rom_blk_mem_gen_generic_cstr is
+begin
+\ramloop[0].ram.r\: entity work.hop_rom_blk_mem_gen_prim_width
+     port map (
+      addra(7 downto 0) => addra(7 downto 0),
+      clka => clka,
+      douta(31 downto 0) => douta(31 downto 0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity hop_rom_blk_mem_gen_top is
+  port (
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    clka : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_top : entity is "blk_mem_gen_top";
+end hop_rom_blk_mem_gen_top;
+
+architecture STRUCTURE of hop_rom_blk_mem_gen_top is
+begin
+\valid.cstr\: entity work.hop_rom_blk_mem_gen_generic_cstr
+     port map (
+      addra(7 downto 0) => addra(7 downto 0),
+      clka => clka,
+      douta(31 downto 0) => douta(31 downto 0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity hop_rom_blk_mem_gen_v8_4_3_synth is
+  port (
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    clka : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth";
+end hop_rom_blk_mem_gen_v8_4_3_synth;
+
+architecture STRUCTURE of hop_rom_blk_mem_gen_v8_4_3_synth is
+begin
+\gnbram.gnativebmg.native_blk_mem_gen\: entity work.hop_rom_blk_mem_gen_top
+     port map (
+      addra(7 downto 0) => addra(7 downto 0),
+      clka => clka,
+      douta(31 downto 0) => douta(31 downto 0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity hop_rom_blk_mem_gen_v8_4_3 is
+  port (
+    clka : in STD_LOGIC;
+    rsta : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    regcea : in STD_LOGIC;
+    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
+    addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    clkb : in STD_LOGIC;
+    rstb : in STD_LOGIC;
+    enb : in STD_LOGIC;
+    regceb : in STD_LOGIC;
+    web : in STD_LOGIC_VECTOR ( 0 to 0 );
+    addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    injectsbiterr : in STD_LOGIC;
+    injectdbiterr : in STD_LOGIC;
+    eccpipece : in STD_LOGIC;
+    sbiterr : out STD_LOGIC;
+    dbiterr : out STD_LOGIC;
+    rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    sleep : in STD_LOGIC;
+    deepsleep : in STD_LOGIC;
+    shutdown : in STD_LOGIC;
+    rsta_busy : out STD_LOGIC;
+    rstb_busy : out STD_LOGIC;
+    s_aclk : in STD_LOGIC;
+    s_aresetn : in STD_LOGIC;
+    s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_wlast : in STD_LOGIC;
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rlast : out STD_LOGIC;
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    s_axi_injectsbiterr : in STD_LOGIC;
+    s_axi_injectdbiterr : in STD_LOGIC;
+    s_axi_sbiterr : out STD_LOGIC;
+    s_axi_dbiterr : out STD_LOGIC;
+    s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  attribute C_ADDRA_WIDTH : integer;
+  attribute C_ADDRA_WIDTH of hop_rom_blk_mem_gen_v8_4_3 : entity is 8;
+  attribute C_ADDRB_WIDTH : integer;
+  attribute C_ADDRB_WIDTH of hop_rom_blk_mem_gen_v8_4_3 : entity is 8;
+  attribute C_ALGORITHM : integer;
+  attribute C_ALGORITHM of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
+  attribute C_AXI_ID_WIDTH : integer;
+  attribute C_AXI_ID_WIDTH of hop_rom_blk_mem_gen_v8_4_3 : entity is 4;
+  attribute C_AXI_SLAVE_TYPE : integer;
+  attribute C_AXI_SLAVE_TYPE of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_AXI_TYPE : integer;
+  attribute C_AXI_TYPE of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
+  attribute C_BYTE_SIZE : integer;
+  attribute C_BYTE_SIZE of hop_rom_blk_mem_gen_v8_4_3 : entity is 9;
+  attribute C_COMMON_CLK : integer;
+  attribute C_COMMON_CLK of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_COUNT_18K_BRAM : string;
+  attribute C_COUNT_18K_BRAM of hop_rom_blk_mem_gen_v8_4_3 : entity is "1";
+  attribute C_COUNT_36K_BRAM : string;
+  attribute C_COUNT_36K_BRAM of hop_rom_blk_mem_gen_v8_4_3 : entity is "0";
+  attribute C_CTRL_ECC_ALGO : string;
+  attribute C_CTRL_ECC_ALGO of hop_rom_blk_mem_gen_v8_4_3 : entity is "NONE";
+  attribute C_DEFAULT_DATA : string;
+  attribute C_DEFAULT_DATA of hop_rom_blk_mem_gen_v8_4_3 : entity is "0";
+  attribute C_DISABLE_WARN_BHV_COLL : integer;
+  attribute C_DISABLE_WARN_BHV_COLL of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_DISABLE_WARN_BHV_RANGE : integer;
+  attribute C_DISABLE_WARN_BHV_RANGE of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_ELABORATION_DIR : string;
+  attribute C_ELABORATION_DIR of hop_rom_blk_mem_gen_v8_4_3 : entity is "./";
+  attribute C_ENABLE_32BIT_ADDRESS : integer;
+  attribute C_ENABLE_32BIT_ADDRESS of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_EN_DEEPSLEEP_PIN : integer;
+  attribute C_EN_DEEPSLEEP_PIN of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_EN_ECC_PIPE : integer;
+  attribute C_EN_ECC_PIPE of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_EN_RDADDRA_CHG : integer;
+  attribute C_EN_RDADDRA_CHG of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_EN_RDADDRB_CHG : integer;
+  attribute C_EN_RDADDRB_CHG of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_EN_SAFETY_CKT : integer;
+  attribute C_EN_SAFETY_CKT of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_EN_SHUTDOWN_PIN : integer;
+  attribute C_EN_SHUTDOWN_PIN of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_EN_SLEEP_PIN : integer;
+  attribute C_EN_SLEEP_PIN of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_EST_POWER_SUMMARY : string;
+  attribute C_EST_POWER_SUMMARY of hop_rom_blk_mem_gen_v8_4_3 : entity is "Estimated Power for IP     :     3.375199 mW";
+  attribute C_FAMILY : string;
+  attribute C_FAMILY of hop_rom_blk_mem_gen_v8_4_3 : entity is "kintex7";
+  attribute C_HAS_AXI_ID : integer;
+  attribute C_HAS_AXI_ID of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_ENA : integer;
+  attribute C_HAS_ENA of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_ENB : integer;
+  attribute C_HAS_ENB of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_INJECTERR : integer;
+  attribute C_HAS_INJECTERR of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
+  attribute C_HAS_MEM_OUTPUT_REGS_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
+  attribute C_HAS_MEM_OUTPUT_REGS_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
+  attribute C_HAS_MUX_OUTPUT_REGS_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
+  attribute C_HAS_MUX_OUTPUT_REGS_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_REGCEA : integer;
+  attribute C_HAS_REGCEA of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_REGCEB : integer;
+  attribute C_HAS_REGCEB of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_RSTA : integer;
+  attribute C_HAS_RSTA of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_RSTB : integer;
+  attribute C_HAS_RSTB of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
+  attribute C_HAS_SOFTECC_INPUT_REGS_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
+  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_INITA_VAL : string;
+  attribute C_INITA_VAL of hop_rom_blk_mem_gen_v8_4_3 : entity is "0";
+  attribute C_INITB_VAL : string;
+  attribute C_INITB_VAL of hop_rom_blk_mem_gen_v8_4_3 : entity is "0";
+  attribute C_INIT_FILE : string;
+  attribute C_INIT_FILE of hop_rom_blk_mem_gen_v8_4_3 : entity is "hop_rom.mem";
+  attribute C_INIT_FILE_NAME : string;
+  attribute C_INIT_FILE_NAME of hop_rom_blk_mem_gen_v8_4_3 : entity is "hop_rom.mif";
+  attribute C_INTERFACE_TYPE : integer;
+  attribute C_INTERFACE_TYPE of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_LOAD_INIT_FILE : integer;
+  attribute C_LOAD_INIT_FILE of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
+  attribute C_MEM_TYPE : integer;
+  attribute C_MEM_TYPE of hop_rom_blk_mem_gen_v8_4_3 : entity is 3;
+  attribute C_MUX_PIPELINE_STAGES : integer;
+  attribute C_MUX_PIPELINE_STAGES of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_PRIM_TYPE : integer;
+  attribute C_PRIM_TYPE of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
+  attribute C_READ_DEPTH_A : integer;
+  attribute C_READ_DEPTH_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 256;
+  attribute C_READ_DEPTH_B : integer;
+  attribute C_READ_DEPTH_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 256;
+  attribute C_READ_LATENCY_A : integer;
+  attribute C_READ_LATENCY_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
+  attribute C_READ_LATENCY_B : integer;
+  attribute C_READ_LATENCY_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
+  attribute C_READ_WIDTH_A : integer;
+  attribute C_READ_WIDTH_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 32;
+  attribute C_READ_WIDTH_B : integer;
+  attribute C_READ_WIDTH_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 32;
+  attribute C_RSTRAM_A : integer;
+  attribute C_RSTRAM_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_RSTRAM_B : integer;
+  attribute C_RSTRAM_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_RST_PRIORITY_A : string;
+  attribute C_RST_PRIORITY_A of hop_rom_blk_mem_gen_v8_4_3 : entity is "CE";
+  attribute C_RST_PRIORITY_B : string;
+  attribute C_RST_PRIORITY_B of hop_rom_blk_mem_gen_v8_4_3 : entity is "CE";
+  attribute C_SIM_COLLISION_CHECK : string;
+  attribute C_SIM_COLLISION_CHECK of hop_rom_blk_mem_gen_v8_4_3 : entity is "ALL";
+  attribute C_USE_BRAM_BLOCK : integer;
+  attribute C_USE_BRAM_BLOCK of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_USE_BYTE_WEA : integer;
+  attribute C_USE_BYTE_WEA of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_USE_BYTE_WEB : integer;
+  attribute C_USE_BYTE_WEB of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_USE_DEFAULT_DATA : integer;
+  attribute C_USE_DEFAULT_DATA of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_USE_ECC : integer;
+  attribute C_USE_ECC of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_USE_SOFTECC : integer;
+  attribute C_USE_SOFTECC of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_USE_URAM : integer;
+  attribute C_USE_URAM of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_WEA_WIDTH : integer;
+  attribute C_WEA_WIDTH of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
+  attribute C_WEB_WIDTH : integer;
+  attribute C_WEB_WIDTH of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
+  attribute C_WRITE_DEPTH_A : integer;
+  attribute C_WRITE_DEPTH_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 256;
+  attribute C_WRITE_DEPTH_B : integer;
+  attribute C_WRITE_DEPTH_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 256;
+  attribute C_WRITE_MODE_A : string;
+  attribute C_WRITE_MODE_A of hop_rom_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST";
+  attribute C_WRITE_MODE_B : string;
+  attribute C_WRITE_MODE_B of hop_rom_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST";
+  attribute C_WRITE_WIDTH_A : integer;
+  attribute C_WRITE_WIDTH_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 32;
+  attribute C_WRITE_WIDTH_B : integer;
+  attribute C_WRITE_WIDTH_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 32;
+  attribute C_XDEVICEFAMILY : string;
+  attribute C_XDEVICEFAMILY of hop_rom_blk_mem_gen_v8_4_3 : entity is "kintex7";
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3";
+  attribute downgradeipidentifiedwarnings : string;
+  attribute downgradeipidentifiedwarnings of hop_rom_blk_mem_gen_v8_4_3 : entity is "yes";
+end hop_rom_blk_mem_gen_v8_4_3;
+
+architecture STRUCTURE of hop_rom_blk_mem_gen_v8_4_3 is
+  signal \<const0>\ : STD_LOGIC;
+begin
+  dbiterr <= \<const0>\;
+  doutb(31) <= \<const0>\;
+  doutb(30) <= \<const0>\;
+  doutb(29) <= \<const0>\;
+  doutb(28) <= \<const0>\;
+  doutb(27) <= \<const0>\;
+  doutb(26) <= \<const0>\;
+  doutb(25) <= \<const0>\;
+  doutb(24) <= \<const0>\;
+  doutb(23) <= \<const0>\;
+  doutb(22) <= \<const0>\;
+  doutb(21) <= \<const0>\;
+  doutb(20) <= \<const0>\;
+  doutb(19) <= \<const0>\;
+  doutb(18) <= \<const0>\;
+  doutb(17) <= \<const0>\;
+  doutb(16) <= \<const0>\;
+  doutb(15) <= \<const0>\;
+  doutb(14) <= \<const0>\;
+  doutb(13) <= \<const0>\;
+  doutb(12) <= \<const0>\;
+  doutb(11) <= \<const0>\;
+  doutb(10) <= \<const0>\;
+  doutb(9) <= \<const0>\;
+  doutb(8) <= \<const0>\;
+  doutb(7) <= \<const0>\;
+  doutb(6) <= \<const0>\;
+  doutb(5) <= \<const0>\;
+  doutb(4) <= \<const0>\;
+  doutb(3) <= \<const0>\;
+  doutb(2) <= \<const0>\;
+  doutb(1) <= \<const0>\;
+  doutb(0) <= \<const0>\;
+  rdaddrecc(7) <= \<const0>\;
+  rdaddrecc(6) <= \<const0>\;
+  rdaddrecc(5) <= \<const0>\;
+  rdaddrecc(4) <= \<const0>\;
+  rdaddrecc(3) <= \<const0>\;
+  rdaddrecc(2) <= \<const0>\;
+  rdaddrecc(1) <= \<const0>\;
+  rdaddrecc(0) <= \<const0>\;
+  rsta_busy <= \<const0>\;
+  rstb_busy <= \<const0>\;
+  s_axi_arready <= \<const0>\;
+  s_axi_awready <= \<const0>\;
+  s_axi_bid(3) <= \<const0>\;
+  s_axi_bid(2) <= \<const0>\;
+  s_axi_bid(1) <= \<const0>\;
+  s_axi_bid(0) <= \<const0>\;
+  s_axi_bresp(1) <= \<const0>\;
+  s_axi_bresp(0) <= \<const0>\;
+  s_axi_bvalid <= \<const0>\;
+  s_axi_dbiterr <= \<const0>\;
+  s_axi_rdaddrecc(7) <= \<const0>\;
+  s_axi_rdaddrecc(6) <= \<const0>\;
+  s_axi_rdaddrecc(5) <= \<const0>\;
+  s_axi_rdaddrecc(4) <= \<const0>\;
+  s_axi_rdaddrecc(3) <= \<const0>\;
+  s_axi_rdaddrecc(2) <= \<const0>\;
+  s_axi_rdaddrecc(1) <= \<const0>\;
+  s_axi_rdaddrecc(0) <= \<const0>\;
+  s_axi_rdata(31) <= \<const0>\;
+  s_axi_rdata(30) <= \<const0>\;
+  s_axi_rdata(29) <= \<const0>\;
+  s_axi_rdata(28) <= \<const0>\;
+  s_axi_rdata(27) <= \<const0>\;
+  s_axi_rdata(26) <= \<const0>\;
+  s_axi_rdata(25) <= \<const0>\;
+  s_axi_rdata(24) <= \<const0>\;
+  s_axi_rdata(23) <= \<const0>\;
+  s_axi_rdata(22) <= \<const0>\;
+  s_axi_rdata(21) <= \<const0>\;
+  s_axi_rdata(20) <= \<const0>\;
+  s_axi_rdata(19) <= \<const0>\;
+  s_axi_rdata(18) <= \<const0>\;
+  s_axi_rdata(17) <= \<const0>\;
+  s_axi_rdata(16) <= \<const0>\;
+  s_axi_rdata(15) <= \<const0>\;
+  s_axi_rdata(14) <= \<const0>\;
+  s_axi_rdata(13) <= \<const0>\;
+  s_axi_rdata(12) <= \<const0>\;
+  s_axi_rdata(11) <= \<const0>\;
+  s_axi_rdata(10) <= \<const0>\;
+  s_axi_rdata(9) <= \<const0>\;
+  s_axi_rdata(8) <= \<const0>\;
+  s_axi_rdata(7) <= \<const0>\;
+  s_axi_rdata(6) <= \<const0>\;
+  s_axi_rdata(5) <= \<const0>\;
+  s_axi_rdata(4) <= \<const0>\;
+  s_axi_rdata(3) <= \<const0>\;
+  s_axi_rdata(2) <= \<const0>\;
+  s_axi_rdata(1) <= \<const0>\;
+  s_axi_rdata(0) <= \<const0>\;
+  s_axi_rid(3) <= \<const0>\;
+  s_axi_rid(2) <= \<const0>\;
+  s_axi_rid(1) <= \<const0>\;
+  s_axi_rid(0) <= \<const0>\;
+  s_axi_rlast <= \<const0>\;
+  s_axi_rresp(1) <= \<const0>\;
+  s_axi_rresp(0) <= \<const0>\;
+  s_axi_rvalid <= \<const0>\;
+  s_axi_sbiterr <= \<const0>\;
+  s_axi_wready <= \<const0>\;
+  sbiterr <= \<const0>\;
+GND: unisim.vcomponents.GND
+     port map (
+      G => \<const0>\
+    );
+inst_blk_mem_gen: entity work.hop_rom_blk_mem_gen_v8_4_3_synth
+     port map (
+      addra(7 downto 0) => addra(7 downto 0),
+      clka => clka,
+      douta(31 downto 0) => douta(31 downto 0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity hop_rom is
+  port (
+    clka : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+  attribute NotValidForBitStream : boolean;
+  attribute NotValidForBitStream of hop_rom : entity is true;
+  attribute CHECK_LICENSE_TYPE : string;
+  attribute CHECK_LICENSE_TYPE of hop_rom : entity is "hop_rom,blk_mem_gen_v8_4_3,{}";
+  attribute downgradeipidentifiedwarnings : string;
+  attribute downgradeipidentifiedwarnings of hop_rom : entity is "yes";
+  attribute x_core_info : string;
+  attribute x_core_info of hop_rom : entity is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
+end hop_rom;
+
+architecture STRUCTURE of hop_rom is
+  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+  attribute C_ADDRA_WIDTH : integer;
+  attribute C_ADDRA_WIDTH of U0 : label is 8;
+  attribute C_ADDRB_WIDTH : integer;
+  attribute C_ADDRB_WIDTH of U0 : label is 8;
+  attribute C_ALGORITHM : integer;
+  attribute C_ALGORITHM of U0 : label is 1;
+  attribute C_AXI_ID_WIDTH : integer;
+  attribute C_AXI_ID_WIDTH of U0 : label is 4;
+  attribute C_AXI_SLAVE_TYPE : integer;
+  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
+  attribute C_AXI_TYPE : integer;
+  attribute C_AXI_TYPE of U0 : label is 1;
+  attribute C_BYTE_SIZE : integer;
+  attribute C_BYTE_SIZE of U0 : label is 9;
+  attribute C_COMMON_CLK : integer;
+  attribute C_COMMON_CLK of U0 : label is 0;
+  attribute C_COUNT_18K_BRAM : string;
+  attribute C_COUNT_18K_BRAM of U0 : label is "1";
+  attribute C_COUNT_36K_BRAM : string;
+  attribute C_COUNT_36K_BRAM of U0 : label is "0";
+  attribute C_CTRL_ECC_ALGO : string;
+  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
+  attribute C_DEFAULT_DATA : string;
+  attribute C_DEFAULT_DATA of U0 : label is "0";
+  attribute C_DISABLE_WARN_BHV_COLL : integer;
+  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
+  attribute C_DISABLE_WARN_BHV_RANGE : integer;
+  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
+  attribute C_ELABORATION_DIR : string;
+  attribute C_ELABORATION_DIR of U0 : label is "./";
+  attribute C_ENABLE_32BIT_ADDRESS : integer;
+  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
+  attribute C_EN_DEEPSLEEP_PIN : integer;
+  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
+  attribute C_EN_ECC_PIPE : integer;
+  attribute C_EN_ECC_PIPE of U0 : label is 0;
+  attribute C_EN_RDADDRA_CHG : integer;
+  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
+  attribute C_EN_RDADDRB_CHG : integer;
+  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
+  attribute C_EN_SAFETY_CKT : integer;
+  attribute C_EN_SAFETY_CKT of U0 : label is 0;
+  attribute C_EN_SHUTDOWN_PIN : integer;
+  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
+  attribute C_EN_SLEEP_PIN : integer;
+  attribute C_EN_SLEEP_PIN of U0 : label is 0;
+  attribute C_EST_POWER_SUMMARY : string;
+  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     3.375199 mW";
+  attribute C_FAMILY : string;
+  attribute C_FAMILY of U0 : label is "kintex7";
+  attribute C_HAS_AXI_ID : integer;
+  attribute C_HAS_AXI_ID of U0 : label is 0;
+  attribute C_HAS_ENA : integer;
+  attribute C_HAS_ENA of U0 : label is 0;
+  attribute C_HAS_ENB : integer;
+  attribute C_HAS_ENB of U0 : label is 0;
+  attribute C_HAS_INJECTERR : integer;
+  attribute C_HAS_INJECTERR of U0 : label is 0;
+  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
+  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
+  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
+  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
+  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
+  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
+  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
+  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
+  attribute C_HAS_REGCEA : integer;
+  attribute C_HAS_REGCEA of U0 : label is 0;
+  attribute C_HAS_REGCEB : integer;
+  attribute C_HAS_REGCEB of U0 : label is 0;
+  attribute C_HAS_RSTA : integer;
+  attribute C_HAS_RSTA of U0 : label is 0;
+  attribute C_HAS_RSTB : integer;
+  attribute C_HAS_RSTB of U0 : label is 0;
+  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
+  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
+  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
+  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
+  attribute C_INITA_VAL : string;
+  attribute C_INITA_VAL of U0 : label is "0";
+  attribute C_INITB_VAL : string;
+  attribute C_INITB_VAL of U0 : label is "0";
+  attribute C_INIT_FILE : string;
+  attribute C_INIT_FILE of U0 : label is "hop_rom.mem";
+  attribute C_INIT_FILE_NAME : string;
+  attribute C_INIT_FILE_NAME of U0 : label is "hop_rom.mif";
+  attribute C_INTERFACE_TYPE : integer;
+  attribute C_INTERFACE_TYPE of U0 : label is 0;
+  attribute C_LOAD_INIT_FILE : integer;
+  attribute C_LOAD_INIT_FILE of U0 : label is 1;
+  attribute C_MEM_TYPE : integer;
+  attribute C_MEM_TYPE of U0 : label is 3;
+  attribute C_MUX_PIPELINE_STAGES : integer;
+  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
+  attribute C_PRIM_TYPE : integer;
+  attribute C_PRIM_TYPE of U0 : label is 1;
+  attribute C_READ_DEPTH_A : integer;
+  attribute C_READ_DEPTH_A of U0 : label is 256;
+  attribute C_READ_DEPTH_B : integer;
+  attribute C_READ_DEPTH_B of U0 : label is 256;
+  attribute C_READ_LATENCY_A : integer;
+  attribute C_READ_LATENCY_A of U0 : label is 1;
+  attribute C_READ_LATENCY_B : integer;
+  attribute C_READ_LATENCY_B of U0 : label is 1;
+  attribute C_READ_WIDTH_A : integer;
+  attribute C_READ_WIDTH_A of U0 : label is 32;
+  attribute C_READ_WIDTH_B : integer;
+  attribute C_READ_WIDTH_B of U0 : label is 32;
+  attribute C_RSTRAM_A : integer;
+  attribute C_RSTRAM_A of U0 : label is 0;
+  attribute C_RSTRAM_B : integer;
+  attribute C_RSTRAM_B of U0 : label is 0;
+  attribute C_RST_PRIORITY_A : string;
+  attribute C_RST_PRIORITY_A of U0 : label is "CE";
+  attribute C_RST_PRIORITY_B : string;
+  attribute C_RST_PRIORITY_B of U0 : label is "CE";
+  attribute C_SIM_COLLISION_CHECK : string;
+  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
+  attribute C_USE_BRAM_BLOCK : integer;
+  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
+  attribute C_USE_BYTE_WEA : integer;
+  attribute C_USE_BYTE_WEA of U0 : label is 0;
+  attribute C_USE_BYTE_WEB : integer;
+  attribute C_USE_BYTE_WEB of U0 : label is 0;
+  attribute C_USE_DEFAULT_DATA : integer;
+  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
+  attribute C_USE_ECC : integer;
+  attribute C_USE_ECC of U0 : label is 0;
+  attribute C_USE_SOFTECC : integer;
+  attribute C_USE_SOFTECC of U0 : label is 0;
+  attribute C_USE_URAM : integer;
+  attribute C_USE_URAM of U0 : label is 0;
+  attribute C_WEA_WIDTH : integer;
+  attribute C_WEA_WIDTH of U0 : label is 1;
+  attribute C_WEB_WIDTH : integer;
+  attribute C_WEB_WIDTH of U0 : label is 1;
+  attribute C_WRITE_DEPTH_A : integer;
+  attribute C_WRITE_DEPTH_A of U0 : label is 256;
+  attribute C_WRITE_DEPTH_B : integer;
+  attribute C_WRITE_DEPTH_B of U0 : label is 256;
+  attribute C_WRITE_MODE_A : string;
+  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
+  attribute C_WRITE_MODE_B : string;
+  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
+  attribute C_WRITE_WIDTH_A : integer;
+  attribute C_WRITE_WIDTH_A of U0 : label is 32;
+  attribute C_WRITE_WIDTH_B : integer;
+  attribute C_WRITE_WIDTH_B of U0 : label is 32;
+  attribute C_XDEVICEFAMILY : string;
+  attribute C_XDEVICEFAMILY of U0 : label is "kintex7";
+  attribute downgradeipidentifiedwarnings of U0 : label is "yes";
+  attribute x_interface_info : string;
+  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
+  attribute x_interface_parameter : string;
+  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
+  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
+  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
+begin
+U0: entity work.hop_rom_blk_mem_gen_v8_4_3
+     port map (
+      addra(7 downto 0) => addra(7 downto 0),
+      addrb(7 downto 0) => B"00000000",
+      clka => clka,
+      clkb => '0',
+      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
+      deepsleep => '0',
+      dina(31 downto 0) => B"00000000000000000000000000000000",
+      dinb(31 downto 0) => B"00000000000000000000000000000000",
+      douta(31 downto 0) => douta(31 downto 0),
+      doutb(31 downto 0) => NLW_U0_doutb_UNCONNECTED(31 downto 0),
+      eccpipece => '0',
+      ena => '0',
+      enb => '0',
+      injectdbiterr => '0',
+      injectsbiterr => '0',
+      rdaddrecc(7 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(7 downto 0),
+      regcea => '0',
+      regceb => '0',
+      rsta => '0',
+      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
+      rstb => '0',
+      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
+      s_aclk => '0',
+      s_aresetn => '0',
+      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
+      s_axi_arburst(1 downto 0) => B"00",
+      s_axi_arid(3 downto 0) => B"0000",
+      s_axi_arlen(7 downto 0) => B"00000000",
+      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
+      s_axi_arsize(2 downto 0) => B"000",
+      s_axi_arvalid => '0',
+      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
+      s_axi_awburst(1 downto 0) => B"00",
+      s_axi_awid(3 downto 0) => B"0000",
+      s_axi_awlen(7 downto 0) => B"00000000",
+      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
+      s_axi_awsize(2 downto 0) => B"000",
+      s_axi_awvalid => '0',
+      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
+      s_axi_bready => '0',
+      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
+      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
+      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
+      s_axi_injectdbiterr => '0',
+      s_axi_injectsbiterr => '0',
+      s_axi_rdaddrecc(7 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(7 downto 0),
+      s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
+      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
+      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
+      s_axi_rready => '0',
+      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
+      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
+      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
+      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
+      s_axi_wlast => '0',
+      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
+      s_axi_wstrb(0) => '0',
+      s_axi_wvalid => '0',
+      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
+      shutdown => '0',
+      sleep => '0',
+      wea(0) => '0',
+      web(0) => '0'
+    );
+end STRUCTURE;

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom/hop_rom_stub.v

@@ -0,0 +1,22 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:15:57 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v
+// Design      : hop_rom
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
+module hop_rom(clka, addra, douta)
+/* synthesis syn_black_box black_box_pad_pin="clka,addra[7:0],douta[31:0]" */;
+  input clka;
+  input [7:0]addra;
+  output [31:0]douta;
+endmodule

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom/hop_rom_stub.vhdl

@@ -0,0 +1,32 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:15:57 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl
+-- Design      : hop_rom
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity hop_rom is
+  Port ( 
+    clka : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+
+end hop_rom;
+
+architecture stub of hop_rom is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clka,addra[7:0],douta[31:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
+begin
+end;

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom/sim/hop_rom.v

@@ -0,0 +1,211 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 3
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module hop_rom (
+  clka,
+  addra,
+  douta
+);
+
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
+input wire clka;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
+input wire [7 : 0] addra;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
+output wire [31 : 0] douta;
+
+  blk_mem_gen_v8_4_3 #(
+    .C_FAMILY("kintex7"),
+    .C_XDEVICEFAMILY("kintex7"),
+    .C_ELABORATION_DIR("./"),
+    .C_INTERFACE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_USE_BRAM_BLOCK(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
+    .C_CTRL_ECC_ALGO("NONE"),
+    .C_HAS_AXI_ID(0),
+    .C_AXI_ID_WIDTH(4),
+    .C_MEM_TYPE(3),
+    .C_BYTE_SIZE(9),
+    .C_ALGORITHM(1),
+    .C_PRIM_TYPE(1),
+    .C_LOAD_INIT_FILE(1),
+    .C_INIT_FILE_NAME("hop_rom.mif"),
+    .C_INIT_FILE("hop_rom.mem"),
+    .C_USE_DEFAULT_DATA(0),
+    .C_DEFAULT_DATA("0"),
+    .C_HAS_RSTA(0),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RSTRAM_A(0),
+    .C_INITA_VAL("0"),
+    .C_HAS_ENA(0),
+    .C_HAS_REGCEA(0),
+    .C_USE_BYTE_WEA(0),
+    .C_WEA_WIDTH(1),
+    .C_WRITE_MODE_A("WRITE_FIRST"),
+    .C_WRITE_WIDTH_A(32),
+    .C_READ_WIDTH_A(32),
+    .C_WRITE_DEPTH_A(256),
+    .C_READ_DEPTH_A(256),
+    .C_ADDRA_WIDTH(8),
+    .C_HAS_RSTB(0),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RSTRAM_B(0),
+    .C_INITB_VAL("0"),
+    .C_HAS_ENB(0),
+    .C_HAS_REGCEB(0),
+    .C_USE_BYTE_WEB(0),
+    .C_WEB_WIDTH(1),
+    .C_WRITE_MODE_B("WRITE_FIRST"),
+    .C_WRITE_WIDTH_B(32),
+    .C_READ_WIDTH_B(32),
+    .C_WRITE_DEPTH_B(256),
+    .C_READ_DEPTH_B(256),
+    .C_ADDRB_WIDTH(8),
+    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_USE_SOFTECC(0),
+    .C_USE_ECC(0),
+    .C_EN_ECC_PIPE(0),
+    .C_READ_LATENCY_A(1),
+    .C_READ_LATENCY_B(1),
+    .C_HAS_INJECTERR(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_COMMON_CLK(0),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_EN_SLEEP_PIN(0),
+    .C_USE_URAM(0),
+    .C_EN_RDADDRA_CHG(0),
+    .C_EN_RDADDRB_CHG(0),
+    .C_EN_DEEPSLEEP_PIN(0),
+    .C_EN_SHUTDOWN_PIN(0),
+    .C_EN_SAFETY_CKT(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_COUNT_36K_BRAM("0"),
+    .C_COUNT_18K_BRAM("1"),
+    .C_EST_POWER_SUMMARY("Estimated Power for IP     :     3.375199 mW")
+  ) inst (
+    .clka(clka),
+    .rsta(1'D0),
+    .ena(1'D0),
+    .regcea(1'D0),
+    .wea(1'B0),
+    .addra(addra),
+    .dina(32'B0),
+    .douta(douta),
+    .clkb(1'D0),
+    .rstb(1'D0),
+    .enb(1'D0),
+    .regceb(1'D0),
+    .web(1'B0),
+    .addrb(8'B0),
+    .dinb(32'B0),
+    .doutb(),
+    .injectsbiterr(1'D0),
+    .injectdbiterr(1'D0),
+    .eccpipece(1'D0),
+    .sbiterr(),
+    .dbiterr(),
+    .rdaddrecc(),
+    .sleep(1'D0),
+    .deepsleep(1'D0),
+    .shutdown(1'D0),
+    .rsta_busy(),
+    .rstb_busy(),
+    .s_aclk(1'H0),
+    .s_aresetn(1'D0),
+    .s_axi_awid(4'B0),
+    .s_axi_awaddr(32'B0),
+    .s_axi_awlen(8'B0),
+    .s_axi_awsize(3'B0),
+    .s_axi_awburst(2'B0),
+    .s_axi_awvalid(1'D0),
+    .s_axi_awready(),
+    .s_axi_wdata(32'B0),
+    .s_axi_wstrb(1'B0),
+    .s_axi_wlast(1'D0),
+    .s_axi_wvalid(1'D0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'D0),
+    .s_axi_arid(4'B0),
+    .s_axi_araddr(32'B0),
+    .s_axi_arlen(8'B0),
+    .s_axi_arsize(3'B0),
+    .s_axi_arburst(2'B0),
+    .s_axi_arvalid(1'D0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'D0),
+    .s_axi_injectsbiterr(1'D0),
+    .s_axi_injectdbiterr(1'D0),
+    .s_axi_sbiterr(),
+    .s_axi_dbiterr(),
+    .s_axi_rdaddrecc()
+  );
+endmodule

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hrc_64_12_025/demo_tb/tb_hrc_64_12_025.vhd

@@ -0,0 +1,261 @@
+--------------------------------------------------------------------------------
+-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+-- Description:
+-- This is an example testbench for the FIR Compiler IP core.
+-- The testbench has been generated by Vivado to accompany the IP core
+-- instance you have generated.
+--
+-- This testbench is for demonstration purposes only.  See note below for
+-- instructions on how to use it with your core.
+--
+-- See the FIR Compiler product guide for further information
+-- about this core.
+--
+--------------------------------------------------------------------------------
+-- Using this testbench
+--
+-- This testbench instantiates your generated FIR Compiler core
+-- instance named "hrc_64_12_025".
+--
+-- Use Vivado's Run Simulation flow to run this testbench.  See the Vivado
+-- documentation for details.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_hrc_64_12_025 is
+end tb_hrc_64_12_025;
+
+architecture tb of tb_hrc_64_12_025 is
+
+  -----------------------------------------------------------------------
+  -- Timing constants
+  -----------------------------------------------------------------------
+  constant CLOCK_PERIOD : time := 100 ns;
+  constant T_HOLD       : time := 10 ns;
+  constant T_STROBE     : time := CLOCK_PERIOD - (1 ns);
+
+  -----------------------------------------------------------------------
+  -- DUT signals
+  -----------------------------------------------------------------------
+
+  -- General signals
+  signal aclk                            : std_logic := '0';  -- the master clock
+
+  -- Data slave channel signals
+  signal s_axis_data_tvalid              : std_logic := '0';  -- payload is valid
+  signal s_axis_data_tready              : std_logic := '1';  -- slave is ready
+  signal s_axis_data_tdata               : std_logic_vector(7 downto 0) := (others => '0');  -- data payload
+
+  -- Data master channel signals
+  signal m_axis_data_tvalid              : std_logic := '0';  -- payload is valid
+  signal m_axis_data_tdata               : std_logic_vector(23 downto 0) := (others => '0');  -- data payload
+
+  -----------------------------------------------------------------------
+  -- Aliases for AXI channel TDATA and TUSER fields
+  -- These are a convenience for viewing data in a simulator waveform viewer.
+  -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
+  -- to prevent the simulator optimizing away these signals.
+  -----------------------------------------------------------------------
+
+  -- Data slave channel alias signals
+  signal s_axis_data_tdata_data        : std_logic_vector(1 downto 0) := (others => '0');
+
+  -- Data master channel alias signals
+  signal m_axis_data_tdata_data        : std_logic_vector(17 downto 0) := (others => '0');
+
+
+begin
+
+  -----------------------------------------------------------------------
+  -- Instantiate the DUT
+  -----------------------------------------------------------------------
+
+  dut : entity work.hrc_64_12_025
+    port map (
+      aclk                            => aclk,
+      s_axis_data_tvalid              => s_axis_data_tvalid,
+      s_axis_data_tready              => s_axis_data_tready,
+      s_axis_data_tdata               => s_axis_data_tdata,
+      m_axis_data_tvalid              => m_axis_data_tvalid,
+      m_axis_data_tdata               => m_axis_data_tdata
+      );
+
+  -----------------------------------------------------------------------
+  -- Generate clock
+  -----------------------------------------------------------------------
+
+  clock_gen : process
+  begin
+    aclk <= '0';
+    wait for CLOCK_PERIOD;
+    loop
+      aclk <= '0';
+      wait for CLOCK_PERIOD/2;
+      aclk <= '1';
+      wait for CLOCK_PERIOD/2;
+    end loop;
+  end process clock_gen;
+
+  -----------------------------------------------------------------------
+  -- Generate inputs
+  -----------------------------------------------------------------------
+
+  stimuli : process
+
+    -- Procedure to drive a number of input samples with specific data
+    -- data is the data value to drive on the tdata signal
+    -- samples is the number of zero-data input samples to drive
+    procedure drive_data ( data    : std_logic_vector(7 downto 0);
+                           samples : natural := 1 ) is
+      variable ip_count : integer := 0;
+    begin
+      ip_count := 0;
+      loop
+        s_axis_data_tvalid <= '1';
+        s_axis_data_tdata  <= data;
+        loop
+          wait until rising_edge(aclk);
+          exit when s_axis_data_tready = '1';
+        end loop;
+        ip_count := ip_count + 1;
+        wait for T_HOLD;
+      -- Input rate is 1 input each 64 clock cycles: drive valid inputs at this rate
+        s_axis_data_tvalid <= '0';
+        wait for CLOCK_PERIOD * 63;
+        exit when ip_count >= samples;
+      end loop;
+    end procedure drive_data;
+
+    -- Procedure to drive a number of zero-data input samples
+    -- samples is the number of zero-data input samples to drive
+    procedure drive_zeros ( samples : natural := 1 ) is
+    begin
+      drive_data((others => '0'), samples);
+    end procedure drive_zeros;
+
+    -- Procedure to drive an impulse and let the impulse response emerge on the data master channel
+    -- samples is the number of input samples to drive; default is enough for impulse response output to emerge
+    procedure drive_impulse ( samples : natural := 837 ) is
+      variable impulse : std_logic_vector(7 downto 0);
+    begin
+      impulse := (others => '0');  -- initialize unused bits to zero
+      impulse(1 downto 0) := "01";
+      drive_data(impulse);
+      if samples > 1 then
+        drive_zeros(samples-1);
+      end if;
+    end procedure drive_impulse;
+
+  begin
+
+    -- Drive inputs T_HOLD time after rising edge of clock
+    wait until rising_edge(aclk);
+    wait for T_HOLD;
+
+    -- Drive a single impulse and let the impulse response emerge
+    drive_impulse;
+
+    -- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
+    drive_impulse(2);  -- start of impulse; data is now zero
+    s_axis_data_tvalid <= '0';
+    wait for CLOCK_PERIOD * 320;  -- provide no data for 5 input samples worth
+    drive_zeros(2);  -- 2 normal input samples
+    s_axis_data_tvalid <= '1';
+    wait for CLOCK_PERIOD * 320;  -- provide data as fast as the core can accept it for 5 input samples worth
+    drive_zeros(828);  -- back to normal operation
+
+    -- End of test
+    report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
+    wait;
+
+  end process stimuli;
+
+  -----------------------------------------------------------------------
+  -- Check outputs
+  -----------------------------------------------------------------------
+
+  check_outputs : process
+    variable check_ok : boolean := true;
+  begin
+
+    -- Check outputs T_STROBE time after rising edge of clock
+    wait until rising_edge(aclk);
+    wait for T_STROBE;
+
+    -- Do not check the output payload values, as this requires the behavioral model
+    -- which would make this demonstration testbench unwieldy.
+    -- Instead, check the protocol of the master DATA channel:
+    -- check that the payload is valid (not X) when TVALID is high
+
+    if m_axis_data_tvalid = '1' then
+      if is_x(m_axis_data_tdata) then
+        report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
+        check_ok := false;
+      end if;
+
+    end if;
+
+    assert check_ok
+      report "ERROR: terminating test with failures." severity failure;
+
+  end process check_outputs;
+
+  -----------------------------------------------------------------------
+  -- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
+  -----------------------------------------------------------------------
+
+  -- Data slave channel alias signals
+  s_axis_data_tdata_data        <= s_axis_data_tdata(1 downto 0);
+
+  -- Data master channel alias signals: update these only when they are valid
+  m_axis_data_tdata_data        <= m_axis_data_tdata(17 downto 0) when m_axis_data_tvalid = '1';
+
+end tb;

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hrc_64_12_025/hrc_64_12_025.veo

@@ -0,0 +1,70 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fir_compiler:7.2
+// IP Revision: 12
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+hrc_64_12_025 your_instance_name (
+  .aclk(aclk),                              // input wire aclk
+  .s_axis_data_tvalid(s_axis_data_tvalid),  // input wire s_axis_data_tvalid
+  .s_axis_data_tready(s_axis_data_tready),  // output wire s_axis_data_tready
+  .s_axis_data_tdata(s_axis_data_tdata),    // input wire [7 : 0] s_axis_data_tdata
+  .m_axis_data_tvalid(m_axis_data_tvalid),  // output wire m_axis_data_tvalid
+  .m_axis_data_tdata(m_axis_data_tdata)    // output wire [23 : 0] m_axis_data_tdata
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file hrc_64_12_025.v when simulating
+// the core, hrc_64_12_025. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hrc_64_12_025/hrc_64_12_025.vho

@@ -0,0 +1,85 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
+-- IP Revision: 12
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT hrc_64_12_025
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_data_tvalid : IN STD_LOGIC;
+    s_axis_data_tready : OUT STD_LOGIC;
+    s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    m_axis_data_tvalid : OUT STD_LOGIC;
+    m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : hrc_64_12_025
+  PORT MAP (
+    aclk => aclk,
+    s_axis_data_tvalid => s_axis_data_tvalid,
+    s_axis_data_tready => s_axis_data_tready,
+    s_axis_data_tdata => s_axis_data_tdata,
+    m_axis_data_tvalid => m_axis_data_tvalid,
+    m_axis_data_tdata => m_axis_data_tdata
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file hrc_64_12_025.vhd when simulating
+-- the core, hrc_64_12_025. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hrc_64_12_025/hrc_64_12_025_stub.v

@@ -0,0 +1,26 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:15:42 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.v
+// Design      : hrc_64_12_025
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
+module hrc_64_12_025(aclk, s_axis_data_tvalid, s_axis_data_tready, 
+  s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
+/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
+  input aclk;
+  input s_axis_data_tvalid;
+  output s_axis_data_tready;
+  input [7:0]s_axis_data_tdata;
+  output m_axis_data_tvalid;
+  output [23:0]m_axis_data_tdata;
+endmodule

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hrc_64_12_025/hrc_64_12_025_stub.vhdl

@@ -0,0 +1,35 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:15:42 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.vhdl
+-- Design      : hrc_64_12_025
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity hrc_64_12_025 is
+  Port ( 
+    aclk : in STD_LOGIC;
+    s_axis_data_tvalid : in STD_LOGIC;
+    s_axis_data_tready : out STD_LOGIC;
+    s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    m_axis_data_tvalid : out STD_LOGIC;
+    m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+
+end hrc_64_12_025;
+
+architecture stub of hrc_64_12_025 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
+begin
+end;

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hrc_64_12_025/sim/hrc_64_12_025.vhd

@@ -0,0 +1,281 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
+-- IP Revision: 12
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY fir_compiler_v7_2_12;
+USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
+
+ENTITY hrc_64_12_025 IS
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_data_tvalid : IN STD_LOGIC;
+    s_axis_data_tready : OUT STD_LOGIC;
+    s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    m_axis_data_tvalid : OUT STD_LOGIC;
+    m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END hrc_64_12_025;
+
+ARCHITECTURE hrc_64_12_025_arch OF hrc_64_12_025 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF hrc_64_12_025_arch: ARCHITECTURE IS "yes";
+  COMPONENT fir_compiler_v7_2_12 IS
+    GENERIC (
+      C_XDEVICEFAMILY : STRING;
+      C_ELABORATION_DIR : STRING;
+      C_COMPONENT_NAME : STRING;
+      C_COEF_FILE : STRING;
+      C_COEF_FILE_LINES : INTEGER;
+      C_FILTER_TYPE : INTEGER;
+      C_INTERP_RATE : INTEGER;
+      C_DECIM_RATE : INTEGER;
+      C_ZERO_PACKING_FACTOR : INTEGER;
+      C_SYMMETRY : INTEGER;
+      C_NUM_FILTS : INTEGER;
+      C_NUM_TAPS : INTEGER;
+      C_NUM_CHANNELS : INTEGER;
+      C_CHANNEL_PATTERN : STRING;
+      C_ROUND_MODE : INTEGER;
+      C_COEF_RELOAD : INTEGER;
+      C_NUM_RELOAD_SLOTS : INTEGER;
+      C_COL_MODE : INTEGER;
+      C_COL_PIPE_LEN : INTEGER;
+      C_COL_CONFIG : STRING;
+      C_OPTIMIZATION : INTEGER;
+      C_DATA_PATH_WIDTHS : STRING;
+      C_DATA_IP_PATH_WIDTHS : STRING;
+      C_DATA_PX_PATH_WIDTHS : STRING;
+      C_DATA_WIDTH : INTEGER;
+      C_COEF_PATH_WIDTHS : STRING;
+      C_COEF_WIDTH : INTEGER;
+      C_DATA_PATH_SRC : STRING;
+      C_COEF_PATH_SRC : STRING;
+      C_PX_PATH_SRC : STRING;
+      C_DATA_PATH_SIGN : STRING;
+      C_COEF_PATH_SIGN : STRING;
+      C_ACCUM_PATH_WIDTHS : STRING;
+      C_OUTPUT_WIDTH : INTEGER;
+      C_OUTPUT_PATH_WIDTHS : STRING;
+      C_ACCUM_OP_PATH_WIDTHS : STRING;
+      C_EXT_MULT_CNFG : STRING;
+      C_DATA_PATH_PSAMP_SRC : STRING;
+      C_OP_PATH_PSAMP_SRC : STRING;
+      C_NUM_MADDS : INTEGER;
+      C_OPT_MADDS : STRING;
+      C_OVERSAMPLING_RATE : INTEGER;
+      C_INPUT_RATE : INTEGER;
+      C_OUTPUT_RATE : INTEGER;
+      C_DATA_MEMTYPE : INTEGER;
+      C_COEF_MEMTYPE : INTEGER;
+      C_IPBUFF_MEMTYPE : INTEGER;
+      C_OPBUFF_MEMTYPE : INTEGER;
+      C_DATAPATH_MEMTYPE : INTEGER;
+      C_MEM_ARRANGEMENT : INTEGER;
+      C_DATA_MEM_PACKING : INTEGER;
+      C_COEF_MEM_PACKING : INTEGER;
+      C_FILTS_PACKED : INTEGER;
+      C_LATENCY : INTEGER;
+      C_HAS_ARESETn : INTEGER;
+      C_HAS_ACLKEN : INTEGER;
+      C_DATA_HAS_TLAST : INTEGER;
+      C_S_DATA_HAS_FIFO : INTEGER;
+      C_S_DATA_HAS_TUSER : INTEGER;
+      C_S_DATA_TDATA_WIDTH : INTEGER;
+      C_S_DATA_TUSER_WIDTH : INTEGER;
+      C_M_DATA_HAS_TREADY : INTEGER;
+      C_M_DATA_HAS_TUSER : INTEGER;
+      C_M_DATA_TDATA_WIDTH : INTEGER;
+      C_M_DATA_TUSER_WIDTH : INTEGER;
+      C_HAS_CONFIG_CHANNEL : INTEGER;
+      C_CONFIG_SYNC_MODE : INTEGER;
+      C_CONFIG_PACKET_SIZE : INTEGER;
+      C_CONFIG_TDATA_WIDTH : INTEGER;
+      C_RELOAD_TDATA_WIDTH : INTEGER
+    );
+    PORT (
+      aresetn : IN STD_LOGIC;
+      aclk : IN STD_LOGIC;
+      aclken : IN STD_LOGIC;
+      s_axis_data_tvalid : IN STD_LOGIC;
+      s_axis_data_tready : OUT STD_LOGIC;
+      s_axis_data_tlast : IN STD_LOGIC;
+      s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axis_config_tvalid : IN STD_LOGIC;
+      s_axis_config_tready : OUT STD_LOGIC;
+      s_axis_config_tlast : IN STD_LOGIC;
+      s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_reload_tvalid : IN STD_LOGIC;
+      s_axis_reload_tready : OUT STD_LOGIC;
+      s_axis_reload_tlast : IN STD_LOGIC;
+      s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_data_tvalid : OUT STD_LOGIC;
+      m_axis_data_tready : IN STD_LOGIC;
+      m_axis_data_tlast : OUT STD_LOGIC;
+      m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+      event_s_data_tlast_missing : OUT STD_LOGIC;
+      event_s_data_tlast_unexpected : OUT STD_LOGIC;
+      event_s_data_chanid_incorrect : OUT STD_LOGIC;
+      event_s_config_tlast_missing : OUT STD_LOGIC;
+      event_s_config_tlast_unexpected : OUT STD_LOGIC;
+      event_s_reload_tlast_missing : OUT STD_LOGIC;
+      event_s_reload_tlast_unexpected : OUT STD_LOGIC
+    );
+  END COMPONENT fir_compiler_v7_2_12;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
+BEGIN
+  U0 : fir_compiler_v7_2_12
+    GENERIC MAP (
+      C_XDEVICEFAMILY => "kintex7",
+      C_ELABORATION_DIR => "./",
+      C_COMPONENT_NAME => "hrc_64_12_025",
+      C_COEF_FILE => "hrc_64_12_025.mif",
+      C_COEF_FILE_LINES => 832,
+      C_FILTER_TYPE => 2,
+      C_INTERP_RATE => 64,
+      C_DECIM_RATE => 1,
+      C_ZERO_PACKING_FACTOR => 1,
+      C_SYMMETRY => 0,
+      C_NUM_FILTS => 1,
+      C_NUM_TAPS => 769,
+      C_NUM_CHANNELS => 1,
+      C_CHANNEL_PATTERN => "fixed",
+      C_ROUND_MODE => 0,
+      C_COEF_RELOAD => 0,
+      C_NUM_RELOAD_SLOTS => 1,
+      C_COL_MODE => 1,
+      C_COL_PIPE_LEN => 4,
+      C_COL_CONFIG => "13",
+      C_OPTIMIZATION => 0,
+      C_DATA_PATH_WIDTHS => "2",
+      C_DATA_IP_PATH_WIDTHS => "2",
+      C_DATA_PX_PATH_WIDTHS => "2",
+      C_DATA_WIDTH => 2,
+      C_COEF_PATH_WIDTHS => "16",
+      C_COEF_WIDTH => 16,
+      C_DATA_PATH_SRC => "0",
+      C_COEF_PATH_SRC => "0",
+      C_PX_PATH_SRC => "0",
+      C_DATA_PATH_SIGN => "0",
+      C_COEF_PATH_SIGN => "0",
+      C_ACCUM_PATH_WIDTHS => "18",
+      C_OUTPUT_WIDTH => 18,
+      C_OUTPUT_PATH_WIDTHS => "18",
+      C_ACCUM_OP_PATH_WIDTHS => "18",
+      C_EXT_MULT_CNFG => "none",
+      C_DATA_PATH_PSAMP_SRC => "0",
+      C_OP_PATH_PSAMP_SRC => "0",
+      C_NUM_MADDS => 13,
+      C_OPT_MADDS => "none",
+      C_OVERSAMPLING_RATE => 1,
+      C_INPUT_RATE => 64,
+      C_OUTPUT_RATE => 1,
+      C_DATA_MEMTYPE => 0,
+      C_COEF_MEMTYPE => 2,
+      C_IPBUFF_MEMTYPE => 0,
+      C_OPBUFF_MEMTYPE => 0,
+      C_DATAPATH_MEMTYPE => 0,
+      C_MEM_ARRANGEMENT => 2,
+      C_DATA_MEM_PACKING => 0,
+      C_COEF_MEM_PACKING => 0,
+      C_FILTS_PACKED => 0,
+      C_LATENCY => 19,
+      C_HAS_ARESETn => 0,
+      C_HAS_ACLKEN => 0,
+      C_DATA_HAS_TLAST => 0,
+      C_S_DATA_HAS_FIFO => 0,
+      C_S_DATA_HAS_TUSER => 0,
+      C_S_DATA_TDATA_WIDTH => 8,
+      C_S_DATA_TUSER_WIDTH => 1,
+      C_M_DATA_HAS_TREADY => 0,
+      C_M_DATA_HAS_TUSER => 0,
+      C_M_DATA_TDATA_WIDTH => 24,
+      C_M_DATA_TUSER_WIDTH => 1,
+      C_HAS_CONFIG_CHANNEL => 0,
+      C_CONFIG_SYNC_MODE => 0,
+      C_CONFIG_PACKET_SIZE => 0,
+      C_CONFIG_TDATA_WIDTH => 1,
+      C_RELOAD_TDATA_WIDTH => 1
+    )
+    PORT MAP (
+      aresetn => '1',
+      aclk => aclk,
+      aclken => '1',
+      s_axis_data_tvalid => s_axis_data_tvalid,
+      s_axis_data_tready => s_axis_data_tready,
+      s_axis_data_tlast => '0',
+      s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_data_tdata => s_axis_data_tdata,
+      s_axis_config_tvalid => '0',
+      s_axis_config_tlast => '0',
+      s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_reload_tvalid => '0',
+      s_axis_reload_tlast => '0',
+      s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      m_axis_data_tvalid => m_axis_data_tvalid,
+      m_axis_data_tready => '1',
+      m_axis_data_tdata => m_axis_data_tdata
+    );
+END hrc_64_12_025_arch;

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd

@@ -0,0 +1,418 @@
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+`protect end_protected

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/mem_init_files/hop_rom.mif

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modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/mem_init_files/hrc_64_12_025.coe

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modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/mem_init_files/sweep_freq.coe

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+MEMORY_INITIALIZATION_RADIX = 10;
+MEMORY_INITIALIZATION_VECTOR = 
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modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/README.txt

@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x8.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x8.sh' script.
+
+./cmpy_18x8.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x8.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x8.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/cmpy_18x8.sh

@@ -0,0 +1,154 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x8.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
+# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x8.sh [-help]
+# usage: cmpy_18x8.sh [-lib_map_path]
+# usage: cmpy_18x8.sh [-noclean_files]
+# usage: cmpy_18x8.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+  if [[ ($1 != "" && -e $1) ]]; then
+    lib_map_path="$1"
+  else
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x8.sh [-help]\n\
+Usage: cmpy_18x8.sh [-lib_map_path]\n\
+Usage: cmpy_18x8.sh [-reset_run]\n\
+Usage: cmpy_18x8.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/compile.do

@@ -0,0 +1,52 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xil_defaultlib
+vlib activehdl/xpm
+vlib activehdl/xbip_utils_v3_0_10
+vlib activehdl/axi_utils_v2_0_6
+vlib activehdl/xbip_pipe_v3_0_6
+vlib activehdl/xbip_bram18k_v3_0_6
+vlib activehdl/mult_gen_v12_0_15
+vlib activehdl/cmpy_v6_0_17
+
+vmap xil_defaultlib activehdl/xil_defaultlib
+vmap xpm activehdl/xpm
+vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 activehdl/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 activehdl/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 activehdl/mult_gen_v12_0_15
+vmap cmpy_v6_0_17 activehdl/cmpy_v6_0_17
+
+vlog -work xil_defaultlib  -sv2k12 \
+"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xbip_utils_v3_0_10 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work cmpy_v6_0_17 -93 \
+"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/file_info.txt

@@ -0,0 +1,10 @@
+xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/simulate.do

@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+cmpy_18x8 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cmpy_18x8 xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {cmpy_18x8.udo}
+
+run -all
+
+endsim
+
+quit -force

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/README.txt

@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x8.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x8.sh' script.
+
+./cmpy_18x8.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x8.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x8.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/cmpy_18x8.sh

@@ -0,0 +1,175 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x8.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
+# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x8.sh [-help]
+# usage: cmpy_18x8.sh [-lib_map_path]
+# usage: cmpy_18x8.sh [-noclean_files]
+# usage: cmpy_18x8.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.cmpy_18x8 \
+       -f run.f \
+       -top glbl \
+       glbl.v
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x8.sh [-help]\n\
+Usage: cmpy_18x8.sh [-lib_map_path]\n\
+Usage: cmpy_18x8.sh [-reset_run]\n\
+Usage: cmpy_18x8.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/file_info.txt

@@ -0,0 +1,10 @@
+xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/run.f

@@ -0,0 +1,31 @@
+-makelib ies_lib/xil_defaultlib -sv \
+  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/xbip_utils_v3_0_10 \
+  "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/axi_utils_v2_0_6 \
+  "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xbip_pipe_v3_0_6 \
+  "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xbip_bram18k_v3_0_6 \
+  "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/mult_gen_v12_0_15 \
+  "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/cmpy_v6_0_17 \
+  "../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x8.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x8.sh' script.
+
+./cmpy_18x8.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x8.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x8.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/cmpy_18x8.sh

@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x8.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
+# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x8.sh [-help]
+# usage: cmpy_18x8.sh [-lib_map_path]
+# usage: cmpy_18x8.sh [-noclean_files]
+# usage: cmpy_18x8.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="C:/Mentor/CompLib/2019.1.3"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x8.sh [-help]\n\
+Usage: cmpy_18x8.sh [-lib_map_path]\n\
+Usage: cmpy_18x8.sh [-reset_run]\n\
+Usage: cmpy_18x8.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/compile.do

@@ -0,0 +1,11 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
+
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/file_info.txt

@@ -0,0 +1 @@
+cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/simulate.do

@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.cmpy_18x8
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {cmpy_18x8.udo}
+
+run -all
+
+quit -force

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/wave.do

@@ -0,0 +1 @@
+add wave *

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x8.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x8.sh' script.
+
+./cmpy_18x8.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x8.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x8.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/cmpy_18x8.sh

@@ -0,0 +1,175 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x8.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
+# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x8.sh [-help]
+# usage: cmpy_18x8.sh [-lib_map_path]
+# usage: cmpy_18x8.sh [-noclean_files]
+# usage: cmpy_18x8.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+  if [[ ($1 != "" && -e $1) ]]; then
+    lib_map_path="$1"
+  else
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x8.sh [-help]\n\
+Usage: cmpy_18x8.sh [-lib_map_path]\n\
+Usage: cmpy_18x8.sh [-reset_run]\n\
+Usage: cmpy_18x8.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/compile.do

@@ -0,0 +1,52 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xil_defaultlib
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/xbip_utils_v3_0_10
+vlib questa_lib/msim/axi_utils_v2_0_6
+vlib questa_lib/msim/xbip_pipe_v3_0_6
+vlib questa_lib/msim/xbip_bram18k_v3_0_6
+vlib questa_lib/msim/mult_gen_v12_0_15
+vlib questa_lib/msim/cmpy_v6_0_17
+
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+vmap xpm questa_lib/msim/xpm
+vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 questa_lib/msim/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 questa_lib/msim/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 questa_lib/msim/mult_gen_v12_0_15
+vmap cmpy_v6_0_17 questa_lib/msim/cmpy_v6_0_17
+
+vlog -work xil_defaultlib -64 -sv \
+"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xbip_utils_v3_0_10 -64 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -64 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -64 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work cmpy_v6_0_17 -64 -93 \
+"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/elaborate.do

@@ -0,0 +1 @@
+vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.cmpy_18x8 xil_defaultlib.glbl -o cmpy_18x8_opt

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/file_info.txt

@@ -0,0 +1,10 @@
+xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/simulate.do

@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -t 1ps -lib xil_defaultlib cmpy_18x8_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {cmpy_18x8.udo}
+
+run -all
+
+quit -force

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x8.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x8.sh' script.
+
+./cmpy_18x8.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x8.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x8.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/cmpy_18x8.sh

@@ -0,0 +1,154 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x8.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
+# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x8.sh [-help]
+# usage: cmpy_18x8.sh [-lib_map_path]
+# usage: cmpy_18x8.sh [-noclean_files]
+# usage: cmpy_18x8.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+  if [[ ($1 != "" && -e $1) ]]; then
+    lib_map_path="$1"
+  else
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x8.sh [-help]\n\
+Usage: cmpy_18x8.sh [-lib_map_path]\n\
+Usage: cmpy_18x8.sh [-reset_run]\n\
+Usage: cmpy_18x8.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/compile.do

@@ -0,0 +1,52 @@
+vlib work
+vlib riviera
+
+vlib riviera/xil_defaultlib
+vlib riviera/xpm
+vlib riviera/xbip_utils_v3_0_10
+vlib riviera/axi_utils_v2_0_6
+vlib riviera/xbip_pipe_v3_0_6
+vlib riviera/xbip_bram18k_v3_0_6
+vlib riviera/mult_gen_v12_0_15
+vlib riviera/cmpy_v6_0_17
+
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap xpm riviera/xpm
+vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 riviera/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 riviera/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 riviera/mult_gen_v12_0_15
+vmap cmpy_v6_0_17 riviera/cmpy_v6_0_17
+
+vlog -work xil_defaultlib  -sv2k12 \
+"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xbip_utils_v3_0_10 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work cmpy_v6_0_17 -93 \
+"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/file_info.txt

@@ -0,0 +1,10 @@
+xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/simulate.do

@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+cmpy_18x8 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cmpy_18x8 xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {cmpy_18x8.udo}
+
+run -all
+
+endsim
+
+quit -force

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/vcs/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x8.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x8.sh' script.
+
+./cmpy_18x8.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x8.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x8.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/vcs/cmpy_18x8.sh

@@ -0,0 +1,252 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x8.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
+# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x8.sh [-help]
+# usage: cmpy_18x8.sh [-lib_map_path]
+# usage: cmpy_18x8.sh [-noclean_files]
+# usage: cmpy_18x8.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xil_defaultlib $vlogan_opts -sverilog \
+    "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work axi_utils_v2_0_6 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xbip_pipe_v3_0_6 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xbip_bram18k_v3_0_6 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work mult_gen_v12_0_15 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work cmpy_v6_0_17 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.cmpy_18x8 xil_defaultlib.glbl -o cmpy_18x8_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./cmpy_18x8_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key cmpy_18x8_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc cmpy_18x8_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x8.sh [-help]\n\
+Usage: cmpy_18x8.sh [-lib_map_path]\n\
+Usage: cmpy_18x8.sh [-reset_run]\n\
+Usage: cmpy_18x8.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/vcs/file_info.txt

@@ -0,0 +1,10 @@
+xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/vcs/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/vcs/simulate.do

@@ -0,0 +1,2 @@
+run
+quit

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/README.txt

@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x8.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x8.sh' script.
+
+./cmpy_18x8.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x8.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x8.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/cmpy_18x8.sh

@@ -0,0 +1,175 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x8.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
+# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x8.sh [-help]
+# usage: cmpy_18x8.sh [-lib_map_path]
+# usage: cmpy_18x8.sh [-noclean_files]
+# usage: cmpy_18x8.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.cmpy_18x8 \
+       -f run.f \
+       -top glbl \
+       glbl.v
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x8.sh [-help]\n\
+Usage: cmpy_18x8.sh [-lib_map_path]\n\
+Usage: cmpy_18x8.sh [-reset_run]\n\
+Usage: cmpy_18x8.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/file_info.txt

@@ -0,0 +1,10 @@
+xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/run.f

@@ -0,0 +1,31 @@
+-makelib xcelium_lib/xil_defaultlib -sv \
+  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/xbip_utils_v3_0_10 \
+  "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/axi_utils_v2_0_6 \
+  "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xbip_pipe_v3_0_6 \
+  "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xbip_bram18k_v3_0_6 \
+  "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/mult_gen_v12_0_15 \
+  "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/cmpy_v6_0_17 \
+  "../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xsim/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_18x8.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_18x8.sh' script.
+
+./cmpy_18x8.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_18x8.sh -noclean_files
+
+For more information on the script, please type './cmpy_18x8.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xsim/cmd.tcl

@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xsim/cmpy_18x8.sh

@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_18x8.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
+# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_18x8.sh [-help]
+# usage: cmpy_18x8.sh [-lib_map_path]
+# usage: cmpy_18x8.sh [-noclean_files]
+# usage: cmpy_18x8.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0
+xvhdl_opts="--relax"
+
+
+# Script info
+echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L secureip -L xpm --snapshot cmpy_18x8 xil_defaultlib.cmpy_18x8 -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim cmpy_18x8 -key {Behavioral:sim_1:Functional:cmpy_18x8} -tclbatch cmd.tcl -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb cmpy_18x8.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_18x8.sh [-help]\n\
+Usage: cmpy_18x8.sh [-lib_map_path]\n\
+Usage: cmpy_18x8.sh [-reset_run]\n\
+Usage: cmpy_18x8.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2