Archived
Optimize project dir structure, add dl814_k7 proj.
This commit is contained in:
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
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// Date : Sat Mar 18 23:15:37 2023
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// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
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// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_stub.v
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// Design : dds_32b_8b
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7k410tffg900-2
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// --------------------------------------------------------------------------------
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||||
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "dds_compiler_v6_0_18,Vivado 2019.1.3" *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_config_tvalid,
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s_axis_config_tdata, m_axis_data_tvalid, m_axis_data_tdata)
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/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tvalid,s_axis_config_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
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input aclk;
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input s_axis_config_tvalid;
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input [31:0]s_axis_config_tdata;
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output m_axis_data_tvalid;
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output [15:0]m_axis_data_tdata;
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endmodule
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||||
+34
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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||||
-- --------------------------------------------------------------------------------
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||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
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||||
-- Date : Sat Mar 18 23:15:37 2023
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||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
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||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_stub.vhdl
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||||
-- Design : dds_32b_8b
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||||
-- Purpose : Stub declaration of top-level module interface
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||||
-- Device : xc7k410tffg900-2
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||||
-- --------------------------------------------------------------------------------
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||||
library IEEE;
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||||
use IEEE.STD_LOGIC_1164.ALL;
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||||
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||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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||||
Port (
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||||
aclk : in STD_LOGIC;
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||||
s_axis_config_tvalid : in STD_LOGIC;
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||||
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
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||||
m_axis_data_tvalid : out STD_LOGIC;
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||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
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||||
);
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||||
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||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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||||
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||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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||||
attribute syn_black_box : boolean;
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||||
attribute black_box_pad_pin : string;
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||||
attribute syn_black_box of stub : architecture is true;
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||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_config_tvalid,s_axis_config_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "dds_compiler_v6_0_18,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
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|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_ROM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_A">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">324ccc651779d6cd</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">0137cb81</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">45</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
BIN
Binary file not shown.
+744
@@ -0,0 +1,744 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:15:57 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hop_rom_sim_netlist.v
|
||||
// Design : hop_rom
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "hop_rom,blk_mem_gen_v8_4_3,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||
(* NotValidForBitStream *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||
(clka,
|
||||
addra,
|
||||
douta);
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [7:0]addra;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta;
|
||||
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
wire NLW_U0_dbiterr_UNCONNECTED;
|
||||
wire NLW_U0_rsta_busy_UNCONNECTED;
|
||||
wire NLW_U0_rstb_busy_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_arready_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_awready_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_rlast_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_wready_UNCONNECTED;
|
||||
wire NLW_U0_sbiterr_UNCONNECTED;
|
||||
wire [31:0]NLW_U0_doutb_UNCONNECTED;
|
||||
wire [7:0]NLW_U0_rdaddrecc_UNCONNECTED;
|
||||
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
|
||||
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
|
||||
wire [7:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
|
||||
wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED;
|
||||
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
|
||||
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
|
||||
|
||||
(* C_ADDRA_WIDTH = "8" *)
|
||||
(* C_ADDRB_WIDTH = "8" *)
|
||||
(* C_ALGORITHM = "1" *)
|
||||
(* C_AXI_ID_WIDTH = "4" *)
|
||||
(* C_AXI_SLAVE_TYPE = "0" *)
|
||||
(* C_AXI_TYPE = "1" *)
|
||||
(* C_BYTE_SIZE = "9" *)
|
||||
(* C_COMMON_CLK = "0" *)
|
||||
(* C_COUNT_18K_BRAM = "1" *)
|
||||
(* C_COUNT_36K_BRAM = "0" *)
|
||||
(* C_CTRL_ECC_ALGO = "NONE" *)
|
||||
(* C_DEFAULT_DATA = "0" *)
|
||||
(* C_DISABLE_WARN_BHV_COLL = "0" *)
|
||||
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
|
||||
(* C_ELABORATION_DIR = "./" *)
|
||||
(* C_ENABLE_32BIT_ADDRESS = "0" *)
|
||||
(* C_EN_DEEPSLEEP_PIN = "0" *)
|
||||
(* C_EN_ECC_PIPE = "0" *)
|
||||
(* C_EN_RDADDRA_CHG = "0" *)
|
||||
(* C_EN_RDADDRB_CHG = "0" *)
|
||||
(* C_EN_SAFETY_CKT = "0" *)
|
||||
(* C_EN_SHUTDOWN_PIN = "0" *)
|
||||
(* C_EN_SLEEP_PIN = "0" *)
|
||||
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.375199 mW" *)
|
||||
(* C_FAMILY = "kintex7" *)
|
||||
(* C_HAS_AXI_ID = "0" *)
|
||||
(* C_HAS_ENA = "0" *)
|
||||
(* C_HAS_ENB = "0" *)
|
||||
(* C_HAS_INJECTERR = "0" *)
|
||||
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
|
||||
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
|
||||
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
|
||||
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
|
||||
(* C_HAS_REGCEA = "0" *)
|
||||
(* C_HAS_REGCEB = "0" *)
|
||||
(* C_HAS_RSTA = "0" *)
|
||||
(* C_HAS_RSTB = "0" *)
|
||||
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
|
||||
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
|
||||
(* C_INITA_VAL = "0" *)
|
||||
(* C_INITB_VAL = "0" *)
|
||||
(* C_INIT_FILE = "hop_rom.mem" *)
|
||||
(* C_INIT_FILE_NAME = "hop_rom.mif" *)
|
||||
(* C_INTERFACE_TYPE = "0" *)
|
||||
(* C_LOAD_INIT_FILE = "1" *)
|
||||
(* C_MEM_TYPE = "3" *)
|
||||
(* C_MUX_PIPELINE_STAGES = "0" *)
|
||||
(* C_PRIM_TYPE = "1" *)
|
||||
(* C_READ_DEPTH_A = "256" *)
|
||||
(* C_READ_DEPTH_B = "256" *)
|
||||
(* C_READ_LATENCY_A = "1" *)
|
||||
(* C_READ_LATENCY_B = "1" *)
|
||||
(* C_READ_WIDTH_A = "32" *)
|
||||
(* C_READ_WIDTH_B = "32" *)
|
||||
(* C_RSTRAM_A = "0" *)
|
||||
(* C_RSTRAM_B = "0" *)
|
||||
(* C_RST_PRIORITY_A = "CE" *)
|
||||
(* C_RST_PRIORITY_B = "CE" *)
|
||||
(* C_SIM_COLLISION_CHECK = "ALL" *)
|
||||
(* C_USE_BRAM_BLOCK = "0" *)
|
||||
(* C_USE_BYTE_WEA = "0" *)
|
||||
(* C_USE_BYTE_WEB = "0" *)
|
||||
(* C_USE_DEFAULT_DATA = "0" *)
|
||||
(* C_USE_ECC = "0" *)
|
||||
(* C_USE_SOFTECC = "0" *)
|
||||
(* C_USE_URAM = "0" *)
|
||||
(* C_WEA_WIDTH = "1" *)
|
||||
(* C_WEB_WIDTH = "1" *)
|
||||
(* C_WRITE_DEPTH_A = "256" *)
|
||||
(* C_WRITE_DEPTH_B = "256" *)
|
||||
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
|
||||
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||
(* C_WRITE_WIDTH_A = "32" *)
|
||||
(* C_WRITE_WIDTH_B = "32" *)
|
||||
(* C_XDEVICEFAMILY = "kintex7" *)
|
||||
(* downgradeipidentifiedwarnings = "yes" *)
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 U0
|
||||
(.addra(addra),
|
||||
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.clka(clka),
|
||||
.clkb(1'b0),
|
||||
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
|
||||
.deepsleep(1'b0),
|
||||
.dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.douta(douta),
|
||||
.doutb(NLW_U0_doutb_UNCONNECTED[31:0]),
|
||||
.eccpipece(1'b0),
|
||||
.ena(1'b0),
|
||||
.enb(1'b0),
|
||||
.injectdbiterr(1'b0),
|
||||
.injectsbiterr(1'b0),
|
||||
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[7:0]),
|
||||
.regcea(1'b0),
|
||||
.regceb(1'b0),
|
||||
.rsta(1'b0),
|
||||
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
|
||||
.rstb(1'b0),
|
||||
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
|
||||
.s_aclk(1'b0),
|
||||
.s_aresetn(1'b0),
|
||||
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_arburst({1'b0,1'b0}),
|
||||
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
|
||||
.s_axi_arsize({1'b0,1'b0,1'b0}),
|
||||
.s_axi_arvalid(1'b0),
|
||||
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_awburst({1'b0,1'b0}),
|
||||
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
|
||||
.s_axi_awsize({1'b0,1'b0,1'b0}),
|
||||
.s_axi_awvalid(1'b0),
|
||||
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
|
||||
.s_axi_bready(1'b0),
|
||||
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
|
||||
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
|
||||
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
|
||||
.s_axi_injectdbiterr(1'b0),
|
||||
.s_axi_injectsbiterr(1'b0),
|
||||
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[7:0]),
|
||||
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]),
|
||||
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
|
||||
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
|
||||
.s_axi_rready(1'b0),
|
||||
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
|
||||
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
|
||||
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
|
||||
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_wlast(1'b0),
|
||||
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
|
||||
.s_axi_wstrb(1'b0),
|
||||
.s_axi_wvalid(1'b0),
|
||||
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
|
||||
.shutdown(1'b0),
|
||||
.sleep(1'b0),
|
||||
.wea(1'b0),
|
||||
.web(1'b0));
|
||||
endmodule
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
|
||||
(douta,
|
||||
clka,
|
||||
addra);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta));
|
||||
endmodule
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
|
||||
(douta,
|
||||
clka,
|
||||
addra);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init \prim_init.ram
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta));
|
||||
endmodule
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
|
||||
(douta,
|
||||
clka,
|
||||
addra);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 ;
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
RAMB18E1 #(
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_00(256'h8707070886060607850505068404040583030304820202038101010280000001),
|
||||
.INIT_01(256'h8F0F0F108E0E0E0F8D0D0D0E8C0C0C0D8B0B0B0C8A0A0A0B8909090A88080809),
|
||||
.INIT_02(256'h9717171896161617951515169414141593131314921212139111111290101011),
|
||||
.INIT_03(256'h9F1F1F209E1E1E1F9D1D1D1E9C1C1C1D9B1B1B1C9A1A1A1B9919191A98181819),
|
||||
.INIT_04(256'hA7272728A6262627A5252526A4242425A3232324A2222223A1212122A0202021),
|
||||
.INIT_05(256'hAF2F2F30AE2E2E2FAD2D2D2EAC2C2C2DAB2B2B2CAA2A2A2BA929292AA8282829),
|
||||
.INIT_06(256'hB7373738B6363637B5353536B4343435B3333334B2323233B1313132B0303031),
|
||||
.INIT_07(256'hBF3F3F40BE3E3E3FBD3D3D3EBC3C3C3DBB3B3B3CBA3A3A3BB939393AB8383839),
|
||||
.INIT_08(256'hC7474748C6464647C5454546C4444445C3434344C2424243C1414142C0404041),
|
||||
.INIT_09(256'hCF4F4F50CE4E4E4FCD4D4D4ECC4C4C4DCB4B4B4CCA4A4A4BC949494AC8484849),
|
||||
.INIT_0A(256'hD7575758D6565657D5555556D4545455D3535354D2525253D1515152D0505051),
|
||||
.INIT_0B(256'hDF5F5F60DE5E5E5FDD5D5D5EDC5C5C5DDB5B5B5CDA5A5A5BD959595AD8585859),
|
||||
.INIT_0C(256'hE7676768E6666667E5656566E4646465E3636364E2626263E1616162E0606061),
|
||||
.INIT_0D(256'hEF6F6F70EE6E6E6FED6D6D6EEC6C6C6DEB6B6B6CEA6A6A6BE969696AE8686869),
|
||||
.INIT_0E(256'hF7777778F6767677F5757576F4747475F3737374F2727273F1717172F0707071),
|
||||
.INIT_0F(256'hFF7F7F80FE7E7E7FFD7D7D7EFC7C7C7DFB7B7B7CFA7A7A7BF979797AF8787879),
|
||||
.INIT_10(256'h0787878706868686058585850484848403838383028282820181818100808080),
|
||||
.INIT_11(256'h0F8F8F8F0E8E8E8E0D8D8D8D0C8C8C8C0B8B8B8B0A8A8A8A0989898908888888),
|
||||
.INIT_12(256'h1797979716969696159595951494949413939393129292921191919110909090),
|
||||
.INIT_13(256'h1F9F9F9F1E9E9E9E1D9D9D9D1C9C9C9C1B9B9B9B1A9A9A9A1999999918989898),
|
||||
.INIT_14(256'h27A7A7A726A6A6A625A5A5A524A4A4A423A3A3A322A2A2A221A1A1A120A0A0A0),
|
||||
.INIT_15(256'h2FAFAFAF2EAEAEAE2DADADAD2CACACAC2BABABAB2AAAAAAA29A9A9A928A8A8A8),
|
||||
.INIT_16(256'h37B7B7B736B6B6B635B5B5B534B4B4B433B3B3B332B2B2B231B1B1B130B0B0B0),
|
||||
.INIT_17(256'h3FBFBFBF3EBEBEBE3DBDBDBD3CBCBCBC3BBBBBBB3ABABABA39B9B9B938B8B8B8),
|
||||
.INIT_18(256'h47C7C7C746C6C6C645C5C5C544C4C4C443C3C3C342C2C2C241C1C1C140C0C0C0),
|
||||
.INIT_19(256'h4FCFCFCF4ECECECE4DCDCDCD4CCCCCCC4BCBCBCB4ACACACA49C9C9C948C8C8C8),
|
||||
.INIT_1A(256'h57D7D7D756D6D6D655D5D5D554D4D4D453D3D3D352D2D2D251D1D1D150D0D0D0),
|
||||
.INIT_1B(256'h5FDFDFDF5EDEDEDE5DDDDDDD5CDCDCDC5BDBDBDB5ADADADA59D9D9D958D8D8D8),
|
||||
.INIT_1C(256'h67E7E7E766E6E6E665E5E5E564E4E4E463E3E3E362E2E2E261E1E1E160E0E0E0),
|
||||
.INIT_1D(256'h6FEFEFEF6EEEEEEE6DEDEDED6CECECEC6BEBEBEB6AEAEAEA69E9E9E968E8E8E8),
|
||||
.INIT_1E(256'h77F7F7F776F6F6F675F5F5F574F4F4F473F3F3F372F2F2F271F1F1F170F0F0F0),
|
||||
.INIT_1F(256'h7FFFFFFF7EFEFEFE7DFDFDFD7CFCFCFC7BFBFBFB7AFAFAFA79F9F9F978F8F8F8),
|
||||
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_A(18'h00000),
|
||||
.INIT_B(18'h00000),
|
||||
.INIT_FILE("NONE"),
|
||||
.IS_CLKARDCLK_INVERTED(1'b0),
|
||||
.IS_CLKBWRCLK_INVERTED(1'b0),
|
||||
.IS_ENARDEN_INVERTED(1'b0),
|
||||
.IS_ENBWREN_INVERTED(1'b0),
|
||||
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
|
||||
.IS_RSTRAMB_INVERTED(1'b0),
|
||||
.IS_RSTREGARSTREG_INVERTED(1'b0),
|
||||
.IS_RSTREGB_INVERTED(1'b0),
|
||||
.RAM_MODE("TDP"),
|
||||
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
|
||||
.READ_WIDTH_A(18),
|
||||
.READ_WIDTH_B(18),
|
||||
.RSTREG_PRIORITY_A("REGCE"),
|
||||
.RSTREG_PRIORITY_B("REGCE"),
|
||||
.SIM_COLLISION_CHECK("ALL"),
|
||||
.SIM_DEVICE("7SERIES"),
|
||||
.SRVAL_A(18'h00000),
|
||||
.SRVAL_B(18'h00000),
|
||||
.WRITE_MODE_A("WRITE_FIRST"),
|
||||
.WRITE_MODE_B("WRITE_FIRST"),
|
||||
.WRITE_WIDTH_A(18),
|
||||
.WRITE_WIDTH_B(18))
|
||||
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram
|
||||
(.ADDRARDADDR({1'b0,addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.ADDRBWRADDR({1'b0,addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
|
||||
.CLKARDCLK(clka),
|
||||
.CLKBWRCLK(clka),
|
||||
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DIPADIP({1'b0,1'b0}),
|
||||
.DIPBDIP({1'b0,1'b0}),
|
||||
.DOADO(douta[15:0]),
|
||||
.DOBDO(douta[31:16]),
|
||||
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 }),
|
||||
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 }),
|
||||
.ENARDEN(1'b1),
|
||||
.ENBWREN(1'b1),
|
||||
.REGCEAREGCE(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.RSTRAMARSTRAM(1'b0),
|
||||
.RSTRAMB(1'b0),
|
||||
.RSTREGARSTREG(1'b0),
|
||||
.RSTREGB(1'b0),
|
||||
.WEA({1'b0,1'b0}),
|
||||
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
||||
endmodule
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
|
||||
(douta,
|
||||
clka,
|
||||
addra);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta));
|
||||
endmodule
|
||||
|
||||
(* C_ADDRA_WIDTH = "8" *) (* C_ADDRB_WIDTH = "8" *) (* C_ALGORITHM = "1" *)
|
||||
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
|
||||
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
|
||||
(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
|
||||
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
|
||||
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
|
||||
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
|
||||
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.375199 mW" *)
|
||||
(* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
|
||||
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
|
||||
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
|
||||
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
|
||||
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
|
||||
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "hop_rom.mem" *)
|
||||
(* C_INIT_FILE_NAME = "hop_rom.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
|
||||
(* C_MEM_TYPE = "3" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
|
||||
(* C_READ_DEPTH_A = "256" *) (* C_READ_DEPTH_B = "256" *) (* C_READ_LATENCY_A = "1" *)
|
||||
(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "32" *) (* C_READ_WIDTH_B = "32" *)
|
||||
(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *)
|
||||
(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *)
|
||||
(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *)
|
||||
(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *)
|
||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "256" *)
|
||||
(* C_WRITE_DEPTH_B = "256" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||
(* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *) (* C_XDEVICEFAMILY = "kintex7" *)
|
||||
(* downgradeipidentifiedwarnings = "yes" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3
|
||||
(clka,
|
||||
rsta,
|
||||
ena,
|
||||
regcea,
|
||||
wea,
|
||||
addra,
|
||||
dina,
|
||||
douta,
|
||||
clkb,
|
||||
rstb,
|
||||
enb,
|
||||
regceb,
|
||||
web,
|
||||
addrb,
|
||||
dinb,
|
||||
doutb,
|
||||
injectsbiterr,
|
||||
injectdbiterr,
|
||||
eccpipece,
|
||||
sbiterr,
|
||||
dbiterr,
|
||||
rdaddrecc,
|
||||
sleep,
|
||||
deepsleep,
|
||||
shutdown,
|
||||
rsta_busy,
|
||||
rstb_busy,
|
||||
s_aclk,
|
||||
s_aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
s_axi_injectsbiterr,
|
||||
s_axi_injectdbiterr,
|
||||
s_axi_sbiterr,
|
||||
s_axi_dbiterr,
|
||||
s_axi_rdaddrecc);
|
||||
input clka;
|
||||
input rsta;
|
||||
input ena;
|
||||
input regcea;
|
||||
input [0:0]wea;
|
||||
input [7:0]addra;
|
||||
input [31:0]dina;
|
||||
output [31:0]douta;
|
||||
input clkb;
|
||||
input rstb;
|
||||
input enb;
|
||||
input regceb;
|
||||
input [0:0]web;
|
||||
input [7:0]addrb;
|
||||
input [31:0]dinb;
|
||||
output [31:0]doutb;
|
||||
input injectsbiterr;
|
||||
input injectdbiterr;
|
||||
input eccpipece;
|
||||
output sbiterr;
|
||||
output dbiterr;
|
||||
output [7:0]rdaddrecc;
|
||||
input sleep;
|
||||
input deepsleep;
|
||||
input shutdown;
|
||||
output rsta_busy;
|
||||
output rstb_busy;
|
||||
input s_aclk;
|
||||
input s_aresetn;
|
||||
input [3:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [7:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [0:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [3:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [3:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [7:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [3:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
input s_axi_injectsbiterr;
|
||||
input s_axi_injectdbiterr;
|
||||
output s_axi_sbiterr;
|
||||
output s_axi_dbiterr;
|
||||
output [7:0]s_axi_rdaddrecc;
|
||||
|
||||
wire \<const0> ;
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
|
||||
assign dbiterr = \<const0> ;
|
||||
assign doutb[31] = \<const0> ;
|
||||
assign doutb[30] = \<const0> ;
|
||||
assign doutb[29] = \<const0> ;
|
||||
assign doutb[28] = \<const0> ;
|
||||
assign doutb[27] = \<const0> ;
|
||||
assign doutb[26] = \<const0> ;
|
||||
assign doutb[25] = \<const0> ;
|
||||
assign doutb[24] = \<const0> ;
|
||||
assign doutb[23] = \<const0> ;
|
||||
assign doutb[22] = \<const0> ;
|
||||
assign doutb[21] = \<const0> ;
|
||||
assign doutb[20] = \<const0> ;
|
||||
assign doutb[19] = \<const0> ;
|
||||
assign doutb[18] = \<const0> ;
|
||||
assign doutb[17] = \<const0> ;
|
||||
assign doutb[16] = \<const0> ;
|
||||
assign doutb[15] = \<const0> ;
|
||||
assign doutb[14] = \<const0> ;
|
||||
assign doutb[13] = \<const0> ;
|
||||
assign doutb[12] = \<const0> ;
|
||||
assign doutb[11] = \<const0> ;
|
||||
assign doutb[10] = \<const0> ;
|
||||
assign doutb[9] = \<const0> ;
|
||||
assign doutb[8] = \<const0> ;
|
||||
assign doutb[7] = \<const0> ;
|
||||
assign doutb[6] = \<const0> ;
|
||||
assign doutb[5] = \<const0> ;
|
||||
assign doutb[4] = \<const0> ;
|
||||
assign doutb[3] = \<const0> ;
|
||||
assign doutb[2] = \<const0> ;
|
||||
assign doutb[1] = \<const0> ;
|
||||
assign doutb[0] = \<const0> ;
|
||||
assign rdaddrecc[7] = \<const0> ;
|
||||
assign rdaddrecc[6] = \<const0> ;
|
||||
assign rdaddrecc[5] = \<const0> ;
|
||||
assign rdaddrecc[4] = \<const0> ;
|
||||
assign rdaddrecc[3] = \<const0> ;
|
||||
assign rdaddrecc[2] = \<const0> ;
|
||||
assign rdaddrecc[1] = \<const0> ;
|
||||
assign rdaddrecc[0] = \<const0> ;
|
||||
assign rsta_busy = \<const0> ;
|
||||
assign rstb_busy = \<const0> ;
|
||||
assign s_axi_arready = \<const0> ;
|
||||
assign s_axi_awready = \<const0> ;
|
||||
assign s_axi_bid[3] = \<const0> ;
|
||||
assign s_axi_bid[2] = \<const0> ;
|
||||
assign s_axi_bid[1] = \<const0> ;
|
||||
assign s_axi_bid[0] = \<const0> ;
|
||||
assign s_axi_bresp[1] = \<const0> ;
|
||||
assign s_axi_bresp[0] = \<const0> ;
|
||||
assign s_axi_bvalid = \<const0> ;
|
||||
assign s_axi_dbiterr = \<const0> ;
|
||||
assign s_axi_rdaddrecc[7] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[6] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[5] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[4] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[3] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[2] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[1] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[0] = \<const0> ;
|
||||
assign s_axi_rdata[31] = \<const0> ;
|
||||
assign s_axi_rdata[30] = \<const0> ;
|
||||
assign s_axi_rdata[29] = \<const0> ;
|
||||
assign s_axi_rdata[28] = \<const0> ;
|
||||
assign s_axi_rdata[27] = \<const0> ;
|
||||
assign s_axi_rdata[26] = \<const0> ;
|
||||
assign s_axi_rdata[25] = \<const0> ;
|
||||
assign s_axi_rdata[24] = \<const0> ;
|
||||
assign s_axi_rdata[23] = \<const0> ;
|
||||
assign s_axi_rdata[22] = \<const0> ;
|
||||
assign s_axi_rdata[21] = \<const0> ;
|
||||
assign s_axi_rdata[20] = \<const0> ;
|
||||
assign s_axi_rdata[19] = \<const0> ;
|
||||
assign s_axi_rdata[18] = \<const0> ;
|
||||
assign s_axi_rdata[17] = \<const0> ;
|
||||
assign s_axi_rdata[16] = \<const0> ;
|
||||
assign s_axi_rdata[15] = \<const0> ;
|
||||
assign s_axi_rdata[14] = \<const0> ;
|
||||
assign s_axi_rdata[13] = \<const0> ;
|
||||
assign s_axi_rdata[12] = \<const0> ;
|
||||
assign s_axi_rdata[11] = \<const0> ;
|
||||
assign s_axi_rdata[10] = \<const0> ;
|
||||
assign s_axi_rdata[9] = \<const0> ;
|
||||
assign s_axi_rdata[8] = \<const0> ;
|
||||
assign s_axi_rdata[7] = \<const0> ;
|
||||
assign s_axi_rdata[6] = \<const0> ;
|
||||
assign s_axi_rdata[5] = \<const0> ;
|
||||
assign s_axi_rdata[4] = \<const0> ;
|
||||
assign s_axi_rdata[3] = \<const0> ;
|
||||
assign s_axi_rdata[2] = \<const0> ;
|
||||
assign s_axi_rdata[1] = \<const0> ;
|
||||
assign s_axi_rdata[0] = \<const0> ;
|
||||
assign s_axi_rid[3] = \<const0> ;
|
||||
assign s_axi_rid[2] = \<const0> ;
|
||||
assign s_axi_rid[1] = \<const0> ;
|
||||
assign s_axi_rid[0] = \<const0> ;
|
||||
assign s_axi_rlast = \<const0> ;
|
||||
assign s_axi_rresp[1] = \<const0> ;
|
||||
assign s_axi_rresp[0] = \<const0> ;
|
||||
assign s_axi_rvalid = \<const0> ;
|
||||
assign s_axi_sbiterr = \<const0> ;
|
||||
assign s_axi_wready = \<const0> ;
|
||||
assign sbiterr = \<const0> ;
|
||||
GND GND
|
||||
(.G(\<const0> ));
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3_synth inst_blk_mem_gen
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta));
|
||||
endmodule
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3_synth
|
||||
(douta,
|
||||
clka,
|
||||
addra);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+857
@@ -0,0 +1,857 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:15:57 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hop_rom_sim_netlist.vhdl
|
||||
-- Design : hop_rom
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
|
||||
attribute box_type : string;
|
||||
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
|
||||
begin
|
||||
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
|
||||
generic map(
|
||||
DOA_REG => 0,
|
||||
DOB_REG => 0,
|
||||
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_00 => X"8707070886060607850505068404040583030304820202038101010280000001",
|
||||
INIT_01 => X"8F0F0F108E0E0E0F8D0D0D0E8C0C0C0D8B0B0B0C8A0A0A0B8909090A88080809",
|
||||
INIT_02 => X"9717171896161617951515169414141593131314921212139111111290101011",
|
||||
INIT_03 => X"9F1F1F209E1E1E1F9D1D1D1E9C1C1C1D9B1B1B1C9A1A1A1B9919191A98181819",
|
||||
INIT_04 => X"A7272728A6262627A5252526A4242425A3232324A2222223A1212122A0202021",
|
||||
INIT_05 => X"AF2F2F30AE2E2E2FAD2D2D2EAC2C2C2DAB2B2B2CAA2A2A2BA929292AA8282829",
|
||||
INIT_06 => X"B7373738B6363637B5353536B4343435B3333334B2323233B1313132B0303031",
|
||||
INIT_07 => X"BF3F3F40BE3E3E3FBD3D3D3EBC3C3C3DBB3B3B3CBA3A3A3BB939393AB8383839",
|
||||
INIT_08 => X"C7474748C6464647C5454546C4444445C3434344C2424243C1414142C0404041",
|
||||
INIT_09 => X"CF4F4F50CE4E4E4FCD4D4D4ECC4C4C4DCB4B4B4CCA4A4A4BC949494AC8484849",
|
||||
INIT_0A => X"D7575758D6565657D5555556D4545455D3535354D2525253D1515152D0505051",
|
||||
INIT_0B => X"DF5F5F60DE5E5E5FDD5D5D5EDC5C5C5DDB5B5B5CDA5A5A5BD959595AD8585859",
|
||||
INIT_0C => X"E7676768E6666667E5656566E4646465E3636364E2626263E1616162E0606061",
|
||||
INIT_0D => X"EF6F6F70EE6E6E6FED6D6D6EEC6C6C6DEB6B6B6CEA6A6A6BE969696AE8686869",
|
||||
INIT_0E => X"F7777778F6767677F5757576F4747475F3737374F2727273F1717172F0707071",
|
||||
INIT_0F => X"FF7F7F80FE7E7E7FFD7D7D7EFC7C7C7DFB7B7B7CFA7A7A7BF979797AF8787879",
|
||||
INIT_10 => X"0787878706868686058585850484848403838383028282820181818100808080",
|
||||
INIT_11 => X"0F8F8F8F0E8E8E8E0D8D8D8D0C8C8C8C0B8B8B8B0A8A8A8A0989898908888888",
|
||||
INIT_12 => X"1797979716969696159595951494949413939393129292921191919110909090",
|
||||
INIT_13 => X"1F9F9F9F1E9E9E9E1D9D9D9D1C9C9C9C1B9B9B9B1A9A9A9A1999999918989898",
|
||||
INIT_14 => X"27A7A7A726A6A6A625A5A5A524A4A4A423A3A3A322A2A2A221A1A1A120A0A0A0",
|
||||
INIT_15 => X"2FAFAFAF2EAEAEAE2DADADAD2CACACAC2BABABAB2AAAAAAA29A9A9A928A8A8A8",
|
||||
INIT_16 => X"37B7B7B736B6B6B635B5B5B534B4B4B433B3B3B332B2B2B231B1B1B130B0B0B0",
|
||||
INIT_17 => X"3FBFBFBF3EBEBEBE3DBDBDBD3CBCBCBC3BBBBBBB3ABABABA39B9B9B938B8B8B8",
|
||||
INIT_18 => X"47C7C7C746C6C6C645C5C5C544C4C4C443C3C3C342C2C2C241C1C1C140C0C0C0",
|
||||
INIT_19 => X"4FCFCFCF4ECECECE4DCDCDCD4CCCCCCC4BCBCBCB4ACACACA49C9C9C948C8C8C8",
|
||||
INIT_1A => X"57D7D7D756D6D6D655D5D5D554D4D4D453D3D3D352D2D2D251D1D1D150D0D0D0",
|
||||
INIT_1B => X"5FDFDFDF5EDEDEDE5DDDDDDD5CDCDCDC5BDBDBDB5ADADADA59D9D9D958D8D8D8",
|
||||
INIT_1C => X"67E7E7E766E6E6E665E5E5E564E4E4E463E3E3E362E2E2E261E1E1E160E0E0E0",
|
||||
INIT_1D => X"6FEFEFEF6EEEEEEE6DEDEDED6CECECEC6BEBEBEB6AEAEAEA69E9E9E968E8E8E8",
|
||||
INIT_1E => X"77F7F7F776F6F6F675F5F5F574F4F4F473F3F3F372F2F2F271F1F1F170F0F0F0",
|
||||
INIT_1F => X"7FFFFFFF7EFEFEFE7DFDFDFD7CFCFCFC7BFBFBFB7AFAFAFA79F9F9F978F8F8F8",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_A => X"00000",
|
||||
INIT_B => X"00000",
|
||||
INIT_FILE => "NONE",
|
||||
IS_CLKARDCLK_INVERTED => '0',
|
||||
IS_CLKBWRCLK_INVERTED => '0',
|
||||
IS_ENARDEN_INVERTED => '0',
|
||||
IS_ENBWREN_INVERTED => '0',
|
||||
IS_RSTRAMARSTRAM_INVERTED => '0',
|
||||
IS_RSTRAMB_INVERTED => '0',
|
||||
IS_RSTREGARSTREG_INVERTED => '0',
|
||||
IS_RSTREGB_INVERTED => '0',
|
||||
RAM_MODE => "TDP",
|
||||
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
|
||||
READ_WIDTH_A => 18,
|
||||
READ_WIDTH_B => 18,
|
||||
RSTREG_PRIORITY_A => "REGCE",
|
||||
RSTREG_PRIORITY_B => "REGCE",
|
||||
SIM_COLLISION_CHECK => "ALL",
|
||||
SIM_DEVICE => "7SERIES",
|
||||
SRVAL_A => X"00000",
|
||||
SRVAL_B => X"00000",
|
||||
WRITE_MODE_A => "WRITE_FIRST",
|
||||
WRITE_MODE_B => "WRITE_FIRST",
|
||||
WRITE_WIDTH_A => 18,
|
||||
WRITE_WIDTH_B => 18
|
||||
)
|
||||
port map (
|
||||
ADDRARDADDR(13) => '0',
|
||||
ADDRARDADDR(12 downto 5) => addra(7 downto 0),
|
||||
ADDRARDADDR(4 downto 0) => B"00000",
|
||||
ADDRBWRADDR(13) => '0',
|
||||
ADDRBWRADDR(12 downto 5) => addra(7 downto 0),
|
||||
ADDRBWRADDR(4 downto 0) => B"10000",
|
||||
CLKARDCLK => clka,
|
||||
CLKBWRCLK => clka,
|
||||
DIADI(15 downto 0) => B"0000000000000000",
|
||||
DIBDI(15 downto 0) => B"0000000000000000",
|
||||
DIPADIP(1 downto 0) => B"00",
|
||||
DIPBDIP(1 downto 0) => B"00",
|
||||
DOADO(15 downto 0) => douta(15 downto 0),
|
||||
DOBDO(15 downto 0) => douta(31 downto 16),
|
||||
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\,
|
||||
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\,
|
||||
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\,
|
||||
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\,
|
||||
ENARDEN => '1',
|
||||
ENBWREN => '1',
|
||||
REGCEAREGCE => '0',
|
||||
REGCEB => '0',
|
||||
RSTRAMARSTRAM => '0',
|
||||
RSTRAMB => '0',
|
||||
RSTREGARSTREG => '0',
|
||||
RSTREGB => '0',
|
||||
WEA(1 downto 0) => B"00",
|
||||
WEBWE(3 downto 0) => B"0000"
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
|
||||
begin
|
||||
\prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
|
||||
port map (
|
||||
addra(7 downto 0) => addra(7 downto 0),
|
||||
clka => clka,
|
||||
douta(31 downto 0) => douta(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
|
||||
begin
|
||||
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
|
||||
port map (
|
||||
addra(7 downto 0) => addra(7 downto 0),
|
||||
clka => clka,
|
||||
douta(31 downto 0) => douta(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
|
||||
begin
|
||||
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
|
||||
port map (
|
||||
addra(7 downto 0) => addra(7 downto 0),
|
||||
clka => clka,
|
||||
douta(31 downto 0) => douta(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3_synth is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3_synth;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3_synth is
|
||||
begin
|
||||
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
|
||||
port map (
|
||||
addra(7 downto 0) => addra(7 downto 0),
|
||||
clka => clka,
|
||||
douta(31 downto 0) => douta(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 is
|
||||
port (
|
||||
clka : in STD_LOGIC;
|
||||
rsta : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
regcea : in STD_LOGIC;
|
||||
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clkb : in STD_LOGIC;
|
||||
rstb : in STD_LOGIC;
|
||||
enb : in STD_LOGIC;
|
||||
regceb : in STD_LOGIC;
|
||||
web : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
injectsbiterr : in STD_LOGIC;
|
||||
injectdbiterr : in STD_LOGIC;
|
||||
eccpipece : in STD_LOGIC;
|
||||
sbiterr : out STD_LOGIC;
|
||||
dbiterr : out STD_LOGIC;
|
||||
rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sleep : in STD_LOGIC;
|
||||
deepsleep : in STD_LOGIC;
|
||||
shutdown : in STD_LOGIC;
|
||||
rsta_busy : out STD_LOGIC;
|
||||
rstb_busy : out STD_LOGIC;
|
||||
s_aclk : in STD_LOGIC;
|
||||
s_aresetn : in STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
s_axi_injectsbiterr : in STD_LOGIC;
|
||||
s_axi_injectdbiterr : in STD_LOGIC;
|
||||
s_axi_sbiterr : out STD_LOGIC;
|
||||
s_axi_dbiterr : out STD_LOGIC;
|
||||
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
attribute C_ADDRA_WIDTH : integer;
|
||||
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 8;
|
||||
attribute C_ADDRB_WIDTH : integer;
|
||||
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 8;
|
||||
attribute C_ALGORITHM : integer;
|
||||
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_AXI_ID_WIDTH : integer;
|
||||
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 4;
|
||||
attribute C_AXI_SLAVE_TYPE : integer;
|
||||
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_AXI_TYPE : integer;
|
||||
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_BYTE_SIZE : integer;
|
||||
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 9;
|
||||
attribute C_COMMON_CLK : integer;
|
||||
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_COUNT_18K_BRAM : string;
|
||||
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "1";
|
||||
attribute C_COUNT_36K_BRAM : string;
|
||||
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "0";
|
||||
attribute C_CTRL_ECC_ALGO : string;
|
||||
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "NONE";
|
||||
attribute C_DEFAULT_DATA : string;
|
||||
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "0";
|
||||
attribute C_DISABLE_WARN_BHV_COLL : integer;
|
||||
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE : integer;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_ELABORATION_DIR : string;
|
||||
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "./";
|
||||
attribute C_ENABLE_32BIT_ADDRESS : integer;
|
||||
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_DEEPSLEEP_PIN : integer;
|
||||
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_ECC_PIPE : integer;
|
||||
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_RDADDRA_CHG : integer;
|
||||
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_RDADDRB_CHG : integer;
|
||||
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_SAFETY_CKT : integer;
|
||||
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_SHUTDOWN_PIN : integer;
|
||||
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_SLEEP_PIN : integer;
|
||||
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EST_POWER_SUMMARY : string;
|
||||
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "Estimated Power for IP : 3.375199 mW";
|
||||
attribute C_FAMILY : string;
|
||||
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "kintex7";
|
||||
attribute C_HAS_AXI_ID : integer;
|
||||
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_ENA : integer;
|
||||
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_ENB : integer;
|
||||
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_INJECTERR : integer;
|
||||
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_REGCEA : integer;
|
||||
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_REGCEB : integer;
|
||||
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_RSTA : integer;
|
||||
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_RSTB : integer;
|
||||
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_INITA_VAL : string;
|
||||
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "0";
|
||||
attribute C_INITB_VAL : string;
|
||||
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "0";
|
||||
attribute C_INIT_FILE : string;
|
||||
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "hop_rom.mem";
|
||||
attribute C_INIT_FILE_NAME : string;
|
||||
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "hop_rom.mif";
|
||||
attribute C_INTERFACE_TYPE : integer;
|
||||
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_LOAD_INIT_FILE : integer;
|
||||
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_MEM_TYPE : integer;
|
||||
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 3;
|
||||
attribute C_MUX_PIPELINE_STAGES : integer;
|
||||
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_PRIM_TYPE : integer;
|
||||
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_READ_DEPTH_A : integer;
|
||||
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 256;
|
||||
attribute C_READ_DEPTH_B : integer;
|
||||
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 256;
|
||||
attribute C_READ_LATENCY_A : integer;
|
||||
attribute C_READ_LATENCY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_READ_LATENCY_B : integer;
|
||||
attribute C_READ_LATENCY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_READ_WIDTH_A : integer;
|
||||
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 32;
|
||||
attribute C_READ_WIDTH_B : integer;
|
||||
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 32;
|
||||
attribute C_RSTRAM_A : integer;
|
||||
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_RSTRAM_B : integer;
|
||||
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_RST_PRIORITY_A : string;
|
||||
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "CE";
|
||||
attribute C_RST_PRIORITY_B : string;
|
||||
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "CE";
|
||||
attribute C_SIM_COLLISION_CHECK : string;
|
||||
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "ALL";
|
||||
attribute C_USE_BRAM_BLOCK : integer;
|
||||
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_BYTE_WEA : integer;
|
||||
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_BYTE_WEB : integer;
|
||||
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_DEFAULT_DATA : integer;
|
||||
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_ECC : integer;
|
||||
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_SOFTECC : integer;
|
||||
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_URAM : integer;
|
||||
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_WEA_WIDTH : integer;
|
||||
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_WEB_WIDTH : integer;
|
||||
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_WRITE_DEPTH_A : integer;
|
||||
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 256;
|
||||
attribute C_WRITE_DEPTH_B : integer;
|
||||
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 256;
|
||||
attribute C_WRITE_MODE_A : string;
|
||||
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST";
|
||||
attribute C_WRITE_MODE_B : string;
|
||||
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST";
|
||||
attribute C_WRITE_WIDTH_A : integer;
|
||||
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 32;
|
||||
attribute C_WRITE_WIDTH_B : integer;
|
||||
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 32;
|
||||
attribute C_XDEVICEFAMILY : string;
|
||||
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "kintex7";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "yes";
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 is
|
||||
signal \<const0>\ : STD_LOGIC;
|
||||
begin
|
||||
dbiterr <= \<const0>\;
|
||||
doutb(31) <= \<const0>\;
|
||||
doutb(30) <= \<const0>\;
|
||||
doutb(29) <= \<const0>\;
|
||||
doutb(28) <= \<const0>\;
|
||||
doutb(27) <= \<const0>\;
|
||||
doutb(26) <= \<const0>\;
|
||||
doutb(25) <= \<const0>\;
|
||||
doutb(24) <= \<const0>\;
|
||||
doutb(23) <= \<const0>\;
|
||||
doutb(22) <= \<const0>\;
|
||||
doutb(21) <= \<const0>\;
|
||||
doutb(20) <= \<const0>\;
|
||||
doutb(19) <= \<const0>\;
|
||||
doutb(18) <= \<const0>\;
|
||||
doutb(17) <= \<const0>\;
|
||||
doutb(16) <= \<const0>\;
|
||||
doutb(15) <= \<const0>\;
|
||||
doutb(14) <= \<const0>\;
|
||||
doutb(13) <= \<const0>\;
|
||||
doutb(12) <= \<const0>\;
|
||||
doutb(11) <= \<const0>\;
|
||||
doutb(10) <= \<const0>\;
|
||||
doutb(9) <= \<const0>\;
|
||||
doutb(8) <= \<const0>\;
|
||||
doutb(7) <= \<const0>\;
|
||||
doutb(6) <= \<const0>\;
|
||||
doutb(5) <= \<const0>\;
|
||||
doutb(4) <= \<const0>\;
|
||||
doutb(3) <= \<const0>\;
|
||||
doutb(2) <= \<const0>\;
|
||||
doutb(1) <= \<const0>\;
|
||||
doutb(0) <= \<const0>\;
|
||||
rdaddrecc(7) <= \<const0>\;
|
||||
rdaddrecc(6) <= \<const0>\;
|
||||
rdaddrecc(5) <= \<const0>\;
|
||||
rdaddrecc(4) <= \<const0>\;
|
||||
rdaddrecc(3) <= \<const0>\;
|
||||
rdaddrecc(2) <= \<const0>\;
|
||||
rdaddrecc(1) <= \<const0>\;
|
||||
rdaddrecc(0) <= \<const0>\;
|
||||
rsta_busy <= \<const0>\;
|
||||
rstb_busy <= \<const0>\;
|
||||
s_axi_arready <= \<const0>\;
|
||||
s_axi_awready <= \<const0>\;
|
||||
s_axi_bid(3) <= \<const0>\;
|
||||
s_axi_bid(2) <= \<const0>\;
|
||||
s_axi_bid(1) <= \<const0>\;
|
||||
s_axi_bid(0) <= \<const0>\;
|
||||
s_axi_bresp(1) <= \<const0>\;
|
||||
s_axi_bresp(0) <= \<const0>\;
|
||||
s_axi_bvalid <= \<const0>\;
|
||||
s_axi_dbiterr <= \<const0>\;
|
||||
s_axi_rdaddrecc(7) <= \<const0>\;
|
||||
s_axi_rdaddrecc(6) <= \<const0>\;
|
||||
s_axi_rdaddrecc(5) <= \<const0>\;
|
||||
s_axi_rdaddrecc(4) <= \<const0>\;
|
||||
s_axi_rdaddrecc(3) <= \<const0>\;
|
||||
s_axi_rdaddrecc(2) <= \<const0>\;
|
||||
s_axi_rdaddrecc(1) <= \<const0>\;
|
||||
s_axi_rdaddrecc(0) <= \<const0>\;
|
||||
s_axi_rdata(31) <= \<const0>\;
|
||||
s_axi_rdata(30) <= \<const0>\;
|
||||
s_axi_rdata(29) <= \<const0>\;
|
||||
s_axi_rdata(28) <= \<const0>\;
|
||||
s_axi_rdata(27) <= \<const0>\;
|
||||
s_axi_rdata(26) <= \<const0>\;
|
||||
s_axi_rdata(25) <= \<const0>\;
|
||||
s_axi_rdata(24) <= \<const0>\;
|
||||
s_axi_rdata(23) <= \<const0>\;
|
||||
s_axi_rdata(22) <= \<const0>\;
|
||||
s_axi_rdata(21) <= \<const0>\;
|
||||
s_axi_rdata(20) <= \<const0>\;
|
||||
s_axi_rdata(19) <= \<const0>\;
|
||||
s_axi_rdata(18) <= \<const0>\;
|
||||
s_axi_rdata(17) <= \<const0>\;
|
||||
s_axi_rdata(16) <= \<const0>\;
|
||||
s_axi_rdata(15) <= \<const0>\;
|
||||
s_axi_rdata(14) <= \<const0>\;
|
||||
s_axi_rdata(13) <= \<const0>\;
|
||||
s_axi_rdata(12) <= \<const0>\;
|
||||
s_axi_rdata(11) <= \<const0>\;
|
||||
s_axi_rdata(10) <= \<const0>\;
|
||||
s_axi_rdata(9) <= \<const0>\;
|
||||
s_axi_rdata(8) <= \<const0>\;
|
||||
s_axi_rdata(7) <= \<const0>\;
|
||||
s_axi_rdata(6) <= \<const0>\;
|
||||
s_axi_rdata(5) <= \<const0>\;
|
||||
s_axi_rdata(4) <= \<const0>\;
|
||||
s_axi_rdata(3) <= \<const0>\;
|
||||
s_axi_rdata(2) <= \<const0>\;
|
||||
s_axi_rdata(1) <= \<const0>\;
|
||||
s_axi_rdata(0) <= \<const0>\;
|
||||
s_axi_rid(3) <= \<const0>\;
|
||||
s_axi_rid(2) <= \<const0>\;
|
||||
s_axi_rid(1) <= \<const0>\;
|
||||
s_axi_rid(0) <= \<const0>\;
|
||||
s_axi_rlast <= \<const0>\;
|
||||
s_axi_rresp(1) <= \<const0>\;
|
||||
s_axi_rresp(0) <= \<const0>\;
|
||||
s_axi_rvalid <= \<const0>\;
|
||||
s_axi_sbiterr <= \<const0>\;
|
||||
s_axi_wready <= \<const0>\;
|
||||
sbiterr <= \<const0>\;
|
||||
GND: unisim.vcomponents.GND
|
||||
port map (
|
||||
G => \<const0>\
|
||||
);
|
||||
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3_synth
|
||||
port map (
|
||||
addra(7 downto 0) => addra(7 downto 0),
|
||||
clka => clka,
|
||||
douta(31 downto 0) => douta(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "hop_rom,blk_mem_gen_v8_4_3,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute C_ADDRA_WIDTH : integer;
|
||||
attribute C_ADDRA_WIDTH of U0 : label is 8;
|
||||
attribute C_ADDRB_WIDTH : integer;
|
||||
attribute C_ADDRB_WIDTH of U0 : label is 8;
|
||||
attribute C_ALGORITHM : integer;
|
||||
attribute C_ALGORITHM of U0 : label is 1;
|
||||
attribute C_AXI_ID_WIDTH : integer;
|
||||
attribute C_AXI_ID_WIDTH of U0 : label is 4;
|
||||
attribute C_AXI_SLAVE_TYPE : integer;
|
||||
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
|
||||
attribute C_AXI_TYPE : integer;
|
||||
attribute C_AXI_TYPE of U0 : label is 1;
|
||||
attribute C_BYTE_SIZE : integer;
|
||||
attribute C_BYTE_SIZE of U0 : label is 9;
|
||||
attribute C_COMMON_CLK : integer;
|
||||
attribute C_COMMON_CLK of U0 : label is 0;
|
||||
attribute C_COUNT_18K_BRAM : string;
|
||||
attribute C_COUNT_18K_BRAM of U0 : label is "1";
|
||||
attribute C_COUNT_36K_BRAM : string;
|
||||
attribute C_COUNT_36K_BRAM of U0 : label is "0";
|
||||
attribute C_CTRL_ECC_ALGO : string;
|
||||
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
|
||||
attribute C_DEFAULT_DATA : string;
|
||||
attribute C_DEFAULT_DATA of U0 : label is "0";
|
||||
attribute C_DISABLE_WARN_BHV_COLL : integer;
|
||||
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE : integer;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
|
||||
attribute C_ELABORATION_DIR : string;
|
||||
attribute C_ELABORATION_DIR of U0 : label is "./";
|
||||
attribute C_ENABLE_32BIT_ADDRESS : integer;
|
||||
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
|
||||
attribute C_EN_DEEPSLEEP_PIN : integer;
|
||||
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
|
||||
attribute C_EN_ECC_PIPE : integer;
|
||||
attribute C_EN_ECC_PIPE of U0 : label is 0;
|
||||
attribute C_EN_RDADDRA_CHG : integer;
|
||||
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
|
||||
attribute C_EN_RDADDRB_CHG : integer;
|
||||
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
|
||||
attribute C_EN_SAFETY_CKT : integer;
|
||||
attribute C_EN_SAFETY_CKT of U0 : label is 0;
|
||||
attribute C_EN_SHUTDOWN_PIN : integer;
|
||||
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
|
||||
attribute C_EN_SLEEP_PIN : integer;
|
||||
attribute C_EN_SLEEP_PIN of U0 : label is 0;
|
||||
attribute C_EST_POWER_SUMMARY : string;
|
||||
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.375199 mW";
|
||||
attribute C_FAMILY : string;
|
||||
attribute C_FAMILY of U0 : label is "kintex7";
|
||||
attribute C_HAS_AXI_ID : integer;
|
||||
attribute C_HAS_AXI_ID of U0 : label is 0;
|
||||
attribute C_HAS_ENA : integer;
|
||||
attribute C_HAS_ENA of U0 : label is 0;
|
||||
attribute C_HAS_ENB : integer;
|
||||
attribute C_HAS_ENB of U0 : label is 0;
|
||||
attribute C_HAS_INJECTERR : integer;
|
||||
attribute C_HAS_INJECTERR of U0 : label is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
|
||||
attribute C_HAS_REGCEA : integer;
|
||||
attribute C_HAS_REGCEA of U0 : label is 0;
|
||||
attribute C_HAS_REGCEB : integer;
|
||||
attribute C_HAS_REGCEB of U0 : label is 0;
|
||||
attribute C_HAS_RSTA : integer;
|
||||
attribute C_HAS_RSTA of U0 : label is 0;
|
||||
attribute C_HAS_RSTB : integer;
|
||||
attribute C_HAS_RSTB of U0 : label is 0;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
|
||||
attribute C_INITA_VAL : string;
|
||||
attribute C_INITA_VAL of U0 : label is "0";
|
||||
attribute C_INITB_VAL : string;
|
||||
attribute C_INITB_VAL of U0 : label is "0";
|
||||
attribute C_INIT_FILE : string;
|
||||
attribute C_INIT_FILE of U0 : label is "hop_rom.mem";
|
||||
attribute C_INIT_FILE_NAME : string;
|
||||
attribute C_INIT_FILE_NAME of U0 : label is "hop_rom.mif";
|
||||
attribute C_INTERFACE_TYPE : integer;
|
||||
attribute C_INTERFACE_TYPE of U0 : label is 0;
|
||||
attribute C_LOAD_INIT_FILE : integer;
|
||||
attribute C_LOAD_INIT_FILE of U0 : label is 1;
|
||||
attribute C_MEM_TYPE : integer;
|
||||
attribute C_MEM_TYPE of U0 : label is 3;
|
||||
attribute C_MUX_PIPELINE_STAGES : integer;
|
||||
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
|
||||
attribute C_PRIM_TYPE : integer;
|
||||
attribute C_PRIM_TYPE of U0 : label is 1;
|
||||
attribute C_READ_DEPTH_A : integer;
|
||||
attribute C_READ_DEPTH_A of U0 : label is 256;
|
||||
attribute C_READ_DEPTH_B : integer;
|
||||
attribute C_READ_DEPTH_B of U0 : label is 256;
|
||||
attribute C_READ_LATENCY_A : integer;
|
||||
attribute C_READ_LATENCY_A of U0 : label is 1;
|
||||
attribute C_READ_LATENCY_B : integer;
|
||||
attribute C_READ_LATENCY_B of U0 : label is 1;
|
||||
attribute C_READ_WIDTH_A : integer;
|
||||
attribute C_READ_WIDTH_A of U0 : label is 32;
|
||||
attribute C_READ_WIDTH_B : integer;
|
||||
attribute C_READ_WIDTH_B of U0 : label is 32;
|
||||
attribute C_RSTRAM_A : integer;
|
||||
attribute C_RSTRAM_A of U0 : label is 0;
|
||||
attribute C_RSTRAM_B : integer;
|
||||
attribute C_RSTRAM_B of U0 : label is 0;
|
||||
attribute C_RST_PRIORITY_A : string;
|
||||
attribute C_RST_PRIORITY_A of U0 : label is "CE";
|
||||
attribute C_RST_PRIORITY_B : string;
|
||||
attribute C_RST_PRIORITY_B of U0 : label is "CE";
|
||||
attribute C_SIM_COLLISION_CHECK : string;
|
||||
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
|
||||
attribute C_USE_BRAM_BLOCK : integer;
|
||||
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
|
||||
attribute C_USE_BYTE_WEA : integer;
|
||||
attribute C_USE_BYTE_WEA of U0 : label is 0;
|
||||
attribute C_USE_BYTE_WEB : integer;
|
||||
attribute C_USE_BYTE_WEB of U0 : label is 0;
|
||||
attribute C_USE_DEFAULT_DATA : integer;
|
||||
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
|
||||
attribute C_USE_ECC : integer;
|
||||
attribute C_USE_ECC of U0 : label is 0;
|
||||
attribute C_USE_SOFTECC : integer;
|
||||
attribute C_USE_SOFTECC of U0 : label is 0;
|
||||
attribute C_USE_URAM : integer;
|
||||
attribute C_USE_URAM of U0 : label is 0;
|
||||
attribute C_WEA_WIDTH : integer;
|
||||
attribute C_WEA_WIDTH of U0 : label is 1;
|
||||
attribute C_WEB_WIDTH : integer;
|
||||
attribute C_WEB_WIDTH of U0 : label is 1;
|
||||
attribute C_WRITE_DEPTH_A : integer;
|
||||
attribute C_WRITE_DEPTH_A of U0 : label is 256;
|
||||
attribute C_WRITE_DEPTH_B : integer;
|
||||
attribute C_WRITE_DEPTH_B of U0 : label is 256;
|
||||
attribute C_WRITE_MODE_A : string;
|
||||
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
|
||||
attribute C_WRITE_MODE_B : string;
|
||||
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
|
||||
attribute C_WRITE_WIDTH_A : integer;
|
||||
attribute C_WRITE_WIDTH_A of U0 : label is 32;
|
||||
attribute C_WRITE_WIDTH_B : integer;
|
||||
attribute C_WRITE_WIDTH_B of U0 : label is 32;
|
||||
attribute C_XDEVICEFAMILY : string;
|
||||
attribute C_XDEVICEFAMILY of U0 : label is "kintex7";
|
||||
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
|
||||
attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
begin
|
||||
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3
|
||||
port map (
|
||||
addra(7 downto 0) => addra(7 downto 0),
|
||||
addrb(7 downto 0) => B"00000000",
|
||||
clka => clka,
|
||||
clkb => '0',
|
||||
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
|
||||
deepsleep => '0',
|
||||
dina(31 downto 0) => B"00000000000000000000000000000000",
|
||||
dinb(31 downto 0) => B"00000000000000000000000000000000",
|
||||
douta(31 downto 0) => douta(31 downto 0),
|
||||
doutb(31 downto 0) => NLW_U0_doutb_UNCONNECTED(31 downto 0),
|
||||
eccpipece => '0',
|
||||
ena => '0',
|
||||
enb => '0',
|
||||
injectdbiterr => '0',
|
||||
injectsbiterr => '0',
|
||||
rdaddrecc(7 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(7 downto 0),
|
||||
regcea => '0',
|
||||
regceb => '0',
|
||||
rsta => '0',
|
||||
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
|
||||
rstb => '0',
|
||||
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
|
||||
s_aclk => '0',
|
||||
s_aresetn => '0',
|
||||
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
|
||||
s_axi_arburst(1 downto 0) => B"00",
|
||||
s_axi_arid(3 downto 0) => B"0000",
|
||||
s_axi_arlen(7 downto 0) => B"00000000",
|
||||
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
|
||||
s_axi_arsize(2 downto 0) => B"000",
|
||||
s_axi_arvalid => '0',
|
||||
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
|
||||
s_axi_awburst(1 downto 0) => B"00",
|
||||
s_axi_awid(3 downto 0) => B"0000",
|
||||
s_axi_awlen(7 downto 0) => B"00000000",
|
||||
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
|
||||
s_axi_awsize(2 downto 0) => B"000",
|
||||
s_axi_awvalid => '0',
|
||||
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
|
||||
s_axi_bready => '0',
|
||||
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
|
||||
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
|
||||
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
|
||||
s_axi_injectdbiterr => '0',
|
||||
s_axi_injectsbiterr => '0',
|
||||
s_axi_rdaddrecc(7 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(7 downto 0),
|
||||
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
|
||||
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
|
||||
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
|
||||
s_axi_rready => '0',
|
||||
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
|
||||
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
|
||||
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
|
||||
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
|
||||
s_axi_wlast => '0',
|
||||
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
|
||||
s_axi_wstrb(0) => '0',
|
||||
s_axi_wvalid => '0',
|
||||
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
|
||||
shutdown => '0',
|
||||
sleep => '0',
|
||||
wea(0) => '0',
|
||||
web(0) => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:15:57 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hop_rom_stub.v
|
||||
// Design : hop_rom
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clka,addra[7:0],douta[31:0]" */;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
output [31:0]douta;
|
||||
endmodule
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:15:57 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hop_rom_stub.vhdl
|
||||
-- Design : hop_rom
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clka,addra[7:0],douta[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>5b4a2e3a64350b28</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>cmpy_18x8</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cmpy" spirit:version="6.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">10000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.APortWidth">18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATUSERWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BPortWidth">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BTUSERWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRLTUSERWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">cmpy_18x8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FlowControl">NonBlocking</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasATLAST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasATUSER">false</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LatencyConfig">Automatic</spirit:configurableElementValue>
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|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
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|
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|
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
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BIN
Binary file not shown.
+1995
File diff suppressed because it is too large
Load Diff
+2603
File diff suppressed because it is too large
Load Diff
+27
@@ -0,0 +1,27 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:15:41 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x8_stub.v
|
||||
// Design : cmpy_18x8
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_a_tvalid, s_axis_a_tdata,
|
||||
s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]" */;
|
||||
input aclk;
|
||||
input s_axis_a_tvalid;
|
||||
input [47:0]s_axis_a_tdata;
|
||||
input s_axis_b_tvalid;
|
||||
input [15:0]s_axis_b_tdata;
|
||||
output m_axis_dout_tvalid;
|
||||
output [63:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:15:41 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x8_stub.vhdl
|
||||
-- Design : cmpy_18x8
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_a_tvalid : in STD_LOGIC;
|
||||
s_axis_a_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||
s_axis_b_tvalid : in STD_LOGIC;
|
||||
s_axis_b_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+107
@@ -0,0 +1,107 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
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<spirit:name>caa0dad6b4ff1e98</spirit:name>
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<spirit:version>0</spirit:version>
|
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<spirit:componentInstances>
|
||||
<spirit:componentInstance>
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<spirit:instanceName>hrc_64_12_025</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fir_compiler" spirit:version="7.2"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BestPrecision">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Blank_Output">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Channel_Sequence">Basic</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Buffer_Type">Automatic</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_from_Spec">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">caa0dad6b4ff1e98</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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</spirit:configurableElementValues>
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</spirit:design>
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BIN
Binary file not shown.
+6448
File diff suppressed because it is too large
Load Diff
+8724
File diff suppressed because it is too large
Load Diff
+26
@@ -0,0 +1,26 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:15:41 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hrc_64_12_025_stub.v
|
||||
// Design : hrc_64_12_025
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_data_tvalid, s_axis_data_tready,
|
||||
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
|
||||
input aclk;
|
||||
input s_axis_data_tvalid;
|
||||
output s_axis_data_tready;
|
||||
input [7:0]s_axis_data_tdata;
|
||||
output m_axis_data_tvalid;
|
||||
output [23:0]m_axis_data_tdata;
|
||||
endmodule
|
||||
+35
@@ -0,0 +1,35 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:15:41 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hrc_64_12_025_stub.vhdl
|
||||
-- Design : hrc_64_12_025
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_data_tvalid : in STD_LOGIC;
|
||||
s_axis_data_tready : out STD_LOGIC;
|
||||
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+19
@@ -0,0 +1,19 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:33:00:00
|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:31:00:00
|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:31:00:00
|
||||
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|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72657365745f636f6d706f736974655f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00
|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f72657365745f6f75747075745f70726f6475637473:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7870675f636f6566696c65776964676465745f62726f777365:31:00:00
|
||||
eof:2287307455
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:31:00:00
|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:32:00:00
|
||||
eof:1740490455
|
||||
+3
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:1
|
||||
eof:
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
version:1
|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
|
||||
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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||||
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||||
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||||
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||||
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:6f75745f6f665f636f6e74657874:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
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||||
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|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
|
||||
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||||
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||||
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||||
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|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
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|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a343373:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313136332e3535394d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3737322e3533314d42:00:00
|
||||
eof:2852106907
|
||||
2352210899
|
||||
+51
@@ -0,0 +1,51 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Sat Mar 18 23:16:15 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="d97f646484634a4ab334ae0b5d6c3a6a" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddExistingIPHandler" value="1" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="2" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="2" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_OK" value="3" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="9" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="13" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
||||
<property name="HACGCCoeFileWidget_BROWSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_EXISTING_IP" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="2" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="XPG_CoeFileWidgdet_BROWSE" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="51" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="34" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
+11
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="cmpy_18x8_synth_1" LaunchDir="D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="dds_32b_8b_synth_1" LaunchDir="D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="hop_rom_synth_1" LaunchDir="D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="hrc_64_12_025_synth_1" LaunchDir="D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="30744" HostCore="20" HostMemory="068448337920">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
BIN
Binary file not shown.
+155
@@ -0,0 +1,155 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES XPM_MEMORY [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1 -new_name cmpy_18x8 -ip [get_ips cmpy_18x8]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top cmpy_18x8 -part xc7k410tffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix cmpy_18x8_ cmpy_18x8.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x8_stub.v
|
||||
lappend ipCachedFiles cmpy_18x8_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x8_stub.vhdl
|
||||
lappend ipCachedFiles cmpy_18x8_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x8_sim_netlist.v
|
||||
lappend ipCachedFiles cmpy_18x8_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x8_sim_netlist.vhdl
|
||||
lappend ipCachedFiles cmpy_18x8_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp cmpy_18x8.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips cmpy_18x8]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all cmpy_18x8_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef cmpy_18x8.dcp
|
||||
create_report "cmpy_18x8_synth_1_synth_report_utilization_0" "report_utilization -file cmpy_18x8_utilization_synth.rpt -pb cmpy_18x8_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_sim_netlist.v -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8.dcp -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci]
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_sim_netlist.v D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_sim_netlist.vhdl D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
+498
@@ -0,0 +1,498 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Sat Mar 18 23:15:10 2023
|
||||
# Process ID: 28200
|
||||
# Current directory: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1
|
||||
# Command line: vivado.exe -log cmpy_18x8.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_18x8.tcl
|
||||
# Log file: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8.vds
|
||||
# Journal file: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
|
||||
source cmpy_18x8.tcl -notrace
|
||||
Command: synth_design -top cmpy_18x8 -part xc7k410tffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 31332
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 884.949 ; gain = 177.055
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'cmpy_18x8' [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/synth/cmpy_18x8.vhd:71]
|
||||
Parameter C_VERBOSITY bound to: 0 - type: integer
|
||||
Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string
|
||||
Parameter C_XDEVICE bound to: xc7k410t - type: string
|
||||
Parameter C_A_WIDTH bound to: 18 - type: integer
|
||||
Parameter C_B_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_OUT_WIDTH bound to: 27 - type: integer
|
||||
Parameter C_LATENCY bound to: 6 - type: integer
|
||||
Parameter C_MULT_TYPE bound to: 1 - type: integer
|
||||
Parameter C_OPTIMIZE_GOAL bound to: 0 - type: integer
|
||||
Parameter HAS_NEGATE bound to: 0 - type: integer
|
||||
Parameter SINGLE_OUTPUT bound to: 0 - type: integer
|
||||
Parameter ROUND bound to: 0 - type: integer
|
||||
Parameter USE_DSP_CASCADES bound to: 1 - type: integer
|
||||
Parameter C_THROTTLE_SCHEME bound to: 3 - type: integer
|
||||
Parameter C_HAS_ACLKEN bound to: 0 - type: integer
|
||||
Parameter C_HAS_ARESETN bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_A_TUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_A_TLAST bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_B_TUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_B_TLAST bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_CTRL_TUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_CTRL_TLAST bound to: 0 - type: integer
|
||||
Parameter C_TLAST_RESOLUTION bound to: 0 - type: integer
|
||||
Parameter C_S_AXIS_A_TDATA_WIDTH bound to: 48 - type: integer
|
||||
Parameter C_S_AXIS_A_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_S_AXIS_B_TDATA_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_S_AXIS_B_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_S_AXIS_CTRL_TDATA_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_S_AXIS_CTRL_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_M_AXIS_DOUT_TDATA_WIDTH bound to: 64 - type: integer
|
||||
Parameter C_M_AXIS_DOUT_TUSER_WIDTH bound to: 1 - type: integer
|
||||
INFO: [Synth 8-3491] module 'cmpy_v6_0_17' declared at 'd:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/hdl/cmpy_v6_0_vh_rfs.vhd:13922' bound to instance 'U0' of component 'cmpy_v6_0_17' [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/synth/cmpy_18x8.vhd:155]
|
||||
INFO: [Synth 8-256] done synthesizing module 'cmpy_18x8' (11#1) [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/synth/cmpy_18x8.vhd:71]
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized1 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized1 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized1 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized0 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized0 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design dsp__parameterized1 has unconnected port SUBTRACT
|
||||
WARNING: [Synth 8-3331] design dsp__parameterized1 has unconnected port CARRY_IN
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized3 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized3 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized3 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized2 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized2 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized1 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized1 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized1 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized3 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized3 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized3 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized2 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized2 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_delay_line__parameterized2 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design dsp__parameterized0 has unconnected port SUBTRACT
|
||||
WARNING: [Synth 8-3331] design dsp__parameterized0 has unconnected port CARRY_IN
|
||||
WARNING: [Synth 8-3331] design dsp has unconnected port CARRY_IN
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized4 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized4 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized4 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized0 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized0 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized0 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design input_negation has unconnected port NEGATE_R
|
||||
WARNING: [Synth 8-3331] design input_negation has unconnected port NEGATE_I
|
||||
WARNING: [Synth 8-3331] design input_negation has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design input_negation has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design input_negation has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port ROUND_CY
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port SO_START
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aclken
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aresetn
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tlast
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[47]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[46]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[45]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[44]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[43]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[42]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[23]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[22]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[21]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[20]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[19]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[18]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tlast
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tvalid
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tlast
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[7]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[6]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[5]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[4]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[3]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[2]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[1]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port m_axis_dout_tready
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1033.062 ; gain = 325.168
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1033.062 ; gain = 325.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1033.062 ; gain = 325.168
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1033.062 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1033.062 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1033.062 ; gain = 325.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1033.062 ; gain = 325.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1033.062 ; gain = 325.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1033.062 ; gain = 325.168
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 1540 (col length:140)
|
||||
BRAMs: 1590 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aclken
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aresetn
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tlast
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[47]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[46]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[45]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[44]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[43]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[42]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[23]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[22]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[21]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[20]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[19]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[18]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tlast
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tvalid
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tlast
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[7]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[6]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[5]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[4]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[3]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[2]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[1]
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][7]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][8]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][9]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][10]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][11]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][12]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][13]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][14]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][15]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][16]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][17]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][18]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][19]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][20]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][21]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][22]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][23]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[0][24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[0]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[0]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[1]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[1]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[2]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[3]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[4]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[5]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[6]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[7]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[8]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[9]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[10]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[11]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[12]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[13]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[14]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[15]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[16]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[16]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[17]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[17]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[18]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[18]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[19]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[20]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[20]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[21]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[21]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[22]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[22]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[23]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult1_preadder_d_plus_a.mult1/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][0]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][0]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][1]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][1]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][2]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][2]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][3]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][4]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][4]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][5]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][5]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][6]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][6]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][7]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][8]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][9]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][10]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][11]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][12]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][13]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][14]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][15]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][16]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][17]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][18]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][19]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][20]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][21]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][22]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][23]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_1.reg_mult1_preadd_d/dN.std_srl.shift_reg_reg[1][24]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[7]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[8]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[9]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[10]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[11]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[12]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[13]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[14]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[15]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[16]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[17]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[18]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[19]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[20]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[21]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[22]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[23]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/mult3_preadder_d_minus_a.mult3/mult/use_prim.iAdelx[0].iAdely[0].use_delay_line.Adelay/d1.dout_i_reg[24]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][7]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][8]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][9]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][10]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][11]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][12]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][13]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][14]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][15]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][16]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][17]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][18]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][19]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][20]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][21]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][22]' (FD) to 'U0/i_synth/i_synth/three_mult_structure.use_dsp.i_dsp48/dsp_preadder_3.reg_mult3_preadd_d/dN.std_srl.shift_reg_reg[1][23]'
|
||||
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 1033.062 ; gain = 325.168
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1076.863 ; gain = 368.969
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1077.309 ; gain = 369.414
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1087.074 ; gain = 379.180
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 1102.883 ; gain = 394.988
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 1102.883 ; gain = 394.988
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 1102.883 ; gain = 394.988
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 1102.883 ; gain = 394.988
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 1102.883 ; gain = 394.988
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 1102.883 ; gain = 394.988
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+----------+------+
|
||||
| |Cell |Count |
|
||||
+------+----------+------+
|
||||
|1 |DSP48E1 | 2|
|
||||
|2 |DSP48E1_1 | 1|
|
||||
|3 |LUT2 | 1|
|
||||
|4 |SRL16E | 37|
|
||||
|5 |FDRE | 62|
|
||||
+------+----------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 1102.883 ; gain = 394.988
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 30 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:04 ; elapsed = 00:00:20 . Memory (MB): peak = 1102.883 ; gain = 394.988
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1102.883 ; gain = 394.988
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1102.883 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
118 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:27 . Memory (MB): peak = 1102.883 ; gain = 717.496
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1102.883 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP cmpy_18x8, cache-ID = 5b4a2e3a64350b28
|
||||
INFO: [Coretcl 2-1174] Renamed 16 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1102.883 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file cmpy_18x8_utilization_synth.rpt -pb cmpy_18x8_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Mar 18 23:15:41 2023...
|
||||
+1984
File diff suppressed because it is too large
Load Diff
+2563
File diff suppressed because it is too large
Load Diff
+27
@@ -0,0 +1,27 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:15:41 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v
|
||||
// Design : cmpy_18x8
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *)
|
||||
module cmpy_18x8(aclk, s_axis_a_tvalid, s_axis_a_tdata,
|
||||
s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]" */;
|
||||
input aclk;
|
||||
input s_axis_a_tvalid;
|
||||
input [47:0]s_axis_a_tdata;
|
||||
input s_axis_b_tvalid;
|
||||
input [15:0]s_axis_b_tdata;
|
||||
output m_axis_dout_tvalid;
|
||||
output [63:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:15:41 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl
|
||||
-- Design : cmpy_18x8
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity cmpy_18x8 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_a_tvalid : in STD_LOGIC;
|
||||
s_axis_a_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||
s_axis_b_tvalid : in STD_LOGIC;
|
||||
s_axis_b_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
|
||||
end cmpy_18x8;
|
||||
|
||||
architecture stub of cmpy_18x8 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
+179
@@ -0,0 +1,179 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
| Date : Sat Mar 18 23:15:41 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file cmpy_18x8_utilization_synth.rpt -pb cmpy_18x8_utilization_synth.pb
|
||||
| Design : cmpy_18x8
|
||||
| Device : 7k410tffg900-2
|
||||
| Design State : Synthesized
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 38 | 0 | 254200 | 0.01 |
|
||||
| LUT as Logic | 1 | 0 | 254200 | <0.01 |
|
||||
| LUT as Memory | 37 | 0 | 90600 | 0.04 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | |
|
||||
| LUT as Shift Register | 37 | 0 | | |
|
||||
| Slice Registers | 62 | 0 | 508400 | 0.01 |
|
||||
| Register as Flip Flop | 62 | 0 | 508400 | 0.01 |
|
||||
| Register as Latch | 0 | 0 | 508400 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 127100 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 63550 | 0.00 |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 62 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 795 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 1590 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| DSPs | 3 | 0 | 1540 | 0.19 |
|
||||
| DSP48E1 only | 3 | | | |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 500 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 480 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 500 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 500 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 62 | Flop & Latch |
|
||||
| SRL16E | 37 | Distributed Memory |
|
||||
| DSP48E1 | 3 | Block Arithmetic |
|
||||
| LUT2 | 1 | LUT |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci
|
||||
# IP: The module: 'cmpy_18x8' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'cmpy_18x8'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci
|
||||
# IP: The module: 'cmpy_18x8' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'cmpy_18x8'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="cmpy_18x8_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679152508">
|
||||
<File Type="PA-TCL" Name="cmpy_18x8.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="cmpy_18x8_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="cmpy_18x8_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="cmpy_18x8.vds"/>
|
||||
<File Type="RDS-UTIL" Name="cmpy_18x8_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="cmpy_18x8_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="cmpy_18x8.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="cmpy_18x8_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="cmpy_18x8_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x8">
|
||||
<File Path="$PPRDIR/../cmpy_18x8/cmpy_18x8.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../cmpy_18x8.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="cmpy_18x8"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x8">
|
||||
<File Path="$PPRDIR/../cmpy_18x8/cmpy_18x8.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../cmpy_18x8.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="cmpy_18x8"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log cmpy_18x8.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_18x8.tcl
|
||||
+35
@@ -0,0 +1,35 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31387838:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6464735f636f6d70696c65725f76365f305f31385c6464735f3332625f3862:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c686f705f726f6d:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6872635f36345f31325f303235:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:34:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3465326630323830363633633462666538363165633665366337636266623331:506172656e742050412070726f6a656374204944:00
|
||||
eof:1911739650
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log cmpy_18x8.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_18x8.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
+43
@@ -0,0 +1,43 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log cmpy_18x8.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_18x8.tcl
|
||||
BIN
Binary file not shown.
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="3520" HostCore="20" HostMemory="068448337920">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
BIN
Binary file not shown.
+155
@@ -0,0 +1,155 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES XPM_MEMORY [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1 -new_name dds_32b_8b -ip [get_ips dds_32b_8b]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top dds_32b_8b -part xc7k410tffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix dds_32b_8b_ dds_32b_8b.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_stub.v
|
||||
lappend ipCachedFiles dds_32b_8b_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_stub.vhdl
|
||||
lappend ipCachedFiles dds_32b_8b_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_sim_netlist.v
|
||||
lappend ipCachedFiles dds_32b_8b_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_sim_netlist.vhdl
|
||||
lappend ipCachedFiles dds_32b_8b_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp dds_32b_8b.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips dds_32b_8b]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all dds_32b_8b_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef dds_32b_8b.dcp
|
||||
create_report "dds_32b_8b_synth_1_synth_report_utilization_0" "report_utilization -file dds_32b_8b_utilization_synth.rpt -pb dds_32b_8b_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_sim_netlist.v -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b.dcp -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci]
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_sim_netlist.v D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_sim_netlist.vhdl D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
+423
@@ -0,0 +1,423 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Sat Mar 18 23:15:10 2023
|
||||
# Process ID: 32708
|
||||
# Current directory: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1
|
||||
# Command line: vivado.exe -log dds_32b_8b.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_32b_8b.tcl
|
||||
# Log file: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b.vds
|
||||
# Journal file: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
|
||||
source dds_32b_8b.tcl -notrace
|
||||
Command: synth_design -top dds_32b_8b -part xc7k410tffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 15380
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 884.562 ; gain = 176.777
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'dds_32b_8b' [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/synth/dds_32b_8b.vhd:69]
|
||||
WARNING: [Synth 8-5640] Port 'debug_axi_pinc_in' is missing in component declaration [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
WARNING: [Synth 8-5640] Port 'debug_axi_poff_in' is missing in component declaration [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
WARNING: [Synth 8-5640] Port 'debug_axi_resync_in' is missing in component declaration [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
WARNING: [Synth 8-5640] Port 'debug_axi_chan_in' is missing in component declaration [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
WARNING: [Synth 8-5640] Port 'debug_core_nd' is missing in component declaration [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
WARNING: [Synth 8-5640] Port 'debug_phase' is missing in component declaration [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
WARNING: [Synth 8-5640] Port 'debug_phase_nd' is missing in component declaration [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string
|
||||
Parameter C_MODE_OF_OPERATION bound to: 0 - type: integer
|
||||
Parameter C_MODULUS bound to: 9 - type: integer
|
||||
Parameter C_ACCUMULATOR_WIDTH bound to: 32 - type: integer
|
||||
Parameter C_CHANNELS bound to: 1 - type: integer
|
||||
Parameter C_HAS_PHASE_OUT bound to: 0 - type: integer
|
||||
Parameter C_HAS_PHASEGEN bound to: 1 - type: integer
|
||||
Parameter C_HAS_SINCOS bound to: 1 - type: integer
|
||||
Parameter C_LATENCY bound to: 3 - type: integer
|
||||
Parameter C_MEM_TYPE bound to: 1 - type: integer
|
||||
Parameter C_NEGATIVE_COSINE bound to: 0 - type: integer
|
||||
Parameter C_NEGATIVE_SINE bound to: 0 - type: integer
|
||||
Parameter C_NOISE_SHAPING bound to: 0 - type: integer
|
||||
Parameter C_OUTPUTS_REQUIRED bound to: 2 - type: integer
|
||||
Parameter C_OUTPUT_FORM bound to: 0 - type: integer
|
||||
Parameter C_OUTPUT_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_PHASE_ANGLE_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_PHASE_INCREMENT bound to: 1 - type: integer
|
||||
Parameter C_PHASE_INCREMENT_VALUE bound to: 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - type: string
|
||||
Parameter C_RESYNC bound to: 0 - type: integer
|
||||
Parameter C_PHASE_OFFSET bound to: 0 - type: integer
|
||||
Parameter C_PHASE_OFFSET_VALUE bound to: 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - type: string
|
||||
Parameter C_OPTIMISE_GOAL bound to: 0 - type: integer
|
||||
Parameter C_USE_DSP48 bound to: 0 - type: integer
|
||||
Parameter C_POR_MODE bound to: 0 - type: integer
|
||||
Parameter C_AMPLITUDE bound to: 0 - type: integer
|
||||
Parameter C_HAS_ACLKEN bound to: 0 - type: integer
|
||||
Parameter C_HAS_ARESETN bound to: 0 - type: integer
|
||||
Parameter C_HAS_TLAST bound to: 0 - type: integer
|
||||
Parameter C_HAS_TREADY bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_PHASE bound to: 0 - type: integer
|
||||
Parameter C_S_PHASE_TDATA_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_S_PHASE_HAS_TUSER bound to: 0 - type: integer
|
||||
Parameter C_S_PHASE_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_HAS_S_CONFIG bound to: 1 - type: integer
|
||||
Parameter C_S_CONFIG_SYNC_MODE bound to: 0 - type: integer
|
||||
Parameter C_S_CONFIG_TDATA_WIDTH bound to: 32 - type: integer
|
||||
Parameter C_HAS_M_DATA bound to: 1 - type: integer
|
||||
Parameter C_M_DATA_TDATA_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_M_DATA_HAS_TUSER bound to: 0 - type: integer
|
||||
Parameter C_M_DATA_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_HAS_M_PHASE bound to: 0 - type: integer
|
||||
Parameter C_M_PHASE_TDATA_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_M_PHASE_HAS_TUSER bound to: 0 - type: integer
|
||||
Parameter C_M_PHASE_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_DEBUG_INTERFACE bound to: 0 - type: integer
|
||||
Parameter C_CHAN_WIDTH bound to: 1 - type: integer
|
||||
INFO: [Synth 8-3491] module 'dds_compiler_v6_0_18' declared at 'd:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/hdl/dds_compiler_v6_0_vh_rfs.vhd:47308' bound to instance 'U0' of component 'dds_compiler_v6_0_18' [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/synth/dds_32b_8b.vhd:174]
|
||||
INFO: [Synth 8-256] done synthesizing module 'dds_32b_8b' (9#1) [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/synth/dds_32b_8b.vhd:69]
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized15 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized15 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized15 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized15 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized15 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized13 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized13 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized13 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized13 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized13 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized11 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized11 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized11 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized11 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized11 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design sin_cos has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized7 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized7 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized7 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port chan_addr[0]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port chan_addr_del2[0]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port chan_addr_del3[0]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port addr_i[3]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port addr_i[2]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port addr_i[1]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port addr_i[0]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port phase_inc_we
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port phase_adj_we
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[31]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[30]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[29]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[28]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[27]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[26]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[25]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[24]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[23]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[22]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[21]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[20]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[19]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[18]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[17]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[16]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[15]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[14]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[13]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[12]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[11]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[10]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[9]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[8]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[7]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[6]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[5]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[4]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[3]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[2]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[1]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[0]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[31]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[30]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[29]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[28]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[27]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[26]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[25]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[24]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[23]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[22]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[21]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[20]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[19]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[18]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[17]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[16]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[15]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[14]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[13]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[12]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[11]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[10]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[9]
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 997.746 ; gain = 289.961
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 997.746 ; gain = 289.961
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 997.746 ; gain = 289.961
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1065.070 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1076.488 ; gain = 11.418
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-7031] Trying to map ROM "sin_cos_lut" into Block RAM due to explicit "ram_style" or "rom_style" specification
|
||||
INFO: [Synth 8-7031] Trying to map ROM "sin_cos_lut" into Block RAM due to explicit "ram_style" or "rom_style" specification
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 1540 (col length:140)
|
||||
BRAMs: 1590 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
|
||||
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6837] The timing for the instance U0/i_synth/i_0/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
||||
INFO: [Synth 8-6837] The timing for the instance U0/i_synth/i_1/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----------+------+
|
||||
| |Cell |Count |
|
||||
+------+-----------+------+
|
||||
|1 |CARRY4 | 9|
|
||||
|2 |LUT2 | 35|
|
||||
|3 |RAMB18E1_2 | 1|
|
||||
|4 |FDRE | 72|
|
||||
+------+-----------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 14 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 1076.488 ; gain = 289.961
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1076.488 ; gain = 368.703
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1094.684 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
21 Infos, 107 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:23 . Memory (MB): peak = 1094.684 ; gain = 707.797
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1094.684 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP dds_32b_8b, cache-ID = 202d32dc30c8d688
|
||||
INFO: [Coretcl 2-1174] Renamed 11 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1094.684 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file dds_32b_8b_utilization_synth.rpt -pb dds_32b_8b_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Mar 18 23:15:37 2023...
|
||||
+1481
File diff suppressed because it is too large
Load Diff
+1868
File diff suppressed because it is too large
Load Diff
+25
@@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:15:37 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v
|
||||
// Design : dds_32b_8b
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "dds_compiler_v6_0_18,Vivado 2019.1.3" *)
|
||||
module dds_32b_8b(aclk, s_axis_config_tvalid,
|
||||
s_axis_config_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tvalid,s_axis_config_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
|
||||
input aclk;
|
||||
input s_axis_config_tvalid;
|
||||
input [31:0]s_axis_config_tdata;
|
||||
output m_axis_data_tvalid;
|
||||
output [15:0]m_axis_data_tdata;
|
||||
endmodule
|
||||
+34
@@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:15:37 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl
|
||||
-- Design : dds_32b_8b
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity dds_32b_8b is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_config_tvalid : in STD_LOGIC;
|
||||
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end dds_32b_8b;
|
||||
|
||||
architecture stub of dds_32b_8b is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_config_tvalid,s_axis_config_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "dds_compiler_v6_0_18,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
+177
@@ -0,0 +1,177 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
| Date : Sat Mar 18 23:15:37 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file dds_32b_8b_utilization_synth.rpt -pb dds_32b_8b_utilization_synth.pb
|
||||
| Design : dds_32b_8b
|
||||
| Device : 7k410tffg900-2
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 34 | 0 | 254200 | 0.01 |
|
||||
| LUT as Logic | 34 | 0 | 254200 | 0.01 |
|
||||
| LUT as Memory | 0 | 0 | 90600 | 0.00 |
|
||||
| Slice Registers | 72 | 0 | 508400 | 0.01 |
|
||||
| Register as Flip Flop | 72 | 0 | 508400 | 0.01 |
|
||||
| Register as Latch | 0 | 0 | 508400 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 127100 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 63550 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 72 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0.5 | 0 | 795 | 0.06 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 |
|
||||
| RAMB18 | 1 | 0 | 1590 | 0.06 |
|
||||
| RAMB18E1 only | 1 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 1540 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 500 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 480 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 500 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 500 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 72 | Flop & Latch |
|
||||
| LUT2 | 35 | LUT |
|
||||
| CARRY4 | 9 | CarryLogic |
|
||||
| RAMB18E1 | 1 | Block Memory |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci
|
||||
# IP: The module: 'dds_32b_8b' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'dds_32b_8b'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci
|
||||
# IP: The module: 'dds_32b_8b' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'dds_32b_8b'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="dds_32b_8b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679152509">
|
||||
<File Type="PA-TCL" Name="dds_32b_8b.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="dds_32b_8b_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="dds_32b_8b_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="dds_32b_8b.vds"/>
|
||||
<File Type="RDS-UTIL" Name="dds_32b_8b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="dds_32b_8b_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="dds_32b_8b.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="dds_32b_8b_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="dds_32b_8b_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_32b_8b">
|
||||
<File Path="$PPRDIR/../dds_32b_8b/dds_32b_8b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../dds_32b_8b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="dds_32b_8b"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_32b_8b">
|
||||
<File Path="$PPRDIR/../dds_32b_8b/dds_32b_8b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../dds_32b_8b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="dds_32b_8b"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log dds_32b_8b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_32b_8b.tcl
|
||||
+35
@@ -0,0 +1,35 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31387838:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6464735f636f6d70696c65725f76365f305f31385c6464735f3332625f3862:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c686f705f726f6d:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6872635f36345f31325f303235:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:34:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3465326630323830363633633462666538363165633665366337636266623331:506172656e742050412070726f6a656374204944:00
|
||||
eof:1911739650
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log dds_32b_8b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_32b_8b.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
+43
@@ -0,0 +1,43 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log dds_32b_8b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_32b_8b.tcl
|
||||
BIN
Binary file not shown.
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="4712" HostCore="20" HostMemory="068448337920">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci
|
||||
# IP: The module: 'hop_rom' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'hop_rom'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci
|
||||
# IP: The module: 'hop_rom' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'hop_rom'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="hop_rom_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679152509">
|
||||
<File Type="PA-TCL" Name="hop_rom.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="hop_rom_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="hop_rom_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="hop_rom.vds"/>
|
||||
<File Type="RDS-UTIL" Name="hop_rom_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="hop_rom_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="hop_rom.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="hop_rom_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="hop_rom_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hop_rom">
|
||||
<File Path="$PPRDIR/../hop_rom/hop_rom.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../hop_rom.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="hop_rom"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hop_rom">
|
||||
<File Path="$PPRDIR/../hop_rom/hop_rom.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../hop_rom.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="hop_rom"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
BIN
Binary file not shown.
+155
@@ -0,0 +1,155 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES XPM_MEMORY [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1 -new_name hop_rom -ip [get_ips hop_rom]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top hop_rom -part xc7k410tffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix hop_rom_ hop_rom.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hop_rom_stub.v
|
||||
lappend ipCachedFiles hop_rom_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hop_rom_stub.vhdl
|
||||
lappend ipCachedFiles hop_rom_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hop_rom_sim_netlist.v
|
||||
lappend ipCachedFiles hop_rom_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hop_rom_sim_netlist.vhdl
|
||||
lappend ipCachedFiles hop_rom_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp hop_rom.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips hop_rom]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all hop_rom_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef hop_rom.dcp
|
||||
create_report "hop_rom_synth_1_synth_report_utilization_0" "report_utilization -file hop_rom_utilization_synth.rpt -pb hop_rom_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.v -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom.dcp -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci]
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.v D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.vhdl D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
+452
@@ -0,0 +1,452 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Sat Mar 18 23:15:11 2023
|
||||
# Process ID: 30584
|
||||
# Current directory: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1
|
||||
# Command line: vivado.exe -log hop_rom.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source hop_rom.tcl
|
||||
# Log file: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom.vds
|
||||
# Journal file: D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
|
||||
source hop_rom.tcl -notrace
|
||||
Command: synth_design -top hop_rom -part xc7k410tffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 30780
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 883.699 ; gain = 177.734
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'hop_rom' [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/synth/hop_rom.vhd:67]
|
||||
Parameter C_FAMILY bound to: kintex7 - type: string
|
||||
Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string
|
||||
Parameter C_ELABORATION_DIR bound to: ./ - type: string
|
||||
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
|
||||
Parameter C_AXI_TYPE bound to: 1 - type: integer
|
||||
Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer
|
||||
Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer
|
||||
Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer
|
||||
Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string
|
||||
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
|
||||
Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_MEM_TYPE bound to: 3 - type: integer
|
||||
Parameter C_BYTE_SIZE bound to: 9 - type: integer
|
||||
Parameter C_ALGORITHM bound to: 1 - type: integer
|
||||
Parameter C_PRIM_TYPE bound to: 1 - type: integer
|
||||
Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer
|
||||
Parameter C_INIT_FILE_NAME bound to: hop_rom.mif - type: string
|
||||
Parameter C_INIT_FILE bound to: hop_rom.mem - type: string
|
||||
Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer
|
||||
Parameter C_DEFAULT_DATA bound to: 0 - type: string
|
||||
Parameter C_HAS_RSTA bound to: 0 - type: integer
|
||||
Parameter C_RST_PRIORITY_A bound to: CE - type: string
|
||||
Parameter C_RSTRAM_A bound to: 0 - type: integer
|
||||
Parameter C_INITA_VAL bound to: 0 - type: string
|
||||
Parameter C_HAS_ENA bound to: 0 - type: integer
|
||||
Parameter C_HAS_REGCEA bound to: 0 - type: integer
|
||||
Parameter C_USE_BYTE_WEA bound to: 0 - type: integer
|
||||
Parameter C_WEA_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string
|
||||
Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer
|
||||
Parameter C_READ_WIDTH_A bound to: 32 - type: integer
|
||||
Parameter C_WRITE_DEPTH_A bound to: 256 - type: integer
|
||||
Parameter C_READ_DEPTH_A bound to: 256 - type: integer
|
||||
Parameter C_ADDRA_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_HAS_RSTB bound to: 0 - type: integer
|
||||
Parameter C_RST_PRIORITY_B bound to: CE - type: string
|
||||
Parameter C_RSTRAM_B bound to: 0 - type: integer
|
||||
Parameter C_INITB_VAL bound to: 0 - type: string
|
||||
Parameter C_HAS_ENB bound to: 0 - type: integer
|
||||
Parameter C_HAS_REGCEB bound to: 0 - type: integer
|
||||
Parameter C_USE_BYTE_WEB bound to: 0 - type: integer
|
||||
Parameter C_WEB_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string
|
||||
Parameter C_WRITE_WIDTH_B bound to: 32 - type: integer
|
||||
Parameter C_READ_WIDTH_B bound to: 32 - type: integer
|
||||
Parameter C_WRITE_DEPTH_B bound to: 256 - type: integer
|
||||
Parameter C_READ_DEPTH_B bound to: 256 - type: integer
|
||||
Parameter C_ADDRB_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 0 - type: integer
|
||||
Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer
|
||||
Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer
|
||||
Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer
|
||||
Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer
|
||||
Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer
|
||||
Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer
|
||||
Parameter C_USE_SOFTECC bound to: 0 - type: integer
|
||||
Parameter C_USE_ECC bound to: 0 - type: integer
|
||||
Parameter C_EN_ECC_PIPE bound to: 0 - type: integer
|
||||
Parameter C_READ_LATENCY_A bound to: 1 - type: integer
|
||||
Parameter C_READ_LATENCY_B bound to: 1 - type: integer
|
||||
Parameter C_HAS_INJECTERR bound to: 0 - type: integer
|
||||
Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string
|
||||
Parameter C_COMMON_CLK bound to: 0 - type: integer
|
||||
Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer
|
||||
Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer
|
||||
Parameter C_USE_URAM bound to: 0 - type: integer
|
||||
Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer
|
||||
Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer
|
||||
Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer
|
||||
Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer
|
||||
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
|
||||
Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer
|
||||
Parameter C_COUNT_36K_BRAM bound to: 0 - type: string
|
||||
Parameter C_COUNT_18K_BRAM bound to: 1 - type: string
|
||||
Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 3.375199 mW - type: string
|
||||
INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_3' declared at 'd:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_3' [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/synth/hop_rom.vhd:230]
|
||||
INFO: [Synth 8-256] done synthesizing module 'hop_rom' (9#1) [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/synth/hop_rom.vhd:67]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port CLKB
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ENB
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port REGCEB
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port WEB[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[8]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[7]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[6]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[5]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[4]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[35]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[34]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[33]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[32]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[31]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[30]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[29]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[28]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[27]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[26]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[25]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[24]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[23]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[22]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[21]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[20]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[19]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[18]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[17]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[16]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[15]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[14]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[13]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[12]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[11]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[10]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[9]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[8]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[7]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[6]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[5]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[4]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SLEEP
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTSBITERR
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTDBITERR
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ECCPIPECE
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ram_rstram_b
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ram_rstreg_b
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port REGCEA[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEA[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEA[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEA[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port REGCEB[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTSBITERR
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTDBITERR
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[31]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[30]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[29]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[28]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[27]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[26]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[25]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[24]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[23]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[22]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[21]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[20]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[19]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[18]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[17]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[16]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[15]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[14]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[13]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[12]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[11]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[10]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[9]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[8]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[7]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[6]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[5]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[4]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[0]
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:29 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:29 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:29 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1163.559 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1163.559 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:33 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:33 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:33 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:33 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 1540 (col length:140)
|
||||
BRAMs: 1590 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:33 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:38 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:38 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:38 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:12 ; elapsed = 00:00:38 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:12 ; elapsed = 00:00:38 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:12 ; elapsed = 00:00:38 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:12 ; elapsed = 00:00:38 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:38 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:12 ; elapsed = 00:00:38 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+---------+------+
|
||||
| |Cell |Count |
|
||||
+------+---------+------+
|
||||
|1 |RAMB18E1 | 1|
|
||||
+------+---------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------------------------------------------+------------------------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------------------------------------------+------------------------------+------+
|
||||
|1 |top | | 1|
|
||||
|2 | U0 |blk_mem_gen_v8_4_3 | 1|
|
||||
|3 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 1|
|
||||
|4 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 1|
|
||||
|5 | \valid.cstr |blk_mem_gen_generic_cstr | 1|
|
||||
|6 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 1|
|
||||
|7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1|
|
||||
+------+---------------------------------------------+------------------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:12 ; elapsed = 00:00:38 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 228 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:02 ; elapsed = 00:00:37 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:38 . Memory (MB): peak = 1163.559 ; gain = 457.594
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1163.559 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:44 . Memory (MB): peak = 1163.559 ; gain = 777.480
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1163.559 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP hop_rom, cache-ID = 324ccc651779d6cd
|
||||
INFO: [Coretcl 2-1174] Renamed 6 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1163.559 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file hop_rom_utilization_synth.rpt -pb hop_rom_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Mar 18 23:15:58 2023...
|
||||
+749
@@ -0,0 +1,749 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:15:57 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.v
|
||||
// Design : hop_rom
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "hop_rom,blk_mem_gen_v8_4_3,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||
(* NotValidForBitStream *)
|
||||
module hop_rom
|
||||
(clka,
|
||||
addra,
|
||||
douta);
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [7:0]addra;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta;
|
||||
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
wire NLW_U0_dbiterr_UNCONNECTED;
|
||||
wire NLW_U0_rsta_busy_UNCONNECTED;
|
||||
wire NLW_U0_rstb_busy_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_arready_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_awready_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_rlast_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_wready_UNCONNECTED;
|
||||
wire NLW_U0_sbiterr_UNCONNECTED;
|
||||
wire [31:0]NLW_U0_doutb_UNCONNECTED;
|
||||
wire [7:0]NLW_U0_rdaddrecc_UNCONNECTED;
|
||||
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
|
||||
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
|
||||
wire [7:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
|
||||
wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED;
|
||||
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
|
||||
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
|
||||
|
||||
(* C_ADDRA_WIDTH = "8" *)
|
||||
(* C_ADDRB_WIDTH = "8" *)
|
||||
(* C_ALGORITHM = "1" *)
|
||||
(* C_AXI_ID_WIDTH = "4" *)
|
||||
(* C_AXI_SLAVE_TYPE = "0" *)
|
||||
(* C_AXI_TYPE = "1" *)
|
||||
(* C_BYTE_SIZE = "9" *)
|
||||
(* C_COMMON_CLK = "0" *)
|
||||
(* C_COUNT_18K_BRAM = "1" *)
|
||||
(* C_COUNT_36K_BRAM = "0" *)
|
||||
(* C_CTRL_ECC_ALGO = "NONE" *)
|
||||
(* C_DEFAULT_DATA = "0" *)
|
||||
(* C_DISABLE_WARN_BHV_COLL = "0" *)
|
||||
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
|
||||
(* C_ELABORATION_DIR = "./" *)
|
||||
(* C_ENABLE_32BIT_ADDRESS = "0" *)
|
||||
(* C_EN_DEEPSLEEP_PIN = "0" *)
|
||||
(* C_EN_ECC_PIPE = "0" *)
|
||||
(* C_EN_RDADDRA_CHG = "0" *)
|
||||
(* C_EN_RDADDRB_CHG = "0" *)
|
||||
(* C_EN_SAFETY_CKT = "0" *)
|
||||
(* C_EN_SHUTDOWN_PIN = "0" *)
|
||||
(* C_EN_SLEEP_PIN = "0" *)
|
||||
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.375199 mW" *)
|
||||
(* C_FAMILY = "kintex7" *)
|
||||
(* C_HAS_AXI_ID = "0" *)
|
||||
(* C_HAS_ENA = "0" *)
|
||||
(* C_HAS_ENB = "0" *)
|
||||
(* C_HAS_INJECTERR = "0" *)
|
||||
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
|
||||
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
|
||||
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
|
||||
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
|
||||
(* C_HAS_REGCEA = "0" *)
|
||||
(* C_HAS_REGCEB = "0" *)
|
||||
(* C_HAS_RSTA = "0" *)
|
||||
(* C_HAS_RSTB = "0" *)
|
||||
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
|
||||
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
|
||||
(* C_INITA_VAL = "0" *)
|
||||
(* C_INITB_VAL = "0" *)
|
||||
(* C_INIT_FILE = "hop_rom.mem" *)
|
||||
(* C_INIT_FILE_NAME = "hop_rom.mif" *)
|
||||
(* C_INTERFACE_TYPE = "0" *)
|
||||
(* C_LOAD_INIT_FILE = "1" *)
|
||||
(* C_MEM_TYPE = "3" *)
|
||||
(* C_MUX_PIPELINE_STAGES = "0" *)
|
||||
(* C_PRIM_TYPE = "1" *)
|
||||
(* C_READ_DEPTH_A = "256" *)
|
||||
(* C_READ_DEPTH_B = "256" *)
|
||||
(* C_READ_LATENCY_A = "1" *)
|
||||
(* C_READ_LATENCY_B = "1" *)
|
||||
(* C_READ_WIDTH_A = "32" *)
|
||||
(* C_READ_WIDTH_B = "32" *)
|
||||
(* C_RSTRAM_A = "0" *)
|
||||
(* C_RSTRAM_B = "0" *)
|
||||
(* C_RST_PRIORITY_A = "CE" *)
|
||||
(* C_RST_PRIORITY_B = "CE" *)
|
||||
(* C_SIM_COLLISION_CHECK = "ALL" *)
|
||||
(* C_USE_BRAM_BLOCK = "0" *)
|
||||
(* C_USE_BYTE_WEA = "0" *)
|
||||
(* C_USE_BYTE_WEB = "0" *)
|
||||
(* C_USE_DEFAULT_DATA = "0" *)
|
||||
(* C_USE_ECC = "0" *)
|
||||
(* C_USE_SOFTECC = "0" *)
|
||||
(* C_USE_URAM = "0" *)
|
||||
(* C_WEA_WIDTH = "1" *)
|
||||
(* C_WEB_WIDTH = "1" *)
|
||||
(* C_WRITE_DEPTH_A = "256" *)
|
||||
(* C_WRITE_DEPTH_B = "256" *)
|
||||
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
|
||||
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||
(* C_WRITE_WIDTH_A = "32" *)
|
||||
(* C_WRITE_WIDTH_B = "32" *)
|
||||
(* C_XDEVICEFAMILY = "kintex7" *)
|
||||
(* downgradeipidentifiedwarnings = "yes" *)
|
||||
hop_rom_blk_mem_gen_v8_4_3 U0
|
||||
(.addra(addra),
|
||||
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.clka(clka),
|
||||
.clkb(1'b0),
|
||||
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
|
||||
.deepsleep(1'b0),
|
||||
.dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.douta(douta),
|
||||
.doutb(NLW_U0_doutb_UNCONNECTED[31:0]),
|
||||
.eccpipece(1'b0),
|
||||
.ena(1'b0),
|
||||
.enb(1'b0),
|
||||
.injectdbiterr(1'b0),
|
||||
.injectsbiterr(1'b0),
|
||||
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[7:0]),
|
||||
.regcea(1'b0),
|
||||
.regceb(1'b0),
|
||||
.rsta(1'b0),
|
||||
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
|
||||
.rstb(1'b0),
|
||||
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
|
||||
.s_aclk(1'b0),
|
||||
.s_aresetn(1'b0),
|
||||
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_arburst({1'b0,1'b0}),
|
||||
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
|
||||
.s_axi_arsize({1'b0,1'b0,1'b0}),
|
||||
.s_axi_arvalid(1'b0),
|
||||
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_awburst({1'b0,1'b0}),
|
||||
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
|
||||
.s_axi_awsize({1'b0,1'b0,1'b0}),
|
||||
.s_axi_awvalid(1'b0),
|
||||
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
|
||||
.s_axi_bready(1'b0),
|
||||
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
|
||||
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
|
||||
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
|
||||
.s_axi_injectdbiterr(1'b0),
|
||||
.s_axi_injectsbiterr(1'b0),
|
||||
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[7:0]),
|
||||
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]),
|
||||
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
|
||||
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
|
||||
.s_axi_rready(1'b0),
|
||||
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
|
||||
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
|
||||
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
|
||||
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_wlast(1'b0),
|
||||
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
|
||||
.s_axi_wstrb(1'b0),
|
||||
.s_axi_wvalid(1'b0),
|
||||
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
|
||||
.shutdown(1'b0),
|
||||
.sleep(1'b0),
|
||||
.wea(1'b0),
|
||||
.web(1'b0));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
||||
module hop_rom_blk_mem_gen_generic_cstr
|
||||
(douta,
|
||||
clka,
|
||||
addra);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
|
||||
hop_rom_blk_mem_gen_prim_width \ramloop[0].ram.r
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
||||
module hop_rom_blk_mem_gen_prim_width
|
||||
(douta,
|
||||
clka,
|
||||
addra);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
|
||||
hop_rom_blk_mem_gen_prim_wrapper_init \prim_init.ram
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
||||
module hop_rom_blk_mem_gen_prim_wrapper_init
|
||||
(douta,
|
||||
clka,
|
||||
addra);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 ;
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
RAMB18E1 #(
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_00(256'h8707070886060607850505068404040583030304820202038101010280000001),
|
||||
.INIT_01(256'h8F0F0F108E0E0E0F8D0D0D0E8C0C0C0D8B0B0B0C8A0A0A0B8909090A88080809),
|
||||
.INIT_02(256'h9717171896161617951515169414141593131314921212139111111290101011),
|
||||
.INIT_03(256'h9F1F1F209E1E1E1F9D1D1D1E9C1C1C1D9B1B1B1C9A1A1A1B9919191A98181819),
|
||||
.INIT_04(256'hA7272728A6262627A5252526A4242425A3232324A2222223A1212122A0202021),
|
||||
.INIT_05(256'hAF2F2F30AE2E2E2FAD2D2D2EAC2C2C2DAB2B2B2CAA2A2A2BA929292AA8282829),
|
||||
.INIT_06(256'hB7373738B6363637B5353536B4343435B3333334B2323233B1313132B0303031),
|
||||
.INIT_07(256'hBF3F3F40BE3E3E3FBD3D3D3EBC3C3C3DBB3B3B3CBA3A3A3BB939393AB8383839),
|
||||
.INIT_08(256'hC7474748C6464647C5454546C4444445C3434344C2424243C1414142C0404041),
|
||||
.INIT_09(256'hCF4F4F50CE4E4E4FCD4D4D4ECC4C4C4DCB4B4B4CCA4A4A4BC949494AC8484849),
|
||||
.INIT_0A(256'hD7575758D6565657D5555556D4545455D3535354D2525253D1515152D0505051),
|
||||
.INIT_0B(256'hDF5F5F60DE5E5E5FDD5D5D5EDC5C5C5DDB5B5B5CDA5A5A5BD959595AD8585859),
|
||||
.INIT_0C(256'hE7676768E6666667E5656566E4646465E3636364E2626263E1616162E0606061),
|
||||
.INIT_0D(256'hEF6F6F70EE6E6E6FED6D6D6EEC6C6C6DEB6B6B6CEA6A6A6BE969696AE8686869),
|
||||
.INIT_0E(256'hF7777778F6767677F5757576F4747475F3737374F2727273F1717172F0707071),
|
||||
.INIT_0F(256'hFF7F7F80FE7E7E7FFD7D7D7EFC7C7C7DFB7B7B7CFA7A7A7BF979797AF8787879),
|
||||
.INIT_10(256'h0787878706868686058585850484848403838383028282820181818100808080),
|
||||
.INIT_11(256'h0F8F8F8F0E8E8E8E0D8D8D8D0C8C8C8C0B8B8B8B0A8A8A8A0989898908888888),
|
||||
.INIT_12(256'h1797979716969696159595951494949413939393129292921191919110909090),
|
||||
.INIT_13(256'h1F9F9F9F1E9E9E9E1D9D9D9D1C9C9C9C1B9B9B9B1A9A9A9A1999999918989898),
|
||||
.INIT_14(256'h27A7A7A726A6A6A625A5A5A524A4A4A423A3A3A322A2A2A221A1A1A120A0A0A0),
|
||||
.INIT_15(256'h2FAFAFAF2EAEAEAE2DADADAD2CACACAC2BABABAB2AAAAAAA29A9A9A928A8A8A8),
|
||||
.INIT_16(256'h37B7B7B736B6B6B635B5B5B534B4B4B433B3B3B332B2B2B231B1B1B130B0B0B0),
|
||||
.INIT_17(256'h3FBFBFBF3EBEBEBE3DBDBDBD3CBCBCBC3BBBBBBB3ABABABA39B9B9B938B8B8B8),
|
||||
.INIT_18(256'h47C7C7C746C6C6C645C5C5C544C4C4C443C3C3C342C2C2C241C1C1C140C0C0C0),
|
||||
.INIT_19(256'h4FCFCFCF4ECECECE4DCDCDCD4CCCCCCC4BCBCBCB4ACACACA49C9C9C948C8C8C8),
|
||||
.INIT_1A(256'h57D7D7D756D6D6D655D5D5D554D4D4D453D3D3D352D2D2D251D1D1D150D0D0D0),
|
||||
.INIT_1B(256'h5FDFDFDF5EDEDEDE5DDDDDDD5CDCDCDC5BDBDBDB5ADADADA59D9D9D958D8D8D8),
|
||||
.INIT_1C(256'h67E7E7E766E6E6E665E5E5E564E4E4E463E3E3E362E2E2E261E1E1E160E0E0E0),
|
||||
.INIT_1D(256'h6FEFEFEF6EEEEEEE6DEDEDED6CECECEC6BEBEBEB6AEAEAEA69E9E9E968E8E8E8),
|
||||
.INIT_1E(256'h77F7F7F776F6F6F675F5F5F574F4F4F473F3F3F372F2F2F271F1F1F170F0F0F0),
|
||||
.INIT_1F(256'h7FFFFFFF7EFEFEFE7DFDFDFD7CFCFCFC7BFBFBFB7AFAFAFA79F9F9F978F8F8F8),
|
||||
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_A(18'h00000),
|
||||
.INIT_B(18'h00000),
|
||||
.INIT_FILE("NONE"),
|
||||
.IS_CLKARDCLK_INVERTED(1'b0),
|
||||
.IS_CLKBWRCLK_INVERTED(1'b0),
|
||||
.IS_ENARDEN_INVERTED(1'b0),
|
||||
.IS_ENBWREN_INVERTED(1'b0),
|
||||
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
|
||||
.IS_RSTRAMB_INVERTED(1'b0),
|
||||
.IS_RSTREGARSTREG_INVERTED(1'b0),
|
||||
.IS_RSTREGB_INVERTED(1'b0),
|
||||
.RAM_MODE("TDP"),
|
||||
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
|
||||
.READ_WIDTH_A(18),
|
||||
.READ_WIDTH_B(18),
|
||||
.RSTREG_PRIORITY_A("REGCE"),
|
||||
.RSTREG_PRIORITY_B("REGCE"),
|
||||
.SIM_COLLISION_CHECK("ALL"),
|
||||
.SIM_DEVICE("7SERIES"),
|
||||
.SRVAL_A(18'h00000),
|
||||
.SRVAL_B(18'h00000),
|
||||
.WRITE_MODE_A("WRITE_FIRST"),
|
||||
.WRITE_MODE_B("WRITE_FIRST"),
|
||||
.WRITE_WIDTH_A(18),
|
||||
.WRITE_WIDTH_B(18))
|
||||
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram
|
||||
(.ADDRARDADDR({1'b0,addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.ADDRBWRADDR({1'b0,addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
|
||||
.CLKARDCLK(clka),
|
||||
.CLKBWRCLK(clka),
|
||||
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DIPADIP({1'b0,1'b0}),
|
||||
.DIPBDIP({1'b0,1'b0}),
|
||||
.DOADO(douta[15:0]),
|
||||
.DOBDO(douta[31:16]),
|
||||
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 }),
|
||||
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 }),
|
||||
.ENARDEN(1'b1),
|
||||
.ENBWREN(1'b1),
|
||||
.REGCEAREGCE(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.RSTRAMARSTRAM(1'b0),
|
||||
.RSTRAMB(1'b0),
|
||||
.RSTREGARSTREG(1'b0),
|
||||
.RSTREGB(1'b0),
|
||||
.WEA({1'b0,1'b0}),
|
||||
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
||||
module hop_rom_blk_mem_gen_top
|
||||
(douta,
|
||||
clka,
|
||||
addra);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
|
||||
hop_rom_blk_mem_gen_generic_cstr \valid.cstr
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta));
|
||||
endmodule
|
||||
|
||||
(* C_ADDRA_WIDTH = "8" *) (* C_ADDRB_WIDTH = "8" *) (* C_ALGORITHM = "1" *)
|
||||
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
|
||||
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
|
||||
(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
|
||||
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
|
||||
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
|
||||
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
|
||||
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.375199 mW" *)
|
||||
(* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
|
||||
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
|
||||
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
|
||||
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
|
||||
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
|
||||
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "hop_rom.mem" *)
|
||||
(* C_INIT_FILE_NAME = "hop_rom.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
|
||||
(* C_MEM_TYPE = "3" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
|
||||
(* C_READ_DEPTH_A = "256" *) (* C_READ_DEPTH_B = "256" *) (* C_READ_LATENCY_A = "1" *)
|
||||
(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "32" *) (* C_READ_WIDTH_B = "32" *)
|
||||
(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *)
|
||||
(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *)
|
||||
(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *)
|
||||
(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *)
|
||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "256" *)
|
||||
(* C_WRITE_DEPTH_B = "256" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||
(* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *) (* C_XDEVICEFAMILY = "kintex7" *)
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3" *) (* downgradeipidentifiedwarnings = "yes" *)
|
||||
module hop_rom_blk_mem_gen_v8_4_3
|
||||
(clka,
|
||||
rsta,
|
||||
ena,
|
||||
regcea,
|
||||
wea,
|
||||
addra,
|
||||
dina,
|
||||
douta,
|
||||
clkb,
|
||||
rstb,
|
||||
enb,
|
||||
regceb,
|
||||
web,
|
||||
addrb,
|
||||
dinb,
|
||||
doutb,
|
||||
injectsbiterr,
|
||||
injectdbiterr,
|
||||
eccpipece,
|
||||
sbiterr,
|
||||
dbiterr,
|
||||
rdaddrecc,
|
||||
sleep,
|
||||
deepsleep,
|
||||
shutdown,
|
||||
rsta_busy,
|
||||
rstb_busy,
|
||||
s_aclk,
|
||||
s_aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
s_axi_injectsbiterr,
|
||||
s_axi_injectdbiterr,
|
||||
s_axi_sbiterr,
|
||||
s_axi_dbiterr,
|
||||
s_axi_rdaddrecc);
|
||||
input clka;
|
||||
input rsta;
|
||||
input ena;
|
||||
input regcea;
|
||||
input [0:0]wea;
|
||||
input [7:0]addra;
|
||||
input [31:0]dina;
|
||||
output [31:0]douta;
|
||||
input clkb;
|
||||
input rstb;
|
||||
input enb;
|
||||
input regceb;
|
||||
input [0:0]web;
|
||||
input [7:0]addrb;
|
||||
input [31:0]dinb;
|
||||
output [31:0]doutb;
|
||||
input injectsbiterr;
|
||||
input injectdbiterr;
|
||||
input eccpipece;
|
||||
output sbiterr;
|
||||
output dbiterr;
|
||||
output [7:0]rdaddrecc;
|
||||
input sleep;
|
||||
input deepsleep;
|
||||
input shutdown;
|
||||
output rsta_busy;
|
||||
output rstb_busy;
|
||||
input s_aclk;
|
||||
input s_aresetn;
|
||||
input [3:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [7:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [0:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [3:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [3:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [7:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [3:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
input s_axi_injectsbiterr;
|
||||
input s_axi_injectdbiterr;
|
||||
output s_axi_sbiterr;
|
||||
output s_axi_dbiterr;
|
||||
output [7:0]s_axi_rdaddrecc;
|
||||
|
||||
wire \<const0> ;
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
|
||||
assign dbiterr = \<const0> ;
|
||||
assign doutb[31] = \<const0> ;
|
||||
assign doutb[30] = \<const0> ;
|
||||
assign doutb[29] = \<const0> ;
|
||||
assign doutb[28] = \<const0> ;
|
||||
assign doutb[27] = \<const0> ;
|
||||
assign doutb[26] = \<const0> ;
|
||||
assign doutb[25] = \<const0> ;
|
||||
assign doutb[24] = \<const0> ;
|
||||
assign doutb[23] = \<const0> ;
|
||||
assign doutb[22] = \<const0> ;
|
||||
assign doutb[21] = \<const0> ;
|
||||
assign doutb[20] = \<const0> ;
|
||||
assign doutb[19] = \<const0> ;
|
||||
assign doutb[18] = \<const0> ;
|
||||
assign doutb[17] = \<const0> ;
|
||||
assign doutb[16] = \<const0> ;
|
||||
assign doutb[15] = \<const0> ;
|
||||
assign doutb[14] = \<const0> ;
|
||||
assign doutb[13] = \<const0> ;
|
||||
assign doutb[12] = \<const0> ;
|
||||
assign doutb[11] = \<const0> ;
|
||||
assign doutb[10] = \<const0> ;
|
||||
assign doutb[9] = \<const0> ;
|
||||
assign doutb[8] = \<const0> ;
|
||||
assign doutb[7] = \<const0> ;
|
||||
assign doutb[6] = \<const0> ;
|
||||
assign doutb[5] = \<const0> ;
|
||||
assign doutb[4] = \<const0> ;
|
||||
assign doutb[3] = \<const0> ;
|
||||
assign doutb[2] = \<const0> ;
|
||||
assign doutb[1] = \<const0> ;
|
||||
assign doutb[0] = \<const0> ;
|
||||
assign rdaddrecc[7] = \<const0> ;
|
||||
assign rdaddrecc[6] = \<const0> ;
|
||||
assign rdaddrecc[5] = \<const0> ;
|
||||
assign rdaddrecc[4] = \<const0> ;
|
||||
assign rdaddrecc[3] = \<const0> ;
|
||||
assign rdaddrecc[2] = \<const0> ;
|
||||
assign rdaddrecc[1] = \<const0> ;
|
||||
assign rdaddrecc[0] = \<const0> ;
|
||||
assign rsta_busy = \<const0> ;
|
||||
assign rstb_busy = \<const0> ;
|
||||
assign s_axi_arready = \<const0> ;
|
||||
assign s_axi_awready = \<const0> ;
|
||||
assign s_axi_bid[3] = \<const0> ;
|
||||
assign s_axi_bid[2] = \<const0> ;
|
||||
assign s_axi_bid[1] = \<const0> ;
|
||||
assign s_axi_bid[0] = \<const0> ;
|
||||
assign s_axi_bresp[1] = \<const0> ;
|
||||
assign s_axi_bresp[0] = \<const0> ;
|
||||
assign s_axi_bvalid = \<const0> ;
|
||||
assign s_axi_dbiterr = \<const0> ;
|
||||
assign s_axi_rdaddrecc[7] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[6] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[5] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[4] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[3] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[2] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[1] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[0] = \<const0> ;
|
||||
assign s_axi_rdata[31] = \<const0> ;
|
||||
assign s_axi_rdata[30] = \<const0> ;
|
||||
assign s_axi_rdata[29] = \<const0> ;
|
||||
assign s_axi_rdata[28] = \<const0> ;
|
||||
assign s_axi_rdata[27] = \<const0> ;
|
||||
assign s_axi_rdata[26] = \<const0> ;
|
||||
assign s_axi_rdata[25] = \<const0> ;
|
||||
assign s_axi_rdata[24] = \<const0> ;
|
||||
assign s_axi_rdata[23] = \<const0> ;
|
||||
assign s_axi_rdata[22] = \<const0> ;
|
||||
assign s_axi_rdata[21] = \<const0> ;
|
||||
assign s_axi_rdata[20] = \<const0> ;
|
||||
assign s_axi_rdata[19] = \<const0> ;
|
||||
assign s_axi_rdata[18] = \<const0> ;
|
||||
assign s_axi_rdata[17] = \<const0> ;
|
||||
assign s_axi_rdata[16] = \<const0> ;
|
||||
assign s_axi_rdata[15] = \<const0> ;
|
||||
assign s_axi_rdata[14] = \<const0> ;
|
||||
assign s_axi_rdata[13] = \<const0> ;
|
||||
assign s_axi_rdata[12] = \<const0> ;
|
||||
assign s_axi_rdata[11] = \<const0> ;
|
||||
assign s_axi_rdata[10] = \<const0> ;
|
||||
assign s_axi_rdata[9] = \<const0> ;
|
||||
assign s_axi_rdata[8] = \<const0> ;
|
||||
assign s_axi_rdata[7] = \<const0> ;
|
||||
assign s_axi_rdata[6] = \<const0> ;
|
||||
assign s_axi_rdata[5] = \<const0> ;
|
||||
assign s_axi_rdata[4] = \<const0> ;
|
||||
assign s_axi_rdata[3] = \<const0> ;
|
||||
assign s_axi_rdata[2] = \<const0> ;
|
||||
assign s_axi_rdata[1] = \<const0> ;
|
||||
assign s_axi_rdata[0] = \<const0> ;
|
||||
assign s_axi_rid[3] = \<const0> ;
|
||||
assign s_axi_rid[2] = \<const0> ;
|
||||
assign s_axi_rid[1] = \<const0> ;
|
||||
assign s_axi_rid[0] = \<const0> ;
|
||||
assign s_axi_rlast = \<const0> ;
|
||||
assign s_axi_rresp[1] = \<const0> ;
|
||||
assign s_axi_rresp[0] = \<const0> ;
|
||||
assign s_axi_rvalid = \<const0> ;
|
||||
assign s_axi_sbiterr = \<const0> ;
|
||||
assign s_axi_wready = \<const0> ;
|
||||
assign sbiterr = \<const0> ;
|
||||
GND GND
|
||||
(.G(\<const0> ));
|
||||
hop_rom_blk_mem_gen_v8_4_3_synth inst_blk_mem_gen
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3_synth" *)
|
||||
module hop_rom_blk_mem_gen_v8_4_3_synth
|
||||
(douta,
|
||||
clka,
|
||||
addra);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
|
||||
wire [7:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]douta;
|
||||
|
||||
hop_rom_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+869
@@ -0,0 +1,869 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:15:57 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.vhdl
|
||||
-- Design : hop_rom
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity hop_rom_blk_mem_gen_prim_wrapper_init is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
||||
end hop_rom_blk_mem_gen_prim_wrapper_init;
|
||||
|
||||
architecture STRUCTURE of hop_rom_blk_mem_gen_prim_wrapper_init is
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
|
||||
attribute box_type : string;
|
||||
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
|
||||
begin
|
||||
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
|
||||
generic map(
|
||||
DOA_REG => 0,
|
||||
DOB_REG => 0,
|
||||
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_00 => X"8707070886060607850505068404040583030304820202038101010280000001",
|
||||
INIT_01 => X"8F0F0F108E0E0E0F8D0D0D0E8C0C0C0D8B0B0B0C8A0A0A0B8909090A88080809",
|
||||
INIT_02 => X"9717171896161617951515169414141593131314921212139111111290101011",
|
||||
INIT_03 => X"9F1F1F209E1E1E1F9D1D1D1E9C1C1C1D9B1B1B1C9A1A1A1B9919191A98181819",
|
||||
INIT_04 => X"A7272728A6262627A5252526A4242425A3232324A2222223A1212122A0202021",
|
||||
INIT_05 => X"AF2F2F30AE2E2E2FAD2D2D2EAC2C2C2DAB2B2B2CAA2A2A2BA929292AA8282829",
|
||||
INIT_06 => X"B7373738B6363637B5353536B4343435B3333334B2323233B1313132B0303031",
|
||||
INIT_07 => X"BF3F3F40BE3E3E3FBD3D3D3EBC3C3C3DBB3B3B3CBA3A3A3BB939393AB8383839",
|
||||
INIT_08 => X"C7474748C6464647C5454546C4444445C3434344C2424243C1414142C0404041",
|
||||
INIT_09 => X"CF4F4F50CE4E4E4FCD4D4D4ECC4C4C4DCB4B4B4CCA4A4A4BC949494AC8484849",
|
||||
INIT_0A => X"D7575758D6565657D5555556D4545455D3535354D2525253D1515152D0505051",
|
||||
INIT_0B => X"DF5F5F60DE5E5E5FDD5D5D5EDC5C5C5DDB5B5B5CDA5A5A5BD959595AD8585859",
|
||||
INIT_0C => X"E7676768E6666667E5656566E4646465E3636364E2626263E1616162E0606061",
|
||||
INIT_0D => X"EF6F6F70EE6E6E6FED6D6D6EEC6C6C6DEB6B6B6CEA6A6A6BE969696AE8686869",
|
||||
INIT_0E => X"F7777778F6767677F5757576F4747475F3737374F2727273F1717172F0707071",
|
||||
INIT_0F => X"FF7F7F80FE7E7E7FFD7D7D7EFC7C7C7DFB7B7B7CFA7A7A7BF979797AF8787879",
|
||||
INIT_10 => X"0787878706868686058585850484848403838383028282820181818100808080",
|
||||
INIT_11 => X"0F8F8F8F0E8E8E8E0D8D8D8D0C8C8C8C0B8B8B8B0A8A8A8A0989898908888888",
|
||||
INIT_12 => X"1797979716969696159595951494949413939393129292921191919110909090",
|
||||
INIT_13 => X"1F9F9F9F1E9E9E9E1D9D9D9D1C9C9C9C1B9B9B9B1A9A9A9A1999999918989898",
|
||||
INIT_14 => X"27A7A7A726A6A6A625A5A5A524A4A4A423A3A3A322A2A2A221A1A1A120A0A0A0",
|
||||
INIT_15 => X"2FAFAFAF2EAEAEAE2DADADAD2CACACAC2BABABAB2AAAAAAA29A9A9A928A8A8A8",
|
||||
INIT_16 => X"37B7B7B736B6B6B635B5B5B534B4B4B433B3B3B332B2B2B231B1B1B130B0B0B0",
|
||||
INIT_17 => X"3FBFBFBF3EBEBEBE3DBDBDBD3CBCBCBC3BBBBBBB3ABABABA39B9B9B938B8B8B8",
|
||||
INIT_18 => X"47C7C7C746C6C6C645C5C5C544C4C4C443C3C3C342C2C2C241C1C1C140C0C0C0",
|
||||
INIT_19 => X"4FCFCFCF4ECECECE4DCDCDCD4CCCCCCC4BCBCBCB4ACACACA49C9C9C948C8C8C8",
|
||||
INIT_1A => X"57D7D7D756D6D6D655D5D5D554D4D4D453D3D3D352D2D2D251D1D1D150D0D0D0",
|
||||
INIT_1B => X"5FDFDFDF5EDEDEDE5DDDDDDD5CDCDCDC5BDBDBDB5ADADADA59D9D9D958D8D8D8",
|
||||
INIT_1C => X"67E7E7E766E6E6E665E5E5E564E4E4E463E3E3E362E2E2E261E1E1E160E0E0E0",
|
||||
INIT_1D => X"6FEFEFEF6EEEEEEE6DEDEDED6CECECEC6BEBEBEB6AEAEAEA69E9E9E968E8E8E8",
|
||||
INIT_1E => X"77F7F7F776F6F6F675F5F5F574F4F4F473F3F3F372F2F2F271F1F1F170F0F0F0",
|
||||
INIT_1F => X"7FFFFFFF7EFEFEFE7DFDFDFD7CFCFCFC7BFBFBFB7AFAFAFA79F9F9F978F8F8F8",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_A => X"00000",
|
||||
INIT_B => X"00000",
|
||||
INIT_FILE => "NONE",
|
||||
IS_CLKARDCLK_INVERTED => '0',
|
||||
IS_CLKBWRCLK_INVERTED => '0',
|
||||
IS_ENARDEN_INVERTED => '0',
|
||||
IS_ENBWREN_INVERTED => '0',
|
||||
IS_RSTRAMARSTRAM_INVERTED => '0',
|
||||
IS_RSTRAMB_INVERTED => '0',
|
||||
IS_RSTREGARSTREG_INVERTED => '0',
|
||||
IS_RSTREGB_INVERTED => '0',
|
||||
RAM_MODE => "TDP",
|
||||
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
|
||||
READ_WIDTH_A => 18,
|
||||
READ_WIDTH_B => 18,
|
||||
RSTREG_PRIORITY_A => "REGCE",
|
||||
RSTREG_PRIORITY_B => "REGCE",
|
||||
SIM_COLLISION_CHECK => "ALL",
|
||||
SIM_DEVICE => "7SERIES",
|
||||
SRVAL_A => X"00000",
|
||||
SRVAL_B => X"00000",
|
||||
WRITE_MODE_A => "WRITE_FIRST",
|
||||
WRITE_MODE_B => "WRITE_FIRST",
|
||||
WRITE_WIDTH_A => 18,
|
||||
WRITE_WIDTH_B => 18
|
||||
)
|
||||
port map (
|
||||
ADDRARDADDR(13) => '0',
|
||||
ADDRARDADDR(12 downto 5) => addra(7 downto 0),
|
||||
ADDRARDADDR(4 downto 0) => B"00000",
|
||||
ADDRBWRADDR(13) => '0',
|
||||
ADDRBWRADDR(12 downto 5) => addra(7 downto 0),
|
||||
ADDRBWRADDR(4 downto 0) => B"10000",
|
||||
CLKARDCLK => clka,
|
||||
CLKBWRCLK => clka,
|
||||
DIADI(15 downto 0) => B"0000000000000000",
|
||||
DIBDI(15 downto 0) => B"0000000000000000",
|
||||
DIPADIP(1 downto 0) => B"00",
|
||||
DIPBDIP(1 downto 0) => B"00",
|
||||
DOADO(15 downto 0) => douta(15 downto 0),
|
||||
DOBDO(15 downto 0) => douta(31 downto 16),
|
||||
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\,
|
||||
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\,
|
||||
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\,
|
||||
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\,
|
||||
ENARDEN => '1',
|
||||
ENBWREN => '1',
|
||||
REGCEAREGCE => '0',
|
||||
REGCEB => '0',
|
||||
RSTRAMARSTRAM => '0',
|
||||
RSTRAMB => '0',
|
||||
RSTREGARSTREG => '0',
|
||||
RSTREGB => '0',
|
||||
WEA(1 downto 0) => B"00",
|
||||
WEBWE(3 downto 0) => B"0000"
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity hop_rom_blk_mem_gen_prim_width is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
||||
end hop_rom_blk_mem_gen_prim_width;
|
||||
|
||||
architecture STRUCTURE of hop_rom_blk_mem_gen_prim_width is
|
||||
begin
|
||||
\prim_init.ram\: entity work.hop_rom_blk_mem_gen_prim_wrapper_init
|
||||
port map (
|
||||
addra(7 downto 0) => addra(7 downto 0),
|
||||
clka => clka,
|
||||
douta(31 downto 0) => douta(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity hop_rom_blk_mem_gen_generic_cstr is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
||||
end hop_rom_blk_mem_gen_generic_cstr;
|
||||
|
||||
architecture STRUCTURE of hop_rom_blk_mem_gen_generic_cstr is
|
||||
begin
|
||||
\ramloop[0].ram.r\: entity work.hop_rom_blk_mem_gen_prim_width
|
||||
port map (
|
||||
addra(7 downto 0) => addra(7 downto 0),
|
||||
clka => clka,
|
||||
douta(31 downto 0) => douta(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity hop_rom_blk_mem_gen_top is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
||||
end hop_rom_blk_mem_gen_top;
|
||||
|
||||
architecture STRUCTURE of hop_rom_blk_mem_gen_top is
|
||||
begin
|
||||
\valid.cstr\: entity work.hop_rom_blk_mem_gen_generic_cstr
|
||||
port map (
|
||||
addra(7 downto 0) => addra(7 downto 0),
|
||||
clka => clka,
|
||||
douta(31 downto 0) => douta(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity hop_rom_blk_mem_gen_v8_4_3_synth is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth";
|
||||
end hop_rom_blk_mem_gen_v8_4_3_synth;
|
||||
|
||||
architecture STRUCTURE of hop_rom_blk_mem_gen_v8_4_3_synth is
|
||||
begin
|
||||
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.hop_rom_blk_mem_gen_top
|
||||
port map (
|
||||
addra(7 downto 0) => addra(7 downto 0),
|
||||
clka => clka,
|
||||
douta(31 downto 0) => douta(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity hop_rom_blk_mem_gen_v8_4_3 is
|
||||
port (
|
||||
clka : in STD_LOGIC;
|
||||
rsta : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
regcea : in STD_LOGIC;
|
||||
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clkb : in STD_LOGIC;
|
||||
rstb : in STD_LOGIC;
|
||||
enb : in STD_LOGIC;
|
||||
regceb : in STD_LOGIC;
|
||||
web : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
injectsbiterr : in STD_LOGIC;
|
||||
injectdbiterr : in STD_LOGIC;
|
||||
eccpipece : in STD_LOGIC;
|
||||
sbiterr : out STD_LOGIC;
|
||||
dbiterr : out STD_LOGIC;
|
||||
rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sleep : in STD_LOGIC;
|
||||
deepsleep : in STD_LOGIC;
|
||||
shutdown : in STD_LOGIC;
|
||||
rsta_busy : out STD_LOGIC;
|
||||
rstb_busy : out STD_LOGIC;
|
||||
s_aclk : in STD_LOGIC;
|
||||
s_aresetn : in STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
s_axi_injectsbiterr : in STD_LOGIC;
|
||||
s_axi_injectdbiterr : in STD_LOGIC;
|
||||
s_axi_sbiterr : out STD_LOGIC;
|
||||
s_axi_dbiterr : out STD_LOGIC;
|
||||
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
attribute C_ADDRA_WIDTH : integer;
|
||||
attribute C_ADDRA_WIDTH of hop_rom_blk_mem_gen_v8_4_3 : entity is 8;
|
||||
attribute C_ADDRB_WIDTH : integer;
|
||||
attribute C_ADDRB_WIDTH of hop_rom_blk_mem_gen_v8_4_3 : entity is 8;
|
||||
attribute C_ALGORITHM : integer;
|
||||
attribute C_ALGORITHM of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_AXI_ID_WIDTH : integer;
|
||||
attribute C_AXI_ID_WIDTH of hop_rom_blk_mem_gen_v8_4_3 : entity is 4;
|
||||
attribute C_AXI_SLAVE_TYPE : integer;
|
||||
attribute C_AXI_SLAVE_TYPE of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_AXI_TYPE : integer;
|
||||
attribute C_AXI_TYPE of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_BYTE_SIZE : integer;
|
||||
attribute C_BYTE_SIZE of hop_rom_blk_mem_gen_v8_4_3 : entity is 9;
|
||||
attribute C_COMMON_CLK : integer;
|
||||
attribute C_COMMON_CLK of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_COUNT_18K_BRAM : string;
|
||||
attribute C_COUNT_18K_BRAM of hop_rom_blk_mem_gen_v8_4_3 : entity is "1";
|
||||
attribute C_COUNT_36K_BRAM : string;
|
||||
attribute C_COUNT_36K_BRAM of hop_rom_blk_mem_gen_v8_4_3 : entity is "0";
|
||||
attribute C_CTRL_ECC_ALGO : string;
|
||||
attribute C_CTRL_ECC_ALGO of hop_rom_blk_mem_gen_v8_4_3 : entity is "NONE";
|
||||
attribute C_DEFAULT_DATA : string;
|
||||
attribute C_DEFAULT_DATA of hop_rom_blk_mem_gen_v8_4_3 : entity is "0";
|
||||
attribute C_DISABLE_WARN_BHV_COLL : integer;
|
||||
attribute C_DISABLE_WARN_BHV_COLL of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE : integer;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_ELABORATION_DIR : string;
|
||||
attribute C_ELABORATION_DIR of hop_rom_blk_mem_gen_v8_4_3 : entity is "./";
|
||||
attribute C_ENABLE_32BIT_ADDRESS : integer;
|
||||
attribute C_ENABLE_32BIT_ADDRESS of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_DEEPSLEEP_PIN : integer;
|
||||
attribute C_EN_DEEPSLEEP_PIN of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_ECC_PIPE : integer;
|
||||
attribute C_EN_ECC_PIPE of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_RDADDRA_CHG : integer;
|
||||
attribute C_EN_RDADDRA_CHG of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_RDADDRB_CHG : integer;
|
||||
attribute C_EN_RDADDRB_CHG of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_SAFETY_CKT : integer;
|
||||
attribute C_EN_SAFETY_CKT of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_SHUTDOWN_PIN : integer;
|
||||
attribute C_EN_SHUTDOWN_PIN of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_SLEEP_PIN : integer;
|
||||
attribute C_EN_SLEEP_PIN of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EST_POWER_SUMMARY : string;
|
||||
attribute C_EST_POWER_SUMMARY of hop_rom_blk_mem_gen_v8_4_3 : entity is "Estimated Power for IP : 3.375199 mW";
|
||||
attribute C_FAMILY : string;
|
||||
attribute C_FAMILY of hop_rom_blk_mem_gen_v8_4_3 : entity is "kintex7";
|
||||
attribute C_HAS_AXI_ID : integer;
|
||||
attribute C_HAS_AXI_ID of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_ENA : integer;
|
||||
attribute C_HAS_ENA of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_ENB : integer;
|
||||
attribute C_HAS_ENB of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_INJECTERR : integer;
|
||||
attribute C_HAS_INJECTERR of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_REGCEA : integer;
|
||||
attribute C_HAS_REGCEA of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_REGCEB : integer;
|
||||
attribute C_HAS_REGCEB of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_RSTA : integer;
|
||||
attribute C_HAS_RSTA of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_RSTB : integer;
|
||||
attribute C_HAS_RSTB of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_INITA_VAL : string;
|
||||
attribute C_INITA_VAL of hop_rom_blk_mem_gen_v8_4_3 : entity is "0";
|
||||
attribute C_INITB_VAL : string;
|
||||
attribute C_INITB_VAL of hop_rom_blk_mem_gen_v8_4_3 : entity is "0";
|
||||
attribute C_INIT_FILE : string;
|
||||
attribute C_INIT_FILE of hop_rom_blk_mem_gen_v8_4_3 : entity is "hop_rom.mem";
|
||||
attribute C_INIT_FILE_NAME : string;
|
||||
attribute C_INIT_FILE_NAME of hop_rom_blk_mem_gen_v8_4_3 : entity is "hop_rom.mif";
|
||||
attribute C_INTERFACE_TYPE : integer;
|
||||
attribute C_INTERFACE_TYPE of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_LOAD_INIT_FILE : integer;
|
||||
attribute C_LOAD_INIT_FILE of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_MEM_TYPE : integer;
|
||||
attribute C_MEM_TYPE of hop_rom_blk_mem_gen_v8_4_3 : entity is 3;
|
||||
attribute C_MUX_PIPELINE_STAGES : integer;
|
||||
attribute C_MUX_PIPELINE_STAGES of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_PRIM_TYPE : integer;
|
||||
attribute C_PRIM_TYPE of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_READ_DEPTH_A : integer;
|
||||
attribute C_READ_DEPTH_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 256;
|
||||
attribute C_READ_DEPTH_B : integer;
|
||||
attribute C_READ_DEPTH_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 256;
|
||||
attribute C_READ_LATENCY_A : integer;
|
||||
attribute C_READ_LATENCY_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_READ_LATENCY_B : integer;
|
||||
attribute C_READ_LATENCY_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_READ_WIDTH_A : integer;
|
||||
attribute C_READ_WIDTH_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 32;
|
||||
attribute C_READ_WIDTH_B : integer;
|
||||
attribute C_READ_WIDTH_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 32;
|
||||
attribute C_RSTRAM_A : integer;
|
||||
attribute C_RSTRAM_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_RSTRAM_B : integer;
|
||||
attribute C_RSTRAM_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_RST_PRIORITY_A : string;
|
||||
attribute C_RST_PRIORITY_A of hop_rom_blk_mem_gen_v8_4_3 : entity is "CE";
|
||||
attribute C_RST_PRIORITY_B : string;
|
||||
attribute C_RST_PRIORITY_B of hop_rom_blk_mem_gen_v8_4_3 : entity is "CE";
|
||||
attribute C_SIM_COLLISION_CHECK : string;
|
||||
attribute C_SIM_COLLISION_CHECK of hop_rom_blk_mem_gen_v8_4_3 : entity is "ALL";
|
||||
attribute C_USE_BRAM_BLOCK : integer;
|
||||
attribute C_USE_BRAM_BLOCK of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_BYTE_WEA : integer;
|
||||
attribute C_USE_BYTE_WEA of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_BYTE_WEB : integer;
|
||||
attribute C_USE_BYTE_WEB of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_DEFAULT_DATA : integer;
|
||||
attribute C_USE_DEFAULT_DATA of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_ECC : integer;
|
||||
attribute C_USE_ECC of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_SOFTECC : integer;
|
||||
attribute C_USE_SOFTECC of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_URAM : integer;
|
||||
attribute C_USE_URAM of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_WEA_WIDTH : integer;
|
||||
attribute C_WEA_WIDTH of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_WEB_WIDTH : integer;
|
||||
attribute C_WEB_WIDTH of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_WRITE_DEPTH_A : integer;
|
||||
attribute C_WRITE_DEPTH_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 256;
|
||||
attribute C_WRITE_DEPTH_B : integer;
|
||||
attribute C_WRITE_DEPTH_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 256;
|
||||
attribute C_WRITE_MODE_A : string;
|
||||
attribute C_WRITE_MODE_A of hop_rom_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST";
|
||||
attribute C_WRITE_MODE_B : string;
|
||||
attribute C_WRITE_MODE_B of hop_rom_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST";
|
||||
attribute C_WRITE_WIDTH_A : integer;
|
||||
attribute C_WRITE_WIDTH_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 32;
|
||||
attribute C_WRITE_WIDTH_B : integer;
|
||||
attribute C_WRITE_WIDTH_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 32;
|
||||
attribute C_XDEVICEFAMILY : string;
|
||||
attribute C_XDEVICEFAMILY of hop_rom_blk_mem_gen_v8_4_3 : entity is "kintex7";
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of hop_rom_blk_mem_gen_v8_4_3 : entity is "yes";
|
||||
end hop_rom_blk_mem_gen_v8_4_3;
|
||||
|
||||
architecture STRUCTURE of hop_rom_blk_mem_gen_v8_4_3 is
|
||||
signal \<const0>\ : STD_LOGIC;
|
||||
begin
|
||||
dbiterr <= \<const0>\;
|
||||
doutb(31) <= \<const0>\;
|
||||
doutb(30) <= \<const0>\;
|
||||
doutb(29) <= \<const0>\;
|
||||
doutb(28) <= \<const0>\;
|
||||
doutb(27) <= \<const0>\;
|
||||
doutb(26) <= \<const0>\;
|
||||
doutb(25) <= \<const0>\;
|
||||
doutb(24) <= \<const0>\;
|
||||
doutb(23) <= \<const0>\;
|
||||
doutb(22) <= \<const0>\;
|
||||
doutb(21) <= \<const0>\;
|
||||
doutb(20) <= \<const0>\;
|
||||
doutb(19) <= \<const0>\;
|
||||
doutb(18) <= \<const0>\;
|
||||
doutb(17) <= \<const0>\;
|
||||
doutb(16) <= \<const0>\;
|
||||
doutb(15) <= \<const0>\;
|
||||
doutb(14) <= \<const0>\;
|
||||
doutb(13) <= \<const0>\;
|
||||
doutb(12) <= \<const0>\;
|
||||
doutb(11) <= \<const0>\;
|
||||
doutb(10) <= \<const0>\;
|
||||
doutb(9) <= \<const0>\;
|
||||
doutb(8) <= \<const0>\;
|
||||
doutb(7) <= \<const0>\;
|
||||
doutb(6) <= \<const0>\;
|
||||
doutb(5) <= \<const0>\;
|
||||
doutb(4) <= \<const0>\;
|
||||
doutb(3) <= \<const0>\;
|
||||
doutb(2) <= \<const0>\;
|
||||
doutb(1) <= \<const0>\;
|
||||
doutb(0) <= \<const0>\;
|
||||
rdaddrecc(7) <= \<const0>\;
|
||||
rdaddrecc(6) <= \<const0>\;
|
||||
rdaddrecc(5) <= \<const0>\;
|
||||
rdaddrecc(4) <= \<const0>\;
|
||||
rdaddrecc(3) <= \<const0>\;
|
||||
rdaddrecc(2) <= \<const0>\;
|
||||
rdaddrecc(1) <= \<const0>\;
|
||||
rdaddrecc(0) <= \<const0>\;
|
||||
rsta_busy <= \<const0>\;
|
||||
rstb_busy <= \<const0>\;
|
||||
s_axi_arready <= \<const0>\;
|
||||
s_axi_awready <= \<const0>\;
|
||||
s_axi_bid(3) <= \<const0>\;
|
||||
s_axi_bid(2) <= \<const0>\;
|
||||
s_axi_bid(1) <= \<const0>\;
|
||||
s_axi_bid(0) <= \<const0>\;
|
||||
s_axi_bresp(1) <= \<const0>\;
|
||||
s_axi_bresp(0) <= \<const0>\;
|
||||
s_axi_bvalid <= \<const0>\;
|
||||
s_axi_dbiterr <= \<const0>\;
|
||||
s_axi_rdaddrecc(7) <= \<const0>\;
|
||||
s_axi_rdaddrecc(6) <= \<const0>\;
|
||||
s_axi_rdaddrecc(5) <= \<const0>\;
|
||||
s_axi_rdaddrecc(4) <= \<const0>\;
|
||||
s_axi_rdaddrecc(3) <= \<const0>\;
|
||||
s_axi_rdaddrecc(2) <= \<const0>\;
|
||||
s_axi_rdaddrecc(1) <= \<const0>\;
|
||||
s_axi_rdaddrecc(0) <= \<const0>\;
|
||||
s_axi_rdata(31) <= \<const0>\;
|
||||
s_axi_rdata(30) <= \<const0>\;
|
||||
s_axi_rdata(29) <= \<const0>\;
|
||||
s_axi_rdata(28) <= \<const0>\;
|
||||
s_axi_rdata(27) <= \<const0>\;
|
||||
s_axi_rdata(26) <= \<const0>\;
|
||||
s_axi_rdata(25) <= \<const0>\;
|
||||
s_axi_rdata(24) <= \<const0>\;
|
||||
s_axi_rdata(23) <= \<const0>\;
|
||||
s_axi_rdata(22) <= \<const0>\;
|
||||
s_axi_rdata(21) <= \<const0>\;
|
||||
s_axi_rdata(20) <= \<const0>\;
|
||||
s_axi_rdata(19) <= \<const0>\;
|
||||
s_axi_rdata(18) <= \<const0>\;
|
||||
s_axi_rdata(17) <= \<const0>\;
|
||||
s_axi_rdata(16) <= \<const0>\;
|
||||
s_axi_rdata(15) <= \<const0>\;
|
||||
s_axi_rdata(14) <= \<const0>\;
|
||||
s_axi_rdata(13) <= \<const0>\;
|
||||
s_axi_rdata(12) <= \<const0>\;
|
||||
s_axi_rdata(11) <= \<const0>\;
|
||||
s_axi_rdata(10) <= \<const0>\;
|
||||
s_axi_rdata(9) <= \<const0>\;
|
||||
s_axi_rdata(8) <= \<const0>\;
|
||||
s_axi_rdata(7) <= \<const0>\;
|
||||
s_axi_rdata(6) <= \<const0>\;
|
||||
s_axi_rdata(5) <= \<const0>\;
|
||||
s_axi_rdata(4) <= \<const0>\;
|
||||
s_axi_rdata(3) <= \<const0>\;
|
||||
s_axi_rdata(2) <= \<const0>\;
|
||||
s_axi_rdata(1) <= \<const0>\;
|
||||
s_axi_rdata(0) <= \<const0>\;
|
||||
s_axi_rid(3) <= \<const0>\;
|
||||
s_axi_rid(2) <= \<const0>\;
|
||||
s_axi_rid(1) <= \<const0>\;
|
||||
s_axi_rid(0) <= \<const0>\;
|
||||
s_axi_rlast <= \<const0>\;
|
||||
s_axi_rresp(1) <= \<const0>\;
|
||||
s_axi_rresp(0) <= \<const0>\;
|
||||
s_axi_rvalid <= \<const0>\;
|
||||
s_axi_sbiterr <= \<const0>\;
|
||||
s_axi_wready <= \<const0>\;
|
||||
sbiterr <= \<const0>\;
|
||||
GND: unisim.vcomponents.GND
|
||||
port map (
|
||||
G => \<const0>\
|
||||
);
|
||||
inst_blk_mem_gen: entity work.hop_rom_blk_mem_gen_v8_4_3_synth
|
||||
port map (
|
||||
addra(7 downto 0) => addra(7 downto 0),
|
||||
clka => clka,
|
||||
douta(31 downto 0) => douta(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity hop_rom is
|
||||
port (
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of hop_rom : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of hop_rom : entity is "hop_rom,blk_mem_gen_v8_4_3,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of hop_rom : entity is "yes";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of hop_rom : entity is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
end hop_rom;
|
||||
|
||||
architecture STRUCTURE of hop_rom is
|
||||
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute C_ADDRA_WIDTH : integer;
|
||||
attribute C_ADDRA_WIDTH of U0 : label is 8;
|
||||
attribute C_ADDRB_WIDTH : integer;
|
||||
attribute C_ADDRB_WIDTH of U0 : label is 8;
|
||||
attribute C_ALGORITHM : integer;
|
||||
attribute C_ALGORITHM of U0 : label is 1;
|
||||
attribute C_AXI_ID_WIDTH : integer;
|
||||
attribute C_AXI_ID_WIDTH of U0 : label is 4;
|
||||
attribute C_AXI_SLAVE_TYPE : integer;
|
||||
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
|
||||
attribute C_AXI_TYPE : integer;
|
||||
attribute C_AXI_TYPE of U0 : label is 1;
|
||||
attribute C_BYTE_SIZE : integer;
|
||||
attribute C_BYTE_SIZE of U0 : label is 9;
|
||||
attribute C_COMMON_CLK : integer;
|
||||
attribute C_COMMON_CLK of U0 : label is 0;
|
||||
attribute C_COUNT_18K_BRAM : string;
|
||||
attribute C_COUNT_18K_BRAM of U0 : label is "1";
|
||||
attribute C_COUNT_36K_BRAM : string;
|
||||
attribute C_COUNT_36K_BRAM of U0 : label is "0";
|
||||
attribute C_CTRL_ECC_ALGO : string;
|
||||
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
|
||||
attribute C_DEFAULT_DATA : string;
|
||||
attribute C_DEFAULT_DATA of U0 : label is "0";
|
||||
attribute C_DISABLE_WARN_BHV_COLL : integer;
|
||||
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE : integer;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
|
||||
attribute C_ELABORATION_DIR : string;
|
||||
attribute C_ELABORATION_DIR of U0 : label is "./";
|
||||
attribute C_ENABLE_32BIT_ADDRESS : integer;
|
||||
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
|
||||
attribute C_EN_DEEPSLEEP_PIN : integer;
|
||||
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
|
||||
attribute C_EN_ECC_PIPE : integer;
|
||||
attribute C_EN_ECC_PIPE of U0 : label is 0;
|
||||
attribute C_EN_RDADDRA_CHG : integer;
|
||||
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
|
||||
attribute C_EN_RDADDRB_CHG : integer;
|
||||
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
|
||||
attribute C_EN_SAFETY_CKT : integer;
|
||||
attribute C_EN_SAFETY_CKT of U0 : label is 0;
|
||||
attribute C_EN_SHUTDOWN_PIN : integer;
|
||||
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
|
||||
attribute C_EN_SLEEP_PIN : integer;
|
||||
attribute C_EN_SLEEP_PIN of U0 : label is 0;
|
||||
attribute C_EST_POWER_SUMMARY : string;
|
||||
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.375199 mW";
|
||||
attribute C_FAMILY : string;
|
||||
attribute C_FAMILY of U0 : label is "kintex7";
|
||||
attribute C_HAS_AXI_ID : integer;
|
||||
attribute C_HAS_AXI_ID of U0 : label is 0;
|
||||
attribute C_HAS_ENA : integer;
|
||||
attribute C_HAS_ENA of U0 : label is 0;
|
||||
attribute C_HAS_ENB : integer;
|
||||
attribute C_HAS_ENB of U0 : label is 0;
|
||||
attribute C_HAS_INJECTERR : integer;
|
||||
attribute C_HAS_INJECTERR of U0 : label is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
|
||||
attribute C_HAS_REGCEA : integer;
|
||||
attribute C_HAS_REGCEA of U0 : label is 0;
|
||||
attribute C_HAS_REGCEB : integer;
|
||||
attribute C_HAS_REGCEB of U0 : label is 0;
|
||||
attribute C_HAS_RSTA : integer;
|
||||
attribute C_HAS_RSTA of U0 : label is 0;
|
||||
attribute C_HAS_RSTB : integer;
|
||||
attribute C_HAS_RSTB of U0 : label is 0;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
|
||||
attribute C_INITA_VAL : string;
|
||||
attribute C_INITA_VAL of U0 : label is "0";
|
||||
attribute C_INITB_VAL : string;
|
||||
attribute C_INITB_VAL of U0 : label is "0";
|
||||
attribute C_INIT_FILE : string;
|
||||
attribute C_INIT_FILE of U0 : label is "hop_rom.mem";
|
||||
attribute C_INIT_FILE_NAME : string;
|
||||
attribute C_INIT_FILE_NAME of U0 : label is "hop_rom.mif";
|
||||
attribute C_INTERFACE_TYPE : integer;
|
||||
attribute C_INTERFACE_TYPE of U0 : label is 0;
|
||||
attribute C_LOAD_INIT_FILE : integer;
|
||||
attribute C_LOAD_INIT_FILE of U0 : label is 1;
|
||||
attribute C_MEM_TYPE : integer;
|
||||
attribute C_MEM_TYPE of U0 : label is 3;
|
||||
attribute C_MUX_PIPELINE_STAGES : integer;
|
||||
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
|
||||
attribute C_PRIM_TYPE : integer;
|
||||
attribute C_PRIM_TYPE of U0 : label is 1;
|
||||
attribute C_READ_DEPTH_A : integer;
|
||||
attribute C_READ_DEPTH_A of U0 : label is 256;
|
||||
attribute C_READ_DEPTH_B : integer;
|
||||
attribute C_READ_DEPTH_B of U0 : label is 256;
|
||||
attribute C_READ_LATENCY_A : integer;
|
||||
attribute C_READ_LATENCY_A of U0 : label is 1;
|
||||
attribute C_READ_LATENCY_B : integer;
|
||||
attribute C_READ_LATENCY_B of U0 : label is 1;
|
||||
attribute C_READ_WIDTH_A : integer;
|
||||
attribute C_READ_WIDTH_A of U0 : label is 32;
|
||||
attribute C_READ_WIDTH_B : integer;
|
||||
attribute C_READ_WIDTH_B of U0 : label is 32;
|
||||
attribute C_RSTRAM_A : integer;
|
||||
attribute C_RSTRAM_A of U0 : label is 0;
|
||||
attribute C_RSTRAM_B : integer;
|
||||
attribute C_RSTRAM_B of U0 : label is 0;
|
||||
attribute C_RST_PRIORITY_A : string;
|
||||
attribute C_RST_PRIORITY_A of U0 : label is "CE";
|
||||
attribute C_RST_PRIORITY_B : string;
|
||||
attribute C_RST_PRIORITY_B of U0 : label is "CE";
|
||||
attribute C_SIM_COLLISION_CHECK : string;
|
||||
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
|
||||
attribute C_USE_BRAM_BLOCK : integer;
|
||||
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
|
||||
attribute C_USE_BYTE_WEA : integer;
|
||||
attribute C_USE_BYTE_WEA of U0 : label is 0;
|
||||
attribute C_USE_BYTE_WEB : integer;
|
||||
attribute C_USE_BYTE_WEB of U0 : label is 0;
|
||||
attribute C_USE_DEFAULT_DATA : integer;
|
||||
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
|
||||
attribute C_USE_ECC : integer;
|
||||
attribute C_USE_ECC of U0 : label is 0;
|
||||
attribute C_USE_SOFTECC : integer;
|
||||
attribute C_USE_SOFTECC of U0 : label is 0;
|
||||
attribute C_USE_URAM : integer;
|
||||
attribute C_USE_URAM of U0 : label is 0;
|
||||
attribute C_WEA_WIDTH : integer;
|
||||
attribute C_WEA_WIDTH of U0 : label is 1;
|
||||
attribute C_WEB_WIDTH : integer;
|
||||
attribute C_WEB_WIDTH of U0 : label is 1;
|
||||
attribute C_WRITE_DEPTH_A : integer;
|
||||
attribute C_WRITE_DEPTH_A of U0 : label is 256;
|
||||
attribute C_WRITE_DEPTH_B : integer;
|
||||
attribute C_WRITE_DEPTH_B of U0 : label is 256;
|
||||
attribute C_WRITE_MODE_A : string;
|
||||
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
|
||||
attribute C_WRITE_MODE_B : string;
|
||||
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
|
||||
attribute C_WRITE_WIDTH_A : integer;
|
||||
attribute C_WRITE_WIDTH_A of U0 : label is 32;
|
||||
attribute C_WRITE_WIDTH_B : integer;
|
||||
attribute C_WRITE_WIDTH_B of U0 : label is 32;
|
||||
attribute C_XDEVICEFAMILY : string;
|
||||
attribute C_XDEVICEFAMILY of U0 : label is "kintex7";
|
||||
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
|
||||
attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
begin
|
||||
U0: entity work.hop_rom_blk_mem_gen_v8_4_3
|
||||
port map (
|
||||
addra(7 downto 0) => addra(7 downto 0),
|
||||
addrb(7 downto 0) => B"00000000",
|
||||
clka => clka,
|
||||
clkb => '0',
|
||||
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
|
||||
deepsleep => '0',
|
||||
dina(31 downto 0) => B"00000000000000000000000000000000",
|
||||
dinb(31 downto 0) => B"00000000000000000000000000000000",
|
||||
douta(31 downto 0) => douta(31 downto 0),
|
||||
doutb(31 downto 0) => NLW_U0_doutb_UNCONNECTED(31 downto 0),
|
||||
eccpipece => '0',
|
||||
ena => '0',
|
||||
enb => '0',
|
||||
injectdbiterr => '0',
|
||||
injectsbiterr => '0',
|
||||
rdaddrecc(7 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(7 downto 0),
|
||||
regcea => '0',
|
||||
regceb => '0',
|
||||
rsta => '0',
|
||||
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
|
||||
rstb => '0',
|
||||
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
|
||||
s_aclk => '0',
|
||||
s_aresetn => '0',
|
||||
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
|
||||
s_axi_arburst(1 downto 0) => B"00",
|
||||
s_axi_arid(3 downto 0) => B"0000",
|
||||
s_axi_arlen(7 downto 0) => B"00000000",
|
||||
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
|
||||
s_axi_arsize(2 downto 0) => B"000",
|
||||
s_axi_arvalid => '0',
|
||||
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
|
||||
s_axi_awburst(1 downto 0) => B"00",
|
||||
s_axi_awid(3 downto 0) => B"0000",
|
||||
s_axi_awlen(7 downto 0) => B"00000000",
|
||||
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
|
||||
s_axi_awsize(2 downto 0) => B"000",
|
||||
s_axi_awvalid => '0',
|
||||
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
|
||||
s_axi_bready => '0',
|
||||
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
|
||||
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
|
||||
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
|
||||
s_axi_injectdbiterr => '0',
|
||||
s_axi_injectsbiterr => '0',
|
||||
s_axi_rdaddrecc(7 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(7 downto 0),
|
||||
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
|
||||
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
|
||||
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
|
||||
s_axi_rready => '0',
|
||||
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
|
||||
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
|
||||
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
|
||||
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
|
||||
s_axi_wlast => '0',
|
||||
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
|
||||
s_axi_wstrb(0) => '0',
|
||||
s_axi_wvalid => '0',
|
||||
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
|
||||
shutdown => '0',
|
||||
sleep => '0',
|
||||
wea(0) => '0',
|
||||
web(0) => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:15:57 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v
|
||||
// Design : hop_rom
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||
module hop_rom(clka, addra, douta)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clka,addra[7:0],douta[31:0]" */;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
output [31:0]douta;
|
||||
endmodule
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:15:57 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl
|
||||
-- Design : hop_rom
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity hop_rom is
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end hop_rom;
|
||||
|
||||
architecture stub of hop_rom is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clka,addra[7:0],douta[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
+174
@@ -0,0 +1,174 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
| Date : Sat Mar 18 23:15:57 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file hop_rom_utilization_synth.rpt -pb hop_rom_utilization_synth.pb
|
||||
| Design : hop_rom
|
||||
| Device : 7k410tffg900-2
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 0 | 0 | 254200 | 0.00 |
|
||||
| LUT as Logic | 0 | 0 | 254200 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 90600 | 0.00 |
|
||||
| Slice Registers | 0 | 0 | 508400 | 0.00 |
|
||||
| Register as Flip Flop | 0 | 0 | 508400 | 0.00 |
|
||||
| Register as Latch | 0 | 0 | 508400 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 127100 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 63550 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0.5 | 0 | 795 | 0.06 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 |
|
||||
| RAMB18 | 1 | 0 | 1590 | 0.06 |
|
||||
| RAMB18E1 only | 1 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 1540 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 500 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 480 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 500 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 500 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| RAMB18E1 | 1 | Block Memory |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log hop_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source hop_rom.tcl
|
||||
+35
@@ -0,0 +1,35 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31387838:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6464735f636f6d70696c65725f76365f305f31385c6464735f3332625f3862:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c686f705f726f6d:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6872635f36345f31325f303235:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:34:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3465326630323830363633633462666538363165633665366337636266623331:506172656e742050412070726f6a656374204944:00
|
||||
eof:1911739650
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log hop_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source hop_rom.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
+43
@@ -0,0 +1,43 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log hop_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source hop_rom.tcl
|
||||
BIN
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user