Archived
rename duifei_basic to duifei_cmos_1t2r, add duifei_cmos_1t1r
This commit is contained in:
@@ -0,0 +1,77 @@
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// ***************************************************************************
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||||
// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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||||
// This will allow to generate bit files and not release the source code,
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||||
// as long as it attaches to an ADI device.
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||||
//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_rst (
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// clock reset
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input rst_async,
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input clk,
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output rstn,
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output reg rst);
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// internal registers
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reg rst_async_d1 = 1'd1;
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reg rst_async_d2 = 1'd1;
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reg rst_sync = 1'd1;
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reg rst_sync_d = 1'd1;
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// simple reset synchronizer
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always @(posedge clk or posedge rst_async) begin
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if (rst_async) begin
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rst_async_d1 <= 1'b1;
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rst_async_d2 <= 1'b1;
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rst_sync <= 1'b1;
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end else begin
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rst_async_d1 <= 1'b0;
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rst_async_d2 <= rst_async_d1;
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rst_sync <= rst_async_d2;
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end
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end
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// two-stage synchronizer to prevent metastability on the falling edge
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always @(posedge clk) begin
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rst_sync_d <= rst_sync;
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rst <= rst_sync_d;
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end
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assign rstn = ~rst;
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@@ -0,0 +1,239 @@
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
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||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
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||||
// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_axi #(
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parameter AXI_ADDRESS_WIDTH = 16) (
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// reset and clocks
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input up_rstn,
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input up_clk,
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// axi4 interface
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input up_axi_awvalid,
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input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr,
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output up_axi_awready,
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input up_axi_wvalid,
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input [31:0] up_axi_wdata,
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input [ 3:0] up_axi_wstrb,
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output up_axi_wready,
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output up_axi_bvalid,
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output [ 1:0] up_axi_bresp,
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input up_axi_bready,
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input up_axi_arvalid,
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input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr,
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output up_axi_arready,
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output up_axi_rvalid,
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output [ 1:0] up_axi_rresp,
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output [31:0] up_axi_rdata,
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input up_axi_rready,
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// pcore interface
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output up_wreq,
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output [(AXI_ADDRESS_WIDTH-3):0] up_waddr,
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output [31:0] up_wdata,
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input up_wack,
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output up_rreq,
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output [(AXI_ADDRESS_WIDTH-3):0] up_raddr,
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input [31:0] up_rdata,
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input up_rack);
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// internal registers
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reg up_axi_awready_int = 'd0;
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reg up_axi_wready_int = 'd0;
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reg up_axi_bvalid_int = 'd0;
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reg up_wack_d = 'd0;
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reg up_wsel = 'd0;
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reg up_wreq_int = 'd0;
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reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0;
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reg [31:0] up_wdata_int = 'd0;
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reg [ 4:0] up_wcount = 'd0;
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reg up_axi_arready_int = 'd0;
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reg up_axi_rvalid_int = 'd0;
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reg [31:0] up_axi_rdata_int = 'd0;
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reg up_rack_d = 'd0;
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reg [31:0] up_rdata_d = 'd0;
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reg up_rsel = 'd0;
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reg up_rreq_int = 'd0;
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reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0;
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reg [ 4:0] up_rcount = 'd0;
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// internal signals
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wire up_wack_s;
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wire up_rack_s;
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wire [31:0] up_rdata_s;
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// write channel interface
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assign up_axi_awready = up_axi_awready_int;
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assign up_axi_wready = up_axi_wready_int;
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assign up_axi_bvalid = up_axi_bvalid_int;
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assign up_axi_bresp = 2'd0;
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_axi_awready_int <= 'd0;
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up_axi_wready_int <= 'd0;
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up_axi_bvalid_int <= 'd0;
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end else begin
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if (up_axi_awready_int == 1'b1) begin
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up_axi_awready_int <= 1'b0;
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end else if (up_wack_s == 1'b1) begin
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up_axi_awready_int <= 1'b1;
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end
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if (up_axi_wready_int == 1'b1) begin
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up_axi_wready_int <= 1'b0;
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end else if (up_wack_s == 1'b1) begin
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up_axi_wready_int <= 1'b1;
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end
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if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
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up_axi_bvalid_int <= 1'b0;
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end else if (up_wack_d == 1'b1) begin
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up_axi_bvalid_int <= 1'b1;
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end
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end
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end
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assign up_wreq = up_wreq_int;
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assign up_waddr = up_waddr_int;
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assign up_wdata = up_wdata_int;
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assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_wack_d <= 'd0;
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up_wsel <= 'd0;
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up_wreq_int <= 'd0;
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up_waddr_int <= 'd0;
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up_wdata_int <= 'd0;
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up_wcount <= 'd0;
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end else begin
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up_wack_d <= up_wack_s;
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if (up_wsel == 1'b1) begin
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if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
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up_wsel <= 1'b0;
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end
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up_wreq_int <= 1'b0;
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end else begin
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up_wsel <= up_axi_awvalid & up_axi_wvalid;
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up_wreq_int <= up_axi_awvalid & up_axi_wvalid;
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up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2];
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up_wdata_int <= up_axi_wdata;
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end
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if (up_wack_s == 1'b1) begin
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up_wcount <= 5'h00;
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end else if (up_wcount[4] == 1'b1) begin
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up_wcount <= up_wcount + 1'b1;
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end else if (up_wreq_int == 1'b1) begin
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up_wcount <= 5'h10;
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end
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end
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end
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// read channel interface
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assign up_axi_arready = up_axi_arready_int;
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assign up_axi_rvalid = up_axi_rvalid_int;
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assign up_axi_rdata = up_axi_rdata_int;
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assign up_axi_rresp = 2'd0;
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_axi_arready_int <= 'd0;
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up_axi_rvalid_int <= 'd0;
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up_axi_rdata_int <= 'd0;
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end else begin
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if (up_axi_arready_int == 1'b1) begin
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up_axi_arready_int <= 1'b0;
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end else if (up_rack_s == 1'b1) begin
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up_axi_arready_int <= 1'b1;
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end
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if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
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up_axi_rvalid_int <= 1'b0;
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up_axi_rdata_int <= 32'd0;
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end else if (up_rack_d == 1'b1) begin
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up_axi_rvalid_int <= 1'b1;
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up_axi_rdata_int <= up_rdata_d;
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end
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end
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end
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assign up_rreq = up_rreq_int;
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assign up_raddr = up_raddr_int;
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assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
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assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_rack_d <= 'd0;
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up_rdata_d <= 'd0;
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up_rsel <= 'd0;
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up_rreq_int <= 'd0;
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up_raddr_int <= 'd0;
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up_rcount <= 'd0;
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end else begin
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up_rack_d <= up_rack_s;
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up_rdata_d <= up_rdata_s;
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if (up_rsel == 1'b1) begin
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if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
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up_rsel <= 1'b0;
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end
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up_rreq_int <= 1'b0;
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end else begin
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up_rsel <= up_axi_arvalid;
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up_rreq_int <= up_axi_arvalid;
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up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2];
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end
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if (up_rack_s == 1'b1) begin
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up_rcount <= 5'h00;
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end else if (up_rcount[4] == 1'b1) begin
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up_rcount <= up_rcount + 1'b1;
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end else if (up_rreq_int == 1'b1) begin
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up_rcount <= 5'h10;
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end
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||||
end
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end
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endmodule
|
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// ***************************************************************************
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// ***************************************************************************
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@@ -0,0 +1,148 @@
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//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
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//Date : Thu Mar 30 16:04:58 2023
|
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//Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
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//Command : generate_target system_bd_wrapper.bd
|
||||
//Design : system_bd_wrapper
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module system_bd_wrapper
|
||||
(ddr_addr,
|
||||
ddr_ba,
|
||||
ddr_cas_n,
|
||||
ddr_ck_n,
|
||||
ddr_ck_p,
|
||||
ddr_cke,
|
||||
ddr_cs_n,
|
||||
ddr_dm,
|
||||
ddr_dq,
|
||||
ddr_dqs_n,
|
||||
ddr_dqs_p,
|
||||
ddr_odt,
|
||||
ddr_ras_n,
|
||||
ddr_reset_n,
|
||||
ddr_we_n,
|
||||
fixed_io_ddr_vrn,
|
||||
fixed_io_ddr_vrp,
|
||||
fixed_io_mio,
|
||||
fixed_io_ps_clk,
|
||||
fixed_io_ps_porb,
|
||||
fixed_io_ps_srstb,
|
||||
gpio_i,
|
||||
gpio_o,
|
||||
gpio_t,
|
||||
ps_clk_200M,
|
||||
ps_clk_50M,
|
||||
spi_active,
|
||||
spi_cs,
|
||||
spi_sclk,
|
||||
spi_sdi,
|
||||
spi_sdo,
|
||||
spi_sdo_t,
|
||||
spi_three_wire);
|
||||
inout [14:0]ddr_addr;
|
||||
inout [2:0]ddr_ba;
|
||||
inout ddr_cas_n;
|
||||
inout ddr_ck_n;
|
||||
inout ddr_ck_p;
|
||||
inout ddr_cke;
|
||||
inout ddr_cs_n;
|
||||
inout [3:0]ddr_dm;
|
||||
inout [31:0]ddr_dq;
|
||||
inout [3:0]ddr_dqs_n;
|
||||
inout [3:0]ddr_dqs_p;
|
||||
inout ddr_odt;
|
||||
inout ddr_ras_n;
|
||||
inout ddr_reset_n;
|
||||
inout ddr_we_n;
|
||||
inout fixed_io_ddr_vrn;
|
||||
inout fixed_io_ddr_vrp;
|
||||
inout [53:0]fixed_io_mio;
|
||||
inout fixed_io_ps_clk;
|
||||
inout fixed_io_ps_porb;
|
||||
inout fixed_io_ps_srstb;
|
||||
input [47:0]gpio_i;
|
||||
output [47:0]gpio_o;
|
||||
output [47:0]gpio_t;
|
||||
output ps_clk_200M;
|
||||
output ps_clk_50M;
|
||||
output spi_active;
|
||||
output [2:0]spi_cs;
|
||||
output spi_sclk;
|
||||
input [0:0]spi_sdi;
|
||||
output spi_sdo;
|
||||
output spi_sdo_t;
|
||||
output spi_three_wire;
|
||||
|
||||
wire [14:0]ddr_addr;
|
||||
wire [2:0]ddr_ba;
|
||||
wire ddr_cas_n;
|
||||
wire ddr_ck_n;
|
||||
wire ddr_ck_p;
|
||||
wire ddr_cke;
|
||||
wire ddr_cs_n;
|
||||
wire [3:0]ddr_dm;
|
||||
wire [31:0]ddr_dq;
|
||||
wire [3:0]ddr_dqs_n;
|
||||
wire [3:0]ddr_dqs_p;
|
||||
wire ddr_odt;
|
||||
wire ddr_ras_n;
|
||||
wire ddr_reset_n;
|
||||
wire ddr_we_n;
|
||||
wire fixed_io_ddr_vrn;
|
||||
wire fixed_io_ddr_vrp;
|
||||
wire [53:0]fixed_io_mio;
|
||||
wire fixed_io_ps_clk;
|
||||
wire fixed_io_ps_porb;
|
||||
wire fixed_io_ps_srstb;
|
||||
wire [47:0]gpio_i;
|
||||
wire [47:0]gpio_o;
|
||||
wire [47:0]gpio_t;
|
||||
wire ps_clk_200M;
|
||||
wire ps_clk_50M;
|
||||
wire spi_active;
|
||||
wire [2:0]spi_cs;
|
||||
wire spi_sclk;
|
||||
wire [0:0]spi_sdi;
|
||||
wire spi_sdo;
|
||||
wire spi_sdo_t;
|
||||
wire spi_three_wire;
|
||||
|
||||
system_bd system_bd_i
|
||||
(.ddr_addr(ddr_addr),
|
||||
.ddr_ba(ddr_ba),
|
||||
.ddr_cas_n(ddr_cas_n),
|
||||
.ddr_ck_n(ddr_ck_n),
|
||||
.ddr_ck_p(ddr_ck_p),
|
||||
.ddr_cke(ddr_cke),
|
||||
.ddr_cs_n(ddr_cs_n),
|
||||
.ddr_dm(ddr_dm),
|
||||
.ddr_dq(ddr_dq),
|
||||
.ddr_dqs_n(ddr_dqs_n),
|
||||
.ddr_dqs_p(ddr_dqs_p),
|
||||
.ddr_odt(ddr_odt),
|
||||
.ddr_ras_n(ddr_ras_n),
|
||||
.ddr_reset_n(ddr_reset_n),
|
||||
.ddr_we_n(ddr_we_n),
|
||||
.fixed_io_ddr_vrn(fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp(fixed_io_ddr_vrp),
|
||||
.fixed_io_mio(fixed_io_mio),
|
||||
.fixed_io_ps_clk(fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb(fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb(fixed_io_ps_srstb),
|
||||
.gpio_i(gpio_i),
|
||||
.gpio_o(gpio_o),
|
||||
.gpio_t(gpio_t),
|
||||
.ps_clk_200M(ps_clk_200M),
|
||||
.ps_clk_50M(ps_clk_50M),
|
||||
.spi_active(spi_active),
|
||||
.spi_cs(spi_cs),
|
||||
.spi_sclk(spi_sclk),
|
||||
.spi_sdi(spi_sdi),
|
||||
.spi_sdo(spi_sdo),
|
||||
.spi_sdo_t(spi_sdo_t),
|
||||
.spi_three_wire(spi_three_wire));
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,697 @@
|
||||
|
||||
################################################################
|
||||
# This is a generated script based on design: system_bd
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# To test this script, run the following commands from Vivado Tcl console:
|
||||
# source system_bd_script.tcl
|
||||
|
||||
# If there is no project opened, this script will create a
|
||||
# project, but make sure you do not have an existing project
|
||||
# <./myproj/project_1.xpr> in the current working folder.
|
||||
|
||||
set list_projs [get_projects -quiet]
|
||||
if { $list_projs eq "" } {
|
||||
create_project project_1 myproj -part xc7z100ffg900-2
|
||||
}
|
||||
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name system_bd
|
||||
|
||||
# This script was generated for a remote BD. To create a non-remote design,
|
||||
# change the variable <run_remote_bd_flow> to <0>.
|
||||
|
||||
set run_remote_bd_flow 1
|
||||
if { $run_remote_bd_flow == 1 } {
|
||||
# Set the reference directory for source file relative paths (by default
|
||||
# the value is script directory path)
|
||||
set origin_dir ./Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds
|
||||
|
||||
# Use origin directory path location variable, if specified in the tcl shell
|
||||
if { [info exists ::origin_dir_loc] } {
|
||||
set origin_dir $::origin_dir_loc
|
||||
}
|
||||
|
||||
set str_bd_folder [file normalize ${origin_dir}]
|
||||
set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
|
||||
|
||||
# Check if remote design exists on disk
|
||||
if { [file exists $str_bd_filepath ] == 1 } {
|
||||
catch {common::send_msg_id "BD_TCL-110" "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
|
||||
common::send_msg_id "BD_TCL-008" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
|
||||
common::send_msg_id "BD_TCL-009" "INFO" "Also make sure there is no design <$design_name> existing in your current project."
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
# Check if design exists in memory
|
||||
set list_existing_designs [get_bd_designs -quiet $design_name]
|
||||
if { $list_existing_designs ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-111" "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
|
||||
|
||||
common::send_msg_id "BD_TCL-010" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
# Check if design exists on disk within project
|
||||
set list_existing_designs [get_files -quiet */${design_name}.bd]
|
||||
if { $list_existing_designs ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-112" "ERROR" "The design <$design_name> already exists in this project at location:
|
||||
$list_existing_designs"}
|
||||
catch {common::send_msg_id "BD_TCL-113" "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
|
||||
|
||||
common::send_msg_id "BD_TCL-011" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
# Now can create the remote BD
|
||||
# NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
|
||||
create_bd_design -dir $str_bd_folder $design_name
|
||||
} else {
|
||||
|
||||
# Create regular design
|
||||
if { [catch {create_bd_design $design_name} errmsg] } {
|
||||
common::send_msg_id "BD_TCL-012" "INFO" "Please set a different value to variable <design_name>."
|
||||
|
||||
return 1
|
||||
}
|
||||
}
|
||||
|
||||
current_bd_design $design_name
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
# Hierarchical cell: axi_spi_engine
|
||||
proc create_hier_cell_axi_spi_engine { parentCell nameHier } {
|
||||
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_axi_spi_engine() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
# Create cell and set as current instance
|
||||
set hier_obj [create_bd_cell -type hier $nameHier]
|
||||
current_bd_instance $hier_obj
|
||||
|
||||
# Create interface pins
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
||||
|
||||
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
|
||||
|
||||
|
||||
# Create pins
|
||||
create_bd_pin -dir O active
|
||||
create_bd_pin -dir O irq
|
||||
create_bd_pin -dir I -type clk s_axi_aclk
|
||||
create_bd_pin -dir I -type rst s_axi_aresetn
|
||||
create_bd_pin -dir I -type clk spi_clk
|
||||
|
||||
# Create instance: axi_spi_engine, and set properties
|
||||
set axi_spi_engine [ create_bd_cell -type ip -vlnv analog.com:user:axi_spi_engine:1.0 axi_spi_engine ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {8} \
|
||||
CONFIG.NUM_OF_SDI {1} \
|
||||
] $axi_spi_engine
|
||||
|
||||
# Create instance: spi_engine_execution, and set properties
|
||||
set spi_engine_execution [ create_bd_cell -type ip -vlnv analog.com:user:spi_engine_execution:1.0 spi_engine_execution ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {8} \
|
||||
CONFIG.NUM_OF_CS {3} \
|
||||
CONFIG.NUM_OF_SDI {1} \
|
||||
] $spi_engine_execution
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins s_axi] [get_bd_intf_pins axi_spi_engine/s_axi]
|
||||
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins spi] [get_bd_intf_pins spi_engine_execution/spi]
|
||||
connect_bd_intf_net -intf_net axi_spi_engine_spi_engine_ctrl [get_bd_intf_pins axi_spi_engine/spi_engine_ctrl] [get_bd_intf_pins spi_engine_execution/ctrl]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net axi_spi_engine_irq [get_bd_pins irq] [get_bd_pins axi_spi_engine/irq]
|
||||
connect_bd_net -net axi_spi_engine_spi_resetn [get_bd_pins axi_spi_engine/spi_resetn] [get_bd_pins spi_engine_execution/resetn]
|
||||
connect_bd_net -net s_axi_aclk_0_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_spi_engine/s_axi_aclk]
|
||||
connect_bd_net -net s_axi_aresetn_0_1 [get_bd_pins s_axi_aresetn] [get_bd_pins axi_spi_engine/s_axi_aresetn]
|
||||
connect_bd_net -net spi_clk_0_1 [get_bd_pins spi_clk] [get_bd_pins axi_spi_engine/spi_clk] [get_bd_pins spi_engine_execution/clk]
|
||||
connect_bd_net -net spi_engine_execution_active [get_bd_pins active] [get_bd_pins spi_engine_execution/active]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
}
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set ddr [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr ]
|
||||
|
||||
set fixed_io [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io ]
|
||||
|
||||
set spi [ create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi ]
|
||||
|
||||
|
||||
# Create ports
|
||||
set gpio_i [ create_bd_port -dir I -from 47 -to 0 gpio_i ]
|
||||
set gpio_o [ create_bd_port -dir O -from 47 -to 0 gpio_o ]
|
||||
set gpio_t [ create_bd_port -dir O -from 47 -to 0 gpio_t ]
|
||||
set ps_clk_200M [ create_bd_port -dir O -type clk ps_clk_200M ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {200000000} \
|
||||
] $ps_clk_200M
|
||||
set ps_clk_50M [ create_bd_port -dir O -type clk ps_clk_50M ]
|
||||
set spi_active [ create_bd_port -dir O spi_active ]
|
||||
|
||||
# Create instance: axi_interconnect, and set properties
|
||||
set axi_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.NUM_MI {1} \
|
||||
] $axi_interconnect
|
||||
|
||||
# Create instance: axi_spi_engine
|
||||
create_hier_cell_axi_spi_engine [current_bd_instance .] axi_spi_engine
|
||||
|
||||
# Create instance: ps_system, and set properties
|
||||
set ps_system [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 ps_system ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
|
||||
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
|
||||
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
|
||||
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_CLK0_FREQ {50000000} \
|
||||
CONFIG.PCW_CLK1_FREQ {200000000} \
|
||||
CONFIG.PCW_CLK2_FREQ {10000000} \
|
||||
CONFIG.PCW_CLK3_FREQ {10000000} \
|
||||
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
|
||||
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
|
||||
CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
|
||||
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
|
||||
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
|
||||
CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
|
||||
CONFIG.PCW_ENET0_ENET0_IO {<Select>} \
|
||||
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {0} \
|
||||
CONFIG.PCW_ENET0_GRP_MDIO_IO {<Select>} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
|
||||
CONFIG.PCW_ENET0_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_ENET0_RESET_IO {<Select>} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_ENET1_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_ENET_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_ENET_RESET_SELECT {<Select>} \
|
||||
CONFIG.PCW_EN_CLK1_PORT {1} \
|
||||
CONFIG.PCW_EN_EMIO_ENET0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_GPIO {1} \
|
||||
CONFIG.PCW_EN_EMIO_PJTAG {0} \
|
||||
CONFIG.PCW_EN_EMIO_SPI0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_SPI1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_UART0 {0} \
|
||||
CONFIG.PCW_EN_ENET0 {0} \
|
||||
CONFIG.PCW_EN_GPIO {1} \
|
||||
CONFIG.PCW_EN_PJTAG {0} \
|
||||
CONFIG.PCW_EN_QSPI {1} \
|
||||
CONFIG.PCW_EN_SPI0 {0} \
|
||||
CONFIG.PCW_EN_SPI1 {0} \
|
||||
CONFIG.PCW_EN_UART0 {0} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {6} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {6} \
|
||||
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {3} \
|
||||
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {3} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \
|
||||
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200} \
|
||||
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
|
||||
CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \
|
||||
CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
|
||||
CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
|
||||
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
|
||||
CONFIG.PCW_GPIO_EMIO_GPIO_IO {48} \
|
||||
CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {48} \
|
||||
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
|
||||
CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
|
||||
CONFIG.PCW_I2C0_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_I2C1_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
|
||||
CONFIG.PCW_I2C_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_IOPLL_CTRL_FBDIV {54} \
|
||||
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1800.000} \
|
||||
CONFIG.PCW_IRQ_F2P_INTR {1} \
|
||||
CONFIG.PCW_MIO_0_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_0_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_0_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_10_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_10_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_10_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_11_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_11_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_11_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_12_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_12_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_12_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_13_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_13_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_13_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_14_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_14_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_14_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_15_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_15_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_15_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_16_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_16_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_16_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_17_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_17_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_17_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_18_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_18_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_18_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_19_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_19_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_19_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_1_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_1_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_1_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_20_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_20_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_20_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_21_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_21_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_21_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_22_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_22_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_22_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_23_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_23_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_23_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_24_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_24_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_24_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_25_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_25_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_25_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_26_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_26_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_26_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_27_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_27_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_27_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_28_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_28_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_28_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_29_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_29_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_29_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_2_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_2_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_2_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_30_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_30_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_30_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_31_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_31_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_31_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_32_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_32_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_32_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_33_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_33_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_33_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_34_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_34_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_34_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_35_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_35_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_35_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_36_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_36_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_36_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_37_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_37_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_37_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_38_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_38_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_38_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_39_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_39_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_39_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_3_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_3_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_3_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_40_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_40_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_40_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_41_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_41_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_41_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_42_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_42_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_42_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_43_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_43_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_43_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_44_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_44_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_44_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_45_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_45_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_45_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_46_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_46_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_46_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_47_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_47_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_47_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_48_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_48_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_48_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_49_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_49_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_49_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_4_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_4_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_4_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_50_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_50_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_50_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_51_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_51_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_51_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_52_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_52_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_52_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_53_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_53_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_53_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_5_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_5_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_5_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_6_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_6_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_6_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_7_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_7_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_7_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_8_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_8_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_8_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_9_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_9_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_9_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO} \
|
||||
CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#gpio[16]#gpio[17]#gpio[18]#gpio[19]#gpio[20]#gpio[21]#gpio[22]#gpio[23]#gpio[24]#gpio[25]#gpio[26]#gpio[27]#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#gpio[40]#gpio[41]#gpio[42]#gpio[43]#gpio[44]#gpio[45]#gpio[46]#gpio[47]#gpio[48]#gpio[49]#gpio[50]#gpio[51]#gpio[52]#gpio[53]} \
|
||||
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
|
||||
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {9} \
|
||||
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
|
||||
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {9} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
|
||||
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
|
||||
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
|
||||
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \
|
||||
CONFIG.PCW_SPI0_GRP_SS0_IO {<Select>} \
|
||||
CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
|
||||
CONFIG.PCW_SPI0_GRP_SS1_IO {<Select>} \
|
||||
CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
|
||||
CONFIG.PCW_SPI0_GRP_SS2_IO {<Select>} \
|
||||
CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_SPI0_SPI0_IO {<Select>} \
|
||||
CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \
|
||||
CONFIG.PCW_SPI1_GRP_SS0_IO {<Select>} \
|
||||
CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
|
||||
CONFIG.PCW_SPI1_GRP_SS1_IO {<Select>} \
|
||||
CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
|
||||
CONFIG.PCW_SPI1_GRP_SS2_IO {<Select>} \
|
||||
CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_SPI1_SPI1_IO {<Select>} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
|
||||
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
|
||||
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_UART0_UART0_IO {<Select>} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_VALID {0} \
|
||||
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CL {7} \
|
||||
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
|
||||
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
|
||||
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
|
||||
CONFIG.PCW_USB0_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_USB1_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_USB_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
|
||||
] $ps_system
|
||||
|
||||
# Create instance: rst_ps_system_50M, and set properties
|
||||
set rst_ps_system_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps_system_50M ]
|
||||
|
||||
# Create instance: xlconcat_irpt, and set properties
|
||||
set xlconcat_irpt [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_irpt ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.NUM_PORTS {1} \
|
||||
] $xlconcat_irpt
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net axi_interconnect_M00_AXI [get_bd_intf_pins axi_interconnect/M00_AXI] [get_bd_intf_pins axi_spi_engine/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_spi_engine_spi_0 [get_bd_intf_ports spi] [get_bd_intf_pins axi_spi_engine/spi]
|
||||
connect_bd_intf_net -intf_net ps_system_DDR [get_bd_intf_ports ddr] [get_bd_intf_pins ps_system/DDR]
|
||||
connect_bd_intf_net -intf_net ps_system_FIXED_IO [get_bd_intf_ports fixed_io] [get_bd_intf_pins ps_system/FIXED_IO]
|
||||
connect_bd_intf_net -intf_net ps_system_M_AXI_GP0 [get_bd_intf_pins axi_interconnect/S00_AXI] [get_bd_intf_pins ps_system/M_AXI_GP0]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net GPIO_I_0_1 [get_bd_ports gpio_i] [get_bd_pins ps_system/GPIO_I]
|
||||
connect_bd_net -net axi_spi_engine_active_0 [get_bd_ports spi_active] [get_bd_pins axi_spi_engine/active]
|
||||
connect_bd_net -net axi_spi_engine_spi_irq [get_bd_pins axi_spi_engine/irq] [get_bd_pins xlconcat_irpt/In0]
|
||||
connect_bd_net -net ps_system_FCLK_CLK0 [get_bd_ports ps_clk_50M] [get_bd_pins axi_interconnect/ACLK] [get_bd_pins axi_interconnect/M00_ACLK] [get_bd_pins axi_interconnect/S00_ACLK] [get_bd_pins axi_spi_engine/s_axi_aclk] [get_bd_pins axi_spi_engine/spi_clk] [get_bd_pins ps_system/FCLK_CLK0] [get_bd_pins ps_system/M_AXI_GP0_ACLK] [get_bd_pins rst_ps_system_50M/slowest_sync_clk]
|
||||
connect_bd_net -net ps_system_FCLK_CLK1 [get_bd_ports ps_clk_200M] [get_bd_pins ps_system/FCLK_CLK1]
|
||||
connect_bd_net -net ps_system_FCLK_RESET0_N [get_bd_pins ps_system/FCLK_RESET0_N] [get_bd_pins rst_ps_system_50M/ext_reset_in]
|
||||
connect_bd_net -net ps_system_GPIO_O [get_bd_ports gpio_o] [get_bd_pins ps_system/GPIO_O]
|
||||
connect_bd_net -net ps_system_GPIO_T [get_bd_ports gpio_t] [get_bd_pins ps_system/GPIO_T]
|
||||
connect_bd_net -net rst_ps_system_50M_peripheral_aresetn [get_bd_pins axi_interconnect/ARESETN] [get_bd_pins axi_interconnect/M00_ARESETN] [get_bd_pins axi_interconnect/S00_ARESETN] [get_bd_pins axi_spi_engine/s_axi_aresetn] [get_bd_pins rst_ps_system_50M/peripheral_aresetn]
|
||||
connect_bd_net -net xlconcat_irpt_dout [get_bd_pins ps_system/IRQ_F2P] [get_bd_pins xlconcat_irpt/dout]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces ps_system/Data] [get_bd_addr_segs axi_spi_engine/axi_spi_engine/s_axi/axi_lite] SEG_axi_spi_engine_axi_lite
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
+354
@@ -0,0 +1,354 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 19
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRIT\
|
||||
E_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WR\
|
||||
ITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_19_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+356
@@ -0,0 +1,356 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 19
|
||||
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1.3" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_auto_pc_0,axi_protocol_converter_v2_1_19_axi_protocol_converter,{}" *)
|
||||
(* CORE_GENERATION_INFO = "system_bd_auto_pc_0,axi_protocol_converter_v2_1_19_axi_protocol_converter,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=19,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WU\
|
||||
SER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRIT\
|
||||
E_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WR\
|
||||
ITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_19_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
BIN
Binary file not shown.
+213
@@ -0,0 +1,213 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_auto_pc_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_protocol_converter" spirit:version="2.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">ARESETN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.TYPE">INTERCONNECT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
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||||
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||||
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
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||||
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||||
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
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||||
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
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||||
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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||||
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||||
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||||
</spirit:vendorExtensions>
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||||
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||||
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|
||||
</spirit:design>
|
||||
+4342
File diff suppressed because it is too large
Load Diff
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 20 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
+12764
File diff suppressed because it is too large
Load Diff
+14973
File diff suppressed because it is too large
Load Diff
+87
@@ -0,0 +1,87 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:05:42 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0_stub.v
|
||||
// Design : system_bd_auto_pc_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1.3" *)
|
||||
module system_bd_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
|
||||
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
|
||||
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
|
||||
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
|
||||
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
|
||||
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
|
||||
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
|
||||
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
|
||||
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
|
||||
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
|
||||
input aclk;
|
||||
input aresetn;
|
||||
input [11:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [3:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [1:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [11:0]s_axi_wid;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [11:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [11:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [3:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [1:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [11:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [31:0]m_axi_awaddr;
|
||||
output [2:0]m_axi_awprot;
|
||||
output m_axi_awvalid;
|
||||
input m_axi_awready;
|
||||
output [31:0]m_axi_wdata;
|
||||
output [3:0]m_axi_wstrb;
|
||||
output m_axi_wvalid;
|
||||
input m_axi_wready;
|
||||
input [1:0]m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
output m_axi_bready;
|
||||
output [31:0]m_axi_araddr;
|
||||
output [2:0]m_axi_arprot;
|
||||
output m_axi_arvalid;
|
||||
input m_axi_arready;
|
||||
input [31:0]m_axi_rdata;
|
||||
input [1:0]m_axi_rresp;
|
||||
input m_axi_rvalid;
|
||||
output m_axi_rready;
|
||||
endmodule
|
||||
+88
@@ -0,0 +1,88 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:05:42 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0_stub.vhdl
|
||||
-- Design : system_bd_auto_pc_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_auto_pc_0 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_awvalid : out STD_LOGIC;
|
||||
m_axi_awready : in STD_LOGIC;
|
||||
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_wvalid : out STD_LOGIC;
|
||||
m_axi_wready : in STD_LOGIC;
|
||||
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_bvalid : in STD_LOGIC;
|
||||
m_axi_bready : out STD_LOGIC;
|
||||
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_arvalid : out STD_LOGIC;
|
||||
m_axi_arready : in STD_LOGIC;
|
||||
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_rvalid : in STD_LOGIC;
|
||||
m_axi_rready : out STD_LOGIC
|
||||
);
|
||||
|
||||
end system_bd_auto_pc_0;
|
||||
|
||||
architecture stub of system_bd_auto_pc_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+358
@@ -0,0 +1,358 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_axi_interconnect_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_interconnect" spirit:version="2.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_axi_interconnect_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ADVANCED_OPTIONS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_PROTOCOL_CHECKERS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M00_HAS_DATA_FIFO">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M00_HAS_REGSLICE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S10_HAS_DATA_FIFO">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S14_HAS_DATA_FIFO">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STRATEGY">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">3</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XBAR_DATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator_AppCore</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">20</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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</spirit:configurableElementValues>
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<spirit:vendorExtensions>
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<xilinx:componentInstanceExtensions>
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<xilinx:configElementInfos>
|
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_MI" xilinx:valueSource="user"/>
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</xilinx:configElementInfos>
|
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</xilinx:componentInstanceExtensions>
|
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</spirit:vendorExtensions>
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</spirit:componentInstance>
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</spirit:componentInstances>
|
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</spirit:design>
|
||||
+1642
File diff suppressed because it is too large
Load Diff
+245
@@ -0,0 +1,245 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: analog.com:user:axi_spi_engine:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_axi_spi_engine_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awvalid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awready,
|
||||
s_axi_awprot,
|
||||
s_axi_wvalid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wready,
|
||||
s_axi_bvalid,
|
||||
s_axi_bresp,
|
||||
s_axi_bready,
|
||||
s_axi_arvalid,
|
||||
s_axi_araddr,
|
||||
s_axi_arready,
|
||||
s_axi_arprot,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
s_axi_rresp,
|
||||
s_axi_rdata,
|
||||
irq,
|
||||
spi_clk,
|
||||
spi_resetn,
|
||||
cmd_ready,
|
||||
cmd_valid,
|
||||
cmd_data,
|
||||
sdo_data_ready,
|
||||
sdo_data_valid,
|
||||
sdo_data,
|
||||
sdi_data_ready,
|
||||
sdi_data_valid,
|
||||
sdi_data,
|
||||
sync_ready,
|
||||
sync_valid,
|
||||
sync_data
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
|
||||
input wire [15 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
|
||||
input wire [15 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WR\
|
||||
ITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire irq;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *)
|
||||
input wire spi_clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *)
|
||||
output wire spi_resetn;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *)
|
||||
input wire cmd_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *)
|
||||
output wire cmd_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *)
|
||||
output wire [15 : 0] cmd_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *)
|
||||
input wire sdo_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *)
|
||||
output wire sdo_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *)
|
||||
output wire [7 : 0] sdo_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *)
|
||||
output wire sdi_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *)
|
||||
input wire sdi_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *)
|
||||
input wire [7 : 0] sdi_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *)
|
||||
output wire sync_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *)
|
||||
input wire sync_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *)
|
||||
input wire [7 : 0] sync_data;
|
||||
|
||||
axi_spi_engine #(
|
||||
.CMD_FIFO_ADDRESS_WIDTH(4),
|
||||
.SYNC_FIFO_ADDRESS_WIDTH(4),
|
||||
.SDO_FIFO_ADDRESS_WIDTH(5),
|
||||
.SDI_FIFO_ADDRESS_WIDTH(5),
|
||||
.MM_IF_TYPE(0),
|
||||
.ASYNC_SPI_CLK(1'B0),
|
||||
.NUM_OFFLOAD(0),
|
||||
.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4),
|
||||
.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4),
|
||||
.ID(0),
|
||||
.DATA_WIDTH(8),
|
||||
.NUM_OF_SDI(1)
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.up_clk(1'B0),
|
||||
.up_rstn(1'B0),
|
||||
.up_wreq(1'B0),
|
||||
.up_waddr(14'B0),
|
||||
.up_wdata(32'B0),
|
||||
.up_wack(),
|
||||
.up_rreq(1'B0),
|
||||
.up_raddr(14'B0),
|
||||
.up_rdata(),
|
||||
.up_rack(),
|
||||
.irq(irq),
|
||||
.spi_clk(spi_clk),
|
||||
.spi_resetn(spi_resetn),
|
||||
.cmd_ready(cmd_ready),
|
||||
.cmd_valid(cmd_valid),
|
||||
.cmd_data(cmd_data),
|
||||
.sdo_data_ready(sdo_data_ready),
|
||||
.sdo_data_valid(sdo_data_valid),
|
||||
.sdo_data(sdo_data),
|
||||
.sdi_data_ready(sdi_data_ready),
|
||||
.sdi_data_valid(sdi_data_valid),
|
||||
.sdi_data(sdi_data),
|
||||
.sync_ready(sync_ready),
|
||||
.sync_valid(sync_valid),
|
||||
.sync_data(sync_data),
|
||||
.offload0_cmd_wr_en(),
|
||||
.offload0_cmd_wr_data(),
|
||||
.offload0_sdo_wr_en(),
|
||||
.offload0_sdo_wr_data(),
|
||||
.offload0_mem_reset(),
|
||||
.offload0_enable(),
|
||||
.offload0_enabled(1'B0),
|
||||
.offload_sync_ready(),
|
||||
.offload_sync_valid(1'B0),
|
||||
.offload_sync_data(8'B0)
|
||||
);
|
||||
endmodule
|
||||
+245
@@ -0,0 +1,245 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: analog.com:user:axi_spi_engine:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_axi_spi_engine_0,axi_spi_engine,{}" *)
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_axi_spi_engine_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awvalid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awready,
|
||||
s_axi_awprot,
|
||||
s_axi_wvalid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wready,
|
||||
s_axi_bvalid,
|
||||
s_axi_bresp,
|
||||
s_axi_bready,
|
||||
s_axi_arvalid,
|
||||
s_axi_araddr,
|
||||
s_axi_arready,
|
||||
s_axi_arprot,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
s_axi_rresp,
|
||||
s_axi_rdata,
|
||||
irq,
|
||||
spi_clk,
|
||||
spi_resetn,
|
||||
cmd_ready,
|
||||
cmd_valid,
|
||||
cmd_data,
|
||||
sdo_data_ready,
|
||||
sdo_data_valid,
|
||||
sdo_data,
|
||||
sdi_data_ready,
|
||||
sdi_data_valid,
|
||||
sdi_data,
|
||||
sync_ready,
|
||||
sync_valid,
|
||||
sync_data
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
|
||||
input wire [15 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
|
||||
input wire [15 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WR\
|
||||
ITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire irq;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *)
|
||||
input wire spi_clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *)
|
||||
output wire spi_resetn;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *)
|
||||
input wire cmd_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *)
|
||||
output wire cmd_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *)
|
||||
output wire [15 : 0] cmd_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *)
|
||||
input wire sdo_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *)
|
||||
output wire sdo_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *)
|
||||
output wire [7 : 0] sdo_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *)
|
||||
output wire sdi_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *)
|
||||
input wire sdi_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *)
|
||||
input wire [7 : 0] sdi_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *)
|
||||
output wire sync_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *)
|
||||
input wire sync_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *)
|
||||
input wire [7 : 0] sync_data;
|
||||
|
||||
axi_spi_engine #(
|
||||
.CMD_FIFO_ADDRESS_WIDTH(4),
|
||||
.SYNC_FIFO_ADDRESS_WIDTH(4),
|
||||
.SDO_FIFO_ADDRESS_WIDTH(5),
|
||||
.SDI_FIFO_ADDRESS_WIDTH(5),
|
||||
.MM_IF_TYPE(0),
|
||||
.ASYNC_SPI_CLK(1'B0),
|
||||
.NUM_OFFLOAD(0),
|
||||
.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4),
|
||||
.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4),
|
||||
.ID(0),
|
||||
.DATA_WIDTH(8),
|
||||
.NUM_OF_SDI(1)
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.up_clk(1'B0),
|
||||
.up_rstn(1'B0),
|
||||
.up_wreq(1'B0),
|
||||
.up_waddr(14'B0),
|
||||
.up_wdata(32'B0),
|
||||
.up_wack(),
|
||||
.up_rreq(1'B0),
|
||||
.up_raddr(14'B0),
|
||||
.up_rdata(),
|
||||
.up_rack(),
|
||||
.irq(irq),
|
||||
.spi_clk(spi_clk),
|
||||
.spi_resetn(spi_resetn),
|
||||
.cmd_ready(cmd_ready),
|
||||
.cmd_valid(cmd_valid),
|
||||
.cmd_data(cmd_data),
|
||||
.sdo_data_ready(sdo_data_ready),
|
||||
.sdo_data_valid(sdo_data_valid),
|
||||
.sdo_data(sdo_data),
|
||||
.sdi_data_ready(sdi_data_ready),
|
||||
.sdi_data_valid(sdi_data_valid),
|
||||
.sdi_data(sdi_data),
|
||||
.sync_ready(sync_ready),
|
||||
.sync_valid(sync_valid),
|
||||
.sync_data(sync_data),
|
||||
.offload0_cmd_wr_en(),
|
||||
.offload0_cmd_wr_data(),
|
||||
.offload0_sdo_wr_en(),
|
||||
.offload0_sdo_wr_data(),
|
||||
.offload0_mem_reset(),
|
||||
.offload0_enable(),
|
||||
.offload0_enabled(1'B0),
|
||||
.offload_sync_ready(),
|
||||
.offload_sync_valid(1'B0),
|
||||
.offload_sync_data(8'B0)
|
||||
);
|
||||
endmodule
|
||||
BIN
Binary file not shown.
+148
@@ -0,0 +1,148 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_axi_spi_engine_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="analog.com" spirit:library="user" spirit:name="axi_spi_engine" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.PHASE">0.000</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.PHASE">0.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ASYNC_SPI_CLK">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MM_IF_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_OFFLOAD">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASYNC_SPI_CLK">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_axi_spi_engine_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MM_IF_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OFFLOAD">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OF_SDI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OF_SDI" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+2692
File diff suppressed because it is too large
Load Diff
+1
@@ -0,0 +1 @@
|
||||
|
||||
+6411
File diff suppressed because it is too large
Load Diff
+7953
File diff suppressed because it is too large
Load Diff
+60
@@ -0,0 +1,60 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:05:23 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.v
|
||||
// Design : system_bd_axi_spi_engine_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
|
||||
module system_bd_axi_spi_engine_0(s_axi_aclk, s_axi_aresetn, s_axi_awvalid,
|
||||
s_axi_awaddr, s_axi_awready, s_axi_awprot, s_axi_wvalid, s_axi_wdata, s_axi_wstrb,
|
||||
s_axi_wready, s_axi_bvalid, s_axi_bresp, s_axi_bready, s_axi_arvalid, s_axi_araddr,
|
||||
s_axi_arready, s_axi_arprot, s_axi_rvalid, s_axi_rready, s_axi_rresp, s_axi_rdata, irq,
|
||||
spi_clk, spi_resetn, cmd_ready, cmd_valid, cmd_data, sdo_data_ready, sdo_data_valid, sdo_data,
|
||||
sdi_data_ready, sdi_data_valid, sdi_data, sync_ready, sync_valid, sync_data)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]" */;
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
input s_axi_awvalid;
|
||||
input [15:0]s_axi_awaddr;
|
||||
output s_axi_awready;
|
||||
input [2:0]s_axi_awprot;
|
||||
input s_axi_wvalid;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
output s_axi_wready;
|
||||
output s_axi_bvalid;
|
||||
output [1:0]s_axi_bresp;
|
||||
input s_axi_bready;
|
||||
input s_axi_arvalid;
|
||||
input [15:0]s_axi_araddr;
|
||||
output s_axi_arready;
|
||||
input [2:0]s_axi_arprot;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [1:0]s_axi_rresp;
|
||||
output [31:0]s_axi_rdata;
|
||||
output irq;
|
||||
input spi_clk;
|
||||
output spi_resetn;
|
||||
input cmd_ready;
|
||||
output cmd_valid;
|
||||
output [15:0]cmd_data;
|
||||
input sdo_data_ready;
|
||||
output sdo_data_valid;
|
||||
output [7:0]sdo_data;
|
||||
output sdi_data_ready;
|
||||
input sdi_data_valid;
|
||||
input [7:0]sdi_data;
|
||||
output sync_ready;
|
||||
input sync_valid;
|
||||
input [7:0]sync_data;
|
||||
endmodule
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:05:23 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.vhdl
|
||||
-- Design : system_bd_axi_spi_engine_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_axi_spi_engine_0 is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
irq : out STD_LOGIC;
|
||||
spi_clk : in STD_LOGIC;
|
||||
spi_resetn : out STD_LOGIC;
|
||||
cmd_ready : in STD_LOGIC;
|
||||
cmd_valid : out STD_LOGIC;
|
||||
cmd_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
sdo_data_ready : in STD_LOGIC;
|
||||
sdo_data_valid : out STD_LOGIC;
|
||||
sdo_data : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sdi_data_ready : out STD_LOGIC;
|
||||
sdi_data_valid : in STD_LOGIC;
|
||||
sdi_data : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sync_ready : out STD_LOGIC;
|
||||
sync_valid : in STD_LOGIC;
|
||||
sync_data : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
|
||||
end system_bd_axi_spi_engine_0;
|
||||
|
||||
architecture stub of system_bd_axi_spi_engine_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_spi_engine,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+3934
File diff suppressed because it is too large
Load Diff
BIN
Binary file not shown.
+11837
File diff suppressed because it is too large
Load Diff
+139
@@ -0,0 +1,139 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2018 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 10000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 10000000
|
||||
#define UART_FREQ 10000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 50000000
|
||||
#define FPGA1_FREQ 200000000
|
||||
#define FPGA2_FREQ 10000000
|
||||
#define FPGA3_FREQ 10000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+133130
File diff suppressed because it is too large
Load Diff
+790
@@ -0,0 +1,790 @@
|
||||
proc ps7_pll_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00600600
|
||||
mask_write 0XF8000180 0x03F03F30 0x00300300
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000084
|
||||
mask_write 0XF8006004 0x0007FFFF 0x00001082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
|
||||
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00000003 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000666
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
|
||||
mask_write 0XF8006048 0x0003F03F 0x0003C008
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x00010000 0x00000000
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x00000200 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFCF 0x40000000
|
||||
mask_write 0XF8006124 0x7FFFFFCF 0x40000000
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000703FF 0x000003FF
|
||||
mask_write 0XF800620C 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006210 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006214 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF5 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000085
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000220
|
||||
mask_write 0XF8000B70 0x00000001 0x00000001
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000202
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000202
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000724 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000728 0x00003FFF 0x00000200
|
||||
mask_write 0XF800072C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000730 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000734 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000200
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001200
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001200
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001200
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000770 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000774 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000778 0x00003FFF 0x00000200
|
||||
mask_write 0XF800077C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000780 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000784 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000788 0x00003FFF 0x00000200
|
||||
mask_write 0XF800078C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000790 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000794 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000798 0x00003FFF 0x00000200
|
||||
mask_write 0XF800079C 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001200
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000000
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_3_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00600600
|
||||
mask_write 0XF8000180 0x03F03F30 0x00300300
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000084
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000666
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000000
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000000
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000085
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000220
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000202
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000202
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000724 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000728 0x00003FFF 0x00000200
|
||||
mask_write 0XF800072C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000730 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000734 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000200
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001200
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001200
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001200
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000770 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000774 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000778 0x00003FFF 0x00000200
|
||||
mask_write 0XF800077C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000780 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000784 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000788 0x00003FFF 0x00000200
|
||||
mask_write 0XF800078C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000790 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000794 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000798 0x00003FFF 0x00000200
|
||||
mask_write 0XF800079C 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001200
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000000
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_2_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00600600
|
||||
mask_write 0XF8000180 0x03F03F30 0x00300300
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000084
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000666
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000000
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000000
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000085
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x000073FF 0x00000220
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000202
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000202
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000724 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000728 0x00003FFF 0x00000200
|
||||
mask_write 0XF800072C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000730 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000734 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000200
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001200
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001200
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001200
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000770 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000774 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000778 0x00003FFF 0x00000200
|
||||
mask_write 0XF800077C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000780 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000784 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000788 0x00003FFF 0x00000200
|
||||
mask_write 0XF800078C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000790 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000794 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000798 0x00003FFF 0x00000200
|
||||
mask_write 0XF800079C 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001200
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000000
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_1_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 666666666
|
||||
|
||||
|
||||
|
||||
proc mask_poll { addr mask } {
|
||||
set count 1
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
while { $maskedval == 0 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
set count [ expr { $count + 1 } ]
|
||||
if { $count == 100000000 } {
|
||||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc mask_delay { addr val } {
|
||||
set delay [ get_number_of_cycles_for_delay $val ]
|
||||
perf_reset_and_start_timer
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
while { $maskedval == 1 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
}
|
||||
perf_reset_clock
|
||||
}
|
||||
|
||||
proc ps_version { } {
|
||||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||
return $mask_sil_ver;
|
||||
}
|
||||
|
||||
proc ps7_post_config {} {
|
||||
set saved_mode [configparams force-mem-accesses]
|
||||
configparams force-mem-accesses 1
|
||||
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_post_config_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_post_config_2_0
|
||||
} else {
|
||||
ps7_post_config_3_0
|
||||
}
|
||||
configparams force-mem-accesses $saved_mode
|
||||
}
|
||||
|
||||
proc ps7_debug {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_debug_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_debug_2_0
|
||||
} else {
|
||||
ps7_debug_3_0
|
||||
}
|
||||
}
|
||||
proc ps7_init {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_mio_init_data_1_0
|
||||
ps7_pll_init_data_1_0
|
||||
ps7_clock_init_data_1_0
|
||||
ps7_ddr_init_data_1_0
|
||||
ps7_peripherals_init_data_1_0
|
||||
#puts "PCW Silicon Version : 1.0"
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_mio_init_data_2_0
|
||||
ps7_pll_init_data_2_0
|
||||
ps7_clock_init_data_2_0
|
||||
ps7_ddr_init_data_2_0
|
||||
ps7_peripherals_init_data_2_0
|
||||
#puts "PCW Silicon Version : 2.0"
|
||||
} else {
|
||||
ps7_mio_init_data_3_0
|
||||
ps7_pll_init_data_3_0
|
||||
ps7_clock_init_data_3_0
|
||||
ps7_ddr_init_data_3_0
|
||||
ps7_peripherals_init_data_3_0
|
||||
#puts "PCW Silicon Version : 3.0"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# For delay calculation using global timer
|
||||
|
||||
# start timer
|
||||
proc perf_start_clock { } {
|
||||
|
||||
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||
|
||||
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||
}
|
||||
|
||||
# stop timer and reset timer count regs
|
||||
proc perf_reset_clock { } {
|
||||
perf_disable_clock
|
||||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
# Compute mask for given delay in miliseconds
|
||||
proc get_number_of_cycles_for_delay { delay } {
|
||||
|
||||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
variable APU_FREQ
|
||||
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||
}
|
||||
|
||||
|
||||
# stop timer
|
||||
proc perf_disable_clock {} {
|
||||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
proc perf_reset_and_start_timer {} {
|
||||
perf_reset_clock
|
||||
perf_start_clock
|
||||
}
|
||||
|
||||
|
||||
+11831
File diff suppressed because it is too large
Load Diff
+131
@@ -0,0 +1,131 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2018 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init_gpl.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 10000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 10000000
|
||||
#define UART_FREQ 10000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 50000000
|
||||
#define FPGA1_FREQ 200000000
|
||||
#define FPGA2_FREQ 10000000
|
||||
#define FPGA3_FREQ 10000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+643
@@ -0,0 +1,643 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
|
||||
<designInfo version="1.0" >
|
||||
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
|
||||
<PARAMETERS >
|
||||
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
|
||||
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="666.666666" />
|
||||
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
|
||||
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
|
||||
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
|
||||
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
|
||||
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
|
||||
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="48" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO" />
|
||||
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="54" />
|
||||
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1800.000" />
|
||||
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
|
||||
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="9" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="9" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="x4" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="16 Bit" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="80.0515" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="80.0515" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="80.0515" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="80.0515" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="133.8645" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="119.997" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="121.146" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="90.125" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="111.7605" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="123.5525" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="120.714" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="100.836" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41J256M16 RE-125" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.91" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
|
||||
</PARAMETERS>
|
||||
<BUSINTERFACES >
|
||||
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
</BUSINTERFACES>
|
||||
<CLOCKOUTS >
|
||||
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="50.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="200.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" />
|
||||
</CLOCKOUTS>
|
||||
</MODULE>
|
||||
</designInfo>
|
||||
BIN
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+1153
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Load Diff
+588
@@ -0,0 +1,588 @@
|
||||
|
||||
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module system_bd_ps_system_0 (
|
||||
GPIO_I,
|
||||
GPIO_O,
|
||||
GPIO_T,
|
||||
M_AXI_GP0_ARVALID,
|
||||
M_AXI_GP0_AWVALID,
|
||||
M_AXI_GP0_BREADY,
|
||||
M_AXI_GP0_RREADY,
|
||||
M_AXI_GP0_WLAST,
|
||||
M_AXI_GP0_WVALID,
|
||||
M_AXI_GP0_ARID,
|
||||
M_AXI_GP0_AWID,
|
||||
M_AXI_GP0_WID,
|
||||
M_AXI_GP0_ARBURST,
|
||||
M_AXI_GP0_ARLOCK,
|
||||
M_AXI_GP0_ARSIZE,
|
||||
M_AXI_GP0_AWBURST,
|
||||
M_AXI_GP0_AWLOCK,
|
||||
M_AXI_GP0_AWSIZE,
|
||||
M_AXI_GP0_ARPROT,
|
||||
M_AXI_GP0_AWPROT,
|
||||
M_AXI_GP0_ARADDR,
|
||||
M_AXI_GP0_AWADDR,
|
||||
M_AXI_GP0_WDATA,
|
||||
M_AXI_GP0_ARCACHE,
|
||||
M_AXI_GP0_ARLEN,
|
||||
M_AXI_GP0_ARQOS,
|
||||
M_AXI_GP0_AWCACHE,
|
||||
M_AXI_GP0_AWLEN,
|
||||
M_AXI_GP0_AWQOS,
|
||||
M_AXI_GP0_WSTRB,
|
||||
M_AXI_GP0_ACLK,
|
||||
M_AXI_GP0_ARREADY,
|
||||
M_AXI_GP0_AWREADY,
|
||||
M_AXI_GP0_BVALID,
|
||||
M_AXI_GP0_RLAST,
|
||||
M_AXI_GP0_RVALID,
|
||||
M_AXI_GP0_WREADY,
|
||||
M_AXI_GP0_BID,
|
||||
M_AXI_GP0_RID,
|
||||
M_AXI_GP0_BRESP,
|
||||
M_AXI_GP0_RRESP,
|
||||
M_AXI_GP0_RDATA,
|
||||
IRQ_F2P,
|
||||
FCLK_CLK0,
|
||||
FCLK_CLK1,
|
||||
FCLK_RESET0_N,
|
||||
MIO,
|
||||
DDR_CAS_n,
|
||||
DDR_CKE,
|
||||
DDR_Clk_n,
|
||||
DDR_Clk,
|
||||
DDR_CS_n,
|
||||
DDR_DRSTB,
|
||||
DDR_ODT,
|
||||
DDR_RAS_n,
|
||||
DDR_WEB,
|
||||
DDR_BankAddr,
|
||||
DDR_Addr,
|
||||
DDR_VRN,
|
||||
DDR_VRP,
|
||||
DDR_DM,
|
||||
DDR_DQ,
|
||||
DDR_DQS_n,
|
||||
DDR_DQS,
|
||||
PS_SRSTB,
|
||||
PS_CLK,
|
||||
PS_PORB
|
||||
);
|
||||
input [47 : 0] GPIO_I;
|
||||
output [47 : 0] GPIO_O;
|
||||
output [47 : 0] GPIO_T;
|
||||
output M_AXI_GP0_ARVALID;
|
||||
output M_AXI_GP0_AWVALID;
|
||||
output M_AXI_GP0_BREADY;
|
||||
output M_AXI_GP0_RREADY;
|
||||
output M_AXI_GP0_WLAST;
|
||||
output M_AXI_GP0_WVALID;
|
||||
output [11 : 0] M_AXI_GP0_ARID;
|
||||
output [11 : 0] M_AXI_GP0_AWID;
|
||||
output [11 : 0] M_AXI_GP0_WID;
|
||||
output [1 : 0] M_AXI_GP0_ARBURST;
|
||||
output [1 : 0] M_AXI_GP0_ARLOCK;
|
||||
output [2 : 0] M_AXI_GP0_ARSIZE;
|
||||
output [1 : 0] M_AXI_GP0_AWBURST;
|
||||
output [1 : 0] M_AXI_GP0_AWLOCK;
|
||||
output [2 : 0] M_AXI_GP0_AWSIZE;
|
||||
output [2 : 0] M_AXI_GP0_ARPROT;
|
||||
output [2 : 0] M_AXI_GP0_AWPROT;
|
||||
output [31 : 0] M_AXI_GP0_ARADDR;
|
||||
output [31 : 0] M_AXI_GP0_AWADDR;
|
||||
output [31 : 0] M_AXI_GP0_WDATA;
|
||||
output [3 : 0] M_AXI_GP0_ARCACHE;
|
||||
output [3 : 0] M_AXI_GP0_ARLEN;
|
||||
output [3 : 0] M_AXI_GP0_ARQOS;
|
||||
output [3 : 0] M_AXI_GP0_AWCACHE;
|
||||
output [3 : 0] M_AXI_GP0_AWLEN;
|
||||
output [3 : 0] M_AXI_GP0_AWQOS;
|
||||
output [3 : 0] M_AXI_GP0_WSTRB;
|
||||
input M_AXI_GP0_ACLK;
|
||||
input M_AXI_GP0_ARREADY;
|
||||
input M_AXI_GP0_AWREADY;
|
||||
input M_AXI_GP0_BVALID;
|
||||
input M_AXI_GP0_RLAST;
|
||||
input M_AXI_GP0_RVALID;
|
||||
input M_AXI_GP0_WREADY;
|
||||
input [11 : 0] M_AXI_GP0_BID;
|
||||
input [11 : 0] M_AXI_GP0_RID;
|
||||
input [1 : 0] M_AXI_GP0_BRESP;
|
||||
input [1 : 0] M_AXI_GP0_RRESP;
|
||||
input [31 : 0] M_AXI_GP0_RDATA;
|
||||
input [0 : 0] IRQ_F2P;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_CLK1;
|
||||
output FCLK_RESET0_N;
|
||||
input [53 : 0] MIO;
|
||||
input DDR_CAS_n;
|
||||
input DDR_CKE;
|
||||
input DDR_Clk_n;
|
||||
input DDR_Clk;
|
||||
input DDR_CS_n;
|
||||
input DDR_DRSTB;
|
||||
input DDR_ODT;
|
||||
input DDR_RAS_n;
|
||||
input DDR_WEB;
|
||||
input [2 : 0] DDR_BankAddr;
|
||||
input [14 : 0] DDR_Addr;
|
||||
input DDR_VRN;
|
||||
input DDR_VRP;
|
||||
input [3 : 0] DDR_DM;
|
||||
input [31 : 0] DDR_DQ;
|
||||
input [3 : 0] DDR_DQS_n;
|
||||
input [3 : 0] DDR_DQS;
|
||||
input PS_SRSTB;
|
||||
input PS_CLK;
|
||||
input PS_PORB;
|
||||
|
||||
processing_system7_vip_v1_0_7 #(
|
||||
.C_USE_M_AXI_GP0(1),
|
||||
.C_USE_M_AXI_GP1(0),
|
||||
.C_USE_S_AXI_ACP(0),
|
||||
.C_USE_S_AXI_GP0(0),
|
||||
.C_USE_S_AXI_GP1(0),
|
||||
.C_USE_S_AXI_HP0(0),
|
||||
.C_USE_S_AXI_HP1(0),
|
||||
.C_USE_S_AXI_HP2(0),
|
||||
.C_USE_S_AXI_HP3(0),
|
||||
.C_S_AXI_HP0_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP1_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP2_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP3_DATA_WIDTH(64),
|
||||
.C_HIGH_OCM_EN(0),
|
||||
.C_FCLK_CLK0_FREQ(50.0),
|
||||
.C_FCLK_CLK1_FREQ(200.0),
|
||||
.C_FCLK_CLK2_FREQ(10.0),
|
||||
.C_FCLK_CLK3_FREQ(10.0),
|
||||
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
|
||||
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
|
||||
) inst (
|
||||
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
|
||||
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_WID(M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
|
||||
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_BID(M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_RID(M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP1_ARVALID(),
|
||||
.M_AXI_GP1_AWVALID(),
|
||||
.M_AXI_GP1_BREADY(),
|
||||
.M_AXI_GP1_RREADY(),
|
||||
.M_AXI_GP1_WLAST(),
|
||||
.M_AXI_GP1_WVALID(),
|
||||
.M_AXI_GP1_ARID(),
|
||||
.M_AXI_GP1_AWID(),
|
||||
.M_AXI_GP1_WID(),
|
||||
.M_AXI_GP1_ARBURST(),
|
||||
.M_AXI_GP1_ARLOCK(),
|
||||
.M_AXI_GP1_ARSIZE(),
|
||||
.M_AXI_GP1_AWBURST(),
|
||||
.M_AXI_GP1_AWLOCK(),
|
||||
.M_AXI_GP1_AWSIZE(),
|
||||
.M_AXI_GP1_ARPROT(),
|
||||
.M_AXI_GP1_AWPROT(),
|
||||
.M_AXI_GP1_ARADDR(),
|
||||
.M_AXI_GP1_AWADDR(),
|
||||
.M_AXI_GP1_WDATA(),
|
||||
.M_AXI_GP1_ARCACHE(),
|
||||
.M_AXI_GP1_ARLEN(),
|
||||
.M_AXI_GP1_ARQOS(),
|
||||
.M_AXI_GP1_AWCACHE(),
|
||||
.M_AXI_GP1_AWLEN(),
|
||||
.M_AXI_GP1_AWQOS(),
|
||||
.M_AXI_GP1_WSTRB(),
|
||||
.M_AXI_GP1_ACLK(1'B0),
|
||||
.M_AXI_GP1_ARREADY(1'B0),
|
||||
.M_AXI_GP1_AWREADY(1'B0),
|
||||
.M_AXI_GP1_BVALID(1'B0),
|
||||
.M_AXI_GP1_RLAST(1'B0),
|
||||
.M_AXI_GP1_RVALID(1'B0),
|
||||
.M_AXI_GP1_WREADY(1'B0),
|
||||
.M_AXI_GP1_BID(12'B0),
|
||||
.M_AXI_GP1_RID(12'B0),
|
||||
.M_AXI_GP1_BRESP(2'B0),
|
||||
.M_AXI_GP1_RRESP(2'B0),
|
||||
.M_AXI_GP1_RDATA(32'B0),
|
||||
.S_AXI_GP0_ARREADY(),
|
||||
.S_AXI_GP0_AWREADY(),
|
||||
.S_AXI_GP0_BVALID(),
|
||||
.S_AXI_GP0_RLAST(),
|
||||
.S_AXI_GP0_RVALID(),
|
||||
.S_AXI_GP0_WREADY(),
|
||||
.S_AXI_GP0_BRESP(),
|
||||
.S_AXI_GP0_RRESP(),
|
||||
.S_AXI_GP0_RDATA(),
|
||||
.S_AXI_GP0_BID(),
|
||||
.S_AXI_GP0_RID(),
|
||||
.S_AXI_GP0_ACLK(1'B0),
|
||||
.S_AXI_GP0_ARVALID(1'B0),
|
||||
.S_AXI_GP0_AWVALID(1'B0),
|
||||
.S_AXI_GP0_BREADY(1'B0),
|
||||
.S_AXI_GP0_RREADY(1'B0),
|
||||
.S_AXI_GP0_WLAST(1'B0),
|
||||
.S_AXI_GP0_WVALID(1'B0),
|
||||
.S_AXI_GP0_ARBURST(2'B0),
|
||||
.S_AXI_GP0_ARLOCK(2'B0),
|
||||
.S_AXI_GP0_ARSIZE(3'B0),
|
||||
.S_AXI_GP0_AWBURST(2'B0),
|
||||
.S_AXI_GP0_AWLOCK(2'B0),
|
||||
.S_AXI_GP0_AWSIZE(3'B0),
|
||||
.S_AXI_GP0_ARPROT(3'B0),
|
||||
.S_AXI_GP0_AWPROT(3'B0),
|
||||
.S_AXI_GP0_ARADDR(32'B0),
|
||||
.S_AXI_GP0_AWADDR(32'B0),
|
||||
.S_AXI_GP0_WDATA(32'B0),
|
||||
.S_AXI_GP0_ARCACHE(4'B0),
|
||||
.S_AXI_GP0_ARLEN(4'B0),
|
||||
.S_AXI_GP0_ARQOS(4'B0),
|
||||
.S_AXI_GP0_AWCACHE(4'B0),
|
||||
.S_AXI_GP0_AWLEN(4'B0),
|
||||
.S_AXI_GP0_AWQOS(4'B0),
|
||||
.S_AXI_GP0_WSTRB(4'B0),
|
||||
.S_AXI_GP0_ARID(6'B0),
|
||||
.S_AXI_GP0_AWID(6'B0),
|
||||
.S_AXI_GP0_WID(6'B0),
|
||||
.S_AXI_GP1_ARREADY(),
|
||||
.S_AXI_GP1_AWREADY(),
|
||||
.S_AXI_GP1_BVALID(),
|
||||
.S_AXI_GP1_RLAST(),
|
||||
.S_AXI_GP1_RVALID(),
|
||||
.S_AXI_GP1_WREADY(),
|
||||
.S_AXI_GP1_BRESP(),
|
||||
.S_AXI_GP1_RRESP(),
|
||||
.S_AXI_GP1_RDATA(),
|
||||
.S_AXI_GP1_BID(),
|
||||
.S_AXI_GP1_RID(),
|
||||
.S_AXI_GP1_ACLK(1'B0),
|
||||
.S_AXI_GP1_ARVALID(1'B0),
|
||||
.S_AXI_GP1_AWVALID(1'B0),
|
||||
.S_AXI_GP1_BREADY(1'B0),
|
||||
.S_AXI_GP1_RREADY(1'B0),
|
||||
.S_AXI_GP1_WLAST(1'B0),
|
||||
.S_AXI_GP1_WVALID(1'B0),
|
||||
.S_AXI_GP1_ARBURST(2'B0),
|
||||
.S_AXI_GP1_ARLOCK(2'B0),
|
||||
.S_AXI_GP1_ARSIZE(3'B0),
|
||||
.S_AXI_GP1_AWBURST(2'B0),
|
||||
.S_AXI_GP1_AWLOCK(2'B0),
|
||||
.S_AXI_GP1_AWSIZE(3'B0),
|
||||
.S_AXI_GP1_ARPROT(3'B0),
|
||||
.S_AXI_GP1_AWPROT(3'B0),
|
||||
.S_AXI_GP1_ARADDR(32'B0),
|
||||
.S_AXI_GP1_AWADDR(32'B0),
|
||||
.S_AXI_GP1_WDATA(32'B0),
|
||||
.S_AXI_GP1_ARCACHE(4'B0),
|
||||
.S_AXI_GP1_ARLEN(4'B0),
|
||||
.S_AXI_GP1_ARQOS(4'B0),
|
||||
.S_AXI_GP1_AWCACHE(4'B0),
|
||||
.S_AXI_GP1_AWLEN(4'B0),
|
||||
.S_AXI_GP1_AWQOS(4'B0),
|
||||
.S_AXI_GP1_WSTRB(4'B0),
|
||||
.S_AXI_GP1_ARID(6'B0),
|
||||
.S_AXI_GP1_AWID(6'B0),
|
||||
.S_AXI_GP1_WID(6'B0),
|
||||
.S_AXI_ACP_ARREADY(),
|
||||
.S_AXI_ACP_AWREADY(),
|
||||
.S_AXI_ACP_BVALID(),
|
||||
.S_AXI_ACP_RLAST(),
|
||||
.S_AXI_ACP_RVALID(),
|
||||
.S_AXI_ACP_WREADY(),
|
||||
.S_AXI_ACP_BRESP(),
|
||||
.S_AXI_ACP_RRESP(),
|
||||
.S_AXI_ACP_BID(),
|
||||
.S_AXI_ACP_RID(),
|
||||
.S_AXI_ACP_RDATA(),
|
||||
.S_AXI_ACP_ACLK(1'B0),
|
||||
.S_AXI_ACP_ARVALID(1'B0),
|
||||
.S_AXI_ACP_AWVALID(1'B0),
|
||||
.S_AXI_ACP_BREADY(1'B0),
|
||||
.S_AXI_ACP_RREADY(1'B0),
|
||||
.S_AXI_ACP_WLAST(1'B0),
|
||||
.S_AXI_ACP_WVALID(1'B0),
|
||||
.S_AXI_ACP_ARID(3'B0),
|
||||
.S_AXI_ACP_ARPROT(3'B0),
|
||||
.S_AXI_ACP_AWID(3'B0),
|
||||
.S_AXI_ACP_AWPROT(3'B0),
|
||||
.S_AXI_ACP_WID(3'B0),
|
||||
.S_AXI_ACP_ARADDR(32'B0),
|
||||
.S_AXI_ACP_AWADDR(32'B0),
|
||||
.S_AXI_ACP_ARCACHE(4'B0),
|
||||
.S_AXI_ACP_ARLEN(4'B0),
|
||||
.S_AXI_ACP_ARQOS(4'B0),
|
||||
.S_AXI_ACP_AWCACHE(4'B0),
|
||||
.S_AXI_ACP_AWLEN(4'B0),
|
||||
.S_AXI_ACP_AWQOS(4'B0),
|
||||
.S_AXI_ACP_ARBURST(2'B0),
|
||||
.S_AXI_ACP_ARLOCK(2'B0),
|
||||
.S_AXI_ACP_ARSIZE(3'B0),
|
||||
.S_AXI_ACP_AWBURST(2'B0),
|
||||
.S_AXI_ACP_AWLOCK(2'B0),
|
||||
.S_AXI_ACP_AWSIZE(3'B0),
|
||||
.S_AXI_ACP_ARUSER(5'B0),
|
||||
.S_AXI_ACP_AWUSER(5'B0),
|
||||
.S_AXI_ACP_WDATA(64'B0),
|
||||
.S_AXI_ACP_WSTRB(8'B0),
|
||||
.S_AXI_HP0_ARREADY(),
|
||||
.S_AXI_HP0_AWREADY(),
|
||||
.S_AXI_HP0_BVALID(),
|
||||
.S_AXI_HP0_RLAST(),
|
||||
.S_AXI_HP0_RVALID(),
|
||||
.S_AXI_HP0_WREADY(),
|
||||
.S_AXI_HP0_BRESP(),
|
||||
.S_AXI_HP0_RRESP(),
|
||||
.S_AXI_HP0_BID(),
|
||||
.S_AXI_HP0_RID(),
|
||||
.S_AXI_HP0_RDATA(),
|
||||
.S_AXI_HP0_ACLK(1'B0),
|
||||
.S_AXI_HP0_ARVALID(1'B0),
|
||||
.S_AXI_HP0_AWVALID(1'B0),
|
||||
.S_AXI_HP0_BREADY(1'B0),
|
||||
.S_AXI_HP0_RREADY(1'B0),
|
||||
.S_AXI_HP0_WLAST(1'B0),
|
||||
.S_AXI_HP0_WVALID(1'B0),
|
||||
.S_AXI_HP0_ARBURST(2'B0),
|
||||
.S_AXI_HP0_ARLOCK(2'B0),
|
||||
.S_AXI_HP0_ARSIZE(3'B0),
|
||||
.S_AXI_HP0_AWBURST(2'B0),
|
||||
.S_AXI_HP0_AWLOCK(2'B0),
|
||||
.S_AXI_HP0_AWSIZE(3'B0),
|
||||
.S_AXI_HP0_ARPROT(3'B0),
|
||||
.S_AXI_HP0_AWPROT(3'B0),
|
||||
.S_AXI_HP0_ARADDR(32'B0),
|
||||
.S_AXI_HP0_AWADDR(32'B0),
|
||||
.S_AXI_HP0_ARCACHE(4'B0),
|
||||
.S_AXI_HP0_ARLEN(4'B0),
|
||||
.S_AXI_HP0_ARQOS(4'B0),
|
||||
.S_AXI_HP0_AWCACHE(4'B0),
|
||||
.S_AXI_HP0_AWLEN(4'B0),
|
||||
.S_AXI_HP0_AWQOS(4'B0),
|
||||
.S_AXI_HP0_ARID(6'B0),
|
||||
.S_AXI_HP0_AWID(6'B0),
|
||||
.S_AXI_HP0_WID(6'B0),
|
||||
.S_AXI_HP0_WDATA(64'B0),
|
||||
.S_AXI_HP0_WSTRB(8'B0),
|
||||
.S_AXI_HP1_ARREADY(),
|
||||
.S_AXI_HP1_AWREADY(),
|
||||
.S_AXI_HP1_BVALID(),
|
||||
.S_AXI_HP1_RLAST(),
|
||||
.S_AXI_HP1_RVALID(),
|
||||
.S_AXI_HP1_WREADY(),
|
||||
.S_AXI_HP1_BRESP(),
|
||||
.S_AXI_HP1_RRESP(),
|
||||
.S_AXI_HP1_BID(),
|
||||
.S_AXI_HP1_RID(),
|
||||
.S_AXI_HP1_RDATA(),
|
||||
.S_AXI_HP1_ACLK(1'B0),
|
||||
.S_AXI_HP1_ARVALID(1'B0),
|
||||
.S_AXI_HP1_AWVALID(1'B0),
|
||||
.S_AXI_HP1_BREADY(1'B0),
|
||||
.S_AXI_HP1_RREADY(1'B0),
|
||||
.S_AXI_HP1_WLAST(1'B0),
|
||||
.S_AXI_HP1_WVALID(1'B0),
|
||||
.S_AXI_HP1_ARBURST(2'B0),
|
||||
.S_AXI_HP1_ARLOCK(2'B0),
|
||||
.S_AXI_HP1_ARSIZE(3'B0),
|
||||
.S_AXI_HP1_AWBURST(2'B0),
|
||||
.S_AXI_HP1_AWLOCK(2'B0),
|
||||
.S_AXI_HP1_AWSIZE(3'B0),
|
||||
.S_AXI_HP1_ARPROT(3'B0),
|
||||
.S_AXI_HP1_AWPROT(3'B0),
|
||||
.S_AXI_HP1_ARADDR(32'B0),
|
||||
.S_AXI_HP1_AWADDR(32'B0),
|
||||
.S_AXI_HP1_ARCACHE(4'B0),
|
||||
.S_AXI_HP1_ARLEN(4'B0),
|
||||
.S_AXI_HP1_ARQOS(4'B0),
|
||||
.S_AXI_HP1_AWCACHE(4'B0),
|
||||
.S_AXI_HP1_AWLEN(4'B0),
|
||||
.S_AXI_HP1_AWQOS(4'B0),
|
||||
.S_AXI_HP1_ARID(6'B0),
|
||||
.S_AXI_HP1_AWID(6'B0),
|
||||
.S_AXI_HP1_WID(6'B0),
|
||||
.S_AXI_HP1_WDATA(64'B0),
|
||||
.S_AXI_HP1_WSTRB(8'B0),
|
||||
.S_AXI_HP2_ARREADY(),
|
||||
.S_AXI_HP2_AWREADY(),
|
||||
.S_AXI_HP2_BVALID(),
|
||||
.S_AXI_HP2_RLAST(),
|
||||
.S_AXI_HP2_RVALID(),
|
||||
.S_AXI_HP2_WREADY(),
|
||||
.S_AXI_HP2_BRESP(),
|
||||
.S_AXI_HP2_RRESP(),
|
||||
.S_AXI_HP2_BID(),
|
||||
.S_AXI_HP2_RID(),
|
||||
.S_AXI_HP2_RDATA(),
|
||||
.S_AXI_HP2_ACLK(1'B0),
|
||||
.S_AXI_HP2_ARVALID(1'B0),
|
||||
.S_AXI_HP2_AWVALID(1'B0),
|
||||
.S_AXI_HP2_BREADY(1'B0),
|
||||
.S_AXI_HP2_RREADY(1'B0),
|
||||
.S_AXI_HP2_WLAST(1'B0),
|
||||
.S_AXI_HP2_WVALID(1'B0),
|
||||
.S_AXI_HP2_ARBURST(2'B0),
|
||||
.S_AXI_HP2_ARLOCK(2'B0),
|
||||
.S_AXI_HP2_ARSIZE(3'B0),
|
||||
.S_AXI_HP2_AWBURST(2'B0),
|
||||
.S_AXI_HP2_AWLOCK(2'B0),
|
||||
.S_AXI_HP2_AWSIZE(3'B0),
|
||||
.S_AXI_HP2_ARPROT(3'B0),
|
||||
.S_AXI_HP2_AWPROT(3'B0),
|
||||
.S_AXI_HP2_ARADDR(32'B0),
|
||||
.S_AXI_HP2_AWADDR(32'B0),
|
||||
.S_AXI_HP2_ARCACHE(4'B0),
|
||||
.S_AXI_HP2_ARLEN(4'B0),
|
||||
.S_AXI_HP2_ARQOS(4'B0),
|
||||
.S_AXI_HP2_AWCACHE(4'B0),
|
||||
.S_AXI_HP2_AWLEN(4'B0),
|
||||
.S_AXI_HP2_AWQOS(4'B0),
|
||||
.S_AXI_HP2_ARID(6'B0),
|
||||
.S_AXI_HP2_AWID(6'B0),
|
||||
.S_AXI_HP2_WID(6'B0),
|
||||
.S_AXI_HP2_WDATA(64'B0),
|
||||
.S_AXI_HP2_WSTRB(8'B0),
|
||||
.S_AXI_HP3_ARREADY(),
|
||||
.S_AXI_HP3_AWREADY(),
|
||||
.S_AXI_HP3_BVALID(),
|
||||
.S_AXI_HP3_RLAST(),
|
||||
.S_AXI_HP3_RVALID(),
|
||||
.S_AXI_HP3_WREADY(),
|
||||
.S_AXI_HP3_BRESP(),
|
||||
.S_AXI_HP3_RRESP(),
|
||||
.S_AXI_HP3_BID(),
|
||||
.S_AXI_HP3_RID(),
|
||||
.S_AXI_HP3_RDATA(),
|
||||
.S_AXI_HP3_ACLK(1'B0),
|
||||
.S_AXI_HP3_ARVALID(1'B0),
|
||||
.S_AXI_HP3_AWVALID(1'B0),
|
||||
.S_AXI_HP3_BREADY(1'B0),
|
||||
.S_AXI_HP3_RREADY(1'B0),
|
||||
.S_AXI_HP3_WLAST(1'B0),
|
||||
.S_AXI_HP3_WVALID(1'B0),
|
||||
.S_AXI_HP3_ARBURST(2'B0),
|
||||
.S_AXI_HP3_ARLOCK(2'B0),
|
||||
.S_AXI_HP3_ARSIZE(3'B0),
|
||||
.S_AXI_HP3_AWBURST(2'B0),
|
||||
.S_AXI_HP3_AWLOCK(2'B0),
|
||||
.S_AXI_HP3_AWSIZE(3'B0),
|
||||
.S_AXI_HP3_ARPROT(3'B0),
|
||||
.S_AXI_HP3_AWPROT(3'B0),
|
||||
.S_AXI_HP3_ARADDR(32'B0),
|
||||
.S_AXI_HP3_AWADDR(32'B0),
|
||||
.S_AXI_HP3_ARCACHE(4'B0),
|
||||
.S_AXI_HP3_ARLEN(4'B0),
|
||||
.S_AXI_HP3_ARQOS(4'B0),
|
||||
.S_AXI_HP3_AWCACHE(4'B0),
|
||||
.S_AXI_HP3_AWLEN(4'B0),
|
||||
.S_AXI_HP3_AWQOS(4'B0),
|
||||
.S_AXI_HP3_ARID(6'B0),
|
||||
.S_AXI_HP3_AWID(6'B0),
|
||||
.S_AXI_HP3_WID(6'B0),
|
||||
.S_AXI_HP3_WDATA(64'B0),
|
||||
.S_AXI_HP3_WSTRB(8'B0),
|
||||
.FCLK_CLK0(FCLK_CLK0),
|
||||
|
||||
.FCLK_CLK1(FCLK_CLK1),
|
||||
|
||||
.FCLK_CLK2(),
|
||||
|
||||
.FCLK_CLK3(),
|
||||
.FCLK_RESET0_N(FCLK_RESET0_N),
|
||||
.FCLK_RESET1_N(),
|
||||
.FCLK_RESET2_N(),
|
||||
.FCLK_RESET3_N(),
|
||||
.IRQ_F2P(IRQ_F2P),
|
||||
.PS_SRSTB(PS_SRSTB),
|
||||
.PS_CLK(PS_CLK),
|
||||
.PS_PORB(PS_PORB)
|
||||
);
|
||||
endmodule
|
||||
+1005
File diff suppressed because it is too large
Load Diff
BIN
Binary file not shown.
+1885
File diff suppressed because it is too large
Load Diff
+695
@@ -0,0 +1,695 @@
|
||||
############################################################################
|
||||
##
|
||||
## Xilinx, Inc. 2006 www.xilinx.com
|
||||
############################################################################
|
||||
## File name : ps7_constraints.xdc
|
||||
##
|
||||
## Details : Constraints file
|
||||
## FPGA family: zynq
|
||||
## FPGA: xc7z100ffg900-2
|
||||
## Device Size: xc7z100
|
||||
## Package: ffg900
|
||||
## Speedgrade: -2
|
||||
##
|
||||
##
|
||||
############################################################################
|
||||
############################################################################
|
||||
############################################################################
|
||||
# Clock constraints #
|
||||
############################################################################
|
||||
create_clock -name clk_fpga_0 -period "20" [get_pins "PS7_i/FCLKCLK[0]"]
|
||||
set_input_jitter clk_fpga_0 0.6
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_1 -period "5" [get_pins "PS7_i/FCLKCLK[1]"]
|
||||
set_input_jitter clk_fpga_1 0.15
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
|
||||
|
||||
############################################################################
|
||||
# I/O STANDARDS and Location Constraints #
|
||||
############################################################################
|
||||
|
||||
# GPIO / gpio[53] / MIO[53]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
|
||||
set_property PACKAGE_PIN "C18" [get_ports "MIO[53]"]
|
||||
set_property slew "slow" [get_ports "MIO[53]"]
|
||||
set_property drive "8" [get_ports "MIO[53]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[53]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
|
||||
# GPIO / gpio[52] / MIO[52]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
|
||||
set_property PACKAGE_PIN "D19" [get_ports "MIO[52]"]
|
||||
set_property slew "slow" [get_ports "MIO[52]"]
|
||||
set_property drive "8" [get_ports "MIO[52]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[52]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[52]"]
|
||||
# GPIO / gpio[51] / MIO[51]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
|
||||
set_property PACKAGE_PIN "F19" [get_ports "MIO[51]"]
|
||||
set_property slew "slow" [get_ports "MIO[51]"]
|
||||
set_property drive "8" [get_ports "MIO[51]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"]
|
||||
# GPIO / gpio[50] / MIO[50]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
|
||||
set_property PACKAGE_PIN "A19" [get_ports "MIO[50]"]
|
||||
set_property slew "slow" [get_ports "MIO[50]"]
|
||||
set_property drive "8" [get_ports "MIO[50]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"]
|
||||
# GPIO / gpio[49] / MIO[49]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
|
||||
set_property PACKAGE_PIN "D18" [get_ports "MIO[49]"]
|
||||
set_property slew "slow" [get_ports "MIO[49]"]
|
||||
set_property drive "8" [get_ports "MIO[49]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[49]"]
|
||||
# GPIO / gpio[48] / MIO[48]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
|
||||
set_property PACKAGE_PIN "C19" [get_ports "MIO[48]"]
|
||||
set_property slew "slow" [get_ports "MIO[48]"]
|
||||
set_property drive "8" [get_ports "MIO[48]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[48]"]
|
||||
# GPIO / gpio[47] / MIO[47]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
|
||||
set_property PACKAGE_PIN "A18" [get_ports "MIO[47]"]
|
||||
set_property slew "slow" [get_ports "MIO[47]"]
|
||||
set_property drive "8" [get_ports "MIO[47]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[47]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[47]"]
|
||||
# GPIO / gpio[46] / MIO[46]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
|
||||
set_property PACKAGE_PIN "F20" [get_ports "MIO[46]"]
|
||||
set_property slew "slow" [get_ports "MIO[46]"]
|
||||
set_property drive "8" [get_ports "MIO[46]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[46]"]
|
||||
# GPIO / gpio[45] / MIO[45]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
|
||||
set_property PACKAGE_PIN "H18" [get_ports "MIO[45]"]
|
||||
set_property slew "slow" [get_ports "MIO[45]"]
|
||||
set_property drive "8" [get_ports "MIO[45]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
|
||||
# GPIO / gpio[44] / MIO[44]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
|
||||
set_property PACKAGE_PIN "E20" [get_ports "MIO[44]"]
|
||||
set_property slew "slow" [get_ports "MIO[44]"]
|
||||
set_property drive "8" [get_ports "MIO[44]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
|
||||
# GPIO / gpio[43] / MIO[43]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
|
||||
set_property PACKAGE_PIN "E18" [get_ports "MIO[43]"]
|
||||
set_property slew "slow" [get_ports "MIO[43]"]
|
||||
set_property drive "8" [get_ports "MIO[43]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
|
||||
# GPIO / gpio[42] / MIO[42]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
|
||||
set_property PACKAGE_PIN "D20" [get_ports "MIO[42]"]
|
||||
set_property slew "slow" [get_ports "MIO[42]"]
|
||||
set_property drive "8" [get_ports "MIO[42]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
|
||||
# GPIO / gpio[41] / MIO[41]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
|
||||
set_property PACKAGE_PIN "J18" [get_ports "MIO[41]"]
|
||||
set_property slew "slow" [get_ports "MIO[41]"]
|
||||
set_property drive "8" [get_ports "MIO[41]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
|
||||
# GPIO / gpio[40] / MIO[40]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
|
||||
set_property PACKAGE_PIN "B20" [get_ports "MIO[40]"]
|
||||
set_property slew "slow" [get_ports "MIO[40]"]
|
||||
set_property drive "8" [get_ports "MIO[40]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
|
||||
# GPIO / gpio[39] / MIO[39]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
|
||||
set_property PACKAGE_PIN "F18" [get_ports "MIO[39]"]
|
||||
set_property slew "slow" [get_ports "MIO[39]"]
|
||||
set_property drive "8" [get_ports "MIO[39]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
|
||||
# GPIO / gpio[38] / MIO[38]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
|
||||
set_property PACKAGE_PIN "A20" [get_ports "MIO[38]"]
|
||||
set_property slew "slow" [get_ports "MIO[38]"]
|
||||
set_property drive "8" [get_ports "MIO[38]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
|
||||
# GPIO / gpio[37] / MIO[37]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
|
||||
set_property PACKAGE_PIN "B21" [get_ports "MIO[37]"]
|
||||
set_property slew "slow" [get_ports "MIO[37]"]
|
||||
set_property drive "8" [get_ports "MIO[37]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
|
||||
# GPIO / gpio[36] / MIO[36]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
|
||||
set_property PACKAGE_PIN "H17" [get_ports "MIO[36]"]
|
||||
set_property slew "slow" [get_ports "MIO[36]"]
|
||||
set_property drive "8" [get_ports "MIO[36]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[36]"]
|
||||
# GPIO / gpio[35] / MIO[35]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
|
||||
set_property PACKAGE_PIN "G21" [get_ports "MIO[35]"]
|
||||
set_property slew "slow" [get_ports "MIO[35]"]
|
||||
set_property drive "8" [get_ports "MIO[35]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
|
||||
# GPIO / gpio[34] / MIO[34]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
|
||||
set_property PACKAGE_PIN "K18" [get_ports "MIO[34]"]
|
||||
set_property slew "slow" [get_ports "MIO[34]"]
|
||||
set_property drive "8" [get_ports "MIO[34]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
|
||||
# GPIO / gpio[33] / MIO[33]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
|
||||
set_property PACKAGE_PIN "G22" [get_ports "MIO[33]"]
|
||||
set_property slew "slow" [get_ports "MIO[33]"]
|
||||
set_property drive "8" [get_ports "MIO[33]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
|
||||
# GPIO / gpio[32] / MIO[32]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
|
||||
set_property PACKAGE_PIN "K17" [get_ports "MIO[32]"]
|
||||
set_property slew "slow" [get_ports "MIO[32]"]
|
||||
set_property drive "8" [get_ports "MIO[32]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
|
||||
# GPIO / gpio[31] / MIO[31]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
|
||||
set_property PACKAGE_PIN "H21" [get_ports "MIO[31]"]
|
||||
set_property slew "slow" [get_ports "MIO[31]"]
|
||||
set_property drive "8" [get_ports "MIO[31]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[31]"]
|
||||
# GPIO / gpio[30] / MIO[30]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
|
||||
set_property PACKAGE_PIN "L18" [get_ports "MIO[30]"]
|
||||
set_property slew "slow" [get_ports "MIO[30]"]
|
||||
set_property drive "8" [get_ports "MIO[30]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[30]"]
|
||||
# GPIO / gpio[29] / MIO[29]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
|
||||
set_property PACKAGE_PIN "H22" [get_ports "MIO[29]"]
|
||||
set_property slew "slow" [get_ports "MIO[29]"]
|
||||
set_property drive "8" [get_ports "MIO[29]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[29]"]
|
||||
# GPIO / gpio[28] / MIO[28]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
|
||||
set_property PACKAGE_PIN "L17" [get_ports "MIO[28]"]
|
||||
set_property slew "slow" [get_ports "MIO[28]"]
|
||||
set_property drive "8" [get_ports "MIO[28]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
|
||||
# GPIO / gpio[27] / MIO[27]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[27]"]
|
||||
set_property PACKAGE_PIN "G20" [get_ports "MIO[27]"]
|
||||
set_property slew "slow" [get_ports "MIO[27]"]
|
||||
set_property drive "8" [get_ports "MIO[27]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[27]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[27]"]
|
||||
# GPIO / gpio[26] / MIO[26]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[26]"]
|
||||
set_property PACKAGE_PIN "M17" [get_ports "MIO[26]"]
|
||||
set_property slew "slow" [get_ports "MIO[26]"]
|
||||
set_property drive "8" [get_ports "MIO[26]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[26]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[26]"]
|
||||
# GPIO / gpio[25] / MIO[25]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[25]"]
|
||||
set_property PACKAGE_PIN "G19" [get_ports "MIO[25]"]
|
||||
set_property slew "slow" [get_ports "MIO[25]"]
|
||||
set_property drive "8" [get_ports "MIO[25]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[25]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[25]"]
|
||||
# GPIO / gpio[24] / MIO[24]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[24]"]
|
||||
set_property PACKAGE_PIN "M19" [get_ports "MIO[24]"]
|
||||
set_property slew "slow" [get_ports "MIO[24]"]
|
||||
set_property drive "8" [get_ports "MIO[24]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[24]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[24]"]
|
||||
# GPIO / gpio[23] / MIO[23]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[23]"]
|
||||
set_property PACKAGE_PIN "J21" [get_ports "MIO[23]"]
|
||||
set_property slew "slow" [get_ports "MIO[23]"]
|
||||
set_property drive "8" [get_ports "MIO[23]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[23]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[23]"]
|
||||
# GPIO / gpio[22] / MIO[22]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[22]"]
|
||||
set_property PACKAGE_PIN "L20" [get_ports "MIO[22]"]
|
||||
set_property slew "slow" [get_ports "MIO[22]"]
|
||||
set_property drive "8" [get_ports "MIO[22]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[22]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[22]"]
|
||||
# GPIO / gpio[21] / MIO[21]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[21]"]
|
||||
set_property PACKAGE_PIN "J19" [get_ports "MIO[21]"]
|
||||
set_property slew "slow" [get_ports "MIO[21]"]
|
||||
set_property drive "8" [get_ports "MIO[21]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[21]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[21]"]
|
||||
# GPIO / gpio[20] / MIO[20]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[20]"]
|
||||
set_property PACKAGE_PIN "M20" [get_ports "MIO[20]"]
|
||||
set_property slew "slow" [get_ports "MIO[20]"]
|
||||
set_property drive "8" [get_ports "MIO[20]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[20]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[20]"]
|
||||
# GPIO / gpio[19] / MIO[19]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[19]"]
|
||||
set_property PACKAGE_PIN "J20" [get_ports "MIO[19]"]
|
||||
set_property slew "slow" [get_ports "MIO[19]"]
|
||||
set_property drive "8" [get_ports "MIO[19]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[19]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[19]"]
|
||||
# GPIO / gpio[18] / MIO[18]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[18]"]
|
||||
set_property PACKAGE_PIN "K20" [get_ports "MIO[18]"]
|
||||
set_property slew "slow" [get_ports "MIO[18]"]
|
||||
set_property drive "8" [get_ports "MIO[18]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[18]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[18]"]
|
||||
# GPIO / gpio[17] / MIO[17]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[17]"]
|
||||
set_property PACKAGE_PIN "K21" [get_ports "MIO[17]"]
|
||||
set_property slew "slow" [get_ports "MIO[17]"]
|
||||
set_property drive "8" [get_ports "MIO[17]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[17]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[17]"]
|
||||
# GPIO / gpio[16] / MIO[16]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[16]"]
|
||||
set_property PACKAGE_PIN "L19" [get_ports "MIO[16]"]
|
||||
set_property slew "slow" [get_ports "MIO[16]"]
|
||||
set_property drive "8" [get_ports "MIO[16]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[16]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[16]"]
|
||||
# GPIO / gpio[15] / MIO[15]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[15]"]
|
||||
set_property PACKAGE_PIN "C22" [get_ports "MIO[15]"]
|
||||
set_property slew "slow" [get_ports "MIO[15]"]
|
||||
set_property drive "8" [get_ports "MIO[15]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
|
||||
# GPIO / gpio[14] / MIO[14]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[14]"]
|
||||
set_property PACKAGE_PIN "B22" [get_ports "MIO[14]"]
|
||||
set_property slew "slow" [get_ports "MIO[14]"]
|
||||
set_property drive "8" [get_ports "MIO[14]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
|
||||
# GPIO / gpio[13] / MIO[13]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[13]"]
|
||||
set_property PACKAGE_PIN "F22" [get_ports "MIO[13]"]
|
||||
set_property slew "slow" [get_ports "MIO[13]"]
|
||||
set_property drive "8" [get_ports "MIO[13]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
|
||||
# GPIO / gpio[12] / MIO[12]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[12]"]
|
||||
set_property PACKAGE_PIN "E21" [get_ports "MIO[12]"]
|
||||
set_property slew "slow" [get_ports "MIO[12]"]
|
||||
set_property drive "8" [get_ports "MIO[12]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
|
||||
# GPIO / gpio[11] / MIO[11]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[11]"]
|
||||
set_property PACKAGE_PIN "A23" [get_ports "MIO[11]"]
|
||||
set_property slew "slow" [get_ports "MIO[11]"]
|
||||
set_property drive "8" [get_ports "MIO[11]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"]
|
||||
# GPIO / gpio[10] / MIO[10]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[10]"]
|
||||
set_property PACKAGE_PIN "E22" [get_ports "MIO[10]"]
|
||||
set_property slew "slow" [get_ports "MIO[10]"]
|
||||
set_property drive "8" [get_ports "MIO[10]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"]
|
||||
# GPIO / gpio[9] / MIO[9]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[9]"]
|
||||
set_property PACKAGE_PIN "A24" [get_ports "MIO[9]"]
|
||||
set_property slew "slow" [get_ports "MIO[9]"]
|
||||
set_property drive "8" [get_ports "MIO[9]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
|
||||
# GPIO / gpio[8] / MIO[8]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[8]"]
|
||||
set_property PACKAGE_PIN "C21" [get_ports "MIO[8]"]
|
||||
set_property slew "slow" [get_ports "MIO[8]"]
|
||||
set_property drive "8" [get_ports "MIO[8]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
|
||||
# GPIO / gpio[7] / MIO[7]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[7]"]
|
||||
set_property PACKAGE_PIN "B24" [get_ports "MIO[7]"]
|
||||
set_property slew "slow" [get_ports "MIO[7]"]
|
||||
set_property drive "8" [get_ports "MIO[7]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
|
||||
# Quad SPI Flash / qspi0_sclk / MIO[6]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[6]"]
|
||||
set_property PACKAGE_PIN "D24" [get_ports "MIO[6]"]
|
||||
set_property slew "slow" [get_ports "MIO[6]"]
|
||||
set_property drive "8" [get_ports "MIO[6]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
|
||||
# Quad SPI Flash / qspi0_io[3]/HOLD_B / MIO[5]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[5]"]
|
||||
set_property PACKAGE_PIN "C24" [get_ports "MIO[5]"]
|
||||
set_property slew "slow" [get_ports "MIO[5]"]
|
||||
set_property drive "8" [get_ports "MIO[5]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
|
||||
# Quad SPI Flash / qspi0_io[2] / MIO[4]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[4]"]
|
||||
set_property PACKAGE_PIN "E23" [get_ports "MIO[4]"]
|
||||
set_property slew "slow" [get_ports "MIO[4]"]
|
||||
set_property drive "8" [get_ports "MIO[4]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
|
||||
# Quad SPI Flash / qspi0_io[1] / MIO[3]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[3]"]
|
||||
set_property PACKAGE_PIN "C23" [get_ports "MIO[3]"]
|
||||
set_property slew "slow" [get_ports "MIO[3]"]
|
||||
set_property drive "8" [get_ports "MIO[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
|
||||
# Quad SPI Flash / qspi0_io[0] / MIO[2]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[2]"]
|
||||
set_property PACKAGE_PIN "F23" [get_ports "MIO[2]"]
|
||||
set_property slew "slow" [get_ports "MIO[2]"]
|
||||
set_property drive "8" [get_ports "MIO[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
|
||||
# Quad SPI Flash / qspi0_ss_b / MIO[1]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[1]"]
|
||||
set_property PACKAGE_PIN "D23" [get_ports "MIO[1]"]
|
||||
set_property slew "slow" [get_ports "MIO[1]"]
|
||||
set_property drive "8" [get_ports "MIO[1]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
|
||||
# GPIO / gpio[0] / MIO[0]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[0]"]
|
||||
set_property PACKAGE_PIN "F24" [get_ports "MIO[0]"]
|
||||
set_property slew "slow" [get_ports "MIO[0]"]
|
||||
set_property drive "8" [get_ports "MIO[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
|
||||
set_property PACKAGE_PIN "M21" [get_ports "DDR_VRP"]
|
||||
set_property slew "FAST" [get_ports "DDR_VRP"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"]
|
||||
set_property PACKAGE_PIN "N21" [get_ports "DDR_VRN"]
|
||||
set_property slew "FAST" [get_ports "DDR_VRN"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_WEB"]
|
||||
set_property PACKAGE_PIN "N23" [get_ports "DDR_WEB"]
|
||||
set_property slew "SLOW" [get_ports "DDR_WEB"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"]
|
||||
set_property PACKAGE_PIN "N24" [get_ports "DDR_RAS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_RAS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_ODT"]
|
||||
set_property PACKAGE_PIN "L23" [get_ports "DDR_ODT"]
|
||||
set_property slew "SLOW" [get_ports "DDR_ODT"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"]
|
||||
set_property PACKAGE_PIN "F25" [get_ports "DDR_DRSTB"]
|
||||
set_property slew "FAST" [get_ports "DDR_DRSTB"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"]
|
||||
set_property PACKAGE_PIN "L28" [get_ports "DDR_DQS[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[3]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQS[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"]
|
||||
set_property PACKAGE_PIN "G29" [get_ports "DDR_DQS[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[2]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQS[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"]
|
||||
set_property PACKAGE_PIN "C29" [get_ports "DDR_DQS[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"]
|
||||
set_property PACKAGE_PIN "C26" [get_ports "DDR_DQS[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property PACKAGE_PIN "L29" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property PACKAGE_PIN "F29" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property PACKAGE_PIN "B29" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property PACKAGE_PIN "B26" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"]
|
||||
set_property PACKAGE_PIN "A27" [get_ports "DDR_DQ[9]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[9]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"]
|
||||
set_property PACKAGE_PIN "A29" [get_ports "DDR_DQ[8]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[8]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"]
|
||||
set_property PACKAGE_PIN "E27" [get_ports "DDR_DQ[7]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[7]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"]
|
||||
set_property PACKAGE_PIN "D26" [get_ports "DDR_DQ[6]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[6]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"]
|
||||
set_property PACKAGE_PIN "E26" [get_ports "DDR_DQ[5]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[5]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"]
|
||||
set_property PACKAGE_PIN "B25" [get_ports "DDR_DQ[4]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[4]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"]
|
||||
set_property PACKAGE_PIN "D25" [get_ports "DDR_DQ[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"]
|
||||
set_property PACKAGE_PIN "M30" [get_ports "DDR_DQ[31]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[31]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[31]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"]
|
||||
set_property PACKAGE_PIN "L30" [get_ports "DDR_DQ[30]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[30]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[30]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"]
|
||||
set_property PACKAGE_PIN "B27" [get_ports "DDR_DQ[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"]
|
||||
set_property PACKAGE_PIN "M29" [get_ports "DDR_DQ[29]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[29]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[29]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"]
|
||||
set_property PACKAGE_PIN "K30" [get_ports "DDR_DQ[28]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[28]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[28]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"]
|
||||
set_property PACKAGE_PIN "J28" [get_ports "DDR_DQ[27]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[27]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[27]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"]
|
||||
set_property PACKAGE_PIN "J30" [get_ports "DDR_DQ[26]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[26]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[26]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"]
|
||||
set_property PACKAGE_PIN "K27" [get_ports "DDR_DQ[25]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[25]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[25]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"]
|
||||
set_property PACKAGE_PIN "J29" [get_ports "DDR_DQ[24]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[24]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[24]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"]
|
||||
set_property PACKAGE_PIN "F30" [get_ports "DDR_DQ[23]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[23]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[23]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"]
|
||||
set_property PACKAGE_PIN "G30" [get_ports "DDR_DQ[22]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[22]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[22]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"]
|
||||
set_property PACKAGE_PIN "F28" [get_ports "DDR_DQ[21]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[21]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[21]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"]
|
||||
set_property PACKAGE_PIN "E30" [get_ports "DDR_DQ[20]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[20]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[20]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"]
|
||||
set_property PACKAGE_PIN "E25" [get_ports "DDR_DQ[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"]
|
||||
set_property PACKAGE_PIN "E28" [get_ports "DDR_DQ[19]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[19]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[19]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"]
|
||||
set_property PACKAGE_PIN "H28" [get_ports "DDR_DQ[18]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[18]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[18]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"]
|
||||
set_property PACKAGE_PIN "G27" [get_ports "DDR_DQ[17]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[17]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[17]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"]
|
||||
set_property PACKAGE_PIN "H27" [get_ports "DDR_DQ[16]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[16]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[16]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"]
|
||||
set_property PACKAGE_PIN "D29" [get_ports "DDR_DQ[15]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[15]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"]
|
||||
set_property PACKAGE_PIN "D28" [get_ports "DDR_DQ[14]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[14]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"]
|
||||
set_property PACKAGE_PIN "D30" [get_ports "DDR_DQ[13]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[13]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"]
|
||||
set_property PACKAGE_PIN "C28" [get_ports "DDR_DQ[12]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[12]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"]
|
||||
set_property PACKAGE_PIN "A28" [get_ports "DDR_DQ[11]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[11]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"]
|
||||
set_property PACKAGE_PIN "A30" [get_ports "DDR_DQ[10]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[10]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"]
|
||||
set_property PACKAGE_PIN "A25" [get_ports "DDR_DQ[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"]
|
||||
set_property PACKAGE_PIN "K28" [get_ports "DDR_DM[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[3]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DM[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"]
|
||||
set_property PACKAGE_PIN "H29" [get_ports "DDR_DM[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[2]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DM[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"]
|
||||
set_property PACKAGE_PIN "B30" [get_ports "DDR_DM[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"]
|
||||
set_property PACKAGE_PIN "C27" [get_ports "DDR_DM[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_CS_n"]
|
||||
set_property PACKAGE_PIN "N22" [get_ports "DDR_CS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_CKE"]
|
||||
set_property PACKAGE_PIN "M22" [get_ports "DDR_CKE"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CKE"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
|
||||
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"]
|
||||
set_property PACKAGE_PIN "K25" [get_ports "DDR_Clk"]
|
||||
set_property slew "FAST" [get_ports "DDR_Clk"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
|
||||
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"]
|
||||
set_property PACKAGE_PIN "J25" [get_ports "DDR_Clk_n"]
|
||||
set_property slew "FAST" [get_ports "DDR_Clk_n"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"]
|
||||
set_property PACKAGE_PIN "M24" [get_ports "DDR_CAS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CAS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property PACKAGE_PIN "M25" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property PACKAGE_PIN "M26" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property PACKAGE_PIN "M27" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"]
|
||||
set_property PACKAGE_PIN "J23" [get_ports "DDR_Addr[9]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"]
|
||||
set_property PACKAGE_PIN "F27" [get_ports "DDR_Addr[8]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"]
|
||||
set_property PACKAGE_PIN "K22" [get_ports "DDR_Addr[7]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"]
|
||||
set_property PACKAGE_PIN "H26" [get_ports "DDR_Addr[6]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"]
|
||||
set_property PACKAGE_PIN "G24" [get_ports "DDR_Addr[5]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"]
|
||||
set_property PACKAGE_PIN "J26" [get_ports "DDR_Addr[4]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"]
|
||||
set_property PACKAGE_PIN "G25" [get_ports "DDR_Addr[3]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"]
|
||||
set_property PACKAGE_PIN "L27" [get_ports "DDR_Addr[2]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"]
|
||||
set_property PACKAGE_PIN "K26" [get_ports "DDR_Addr[1]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"]
|
||||
set_property PACKAGE_PIN "J24" [get_ports "DDR_Addr[14]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"]
|
||||
set_property PACKAGE_PIN "H23" [get_ports "DDR_Addr[13]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"]
|
||||
set_property PACKAGE_PIN "K23" [get_ports "DDR_Addr[12]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"]
|
||||
set_property PACKAGE_PIN "H24" [get_ports "DDR_Addr[11]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"]
|
||||
set_property PACKAGE_PIN "G26" [get_ports "DDR_Addr[10]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"]
|
||||
set_property PACKAGE_PIN "L25" [get_ports "DDR_Addr[0]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
|
||||
set_property iostandard "LVCMOS18" [get_ports "PS_PORB"]
|
||||
set_property PACKAGE_PIN "D21" [get_ports "PS_PORB"]
|
||||
set_property slew "fast" [get_ports "PS_PORB"]
|
||||
set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"]
|
||||
set_property PACKAGE_PIN "B19" [get_ports "PS_SRSTB"]
|
||||
set_property slew "fast" [get_ports "PS_SRSTB"]
|
||||
set_property iostandard "LVCMOS18" [get_ports "PS_CLK"]
|
||||
set_property PACKAGE_PIN "A22" [get_ports "PS_CLK"]
|
||||
set_property slew "fast" [get_ports "PS_CLK"]
|
||||
|
||||
+39260
File diff suppressed because it is too large
Load Diff
+5127
File diff suppressed because it is too large
Load Diff
+4490
File diff suppressed because it is too large
Load Diff
+97
@@ -0,0 +1,97 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:05:24 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_ps_system_0/system_bd_ps_system_0_stub.v
|
||||
// Design : system_bd_ps_system_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2019.1.3" *)
|
||||
module system_bd_ps_system_0(GPIO_I, GPIO_O, GPIO_T, M_AXI_GP0_ARVALID,
|
||||
M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID,
|
||||
M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK,
|
||||
M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE,
|
||||
M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA,
|
||||
M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN,
|
||||
M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY,
|
||||
M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID,
|
||||
M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0,
|
||||
FCLK_CLK1, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB,
|
||||
DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n,
|
||||
DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
|
||||
/* synthesis syn_black_box black_box_pad_pin="GPIO_I[47:0],GPIO_O[47:0],GPIO_T[47:0],M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
|
||||
input [47:0]GPIO_I;
|
||||
output [47:0]GPIO_O;
|
||||
output [47:0]GPIO_T;
|
||||
output M_AXI_GP0_ARVALID;
|
||||
output M_AXI_GP0_AWVALID;
|
||||
output M_AXI_GP0_BREADY;
|
||||
output M_AXI_GP0_RREADY;
|
||||
output M_AXI_GP0_WLAST;
|
||||
output M_AXI_GP0_WVALID;
|
||||
output [11:0]M_AXI_GP0_ARID;
|
||||
output [11:0]M_AXI_GP0_AWID;
|
||||
output [11:0]M_AXI_GP0_WID;
|
||||
output [1:0]M_AXI_GP0_ARBURST;
|
||||
output [1:0]M_AXI_GP0_ARLOCK;
|
||||
output [2:0]M_AXI_GP0_ARSIZE;
|
||||
output [1:0]M_AXI_GP0_AWBURST;
|
||||
output [1:0]M_AXI_GP0_AWLOCK;
|
||||
output [2:0]M_AXI_GP0_AWSIZE;
|
||||
output [2:0]M_AXI_GP0_ARPROT;
|
||||
output [2:0]M_AXI_GP0_AWPROT;
|
||||
output [31:0]M_AXI_GP0_ARADDR;
|
||||
output [31:0]M_AXI_GP0_AWADDR;
|
||||
output [31:0]M_AXI_GP0_WDATA;
|
||||
output [3:0]M_AXI_GP0_ARCACHE;
|
||||
output [3:0]M_AXI_GP0_ARLEN;
|
||||
output [3:0]M_AXI_GP0_ARQOS;
|
||||
output [3:0]M_AXI_GP0_AWCACHE;
|
||||
output [3:0]M_AXI_GP0_AWLEN;
|
||||
output [3:0]M_AXI_GP0_AWQOS;
|
||||
output [3:0]M_AXI_GP0_WSTRB;
|
||||
input M_AXI_GP0_ACLK;
|
||||
input M_AXI_GP0_ARREADY;
|
||||
input M_AXI_GP0_AWREADY;
|
||||
input M_AXI_GP0_BVALID;
|
||||
input M_AXI_GP0_RLAST;
|
||||
input M_AXI_GP0_RVALID;
|
||||
input M_AXI_GP0_WREADY;
|
||||
input [11:0]M_AXI_GP0_BID;
|
||||
input [11:0]M_AXI_GP0_RID;
|
||||
input [1:0]M_AXI_GP0_BRESP;
|
||||
input [1:0]M_AXI_GP0_RRESP;
|
||||
input [31:0]M_AXI_GP0_RDATA;
|
||||
input [0:0]IRQ_F2P;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_CLK1;
|
||||
output FCLK_RESET0_N;
|
||||
inout [53:0]MIO;
|
||||
inout DDR_CAS_n;
|
||||
inout DDR_CKE;
|
||||
inout DDR_Clk_n;
|
||||
inout DDR_Clk;
|
||||
inout DDR_CS_n;
|
||||
inout DDR_DRSTB;
|
||||
inout DDR_ODT;
|
||||
inout DDR_RAS_n;
|
||||
inout DDR_WEB;
|
||||
inout [2:0]DDR_BankAddr;
|
||||
inout [14:0]DDR_Addr;
|
||||
inout DDR_VRN;
|
||||
inout DDR_VRP;
|
||||
inout [3:0]DDR_DM;
|
||||
inout [31:0]DDR_DQ;
|
||||
inout [3:0]DDR_DQS_n;
|
||||
inout [3:0]DDR_DQS;
|
||||
inout PS_SRSTB;
|
||||
inout PS_CLK;
|
||||
inout PS_PORB;
|
||||
endmodule
|
||||
+96
@@ -0,0 +1,96 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:05:24 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_ps_system_0/system_bd_ps_system_0_stub.vhdl
|
||||
-- Design : system_bd_ps_system_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_ps_system_0 is
|
||||
Port (
|
||||
GPIO_I : in STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||
GPIO_O : out STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||
GPIO_T : out STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||
M_AXI_GP0_ARVALID : out STD_LOGIC;
|
||||
M_AXI_GP0_AWVALID : out STD_LOGIC;
|
||||
M_AXI_GP0_BREADY : out STD_LOGIC;
|
||||
M_AXI_GP0_RREADY : out STD_LOGIC;
|
||||
M_AXI_GP0_WLAST : out STD_LOGIC;
|
||||
M_AXI_GP0_WVALID : out STD_LOGIC;
|
||||
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_ACLK : in STD_LOGIC;
|
||||
M_AXI_GP0_ARREADY : in STD_LOGIC;
|
||||
M_AXI_GP0_AWREADY : in STD_LOGIC;
|
||||
M_AXI_GP0_BVALID : in STD_LOGIC;
|
||||
M_AXI_GP0_RLAST : in STD_LOGIC;
|
||||
M_AXI_GP0_RVALID : in STD_LOGIC;
|
||||
M_AXI_GP0_WREADY : in STD_LOGIC;
|
||||
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
FCLK_CLK0 : out STD_LOGIC;
|
||||
FCLK_CLK1 : out STD_LOGIC;
|
||||
FCLK_RESET0_N : out STD_LOGIC;
|
||||
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
|
||||
DDR_CAS_n : inout STD_LOGIC;
|
||||
DDR_CKE : inout STD_LOGIC;
|
||||
DDR_Clk_n : inout STD_LOGIC;
|
||||
DDR_Clk : inout STD_LOGIC;
|
||||
DDR_CS_n : inout STD_LOGIC;
|
||||
DDR_DRSTB : inout STD_LOGIC;
|
||||
DDR_ODT : inout STD_LOGIC;
|
||||
DDR_RAS_n : inout STD_LOGIC;
|
||||
DDR_WEB : inout STD_LOGIC;
|
||||
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
DDR_VRN : inout STD_LOGIC;
|
||||
DDR_VRP : inout STD_LOGIC;
|
||||
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
PS_SRSTB : inout STD_LOGIC;
|
||||
PS_CLK : inout STD_LOGIC;
|
||||
PS_PORB : inout STD_LOGIC
|
||||
);
|
||||
|
||||
end system_bd_ps_system_0;
|
||||
|
||||
architecture stub of system_bd_ps_system_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "GPIO_I[47:0],GPIO_O[47:0],GPIO_T[47:0],M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+147
@@ -0,0 +1,147 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY system_bd_rst_ps_system_50M_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END system_bd_rst_ps_system_50M_0;
|
||||
|
||||
ARCHITECTURE system_bd_rst_ps_system_50M_0_arch OF system_bd_rst_ps_system_50M_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_rst_ps_system_50M_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END system_bd_rst_ps_system_50M_0_arch;
|
||||
+153
@@ -0,0 +1,153 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY system_bd_rst_ps_system_50M_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END system_bd_rst_ps_system_50M_0;
|
||||
|
||||
ARCHITECTURE system_bd_rst_ps_system_50M_0_arch OF system_bd_rst_ps_system_50M_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_rst_ps_system_50M_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_bd_rst_ps_system_50M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2019.1.3";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_rst_ps_system_50M_0_arch : ARCHITECTURE IS "system_bd_rst_ps_system_50M_0,proc_sys_reset,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_bd_rst_ps_system_50M_0_arch: ARCHITECTURE IS "system_bd_rst_ps_system_50M_0,proc_sys_reset,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=13,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END system_bd_rst_ps_system_50M_0_arch;
|
||||
BIN
Binary file not shown.
+82
@@ -0,0 +1,82 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_rst_ps_system_50M_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="proc_sys_reset" spirit:version="5.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_rst_ps_system_50M_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
|
||||
# file: system_bd_rst_ps_system_50M_0.xdc
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
+942
@@ -0,0 +1,942 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>system_bd_rst_ps_system_50M_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clock</spirit:name>
|
||||
<spirit:displayName>Clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>slowest_sync_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
|
||||
<spirit:description>Slowest Synchronous clock frequency</spirit:description>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">50000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ext_reset</spirit:name>
|
||||
<spirit:displayName>Ext_Reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ext_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
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|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_rst_ps_system_50M_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_rst_ps_system_50M_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>Processor Reset System</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">system_bd_rst_ps_system_50M_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>USE_BOARD_FLOW</spirit:name>
|
||||
<spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RESET_BOARD_INTERFACE</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="3">Custom</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>Processor System Reset</xilinx:displayName>
|
||||
<xilinx:coreRevision>13</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.1.3</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 20 -name slowest_sync_clk [get_ports slowest_sync_clk]
|
||||
|
||||
|
||||
+951
@@ -0,0 +1,951 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:05:22 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_rst_ps_system_50M_0/system_bd_rst_ps_system_50M_0_sim_netlist.v
|
||||
// Design : system_bd_rst_ps_system_50M_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_rst_ps_system_50M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2019.1.3" *)
|
||||
(* NotValidForBitStream *)
|
||||
module system_bd_rst_ps_system_50M_0
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
|
||||
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *)
|
||||
(* C_AUX_RST_WIDTH = "4" *)
|
||||
(* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *)
|
||||
(* C_FAMILY = "zynq" *)
|
||||
(* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_RST = "1" *)
|
||||
system_bd_rst_ps_system_50M_0_proc_sys_reset U0
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.bus_struct_reset(bus_struct_reset),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.interconnect_aresetn(interconnect_aresetn),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.mb_reset(mb_reset),
|
||||
.peripheral_aresetn(peripheral_aresetn),
|
||||
.peripheral_reset(peripheral_reset),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module system_bd_rst_ps_system_50M_0_cdc_sync
|
||||
(lpf_asr_reg,
|
||||
scndry_out,
|
||||
lpf_asr,
|
||||
p_1_in,
|
||||
p_2_in,
|
||||
asr_lpf,
|
||||
aux_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_asr_reg;
|
||||
output scndry_out;
|
||||
input lpf_asr;
|
||||
input p_1_in;
|
||||
input p_2_in;
|
||||
input [0:0]asr_lpf;
|
||||
input aux_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire asr_d1;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_asr_reg;
|
||||
wire p_1_in;
|
||||
wire p_2_in;
|
||||
wire s_level_out_d1_cdc_to;
|
||||
wire s_level_out_d2;
|
||||
wire s_level_out_d3;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(asr_d1),
|
||||
.Q(s_level_out_d1_cdc_to),
|
||||
.R(1'b0));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
|
||||
(.I0(aux_reset_in),
|
||||
.O(asr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(s_level_out_d1_cdc_to),
|
||||
.Q(s_level_out_d2),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(s_level_out_d2),
|
||||
.Q(s_level_out_d3),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(s_level_out_d3),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_asr_i_1
|
||||
(.I0(lpf_asr),
|
||||
.I1(p_1_in),
|
||||
.I2(p_2_in),
|
||||
.I3(scndry_out),
|
||||
.I4(asr_lpf),
|
||||
.O(lpf_asr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module system_bd_rst_ps_system_50M_0_cdc_sync_0
|
||||
(lpf_exr_reg,
|
||||
scndry_out,
|
||||
lpf_exr,
|
||||
p_3_out,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_exr_reg;
|
||||
output scndry_out;
|
||||
input lpf_exr;
|
||||
input [2:0]p_3_out;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire exr_d1;
|
||||
wire ext_reset_in;
|
||||
wire lpf_exr;
|
||||
wire lpf_exr_reg;
|
||||
wire mb_debug_sys_rst;
|
||||
wire [2:0]p_3_out;
|
||||
wire s_level_out_d1_cdc_to;
|
||||
wire s_level_out_d2;
|
||||
wire s_level_out_d3;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(exr_d1),
|
||||
.Q(s_level_out_d1_cdc_to),
|
||||
.R(1'b0));
|
||||
LUT2 #(
|
||||
.INIT(4'hB))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
|
||||
(.I0(mb_debug_sys_rst),
|
||||
.I1(ext_reset_in),
|
||||
.O(exr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(s_level_out_d1_cdc_to),
|
||||
.Q(s_level_out_d2),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(s_level_out_d2),
|
||||
.Q(s_level_out_d3),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(s_level_out_d3),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_exr_i_1
|
||||
(.I0(lpf_exr),
|
||||
.I1(p_3_out[1]),
|
||||
.I2(p_3_out[2]),
|
||||
.I3(scndry_out),
|
||||
.I4(p_3_out[0]),
|
||||
.O(lpf_exr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "lpf" *)
|
||||
module system_bd_rst_ps_system_50M_0_lpf
|
||||
(lpf_int,
|
||||
slowest_sync_clk,
|
||||
dcm_locked,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
aux_reset_in);
|
||||
output lpf_int;
|
||||
input slowest_sync_clk;
|
||||
input dcm_locked;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
|
||||
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
|
||||
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
|
||||
wire Q;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_exr;
|
||||
wire lpf_int;
|
||||
wire lpf_int0__0;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in;
|
||||
wire p_2_in;
|
||||
wire p_3_in1_in;
|
||||
wire [3:0]p_3_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
system_bd_rst_ps_system_50M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
|
||||
(.asr_lpf(asr_lpf),
|
||||
.aux_reset_in(aux_reset_in),
|
||||
.lpf_asr(lpf_asr),
|
||||
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.p_1_in(p_1_in),
|
||||
.p_2_in(p_2_in),
|
||||
.scndry_out(p_3_in1_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
system_bd_rst_ps_system_50M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
|
||||
(.ext_reset_in(ext_reset_in),
|
||||
.lpf_exr(lpf_exr),
|
||||
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.p_3_out(p_3_out[2:0]),
|
||||
.scndry_out(p_3_out[3]),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[1].asr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in1_in),
|
||||
.Q(p_2_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[2].asr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in),
|
||||
.Q(p_1_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[3].asr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in),
|
||||
.Q(asr_lpf),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[1].exr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[3]),
|
||||
.Q(p_3_out[2]),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[2].exr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[2]),
|
||||
.Q(p_3_out[1]),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[3].exr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[1]),
|
||||
.Q(p_3_out[0]),
|
||||
.R(1'b0));
|
||||
(* XILINX_LEGACY_PRIM = "SRL16" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
|
||||
SRL16E #(
|
||||
.INIT(16'hFFFF))
|
||||
POR_SRL_I
|
||||
(.A0(1'b1),
|
||||
.A1(1'b1),
|
||||
.A2(1'b1),
|
||||
.A3(1'b1),
|
||||
.CE(1'b1),
|
||||
.CLK(slowest_sync_clk),
|
||||
.D(1'b0),
|
||||
.Q(Q));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_asr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.Q(lpf_asr),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_exr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.Q(lpf_exr),
|
||||
.R(1'b0));
|
||||
LUT4 #(
|
||||
.INIT(16'hFFFD))
|
||||
lpf_int0
|
||||
(.I0(dcm_locked),
|
||||
.I1(lpf_exr),
|
||||
.I2(lpf_asr),
|
||||
.I3(Q),
|
||||
.O(lpf_int0__0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_int_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(lpf_int0__0),
|
||||
.Q(lpf_int),
|
||||
.R(1'b0));
|
||||
endmodule
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
|
||||
(* ORIG_REF_NAME = "proc_sys_reset" *)
|
||||
module system_bd_rst_ps_system_50M_0_proc_sys_reset
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
input slowest_sync_clk;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
|
||||
wire Bsr_out;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire SEQ_n_3;
|
||||
wire SEQ_n_4;
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire lpf_int;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_3),
|
||||
.Q(interconnect_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_4),
|
||||
.Q(peripheral_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\BSR_OUT_DFF[0].FDRE_BSR
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Bsr_out),
|
||||
.Q(bus_struct_reset),
|
||||
.R(1'b0));
|
||||
system_bd_rst_ps_system_50M_0_lpf EXT_LPF
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_int(lpf_int),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
FDRE_inst
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(MB_out),
|
||||
.Q(mb_reset),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\PR_OUT_DFF[0].FDRE_PER
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Pr_out),
|
||||
.Q(peripheral_reset),
|
||||
.R(1'b0));
|
||||
system_bd_rst_ps_system_50M_0_sequence_psr SEQ
|
||||
(.Bsr_out(Bsr_out),
|
||||
.MB_out(MB_out),
|
||||
.Pr_out(Pr_out),
|
||||
.bsr_reg_0(SEQ_n_3),
|
||||
.lpf_int(lpf_int),
|
||||
.pr_reg_0(SEQ_n_4),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "sequence_psr" *)
|
||||
module system_bd_rst_ps_system_50M_0_sequence_psr
|
||||
(MB_out,
|
||||
Bsr_out,
|
||||
Pr_out,
|
||||
bsr_reg_0,
|
||||
pr_reg_0,
|
||||
lpf_int,
|
||||
slowest_sync_clk);
|
||||
output MB_out;
|
||||
output Bsr_out;
|
||||
output Pr_out;
|
||||
output bsr_reg_0;
|
||||
output pr_reg_0;
|
||||
input lpf_int;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire Bsr_out;
|
||||
wire Core_i_1_n_0;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire \bsr_dec_reg_n_0_[0] ;
|
||||
wire \bsr_dec_reg_n_0_[2] ;
|
||||
wire bsr_i_1_n_0;
|
||||
wire bsr_reg_0;
|
||||
wire \core_dec[0]_i_1_n_0 ;
|
||||
wire \core_dec[2]_i_1_n_0 ;
|
||||
wire \core_dec_reg_n_0_[0] ;
|
||||
wire \core_dec_reg_n_0_[1] ;
|
||||
wire from_sys_i_1_n_0;
|
||||
wire lpf_int;
|
||||
wire p_0_in;
|
||||
wire [2:0]p_3_out;
|
||||
wire [2:0]p_5_out;
|
||||
wire pr_dec0__0;
|
||||
wire \pr_dec_reg_n_0_[0] ;
|
||||
wire \pr_dec_reg_n_0_[2] ;
|
||||
wire pr_i_1_n_0;
|
||||
wire pr_reg_0;
|
||||
wire seq_clr;
|
||||
wire [5:0]seq_cnt;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
|
||||
(.I0(Bsr_out),
|
||||
.O(bsr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
|
||||
(.I0(Pr_out),
|
||||
.O(pr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
Core_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(p_0_in),
|
||||
.O(Core_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
Core_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Core_i_1_n_0),
|
||||
.Q(MB_out),
|
||||
.S(lpf_int));
|
||||
system_bd_rst_ps_system_50M_0_upcnt_n SEQ_COUNTER
|
||||
(.Q(seq_cnt),
|
||||
.seq_clr(seq_clr),
|
||||
.seq_cnt_en(seq_cnt_en),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
LUT4 #(
|
||||
.INIT(16'h0090))
|
||||
\bsr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(p_5_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\bsr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\bsr_dec_reg_n_0_[0] ),
|
||||
.O(p_5_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[0]),
|
||||
.Q(\bsr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[2]),
|
||||
.Q(\bsr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
bsr_i_1
|
||||
(.I0(Bsr_out),
|
||||
.I1(\bsr_dec_reg_n_0_[2] ),
|
||||
.O(bsr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
bsr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(bsr_i_1_n_0),
|
||||
.Q(Bsr_out),
|
||||
.S(lpf_int));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h9000))
|
||||
\core_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(\core_dec[0]_i_1_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\core_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\core_dec_reg_n_0_[0] ),
|
||||
.O(\core_dec[2]_i_1_n_0 ));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[0]_i_1_n_0 ),
|
||||
.Q(\core_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_dec0__0),
|
||||
.Q(\core_dec_reg_n_0_[1] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[2]_i_1_n_0 ),
|
||||
.Q(p_0_in),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
from_sys_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(seq_cnt_en),
|
||||
.O(from_sys_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b0))
|
||||
from_sys_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(from_sys_i_1_n_0),
|
||||
.Q(seq_cnt_en),
|
||||
.S(lpf_int));
|
||||
LUT4 #(
|
||||
.INIT(16'h0018))
|
||||
pr_dec0
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[0]),
|
||||
.I2(seq_cnt[2]),
|
||||
.I3(seq_cnt[1]),
|
||||
.O(pr_dec0__0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h0480))
|
||||
\pr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[3]),
|
||||
.I2(seq_cnt[5]),
|
||||
.I3(seq_cnt[4]),
|
||||
.O(p_3_out[0]));
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\pr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\pr_dec_reg_n_0_[0] ),
|
||||
.O(p_3_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[0]),
|
||||
.Q(\pr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[2]),
|
||||
.Q(\pr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
pr_i_1
|
||||
(.I0(Pr_out),
|
||||
.I1(\pr_dec_reg_n_0_[2] ),
|
||||
.O(pr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
pr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_i_1_n_0),
|
||||
.Q(Pr_out),
|
||||
.S(lpf_int));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
seq_clr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(1'b1),
|
||||
.Q(seq_clr),
|
||||
.R(lpf_int));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "upcnt_n" *)
|
||||
module system_bd_rst_ps_system_50M_0_upcnt_n
|
||||
(Q,
|
||||
seq_clr,
|
||||
seq_cnt_en,
|
||||
slowest_sync_clk);
|
||||
output [5:0]Q;
|
||||
input seq_clr;
|
||||
input seq_cnt_en;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire [5:0]Q;
|
||||
wire clear;
|
||||
wire [5:0]q_int0;
|
||||
wire seq_clr;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[0]_i_1
|
||||
(.I0(Q[0]),
|
||||
.O(q_int0[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\q_int[1]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.O(q_int0[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h78))
|
||||
\q_int[2]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[2]),
|
||||
.O(q_int0[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h7F80))
|
||||
\q_int[3]_i_1
|
||||
(.I0(Q[1]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[2]),
|
||||
.I3(Q[3]),
|
||||
.O(q_int0[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h7FFF8000))
|
||||
\q_int[4]_i_1
|
||||
(.I0(Q[2]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[1]),
|
||||
.I3(Q[3]),
|
||||
.I4(Q[4]),
|
||||
.O(q_int0[4]));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[5]_i_1
|
||||
(.I0(seq_clr),
|
||||
.O(clear));
|
||||
LUT6 #(
|
||||
.INIT(64'h7FFFFFFF80000000))
|
||||
\q_int[5]_i_2
|
||||
(.I0(Q[3]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[0]),
|
||||
.I3(Q[2]),
|
||||
.I4(Q[4]),
|
||||
.I5(Q[5]),
|
||||
.O(q_int0[5]));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[0]),
|
||||
.Q(Q[0]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[1]),
|
||||
.Q(Q[1]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[2]),
|
||||
.Q(Q[2]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[3]),
|
||||
.Q(Q[3]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[4]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[4]),
|
||||
.Q(Q[4]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[5]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[5]),
|
||||
.Q(Q[5]),
|
||||
.R(clear));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+1115
File diff suppressed because it is too large
Load Diff
+31
@@ -0,0 +1,31 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:05:22 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_rst_ps_system_50M_0/system_bd_rst_ps_system_50M_0_stub.v
|
||||
// Design : system_bd_rst_ps_system_50M_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "proc_sys_reset,Vivado 2019.1.3" *)
|
||||
module system_bd_rst_ps_system_50M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
|
||||
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
|
||||
interconnect_aresetn, peripheral_aresetn)
|
||||
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
|
||||
input slowest_sync_clk;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
endmodule
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:05:22 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_rst_ps_system_50M_0/system_bd_rst_ps_system_50M_0_stub.vhdl
|
||||
-- Design : system_bd_rst_ps_system_50M_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_rst_ps_system_50M_0 is
|
||||
Port (
|
||||
slowest_sync_clk : in STD_LOGIC;
|
||||
ext_reset_in : in STD_LOGIC;
|
||||
aux_reset_in : in STD_LOGIC;
|
||||
mb_debug_sys_rst : in STD_LOGIC;
|
||||
dcm_locked : in STD_LOGIC;
|
||||
mb_reset : out STD_LOGIC;
|
||||
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end system_bd_rst_ps_system_50M_0;
|
||||
|
||||
architecture stub of system_bd_rst_ps_system_50M_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+156
@@ -0,0 +1,156 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: analog.com:user:spi_engine_execution:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_spi_engine_execution_0 (
|
||||
clk,
|
||||
resetn,
|
||||
active,
|
||||
cmd_ready,
|
||||
cmd_valid,
|
||||
cmd,
|
||||
sdo_data_valid,
|
||||
sdo_data_ready,
|
||||
sdo_data,
|
||||
sdi_data_ready,
|
||||
sdi_data_valid,
|
||||
sdi_data,
|
||||
sync_ready,
|
||||
sync_valid,
|
||||
sync,
|
||||
sclk,
|
||||
sdo,
|
||||
sdo_t,
|
||||
sdi,
|
||||
cs,
|
||||
three_wire
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_clock, ASSOCIATED_BUSIF ctrl, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_clock, ASSOCIATED_BUSIF spi, ASSOCIATED_RESET resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ctrl_signal_clock CLK, xilinx.com:signal:clock:1.0 spi_signal_clock CLK" *)
|
||||
input wire clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ctrl_signal_reset RST, xilinx.com:signal:reset:1.0 spi_signal_reset RST" *)
|
||||
input wire resetn;
|
||||
output wire active;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_READY" *)
|
||||
output wire cmd_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_VALID" *)
|
||||
input wire cmd_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_DATA" *)
|
||||
input wire [15 : 0] cmd;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_VALID" *)
|
||||
input wire sdo_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_READY" *)
|
||||
output wire sdo_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_DATA" *)
|
||||
input wire [7 : 0] sdo_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_READY" *)
|
||||
input wire sdi_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_VALID" *)
|
||||
output wire sdi_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_DATA" *)
|
||||
output wire [7 : 0] sdi_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_READY" *)
|
||||
input wire sync_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_VALID" *)
|
||||
output wire sync_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_DATA" *)
|
||||
output wire [7 : 0] sync;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SCLK" *)
|
||||
output wire sclk;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO" *)
|
||||
output wire sdo;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO_T" *)
|
||||
output wire sdo_t;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDI" *)
|
||||
input wire [0 : 0] sdi;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi CS" *)
|
||||
output wire [2 : 0] cs;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi THREE_WIRE" *)
|
||||
output wire three_wire;
|
||||
|
||||
spi_engine_execution #(
|
||||
.NUM_OF_CS(3),
|
||||
.DEFAULT_SPI_CFG(0),
|
||||
.DEFAULT_CLK_DIV(0),
|
||||
.DATA_WIDTH(8),
|
||||
.NUM_OF_SDI(1),
|
||||
.SDO_DEFAULT(1'B0),
|
||||
.SDI_DELAY(1'B0)
|
||||
) inst (
|
||||
.clk(clk),
|
||||
.resetn(resetn),
|
||||
.active(active),
|
||||
.cmd_ready(cmd_ready),
|
||||
.cmd_valid(cmd_valid),
|
||||
.cmd(cmd),
|
||||
.sdo_data_valid(sdo_data_valid),
|
||||
.sdo_data_ready(sdo_data_ready),
|
||||
.sdo_data(sdo_data),
|
||||
.sdi_data_ready(sdi_data_ready),
|
||||
.sdi_data_valid(sdi_data_valid),
|
||||
.sdi_data(sdi_data),
|
||||
.sync_ready(sync_ready),
|
||||
.sync_valid(sync_valid),
|
||||
.sync(sync),
|
||||
.sclk(sclk),
|
||||
.sdo(sdo),
|
||||
.sdo_t(sdo_t),
|
||||
.sdi(sdi),
|
||||
.cs(cs),
|
||||
.three_wire(three_wire)
|
||||
);
|
||||
endmodule
|
||||
+156
@@ -0,0 +1,156 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: analog.com:user:spi_engine_execution:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
(* X_CORE_INFO = "spi_engine_execution,Vivado 2019.1.3" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_spi_engine_execution_0,spi_engine_execution,{}" *)
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_spi_engine_execution_0 (
|
||||
clk,
|
||||
resetn,
|
||||
active,
|
||||
cmd_ready,
|
||||
cmd_valid,
|
||||
cmd,
|
||||
sdo_data_valid,
|
||||
sdo_data_ready,
|
||||
sdo_data,
|
||||
sdi_data_ready,
|
||||
sdi_data_valid,
|
||||
sdi_data,
|
||||
sync_ready,
|
||||
sync_valid,
|
||||
sync,
|
||||
sclk,
|
||||
sdo,
|
||||
sdo_t,
|
||||
sdi,
|
||||
cs,
|
||||
three_wire
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_clock, ASSOCIATED_BUSIF ctrl, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_clock, ASSOCIATED_BUSIF spi, ASSOCIATED_RESET resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ctrl_signal_clock CLK, xilinx.com:signal:clock:1.0 spi_signal_clock CLK" *)
|
||||
input wire clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ctrl_signal_reset RST, xilinx.com:signal:reset:1.0 spi_signal_reset RST" *)
|
||||
input wire resetn;
|
||||
output wire active;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_READY" *)
|
||||
output wire cmd_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_VALID" *)
|
||||
input wire cmd_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_DATA" *)
|
||||
input wire [15 : 0] cmd;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_VALID" *)
|
||||
input wire sdo_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_READY" *)
|
||||
output wire sdo_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_DATA" *)
|
||||
input wire [7 : 0] sdo_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_READY" *)
|
||||
input wire sdi_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_VALID" *)
|
||||
output wire sdi_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_DATA" *)
|
||||
output wire [7 : 0] sdi_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_READY" *)
|
||||
input wire sync_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_VALID" *)
|
||||
output wire sync_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_DATA" *)
|
||||
output wire [7 : 0] sync;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SCLK" *)
|
||||
output wire sclk;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO" *)
|
||||
output wire sdo;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO_T" *)
|
||||
output wire sdo_t;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDI" *)
|
||||
input wire [0 : 0] sdi;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi CS" *)
|
||||
output wire [2 : 0] cs;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi THREE_WIRE" *)
|
||||
output wire three_wire;
|
||||
|
||||
spi_engine_execution #(
|
||||
.NUM_OF_CS(3),
|
||||
.DEFAULT_SPI_CFG(0),
|
||||
.DEFAULT_CLK_DIV(0),
|
||||
.DATA_WIDTH(8),
|
||||
.NUM_OF_SDI(1),
|
||||
.SDO_DEFAULT(1'B0),
|
||||
.SDI_DELAY(1'B0)
|
||||
) inst (
|
||||
.clk(clk),
|
||||
.resetn(resetn),
|
||||
.active(active),
|
||||
.cmd_ready(cmd_ready),
|
||||
.cmd_valid(cmd_valid),
|
||||
.cmd(cmd),
|
||||
.sdo_data_valid(sdo_data_valid),
|
||||
.sdo_data_ready(sdo_data_ready),
|
||||
.sdo_data(sdo_data),
|
||||
.sdi_data_ready(sdi_data_ready),
|
||||
.sdi_data_valid(sdi_data_valid),
|
||||
.sdi_data(sdi_data),
|
||||
.sync_ready(sync_ready),
|
||||
.sync_valid(sync_valid),
|
||||
.sync(sync),
|
||||
.sclk(sclk),
|
||||
.sdo(sdo),
|
||||
.sdo_t(sdo_t),
|
||||
.sdi(sdi),
|
||||
.cs(cs),
|
||||
.three_wire(three_wire)
|
||||
);
|
||||
endmodule
|
||||
BIN
Binary file not shown.
+72
@@ -0,0 +1,72 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_spi_engine_execution_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="analog.com" spirit:library="user" spirit:name="spi_engine_execution" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTRL_SIGNAL_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DEFAULT_CLK_DIV">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DEFAULT_SPI_CFG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_OF_CS">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SDI_DELAY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SDO_DEFAULT">"0"</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_spi_engine_execution_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEFAULT_CLK_DIV">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEFAULT_SPI_CFG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OF_CS">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OF_SDI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SDI_DELAY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SDO_DEFAULT">"0"</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OF_CS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OF_SDI" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+963
@@ -0,0 +1,963 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>system_bd_spi_engine_execution_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl_signal_clock</spirit:name>
|
||||
<spirit:displayName>ctrl_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.ASSOCIATED_BUSIF">ctrl</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.ASSOCIATED_RESET">resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.PHASE">0.000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl_signal_reset</spirit:name>
|
||||
<spirit:displayName>ctrl_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SCLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_T</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_t</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>THREE_WIRE</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>three_wire</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CS</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cs</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_signal_clock</spirit:name>
|
||||
<spirit:displayName>spi_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">spi</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.ASSOCIATED_RESET">resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.FREQ_HZ">50000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.PHASE">0.000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_signal_reset</spirit:name>
|
||||
<spirit:displayName>spi_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
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|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_CS</spirit:name>
|
||||
<spirit:displayName>Num Of Cs</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_CS">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DEFAULT_SPI_CFG</spirit:name>
|
||||
<spirit:displayName>Default Spi Cfg</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEFAULT_SPI_CFG">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DEFAULT_CLK_DIV</spirit:name>
|
||||
<spirit:displayName>Default Clk Div</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEFAULT_CLK_DIV">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Num Of Sdi</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDO_DEFAULT</spirit:name>
|
||||
<spirit:displayName>Sdo Default</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDO_DEFAULT" spirit:bitStringLength="1">"0"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDI_DELAY</spirit:name>
|
||||
<spirit:displayName>Sdi Delay</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDI_DELAY">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_5ec0cd51</spirit:name>
|
||||
<spirit:enumeration>"0"</spirit:enumeration>
|
||||
<spirit:enumeration>"1"</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_6e3ded9c</spirit:name>
|
||||
<spirit:enumeration>0</spirit:enumeration>
|
||||
<spirit:enumeration>1</spirit:enumeration>
|
||||
<spirit:enumeration>2</spirit:enumeration>
|
||||
<spirit:enumeration>3</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/802c/spi_engine_execution.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/system_bd_spi_engine_execution_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/802c/spi_engine_execution.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_bd_spi_engine_execution_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_spi_engine_execution_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_spi_engine_execution_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_spi_engine_execution_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_spi_engine_execution_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_spi_engine_execution_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>spi_engine_execution_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_CS</spirit:name>
|
||||
<spirit:displayName>Number of CSN lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_CS" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DEFAULT_SPI_CFG</spirit:name>
|
||||
<spirit:displayName>Default SPI mode</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEFAULT_SPI_CFG" spirit:choiceRef="choice_list_6e3ded9c">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DEFAULT_CLK_DIV</spirit:name>
|
||||
<spirit:displayName>Default SCLK divider</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEFAULT_CLK_DIV" spirit:minimum="0" spirit:maximum="255" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Parallel data width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:minimum="8" spirit:maximum="256" spirit:rangeType="long">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Number of MISO</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_SDI" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDO_DEFAULT</spirit:name>
|
||||
<spirit:displayName>MOSI default level</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SDO_DEFAULT" spirit:choiceRef="choice_list_5ec0cd51" spirit:bitStringLength="1">"0"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDI_DELAY</spirit:name>
|
||||
<spirit:displayName>Delay MISO latching</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SDI_DELAY">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">system_bd_spi_engine_execution_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>spi_engine_execution_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OF_CS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OF_SDI" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.1.3</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5778d7eb"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="5681b5a9"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8b510ac0"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="6b1dd38c"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+2517
File diff suppressed because it is too large
Load Diff
+3236
File diff suppressed because it is too large
Load Diff
+42
@@ -0,0 +1,42 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:05:22 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.v
|
||||
// Design : system_bd_spi_engine_execution_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "spi_engine_execution,Vivado 2019.1.3" *)
|
||||
module system_bd_spi_engine_execution_0(clk, resetn, active, cmd_ready, cmd_valid, cmd,
|
||||
sdo_data_valid, sdo_data_ready, sdo_data, sdi_data_ready, sdi_data_valid, sdi_data,
|
||||
sync_ready, sync_valid, sync, sclk, sdo, sdo_t, sdi, cs, three_wire)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,resetn,active,cmd_ready,cmd_valid,cmd[15:0],sdo_data_valid,sdo_data_ready,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync[7:0],sclk,sdo,sdo_t,sdi[0:0],cs[2:0],three_wire" */;
|
||||
input clk;
|
||||
input resetn;
|
||||
output active;
|
||||
output cmd_ready;
|
||||
input cmd_valid;
|
||||
input [15:0]cmd;
|
||||
input sdo_data_valid;
|
||||
output sdo_data_ready;
|
||||
input [7:0]sdo_data;
|
||||
input sdi_data_ready;
|
||||
output sdi_data_valid;
|
||||
output [7:0]sdi_data;
|
||||
input sync_ready;
|
||||
output sync_valid;
|
||||
output [7:0]sync;
|
||||
output sclk;
|
||||
output sdo;
|
||||
output sdo_t;
|
||||
input [0:0]sdi;
|
||||
output [2:0]cs;
|
||||
output three_wire;
|
||||
endmodule
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:05:22 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.vhdl
|
||||
-- Design : system_bd_spi_engine_execution_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_spi_engine_execution_0 is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
active : out STD_LOGIC;
|
||||
cmd_ready : out STD_LOGIC;
|
||||
cmd_valid : in STD_LOGIC;
|
||||
cmd : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
sdo_data_valid : in STD_LOGIC;
|
||||
sdo_data_ready : out STD_LOGIC;
|
||||
sdo_data : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sdi_data_ready : in STD_LOGIC;
|
||||
sdi_data_valid : out STD_LOGIC;
|
||||
sdi_data : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sync_ready : in STD_LOGIC;
|
||||
sync_valid : out STD_LOGIC;
|
||||
sync : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sclk : out STD_LOGIC;
|
||||
sdo : out STD_LOGIC;
|
||||
sdo_t : out STD_LOGIC;
|
||||
sdi : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
cs : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
three_wire : out STD_LOGIC
|
||||
);
|
||||
|
||||
end system_bd_spi_engine_execution_0;
|
||||
|
||||
architecture stub of system_bd_spi_engine_execution_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,resetn,active,cmd_ready,cmd_valid,cmd[15:0],sdo_data_valid,sdo_data_ready,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync[7:0],sclk,sdo,sdo_t,sdi[0:0],cs[2:0],three_wire";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "spi_engine_execution,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+134
@@ -0,0 +1,134 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 3
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_xlconcat_irpt_0 (
|
||||
In0,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_3_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.dout_width(1),
|
||||
.NUM_PORTS(1)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(1'B0),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+136
@@ -0,0 +1,136 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 3
|
||||
|
||||
(* X_CORE_INFO = "xlconcat_v2_1_3_xlconcat,Vivado 2019.1.3" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_xlconcat_irpt_0,xlconcat_v2_1_3_xlconcat,{}" *)
|
||||
(* CORE_GENERATION_INFO = "system_bd_xlconcat_irpt_0,xlconcat_v2_1_3_xlconcat,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=\
|
||||
1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=1,NUM_PORTS=1}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_xlconcat_irpt_0 (
|
||||
In0,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_3_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.dout_width(1),
|
||||
.NUM_PORTS(1)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(1'B0),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+113
@@ -0,0 +1,113 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_xlconcat_irpt_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconcat" spirit:version="2.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN0_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN10_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN11_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN12_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN13_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN14_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN15_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN16_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN17_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN18_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN19_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN1_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN20_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN21_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN22_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN23_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN24_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN25_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN26_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN27_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN28_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN29_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN2_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN30_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN31_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN3_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN4_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN5_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN6_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN7_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN8_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN9_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_PORTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dout_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_xlconcat_irpt_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN0_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN10_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN11_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN12_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN13_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN14_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN15_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN16_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN17_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN18_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN19_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN1_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN20_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN21_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN22_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN23_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN24_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN25_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN26_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN27_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN28_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN29_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN2_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN30_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN31_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN3_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN4_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN5_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN6_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN7_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN8_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN9_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_PORTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dout_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN0_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_PORTS" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+1386
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,625 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_spi_engine #(
|
||||
|
||||
parameter CMD_FIFO_ADDRESS_WIDTH = 4,
|
||||
parameter SYNC_FIFO_ADDRESS_WIDTH = 4,
|
||||
parameter SDO_FIFO_ADDRESS_WIDTH = 5,
|
||||
parameter SDI_FIFO_ADDRESS_WIDTH = 5,
|
||||
parameter MM_IF_TYPE = 0,
|
||||
parameter ASYNC_SPI_CLK = 0,
|
||||
parameter NUM_OFFLOAD = 0,
|
||||
parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter ID = 0,
|
||||
parameter [15:0] DATA_WIDTH = 8,
|
||||
parameter [ 7:0] NUM_OF_SDI = 1 ) (
|
||||
|
||||
// Slave AXI interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [15:0] s_axi_awaddr,
|
||||
output s_axi_awready,
|
||||
input [2:0] s_axi_awprot,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [15:0] s_axi_araddr,
|
||||
output s_axi_arready,
|
||||
input [2:0] s_axi_arprot,
|
||||
output s_axi_rvalid,
|
||||
input s_axi_rready,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
|
||||
// up interface
|
||||
|
||||
input up_clk,
|
||||
input up_rstn,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack,
|
||||
|
||||
output reg irq,
|
||||
|
||||
// SPI signals
|
||||
|
||||
input spi_clk,
|
||||
|
||||
output spi_resetn,
|
||||
|
||||
input cmd_ready,
|
||||
output cmd_valid,
|
||||
output [15:0] cmd_data,
|
||||
|
||||
input sdo_data_ready,
|
||||
output sdo_data_valid,
|
||||
output [(DATA_WIDTH-1):0] sdo_data,
|
||||
|
||||
output sdi_data_ready,
|
||||
input sdi_data_valid,
|
||||
input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
|
||||
|
||||
output sync_ready,
|
||||
input sync_valid,
|
||||
input [7:0] sync_data,
|
||||
|
||||
// Offload ctrl signals
|
||||
|
||||
output offload0_cmd_wr_en,
|
||||
output [15:0] offload0_cmd_wr_data,
|
||||
|
||||
output offload0_sdo_wr_en,
|
||||
output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,
|
||||
|
||||
output offload0_mem_reset,
|
||||
output offload0_enable,
|
||||
input offload0_enabled,
|
||||
|
||||
output offload_sync_ready,
|
||||
input offload_sync_valid,
|
||||
input [7:0] offload_sync_data);
|
||||
|
||||
localparam PCORE_VERSION = 'h010071;
|
||||
localparam S_AXI = 0;
|
||||
localparam UP_FIFO = 1;
|
||||
|
||||
wire clk;
|
||||
wire rstn;
|
||||
|
||||
wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room;
|
||||
wire cmd_fifo_almost_empty;
|
||||
|
||||
wire [15:0] cmd_fifo_in_data;
|
||||
wire cmd_fifo_in_ready;
|
||||
wire cmd_fifo_in_valid;
|
||||
|
||||
wire [SDO_FIFO_ADDRESS_WIDTH:0] sdo_fifo_room;
|
||||
wire sdo_fifo_almost_empty;
|
||||
|
||||
wire [(DATA_WIDTH-1):0] sdo_fifo_in_data;
|
||||
wire sdo_fifo_in_ready;
|
||||
wire sdo_fifo_in_valid;
|
||||
|
||||
wire sdi_fifo_out_data_msb_s;
|
||||
wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level;
|
||||
wire sdi_fifo_almost_full;
|
||||
|
||||
wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data;
|
||||
wire sdi_fifo_out_ready;
|
||||
wire sdi_fifo_out_valid;
|
||||
|
||||
wire [7:0] sync_fifo_data;
|
||||
wire sync_fifo_valid;
|
||||
|
||||
wire [7:0] offload_sync_fifo_data;
|
||||
wire offload_sync_fifo_valid;
|
||||
|
||||
reg up_sw_reset = 1'b1;
|
||||
wire up_sw_resetn = ~up_sw_reset;
|
||||
|
||||
reg [31:0] up_rdata_ff = 'd0;
|
||||
reg up_wack_ff = 1'b0;
|
||||
reg up_rack_ff = 1'b0;
|
||||
wire up_wreq_s;
|
||||
wire up_rreq_s;
|
||||
wire [31:0] up_wdata_s;
|
||||
wire [13:0] up_waddr_s;
|
||||
wire [13:0] up_raddr_s;
|
||||
|
||||
// Scratch register
|
||||
reg [31:0] up_scratch = 'h00;
|
||||
|
||||
reg [7:0] sync_id = 'h00;
|
||||
reg sync_id_pending = 1'b0;
|
||||
|
||||
reg [7:0] offload_sync_id = 'h00;
|
||||
reg offload_sync_id_pending = 1'b0;
|
||||
|
||||
generate if (MM_IF_TYPE == S_AXI) begin
|
||||
|
||||
// assign clock and reset
|
||||
|
||||
assign clk = s_axi_aclk;
|
||||
assign rstn = s_axi_aresetn;
|
||||
|
||||
// interface wrapper
|
||||
|
||||
up_axi #(
|
||||
.AXI_ADDRESS_WIDTH (16)
|
||||
) i_up_axi (
|
||||
.up_rstn(rstn),
|
||||
.up_clk(clk),
|
||||
.up_axi_awvalid(s_axi_awvalid),
|
||||
.up_axi_awaddr(s_axi_awaddr),
|
||||
.up_axi_awready(s_axi_awready),
|
||||
.up_axi_wvalid(s_axi_wvalid),
|
||||
.up_axi_wdata(s_axi_wdata),
|
||||
.up_axi_wstrb(s_axi_wstrb),
|
||||
.up_axi_wready(s_axi_wready),
|
||||
.up_axi_bvalid(s_axi_bvalid),
|
||||
.up_axi_bresp(s_axi_bresp),
|
||||
.up_axi_bready(s_axi_bready),
|
||||
.up_axi_arvalid(s_axi_arvalid),
|
||||
.up_axi_araddr(s_axi_araddr),
|
||||
.up_axi_arready(s_axi_arready),
|
||||
.up_axi_rvalid(s_axi_rvalid),
|
||||
.up_axi_rresp(s_axi_rresp),
|
||||
.up_axi_rdata(s_axi_rdata),
|
||||
.up_axi_rready(s_axi_rready),
|
||||
.up_wreq(up_wreq_s),
|
||||
.up_waddr(up_waddr_s),
|
||||
.up_wdata(up_wdata_s),
|
||||
.up_wack(up_wack_ff),
|
||||
.up_rreq(up_rreq_s),
|
||||
.up_raddr(up_raddr_s),
|
||||
.up_rdata(up_rdata_ff),
|
||||
.up_rack(up_rack_ff)
|
||||
);
|
||||
|
||||
assign up_rdata = 32'b0;
|
||||
assign up_rack = 1'b0;
|
||||
assign up_wack = 1'b0;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (MM_IF_TYPE == UP_FIFO) begin
|
||||
|
||||
// assign clock and reset
|
||||
|
||||
assign clk = up_clk;
|
||||
assign rstn = up_rstn;
|
||||
|
||||
assign up_wreq_s = up_wreq;
|
||||
assign up_waddr_s = up_waddr;
|
||||
assign up_wdata_s = up_wdata;
|
||||
assign up_wack = up_wack_ff;
|
||||
assign up_rreq_s = up_rreq;
|
||||
assign up_raddr_s = up_raddr;
|
||||
assign up_rdata = up_rdata_ff;
|
||||
assign up_rack = up_rack_ff;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// IRQ handling
|
||||
reg [3:0] up_irq_mask = 'h0;
|
||||
wire [3:0] up_irq_source;
|
||||
wire [3:0] up_irq_pending;
|
||||
|
||||
assign up_irq_source = {
|
||||
offload_sync_id_pending,
|
||||
sync_id_pending,
|
||||
sdi_fifo_almost_full,
|
||||
sdo_fifo_almost_empty,
|
||||
cmd_fifo_almost_empty
|
||||
};
|
||||
|
||||
assign up_irq_pending = up_irq_mask & up_irq_source;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rstn == 1'b0)
|
||||
irq <= 1'b0;
|
||||
else
|
||||
irq <= |up_irq_pending;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rstn == 1'b0) begin
|
||||
up_wack_ff <= 1'b0;
|
||||
up_scratch <= 'h00;
|
||||
up_sw_reset <= 1'b1;
|
||||
end else begin
|
||||
up_wack_ff <= up_wreq_s;
|
||||
if (up_wreq_s) begin
|
||||
case (up_waddr_s)
|
||||
8'h02: up_scratch <= up_wdata_s;
|
||||
8'h10: up_sw_reset <= up_wdata_s;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg offload0_enable_reg;
|
||||
reg offload0_mem_reset_reg;
|
||||
wire offload0_enabled_s;
|
||||
|
||||
// the software reset should reset all the registers
|
||||
always @(posedge clk) begin
|
||||
if (up_sw_resetn == 1'b0) begin
|
||||
up_irq_mask <= 'h00;
|
||||
offload0_enable_reg <= 1'b0;
|
||||
offload0_mem_reset_reg <= 1'b0;
|
||||
end else begin
|
||||
if (up_wreq_s) begin
|
||||
case (up_waddr_s)
|
||||
8'h20: up_irq_mask <= up_wdata_s;
|
||||
8'h40: offload0_enable_reg <= up_wdata_s[0];
|
||||
8'h42: offload0_mem_reset_reg <= up_wdata_s[0];
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rstn == 1'b0) begin
|
||||
up_rack_ff <= 'd0;
|
||||
end else begin
|
||||
up_rack_ff <= up_rreq_s;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (NUM_OF_SDI > 1) begin
|
||||
// Only the first two SDI data can be recovered through AXI regmap
|
||||
assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH];
|
||||
end else begin
|
||||
assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk) begin
|
||||
case (up_raddr_s)
|
||||
8'h00: up_rdata_ff <= PCORE_VERSION;
|
||||
8'h01: up_rdata_ff <= ID;
|
||||
8'h02: up_rdata_ff <= up_scratch;
|
||||
8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
|
||||
8'h10: up_rdata_ff <= up_sw_reset;
|
||||
8'h20: up_rdata_ff <= up_irq_mask;
|
||||
8'h21: up_rdata_ff <= up_irq_pending;
|
||||
8'h22: up_rdata_ff <= up_irq_source;
|
||||
8'h30: up_rdata_ff <= sync_id;
|
||||
8'h31: up_rdata_ff <= offload_sync_id;
|
||||
8'h34: up_rdata_ff <= cmd_fifo_room;
|
||||
8'h35: up_rdata_ff <= sdo_fifo_room;
|
||||
8'h36: up_rdata_ff <= sdi_fifo_level;
|
||||
8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0];
|
||||
8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */
|
||||
8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
|
||||
8'h40: up_rdata_ff <= {offload0_enable_reg};
|
||||
8'h41: up_rdata_ff <= {offload0_enabled_s};
|
||||
default: up_rdata_ff <= 'h00;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (up_sw_resetn == 1'b0) begin
|
||||
sync_id <= 'h00;
|
||||
sync_id_pending <= 1'b0;
|
||||
end else begin
|
||||
if (sync_fifo_valid == 1'b1) begin
|
||||
sync_id <= sync_fifo_data;
|
||||
sync_id_pending <= 1'b1;
|
||||
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
|
||||
sync_id_pending <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (up_sw_resetn == 1'b0) begin
|
||||
offload_sync_id <= 'h00;
|
||||
offload_sync_id_pending <= 1'b0;
|
||||
end else begin
|
||||
if (offload_sync_fifo_valid == 1'b1) begin
|
||||
offload_sync_id <= offload_sync_fifo_data;
|
||||
offload_sync_id_pending <= 1'b1;
|
||||
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
|
||||
offload_sync_id_pending <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
wire spi_reset;
|
||||
ad_rst i_spi_resetn (
|
||||
.rst_async(up_sw_reset),
|
||||
.clk(spi_clk),
|
||||
.rst(spi_reset),
|
||||
.rstn()
|
||||
);
|
||||
assign spi_resetn = ~spi_reset;
|
||||
end else begin
|
||||
assign spi_resetn = ~up_sw_reset;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/* Evaluates to true if FIFO level/room is 3/4 or above */
|
||||
`define axi_spi_engine_check_watermark(x, n) \
|
||||
(x[n] == 1'b1 || x[n-1:n-2] == 2'b11)
|
||||
|
||||
assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38;
|
||||
assign cmd_fifo_in_data = up_wdata_s[15:0];
|
||||
assign cmd_fifo_almost_empty =
|
||||
`axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH);
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(16),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_cmd_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(cmd_fifo_in_ready),
|
||||
.s_axis_valid(cmd_fifo_in_valid),
|
||||
.s_axis_data(cmd_fifo_in_data),
|
||||
.s_axis_room(cmd_fifo_room),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(cmd_ready),
|
||||
.m_axis_valid(cmd_valid),
|
||||
.m_axis_data(cmd_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
|
||||
assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0];
|
||||
assign sdo_fifo_almost_empty =
|
||||
`axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH);
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_sdo_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(sdo_fifo_in_ready),
|
||||
.s_axis_valid(sdo_fifo_in_valid),
|
||||
.s_axis_data(sdo_fifo_in_data),
|
||||
.s_axis_room(sdo_fifo_room),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(sdo_data_ready),
|
||||
.m_axis_valid(sdo_data_valid),
|
||||
.m_axis_data(sdo_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
|
||||
assign sdi_fifo_almost_full =
|
||||
`axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_sdi_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(sdi_data_ready),
|
||||
.s_axis_valid(sdi_data_valid),
|
||||
.s_axis_data(sdi_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(sdi_fifo_out_ready),
|
||||
.m_axis_valid(sdi_fifo_out_valid),
|
||||
.m_axis_data(sdi_fifo_out_data),
|
||||
.m_axis_level(sdi_fifo_level)
|
||||
);
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
// synchronization FIFO for the SYNC interface
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(8),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_sync_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(sync_ready),
|
||||
.s_axis_valid(sync_valid),
|
||||
.s_axis_data(sync_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(sync_fifo_valid),
|
||||
.m_axis_data(sync_fifo_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
// synchronization FIFO for the offload command interface
|
||||
wire up_offload0_cmd_wr_en_s;
|
||||
wire [15:0] up_offload0_cmd_wr_data_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(16),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_offload_cmd_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(),
|
||||
.s_axis_valid(up_offload0_cmd_wr_en_s),
|
||||
.s_axis_data(up_offload0_cmd_wr_data_s),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload0_cmd_wr_en),
|
||||
.m_axis_data(offload0_cmd_wr_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
|
||||
assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0];
|
||||
|
||||
// synchronization FIFO for the offload SDO interface
|
||||
wire up_offload0_sdo_wr_en_s;
|
||||
wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_offload_sdo_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(),
|
||||
.s_axis_valid(up_offload0_sdo_wr_en_s),
|
||||
.s_axis_data(up_offload0_sdo_wr_data_s),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload0_sdo_wr_en),
|
||||
.m_axis_data(offload0_sdo_wr_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
|
||||
assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0];
|
||||
|
||||
// synchronization FIFO for the Offload SYNC interface
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(8),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_offload_sync_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(offload_sync_ready),
|
||||
.s_axis_valid(offload_sync_valid),
|
||||
.s_axis_data(offload_sync_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload_sync_fifo_valid),
|
||||
.m_axis_data(offload_sync_fifo_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
end else begin /* ASYNC_SPI_CLK == 0 */
|
||||
|
||||
assign sync_fifo_valid = sync_valid;
|
||||
assign sync_fifo_data = sync_data;
|
||||
assign sync_ready = 1'b1;
|
||||
|
||||
assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
|
||||
assign offload0_cmd_wr_data = up_wdata_s[15:0];
|
||||
|
||||
assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
|
||||
assign offload0_sdo_wr_data = up_wdata_s[DATA_WIDTH-1:0];
|
||||
|
||||
assign offload_sync_fifo_valid = offload_sync_valid;
|
||||
assign offload_sync_fifo_data = offload_sync_data;
|
||||
assign offload_sync_ready = 1'b1;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_enable_sync (
|
||||
.in_bits (offload0_enable_reg),
|
||||
.out_resetn (spi_resetn),
|
||||
.out_clk (spi_clk),
|
||||
.out_bits (offload0_enable));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_enabled_sync (
|
||||
.in_bits (offload0_enabled),
|
||||
.out_resetn (up_sw_resetn),
|
||||
.out_clk (clk),
|
||||
.out_bits (offload0_enabled_s));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_mem_reset_sync (
|
||||
.in_bits (offload0_mem_reset_reg),
|
||||
.out_resetn (spi_resetn),
|
||||
.out_clk (spi_clk),
|
||||
.out_bits (offload0_mem_reset));
|
||||
|
||||
endmodule
|
||||
+7759
File diff suppressed because it is too large
Load Diff
+18807
File diff suppressed because it is too large
Load Diff
+31945
File diff suppressed because it is too large
Load Diff
+10519
File diff suppressed because it is too large
Load Diff
+278
@@ -0,0 +1,278 @@
|
||||
//------------------------------------------------------------------------
|
||||
//--
|
||||
//-- Filename : xlconcat.v
|
||||
//--
|
||||
//-- Date : 06/05/12
|
||||
//-
|
||||
//- Description : Verilog description of a concat block. This
|
||||
//- block does not use a core.
|
||||
//-
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module xlconcat_v2_1_3_xlconcat (In0, In1, In2, In3, In4, In5, In6, In7, In8, In9, In10, In11, In12, In13, In14, In15, In16, In17, In18, In19, In20, In21, In22, In23, In24, In25, In26, In27, In28, In29, In30, In31, dout);
|
||||
parameter IN0_WIDTH = 1;
|
||||
input [IN0_WIDTH -1:0] In0;
|
||||
parameter IN1_WIDTH = 1;
|
||||
input [IN1_WIDTH -1:0] In1;
|
||||
parameter IN2_WIDTH = 1;
|
||||
input [IN2_WIDTH -1:0] In2;
|
||||
parameter IN3_WIDTH = 1;
|
||||
input [IN3_WIDTH -1:0] In3;
|
||||
parameter IN4_WIDTH = 1;
|
||||
input [IN4_WIDTH -1:0] In4;
|
||||
parameter IN5_WIDTH = 1;
|
||||
input [IN5_WIDTH -1:0] In5;
|
||||
parameter IN6_WIDTH = 1;
|
||||
input [IN6_WIDTH -1:0] In6;
|
||||
parameter IN7_WIDTH = 1;
|
||||
input [IN7_WIDTH -1:0] In7;
|
||||
parameter IN8_WIDTH = 1;
|
||||
input [IN8_WIDTH -1:0] In8;
|
||||
parameter IN9_WIDTH = 1;
|
||||
input [IN9_WIDTH -1:0] In9;
|
||||
parameter IN10_WIDTH = 1;
|
||||
input [IN10_WIDTH -1:0] In10;
|
||||
parameter IN11_WIDTH = 1;
|
||||
input [IN11_WIDTH -1:0] In11;
|
||||
parameter IN12_WIDTH = 1;
|
||||
input [IN12_WIDTH -1:0] In12;
|
||||
parameter IN13_WIDTH = 1;
|
||||
input [IN13_WIDTH -1:0] In13;
|
||||
parameter IN14_WIDTH = 1;
|
||||
input [IN14_WIDTH -1:0] In14;
|
||||
parameter IN15_WIDTH = 1;
|
||||
input [IN15_WIDTH -1:0] In15;
|
||||
parameter IN16_WIDTH = 1;
|
||||
input [IN16_WIDTH -1:0] In16;
|
||||
parameter IN17_WIDTH = 1;
|
||||
input [IN17_WIDTH -1:0] In17;
|
||||
parameter IN18_WIDTH = 1;
|
||||
input [IN18_WIDTH -1:0] In18;
|
||||
parameter IN19_WIDTH = 1;
|
||||
input [IN19_WIDTH -1:0] In19;
|
||||
parameter IN20_WIDTH = 1;
|
||||
input [IN20_WIDTH -1:0] In20;
|
||||
parameter IN21_WIDTH = 1;
|
||||
input [IN21_WIDTH -1:0] In21;
|
||||
parameter IN22_WIDTH = 1;
|
||||
input [IN22_WIDTH -1:0] In22;
|
||||
parameter IN23_WIDTH = 1;
|
||||
input [IN23_WIDTH -1:0] In23;
|
||||
parameter IN24_WIDTH = 1;
|
||||
input [IN24_WIDTH -1:0] In24;
|
||||
parameter IN25_WIDTH = 1;
|
||||
input [IN25_WIDTH -1:0] In25;
|
||||
parameter IN26_WIDTH = 1;
|
||||
input [IN26_WIDTH -1:0] In26;
|
||||
parameter IN27_WIDTH = 1;
|
||||
input [IN27_WIDTH -1:0] In27;
|
||||
parameter IN28_WIDTH = 1;
|
||||
input [IN28_WIDTH -1:0] In28;
|
||||
parameter IN29_WIDTH = 1;
|
||||
input [IN29_WIDTH -1:0] In29;
|
||||
parameter IN30_WIDTH = 1;
|
||||
input [IN30_WIDTH -1:0] In30;
|
||||
parameter IN31_WIDTH = 1;
|
||||
input [IN31_WIDTH -1:0] In31;
|
||||
parameter dout_width = 2;
|
||||
output [dout_width-1:0] dout;
|
||||
parameter NUM_PORTS =2;
|
||||
|
||||
|
||||
generate if (NUM_PORTS == 1)
|
||||
begin : C_NUM_1
|
||||
assign dout = In0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 2)
|
||||
begin : C_NUM_2
|
||||
assign dout = {In1,In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 3)
|
||||
begin:C_NUM_3
|
||||
assign dout = {In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 4)
|
||||
begin:C_NUM_4
|
||||
assign dout = {In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 5)
|
||||
begin:C_NUM_5
|
||||
assign dout = {In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 6)
|
||||
begin:C_NUM_6
|
||||
assign dout = {In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 7)
|
||||
begin:C_NUM_7
|
||||
assign dout = {In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 8)
|
||||
begin:C_NUM_8
|
||||
assign dout = {In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 9)
|
||||
begin:C_NUM_9
|
||||
assign dout = {In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 10)
|
||||
begin:C_NUM_10
|
||||
assign dout = {In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 11)
|
||||
begin:C_NUM_11
|
||||
assign dout = {In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 12)
|
||||
begin:C_NUM_12
|
||||
assign dout = {In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 13)
|
||||
begin:C_NUM_13
|
||||
assign dout = {In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 14)
|
||||
begin:C_NUM_14
|
||||
assign dout = {In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 15)
|
||||
begin:C_NUM_15
|
||||
assign dout = {In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 16)
|
||||
begin:C_NUM_16
|
||||
assign dout = {In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 17)
|
||||
begin:C_NUM_17
|
||||
assign dout = {In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 18)
|
||||
begin:C_NUM_18
|
||||
assign dout = {In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 19)
|
||||
begin:C_NUM_19
|
||||
assign dout = {In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 20)
|
||||
begin:C_NUM_20
|
||||
assign dout = {In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 21)
|
||||
begin:C_NUM_21
|
||||
assign dout = {In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 22)
|
||||
begin:C_NUM_22
|
||||
assign dout = {In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 23)
|
||||
begin:C_NUM_23
|
||||
assign dout = {In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 24)
|
||||
begin:C_NUM_24
|
||||
assign dout = {In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 25)
|
||||
begin:C_NUM_25
|
||||
assign dout = {In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 26)
|
||||
begin:C_NUM_26
|
||||
assign dout = {In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 27)
|
||||
begin:C_NUM_27
|
||||
assign dout = {In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 28)
|
||||
begin:C_NUM_28
|
||||
assign dout = {In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 29)
|
||||
begin:C_NUM_29
|
||||
assign dout = {In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 30)
|
||||
begin:C_NUM_30
|
||||
assign dout = {In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 31)
|
||||
begin:C_NUM_31
|
||||
assign dout = {In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 32)
|
||||
begin:C_NUM_32
|
||||
assign dout = {In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
+3659
File diff suppressed because it is too large
Load Diff
+1956
File diff suppressed because it is too large
Load Diff
+456
@@ -0,0 +1,456 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module spi_engine_execution #(
|
||||
|
||||
parameter NUM_OF_CS = 1,
|
||||
parameter DEFAULT_SPI_CFG = 0,
|
||||
parameter DEFAULT_CLK_DIV = 0,
|
||||
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
|
||||
parameter NUM_OF_SDI = 1,
|
||||
parameter [0:0] SDO_DEFAULT = 1'b0,
|
||||
parameter [1:0] SDI_DELAY = 2'b00) (
|
||||
|
||||
input clk,
|
||||
input resetn,
|
||||
|
||||
output reg active,
|
||||
|
||||
output cmd_ready,
|
||||
input cmd_valid,
|
||||
input [15:0] cmd,
|
||||
|
||||
input sdo_data_valid,
|
||||
output reg sdo_data_ready,
|
||||
input [(DATA_WIDTH-1):0] sdo_data,
|
||||
|
||||
|
||||
input sdi_data_ready,
|
||||
output reg sdi_data_valid,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data,
|
||||
|
||||
input sync_ready,
|
||||
output reg sync_valid,
|
||||
output [7:0] sync,
|
||||
|
||||
output reg sclk,
|
||||
output reg sdo,
|
||||
output reg sdo_t,
|
||||
input [NUM_OF_SDI-1:0] sdi,
|
||||
output reg [NUM_OF_CS-1:0] cs,
|
||||
output reg three_wire
|
||||
);
|
||||
|
||||
localparam CMD_TRANSFER = 2'b00;
|
||||
localparam CMD_CHIPSELECT = 2'b01;
|
||||
localparam CMD_WRITE = 2'b10;
|
||||
localparam CMD_MISC = 2'b11;
|
||||
|
||||
localparam MISC_SYNC = 1'b0;
|
||||
localparam MISC_SLEEP = 1'b1;
|
||||
|
||||
localparam REG_CLK_DIV = 2'b00;
|
||||
localparam REG_CONFIG = 2'b01;
|
||||
localparam REG_WORD_LENGTH = 2'b10;
|
||||
|
||||
localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
|
||||
DATA_WIDTH > 8 ? 4 : 3;
|
||||
|
||||
localparam BIT_COUNTER_CARRY = 2** (BIT_COUNTER_WIDTH + 1);
|
||||
localparam BIT_COUNTER_CLEAR = {{8{1'b1}}, {BIT_COUNTER_WIDTH{1'b0}}, 1'b1};
|
||||
|
||||
reg sclk_int = 1'b0;
|
||||
wire sdo_int_s;
|
||||
reg sdo_t_int = 1'b0;
|
||||
|
||||
reg idle;
|
||||
|
||||
reg [7:0] clk_div_counter = 'h00;
|
||||
reg [7:0] clk_div_counter_next = 'h00;
|
||||
reg clk_div_last;
|
||||
|
||||
reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;
|
||||
|
||||
wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [2:0] cs_sleep_counter2 = counter[(BIT_COUNTER_WIDTH+3):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];
|
||||
wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
|
||||
wire ntx_rx = counter[0];
|
||||
|
||||
reg trigger = 1'b0;
|
||||
reg trigger_next = 1'b0;
|
||||
reg wait_for_io = 1'b0;
|
||||
reg transfer_active = 1'b0;
|
||||
|
||||
wire last_bit;
|
||||
wire first_bit;
|
||||
reg last_transfer;
|
||||
reg [7:0] word_length = DATA_WIDTH;
|
||||
reg [7:0] left_aligned = 8'b0;
|
||||
wire end_of_word;
|
||||
|
||||
reg [7:0] sdi_counter = 8'b0;
|
||||
|
||||
assign first_bit = ((bit_counter == 'h0) || (bit_counter == word_length));
|
||||
assign last_bit = bit_counter == word_length - 1;
|
||||
assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
|
||||
|
||||
reg [15:0] cmd_d1;
|
||||
|
||||
reg cpha = DEFAULT_SPI_CFG[0];
|
||||
reg cpol = DEFAULT_SPI_CFG[1];
|
||||
reg [7:0] clk_div = DEFAULT_CLK_DIV;
|
||||
|
||||
reg sdo_enabled = 1'b0;
|
||||
reg sdi_enabled = 1'b0;
|
||||
|
||||
reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
|
||||
|
||||
reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
|
||||
|
||||
wire [1:0] inst = cmd[13:12];
|
||||
wire [1:0] inst_d1 = cmd_d1[13:12];
|
||||
|
||||
wire exec_cmd = cmd_ready && cmd_valid;
|
||||
wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
|
||||
|
||||
wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
|
||||
wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
|
||||
wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
|
||||
wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
|
||||
|
||||
wire trigger_tx;
|
||||
wire trigger_rx;
|
||||
|
||||
wire sleep_counter_compare;
|
||||
wire cs_sleep_counter_compare;
|
||||
wire cs_sleep_counter_compare2;
|
||||
|
||||
wire io_ready1;
|
||||
wire io_ready2;
|
||||
wire trigger_rx_s;
|
||||
|
||||
wire last_sdi_bit;
|
||||
|
||||
assign cmd_ready = idle;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (exec_transfer_cmd) begin
|
||||
sdo_enabled <= cmd[8];
|
||||
sdi_enabled <= cmd[9];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cmd_ready & cmd_valid)
|
||||
cmd_d1 <= cmd;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
active <= 1'b0;
|
||||
end else begin
|
||||
if (exec_cmd == 1'b1)
|
||||
active <= 1'b1;
|
||||
else if (sync_ready == 1'b1 && sync_valid == 1'b1)
|
||||
active <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Load the interface configurations from the 'Configuration Write'
|
||||
// instruction
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cpha <= DEFAULT_SPI_CFG[0];
|
||||
cpol <= DEFAULT_SPI_CFG[1];
|
||||
three_wire <= DEFAULT_SPI_CFG[2];
|
||||
clk_div <= DEFAULT_CLK_DIV;
|
||||
word_length <= DATA_WIDTH;
|
||||
left_aligned <= 8'b0;
|
||||
end else if (exec_write_cmd == 1'b1) begin
|
||||
if (cmd[9:8] == REG_CONFIG) begin
|
||||
cpha <= cmd[0];
|
||||
cpol <= cmd[1];
|
||||
three_wire <= cmd[2];
|
||||
end else if (cmd[9:8] == REG_CLK_DIV) begin
|
||||
clk_div <= cmd[7:0];
|
||||
end else if (cmd[9:8] == REG_WORD_LENGTH) begin
|
||||
// the max value of this reg must be DATA_WIDTH
|
||||
word_length <= cmd[7:0];
|
||||
left_aligned <= DATA_WIDTH - cmd[7:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
|
||||
clk_div_counter == 'h01) || clk_div == 'h00)
|
||||
clk_div_last <= 1'b1;
|
||||
else
|
||||
clk_div_last <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
|
||||
clk_div_counter <= clk_div;
|
||||
trigger <= 1'b1;
|
||||
end else begin
|
||||
clk_div_counter <= clk_div_counter - 1'b1;
|
||||
trigger <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
|
||||
assign trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
|
||||
|
||||
assign sleep_counter_compare = sleep_counter == cmd_d1[7:0] && clk_div_last == 1'b1;
|
||||
assign cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last == 1'b1;
|
||||
assign cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (idle == 1'b1) begin
|
||||
counter <= 'h00;
|
||||
end else if (clk_div_last == 1'b1 && wait_for_io == 1'b0) begin
|
||||
if (bit_counter == word_length) begin
|
||||
counter <= (counter & BIT_COUNTER_CLEAR) + (transfer_active ? 'h1 : 'h10) + BIT_COUNTER_CARRY;
|
||||
end else begin
|
||||
counter <= counter + (transfer_active ? 'h1 : 'h10);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
idle <= 1'b1;
|
||||
end else begin
|
||||
if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
|
||||
idle <= 1'b0;
|
||||
end else begin
|
||||
case (inst_d1)
|
||||
CMD_TRANSFER: begin
|
||||
if (transfer_active == 1'b0 && wait_for_io == 1'b0)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
CMD_CHIPSELECT: begin
|
||||
if (cs_sleep_counter_compare2)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
CMD_MISC: begin
|
||||
case (cmd_d1[8])
|
||||
MISC_SLEEP: begin
|
||||
if (sleep_counter_compare)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
MISC_SYNC: begin
|
||||
if (sync_ready)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cs <= 'hff;
|
||||
end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
|
||||
cs <= cmd_d1[NUM_OF_CS-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
sync_valid <= 1'b0;
|
||||
end else begin
|
||||
if (exec_sync_cmd == 1'b1) begin
|
||||
sync_valid <= 1'b1;
|
||||
end else if (sync_ready == 1'b1) begin
|
||||
sync_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sync = cmd_d1[7:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0)
|
||||
sdo_data_ready <= 1'b0;
|
||||
else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 && transfer_active == 1'b1)
|
||||
sdo_data_ready <= 1'b1;
|
||||
else if (sdo_data_valid == 1'b1)
|
||||
sdo_data_ready <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0)
|
||||
sdi_data_valid <= 1'b0;
|
||||
else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
|
||||
sdi_data_valid <= 1'b1;
|
||||
else if (sdi_data_ready == 1'b1)
|
||||
sdi_data_valid <= 1'b0;
|
||||
end
|
||||
|
||||
assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
|
||||
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
|
||||
assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
|
||||
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (idle == 1'b1) begin
|
||||
last_transfer <= 1'b0;
|
||||
end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
|
||||
if (transfer_counter == cmd_d1[7:0])
|
||||
last_transfer <= 1'b1;
|
||||
else
|
||||
last_transfer <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
transfer_active <= 1'b0;
|
||||
wait_for_io <= 1'b0;
|
||||
end else begin
|
||||
if (exec_transfer_cmd == 1'b1) begin
|
||||
wait_for_io <= 1'b1;
|
||||
transfer_active <= 1'b0;
|
||||
end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
|
||||
wait_for_io <= 1'b0;
|
||||
if (last_transfer == 1'b0)
|
||||
transfer_active <= 1'b1;
|
||||
else
|
||||
transfer_active <= 1'b0;
|
||||
end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
|
||||
if (last_transfer == 1'b1 || io_ready2 == 1'b0)
|
||||
transfer_active <= 1'b0;
|
||||
if (io_ready2 == 1'b0)
|
||||
wait_for_io <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (transfer_active == 1'b1 || wait_for_io == 1'b1)
|
||||
begin
|
||||
sdo_t_int <= ~sdo_enabled;
|
||||
end else begin
|
||||
sdo_t_int <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Load the SDO parallel data into the SDO shift register. In case of a custom
|
||||
// data width, additional bit shifting must done at load.
|
||||
always @(posedge clk) begin
|
||||
if ((inst_d1 == CMD_TRANSFER) && (!sdo_enabled)) begin
|
||||
data_sdo_shift <= {DATA_WIDTH{SDO_DEFAULT}};
|
||||
end else if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
|
||||
if (first_bit == 1'b1)
|
||||
data_sdo_shift <= sdo_data << left_aligned;
|
||||
else
|
||||
data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
|
||||
end
|
||||
end
|
||||
|
||||
assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1];
|
||||
|
||||
// In case of an interface with high clock rate (SCLK > 50MHz), the latch of
|
||||
// the SDI line can be delayed with 1, 2 or 3 SPI core clock cycle.
|
||||
// Taking the fact that in high SCLK frequencies the pre-scaler most likely will
|
||||
// be set to 0, to reduce the core clock's speed, this delay will mean that SDI will
|
||||
// be latched at one of the next consecutive SCLK edge.
|
||||
|
||||
always @(posedge clk) begin
|
||||
trigger_rx_d <= {trigger_rx_d, trigger_rx};
|
||||
end
|
||||
|
||||
assign trigger_rx_s = trigger_rx_d[SDI_DELAY+1];
|
||||
|
||||
// Load the serial data into SDI shift register(s), then link it to the output
|
||||
// register of the module
|
||||
|
||||
wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);
|
||||
genvar i;
|
||||
generate
|
||||
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
|
||||
|
||||
reg [DATA_WIDTH-1:0] data_sdi_shift;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
data_sdi_shift <= 0;
|
||||
end else begin
|
||||
if (trigger_rx_s == 1'b1) begin
|
||||
data_sdi_shift <= {data_sdi_shift, sdi[i]};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sdi_data[i*DATA_WIDTH+:DATA_WIDTH] = data_sdi_shift;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign last_sdi_bit = (sdi_counter == word_length-1);
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
sdi_counter <= 8'b0;
|
||||
end else begin
|
||||
if (trigger_rx_s == 1'b1) begin
|
||||
sdi_counter <= last_sdi_bit ? 8'b0 : sdi_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (transfer_active == 1'b1) begin
|
||||
sclk_int <= cpol ^ cpha ^ ntx_rx;
|
||||
end else begin
|
||||
sclk_int <= cpol;
|
||||
end
|
||||
end
|
||||
|
||||
// Additional register stage to improve timing
|
||||
always @(posedge clk) begin
|
||||
sclk <= sclk_int;
|
||||
sdo <= sdo_int_s;
|
||||
sdo_t <= sdo_t_int;
|
||||
end
|
||||
|
||||
endmodule
|
||||
+1646
File diff suppressed because it is too large
Load Diff
+842
@@ -0,0 +1,842 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_apis.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Set of Zynq VIP APIs that are used for writing tests.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* API for setting the STOP_ON_ERROR*/
|
||||
task automatic set_stop_on_error;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL);
|
||||
STOP_ON_ERROR = LEVEL;
|
||||
// M_AXI_GP0.master.set_stop_on_error(LEVEL);
|
||||
// M_AXI_GP1.master.set_stop_on_error(LEVEL);
|
||||
// S_AXI_GP0.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_GP1.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP0.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP1.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP2.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP3.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_ACP.slave.set_stop_on_error(LEVEL);
|
||||
M_AXI_GP0.STOP_ON_ERROR = LEVEL;
|
||||
M_AXI_GP1.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_GP0.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_GP1.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP0.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP1.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP2.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP3.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_ACP.STOP_ON_ERROR = LEVEL;
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting the verbosity for channel level info*/
|
||||
task automatic set_channel_level_info;
|
||||
input [1023:0] name;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO, name , LEVEL);
|
||||
case(name)
|
||||
// "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL);
|
||||
// "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL);
|
||||
"ALL" : begin
|
||||
// M_AXI_GP0.master.set_channel_level_info(LEVEL);
|
||||
// M_AXI_GP1.master.set_channel_level_info(LEVEL);
|
||||
// S_AXI_GP0.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_GP1.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP0.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP1.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP2.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP3.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_ACP.slave.set_channel_level_info(LEVEL);
|
||||
end
|
||||
default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting the verbosity for function level info*/
|
||||
task automatic set_function_level_info;
|
||||
input [1023:0] name;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO, name , LEVEL);
|
||||
case(name)
|
||||
// "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL);
|
||||
// "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL);
|
||||
// "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL);
|
||||
"ALL" : begin
|
||||
// M_AXI_GP0.master.set_function_level_info(LEVEL);
|
||||
// M_AXI_GP1.master.set_function_level_info(LEVEL);
|
||||
// S_AXI_GP0.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_GP1.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP0.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP1.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP2.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP3.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_ACP.slave.set_function_level_info(LEVEL);
|
||||
end
|
||||
default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting the Message verbosity */
|
||||
task automatic set_debug_level_info;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO, LEVEL);
|
||||
DEBUG_INFO = LEVEL;
|
||||
M_AXI_GP0.DEBUG_INFO = LEVEL;
|
||||
M_AXI_GP1.DEBUG_INFO = LEVEL;
|
||||
S_AXI_GP0.DEBUG_INFO = LEVEL;
|
||||
S_AXI_GP1.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP0.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP1.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP2.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP3.DEBUG_INFO = LEVEL;
|
||||
S_AXI_ACP.DEBUG_INFO = LEVEL;
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting ARQos Values */
|
||||
task automatic set_arqos;
|
||||
input [1023:0] name;
|
||||
input [axi_qos_width-1:0] value;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO, name , value);
|
||||
case(name)
|
||||
"S_AXI_GP0" : S_AXI_GP0.set_arqos(value);
|
||||
"S_AXI_GP1" : S_AXI_GP1.set_arqos(value);
|
||||
"S_AXI_HP0" : S_AXI_HP0.set_arqos(value);
|
||||
"S_AXI_HP1" : S_AXI_HP1.set_arqos(value);
|
||||
"S_AXI_HP2" : S_AXI_HP2.set_arqos(value);
|
||||
"S_AXI_HP3" : S_AXI_HP3.set_arqos(value);
|
||||
"S_AXI_ACP" : S_AXI_ACP.set_arqos(value);
|
||||
default : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting AWQos Values */
|
||||
task automatic set_awqos;
|
||||
input [1023:0] name;
|
||||
input [axi_qos_width-1:0] value;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO, name , value);
|
||||
case(name)
|
||||
"S_AXI_GP0" : S_AXI_GP0.set_awqos(value);
|
||||
"S_AXI_GP1" : S_AXI_GP1.set_awqos(value);
|
||||
"S_AXI_HP0" : S_AXI_HP0.set_awqos(value);
|
||||
"S_AXI_HP1" : S_AXI_HP1.set_awqos(value);
|
||||
"S_AXI_HP2" : S_AXI_HP2.set_awqos(value);
|
||||
"S_AXI_HP3" : S_AXI_HP3.set_awqos(value);
|
||||
"S_AXI_ACP" : S_AXI_ACP.set_awqos(value);
|
||||
default : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for soft reset control */
|
||||
task automatic fpga_soft_reset;
|
||||
input[data_width-1:0] reset_ctrl;
|
||||
begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO, reset_ctrl);
|
||||
gen_rst.fpga_soft_reset(reset_ctrl);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for por and strb reset control */
|
||||
// task automatic por_srstb_reset;
|
||||
// input por_reset_ctrl;
|
||||
// begin
|
||||
// if(DEBUG_INFO) $display("[%0d] : %0s : POR and STRB Reset called for 0x%0h",$time, DISP_INFO, por_reset_ctrl);
|
||||
// // gen_rst.por_srstb_reset(por_reset_ctrl);
|
||||
// gen_rst.por_srstb_reset(por_reset_ctrl);
|
||||
//
|
||||
// end
|
||||
// endtask
|
||||
|
||||
/* API for pre-loading memories from (DDR/OCM model) */
|
||||
task automatic pre_load_mem_from_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
succ = $fopen(file_name,"r");
|
||||
if(succ == 0) begin
|
||||
$display("[%0d] : %0s : '%0s' doesn't exist. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, file_name);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
else if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem_from_file' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for pre-loading memories (DDR/OCM) */
|
||||
task automatic pre_load_mem;
|
||||
input [1:0] data_type;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for backdoor write to memories (DDR/OCM) */
|
||||
task automatic write_mem;
|
||||
input [max_burst_bits-1 :0] data;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_burst_bytes_width:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
|
||||
else
|
||||
ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes,all_strb_valid);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'write_mem' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_mem' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* read_memory */
|
||||
task automatic read_mem;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_burst_bytes_width :0] no_of_bytes;
|
||||
output[max_burst_bits-1 :0] data;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.read_mem(data,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.read_mem(data,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'read_mem' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_mem' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for backdoor read to memories (DDR/OCM) */
|
||||
task automatic peek_mem_to_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'peek_mem_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'peek_mem_to_file' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to read interrupt status */
|
||||
task automatic read_interrupt;
|
||||
output[irq_width-1:0] irq_status;
|
||||
begin
|
||||
irq_status = IRQ_F2P;
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO, irq_status);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to wait on interrup */
|
||||
task automatic wait_interrupt;
|
||||
input [3:0] irq;
|
||||
output[irq_width-1:0] irq_status;
|
||||
begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO, irq);
|
||||
|
||||
case(irq)
|
||||
0 : wait(IRQ_F2P[0] === 1'b1);
|
||||
1 : wait(IRQ_F2P[1] === 1'b1);
|
||||
2 : wait(IRQ_F2P[2] === 1'b1);
|
||||
3 : wait(IRQ_F2P[3] === 1'b1);
|
||||
4 : wait(IRQ_F2P[4] === 1'b1);
|
||||
5 : wait(IRQ_F2P[5] === 1'b1);
|
||||
6 : wait(IRQ_F2P[6] === 1'b1);
|
||||
7 : wait(IRQ_F2P[7] === 1'b1);
|
||||
8 : wait(IRQ_F2P[8] === 1'b1);
|
||||
9 : wait(IRQ_F2P[9] === 1'b1);
|
||||
10: wait(IRQ_F2P[10] === 1'b1);
|
||||
11: wait(IRQ_F2P[11] === 1'b1);
|
||||
12: wait(IRQ_F2P[12] === 1'b1);
|
||||
13: wait(IRQ_F2P[13] === 1'b1);
|
||||
14: wait(IRQ_F2P[14] === 1'b1);
|
||||
15: wait(IRQ_F2P[15] === 1'b1);
|
||||
default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR);
|
||||
endcase
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO, irq);
|
||||
irq_status = IRQ_F2P;
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to wait for a certain match pattern*/
|
||||
task automatic wait_mem_update;
|
||||
input[addr_width-1:0] address;
|
||||
input[data_width-1:0] data_in;
|
||||
output[data_width-1:0] data_out;
|
||||
reg[data_width-1:0] datao;
|
||||
begin
|
||||
if(mem_update_key) begin
|
||||
mem_update_key = 0;
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : 'wait_mem_update' called for Address(0x%0h) , Match Pattern(0x%0h) \n",$time, DISP_INFO, address, data_in);
|
||||
if(check_addr_aligned(address)) begin
|
||||
ddrc.ddr.wait_mem_update(address, datao);
|
||||
if(datao != data_in)begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \n",$time, DISP_ERR, address, data_in,datao);
|
||||
$stop;
|
||||
end else
|
||||
$display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \n",$time, DISP_INFO, address, data_in);
|
||||
data_out = datao;
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'wait_mem_update' call failed ...\n",$time, DISP_ERR, address);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
mem_update_key = 1;
|
||||
end else
|
||||
$display("[%0d] : %0s : One instance of 'wait_mem_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
/* API to initiate a WRITE transaction on one of the AXI-Master ports*/
|
||||
task automatic write_from_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] wr_size;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
integer succ;
|
||||
begin
|
||||
succ = $fopen(file_name,"r");
|
||||
if(succ == 0) begin
|
||||
$display("[%0d] : %0s : '%0s' doesn't exist. 'write_from_file' call failed ...\n",$time, DISP_ERR, file_name);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
else if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(check_addr_aligned(start_addr)) begin
|
||||
$fclose(succ);
|
||||
// case(start_addr[31:30])
|
||||
if (start_addr[31:30] === 2'b01) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name);
|
||||
M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name);
|
||||
M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
// endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to initiate a READ transaction on one of the AXI-Master ports*/
|
||||
task automatic read_to_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] rd_size;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR , start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(check_addr_aligned(start_addr)) begin
|
||||
// case(start_addr[31:30])
|
||||
if (start_addr[31:30] === 2'b01) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name);
|
||||
M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name);
|
||||
M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
// end
|
||||
// default : $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
// endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/
|
||||
task automatic write_data;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_transfer_bytes_width:0] wr_size;
|
||||
input [(max_transfer_bytes*8)-1:0] w_data;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(wr_size > max_transfer_bytes) begin
|
||||
$display("[%0d] : %0s : Byte Size supported is 128 bytes only. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size);
|
||||
M_AXI_GP0.write_data(start_addr,wr_size,w_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size);
|
||||
M_AXI_GP1.write_data(start_addr,wr_size,w_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/
|
||||
task automatic read_data;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_transfer_bytes_width:0] rd_size;
|
||||
output[(max_transfer_bytes*8)-1:0] rd_data;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range 'read_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(rd_size > max_transfer_bytes) begin
|
||||
$display("[%0d] : %0s : Byte Size supported is 128 bytes only.'read_data' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size);
|
||||
M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size);
|
||||
M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'read_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* Hooks to call to VIP APIs */
|
||||
task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === 2'b01) begin
|
||||
// end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
// end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
|
||||
reg[511:0] rsp; /// string for response
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst_concurrent' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === 2'b01) begin
|
||||
// end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
// end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst_concurrent' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic read_burst;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [axi_len_width-1:0] len;
|
||||
input [axi_size_width-1:0] siz;
|
||||
input [axi_brst_type_width-1:0] burst;
|
||||
input [axi_lock_width-1:0] lck;
|
||||
input [axi_cache_width-1:0] cache;
|
||||
input [axi_prot_width-1:0] prot;
|
||||
output [(axi_mgp_data_width*axi_burst_len)-1:0] data;
|
||||
output [(axi_rsp_width*axi_burst_len)-1:0] response;
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'read_burst' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === 2'b01) begin
|
||||
// end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr);
|
||||
M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
// end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr);
|
||||
M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'read_burst' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic wait_reg_update;
|
||||
input [addr_width-1:0] addr;
|
||||
input [data_width-1:0] data_i;
|
||||
input [data_width-1:0] mask_i;
|
||||
input [int_width-1:0] time_interval;
|
||||
input [int_width-1:0] time_out;
|
||||
output [data_width-1:0] data_o;
|
||||
|
||||
reg upd_done0;
|
||||
reg upd_done1;
|
||||
begin
|
||||
if(!check_master_address(addr)) begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out of range. 'wait_reg_update' call failed ...\n",$time, DISP_ERR, addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(addr[31:30] === 2'b01) begin
|
||||
// end else if(addr[31:30] === GP_M0) begin
|
||||
if(reg_update_key_0) begin
|
||||
reg_update_key_0 = 0;
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i);
|
||||
M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0);
|
||||
if(DEBUG_INFO && upd_done0)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr);
|
||||
reg_update_key_0 = 1;
|
||||
end else
|
||||
$display("[%0d] : M_AXI_GP0 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
|
||||
end else if(addr[31:30] === 2'b10) begin
|
||||
// end else if(addr[31:30] === GP_M1) begin
|
||||
if(reg_update_key_1) begin
|
||||
reg_update_key_1 = 0;
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i);
|
||||
M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1);
|
||||
if(DEBUG_INFO && upd_done1)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr);
|
||||
reg_update_key_1 = 1;
|
||||
end else
|
||||
$display("[%0d] : M_AXI_GP1 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'wait_reg_update' call failed ... \n",$time, DISP_ERR, addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to read register map */
|
||||
task read_register_map;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_regs_width:0] no_of_registers;
|
||||
output[max_burst_bits-1 :0] data;
|
||||
reg [max_regs_width:0] no_of_regs;
|
||||
begin
|
||||
no_of_regs = no_of_registers;
|
||||
if(no_of_registers > 32) begin
|
||||
$display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\n Only 32 registers will be read.",$time, DISP_ERR, start_addr);
|
||||
no_of_regs = 32;
|
||||
end
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
if(decode_address(start_addr) == REG_MEM) begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO, start_addr,no_of_regs );
|
||||
regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, start_addr, data );
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
end else begin
|
||||
data = 0;
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to read single register */
|
||||
task read_register;
|
||||
input [addr_width-1:0] addr;
|
||||
output[data_width-1:0] data;
|
||||
begin
|
||||
if(check_addr_aligned(addr)) begin
|
||||
if(decode_address(addr) == REG_MEM) begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO, addr );
|
||||
regc.regm.get_data(addr >> 2, data);
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, addr, data );
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register' call failed ...",$time, DISP_ERR, addr);
|
||||
end
|
||||
end else begin
|
||||
data = 0;
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register' call failed ...",$time, DISP_ERR, addr);
|
||||
end
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to set the AXI-Slave profile*/
|
||||
task automatic set_slave_profile;
|
||||
input[1023:0] name;
|
||||
input[1:0] latency ;
|
||||
begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO, name);
|
||||
case(name)
|
||||
"S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency);
|
||||
"S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency);
|
||||
"S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency);
|
||||
"S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency);
|
||||
"S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency);
|
||||
"S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency);
|
||||
"S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency);
|
||||
"ALL" : begin
|
||||
S_AXI_GP0.set_latency_type(latency);
|
||||
S_AXI_GP1.set_latency_type(latency);
|
||||
S_AXI_HP0.set_latency_type(latency);
|
||||
S_AXI_HP1.set_latency_type(latency);
|
||||
S_AXI_HP2.set_latency_type(latency);
|
||||
S_AXI_HP3.set_latency_type(latency);
|
||||
S_AXI_ACP.set_latency_type(latency);
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
/*------------------------------ LOCAL APIs ------------------------------------------------ */
|
||||
|
||||
/* local API for address decoding*/
|
||||
function automatic [1:0] decode_address;
|
||||
input [addr_width-1:0] address;
|
||||
begin
|
||||
if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr ))
|
||||
decode_address = OCM_MEM; /// OCM
|
||||
else if(address >= ddr_start_addr && address <= ddr_end_addr)
|
||||
decode_address = DDR_MEM; /// DDR
|
||||
else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr)
|
||||
decode_address = OCM_MEM; /// OCM
|
||||
else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr)
|
||||
decode_address = REG_MEM; /// Register Map
|
||||
else
|
||||
decode_address = INVALID_MEM_TYPE; /// ERROR in Address
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* local API for checking address is 32-bit (4-byte) aligned */
|
||||
function automatic check_addr_aligned;
|
||||
input [addr_width-1:0] address;
|
||||
begin
|
||||
if((address%4) !=0 ) begin //
|
||||
check_addr_aligned = 0; ///not_aligned
|
||||
end else
|
||||
check_addr_aligned = 1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* local API to check address for GP Masters */
|
||||
function check_master_address;
|
||||
input [addr_width-1:0] address;
|
||||
begin
|
||||
if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr)
|
||||
check_master_address = 1'b1;
|
||||
else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr)
|
||||
check_master_address = 1'b1;
|
||||
else
|
||||
check_master_address = 1'b0; /// ERROR in Address
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* Response decode */
|
||||
function automatic [511:0] get_resp;
|
||||
input[axi_rsp_width-1:0] response;
|
||||
begin
|
||||
case(response)
|
||||
2'b00 : get_resp = "OKAY";
|
||||
2'b01 : get_resp = "EXOKAY";
|
||||
2'b10 : get_resp = "SLVERR";
|
||||
2'b11 : get_resp = "DECERR";
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
+94
@@ -0,0 +1,94 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_axi_acp.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Connections for ACP port
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* AXI Slave ACP */
|
||||
processing_system7_vip_v1_0_7_axi_slave_acp #( C_USE_S_AXI_ACP, // enable
|
||||
axi_acp_name, // name
|
||||
axi_acp_data_width, // data width
|
||||
addr_width, /// address width
|
||||
axi_acp_id_width, // ID width
|
||||
C_S_AXI_ACP_BASEADDR, // slave base address
|
||||
C_S_AXI_ACP_HIGHADDR,// slave size
|
||||
axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes
|
||||
axi_slv_excl_support, // Exclusive access support
|
||||
axi_acp_wr_outstanding,
|
||||
axi_acp_rd_outstanding)
|
||||
S_AXI_ACP(.S_RESETN (net_axi_acp_rstn),
|
||||
.S_ACLK (S_AXI_ACP_ACLK),
|
||||
// Write Address Channel
|
||||
.S_AWID (S_AXI_ACP_AWID),
|
||||
.S_AWADDR (S_AXI_ACP_AWADDR),
|
||||
.S_AWLEN (S_AXI_ACP_AWLEN),
|
||||
.S_AWSIZE (S_AXI_ACP_AWSIZE),
|
||||
.S_AWBURST (S_AXI_ACP_AWBURST),
|
||||
.S_AWLOCK (S_AXI_ACP_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_ACP_AWCACHE),
|
||||
.S_AWPROT (S_AXI_ACP_AWPROT),
|
||||
.S_AWVALID (S_AXI_ACP_AWVALID),
|
||||
.S_AWREADY (S_AXI_ACP_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.S_WID (S_AXI_ACP_WID),
|
||||
.S_WDATA (S_AXI_ACP_WDATA),
|
||||
.S_WSTRB (S_AXI_ACP_WSTRB),
|
||||
.S_WLAST (S_AXI_ACP_WLAST),
|
||||
.S_WVALID (S_AXI_ACP_WVALID),
|
||||
.S_WREADY (S_AXI_ACP_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.S_BID (S_AXI_ACP_BID),
|
||||
.S_BRESP (S_AXI_ACP_BRESP),
|
||||
.S_BVALID (S_AXI_ACP_BVALID),
|
||||
.S_BREADY (S_AXI_ACP_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.S_ARID (S_AXI_ACP_ARID),
|
||||
.S_ARADDR (S_AXI_ACP_ARADDR),
|
||||
.S_ARLEN (S_AXI_ACP_ARLEN),
|
||||
.S_ARSIZE (S_AXI_ACP_ARSIZE),
|
||||
.S_ARBURST (S_AXI_ACP_ARBURST),
|
||||
.S_ARLOCK (S_AXI_ACP_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_ACP_ARCACHE),
|
||||
.S_ARPROT (S_AXI_ACP_ARPROT),
|
||||
.S_ARVALID (S_AXI_ACP_ARVALID),
|
||||
.S_ARREADY (S_AXI_ACP_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.S_RID (S_AXI_ACP_RID),
|
||||
.S_RDATA (S_AXI_ACP_RDATA),
|
||||
.S_RRESP (S_AXI_ACP_RRESP),
|
||||
.S_RLAST (S_AXI_ACP_RLAST),
|
||||
.S_RVALID (S_AXI_ACP_RVALID),
|
||||
.S_RREADY (S_AXI_ACP_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_ACP_AWQOS),
|
||||
.S_ARQOS (S_AXI_ACP_ARQOS), // Side band signals
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/
|
||||
.WR_DATA_ACK_DDR (ddr_wr_ack_port0),
|
||||
.WR_DATA_ACK_OCM (ocm_wr_ack_port0),
|
||||
.WR_DATA (net_wr_data_acp),
|
||||
.WR_DATA_STRB (net_wr_strb_acp),
|
||||
.WR_ADDR (net_wr_addr_acp),
|
||||
.WR_BYTES (net_wr_bytes_acp),
|
||||
.WR_DATA_VALID_DDR (ddr_wr_dv_port0),
|
||||
.WR_DATA_VALID_OCM (ocm_wr_dv_port0),
|
||||
.WR_QOS (net_wr_qos_acp),
|
||||
|
||||
.RD_REQ_DDR (ddr_rd_req_port0),
|
||||
.RD_REQ_OCM (ocm_rd_req_port0),
|
||||
.RD_REQ_REG (reg_rd_req_port0),
|
||||
.RD_ADDR (net_rd_addr_acp),
|
||||
.RD_DATA_DDR (ddr_rd_data_port0),
|
||||
.RD_DATA_OCM (ocm_rd_data_port0),
|
||||
.RD_DATA_REG (reg_rd_data_port0),
|
||||
.RD_BYTES (net_rd_bytes_acp),
|
||||
.RD_DATA_VALID_DDR (ddr_rd_dv_port0),
|
||||
.RD_DATA_VALID_OCM (ocm_rd_dv_port0),
|
||||
.RD_DATA_VALID_REG (reg_rd_dv_port0),
|
||||
.RD_QOS (net_rd_qos_acp)
|
||||
|
||||
);
|
||||
+311
@@ -0,0 +1,311 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_axi_gp.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Connections for AXI GP ports
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* IDs for Masters
|
||||
// l2m1 (CPU000)
|
||||
12'b11_000_000_00_00
|
||||
12'b11_010_000_00_00
|
||||
12'b11_011_000_00_00
|
||||
12'b11_100_000_00_00
|
||||
12'b11_101_000_00_00
|
||||
12'b11_110_000_00_00
|
||||
12'b11_111_000_00_00
|
||||
// l2m1 (CPU001)
|
||||
12'b11_000_001_00_00
|
||||
12'b11_010_001_00_00
|
||||
12'b11_011_001_00_00
|
||||
12'b11_100_001_00_00
|
||||
12'b11_101_001_00_00
|
||||
12'b11_110_001_00_00
|
||||
12'b11_111_001_00_00
|
||||
*/
|
||||
|
||||
/* AXI -Master GP0 */
|
||||
processing_system7_vip_v1_0_7_axi_master #(C_USE_M_AXI_GP0, // enable
|
||||
axi_mgp0_name,// name
|
||||
axi_mgp_data_width, /// Data Width
|
||||
addr_width, /// Address width
|
||||
axi_mgp_id_width, //// ID Width
|
||||
axi_mgp_outstanding, //// Outstanding transactions
|
||||
axi_mst_excl_support, // EXCL Access Support
|
||||
axi_mgp_wr_id, //WR_ID
|
||||
axi_mgp_rd_id) //RD_ID
|
||||
M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn),
|
||||
.M_ACLK (M_AXI_GP0_ACLK),
|
||||
// Write Address Channel
|
||||
.M_AWID (M_AXI_GP0_AWID_FULL),
|
||||
.M_AWADDR (M_AXI_GP0_AWADDR),
|
||||
.M_AWLEN (M_AXI_GP0_AWLEN),
|
||||
.M_AWSIZE (M_AXI_GP0_AWSIZE),
|
||||
.M_AWBURST (M_AXI_GP0_AWBURST),
|
||||
.M_AWLOCK (M_AXI_GP0_AWLOCK),
|
||||
.M_AWCACHE (M_AXI_GP0_AWCACHE),
|
||||
.M_AWPROT (M_AXI_GP0_AWPROT),
|
||||
.M_AWVALID (M_AXI_GP0_AWVALID),
|
||||
.M_AWREADY (M_AXI_GP0_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.M_WID (M_AXI_GP0_WID_FULL),
|
||||
.M_WDATA (M_AXI_GP0_WDATA),
|
||||
.M_WSTRB (M_AXI_GP0_WSTRB),
|
||||
.M_WLAST (M_AXI_GP0_WLAST),
|
||||
.M_WVALID (M_AXI_GP0_WVALID),
|
||||
.M_WREADY (M_AXI_GP0_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.M_BID (M_AXI_GP0_BID_FULL),
|
||||
.M_BRESP (M_AXI_GP0_BRESP),
|
||||
.M_BVALID (M_AXI_GP0_BVALID),
|
||||
.M_BREADY (M_AXI_GP0_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.M_ARID (M_AXI_GP0_ARID_FULL),
|
||||
.M_ARADDR (M_AXI_GP0_ARADDR),
|
||||
.M_ARLEN (M_AXI_GP0_ARLEN),
|
||||
.M_ARSIZE (M_AXI_GP0_ARSIZE),
|
||||
.M_ARBURST (M_AXI_GP0_ARBURST),
|
||||
.M_ARLOCK (M_AXI_GP0_ARLOCK),
|
||||
.M_ARCACHE (M_AXI_GP0_ARCACHE),
|
||||
.M_ARPROT (M_AXI_GP0_ARPROT),
|
||||
.M_ARVALID (M_AXI_GP0_ARVALID),
|
||||
.M_ARREADY (M_AXI_GP0_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.M_RID (M_AXI_GP0_RID_FULL),
|
||||
.M_RDATA (M_AXI_GP0_RDATA),
|
||||
.M_RRESP (M_AXI_GP0_RRESP),
|
||||
.M_RLAST (M_AXI_GP0_RLAST),
|
||||
.M_RVALID (M_AXI_GP0_RVALID),
|
||||
.M_RREADY (M_AXI_GP0_RREADY),
|
||||
// Side band signals
|
||||
.M_AWQOS (M_AXI_GP0_AWQOS),
|
||||
.M_ARQOS (M_AXI_GP0_ARQOS)
|
||||
);
|
||||
|
||||
/* AXI Master GP1 */
|
||||
processing_system7_vip_v1_0_7_axi_master #(C_USE_M_AXI_GP1, // enable
|
||||
axi_mgp1_name,// name
|
||||
axi_mgp_data_width, /// Data Width
|
||||
addr_width, /// Address width
|
||||
axi_mgp_id_width, //// ID Width
|
||||
axi_mgp_outstanding, //// Outstanding transactions
|
||||
axi_mst_excl_support, // EXCL Access Support
|
||||
axi_mgp_wr_id, //WR_ID
|
||||
axi_mgp_rd_id) //RD_ID
|
||||
M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn),
|
||||
.M_ACLK (M_AXI_GP1_ACLK),
|
||||
// Write Address Channel
|
||||
.M_AWID (M_AXI_GP1_AWID_FULL),
|
||||
.M_AWADDR (M_AXI_GP1_AWADDR),
|
||||
.M_AWLEN (M_AXI_GP1_AWLEN),
|
||||
.M_AWSIZE (M_AXI_GP1_AWSIZE),
|
||||
.M_AWBURST (M_AXI_GP1_AWBURST),
|
||||
.M_AWLOCK (M_AXI_GP1_AWLOCK),
|
||||
.M_AWCACHE (M_AXI_GP1_AWCACHE),
|
||||
.M_AWPROT (M_AXI_GP1_AWPROT),
|
||||
.M_AWVALID (M_AXI_GP1_AWVALID),
|
||||
.M_AWREADY (M_AXI_GP1_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.M_WID (M_AXI_GP1_WID_FULL),
|
||||
.M_WDATA (M_AXI_GP1_WDATA),
|
||||
.M_WSTRB (M_AXI_GP1_WSTRB),
|
||||
.M_WLAST (M_AXI_GP1_WLAST),
|
||||
.M_WVALID (M_AXI_GP1_WVALID),
|
||||
.M_WREADY (M_AXI_GP1_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.M_BID (M_AXI_GP1_BID_FULL),
|
||||
.M_BRESP (M_AXI_GP1_BRESP),
|
||||
.M_BVALID (M_AXI_GP1_BVALID),
|
||||
.M_BREADY (M_AXI_GP1_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.M_ARID (M_AXI_GP1_ARID_FULL),
|
||||
.M_ARADDR (M_AXI_GP1_ARADDR),
|
||||
.M_ARLEN (M_AXI_GP1_ARLEN),
|
||||
.M_ARSIZE (M_AXI_GP1_ARSIZE),
|
||||
.M_ARBURST (M_AXI_GP1_ARBURST),
|
||||
.M_ARLOCK (M_AXI_GP1_ARLOCK),
|
||||
.M_ARCACHE (M_AXI_GP1_ARCACHE),
|
||||
.M_ARPROT (M_AXI_GP1_ARPROT),
|
||||
.M_ARVALID (M_AXI_GP1_ARVALID),
|
||||
.M_ARREADY (M_AXI_GP1_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.M_RID (M_AXI_GP1_RID_FULL),
|
||||
.M_RDATA (M_AXI_GP1_RDATA),
|
||||
.M_RRESP (M_AXI_GP1_RRESP),
|
||||
.M_RLAST (M_AXI_GP1_RLAST),
|
||||
.M_RVALID (M_AXI_GP1_RVALID),
|
||||
.M_RREADY (M_AXI_GP1_RREADY),
|
||||
// Side band signals
|
||||
.M_AWQOS (M_AXI_GP1_AWQOS),
|
||||
.M_ARQOS (M_AXI_GP1_ARQOS)
|
||||
);
|
||||
|
||||
/* AXI Slave GP0 */
|
||||
processing_system7_vip_v1_0_7_axi_slave #(C_USE_S_AXI_GP0, /// enable
|
||||
axi_sgp0_name, //name
|
||||
axi_sgp_data_width, /// data width
|
||||
addr_width, /// address width
|
||||
axi_sgp_id_width, /// ID width
|
||||
C_S_AXI_GP0_BASEADDR,//// base address
|
||||
C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr)
|
||||
axi_sgp_outstanding, // outstanding transactions
|
||||
axi_slv_excl_support, // exclusive access not supported
|
||||
axi_sgp_wr_outstanding,
|
||||
axi_sgp_rd_outstanding)
|
||||
S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn),
|
||||
.S_ACLK (S_AXI_GP0_ACLK),
|
||||
// Write Address Channel
|
||||
.S_AWID (S_AXI_GP0_AWID),
|
||||
.S_AWADDR (S_AXI_GP0_AWADDR),
|
||||
.S_AWLEN (S_AXI_GP0_AWLEN),
|
||||
.S_AWSIZE (S_AXI_GP0_AWSIZE),
|
||||
.S_AWBURST (S_AXI_GP0_AWBURST),
|
||||
.S_AWLOCK (S_AXI_GP0_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_GP0_AWCACHE),
|
||||
.S_AWPROT (S_AXI_GP0_AWPROT),
|
||||
.S_AWVALID (S_AXI_GP0_AWVALID),
|
||||
.S_AWREADY (S_AXI_GP0_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.S_WID (S_AXI_GP0_WID),
|
||||
.S_WDATA (S_AXI_GP0_WDATA),
|
||||
.S_WSTRB (S_AXI_GP0_WSTRB),
|
||||
.S_WLAST (S_AXI_GP0_WLAST),
|
||||
.S_WVALID (S_AXI_GP0_WVALID),
|
||||
.S_WREADY (S_AXI_GP0_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.S_BID (S_AXI_GP0_BID),
|
||||
.S_BRESP (S_AXI_GP0_BRESP),
|
||||
.S_BVALID (S_AXI_GP0_BVALID),
|
||||
.S_BREADY (S_AXI_GP0_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.S_ARID (S_AXI_GP0_ARID),
|
||||
.S_ARADDR (S_AXI_GP0_ARADDR),
|
||||
.S_ARLEN (S_AXI_GP0_ARLEN),
|
||||
.S_ARSIZE (S_AXI_GP0_ARSIZE),
|
||||
.S_ARBURST (S_AXI_GP0_ARBURST),
|
||||
.S_ARLOCK (S_AXI_GP0_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_GP0_ARCACHE),
|
||||
.S_ARPROT (S_AXI_GP0_ARPROT),
|
||||
.S_ARVALID (S_AXI_GP0_ARVALID),
|
||||
.S_ARREADY (S_AXI_GP0_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.S_RID (S_AXI_GP0_RID),
|
||||
.S_RDATA (S_AXI_GP0_RDATA),
|
||||
.S_RRESP (S_AXI_GP0_RRESP),
|
||||
.S_RLAST (S_AXI_GP0_RLAST),
|
||||
.S_RVALID (S_AXI_GP0_RVALID),
|
||||
.S_RREADY (S_AXI_GP0_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_GP0_AWQOS),
|
||||
.S_ARQOS (S_AXI_GP0_ARQOS),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0),
|
||||
.WR_DATA (net_wr_data_gp0),
|
||||
.WR_DATA_STRB (net_wr_strb_gp0),
|
||||
.WR_ADDR (net_wr_addr_gp0),
|
||||
.WR_BYTES (net_wr_bytes_gp0),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_gp0),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_gp0),
|
||||
.WR_QOS (net_wr_qos_gp0),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_gp0),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_gp0),
|
||||
.RD_REQ_REG (net_rd_req_reg_gp0),
|
||||
.RD_ADDR (net_rd_addr_gp0),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_gp0),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_gp0),
|
||||
.RD_DATA_REG (net_rd_data_reg_gp0),
|
||||
.RD_BYTES (net_rd_bytes_gp0),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0),
|
||||
.RD_DATA_VALID_REG (net_rd_dv_reg_gp0),
|
||||
.RD_QOS (net_rd_qos_gp0)
|
||||
|
||||
);
|
||||
|
||||
/* AXI Slave GP1 */
|
||||
processing_system7_vip_v1_0_7_axi_slave #(C_USE_S_AXI_GP1, /// enable
|
||||
axi_sgp1_name, //name
|
||||
axi_sgp_data_width, /// data width
|
||||
addr_width, /// address width
|
||||
axi_sgp_id_width, /// ID width
|
||||
C_S_AXI_GP1_BASEADDR,//// base address
|
||||
C_S_AXI_GP1_HIGHADDR,/// HIGh_addr
|
||||
axi_sgp_outstanding, // outstanding transactions
|
||||
axi_slv_excl_support, // exclusive access
|
||||
axi_sgp_wr_outstanding,
|
||||
axi_sgp_rd_outstanding)
|
||||
S_AXI_GP1(.S_RESETN (net_axi_gp1_rstn),
|
||||
.S_ACLK (S_AXI_GP1_ACLK),
|
||||
// Write Address Channel
|
||||
.S_AWID (S_AXI_GP1_AWID),
|
||||
.S_AWADDR (S_AXI_GP1_AWADDR),
|
||||
.S_AWLEN (S_AXI_GP1_AWLEN),
|
||||
.S_AWSIZE (S_AXI_GP1_AWSIZE),
|
||||
.S_AWBURST (S_AXI_GP1_AWBURST),
|
||||
.S_AWLOCK (S_AXI_GP1_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_GP1_AWCACHE),
|
||||
.S_AWPROT (S_AXI_GP1_AWPROT),
|
||||
.S_AWVALID (S_AXI_GP1_AWVALID),
|
||||
.S_AWREADY (S_AXI_GP1_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.S_WID (S_AXI_GP1_WID),
|
||||
.S_WDATA (S_AXI_GP1_WDATA),
|
||||
.S_WSTRB (S_AXI_GP1_WSTRB),
|
||||
.S_WLAST (S_AXI_GP1_WLAST),
|
||||
.S_WVALID (S_AXI_GP1_WVALID),
|
||||
.S_WREADY (S_AXI_GP1_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.S_BID (S_AXI_GP1_BID),
|
||||
.S_BRESP (S_AXI_GP1_BRESP),
|
||||
.S_BVALID (S_AXI_GP1_BVALID),
|
||||
.S_BREADY (S_AXI_GP1_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.S_ARID (S_AXI_GP1_ARID),
|
||||
.S_ARADDR (S_AXI_GP1_ARADDR),
|
||||
.S_ARLEN (S_AXI_GP1_ARLEN),
|
||||
.S_ARSIZE (S_AXI_GP1_ARSIZE),
|
||||
.S_ARBURST (S_AXI_GP1_ARBURST),
|
||||
.S_ARLOCK (S_AXI_GP1_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_GP1_ARCACHE),
|
||||
.S_ARPROT (S_AXI_GP1_ARPROT),
|
||||
.S_ARVALID (S_AXI_GP1_ARVALID),
|
||||
.S_ARREADY (S_AXI_GP1_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.S_RID (S_AXI_GP1_RID),
|
||||
.S_RDATA (S_AXI_GP1_RDATA),
|
||||
.S_RRESP (S_AXI_GP1_RRESP),
|
||||
.S_RLAST (S_AXI_GP1_RLAST),
|
||||
.S_RVALID (S_AXI_GP1_RVALID),
|
||||
.S_RREADY (S_AXI_GP1_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_GP1_AWQOS),
|
||||
.S_ARQOS (S_AXI_GP1_ARQOS),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1),
|
||||
.WR_DATA (net_wr_data_gp1),
|
||||
.WR_DATA_STRB (net_wr_strb_gp1),
|
||||
.WR_ADDR (net_wr_addr_gp1),
|
||||
.WR_BYTES (net_wr_bytes_gp1),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_gp1),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_gp1),
|
||||
.WR_QOS (net_wr_qos_gp1),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_gp1),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_gp1),
|
||||
.RD_REQ_REG (net_rd_req_reg_gp1),
|
||||
.RD_ADDR (net_rd_addr_gp1),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_gp1),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_gp1),
|
||||
.RD_DATA_REG (net_rd_data_reg_gp1),
|
||||
.RD_BYTES (net_rd_bytes_gp1),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1),
|
||||
.RD_DATA_VALID_REG (net_rd_dv_reg_gp1),
|
||||
.RD_QOS (net_rd_qos_gp1)
|
||||
|
||||
);
|
||||
+350
@@ -0,0 +1,350 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_axi_hp.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Connections for AXI HP ports
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* AXI Slave HP0 */
|
||||
processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP0, // enable
|
||||
axi_hp0_name, // name
|
||||
C_S_AXI_HP0_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP0_BASEADDR, // slave base address
|
||||
C_S_AXI_HP0_HIGHADDR, // slave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn),
|
||||
.S_ACLK (S_AXI_HP0_ACLK),
|
||||
// Write Address channel
|
||||
.S_AWID (S_AXI_HP0_AWID),
|
||||
.S_AWADDR (S_AXI_HP0_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP0_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP0_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP0_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP0_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP0_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP0_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP0_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP0_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP0_WID),
|
||||
.S_WDATA (S_AXI_HP0_WDATA),
|
||||
.S_WSTRB (S_AXI_HP0_WSTRB),
|
||||
.S_WLAST (S_AXI_HP0_WLAST),
|
||||
.S_WVALID (S_AXI_HP0_WVALID),
|
||||
.S_WREADY (S_AXI_HP0_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP0_BID),
|
||||
.S_BRESP (S_AXI_HP0_BRESP),
|
||||
.S_BVALID (S_AXI_HP0_BVALID),
|
||||
.S_BREADY (S_AXI_HP0_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP0_ARID),
|
||||
.S_ARADDR (S_AXI_HP0_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP0_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP0_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP0_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP0_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP0_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP0_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP0_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP0_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP0_RID),
|
||||
.S_RDATA (S_AXI_HP0_RDATA),
|
||||
.S_RRESP (S_AXI_HP0_RRESP),
|
||||
.S_RLAST (S_AXI_HP0_RLAST),
|
||||
.S_RVALID (S_AXI_HP0_RVALID),
|
||||
.S_RREADY (S_AXI_HP0_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP0_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP0_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP0_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP0_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP0_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP0_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0),
|
||||
.WR_DATA (net_wr_data_hp0),
|
||||
.WR_DATA_STRB (net_wr_strb_hp0),
|
||||
.WR_ADDR (net_wr_addr_hp0),
|
||||
.WR_BYTES (net_wr_bytes_hp0),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp0),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp0),
|
||||
.WR_QOS (net_wr_qos_hp0),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp0),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp0),
|
||||
.RD_ADDR (net_rd_addr_hp0),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp0),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp0),
|
||||
.RD_BYTES (net_rd_bytes_hp0),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0),
|
||||
.RD_QOS (net_rd_qos_hp0)
|
||||
);
|
||||
|
||||
/* AXI Slave HP1 */
|
||||
processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP1, // enable
|
||||
axi_hp1_name, // name
|
||||
C_S_AXI_HP1_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP1_BASEADDR, // slave base address
|
||||
C_S_AXI_HP1_HIGHADDR, // Slave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn),
|
||||
.S_ACLK (S_AXI_HP1_ACLK),
|
||||
// Write Address channel
|
||||
.S_AWID (S_AXI_HP1_AWID),
|
||||
.S_AWADDR (S_AXI_HP1_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP1_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP1_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP1_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP1_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP1_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP1_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP1_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP1_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP1_WID),
|
||||
.S_WDATA (S_AXI_HP1_WDATA),
|
||||
.S_WSTRB (S_AXI_HP1_WSTRB),
|
||||
.S_WLAST (S_AXI_HP1_WLAST),
|
||||
.S_WVALID (S_AXI_HP1_WVALID),
|
||||
.S_WREADY (S_AXI_HP1_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP1_BID),
|
||||
.S_BRESP (S_AXI_HP1_BRESP),
|
||||
.S_BVALID (S_AXI_HP1_BVALID),
|
||||
.S_BREADY (S_AXI_HP1_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP1_ARID),
|
||||
.S_ARADDR (S_AXI_HP1_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP1_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP1_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP1_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP1_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP1_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP1_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP1_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP1_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP1_RID),
|
||||
.S_RDATA (S_AXI_HP1_RDATA),
|
||||
.S_RRESP (S_AXI_HP1_RRESP),
|
||||
.S_RLAST (S_AXI_HP1_RLAST),
|
||||
.S_RVALID (S_AXI_HP1_RVALID),
|
||||
.S_RREADY (S_AXI_HP1_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP1_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP1_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP1_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP1_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP1_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP1_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1),
|
||||
.WR_DATA (net_wr_data_hp1),
|
||||
.WR_DATA_STRB (net_wr_strb_hp1),
|
||||
.WR_ADDR (net_wr_addr_hp1),
|
||||
.WR_BYTES (net_wr_bytes_hp1),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1),
|
||||
.WR_QOS (net_wr_qos_hp1),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp1),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp1),
|
||||
.RD_ADDR (net_rd_addr_hp1),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp1),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp1),
|
||||
.RD_BYTES (net_rd_bytes_hp1),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1),
|
||||
.RD_QOS (net_rd_qos_hp1)
|
||||
|
||||
);
|
||||
|
||||
/* AXI Slave HP2 */
|
||||
processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP2, // enable
|
||||
axi_hp2_name, // name
|
||||
C_S_AXI_HP2_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP2_BASEADDR, // slave base address
|
||||
C_S_AXI_HP2_HIGHADDR, // SLave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn),
|
||||
.S_ACLK (S_AXI_HP2_ACLK),
|
||||
// Write Address channel
|
||||
.S_AWID (S_AXI_HP2_AWID),
|
||||
.S_AWADDR (S_AXI_HP2_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP2_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP2_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP2_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP2_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP2_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP2_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP2_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP2_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP2_WID),
|
||||
.S_WDATA (S_AXI_HP2_WDATA),
|
||||
.S_WSTRB (S_AXI_HP2_WSTRB),
|
||||
.S_WLAST (S_AXI_HP2_WLAST),
|
||||
.S_WVALID (S_AXI_HP2_WVALID),
|
||||
.S_WREADY (S_AXI_HP2_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP2_BID),
|
||||
.S_BRESP (S_AXI_HP2_BRESP),
|
||||
.S_BVALID (S_AXI_HP2_BVALID),
|
||||
.S_BREADY (S_AXI_HP2_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP2_ARID),
|
||||
.S_ARADDR (S_AXI_HP2_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP2_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP2_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP2_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP2_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP2_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP2_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP2_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP2_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP2_RID),
|
||||
.S_RDATA (S_AXI_HP2_RDATA),
|
||||
.S_RRESP (S_AXI_HP2_RRESP),
|
||||
.S_RLAST (S_AXI_HP2_RLAST),
|
||||
.S_RVALID (S_AXI_HP2_RVALID),
|
||||
.S_RREADY (S_AXI_HP2_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP2_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP2_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP2_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP2_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP2_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP2_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2),
|
||||
.WR_DATA (net_wr_data_hp2),
|
||||
.WR_DATA_STRB (net_wr_strb_hp2),
|
||||
.WR_ADDR (net_wr_addr_hp2),
|
||||
.WR_BYTES (net_wr_bytes_hp2),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp2),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp2),
|
||||
.WR_QOS (net_wr_qos_hp2),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp2),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp2),
|
||||
.RD_ADDR (net_rd_addr_hp2),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp2),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp2),
|
||||
.RD_BYTES (net_rd_bytes_hp2),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2),
|
||||
.RD_QOS (net_rd_qos_hp2)
|
||||
|
||||
);
|
||||
|
||||
/* AXI Slave HP3 */
|
||||
processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP3, // enable
|
||||
axi_hp3_name, // name
|
||||
C_S_AXI_HP3_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP3_BASEADDR, // slave base address
|
||||
C_S_AXI_HP3_HIGHADDR, // SLave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn),
|
||||
.S_ACLK (S_AXI_HP3_ACLK),
|
||||
// Write ADDRESS CHANNEL
|
||||
.S_AWID (S_AXI_HP3_AWID),
|
||||
.S_AWADDR (S_AXI_HP3_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP3_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP3_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP3_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP3_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP3_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP3_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP3_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP3_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP3_WID),
|
||||
.S_WDATA (S_AXI_HP3_WDATA),
|
||||
.S_WSTRB (S_AXI_HP3_WSTRB),
|
||||
.S_WLAST (S_AXI_HP3_WLAST),
|
||||
.S_WVALID (S_AXI_HP3_WVALID),
|
||||
.S_WREADY (S_AXI_HP3_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP3_BID),
|
||||
.S_BRESP (S_AXI_HP3_BRESP),
|
||||
.S_BVALID (S_AXI_HP3_BVALID),
|
||||
.S_BREADY (S_AXI_HP3_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP3_ARID),
|
||||
.S_ARADDR (S_AXI_HP3_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP3_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP3_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP3_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP3_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP3_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP3_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP3_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP3_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP3_RID),
|
||||
.S_RDATA (S_AXI_HP3_RDATA),
|
||||
.S_RRESP (S_AXI_HP3_RRESP),
|
||||
.S_RLAST (S_AXI_HP3_RLAST),
|
||||
.S_RVALID (S_AXI_HP3_RVALID),
|
||||
.S_RREADY (S_AXI_HP3_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP3_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP3_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP3_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP3_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP3_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP3_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3),
|
||||
.WR_DATA (net_wr_data_hp3),
|
||||
.WR_DATA_STRB (net_wr_strb_hp3),
|
||||
.WR_ADDR (net_wr_addr_hp3),
|
||||
.WR_BYTES (net_wr_bytes_hp3),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp3),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp3),
|
||||
.WR_QOS (net_wr_qos_hp3),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp3),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp3),
|
||||
.RD_ADDR (net_rd_addr_hp3),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp3),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp3),
|
||||
.RD_BYTES (net_rd_bytes_hp3),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3),
|
||||
.RD_QOS (net_rd_qos_hp3)
|
||||
);
|
||||
+244
@@ -0,0 +1,244 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_local_params.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Parameters used in Zynq VIP
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/* local */
|
||||
parameter m_axi_gp0_baseaddr = 32'h4000_0000;
|
||||
parameter m_axi_gp1_baseaddr = 32'h8000_0000;
|
||||
parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF;
|
||||
parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF;
|
||||
|
||||
parameter addr_width = 32; // maximum address width
|
||||
parameter data_width = 32; // maximum data width.
|
||||
parameter max_chars = 128; // max characters for file name
|
||||
parameter mem_width = data_width/8; /// memory width in bytes
|
||||
parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted
|
||||
parameter int_width = 32; //integre width
|
||||
|
||||
/* for internal read/write APIs used for data transfers */
|
||||
parameter max_burst_len = 16; /// maximum brst length on axi
|
||||
parameter max_data_width = 64; // maximum data width for internal AXI bursts
|
||||
parameter max_burst_bits = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts
|
||||
parameter max_burst_bytes = (max_burst_bits)/8; // maximum data bytes in each transfer
|
||||
parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts
|
||||
|
||||
parameter max_registers = 32;
|
||||
parameter max_regs_width = clogb2(max_registers);
|
||||
|
||||
parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11;
|
||||
|
||||
/* Interrupt bits supported */
|
||||
parameter irq_width = 16;
|
||||
|
||||
/* GP Master0 & Master1 address decode */
|
||||
parameter GP_M0 = 2'b01;
|
||||
parameter GP_M1 = 2'b10;
|
||||
|
||||
parameter ALL_RANDOM= 2'b00;
|
||||
parameter ALL_ZEROS = 2'b01;
|
||||
parameter ALL_ONES = 2'b10;
|
||||
|
||||
parameter ddr_start_addr = 32'h0008_0000;
|
||||
parameter ddr_end_addr = 32'h7FFF_FFFF;
|
||||
|
||||
parameter ocm_start_addr = 32'h0000_0000;
|
||||
parameter ocm_end_addr = 32'h0003_FFFF;
|
||||
parameter high_ocm_start_addr = 32'hFFFC_0000;
|
||||
parameter high_ocm_end_addr = 32'hFFFF_FFFF;
|
||||
parameter ocm_low_addr = 32'hFFFF_0000;
|
||||
|
||||
parameter reg_start_addr = 32'hE000_0000;
|
||||
parameter reg_end_addr = 32'hF8F0_2F80;
|
||||
|
||||
|
||||
/* for Master port APIs and AXI protocol related signal widths*/
|
||||
parameter axi_burst_len = 16;
|
||||
parameter axi_len_width = clogb2(axi_burst_len);
|
||||
parameter axi_size_width = 3;
|
||||
parameter axi_brst_type_width = 2;
|
||||
parameter axi_lock_width = 2;
|
||||
parameter axi_cache_width = 4;
|
||||
parameter axi_prot_width = 3;
|
||||
parameter axi_rsp_width = 2;
|
||||
parameter axi_mgp_data_width = 32;
|
||||
parameter axi_mgp_id_width = 12;
|
||||
parameter axi_mgp_outstanding = 8;
|
||||
parameter axi_mgp_wr_id = 12'hC00;
|
||||
parameter axi_mgp_rd_id = 12'hC0C;
|
||||
parameter axi_mgp0_name = "M_AXI_GP0";
|
||||
parameter axi_mgp1_name = "M_AXI_GP1";
|
||||
parameter axi_qos_width = 4;
|
||||
parameter max_transfer_bytes = 256; // For Master APIs.
|
||||
parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs.
|
||||
|
||||
|
||||
/* for GP slave ports*/
|
||||
parameter axi_sgp_data_width = 32;
|
||||
parameter axi_sgp_id_width = 6;
|
||||
parameter axi_sgp_rd_outstanding = 8;
|
||||
parameter axi_sgp_wr_outstanding = 8;
|
||||
parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding;
|
||||
parameter axi_sgp0_name = "S_AXI_GP0";
|
||||
parameter axi_sgp1_name = "S_AXI_GP1";
|
||||
|
||||
/* for ACP slave ports*/
|
||||
parameter axi_acp_data_width = 64;
|
||||
parameter axi_acp_id_width = 3;
|
||||
parameter axi_acp_rd_outstanding = 7;
|
||||
parameter axi_acp_wr_outstanding = 3;
|
||||
parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding;
|
||||
parameter axi_acp_name = "S_AXI_ACP";
|
||||
|
||||
/* for HP slave ports*/
|
||||
parameter axi_hp_id_width = 6;
|
||||
parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT ..
|
||||
parameter axi_hp0_name = "S_AXI_HP0";
|
||||
parameter axi_hp1_name = "S_AXI_HP1";
|
||||
parameter axi_hp2_name = "S_AXI_HP2";
|
||||
parameter axi_hp3_name = "S_AXI_HP3";
|
||||
|
||||
|
||||
parameter axi_slv_excl_support = 0; // For Slave ports EXCL access is not supported
|
||||
parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported
|
||||
|
||||
/* AXI transfer types */
|
||||
parameter AXI_FIXED = 2'b00;
|
||||
parameter AXI_INCR = 2'b01;
|
||||
parameter AXI_WRAP = 2'b10;
|
||||
|
||||
/* Exclusive Access */
|
||||
parameter AXI_NRML = 2'b00;
|
||||
parameter AXI_EXCL = 2'b01;
|
||||
parameter AXI_LOCK = 2'b10;
|
||||
|
||||
/* AXI Response types */
|
||||
parameter AXI_OK = 2'b00;
|
||||
parameter AXI_EXCL_OK = 2'b01;
|
||||
parameter AXI_SLV_ERR = 2'b10;
|
||||
parameter AXI_DEC_ERR = 2'b11;
|
||||
|
||||
function automatic integer clogb2;
|
||||
input [31:0] value;
|
||||
begin
|
||||
value = value - 1;
|
||||
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
|
||||
value = value >> 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* needed only for AFI modules and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */
|
||||
/* WR FIFO data */
|
||||
// parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
|
||||
// parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
|
||||
// parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1);
|
||||
// parameter wr_bytes_lsb = 0;
|
||||
// parameter wr_bytes_msb = max_burst_bytes_width;
|
||||
// parameter wr_addr_lsb = wr_bytes_msb + 1;
|
||||
// parameter wr_addr_msb = wr_addr_lsb + addr_width-1;
|
||||
// parameter wr_data_lsb = wr_addr_msb + 1;
|
||||
// parameter wr_data_msb = wr_data_lsb + max_burst_bits-1;
|
||||
// parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1;
|
||||
// parameter wr_qos_lsb = wr_data_msb + 1;
|
||||
// `parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1;
|
||||
|
||||
/* WR AFI FIFO data */
|
||||
/* ID - 1071:1066
|
||||
Resp - 1065:1064
|
||||
data - 1063:40
|
||||
address - 39:8
|
||||
valid_bytes - 7:0
|
||||
*/
|
||||
// parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1);
|
||||
// parameter wr_afi_bytes_lsb = 0;
|
||||
// parameter wr_afi_bytes_msb = max_burst_bytes_width;
|
||||
// parameter wr_afi_addr_lsb = wr_afi_bytes_msb + 1;
|
||||
// parameter wr_afi_addr_msb = wr_afi_addr_lsb + addr_width-1;
|
||||
// parameter wr_afi_data_lsb = wr_afi_addr_msb + 1;
|
||||
// parameter wr_afi_rsp_msb = wr_afi_rsp_lsb + axi_rsp_width-1;
|
||||
// parameter wr_afi_id_lsb = wr_afi_rsp_msb + 1;
|
||||
// parameter wr_afi_id_msb = wr_afi_id_lsb + axi_hp_id_width-1;
|
||||
// parameter wr_afi_ln_lsb = wr_afi_id_msb + 1;
|
||||
// parameter wr_afi_ln_msb = wr_afi_ln_lsb + axi_len_width-1;
|
||||
// parameter wr_afi_qos_lsb = wr_afi_ln_msb + 1;
|
||||
// parameter wr_afi_qos_msb = wr_afi_qos_lsb + axi_qos_width-1;
|
||||
|
||||
|
||||
parameter afi_fifo_size = 1024; /// AFI FIFO is stored as 1024-bytes
|
||||
parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes)
|
||||
parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location
|
||||
|
||||
/* for interconnect fifo models */
|
||||
parameter intr_max_outstanding = 8;
|
||||
parameter intr_cnt_width = clogb2(intr_max_outstanding)+1;
|
||||
parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width + axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1);
|
||||
parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ;
|
||||
|
||||
//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
|
||||
parameter rd_afi_bytes_lsb = 0;
|
||||
parameter rd_afi_bytes_msb = max_burst_bytes_width;
|
||||
parameter rd_afi_rsp_lsb = rd_afi_bytes_msb + 1;
|
||||
parameter rd_afi_rsp_msb = rd_afi_rsp_lsb + axi_rsp_width-1;
|
||||
parameter rd_afi_id_lsb = rd_afi_rsp_msb + 1;
|
||||
parameter rd_afi_id_msb = rd_afi_id_lsb + axi_hp_id_width-1;
|
||||
parameter rd_afi_ln_lsb = rd_afi_id_msb + 1;
|
||||
parameter rd_afi_ln_msb = rd_afi_ln_lsb + axi_len_width-1;
|
||||
parameter rd_afi_brst_lsb = rd_afi_ln_msb + 1;
|
||||
parameter rd_afi_brst_msb = rd_afi_brst_lsb + axi_brst_type_width-1;
|
||||
parameter rd_afi_siz_lsb = rd_afi_brst_msb + 1;
|
||||
parameter rd_afi_siz_msb = rd_afi_siz_lsb + axi_size_width-1;
|
||||
parameter rd_afi_addr_lsb = rd_afi_siz_msb + 1;
|
||||
parameter rd_afi_addr_msb = rd_afi_addr_lsb + addr_width-1;
|
||||
parameter rd_afi_data_lsb = rd_afi_addr_msb + 1;
|
||||
parameter rd_afi_data_msb = rd_afi_data_lsb + max_burst_bits-1;
|
||||
|
||||
|
||||
/* Latency types */
|
||||
parameter BEST_CASE = 0;
|
||||
parameter AVG_CASE = 1;
|
||||
parameter WORST_CASE = 2;
|
||||
parameter RANDOM_CASE = 3;
|
||||
|
||||
/* Latency Parameters ACP */
|
||||
parameter acp_wr_min = 21;
|
||||
parameter acp_wr_avg = 16;
|
||||
parameter acp_wr_max = 27;
|
||||
parameter acp_rd_min = 34;
|
||||
parameter acp_rd_avg = 125;
|
||||
parameter acp_rd_max = 130;
|
||||
|
||||
/* Latency Parameters GP */
|
||||
parameter gp_wr_min = 21;
|
||||
parameter gp_wr_avg = 16;
|
||||
parameter gp_wr_max = 46;
|
||||
parameter gp_rd_min = 38;
|
||||
parameter gp_rd_avg = 125;
|
||||
parameter gp_rd_max = 130;
|
||||
|
||||
/* Latency Parameters HP */
|
||||
parameter afi_wr_min = 37;
|
||||
parameter afi_wr_avg = 41;
|
||||
parameter afi_wr_max = 42;
|
||||
parameter afi_rd_min = 41;
|
||||
parameter afi_rd_avg = 221;
|
||||
parameter afi_rd_max = 229;
|
||||
|
||||
/* ID VALID and INVALID */
|
||||
parameter secure_access_enabled = 0;
|
||||
parameter id_invalid = 0;
|
||||
parameter id_valid = 1;
|
||||
|
||||
/* Display */
|
||||
parameter DISP_INFO = "*ZYNQ_VIP_INFO";
|
||||
parameter DISP_WARN = "*ZYNQ_VIP_WARNING";
|
||||
parameter DISP_ERR = "*ZYNQ_VIP_ERROR";
|
||||
parameter DISP_INT_INFO = "ZYNQ_VIP_INT_INFO";
|
||||
|
||||
parameter all_strb_valid = 2048'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
|
||||
|
||||
+2924
File diff suppressed because it is too large
Load Diff
+10519
File diff suppressed because it is too large
Load Diff
+433
@@ -0,0 +1,433 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_unused_ports.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Semantic checks for unused ports.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* CAN */
|
||||
assign CAN0_PHY_TX = 0;
|
||||
assign CAN1_PHY_TX = 0;
|
||||
always @(CAN0_PHY_RX or CAN1_PHY_RX)
|
||||
begin
|
||||
if(CAN0_PHY_RX | CAN1_PHY_RX)
|
||||
$display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* ETHERNET */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign ENET0_GMII_TX_EN = 0;
|
||||
assign ENET0_GMII_TX_ER = 0;
|
||||
assign ENET0_MDIO_MDC = 0;
|
||||
assign ENET0_MDIO_O = 0; /// confirm
|
||||
assign ENET0_MDIO_T = 0;
|
||||
assign ENET0_PTP_DELAY_REQ_RX = 0;
|
||||
assign ENET0_PTP_DELAY_REQ_TX = 0;
|
||||
assign ENET0_PTP_PDELAY_REQ_RX = 0;
|
||||
assign ENET0_PTP_PDELAY_REQ_TX = 0;
|
||||
assign ENET0_PTP_PDELAY_RESP_RX = 0;
|
||||
assign ENET0_PTP_PDELAY_RESP_TX = 0;
|
||||
assign ENET0_PTP_SYNC_FRAME_RX = 0;
|
||||
assign ENET0_PTP_SYNC_FRAME_TX = 0;
|
||||
assign ENET0_SOF_RX = 0;
|
||||
assign ENET0_SOF_TX = 0;
|
||||
assign ENET0_GMII_TXD = 0;
|
||||
always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or
|
||||
ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
|
||||
ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
|
||||
begin
|
||||
if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN |
|
||||
ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
|
||||
ENET0_GMII_TX_CLK | ENET0_MDIO_I )
|
||||
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign ENET1_GMII_TX_EN = 0;
|
||||
assign ENET1_GMII_TX_ER = 0;
|
||||
assign ENET1_MDIO_MDC = 0;
|
||||
assign ENET1_MDIO_O = 0;/// confirm
|
||||
assign ENET1_MDIO_T = 0;
|
||||
assign ENET1_PTP_DELAY_REQ_RX = 0;
|
||||
assign ENET1_PTP_DELAY_REQ_TX = 0;
|
||||
assign ENET1_PTP_PDELAY_REQ_RX = 0;
|
||||
assign ENET1_PTP_PDELAY_REQ_TX = 0;
|
||||
assign ENET1_PTP_PDELAY_RESP_RX = 0;
|
||||
assign ENET1_PTP_PDELAY_RESP_TX = 0;
|
||||
assign ENET1_PTP_SYNC_FRAME_RX = 0;
|
||||
assign ENET1_PTP_SYNC_FRAME_TX = 0;
|
||||
assign ENET1_SOF_RX = 0;
|
||||
assign ENET1_SOF_TX = 0;
|
||||
assign ENET1_GMII_TXD = 0;
|
||||
always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or
|
||||
ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
|
||||
ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
|
||||
begin
|
||||
if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN |
|
||||
ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
|
||||
ENET1_GMII_TX_CLK | ENET1_MDIO_I )
|
||||
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* GPIO */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign GPIO_O = 0;
|
||||
assign GPIO_T = 0;
|
||||
always@(GPIO_I)
|
||||
begin
|
||||
// if(GPIO_I !== 0)
|
||||
// $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* I2C */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign I2C0_SDA_O = 0;
|
||||
assign I2C0_SDA_T = 0;
|
||||
assign I2C0_SCL_O = 0;
|
||||
assign I2C0_SCL_T = 0;
|
||||
assign I2C1_SDA_O = 0;
|
||||
assign I2C1_SDA_T = 0;
|
||||
assign I2C1_SCL_O = 0;
|
||||
assign I2C1_SCL_T = 0;
|
||||
always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
|
||||
begin
|
||||
if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
|
||||
$display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* JTAG */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign PJTAG_TD_T = 0;
|
||||
assign PJTAG_TD_O = 0;
|
||||
always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
|
||||
begin
|
||||
if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
|
||||
$display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* SDIO */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign SDIO0_CLK = 0;
|
||||
assign SDIO0_CMD_O = 0;
|
||||
assign SDIO0_CMD_T = 0;
|
||||
assign SDIO0_DATA_O = 0;
|
||||
assign SDIO0_DATA_T = 0;
|
||||
assign SDIO0_LED = 0;
|
||||
assign SDIO0_BUSPOW = 0;
|
||||
assign SDIO0_BUSVOLT = 0;
|
||||
always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
|
||||
begin
|
||||
if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
|
||||
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign SDIO1_CLK = 0;
|
||||
assign SDIO1_CMD_O = 0;
|
||||
assign SDIO1_CMD_T = 0;
|
||||
assign SDIO1_DATA_O = 0;
|
||||
assign SDIO1_DATA_T = 0;
|
||||
assign SDIO1_LED = 0;
|
||||
assign SDIO1_BUSPOW = 0;
|
||||
assign SDIO1_BUSVOLT = 0;
|
||||
always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
|
||||
begin
|
||||
if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
|
||||
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* SPI */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign SPI0_SCLK_O = 0;
|
||||
assign SPI0_SCLK_T = 0;
|
||||
assign SPI0_MOSI_O = 0;
|
||||
assign SPI0_MOSI_T = 0;
|
||||
assign SPI0_MISO_O = 0;
|
||||
assign SPI0_MISO_T = 0;
|
||||
assign SPI0_SS_O = 0; /// confirm
|
||||
assign SPI0_SS1_O = 0;/// confirm
|
||||
assign SPI0_SS2_O = 0;/// confirm
|
||||
assign SPI0_SS_T = 0;
|
||||
always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
|
||||
begin
|
||||
if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
|
||||
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign SPI1_SCLK_O = 0;
|
||||
assign SPI1_SCLK_T = 0;
|
||||
assign SPI1_MOSI_O = 0;
|
||||
assign SPI1_MOSI_T = 0;
|
||||
assign SPI1_MISO_O = 0;
|
||||
assign SPI1_MISO_T = 0;
|
||||
assign SPI1_SS_O = 0;
|
||||
assign SPI1_SS1_O = 0;
|
||||
assign SPI1_SS2_O = 0;
|
||||
assign SPI1_SS_T = 0;
|
||||
always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
|
||||
begin
|
||||
if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
|
||||
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* UART */
|
||||
/* ------------------------------------------- */
|
||||
/// confirm
|
||||
assign UART0_DTRN = 0;
|
||||
assign UART0_RTSN = 0;
|
||||
assign UART0_TX = 0;
|
||||
always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
|
||||
begin
|
||||
if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
|
||||
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign UART1_DTRN = 0;
|
||||
assign UART1_RTSN = 0;
|
||||
assign UART1_TX = 0;
|
||||
always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
|
||||
begin
|
||||
if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
|
||||
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* TTC */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign TTC0_WAVE0_OUT = 0;
|
||||
assign TTC0_WAVE1_OUT = 0;
|
||||
assign TTC0_WAVE2_OUT = 0;
|
||||
always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
|
||||
begin
|
||||
if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
|
||||
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign TTC1_WAVE0_OUT = 0;
|
||||
assign TTC1_WAVE1_OUT = 0;
|
||||
assign TTC1_WAVE2_OUT = 0;
|
||||
always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
|
||||
begin
|
||||
if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
|
||||
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* WDT */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign WDT_RST_OUT = 0;
|
||||
always@(WDT_CLK_IN)
|
||||
begin
|
||||
if(WDT_CLK_IN)
|
||||
$display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* TRACE */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign TRACE_CTL = 0;
|
||||
assign TRACE_DATA = 0;
|
||||
always@(TRACE_CLK)
|
||||
begin
|
||||
if(TRACE_CLK)
|
||||
$display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* USB */
|
||||
/* ------------------------------------------- */
|
||||
assign USB0_PORT_INDCTL = 0;
|
||||
assign USB0_VBUS_PWRSELECT = 0;
|
||||
always@(USB0_VBUS_PWRFAULT)
|
||||
begin
|
||||
if(USB0_VBUS_PWRFAULT)
|
||||
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign USB1_PORT_INDCTL = 0;
|
||||
assign USB1_VBUS_PWRSELECT = 0;
|
||||
always@(USB1_VBUS_PWRFAULT)
|
||||
begin
|
||||
if(USB1_VBUS_PWRFAULT)
|
||||
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
always@(SRAM_INTIN)
|
||||
begin
|
||||
if(SRAM_INTIN)
|
||||
$display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* DMA */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign DMA0_DATYPE = 0;
|
||||
assign DMA0_DAVALID = 0;
|
||||
assign DMA0_DRREADY = 0;
|
||||
assign DMA0_RSTN = 0;
|
||||
always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
|
||||
begin
|
||||
if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign DMA1_DATYPE = 0;
|
||||
assign DMA1_DAVALID = 0;
|
||||
assign DMA1_DRREADY = 0;
|
||||
assign DMA1_RSTN = 0;
|
||||
always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
|
||||
begin
|
||||
if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign DMA2_DATYPE = 0;
|
||||
assign DMA2_DAVALID = 0;
|
||||
assign DMA2_DRREADY = 0;
|
||||
assign DMA2_RSTN = 0;
|
||||
always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
|
||||
begin
|
||||
if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign DMA3_DATYPE = 0;
|
||||
assign DMA3_DAVALID = 0;
|
||||
assign DMA3_DRREADY = 0;
|
||||
assign DMA3_RSTN = 0;
|
||||
always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
|
||||
begin
|
||||
if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* FTM */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign FTMT_F2P_TRIGACK = 0;
|
||||
assign FTMT_P2F_TRIG = 0;
|
||||
assign FTMT_P2F_DEBUG = 0;
|
||||
always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or
|
||||
FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
|
||||
begin
|
||||
if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
|
||||
$display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* EVENT */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign EVENT_EVENTO = 0;
|
||||
assign EVENT_STANDBYWFE = 0;
|
||||
assign EVENT_STANDBYWFI = 0;
|
||||
always@(EVENT_EVENTI)
|
||||
begin
|
||||
if(EVENT_EVENTI)
|
||||
$display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* MIO */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
always@(MIO)
|
||||
begin
|
||||
// if(MIO !== 0)
|
||||
// $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* FCLK_TRIG */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
|
||||
begin
|
||||
if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
|
||||
$display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* MISC */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
always@(FPGA_IDLE_N)
|
||||
begin
|
||||
if(FPGA_IDLE_N)
|
||||
$display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
always@(DDR_ARB)
|
||||
begin
|
||||
// if(DDR_ARB !== 0)
|
||||
// $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
|
||||
begin
|
||||
if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ)
|
||||
$display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* DDR */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign DDR_WEB = 0;
|
||||
always@(DDR_Clk or DDR_CS_n)
|
||||
begin
|
||||
if(!DDR_CS_n)
|
||||
$display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* IRQ_P2F */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign IRQ_P2F_DMAC_ABORT = 0;
|
||||
assign IRQ_P2F_DMAC0 = 0;
|
||||
assign IRQ_P2F_DMAC1 = 0;
|
||||
assign IRQ_P2F_DMAC2 = 0;
|
||||
assign IRQ_P2F_DMAC3 = 0;
|
||||
assign IRQ_P2F_DMAC4 = 0;
|
||||
assign IRQ_P2F_DMAC5 = 0;
|
||||
assign IRQ_P2F_DMAC6 = 0;
|
||||
assign IRQ_P2F_DMAC7 = 0;
|
||||
assign IRQ_P2F_SMC = 0;
|
||||
assign IRQ_P2F_QSPI = 0;
|
||||
assign IRQ_P2F_CTI = 0;
|
||||
assign IRQ_P2F_GPIO = 0;
|
||||
assign IRQ_P2F_USB0 = 0;
|
||||
assign IRQ_P2F_ENET0 = 0;
|
||||
assign IRQ_P2F_ENET_WAKE0 = 0;
|
||||
assign IRQ_P2F_SDIO0 = 0;
|
||||
assign IRQ_P2F_I2C0 = 0;
|
||||
assign IRQ_P2F_SPI0 = 0;
|
||||
assign IRQ_P2F_UART0 = 0;
|
||||
assign IRQ_P2F_CAN0 = 0;
|
||||
assign IRQ_P2F_USB1 = 0;
|
||||
assign IRQ_P2F_ENET1 = 0;
|
||||
assign IRQ_P2F_ENET_WAKE1 = 0;
|
||||
assign IRQ_P2F_SDIO1 = 0;
|
||||
assign IRQ_P2F_I2C1 = 0;
|
||||
assign IRQ_P2F_SPI1 = 0;
|
||||
assign IRQ_P2F_UART1 = 0;
|
||||
assign IRQ_P2F_CAN1 = 0;
|
||||
+13831
File diff suppressed because it is too large
Load Diff
+409
@@ -0,0 +1,409 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
|
||||
//--
|
||||
//-- This file contains confidential and proprietary information
|
||||
//-- of Xilinx, Inc. and is protected under U.S. and
|
||||
//-- international copyright and other intellectual property
|
||||
//-- laws.
|
||||
//--
|
||||
//-- DISCLAIMER
|
||||
//-- This disclaimer is not a license and does not grant any
|
||||
//-- rights to the materials distributed herewith. Except as
|
||||
//-- otherwise provided in a valid license issued to you by
|
||||
//-- Xilinx, and to the maximum extent permitted by applicable
|
||||
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
//-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
//-- including negligence, or under any other theory of
|
||||
//-- liability) for any loss or damage of any kind or nature
|
||||
//-- related to, arising under or in connection with these
|
||||
//-- materials, including for any direct, or any indirect,
|
||||
//-- special, incidental, or consequential loss or damage
|
||||
//-- (including loss of data, profits, goodwill, or any type of
|
||||
//-- loss or damage suffered as a result of any action brought
|
||||
//-- by a third party) even if such damage or loss was
|
||||
//-- reasonably foreseeable or Xilinx had been advised of the
|
||||
//-- possibility of the same.
|
||||
//--
|
||||
//-- CRITICAL APPLICATIONS
|
||||
//-- Xilinx products are not designed or intended to be fail-
|
||||
//-- safe, or for use in any application requiring fail-safe
|
||||
//-- performance, such as life-support or safety devices or
|
||||
//-- systems, Class III medical devices, nuclear facilities,
|
||||
//-- applications related to the deployment of airbags, or any
|
||||
//-- other applications that could lead to death, personal
|
||||
//-- injury, or severe property or environmental damage
|
||||
//-- (individually and collectively, "Critical
|
||||
//-- Applications"). Customer assumes the sole risk and
|
||||
//-- liability of any use of Xilinx products in Critical
|
||||
//-- Applications, subject only to applicable laws and
|
||||
//-- regulations governing limitations on product liability.
|
||||
//--
|
||||
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
//-- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: ACP Transaction Checker
|
||||
//
|
||||
// Check for optimized ACP transactions and flag if they are broken.
|
||||
//
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// atc
|
||||
// aw_atc
|
||||
// w_atc
|
||||
// b_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
module processing_system7_v5_5_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
// Width of all ADDR signals on SI and MI side of checker.
|
||||
// Range: 32.
|
||||
parameter integer C_AXI_DATA_WIDTH = 64,
|
||||
// Width of all DATA signals on SI and MI side of checker.
|
||||
// Range: 64.
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
// Width of ARUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
// Width of WUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
// Width of RUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1
|
||||
// Width of BUSER signals.
|
||||
// Range: >= 1.
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ACLK,
|
||||
input wire ARESETN,
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
|
||||
input wire [4-1:0] S_AXI_AWLEN,
|
||||
input wire [3-1:0] S_AXI_AWSIZE,
|
||||
input wire [2-1:0] S_AXI_AWBURST,
|
||||
input wire [2-1:0] S_AXI_AWLOCK,
|
||||
input wire [4-1:0] S_AXI_AWCACHE,
|
||||
input wire [3-1:0] S_AXI_AWPROT,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
|
||||
input wire S_AXI_AWVALID,
|
||||
output wire S_AXI_AWREADY,
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
|
||||
input wire S_AXI_WLAST,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
|
||||
input wire S_AXI_WVALID,
|
||||
output wire S_AXI_WREADY,
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
|
||||
output wire [2-1:0] S_AXI_BRESP,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
|
||||
output wire S_AXI_BVALID,
|
||||
input wire S_AXI_BREADY,
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
|
||||
input wire [4-1:0] S_AXI_ARLEN,
|
||||
input wire [3-1:0] S_AXI_ARSIZE,
|
||||
input wire [2-1:0] S_AXI_ARBURST,
|
||||
input wire [2-1:0] S_AXI_ARLOCK,
|
||||
input wire [4-1:0] S_AXI_ARCACHE,
|
||||
input wire [3-1:0] S_AXI_ARPROT,
|
||||
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
|
||||
input wire S_AXI_ARVALID,
|
||||
output wire S_AXI_ARREADY,
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
|
||||
output wire [2-1:0] S_AXI_RRESP,
|
||||
output wire S_AXI_RLAST,
|
||||
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
|
||||
output wire S_AXI_RVALID,
|
||||
input wire S_AXI_RREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
|
||||
output wire [4-1:0] M_AXI_AWLEN,
|
||||
output wire [3-1:0] M_AXI_AWSIZE,
|
||||
output wire [2-1:0] M_AXI_AWBURST,
|
||||
output wire [2-1:0] M_AXI_AWLOCK,
|
||||
output wire [4-1:0] M_AXI_AWCACHE,
|
||||
output wire [3-1:0] M_AXI_AWPROT,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
|
||||
output wire M_AXI_AWVALID,
|
||||
input wire M_AXI_AWREADY,
|
||||
// Master Interface Write Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
|
||||
output wire M_AXI_WLAST,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
|
||||
output wire M_AXI_WVALID,
|
||||
input wire M_AXI_WREADY,
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
|
||||
input wire [2-1:0] M_AXI_BRESP,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
|
||||
input wire M_AXI_BVALID,
|
||||
output wire M_AXI_BREADY,
|
||||
// Master Interface Read Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
|
||||
output wire [4-1:0] M_AXI_ARLEN,
|
||||
output wire [3-1:0] M_AXI_ARSIZE,
|
||||
output wire [2-1:0] M_AXI_ARBURST,
|
||||
output wire [2-1:0] M_AXI_ARLOCK,
|
||||
output wire [4-1:0] M_AXI_ARCACHE,
|
||||
output wire [3-1:0] M_AXI_ARPROT,
|
||||
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
|
||||
output wire M_AXI_ARVALID,
|
||||
input wire M_AXI_ARREADY,
|
||||
// Master Interface Read Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
|
||||
input wire [2-1:0] M_AXI_RRESP,
|
||||
input wire M_AXI_RLAST,
|
||||
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
|
||||
input wire M_AXI_RVALID,
|
||||
output wire M_AXI_RREADY,
|
||||
|
||||
output wire ERROR_TRIGGER,
|
||||
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
localparam C_FIFO_DEPTH_LOG = 4;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Internal reset.
|
||||
reg ARESET;
|
||||
|
||||
// AW->W command queue signals.
|
||||
wire cmd_w_valid;
|
||||
wire cmd_w_check;
|
||||
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
|
||||
wire cmd_w_ready;
|
||||
|
||||
// W->B command queue signals.
|
||||
wire cmd_b_push;
|
||||
wire cmd_b_error;
|
||||
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
|
||||
wire cmd_b_full;
|
||||
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
|
||||
wire cmd_b_ready;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Internal Reset
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
always @ (posedge ACLK) begin
|
||||
ARESET <= !ARESETN;
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Write Channels (AW/W/B)
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Write Address Channel.
|
||||
processing_system7_v5_5_aw_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
|
||||
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
|
||||
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
|
||||
) write_addr_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (Out)
|
||||
.cmd_w_valid (cmd_w_valid),
|
||||
.cmd_w_check (cmd_w_check),
|
||||
.cmd_w_id (cmd_w_id),
|
||||
.cmd_w_ready (cmd_w_ready),
|
||||
.cmd_b_addr (cmd_b_addr),
|
||||
.cmd_b_ready (cmd_b_ready),
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
.S_AXI_AWID (S_AXI_AWID),
|
||||
.S_AXI_AWADDR (S_AXI_AWADDR),
|
||||
.S_AXI_AWLEN (S_AXI_AWLEN),
|
||||
.S_AXI_AWSIZE (S_AXI_AWSIZE),
|
||||
.S_AXI_AWBURST (S_AXI_AWBURST),
|
||||
.S_AXI_AWLOCK (S_AXI_AWLOCK),
|
||||
.S_AXI_AWCACHE (S_AXI_AWCACHE),
|
||||
.S_AXI_AWPROT (S_AXI_AWPROT),
|
||||
.S_AXI_AWUSER (S_AXI_AWUSER),
|
||||
.S_AXI_AWVALID (S_AXI_AWVALID),
|
||||
.S_AXI_AWREADY (S_AXI_AWREADY),
|
||||
|
||||
// Master Interface Write Address Port
|
||||
.M_AXI_AWID (M_AXI_AWID),
|
||||
.M_AXI_AWADDR (M_AXI_AWADDR),
|
||||
.M_AXI_AWLEN (M_AXI_AWLEN),
|
||||
.M_AXI_AWSIZE (M_AXI_AWSIZE),
|
||||
.M_AXI_AWBURST (M_AXI_AWBURST),
|
||||
.M_AXI_AWLOCK (M_AXI_AWLOCK),
|
||||
.M_AXI_AWCACHE (M_AXI_AWCACHE),
|
||||
.M_AXI_AWPROT (M_AXI_AWPROT),
|
||||
.M_AXI_AWUSER (M_AXI_AWUSER),
|
||||
.M_AXI_AWVALID (M_AXI_AWVALID),
|
||||
.M_AXI_AWREADY (M_AXI_AWREADY)
|
||||
);
|
||||
|
||||
// Write Data channel.
|
||||
processing_system7_v5_5_w_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
|
||||
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
|
||||
) write_data_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (In)
|
||||
.cmd_w_valid (cmd_w_valid),
|
||||
.cmd_w_check (cmd_w_check),
|
||||
.cmd_w_id (cmd_w_id),
|
||||
.cmd_w_ready (cmd_w_ready),
|
||||
|
||||
// Command Interface (Out)
|
||||
.cmd_b_push (cmd_b_push),
|
||||
.cmd_b_error (cmd_b_error),
|
||||
.cmd_b_id (cmd_b_id),
|
||||
.cmd_b_full (cmd_b_full),
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
.S_AXI_WID (S_AXI_WID),
|
||||
.S_AXI_WDATA (S_AXI_WDATA),
|
||||
.S_AXI_WSTRB (S_AXI_WSTRB),
|
||||
.S_AXI_WLAST (S_AXI_WLAST),
|
||||
.S_AXI_WUSER (S_AXI_WUSER),
|
||||
.S_AXI_WVALID (S_AXI_WVALID),
|
||||
.S_AXI_WREADY (S_AXI_WREADY),
|
||||
|
||||
// Master Interface Write Data Ports
|
||||
.M_AXI_WID (M_AXI_WID),
|
||||
.M_AXI_WDATA (M_AXI_WDATA),
|
||||
.M_AXI_WSTRB (M_AXI_WSTRB),
|
||||
.M_AXI_WLAST (M_AXI_WLAST),
|
||||
.M_AXI_WUSER (M_AXI_WUSER),
|
||||
.M_AXI_WVALID (M_AXI_WVALID),
|
||||
.M_AXI_WREADY (M_AXI_WREADY)
|
||||
);
|
||||
|
||||
// Write Response channel.
|
||||
processing_system7_v5_5_b_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
|
||||
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
|
||||
) write_response_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (In)
|
||||
.cmd_b_push (cmd_b_push),
|
||||
.cmd_b_error (cmd_b_error),
|
||||
.cmd_b_id (cmd_b_id),
|
||||
.cmd_b_full (cmd_b_full),
|
||||
.cmd_b_addr (cmd_b_addr),
|
||||
.cmd_b_ready (cmd_b_ready),
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
.S_AXI_BID (S_AXI_BID),
|
||||
.S_AXI_BRESP (S_AXI_BRESP),
|
||||
.S_AXI_BUSER (S_AXI_BUSER),
|
||||
.S_AXI_BVALID (S_AXI_BVALID),
|
||||
.S_AXI_BREADY (S_AXI_BREADY),
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
.M_AXI_BID (M_AXI_BID),
|
||||
.M_AXI_BRESP (M_AXI_BRESP),
|
||||
.M_AXI_BUSER (M_AXI_BUSER),
|
||||
.M_AXI_BVALID (M_AXI_BVALID),
|
||||
.M_AXI_BREADY (M_AXI_BREADY),
|
||||
|
||||
// Trigger detection
|
||||
.ERROR_TRIGGER (ERROR_TRIGGER),
|
||||
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
|
||||
);
|
||||
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Read Channels (AR/R)
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Read Address Port
|
||||
assign M_AXI_ARID = S_AXI_ARID;
|
||||
assign M_AXI_ARADDR = S_AXI_ARADDR;
|
||||
assign M_AXI_ARLEN = S_AXI_ARLEN;
|
||||
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
|
||||
assign M_AXI_ARBURST = S_AXI_ARBURST;
|
||||
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
|
||||
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
|
||||
assign M_AXI_ARPROT = S_AXI_ARPROT;
|
||||
assign M_AXI_ARUSER = S_AXI_ARUSER;
|
||||
assign M_AXI_ARVALID = S_AXI_ARVALID;
|
||||
assign S_AXI_ARREADY = M_AXI_ARREADY;
|
||||
|
||||
// Read Data Port
|
||||
assign S_AXI_RID = M_AXI_RID;
|
||||
assign S_AXI_RDATA = M_AXI_RDATA;
|
||||
assign S_AXI_RRESP = M_AXI_RRESP;
|
||||
assign S_AXI_RLAST = M_AXI_RLAST;
|
||||
assign S_AXI_RUSER = M_AXI_RUSER;
|
||||
assign S_AXI_RVALID = M_AXI_RVALID;
|
||||
assign M_AXI_RREADY = S_AXI_RREADY;
|
||||
|
||||
|
||||
endmodule
|
||||
`default_nettype wire
|
||||
+298
@@ -0,0 +1,298 @@
|
||||
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: Address Write Channel for ATC
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// aw_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module processing_system7_v5_5_aw_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
// Width of all ADDR signals on SI and MI side of checker.
|
||||
// Range: 32.
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_FIFO_DEPTH_LOG = 4
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ARESET,
|
||||
input wire ACLK,
|
||||
|
||||
// Command Interface
|
||||
output reg cmd_w_valid,
|
||||
output wire cmd_w_check,
|
||||
output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
|
||||
input wire cmd_w_ready,
|
||||
input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
|
||||
input wire cmd_b_ready,
|
||||
|
||||
// Slave Interface Write Address Port
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
|
||||
input wire [4-1:0] S_AXI_AWLEN,
|
||||
input wire [3-1:0] S_AXI_AWSIZE,
|
||||
input wire [2-1:0] S_AXI_AWBURST,
|
||||
input wire [2-1:0] S_AXI_AWLOCK,
|
||||
input wire [4-1:0] S_AXI_AWCACHE,
|
||||
input wire [3-1:0] S_AXI_AWPROT,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
|
||||
input wire S_AXI_AWVALID,
|
||||
output wire S_AXI_AWREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
|
||||
output wire [4-1:0] M_AXI_AWLEN,
|
||||
output wire [3-1:0] M_AXI_AWSIZE,
|
||||
output wire [2-1:0] M_AXI_AWBURST,
|
||||
output wire [2-1:0] M_AXI_AWLOCK,
|
||||
output wire [4-1:0] M_AXI_AWCACHE,
|
||||
output wire [3-1:0] M_AXI_AWPROT,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
|
||||
output wire M_AXI_AWVALID,
|
||||
input wire M_AXI_AWREADY
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Constants for burst types.
|
||||
localparam [2-1:0] C_FIX_BURST = 2'b00;
|
||||
localparam [2-1:0] C_INCR_BURST = 2'b01;
|
||||
localparam [2-1:0] C_WRAP_BURST = 2'b10;
|
||||
|
||||
// Constants for size.
|
||||
localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011;
|
||||
|
||||
// Constants for length.
|
||||
localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011;
|
||||
|
||||
// Constants for cacheline address.
|
||||
localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0;
|
||||
|
||||
// Command FIFO settings
|
||||
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
|
||||
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Variables for generating parameter controlled instances.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
integer index;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Transaction properties.
|
||||
wire access_is_incr;
|
||||
wire access_is_wrap;
|
||||
wire access_is_coherent;
|
||||
wire access_optimized_size;
|
||||
wire incr_addr_boundary;
|
||||
wire incr_is_optimized;
|
||||
wire wrap_is_optimized;
|
||||
wire access_is_optimized;
|
||||
|
||||
// Command FIFO.
|
||||
wire cmd_w_push;
|
||||
reg cmd_full;
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
|
||||
wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr;
|
||||
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Decode:
|
||||
//
|
||||
// Detect if transaction is of correct typ, size and length to qualify as
|
||||
// an optimized transaction that has to be checked for errors.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Transaction burst type.
|
||||
assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST );
|
||||
assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST );
|
||||
|
||||
// Transaction has to be Coherent.
|
||||
assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) &
|
||||
( S_AXI_AWCACHE[1] == 1'b1 );
|
||||
|
||||
// Transaction cacheline boundary address.
|
||||
assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET );
|
||||
|
||||
// Transaction length & size.
|
||||
assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) &
|
||||
( S_AXI_AWLEN == C_OPTIMIZED_LEN );
|
||||
|
||||
// Transaction is optimized.
|
||||
assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary;
|
||||
assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size;
|
||||
assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized );
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Command FIFO:
|
||||
//
|
||||
// Since supported write interleaving is only 1, it is safe to use only a
|
||||
// simple SRL based FIFO as a command queue.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Determine when transaction infromation is pushed to the FIFO.
|
||||
assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full;
|
||||
|
||||
// SRL FIFO Pointer.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
end else begin
|
||||
if ( cmd_w_push & ~cmd_w_ready ) begin
|
||||
addr_ptr <= addr_ptr + 1;
|
||||
end else if ( ~cmd_w_push & cmd_w_ready ) begin
|
||||
addr_ptr <= addr_ptr - 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Total number of buffered commands.
|
||||
assign all_addr_ptr = addr_ptr + cmd_b_addr + 2;
|
||||
|
||||
// FIFO Flags.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
cmd_full <= 1'b0;
|
||||
cmd_w_valid <= 1'b0;
|
||||
end else begin
|
||||
if ( cmd_w_push & ~cmd_w_ready ) begin
|
||||
cmd_w_valid <= 1'b1;
|
||||
end else if ( ~cmd_w_push & cmd_w_ready ) begin
|
||||
cmd_w_valid <= ( addr_ptr != 0 );
|
||||
end
|
||||
if ( cmd_w_push & ~cmd_b_ready ) begin
|
||||
// Going to full.
|
||||
cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 );
|
||||
end else if ( ~cmd_w_push & cmd_b_ready ) begin
|
||||
// Pop in middle of queue doesn't affect full status.
|
||||
cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 );
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Infere SRL for storage.
|
||||
always @ (posedge ACLK) begin
|
||||
if ( cmd_w_push ) begin
|
||||
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
|
||||
data_srl[index+1] <= data_srl[index];
|
||||
end
|
||||
data_srl[0] <= {access_is_optimized, S_AXI_AWID};
|
||||
end
|
||||
end
|
||||
|
||||
// Get current transaction info.
|
||||
assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr];
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Throttling:
|
||||
//
|
||||
// Stall commands if FIFO is full.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Propagate masked valid.
|
||||
assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full;
|
||||
|
||||
// Return ready with push back.
|
||||
assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Address Write propagation:
|
||||
//
|
||||
// All information is simply forwarded on from the SI- to MI-Side untouched.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// 1:1 mapping.
|
||||
assign M_AXI_AWID = S_AXI_AWID;
|
||||
assign M_AXI_AWADDR = S_AXI_AWADDR;
|
||||
assign M_AXI_AWLEN = S_AXI_AWLEN;
|
||||
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
|
||||
assign M_AXI_AWBURST = S_AXI_AWBURST;
|
||||
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
|
||||
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
|
||||
assign M_AXI_AWPROT = S_AXI_AWPROT;
|
||||
assign M_AXI_AWUSER = S_AXI_AWUSER;
|
||||
|
||||
|
||||
endmodule
|
||||
+413
@@ -0,0 +1,413 @@
|
||||
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: Write Response Channel for ATC
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// b_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module processing_system7_v5_5_b_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_FIFO_DEPTH_LOG = 4
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ARESET,
|
||||
input wire ACLK,
|
||||
|
||||
// Command Interface
|
||||
input wire cmd_b_push,
|
||||
input wire cmd_b_error,
|
||||
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
|
||||
output wire cmd_b_ready,
|
||||
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
|
||||
output reg cmd_b_full,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
|
||||
output reg [2-1:0] S_AXI_BRESP,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
|
||||
output wire S_AXI_BVALID,
|
||||
input wire S_AXI_BREADY,
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
|
||||
input wire [2-1:0] M_AXI_BRESP,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
|
||||
input wire M_AXI_BVALID,
|
||||
output wire M_AXI_BREADY,
|
||||
|
||||
// Trigger detection
|
||||
output reg ERROR_TRIGGER,
|
||||
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Constants for packing levels.
|
||||
localparam [2-1:0] C_RESP_OKAY = 2'b00;
|
||||
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
|
||||
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
|
||||
localparam [2-1:0] C_RESP_DECERR = 2'b11;
|
||||
|
||||
// Command FIFO settings
|
||||
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
|
||||
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Variables for generating parameter controlled instances.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
integer index;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Command Queue.
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
|
||||
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
|
||||
reg cmd_b_valid;
|
||||
wire cmd_b_ready_i;
|
||||
wire inject_error;
|
||||
wire [C_AXI_ID_WIDTH-1:0] current_id;
|
||||
|
||||
// Search command.
|
||||
wire found_match;
|
||||
wire use_match;
|
||||
wire matching_id;
|
||||
|
||||
// Manage valid command.
|
||||
wire write_valid_cmd;
|
||||
reg [C_FIFO_DEPTH-2:0] valid_cmd;
|
||||
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
|
||||
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
|
||||
|
||||
// Pipelined data
|
||||
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
|
||||
reg [2-1:0] M_AXI_BRESP_I;
|
||||
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
|
||||
reg M_AXI_BVALID_I;
|
||||
wire M_AXI_BREADY_I;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Command Queue:
|
||||
//
|
||||
// Keep track of depth of Queue to generate full flag.
|
||||
//
|
||||
// Also generate valid to mark pressence of commands in Queue.
|
||||
//
|
||||
// Maintain Queue and extract data from currently searched entry.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// SRL FIFO Pointer.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
end else begin
|
||||
if ( cmd_b_push & ~cmd_b_ready_i ) begin
|
||||
// Pushing data increase length/addr.
|
||||
addr_ptr <= addr_ptr + 1;
|
||||
end else if ( cmd_b_ready_i ) begin
|
||||
// Collapse addr when data is popped.
|
||||
addr_ptr <= collapsed_addr_ptr;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// FIFO Flags.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
cmd_b_full <= 1'b0;
|
||||
cmd_b_valid <= 1'b0;
|
||||
end else begin
|
||||
if ( cmd_b_push & ~cmd_b_ready_i ) begin
|
||||
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
|
||||
cmd_b_valid <= 1'b1;
|
||||
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
|
||||
cmd_b_full <= 1'b0;
|
||||
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Infere SRL for storage.
|
||||
always @ (posedge ACLK) begin
|
||||
if ( cmd_b_push ) begin
|
||||
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
|
||||
data_srl[index+1] <= data_srl[index];
|
||||
end
|
||||
data_srl[0] <= {cmd_b_error, cmd_b_id};
|
||||
end
|
||||
end
|
||||
|
||||
// Get current transaction info.
|
||||
assign {inject_error, current_id} = data_srl[search_addr_ptr];
|
||||
|
||||
// Assign outputs.
|
||||
assign cmd_b_addr = collapsed_addr_ptr;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Search Command Queue:
|
||||
//
|
||||
// Search for matching valid command in queue.
|
||||
//
|
||||
// A command is found when an valid entry with correct ID is found. The queue
|
||||
// is search from the oldest entry, i.e. from a high value.
|
||||
// When new commands are pushed the search address has to be updated to always
|
||||
// start the search from the oldest available.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Handle search addr.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
end else begin
|
||||
if ( cmd_b_ready_i ) begin
|
||||
// Collapse addr when data is popped.
|
||||
search_addr_ptr <= collapsed_addr_ptr;
|
||||
|
||||
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
|
||||
// Skip non valid command.
|
||||
search_addr_ptr <= search_addr_ptr - 1;
|
||||
|
||||
end else if ( cmd_b_push ) begin
|
||||
search_addr_ptr <= search_addr_ptr + 1;
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Check if searched command is valid and match ID (for existing response on MI side).
|
||||
assign matching_id = ( M_AXI_BID_I == current_id );
|
||||
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
|
||||
assign use_match = found_match & S_AXI_BREADY;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Track Used Commands:
|
||||
//
|
||||
// Actions that affect Valid Command:
|
||||
// * When a new command is pushed
|
||||
// => Shift valid vector one step
|
||||
// * When a command is used
|
||||
// => Clear corresponding valid bit
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Valid command status is updated when a command is used or a new one is pushed.
|
||||
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
|
||||
|
||||
// Update the used command valid bit.
|
||||
always @ *
|
||||
begin
|
||||
updated_valid_cmd = valid_cmd;
|
||||
updated_valid_cmd[search_addr_ptr] = ~use_match;
|
||||
end
|
||||
|
||||
// Shift valid vector when command is pushed.
|
||||
always @ *
|
||||
begin
|
||||
if ( cmd_b_push ) begin
|
||||
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
|
||||
end else begin
|
||||
next_valid_cmd = updated_valid_cmd;
|
||||
end
|
||||
end
|
||||
|
||||
// Valid signals for next cycle.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
|
||||
end else if ( write_valid_cmd ) begin
|
||||
valid_cmd <= next_valid_cmd;
|
||||
end
|
||||
end
|
||||
|
||||
// Detect oldest available command in Queue.
|
||||
always @ *
|
||||
begin
|
||||
// Default to empty.
|
||||
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
|
||||
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
|
||||
if ( next_valid_cmd[index] ) begin
|
||||
collapsed_addr_ptr = index;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Pipe incoming data:
|
||||
//
|
||||
// The B channel is piped to improve timing and avoid impact in search
|
||||
// mechanism due to late arriving signals.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Clock data.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
|
||||
M_AXI_BRESP_I <= 2'b00;
|
||||
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
|
||||
M_AXI_BVALID_I <= 1'b0;
|
||||
end else begin
|
||||
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
|
||||
M_AXI_BVALID_I <= 1'b0;
|
||||
end
|
||||
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
|
||||
M_AXI_BID_I <= M_AXI_BID;
|
||||
M_AXI_BRESP_I <= M_AXI_BRESP;
|
||||
M_AXI_BUSER_I <= M_AXI_BUSER;
|
||||
M_AXI_BVALID_I <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Generate ready to get new transaction.
|
||||
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Inject Error:
|
||||
//
|
||||
// BRESP is modified according to command information.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Inject error in response.
|
||||
always @ *
|
||||
begin
|
||||
if ( inject_error ) begin
|
||||
S_AXI_BRESP = C_RESP_SLVERROR;
|
||||
end else begin
|
||||
S_AXI_BRESP = M_AXI_BRESP_I;
|
||||
end
|
||||
end
|
||||
|
||||
// Handle interrupt generation.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
ERROR_TRIGGER <= 1'b0;
|
||||
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
|
||||
end else begin
|
||||
if ( inject_error & cmd_b_ready_i ) begin
|
||||
ERROR_TRIGGER <= 1'b1;
|
||||
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
|
||||
end else begin
|
||||
ERROR_TRIGGER <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Throttling:
|
||||
//
|
||||
// Response is passed forward when a matching entry has been found in queue.
|
||||
// Both ready and valid are set when the command is completed.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Propagate masked valid.
|
||||
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
|
||||
|
||||
// Return ready with push back.
|
||||
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
|
||||
|
||||
// Command has been handled.
|
||||
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
|
||||
assign cmd_b_ready = cmd_b_ready_i;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Write Response Propagation:
|
||||
//
|
||||
// All information is simply forwarded on from MI- to SI-Side untouched.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// 1:1 mapping.
|
||||
assign S_AXI_BID = M_AXI_BID_I;
|
||||
assign S_AXI_BUSER = M_AXI_BUSER_I;
|
||||
|
||||
|
||||
endmodule
|
||||
+310
@@ -0,0 +1,310 @@
|
||||
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
// Filename: trace_buffer.v
|
||||
// Description: Trace port buffer
|
||||
//-----------------------------------------------------------------------------
|
||||
// Structure: This section shows the hierarchical structure of
|
||||
// pss_wrapper.
|
||||
//
|
||||
// --processing_system7
|
||||
// |
|
||||
// --trace_buffer
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
module processing_system7_v5_5_trace_buffer #
|
||||
(
|
||||
parameter integer FIFO_SIZE = 128,
|
||||
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
|
||||
parameter integer C_DELAY_CLKS = 12
|
||||
)
|
||||
(
|
||||
input wire TRACE_CLK,
|
||||
input wire RST,
|
||||
input wire TRACE_VALID_IN,
|
||||
input wire [3:0] TRACE_ATID_IN,
|
||||
input wire [31:0] TRACE_DATA_IN,
|
||||
output wire TRACE_VALID_OUT,
|
||||
output wire [3:0] TRACE_ATID_OUT,
|
||||
output wire [31:0] TRACE_DATA_OUT
|
||||
);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Architecture section
|
||||
//------------------------------------------------------------
|
||||
|
||||
// function called clogb2 that returns an integer which has the
|
||||
// value of the ceiling of the log base 2.
|
||||
|
||||
function integer clogb2 (input integer bit_depth);
|
||||
integer i;
|
||||
integer temp_log;
|
||||
begin
|
||||
temp_log = 0;
|
||||
for(i=bit_depth; i > 0; i = i>>1)
|
||||
clogb2 = temp_log;
|
||||
temp_log=temp_log+1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam DEPTH = clogb2(FIFO_SIZE-1);
|
||||
|
||||
wire [31:0] reset_zeros;
|
||||
reg [31:0] trace_pedge; // write enable for FIFO
|
||||
reg [31:0] ti;
|
||||
reg [31:0] tom;
|
||||
|
||||
reg [3:0] atid;
|
||||
|
||||
reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
|
||||
|
||||
reg [4:0] dly_ctr;
|
||||
reg [DEPTH-1:0] fifo_wp;
|
||||
reg [DEPTH-1:0] fifo_rp;
|
||||
|
||||
reg fifo_re;
|
||||
wire fifo_empty;
|
||||
wire fifo_full;
|
||||
reg fifo_full_reg;
|
||||
|
||||
assign reset_zeros = 32'h0;
|
||||
|
||||
|
||||
// Pipeline Stage for Traceport ATID ports
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process pedge_ti
|
||||
// rising clock edge
|
||||
if((RST == 1'b1)) begin
|
||||
atid <= reset_zeros;
|
||||
end
|
||||
else begin
|
||||
atid <= TRACE_ATID_IN;
|
||||
end
|
||||
end
|
||||
|
||||
assign TRACE_ATID_OUT = atid;
|
||||
|
||||
/////////////////////////////////////////////
|
||||
// Generate FIFO data based on TRACE_VALID_IN
|
||||
/////////////////////////////////////////////
|
||||
generate
|
||||
if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
|
||||
/////////////////////////////////////////////
|
||||
|
||||
// memory update process
|
||||
// Update memory when positive edge detected and FIFO not full
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
|
||||
trace_fifo[fifo_wp] <= TRACE_DATA_IN;
|
||||
end
|
||||
end
|
||||
|
||||
// fifo write pointer
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process
|
||||
if(RST == 1'b1) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
else if(TRACE_VALID_IN ) begin
|
||||
if(fifo_wp == (FIFO_SIZE - 1)) begin
|
||||
if (fifo_empty) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
end
|
||||
else begin
|
||||
fifo_wp <= fifo_wp + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////
|
||||
// Generate FIFO data based on data edge
|
||||
/////////////////////////////////////////////
|
||||
end else begin : gen_data_edge_detector
|
||||
/////////////////////////////////////////////
|
||||
|
||||
|
||||
// purpose: check for pos edge on any trace input
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process pedge_ti
|
||||
// rising clock edge
|
||||
if((RST == 1'b1)) begin
|
||||
ti <= reset_zeros;
|
||||
trace_pedge <= reset_zeros;
|
||||
end
|
||||
else begin
|
||||
ti <= TRACE_DATA_IN;
|
||||
trace_pedge <= (~ti & TRACE_DATA_IN);
|
||||
//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
|
||||
// posedge only
|
||||
end
|
||||
end
|
||||
|
||||
// memory update process
|
||||
// Update memory when positive edge detected and FIFO not full
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
|
||||
trace_fifo[fifo_wp] <= trace_pedge;
|
||||
end
|
||||
end
|
||||
|
||||
// fifo write pointer
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process
|
||||
if(RST == 1'b1) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
else if(|(trace_pedge) == 1'b1) begin
|
||||
if(fifo_wp == (FIFO_SIZE - 1)) begin
|
||||
if (fifo_empty) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
end
|
||||
else begin
|
||||
fifo_wp <= fifo_wp + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
always @(posedge TRACE_CLK) begin
|
||||
tom <= trace_fifo[fifo_rp] ;
|
||||
end
|
||||
|
||||
|
||||
// // fifo write pointer
|
||||
// always @(posedge TRACE_CLK) begin
|
||||
// // process
|
||||
// if(RST == 1'b1) begin
|
||||
// fifo_wp <= {DEPTH{1'b0}};
|
||||
// end
|
||||
// else if(|(trace_pedge) == 1'b1) begin
|
||||
// if(fifo_wp == (FIFO_SIZE - 1)) begin
|
||||
// fifo_wp <= {DEPTH{1'b0}};
|
||||
// end
|
||||
// else begin
|
||||
// fifo_wp <= fifo_wp + 1;
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
// fifo read pointer update
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(RST == 1'b1) begin
|
||||
fifo_rp <= {DEPTH{1'b0}};
|
||||
fifo_re <= 1'b0;
|
||||
end
|
||||
else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
|
||||
fifo_re <= 1'b1;
|
||||
if(fifo_rp == (FIFO_SIZE - 1)) begin
|
||||
fifo_rp <= {DEPTH{1'b0}};
|
||||
end
|
||||
else begin
|
||||
fifo_rp <= fifo_rp + 1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
fifo_re <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// delay counter update
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(RST == 1'b1) begin
|
||||
dly_ctr <= 5'h0;
|
||||
end
|
||||
else if (fifo_re == 1'b1) begin
|
||||
dly_ctr <= C_DELAY_CLKS-1;
|
||||
end
|
||||
else if(dly_ctr != 5'h0) begin
|
||||
dly_ctr <= dly_ctr - 1;
|
||||
end
|
||||
end
|
||||
|
||||
// fifo empty update
|
||||
assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
|
||||
|
||||
// fifo full update
|
||||
assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
|
||||
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(RST == 1'b1) begin
|
||||
fifo_full_reg <= 1'b0;
|
||||
end
|
||||
else if (fifo_empty) begin
|
||||
fifo_full_reg <= 1'b0;
|
||||
end else begin
|
||||
fifo_full_reg <= fifo_full;
|
||||
end
|
||||
end
|
||||
|
||||
// always @(posedge TRACE_CLK) begin
|
||||
// if(RST == 1'b1) begin
|
||||
// fifo_full_reg <= 1'b0;
|
||||
// end
|
||||
// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
|
||||
// fifo_full_reg <= 1'b1;
|
||||
// end
|
||||
// else begin
|
||||
// fifo_full_reg <= 1'b0;
|
||||
// end
|
||||
// end
|
||||
//
|
||||
assign TRACE_DATA_OUT = tom;
|
||||
|
||||
assign TRACE_VALID_OUT = fifo_re;
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+244
@@ -0,0 +1,244 @@
|
||||
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: Write Channel for ATC
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// w_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module processing_system7_v5_5_w_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_DATA_WIDTH = 64,
|
||||
// Width of all DATA signals on SI and MI side of checker.
|
||||
// Range: 64.
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ARESET,
|
||||
input wire ACLK,
|
||||
|
||||
// Command Interface (In)
|
||||
input wire cmd_w_valid,
|
||||
input wire cmd_w_check,
|
||||
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
|
||||
output wire cmd_w_ready,
|
||||
|
||||
// Command Interface (Out)
|
||||
output wire cmd_b_push,
|
||||
output wire cmd_b_error,
|
||||
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
|
||||
input wire cmd_b_full,
|
||||
|
||||
// Slave Interface Write Port
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
|
||||
input wire S_AXI_WLAST,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
|
||||
input wire S_AXI_WVALID,
|
||||
output wire S_AXI_WREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
|
||||
output wire M_AXI_WLAST,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
|
||||
output wire M_AXI_WVALID,
|
||||
input wire M_AXI_WREADY
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Variables for generating parameter controlled instances.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Detecttion.
|
||||
wire any_strb_deasserted;
|
||||
wire incoming_strb_issue;
|
||||
reg first_word;
|
||||
reg strb_issue;
|
||||
|
||||
// Data flow.
|
||||
wire data_pop;
|
||||
wire cmd_b_push_blocked;
|
||||
reg cmd_b_push_i;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Detect error:
|
||||
//
|
||||
// Detect and accumulate error when a transaction shall be scanned for
|
||||
// potential issues.
|
||||
// Accumulation of error is restarted for each ne transaction.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Check stobe information
|
||||
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
|
||||
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
|
||||
|
||||
// Keep track of first word in a transaction.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
first_word <= 1'b1;
|
||||
end else if ( data_pop ) begin
|
||||
first_word <= S_AXI_WLAST;
|
||||
end
|
||||
end
|
||||
|
||||
// Keep track of error status.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
strb_issue <= 1'b0;
|
||||
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
|
||||
end else if ( data_pop ) begin
|
||||
if ( first_word ) begin
|
||||
strb_issue <= incoming_strb_issue;
|
||||
end else begin
|
||||
strb_issue <= incoming_strb_issue | strb_issue;
|
||||
end
|
||||
cmd_b_id <= cmd_w_id;
|
||||
end
|
||||
end
|
||||
|
||||
assign cmd_b_error = strb_issue;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Control command queue to B:
|
||||
//
|
||||
// Push command to B queue when all data for the transaction has flowed
|
||||
// through.
|
||||
// Delay pipelined command until there is room in the Queue.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Detect when data is popped.
|
||||
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
|
||||
|
||||
// Push command when last word in transfered (pipelined).
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
cmd_b_push_i <= 1'b0;
|
||||
end else begin
|
||||
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
|
||||
end
|
||||
end
|
||||
|
||||
// Detect if pipelined push is blocked.
|
||||
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
|
||||
|
||||
// Assign output.
|
||||
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Throttling:
|
||||
//
|
||||
// Stall commands if FIFO is full or there is no valid command information
|
||||
// from AW.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Propagate masked valid.
|
||||
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
|
||||
|
||||
// Return ready with push back.
|
||||
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
|
||||
|
||||
// End of burst.
|
||||
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Write propagation:
|
||||
//
|
||||
// All information is simply forwarded on from the SI- to MI-Side untouched.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// 1:1 mapping.
|
||||
assign M_AXI_WID = S_AXI_WID;
|
||||
assign M_AXI_WDATA = S_AXI_WDATA;
|
||||
assign M_AXI_WSTRB = S_AXI_WSTRB;
|
||||
assign M_AXI_WLAST = S_AXI_WLAST;
|
||||
assign M_AXI_WUSER = S_AXI_WUSER;
|
||||
|
||||
|
||||
endmodule
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user