rename duifei_basic to duifei_cmos_1t2r, add duifei_cmos_1t1r

2023-04-06 15:07:46 +08:00
parent 6acef7b40f
commit 53bd4d459d
1743 changed files with 4866477 additions and 114 deletions
@@ -0,0 +1,148 @@
+//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+//Date        : Thu Mar 30 16:04:58 2023
+//Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+//Command     : generate_target system_bd_wrapper.bd
+//Design      : system_bd_wrapper
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module system_bd_wrapper
+   (ddr_addr,
+    ddr_ba,
+    ddr_cas_n,
+    ddr_ck_n,
+    ddr_ck_p,
+    ddr_cke,
+    ddr_cs_n,
+    ddr_dm,
+    ddr_dq,
+    ddr_dqs_n,
+    ddr_dqs_p,
+    ddr_odt,
+    ddr_ras_n,
+    ddr_reset_n,
+    ddr_we_n,
+    fixed_io_ddr_vrn,
+    fixed_io_ddr_vrp,
+    fixed_io_mio,
+    fixed_io_ps_clk,
+    fixed_io_ps_porb,
+    fixed_io_ps_srstb,
+    gpio_i,
+    gpio_o,
+    gpio_t,
+    ps_clk_200M,
+    ps_clk_50M,
+    spi_active,
+    spi_cs,
+    spi_sclk,
+    spi_sdi,
+    spi_sdo,
+    spi_sdo_t,
+    spi_three_wire);
+  inout [14:0]ddr_addr;
+  inout [2:0]ddr_ba;
+  inout ddr_cas_n;
+  inout ddr_ck_n;
+  inout ddr_ck_p;
+  inout ddr_cke;
+  inout ddr_cs_n;
+  inout [3:0]ddr_dm;
+  inout [31:0]ddr_dq;
+  inout [3:0]ddr_dqs_n;
+  inout [3:0]ddr_dqs_p;
+  inout ddr_odt;
+  inout ddr_ras_n;
+  inout ddr_reset_n;
+  inout ddr_we_n;
+  inout fixed_io_ddr_vrn;
+  inout fixed_io_ddr_vrp;
+  inout [53:0]fixed_io_mio;
+  inout fixed_io_ps_clk;
+  inout fixed_io_ps_porb;
+  inout fixed_io_ps_srstb;
+  input [47:0]gpio_i;
+  output [47:0]gpio_o;
+  output [47:0]gpio_t;
+  output ps_clk_200M;
+  output ps_clk_50M;
+  output spi_active;
+  output [2:0]spi_cs;
+  output spi_sclk;
+  input [0:0]spi_sdi;
+  output spi_sdo;
+  output spi_sdo_t;
+  output spi_three_wire;
+
+  wire [14:0]ddr_addr;
+  wire [2:0]ddr_ba;
+  wire ddr_cas_n;
+  wire ddr_ck_n;
+  wire ddr_ck_p;
+  wire ddr_cke;
+  wire ddr_cs_n;
+  wire [3:0]ddr_dm;
+  wire [31:0]ddr_dq;
+  wire [3:0]ddr_dqs_n;
+  wire [3:0]ddr_dqs_p;
+  wire ddr_odt;
+  wire ddr_ras_n;
+  wire ddr_reset_n;
+  wire ddr_we_n;
+  wire fixed_io_ddr_vrn;
+  wire fixed_io_ddr_vrp;
+  wire [53:0]fixed_io_mio;
+  wire fixed_io_ps_clk;
+  wire fixed_io_ps_porb;
+  wire fixed_io_ps_srstb;
+  wire [47:0]gpio_i;
+  wire [47:0]gpio_o;
+  wire [47:0]gpio_t;
+  wire ps_clk_200M;
+  wire ps_clk_50M;
+  wire spi_active;
+  wire [2:0]spi_cs;
+  wire spi_sclk;
+  wire [0:0]spi_sdi;
+  wire spi_sdo;
+  wire spi_sdo_t;
+  wire spi_three_wire;
+
+  system_bd system_bd_i
+       (.ddr_addr(ddr_addr),
+        .ddr_ba(ddr_ba),
+        .ddr_cas_n(ddr_cas_n),
+        .ddr_ck_n(ddr_ck_n),
+        .ddr_ck_p(ddr_ck_p),
+        .ddr_cke(ddr_cke),
+        .ddr_cs_n(ddr_cs_n),
+        .ddr_dm(ddr_dm),
+        .ddr_dq(ddr_dq),
+        .ddr_dqs_n(ddr_dqs_n),
+        .ddr_dqs_p(ddr_dqs_p),
+        .ddr_odt(ddr_odt),
+        .ddr_ras_n(ddr_ras_n),
+        .ddr_reset_n(ddr_reset_n),
+        .ddr_we_n(ddr_we_n),
+        .fixed_io_ddr_vrn(fixed_io_ddr_vrn),
+        .fixed_io_ddr_vrp(fixed_io_ddr_vrp),
+        .fixed_io_mio(fixed_io_mio),
+        .fixed_io_ps_clk(fixed_io_ps_clk),
+        .fixed_io_ps_porb(fixed_io_ps_porb),
+        .fixed_io_ps_srstb(fixed_io_ps_srstb),
+        .gpio_i(gpio_i),
+        .gpio_o(gpio_o),
+        .gpio_t(gpio_t),
+        .ps_clk_200M(ps_clk_200M),
+        .ps_clk_50M(ps_clk_50M),
+        .spi_active(spi_active),
+        .spi_cs(spi_cs),
+        .spi_sclk(spi_sclk),
+        .spi_sdi(spi_sdi),
+        .spi_sdo(spi_sdo),
+        .spi_sdo_t(spi_sdo_t),
+        .spi_three_wire(spi_three_wire));
+endmodule