rename duifei_basic to duifei_cmos_1t2r, add duifei_cmos_1t1r

This commit is contained in:
2023-04-06 15:07:46 +08:00
parent 6acef7b40f
commit 53bd4d459d
1743 changed files with 4866477 additions and 114 deletions
@@ -0,0 +1,318 @@
{
"version": "1.0",
"modules": {
"system_bd": {
"proto_instances": {
"/axi_interconnect/M00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M00_ACLK"},
"ARADDR": { "actual": "M00_AXI_araddr[31:0]"},
"ARESETN": { "actual": "ARESETN"},
"ARPROT": { "actual": "M00_AXI_arprot[2:0]"},
"ARREADY": { "actual": "M00_AXI_arready"},
"ARVALID": { "actual": "M00_AXI_arvalid"},
"AWADDR": { "actual": "M00_AXI_awaddr[31:0]"},
"AWPROT": { "actual": "M00_AXI_awprot[2:0]"},
"AWREADY": { "actual": "M00_AXI_awready"},
"AWVALID": { "actual": "M00_AXI_awvalid"},
"BREADY": { "actual": "M00_AXI_bready"},
"BRESP": { "actual": "M00_AXI_bresp[1:0]"},
"BVALID": { "actual": "M00_AXI_bvalid"},
"RDATA": { "actual": "M00_AXI_rdata[31:0]"},
"RREADY": { "actual": "M00_AXI_rready"},
"RRESP": { "actual": "M00_AXI_rresp[1:0]"},
"RVALID": { "actual": "M00_AXI_rvalid"},
"WDATA": { "actual": "M00_AXI_wdata[31:0]"},
"WREADY": { "actual": "M00_AXI_wready"},
"WSTRB": { "actual": "M00_AXI_wstrb[3:0]"},
"WVALID": { "actual": "M00_AXI_wvalid"}
}
},
"/axi_interconnect/S00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S00_ACLK"},
"ARADDR": { "actual": "S00_AXI_araddr[31:0]"},
"ARBURST": { "actual": "S00_AXI_arburst[1:0]"},
"ARCACHE": { "actual": "S00_AXI_arcache[3:0]"},
"ARESETN": { "actual": "ARESETN"},
"ARID": { "actual": "S00_AXI_arid[11:0]"},
"ARLEN": { "actual": "S00_AXI_arlen[7:0]"},
"ARLOCK": { "actual": "S00_AXI_arlock[0:0]"},
"ARPROT": { "actual": "S00_AXI_arprot[2:0]"},
"ARQOS": { "actual": "S00_AXI_arqos[3:0]"},
"ARREADY": { "actual": "S00_AXI_arready"},
"ARSIZE": { "actual": "S00_AXI_arsize[2:0]"},
"ARVALID": { "actual": "S00_AXI_arvalid"},
"AWADDR": { "actual": "S00_AXI_awaddr[31:0]"},
"AWBURST": { "actual": "S00_AXI_awburst[1:0]"},
"AWCACHE": { "actual": "S00_AXI_awcache[3:0]"},
"AWID": { "actual": "S00_AXI_awid[11:0]"},
"AWLEN": { "actual": "S00_AXI_awlen[7:0]"},
"AWLOCK": { "actual": "S00_AXI_awlock[0:0]"},
"AWPROT": { "actual": "S00_AXI_awprot[2:0]"},
"AWQOS": { "actual": "S00_AXI_awqos[3:0]"},
"AWREADY": { "actual": "S00_AXI_awready"},
"AWSIZE": { "actual": "S00_AXI_awsize[2:0]"},
"AWVALID": { "actual": "S00_AXI_awvalid"},
"BID": { "actual": "S00_AXI_bid[11:0]"},
"BREADY": { "actual": "S00_AXI_bready"},
"BRESP": { "actual": "S00_AXI_bresp[1:0]"},
"BVALID": { "actual": "S00_AXI_bvalid"},
"RDATA": { "actual": "S00_AXI_rdata[31:0]"},
"RID": { "actual": "S00_AXI_rid[11:0]"},
"RLAST": { "actual": "S00_AXI_rlast"},
"RREADY": { "actual": "S00_AXI_rready"},
"RRESP": { "actual": "S00_AXI_rresp[1:0]"},
"RVALID": { "actual": "S00_AXI_rvalid"},
"WDATA": { "actual": "S00_AXI_wdata[31:0]"},
"WID": { "actual": "S00_AXI_wid[11:0]"},
"WLAST": { "actual": "S00_AXI_wlast"},
"WREADY": { "actual": "S00_AXI_wready"},
"WSTRB": { "actual": "S00_AXI_wstrb[3:0]"},
"WVALID": { "actual": "S00_AXI_wvalid"}
}
},
"/axi_interconnect/s00_couplers/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_ACLK"},
"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
"ARESETN": { "actual": "M_ARESETN"},
"ARPROT": { "actual": "M_AXI_arprot[2:0]"},
"ARREADY": { "actual": "M_AXI_arready"},
"ARVALID": { "actual": "M_AXI_arvalid"},
"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
"AWPROT": { "actual": "M_AXI_awprot[2:0]"},
"AWREADY": { "actual": "M_AXI_awready"},
"AWVALID": { "actual": "M_AXI_awvalid"},
"BREADY": { "actual": "M_AXI_bready"},
"BRESP": { "actual": "M_AXI_bresp[1:0]"},
"BVALID": { "actual": "M_AXI_bvalid"},
"RDATA": { "actual": "M_AXI_rdata[31:0]"},
"RREADY": { "actual": "M_AXI_rready"},
"RRESP": { "actual": "M_AXI_rresp[1:0]"},
"RVALID": { "actual": "M_AXI_rvalid"},
"WDATA": { "actual": "M_AXI_wdata[31:0]"},
"WREADY": { "actual": "M_AXI_wready"},
"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
"WVALID": { "actual": "M_AXI_wvalid"}
}
},
"/axi_interconnect/s00_couplers/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_ACLK"},
"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
"ARBURST": { "actual": "S_AXI_arburst[1:0]"},
"ARCACHE": { "actual": "S_AXI_arcache[3:0]"},
"ARESETN": { "actual": "S_ARESETN"},
"ARID": { "actual": "S_AXI_arid[11:0]"},
"ARLEN": { "actual": "S_AXI_arlen[7:0]"},
"ARLOCK": { "actual": "S_AXI_arlock[0:0]"},
"ARPROT": { "actual": "S_AXI_arprot[2:0]"},
"ARQOS": { "actual": "S_AXI_arqos[3:0]"},
"ARREADY": { "actual": "S_AXI_arready"},
"ARSIZE": { "actual": "S_AXI_arsize[2:0]"},
"ARVALID": { "actual": "S_AXI_arvalid"},
"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
"AWBURST": { "actual": "S_AXI_awburst[1:0]"},
"AWCACHE": { "actual": "S_AXI_awcache[3:0]"},
"AWID": { "actual": "S_AXI_awid[11:0]"},
"AWLEN": { "actual": "S_AXI_awlen[7:0]"},
"AWLOCK": { "actual": "S_AXI_awlock[0:0]"},
"AWPROT": { "actual": "S_AXI_awprot[2:0]"},
"AWQOS": { "actual": "S_AXI_awqos[3:0]"},
"AWREADY": { "actual": "S_AXI_awready"},
"AWSIZE": { "actual": "S_AXI_awsize[2:0]"},
"AWVALID": { "actual": "S_AXI_awvalid"},
"BID": { "actual": "S_AXI_bid[11:0]"},
"BREADY": { "actual": "S_AXI_bready"},
"BRESP": { "actual": "S_AXI_bresp[1:0]"},
"BVALID": { "actual": "S_AXI_bvalid"},
"RDATA": { "actual": "S_AXI_rdata[31:0]"},
"RID": { "actual": "S_AXI_rid[11:0]"},
"RLAST": { "actual": "S_AXI_rlast"},
"RREADY": { "actual": "S_AXI_rready"},
"RRESP": { "actual": "S_AXI_rresp[1:0]"},
"RVALID": { "actual": "S_AXI_rvalid"},
"WDATA": { "actual": "S_AXI_wdata[31:0]"},
"WID": { "actual": "S_AXI_wid[11:0]"},
"WLAST": { "actual": "S_AXI_wlast"},
"WREADY": { "actual": "S_AXI_wready"},
"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
"WVALID": { "actual": "S_AXI_wvalid"}
}
},
"/axi_interconnect/s00_couplers/auto_pc/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr"},
"ARESETN": { "actual": "aresetn"},
"ARPROT": { "actual": "m_axi_arprot"},
"ARREADY": { "actual": "m_axi_arready"},
"ARVALID": { "actual": "m_axi_arvalid"},
"AWADDR": { "actual": "m_axi_awaddr"},
"AWPROT": { "actual": "m_axi_awprot"},
"AWREADY": { "actual": "m_axi_awready"},
"AWVALID": { "actual": "m_axi_awvalid"},
"BREADY": { "actual": "m_axi_bready"},
"BRESP": { "actual": "m_axi_bresp"},
"BVALID": { "actual": "m_axi_bvalid"},
"RDATA": { "actual": "m_axi_rdata"},
"RREADY": { "actual": "m_axi_rready"},
"RRESP": { "actual": "m_axi_rresp"},
"RVALID": { "actual": "m_axi_rvalid"},
"WDATA": { "actual": "m_axi_wdata"},
"WREADY": { "actual": "m_axi_wready"},
"WSTRB": { "actual": "m_axi_wstrb"},
"WVALID": { "actual": "m_axi_wvalid"}
}
},
"/axi_interconnect/s00_couplers/auto_pc/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARBURST": { "actual": "s_axi_arburst"},
"ARCACHE": { "actual": "s_axi_arcache"},
"ARESETN": { "actual": "aresetn"},
"ARID": { "actual": "s_axi_arid"},
"ARLEN": { "actual": "s_axi_arlen"},
"ARLOCK": { "actual": "s_axi_arlock"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARQOS": { "actual": "s_axi_arqos"},
"ARREADY": { "actual": "s_axi_arready"},
"ARSIZE": { "actual": "s_axi_arsize"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWBURST": { "actual": "s_axi_awburst"},
"AWCACHE": { "actual": "s_axi_awcache"},
"AWID": { "actual": "s_axi_awid"},
"AWLEN": { "actual": "s_axi_awlen"},
"AWLOCK": { "actual": "s_axi_awlock"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWQOS": { "actual": "s_axi_awqos"},
"AWREADY": { "actual": "s_axi_awready"},
"AWSIZE": { "actual": "s_axi_awsize"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BID": { "actual": "s_axi_bid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RID": { "actual": "s_axi_rid"},
"RLAST": { "actual": "s_axi_rlast"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WID": { "actual": "s_axi_wid"},
"WLAST": { "actual": "s_axi_wlast"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_spi_engine/axi_spi_engine/s_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_spi_engine/s_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARPROT": { "actual": "s_axi_arprot"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWPROT": { "actual": "s_axi_awprot"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/ps_system/M_AXI_GP0": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_AXI_GP0_ACLK"},
"ARADDR": { "actual": "M_AXI_GP0_ARADDR"},
"ARBURST": { "actual": "M_AXI_GP0_ARBURST"},
"ARCACHE": { "actual": "M_AXI_GP0_ARCACHE"},
"ARID": { "actual": "M_AXI_GP0_ARID"},
"ARLEN": { "actual": "M_AXI_GP0_ARLEN"},
"ARLOCK": { "actual": "M_AXI_GP0_ARLOCK"},
"ARPROT": { "actual": "M_AXI_GP0_ARPROT"},
"ARQOS": { "actual": "M_AXI_GP0_ARQOS"},
"ARREADY": { "actual": "M_AXI_GP0_ARREADY"},
"ARSIZE": { "actual": "M_AXI_GP0_ARSIZE"},
"ARVALID": { "actual": "M_AXI_GP0_ARVALID"},
"AWADDR": { "actual": "M_AXI_GP0_AWADDR"},
"AWBURST": { "actual": "M_AXI_GP0_AWBURST"},
"AWCACHE": { "actual": "M_AXI_GP0_AWCACHE"},
"AWID": { "actual": "M_AXI_GP0_AWID"},
"AWLEN": { "actual": "M_AXI_GP0_AWLEN"},
"AWLOCK": { "actual": "M_AXI_GP0_AWLOCK"},
"AWPROT": { "actual": "M_AXI_GP0_AWPROT"},
"AWQOS": { "actual": "M_AXI_GP0_AWQOS"},
"AWREADY": { "actual": "M_AXI_GP0_AWREADY"},
"AWSIZE": { "actual": "M_AXI_GP0_AWSIZE"},
"AWVALID": { "actual": "M_AXI_GP0_AWVALID"},
"BID": { "actual": "M_AXI_GP0_BID"},
"BREADY": { "actual": "M_AXI_GP0_BREADY"},
"BRESP": { "actual": "M_AXI_GP0_BRESP"},
"BVALID": { "actual": "M_AXI_GP0_BVALID"},
"RDATA": { "actual": "M_AXI_GP0_RDATA"},
"RID": { "actual": "M_AXI_GP0_RID"},
"RLAST": { "actual": "M_AXI_GP0_RLAST"},
"RREADY": { "actual": "M_AXI_GP0_RREADY"},
"RRESP": { "actual": "M_AXI_GP0_RRESP"},
"RVALID": { "actual": "M_AXI_GP0_RVALID"},
"WDATA": { "actual": "M_AXI_GP0_WDATA"},
"WID": { "actual": "M_AXI_GP0_WID"},
"WLAST": { "actual": "M_AXI_GP0_WLAST"},
"WREADY": { "actual": "M_AXI_GP0_WREADY"},
"WSTRB": { "actual": "M_AXI_GP0_WSTRB"},
"WVALID": { "actual": "M_AXI_GP0_WVALID"}
}
}
}
}
}
}
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