Archived
rename duifei_basic to duifei_cmos_1t2r, add duifei_cmos_1t1r
This commit is contained in:
@@ -0,0 +1,133 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2022/11/01 11:15:25
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// Design Name:
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// Module Name: clk_dist
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description: Clock distribution module
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module clk_dist
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(
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// input clocks
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input clk_250m_p , // generated by ad9516, 250mhz
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input clk_250m_n ,
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input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
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input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
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// output clocks & reset
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// global reset
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output sys_rst , // global reset signal, active high
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output ant_rst , // phased-array & rf control reset signal, active high
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// pl signal processing clock
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output sys_clk , // 41.6667mhz
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output sys_clk_2x , // 83.3333mhz
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output sys_clk_3x , // 125mhz
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output sys_clk_4x , // 166.6667mhz
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output sys_clk_ld , // system main clock locked indicator
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// ad9361-1 clocks
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output ad9361_1_clk , // 41.6667mhz
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output ad9361_1_clk_2x , // 83.3333mhz
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output ad9361_1_clk_3x , // 125mhz
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output ad9361_1_clk_4x , // 166.6667mhz
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output ad9361_1_clk_ld , // ad9361-1 clock group locked indicator
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// ad9361-2 clocks
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output ad9361_2_clk , // 41.6667mhz
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output ad9361_2_clk_2x , // 83.3333mhz
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output ad9361_2_clk_3x , // 125mhz
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output ad9361_2_clk_4x , // 166.6667mhz
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output ad9361_2_clk_ld , // ad9361-2 clock group locked indicator
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// phased-array & rf control clocks
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output clk_96m ,
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output clk_48m ,
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output clk_32m ,
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output clk_19p2m
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);
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assign sys_clk = ad9361_1_clk ;
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assign sys_clk_2x = ad9361_1_clk_2x;
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assign sys_clk_3x = ad9361_1_clk_3x;
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assign sys_clk_4x = ad9361_1_clk_4x;
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assign sys_clk_ld = ad9361_1_clk_ld;
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assign sys_rst = ~sys_clk_ld;
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ad9361_clk_gen u_ad9361_1_clk_gen
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(
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// Clock out ports
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.clk_out1 (ad9361_1_clk ), // output clk_out1
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.clk_out2 (ad9361_1_clk_2x ), // output clk_out2
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.clk_out3 (ad9361_1_clk_3x ), // output clk_out3
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.clk_out4 (ad9361_1_clk_4x ), // output clk_out4
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// Status and control signals
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.locked (ad9361_1_clk_ld ), // output locked
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// Clock in ports
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.clk_in1 (ad9361_1_rx_data_clk ) // input clk_in1
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);
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ad9361_clk_gen u_ad9361_2_clk_gen
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(
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// Clock out ports
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.clk_out1 (ad9361_2_clk ), // output clk_out1
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.clk_out2 (ad9361_2_clk_2x ), // output clk_out2
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.clk_out3 (ad9361_2_clk_3x ), // output clk_out3
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.clk_out4 (ad9361_2_clk_4x ), // output clk_out4
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// Status and control signals
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.locked (ad9361_2_clk_ld ), // output locked
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// Clock in ports
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.clk_in1 (ad9361_2_rx_data_clk ) // input clk_in1
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);
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wire ant_clk_stg1_96m;
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wire ant_clk_stg1_ld;
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wire ant_clk_stg2_ld;
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assign ant_rst = ~ant_clk_stg2_ld;
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ant_clk_gen_stg1 u_ant_clk_gen_stg1
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(
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// Clock out ports
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.clk_out1 (ant_clk_stg1_96m ), // output clk_out1
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// Status and control signals
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.locked (ant_clk_stg1_ld ), // output locked
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// Clock in ports
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.clk_in1_p (clk_250m_p ), // input clk_in1_p
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.clk_in1_n (clk_250m_n ) // input clk_in1_n
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);
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ant_clk_gen_stg2 u_ant_clk_gen_stg2
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(
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// Clock out ports
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.clk_out1 (clk_96m ), // output clk_out1
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.clk_out2 (clk_48m ), // output clk_out2
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.clk_out3 (clk_32m ), // output clk_out3
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.clk_out4 (clk_19p2m ), // output clk_out4
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// Status and control signals
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.locked (ant_clk_stg2_ld ), // output locked
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// Clock in ports
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.clk_in1 (ant_clk_stg1_96m ) // input clk_in1
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);
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endmodule
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@@ -0,0 +1,527 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2021/12/14 15:54:11
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// Design Name:
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// Module Name: system_top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module system_top
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(
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/***************************************************************************
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* Contents
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* 01. Clocks
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* 02. HMC7044 Interface
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* 03. AD9361-1 Interface
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* 04. AD9361-2 Interface
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* 05. Phased-Array Control
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* 06. RF Synthesizer Control
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* 07. Debug IO
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* 08. DDR and Fixed-io (Do NOT Modify)
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**************************************************************************/
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// *************************************************************************
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// ******************************** Clocks *********************************
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// *************************************************************************
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// fpga logic clock
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input clk_250m_p , // generated by hmc7044, 250mhz
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input clk_250m_n ,
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// ad9361 buffered clock
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input ad9361_1_buffer_clk , // derived from ad9361 input clock
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input ad9361_2_buffer_clk , // derived from ad9361 input clock
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// *************************************************************************
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// *************************** HMC7044 Interface ***************************
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// *************************************************************************
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// spi interface
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output hmc7044_spi_clk ,
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output hmc7044_spi_csn ,
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inout hmc7044_spi_sdio ,
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// control signals
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output hmc7044_reset , // hmc7044 active-high reset signal, set to 0 in normal operation
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output hmc7044_sync , // hmc7044 multichip synchronization signal, set to 0 if not used
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// gpio
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inout [ 3:0] hmc7044_gpio ,
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// *************************************************************************
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// ************************** AD9361-1 Interface ***************************
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// *************************************************************************
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// rx data (rx channels are tied to ground physically)
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input ad9361_1_rx_data_clk, // ad9361 rx data clock, 96mhz
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input ad9361_1_rx_frame ,
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input [11:0] ad9361_1_rx_data ,
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// tx data
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output ad9361_1_tx_fb_clk ,
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output ad9361_1_tx_frame ,
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output [11:0] ad9361_1_tx_data ,
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// spi interface
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output ad9361_1_spi_clk ,
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output ad9361_1_spi_csn ,
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output ad9361_1_spi_mosi ,
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input ad9361_1_spi_miso ,
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// control signals
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output ad9361_1_reset_b , // ad9361 active-low reset control
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output ad9361_1_en_agc , // ad9361 manual agc control
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output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed)
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output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
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input [ 3:0] ad9361_1_ctrl_in ,
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output [ 7:0] ad9361_1_ctrl_out ,
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// *************************************************************************
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// ************************** AD9361-2 Interface ***************************
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// *************************************************************************
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// rx data (rx channels are tied to ground physically)
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input ad9361_2_rx_data_clk,
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input ad9361_2_rx_frame ,
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input [11:0] ad9361_2_rx_data ,
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// tx data
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output ad9361_2_tx_fb_clk ,
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output ad9361_2_tx_frame ,
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output [11:0] ad9361_2_tx_data ,
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// spi interface
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output ad9361_2_spi_clk ,
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output ad9361_2_spi_csn ,
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output ad9361_2_spi_mosi ,
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input ad9361_2_spi_miso ,
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// control signals
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output ad9361_2_reset_b , // ad9361 active-low reset control
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output ad9361_2_en_agc , // ad9361 manual agc control
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output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed)
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output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
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input [ 3:0] ad9361_2_ctrl_in ,
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output [ 7:0] ad9361_2_ctrl_out ,
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// *************************************************************************
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// ************************* Phased-Array Control **************************
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// *************************************************************************
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output ant_clk ,
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output ant_en ,
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output ant_data ,
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output ant_tr ,
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output ant_dary ,
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input ant_dout ,
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// *************************************************************************
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// ************************ RF Synthesizer Control *************************
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// *************************************************************************
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output rf_standby ,
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output rf_sw_pll ,
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output rf_t ,
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output rf_r ,
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output rf_sw_bpf ,
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output rf_sclk1 ,
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output rf_sdio1 ,
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output rf_cs1 ,
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input rf_ld1 ,
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output rf_sclk2 ,
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output rf_sdio2 ,
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output rf_cs2 ,
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input rf_ld2 ,
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output rf_sclk3 ,
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output rf_sdio3 ,
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output rf_cs3 ,
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input rf_ld3 ,
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output rf_tmgc_16 ,
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output rf_tmgc_8 ,
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output rf_tmgc_4 ,
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output rf_tmgc_2 ,
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output rf_tmgc_1 ,
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output rf_rmgc_16 ,
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output rf_rmgc_8 ,
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output rf_rmgc_4 ,
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output rf_rmgc_2 ,
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output rf_rmgc_1 ,
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output rf_enable ,
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output rf_sc ,
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output rf_sd ,
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output rf_endsyn ,
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input rf_sdout ,
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inout rf_dq_wd ,
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output rf_sw_rx ,
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// *************************************************************************
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// ******************************* Debug IO ********************************
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// *************************************************************************
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// 3.3v ports
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output uart1_txd ,
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input uart1_rxd ,
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output uart2_txd ,
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input uart2_rxd ,
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output uart3_txd ,
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input uart3_rxd ,
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// 1.8v ports
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inout debug_io_1 ,
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inout debug_io_2 ,
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// 3.3v ports
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inout debug_io_3 ,
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inout debug_io_4 ,
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inout debug_io_5 ,
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inout debug_io_6 ,
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inout debug_io_7 ,
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// *************************************************************************
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// ******************* DDR and Fixed-io (Do NOT Modify) ********************
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// *************************************************************************
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// ddr
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inout [14:0] ddr_addr ,
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inout [ 2:0] ddr_ba ,
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inout ddr_cas_n ,
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inout ddr_ck_n ,
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inout ddr_ck_p ,
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inout ddr_cke ,
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inout ddr_cs_n ,
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inout [ 3:0] ddr_dm ,
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inout [31:0] ddr_dq ,
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inout [ 3:0] ddr_dqs_n ,
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inout [ 3:0] ddr_dqs_p ,
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inout ddr_odt ,
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inout ddr_ras_n ,
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inout ddr_reset_n ,
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inout ddr_we_n ,
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// fixed-io
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inout fixed_io_ddr_vrn ,
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inout fixed_io_ddr_vrp ,
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inout [53:0] fixed_io_mio ,
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inout fixed_io_ps_clk ,
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inout fixed_io_ps_porb ,
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inout fixed_io_ps_srstb
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);
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////////////////////////////////////////////////////////////////////////////////
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/////////////////////////// System Clock Generation ////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// global reset
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wire sys_rst ; // global reset signal, active high
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wire ant_rst ; // phased-array & rf control reset signal, active high
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// pl signal processing clock
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wire sys_clk ; // 48MHz 41.6667MHz
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wire sys_clk_2x ; // 96MHz 83.3333MHz
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wire sys_clk_3x ; // 144MHz 125MHz
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wire sys_clk_4x ; // 192MHz 166.6667MHz
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wire sys_clk_ld ; // system main clock locked indicator
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// ad9361-1 clocks
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wire ad9361_1_clk ; // 48MHz 41.6667MHz
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wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz
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wire ad9361_1_clk_3x ; // 144MHz 125MHz
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wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz
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wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator
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// ad9361-2 clocks
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wire ad9361_2_clk ; // 48MHz 41.6667MHz
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wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz
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wire ad9361_2_clk_3x ; // 144MHz 125MHz
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wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz
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wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator
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// phased-array & rf control clocks
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wire clk_96m ;
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wire clk_48m ;
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wire clk_32m ;
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wire clk_19p2m ;
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clk_dist u_clk_dist
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(
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// input clocks
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.clk_250m_p (clk_250m_p ), // generated by ad9516, 250mhz
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.clk_250m_n (clk_250m_n ),
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.ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
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.ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
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// output clocks & reset
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// global reset
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.sys_rst (sys_rst ), // global reset signal, active high
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.ant_rst (ant_rst ), // phased-array & rf control reset signal, active high
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// pl signal processing clock
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.sys_clk (sys_clk ), // 48MHz 41.6667MHz
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.sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz
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.sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz
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.sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz
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.sys_clk_ld (sys_clk_ld ), // system main clock locked indicator
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// ad9361-1 clocks
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.ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz
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.ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz
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.ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz
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.ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz
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.ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator
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// ad9361-2 clocks
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.ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz
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.ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz
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.ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz
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.ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz
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.ad9361_2_clk_ld (ad9361_2_clk_ld ), // ad9361-2 clock group locked indicator
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// phased-array & rf control clocks
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.clk_96m (clk_96m ),
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.clk_48m (clk_48m ),
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.clk_32m (clk_32m ),
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.clk_19p2m (clk_19p2m )
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);
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////////////////////////////////////////////////////////////////////////////////
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//////////////////////////// Block Design Interface ////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// gpio
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wire [47:0] gpio_i;
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wire [47:0] gpio_o;
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wire [47:0] gpio_t;
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wire ad9361_rx_fifo_rst;
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assign gpio_i[47:39] = gpio_o[47:39];
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// hmc7044
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assign hmc7044_reset = gpio_o[ 0]; // hmc7044 reset
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assign hmc7044_sync = gpio_o[ 1]; // hmc7044 multichip synchronization
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assign hmc7044_gpio[0] = gpio_t[ 2] ? gpio_i[ 2] : gpio_o[ 2];
|
||||
assign hmc7044_gpio[1] = gpio_t[ 3] ? gpio_i[ 3] : gpio_o[ 3];
|
||||
assign hmc7044_gpio[2] = gpio_t[ 4] ? gpio_i[ 4] : gpio_o[ 4];
|
||||
assign hmc7044_gpio[3] = gpio_t[ 5] ? gpio_i[ 5] : gpio_o[ 5];
|
||||
// ad9361-1
|
||||
assign ad9361_1_txnrx = gpio_o[ 6]; // ad9361 enable state machine control
|
||||
assign ad9361_1_enable = gpio_o[ 7]; // ad9361 enable state machine control
|
||||
assign ad9361_1_en_agc = gpio_o[ 8]; // ad9361 agc control
|
||||
assign ad9361_1_reset_b = gpio_o[ 9]; // ad9361 reset
|
||||
assign ad9361_1_ctrl_out = gpio_o[17:10];
|
||||
assign gpio_i[21:18] = ad9361_1_ctrl_in;
|
||||
// ad9361-2
|
||||
assign ad9361_2_txnrx = gpio_o[22]; // ad9361 enable state machine control
|
||||
assign ad9361_2_enable = gpio_o[23]; // ad9361 enable state machine control
|
||||
assign ad9361_2_en_agc = gpio_o[24]; // ad9361 agc control
|
||||
assign ad9361_2_reset_b = gpio_o[25]; // ad9361 reset
|
||||
assign ad9361_2_ctrl_out = gpio_o[33:26];
|
||||
assign gpio_i[37:34] = ad9361_2_ctrl_in;
|
||||
// ad9361 rx fifo reset
|
||||
assign ad9361_rx_fifo_rst= gpio_o[38];
|
||||
|
||||
// spi interface
|
||||
wire spi_sclk ;
|
||||
wire [ 2:0] spi_cs ;
|
||||
reg spi_sdi ;
|
||||
wire spi_sdo ;
|
||||
wire spi_sdo_t ;
|
||||
wire spi_three_wire;
|
||||
wire spi_active ;
|
||||
|
||||
// hmc7044 - three-wire spi
|
||||
assign hmc7044_spi_clk = spi_sclk;
|
||||
assign hmc7044_spi_csn = spi_cs[0];
|
||||
assign hmc7044_spi_sdio = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// ad9361-1 - three-wire spi or four-wire spi
|
||||
assign ad9361_1_spi_clk = spi_sclk;
|
||||
assign ad9361_1_spi_csn = spi_cs[1];
|
||||
assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// ad9361-2 - three-wire spi or four-wire spi
|
||||
assign ad9361_2_spi_clk = spi_sclk;
|
||||
assign ad9361_2_spi_csn = spi_cs[2];
|
||||
assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// select sdi signal
|
||||
always @(*) begin
|
||||
if (~hmc7044_spi_csn)
|
||||
spi_sdi = hmc7044_spi_sdio;
|
||||
else if (~ad9361_1_spi_csn)
|
||||
spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso;
|
||||
else if (~ad9361_2_spi_csn)
|
||||
spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso;
|
||||
else
|
||||
spi_sdi = 1'bz;
|
||||
end
|
||||
|
||||
// ps clock
|
||||
wire ps_clk_50M;
|
||||
wire ps_clk_200M;
|
||||
|
||||
system_bd_wrapper u_system_bd_wrapper
|
||||
(
|
||||
// ddr
|
||||
.ddr_addr (ddr_addr ), // inout [14:0]ddr_addr
|
||||
.ddr_ba (ddr_ba ), // inout [2:0]ddr_ba
|
||||
.ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n
|
||||
.ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n
|
||||
.ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p
|
||||
.ddr_cke (ddr_cke ), // inout ddr_cke
|
||||
.ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n
|
||||
.ddr_dm (ddr_dm ), // inout [3:0]ddr_dm
|
||||
.ddr_dq (ddr_dq ), // inout [31:0]ddr_dq
|
||||
.ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n
|
||||
.ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p
|
||||
.ddr_odt (ddr_odt ), // inout ddr_odt
|
||||
.ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n
|
||||
.ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n
|
||||
.ddr_we_n (ddr_we_n ), // inout ddr_we_n
|
||||
|
||||
// fixed-io
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp
|
||||
.fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb
|
||||
|
||||
// gpio, for control signals
|
||||
.gpio_i (gpio_i ), // input [47:0]gpio_i
|
||||
.gpio_o (gpio_o ), // output [47:0]gpio_o
|
||||
.gpio_t (gpio_t ), // output [47:0]gpio_t
|
||||
|
||||
// spi interface
|
||||
.spi_sclk (spi_sclk ), // output spi_sclk
|
||||
.spi_cs (spi_cs ), // output [2:0]spi_cs
|
||||
.spi_sdi (spi_sdi ), // input [0:0]spi_sdi
|
||||
.spi_sdo (spi_sdo ), // output spi_sdo
|
||||
.spi_sdo_t (spi_sdo_t ), // output spi_sdo_t
|
||||
.spi_three_wire (spi_three_wire ), // output spi_three_wire
|
||||
.spi_active (spi_active ), // output spi_active
|
||||
|
||||
// ps clock
|
||||
.ps_clk_50M (ps_clk_50M ), // output ps_clk_50M
|
||||
.ps_clk_200M (ps_clk_200M ) // output ps_clk_200M
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Tx Signal ///////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// baseband signal
|
||||
wire [11:0] tx_data_i;
|
||||
wire [11:0] tx_data_q;
|
||||
|
||||
ad9361_tx_map_cmos_single u_ad9361_tx_map
|
||||
(
|
||||
.clk_in (ad9361_1_clk ), // input clk_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.tx_data_clk (sys_clk ), // input tx_data_clk
|
||||
.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
|
||||
|
||||
.tx_data_i (tx_data_i ), // input [11:0] tx_data_i
|
||||
.tx_data_q (tx_data_q ), // input [11:0] tx_data_q
|
||||
.clk_out (ad9361_1_tx_fb_clk ), // output clk_out
|
||||
.tx_frame (ad9361_1_tx_frame ), // output tx_frame
|
||||
.tx_data (ad9361_1_tx_data ) // output [11:0] tx_data
|
||||
);
|
||||
|
||||
assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk;
|
||||
// assign ad9361_2_tx_frame = ad9361_1_tx_frame ;
|
||||
// assign ad9361_2_tx_data = ad9361_1_tx_data ;
|
||||
|
||||
// <--------------------------------------------------------------------------->
|
||||
// <--------------------- insert transmitter logic below ---------------------->
|
||||
// <--------------------------------------------------------------------------->
|
||||
wire [ 1:0] waveform_sel;
|
||||
wire sweep_on ;
|
||||
wire [31:0] freq_set ;
|
||||
wire [ 1:0] iq_sel ;
|
||||
wire [ 3:0] bb_rshift ;
|
||||
|
||||
tx_qpsk u_tx_qpsk
|
||||
(
|
||||
.clk (sys_clk ), // input clk
|
||||
.rst (sys_rst ), // input rst
|
||||
.tx_data_i (tx_data_i ), // output [11:0] tx_data_i
|
||||
.tx_data_q (tx_data_q ), // output [11:0] tx_data_q
|
||||
// debug ports
|
||||
.waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel
|
||||
.sweep_on (sweep_on ), // input sweep_on
|
||||
.freq_set (freq_set ), // input [31:0] freq_set
|
||||
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
|
||||
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// RF control //////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Rx Signals //////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
wire [11:0] rx_ch1_i, rx_ch1_q;
|
||||
wire [11:0] rx_ch2_i, rx_ch2_q;
|
||||
wire [11:0] rx_ch3_i, rx_ch3_q;
|
||||
wire [11:0] rx_ch4_i, rx_ch4_q;
|
||||
|
||||
ad9361_rx_map_cmos_single u_ad9361_1_rx_map
|
||||
(
|
||||
.clk_in (ad9361_1_clk ), // input clk_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_1_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_1_rx_data ), // input [11:0] rx_data
|
||||
.rx_data_i (rx_ch1_i ), // output [11:0] rx_data_i
|
||||
.rx_data_q (rx_ch1_q ) // output [11:0] rx_data_q
|
||||
);
|
||||
|
||||
ad9361_rx_map_cmos_single u_ad9361_2_rx_map
|
||||
(
|
||||
.clk_in (ad9361_2_clk ), // input clk_in
|
||||
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_2_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_2_rx_data ), // input [11:0] rx_data
|
||||
.rx_data_i (rx_ch2_i ), // output [11:0] rx_data_i
|
||||
.rx_data_q (rx_ch2_q ) // output [11:0] rx_data_q
|
||||
);
|
||||
|
||||
// <--------------------------------------------------------------------------->
|
||||
// <----------------------- insert receiver logic below ----------------------->
|
||||
// <--------------------------------------------------------------------------->
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////// ILAs and VIOs /////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ila_tx u_ila_tx
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (tx_data_i ), // input wire [11:0] probe0
|
||||
.probe1 (tx_data_q ) // input wire [11:0] probe1
|
||||
);
|
||||
|
||||
ila_rx u_ila_rx
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (rx_ch1_i ), // input wire [11:0] probe0
|
||||
.probe1 (rx_ch1_q ), // input wire [11:0] probe1
|
||||
.probe2 (rx_ch2_i ), // input wire [11:0] probe2
|
||||
.probe3 (rx_ch2_q ) // input wire [11:0] probe3
|
||||
);
|
||||
|
||||
vio_manual_ctrl u_vio_manual_ctrl
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe_out0 (waveform_sel ), // output wire [1 : 0] probe_out0
|
||||
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
|
||||
.probe_out2 (freq_set ), // output wire [31 : 0] probe_out2
|
||||
.probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3
|
||||
.probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4
|
||||
);
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user