Archived
rename duifei_basic to duifei_cmos_1t2r, add duifei_cmos_1t1r
This commit is contained in:
@@ -0,0 +1,625 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_spi_engine #(
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parameter CMD_FIFO_ADDRESS_WIDTH = 4,
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parameter SYNC_FIFO_ADDRESS_WIDTH = 4,
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parameter SDO_FIFO_ADDRESS_WIDTH = 5,
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parameter SDI_FIFO_ADDRESS_WIDTH = 5,
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parameter MM_IF_TYPE = 0,
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parameter ASYNC_SPI_CLK = 0,
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parameter NUM_OFFLOAD = 0,
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parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4,
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parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,
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parameter ID = 0,
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parameter [15:0] DATA_WIDTH = 8,
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parameter [ 7:0] NUM_OF_SDI = 1 ) (
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// Slave AXI interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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output s_axi_awready,
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input [2:0] s_axi_awprot,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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output s_axi_arready,
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input [2:0] s_axi_arprot,
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output s_axi_rvalid,
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input s_axi_rready,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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// up interface
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input up_clk,
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input up_rstn,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack,
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output reg irq,
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// SPI signals
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input spi_clk,
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output spi_resetn,
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input cmd_ready,
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output cmd_valid,
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output [15:0] cmd_data,
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input sdo_data_ready,
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output sdo_data_valid,
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output [(DATA_WIDTH-1):0] sdo_data,
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output sdi_data_ready,
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input sdi_data_valid,
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input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
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output sync_ready,
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input sync_valid,
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input [7:0] sync_data,
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// Offload ctrl signals
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output offload0_cmd_wr_en,
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output [15:0] offload0_cmd_wr_data,
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output offload0_sdo_wr_en,
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output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,
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output offload0_mem_reset,
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output offload0_enable,
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input offload0_enabled,
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output offload_sync_ready,
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input offload_sync_valid,
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input [7:0] offload_sync_data);
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localparam PCORE_VERSION = 'h010071;
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localparam S_AXI = 0;
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localparam UP_FIFO = 1;
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wire clk;
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wire rstn;
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wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room;
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wire cmd_fifo_almost_empty;
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wire [15:0] cmd_fifo_in_data;
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wire cmd_fifo_in_ready;
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wire cmd_fifo_in_valid;
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wire [SDO_FIFO_ADDRESS_WIDTH:0] sdo_fifo_room;
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wire sdo_fifo_almost_empty;
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wire [(DATA_WIDTH-1):0] sdo_fifo_in_data;
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wire sdo_fifo_in_ready;
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wire sdo_fifo_in_valid;
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wire sdi_fifo_out_data_msb_s;
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wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level;
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wire sdi_fifo_almost_full;
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wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data;
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wire sdi_fifo_out_ready;
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wire sdi_fifo_out_valid;
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wire [7:0] sync_fifo_data;
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wire sync_fifo_valid;
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wire [7:0] offload_sync_fifo_data;
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wire offload_sync_fifo_valid;
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reg up_sw_reset = 1'b1;
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wire up_sw_resetn = ~up_sw_reset;
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reg [31:0] up_rdata_ff = 'd0;
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reg up_wack_ff = 1'b0;
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reg up_rack_ff = 1'b0;
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wire up_wreq_s;
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wire up_rreq_s;
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wire [31:0] up_wdata_s;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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// Scratch register
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reg [31:0] up_scratch = 'h00;
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reg [7:0] sync_id = 'h00;
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reg sync_id_pending = 1'b0;
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reg [7:0] offload_sync_id = 'h00;
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reg offload_sync_id_pending = 1'b0;
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generate if (MM_IF_TYPE == S_AXI) begin
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// assign clock and reset
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assign clk = s_axi_aclk;
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assign rstn = s_axi_aresetn;
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// interface wrapper
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up_axi #(
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.AXI_ADDRESS_WIDTH (16)
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) i_up_axi (
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.up_rstn(rstn),
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.up_clk(clk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_wreq(up_wreq_s),
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.up_waddr(up_waddr_s),
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.up_wdata(up_wdata_s),
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.up_wack(up_wack_ff),
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.up_rreq(up_rreq_s),
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.up_raddr(up_raddr_s),
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.up_rdata(up_rdata_ff),
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.up_rack(up_rack_ff)
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);
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assign up_rdata = 32'b0;
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assign up_rack = 1'b0;
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assign up_wack = 1'b0;
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end
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endgenerate
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generate if (MM_IF_TYPE == UP_FIFO) begin
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// assign clock and reset
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assign clk = up_clk;
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assign rstn = up_rstn;
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assign up_wreq_s = up_wreq;
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assign up_waddr_s = up_waddr;
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assign up_wdata_s = up_wdata;
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assign up_wack = up_wack_ff;
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assign up_rreq_s = up_rreq;
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assign up_raddr_s = up_raddr;
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assign up_rdata = up_rdata_ff;
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assign up_rack = up_rack_ff;
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end
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endgenerate
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// IRQ handling
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reg [3:0] up_irq_mask = 'h0;
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wire [3:0] up_irq_source;
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wire [3:0] up_irq_pending;
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assign up_irq_source = {
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offload_sync_id_pending,
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sync_id_pending,
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sdi_fifo_almost_full,
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sdo_fifo_almost_empty,
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cmd_fifo_almost_empty
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};
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assign up_irq_pending = up_irq_mask & up_irq_source;
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always @(posedge clk) begin
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if (rstn == 1'b0)
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irq <= 1'b0;
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else
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irq <= |up_irq_pending;
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end
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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up_wack_ff <= 1'b0;
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up_scratch <= 'h00;
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up_sw_reset <= 1'b1;
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end else begin
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up_wack_ff <= up_wreq_s;
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if (up_wreq_s) begin
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case (up_waddr_s)
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8'h02: up_scratch <= up_wdata_s;
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8'h10: up_sw_reset <= up_wdata_s;
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endcase
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end
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end
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end
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reg offload0_enable_reg;
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reg offload0_mem_reset_reg;
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wire offload0_enabled_s;
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// the software reset should reset all the registers
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always @(posedge clk) begin
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if (up_sw_resetn == 1'b0) begin
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up_irq_mask <= 'h00;
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offload0_enable_reg <= 1'b0;
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offload0_mem_reset_reg <= 1'b0;
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end else begin
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if (up_wreq_s) begin
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case (up_waddr_s)
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8'h20: up_irq_mask <= up_wdata_s;
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8'h40: offload0_enable_reg <= up_wdata_s[0];
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8'h42: offload0_mem_reset_reg <= up_wdata_s[0];
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endcase
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end
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end
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end
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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up_rack_ff <= 'd0;
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end else begin
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up_rack_ff <= up_rreq_s;
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end
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end
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generate
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if (NUM_OF_SDI > 1) begin
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// Only the first two SDI data can be recovered through AXI regmap
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assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH];
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end else begin
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assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data;
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end
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endgenerate
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always @(posedge clk) begin
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case (up_raddr_s)
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8'h00: up_rdata_ff <= PCORE_VERSION;
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8'h01: up_rdata_ff <= ID;
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8'h02: up_rdata_ff <= up_scratch;
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8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
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8'h10: up_rdata_ff <= up_sw_reset;
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8'h20: up_rdata_ff <= up_irq_mask;
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8'h21: up_rdata_ff <= up_irq_pending;
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8'h22: up_rdata_ff <= up_irq_source;
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8'h30: up_rdata_ff <= sync_id;
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8'h31: up_rdata_ff <= offload_sync_id;
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8'h34: up_rdata_ff <= cmd_fifo_room;
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8'h35: up_rdata_ff <= sdo_fifo_room;
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8'h36: up_rdata_ff <= sdi_fifo_level;
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8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0];
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8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */
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8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
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8'h40: up_rdata_ff <= {offload0_enable_reg};
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8'h41: up_rdata_ff <= {offload0_enabled_s};
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default: up_rdata_ff <= 'h00;
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endcase
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end
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always @(posedge clk) begin
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if (up_sw_resetn == 1'b0) begin
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sync_id <= 'h00;
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sync_id_pending <= 1'b0;
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end else begin
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if (sync_fifo_valid == 1'b1) begin
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sync_id <= sync_fifo_data;
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sync_id_pending <= 1'b1;
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end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
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sync_id_pending <= 1'b0;
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end
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end
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end
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always @(posedge clk) begin
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if (up_sw_resetn == 1'b0) begin
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offload_sync_id <= 'h00;
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offload_sync_id_pending <= 1'b0;
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end else begin
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||||
if (offload_sync_fifo_valid == 1'b1) begin
|
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offload_sync_id <= offload_sync_fifo_data;
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offload_sync_id_pending <= 1'b1;
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end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
|
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offload_sync_id_pending <= 1'b0;
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end
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||||
end
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end
|
||||
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generate if (ASYNC_SPI_CLK) begin
|
||||
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||||
wire spi_reset;
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||||
ad_rst i_spi_resetn (
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||||
.rst_async(up_sw_reset),
|
||||
.clk(spi_clk),
|
||||
.rst(spi_reset),
|
||||
.rstn()
|
||||
);
|
||||
assign spi_resetn = ~spi_reset;
|
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end else begin
|
||||
assign spi_resetn = ~up_sw_reset;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/* Evaluates to true if FIFO level/room is 3/4 or above */
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`define axi_spi_engine_check_watermark(x, n) \
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(x[n] == 1'b1 || x[n-1:n-2] == 2'b11)
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||||
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||||
assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38;
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assign cmd_fifo_in_data = up_wdata_s[15:0];
|
||||
assign cmd_fifo_almost_empty =
|
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`axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH);
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(16),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_cmd_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(cmd_fifo_in_ready),
|
||||
.s_axis_valid(cmd_fifo_in_valid),
|
||||
.s_axis_data(cmd_fifo_in_data),
|
||||
.s_axis_room(cmd_fifo_room),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(cmd_ready),
|
||||
.m_axis_valid(cmd_valid),
|
||||
.m_axis_data(cmd_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
|
||||
assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0];
|
||||
assign sdo_fifo_almost_empty =
|
||||
`axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH);
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_sdo_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(sdo_fifo_in_ready),
|
||||
.s_axis_valid(sdo_fifo_in_valid),
|
||||
.s_axis_data(sdo_fifo_in_data),
|
||||
.s_axis_room(sdo_fifo_room),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(sdo_data_ready),
|
||||
.m_axis_valid(sdo_data_valid),
|
||||
.m_axis_data(sdo_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
|
||||
assign sdi_fifo_almost_full =
|
||||
`axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_sdi_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(sdi_data_ready),
|
||||
.s_axis_valid(sdi_data_valid),
|
||||
.s_axis_data(sdi_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(sdi_fifo_out_ready),
|
||||
.m_axis_valid(sdi_fifo_out_valid),
|
||||
.m_axis_data(sdi_fifo_out_data),
|
||||
.m_axis_level(sdi_fifo_level)
|
||||
);
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
// synchronization FIFO for the SYNC interface
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(8),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_sync_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(sync_ready),
|
||||
.s_axis_valid(sync_valid),
|
||||
.s_axis_data(sync_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(sync_fifo_valid),
|
||||
.m_axis_data(sync_fifo_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
// synchronization FIFO for the offload command interface
|
||||
wire up_offload0_cmd_wr_en_s;
|
||||
wire [15:0] up_offload0_cmd_wr_data_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(16),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_offload_cmd_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(),
|
||||
.s_axis_valid(up_offload0_cmd_wr_en_s),
|
||||
.s_axis_data(up_offload0_cmd_wr_data_s),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload0_cmd_wr_en),
|
||||
.m_axis_data(offload0_cmd_wr_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
|
||||
assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0];
|
||||
|
||||
// synchronization FIFO for the offload SDO interface
|
||||
wire up_offload0_sdo_wr_en_s;
|
||||
wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_offload_sdo_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(),
|
||||
.s_axis_valid(up_offload0_sdo_wr_en_s),
|
||||
.s_axis_data(up_offload0_sdo_wr_data_s),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload0_sdo_wr_en),
|
||||
.m_axis_data(offload0_sdo_wr_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
|
||||
assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0];
|
||||
|
||||
// synchronization FIFO for the Offload SYNC interface
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(8),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_offload_sync_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(offload_sync_ready),
|
||||
.s_axis_valid(offload_sync_valid),
|
||||
.s_axis_data(offload_sync_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload_sync_fifo_valid),
|
||||
.m_axis_data(offload_sync_fifo_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
end else begin /* ASYNC_SPI_CLK == 0 */
|
||||
|
||||
assign sync_fifo_valid = sync_valid;
|
||||
assign sync_fifo_data = sync_data;
|
||||
assign sync_ready = 1'b1;
|
||||
|
||||
assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
|
||||
assign offload0_cmd_wr_data = up_wdata_s[15:0];
|
||||
|
||||
assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
|
||||
assign offload0_sdo_wr_data = up_wdata_s[DATA_WIDTH-1:0];
|
||||
|
||||
assign offload_sync_fifo_valid = offload_sync_valid;
|
||||
assign offload_sync_fifo_data = offload_sync_data;
|
||||
assign offload_sync_ready = 1'b1;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_enable_sync (
|
||||
.in_bits (offload0_enable_reg),
|
||||
.out_resetn (spi_resetn),
|
||||
.out_clk (spi_clk),
|
||||
.out_bits (offload0_enable));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_enabled_sync (
|
||||
.in_bits (offload0_enabled),
|
||||
.out_resetn (up_sw_resetn),
|
||||
.out_clk (clk),
|
||||
.out_bits (offload0_enabled_s));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_mem_reset_sync (
|
||||
.in_bits (offload0_mem_reset_reg),
|
||||
.out_resetn (spi_resetn),
|
||||
.out_clk (spi_clk),
|
||||
.out_bits (offload0_mem_reset));
|
||||
|
||||
endmodule
|
||||
+7759
File diff suppressed because it is too large
Load Diff
+18807
File diff suppressed because it is too large
Load Diff
+31945
File diff suppressed because it is too large
Load Diff
+10519
File diff suppressed because it is too large
Load Diff
+278
@@ -0,0 +1,278 @@
|
||||
//------------------------------------------------------------------------
|
||||
//--
|
||||
//-- Filename : xlconcat.v
|
||||
//--
|
||||
//-- Date : 06/05/12
|
||||
//-
|
||||
//- Description : Verilog description of a concat block. This
|
||||
//- block does not use a core.
|
||||
//-
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module xlconcat_v2_1_3_xlconcat (In0, In1, In2, In3, In4, In5, In6, In7, In8, In9, In10, In11, In12, In13, In14, In15, In16, In17, In18, In19, In20, In21, In22, In23, In24, In25, In26, In27, In28, In29, In30, In31, dout);
|
||||
parameter IN0_WIDTH = 1;
|
||||
input [IN0_WIDTH -1:0] In0;
|
||||
parameter IN1_WIDTH = 1;
|
||||
input [IN1_WIDTH -1:0] In1;
|
||||
parameter IN2_WIDTH = 1;
|
||||
input [IN2_WIDTH -1:0] In2;
|
||||
parameter IN3_WIDTH = 1;
|
||||
input [IN3_WIDTH -1:0] In3;
|
||||
parameter IN4_WIDTH = 1;
|
||||
input [IN4_WIDTH -1:0] In4;
|
||||
parameter IN5_WIDTH = 1;
|
||||
input [IN5_WIDTH -1:0] In5;
|
||||
parameter IN6_WIDTH = 1;
|
||||
input [IN6_WIDTH -1:0] In6;
|
||||
parameter IN7_WIDTH = 1;
|
||||
input [IN7_WIDTH -1:0] In7;
|
||||
parameter IN8_WIDTH = 1;
|
||||
input [IN8_WIDTH -1:0] In8;
|
||||
parameter IN9_WIDTH = 1;
|
||||
input [IN9_WIDTH -1:0] In9;
|
||||
parameter IN10_WIDTH = 1;
|
||||
input [IN10_WIDTH -1:0] In10;
|
||||
parameter IN11_WIDTH = 1;
|
||||
input [IN11_WIDTH -1:0] In11;
|
||||
parameter IN12_WIDTH = 1;
|
||||
input [IN12_WIDTH -1:0] In12;
|
||||
parameter IN13_WIDTH = 1;
|
||||
input [IN13_WIDTH -1:0] In13;
|
||||
parameter IN14_WIDTH = 1;
|
||||
input [IN14_WIDTH -1:0] In14;
|
||||
parameter IN15_WIDTH = 1;
|
||||
input [IN15_WIDTH -1:0] In15;
|
||||
parameter IN16_WIDTH = 1;
|
||||
input [IN16_WIDTH -1:0] In16;
|
||||
parameter IN17_WIDTH = 1;
|
||||
input [IN17_WIDTH -1:0] In17;
|
||||
parameter IN18_WIDTH = 1;
|
||||
input [IN18_WIDTH -1:0] In18;
|
||||
parameter IN19_WIDTH = 1;
|
||||
input [IN19_WIDTH -1:0] In19;
|
||||
parameter IN20_WIDTH = 1;
|
||||
input [IN20_WIDTH -1:0] In20;
|
||||
parameter IN21_WIDTH = 1;
|
||||
input [IN21_WIDTH -1:0] In21;
|
||||
parameter IN22_WIDTH = 1;
|
||||
input [IN22_WIDTH -1:0] In22;
|
||||
parameter IN23_WIDTH = 1;
|
||||
input [IN23_WIDTH -1:0] In23;
|
||||
parameter IN24_WIDTH = 1;
|
||||
input [IN24_WIDTH -1:0] In24;
|
||||
parameter IN25_WIDTH = 1;
|
||||
input [IN25_WIDTH -1:0] In25;
|
||||
parameter IN26_WIDTH = 1;
|
||||
input [IN26_WIDTH -1:0] In26;
|
||||
parameter IN27_WIDTH = 1;
|
||||
input [IN27_WIDTH -1:0] In27;
|
||||
parameter IN28_WIDTH = 1;
|
||||
input [IN28_WIDTH -1:0] In28;
|
||||
parameter IN29_WIDTH = 1;
|
||||
input [IN29_WIDTH -1:0] In29;
|
||||
parameter IN30_WIDTH = 1;
|
||||
input [IN30_WIDTH -1:0] In30;
|
||||
parameter IN31_WIDTH = 1;
|
||||
input [IN31_WIDTH -1:0] In31;
|
||||
parameter dout_width = 2;
|
||||
output [dout_width-1:0] dout;
|
||||
parameter NUM_PORTS =2;
|
||||
|
||||
|
||||
generate if (NUM_PORTS == 1)
|
||||
begin : C_NUM_1
|
||||
assign dout = In0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 2)
|
||||
begin : C_NUM_2
|
||||
assign dout = {In1,In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 3)
|
||||
begin:C_NUM_3
|
||||
assign dout = {In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 4)
|
||||
begin:C_NUM_4
|
||||
assign dout = {In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 5)
|
||||
begin:C_NUM_5
|
||||
assign dout = {In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 6)
|
||||
begin:C_NUM_6
|
||||
assign dout = {In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 7)
|
||||
begin:C_NUM_7
|
||||
assign dout = {In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 8)
|
||||
begin:C_NUM_8
|
||||
assign dout = {In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 9)
|
||||
begin:C_NUM_9
|
||||
assign dout = {In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 10)
|
||||
begin:C_NUM_10
|
||||
assign dout = {In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 11)
|
||||
begin:C_NUM_11
|
||||
assign dout = {In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 12)
|
||||
begin:C_NUM_12
|
||||
assign dout = {In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 13)
|
||||
begin:C_NUM_13
|
||||
assign dout = {In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 14)
|
||||
begin:C_NUM_14
|
||||
assign dout = {In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 15)
|
||||
begin:C_NUM_15
|
||||
assign dout = {In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 16)
|
||||
begin:C_NUM_16
|
||||
assign dout = {In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 17)
|
||||
begin:C_NUM_17
|
||||
assign dout = {In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 18)
|
||||
begin:C_NUM_18
|
||||
assign dout = {In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 19)
|
||||
begin:C_NUM_19
|
||||
assign dout = {In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 20)
|
||||
begin:C_NUM_20
|
||||
assign dout = {In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 21)
|
||||
begin:C_NUM_21
|
||||
assign dout = {In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 22)
|
||||
begin:C_NUM_22
|
||||
assign dout = {In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 23)
|
||||
begin:C_NUM_23
|
||||
assign dout = {In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 24)
|
||||
begin:C_NUM_24
|
||||
assign dout = {In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 25)
|
||||
begin:C_NUM_25
|
||||
assign dout = {In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 26)
|
||||
begin:C_NUM_26
|
||||
assign dout = {In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 27)
|
||||
begin:C_NUM_27
|
||||
assign dout = {In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 28)
|
||||
begin:C_NUM_28
|
||||
assign dout = {In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 29)
|
||||
begin:C_NUM_29
|
||||
assign dout = {In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 30)
|
||||
begin:C_NUM_30
|
||||
assign dout = {In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 31)
|
||||
begin:C_NUM_31
|
||||
assign dout = {In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (NUM_PORTS == 32)
|
||||
begin:C_NUM_32
|
||||
assign dout = {In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
+3659
File diff suppressed because it is too large
Load Diff
+1956
File diff suppressed because it is too large
Load Diff
+456
@@ -0,0 +1,456 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module spi_engine_execution #(
|
||||
|
||||
parameter NUM_OF_CS = 1,
|
||||
parameter DEFAULT_SPI_CFG = 0,
|
||||
parameter DEFAULT_CLK_DIV = 0,
|
||||
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
|
||||
parameter NUM_OF_SDI = 1,
|
||||
parameter [0:0] SDO_DEFAULT = 1'b0,
|
||||
parameter [1:0] SDI_DELAY = 2'b00) (
|
||||
|
||||
input clk,
|
||||
input resetn,
|
||||
|
||||
output reg active,
|
||||
|
||||
output cmd_ready,
|
||||
input cmd_valid,
|
||||
input [15:0] cmd,
|
||||
|
||||
input sdo_data_valid,
|
||||
output reg sdo_data_ready,
|
||||
input [(DATA_WIDTH-1):0] sdo_data,
|
||||
|
||||
|
||||
input sdi_data_ready,
|
||||
output reg sdi_data_valid,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data,
|
||||
|
||||
input sync_ready,
|
||||
output reg sync_valid,
|
||||
output [7:0] sync,
|
||||
|
||||
output reg sclk,
|
||||
output reg sdo,
|
||||
output reg sdo_t,
|
||||
input [NUM_OF_SDI-1:0] sdi,
|
||||
output reg [NUM_OF_CS-1:0] cs,
|
||||
output reg three_wire
|
||||
);
|
||||
|
||||
localparam CMD_TRANSFER = 2'b00;
|
||||
localparam CMD_CHIPSELECT = 2'b01;
|
||||
localparam CMD_WRITE = 2'b10;
|
||||
localparam CMD_MISC = 2'b11;
|
||||
|
||||
localparam MISC_SYNC = 1'b0;
|
||||
localparam MISC_SLEEP = 1'b1;
|
||||
|
||||
localparam REG_CLK_DIV = 2'b00;
|
||||
localparam REG_CONFIG = 2'b01;
|
||||
localparam REG_WORD_LENGTH = 2'b10;
|
||||
|
||||
localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
|
||||
DATA_WIDTH > 8 ? 4 : 3;
|
||||
|
||||
localparam BIT_COUNTER_CARRY = 2** (BIT_COUNTER_WIDTH + 1);
|
||||
localparam BIT_COUNTER_CLEAR = {{8{1'b1}}, {BIT_COUNTER_WIDTH{1'b0}}, 1'b1};
|
||||
|
||||
reg sclk_int = 1'b0;
|
||||
wire sdo_int_s;
|
||||
reg sdo_t_int = 1'b0;
|
||||
|
||||
reg idle;
|
||||
|
||||
reg [7:0] clk_div_counter = 'h00;
|
||||
reg [7:0] clk_div_counter_next = 'h00;
|
||||
reg clk_div_last;
|
||||
|
||||
reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;
|
||||
|
||||
wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [2:0] cs_sleep_counter2 = counter[(BIT_COUNTER_WIDTH+3):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];
|
||||
wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
|
||||
wire ntx_rx = counter[0];
|
||||
|
||||
reg trigger = 1'b0;
|
||||
reg trigger_next = 1'b0;
|
||||
reg wait_for_io = 1'b0;
|
||||
reg transfer_active = 1'b0;
|
||||
|
||||
wire last_bit;
|
||||
wire first_bit;
|
||||
reg last_transfer;
|
||||
reg [7:0] word_length = DATA_WIDTH;
|
||||
reg [7:0] left_aligned = 8'b0;
|
||||
wire end_of_word;
|
||||
|
||||
reg [7:0] sdi_counter = 8'b0;
|
||||
|
||||
assign first_bit = ((bit_counter == 'h0) || (bit_counter == word_length));
|
||||
assign last_bit = bit_counter == word_length - 1;
|
||||
assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
|
||||
|
||||
reg [15:0] cmd_d1;
|
||||
|
||||
reg cpha = DEFAULT_SPI_CFG[0];
|
||||
reg cpol = DEFAULT_SPI_CFG[1];
|
||||
reg [7:0] clk_div = DEFAULT_CLK_DIV;
|
||||
|
||||
reg sdo_enabled = 1'b0;
|
||||
reg sdi_enabled = 1'b0;
|
||||
|
||||
reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
|
||||
|
||||
reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
|
||||
|
||||
wire [1:0] inst = cmd[13:12];
|
||||
wire [1:0] inst_d1 = cmd_d1[13:12];
|
||||
|
||||
wire exec_cmd = cmd_ready && cmd_valid;
|
||||
wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
|
||||
|
||||
wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
|
||||
wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
|
||||
wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
|
||||
wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
|
||||
|
||||
wire trigger_tx;
|
||||
wire trigger_rx;
|
||||
|
||||
wire sleep_counter_compare;
|
||||
wire cs_sleep_counter_compare;
|
||||
wire cs_sleep_counter_compare2;
|
||||
|
||||
wire io_ready1;
|
||||
wire io_ready2;
|
||||
wire trigger_rx_s;
|
||||
|
||||
wire last_sdi_bit;
|
||||
|
||||
assign cmd_ready = idle;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (exec_transfer_cmd) begin
|
||||
sdo_enabled <= cmd[8];
|
||||
sdi_enabled <= cmd[9];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cmd_ready & cmd_valid)
|
||||
cmd_d1 <= cmd;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
active <= 1'b0;
|
||||
end else begin
|
||||
if (exec_cmd == 1'b1)
|
||||
active <= 1'b1;
|
||||
else if (sync_ready == 1'b1 && sync_valid == 1'b1)
|
||||
active <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Load the interface configurations from the 'Configuration Write'
|
||||
// instruction
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cpha <= DEFAULT_SPI_CFG[0];
|
||||
cpol <= DEFAULT_SPI_CFG[1];
|
||||
three_wire <= DEFAULT_SPI_CFG[2];
|
||||
clk_div <= DEFAULT_CLK_DIV;
|
||||
word_length <= DATA_WIDTH;
|
||||
left_aligned <= 8'b0;
|
||||
end else if (exec_write_cmd == 1'b1) begin
|
||||
if (cmd[9:8] == REG_CONFIG) begin
|
||||
cpha <= cmd[0];
|
||||
cpol <= cmd[1];
|
||||
three_wire <= cmd[2];
|
||||
end else if (cmd[9:8] == REG_CLK_DIV) begin
|
||||
clk_div <= cmd[7:0];
|
||||
end else if (cmd[9:8] == REG_WORD_LENGTH) begin
|
||||
// the max value of this reg must be DATA_WIDTH
|
||||
word_length <= cmd[7:0];
|
||||
left_aligned <= DATA_WIDTH - cmd[7:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
|
||||
clk_div_counter == 'h01) || clk_div == 'h00)
|
||||
clk_div_last <= 1'b1;
|
||||
else
|
||||
clk_div_last <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
|
||||
clk_div_counter <= clk_div;
|
||||
trigger <= 1'b1;
|
||||
end else begin
|
||||
clk_div_counter <= clk_div_counter - 1'b1;
|
||||
trigger <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
|
||||
assign trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
|
||||
|
||||
assign sleep_counter_compare = sleep_counter == cmd_d1[7:0] && clk_div_last == 1'b1;
|
||||
assign cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last == 1'b1;
|
||||
assign cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (idle == 1'b1) begin
|
||||
counter <= 'h00;
|
||||
end else if (clk_div_last == 1'b1 && wait_for_io == 1'b0) begin
|
||||
if (bit_counter == word_length) begin
|
||||
counter <= (counter & BIT_COUNTER_CLEAR) + (transfer_active ? 'h1 : 'h10) + BIT_COUNTER_CARRY;
|
||||
end else begin
|
||||
counter <= counter + (transfer_active ? 'h1 : 'h10);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
idle <= 1'b1;
|
||||
end else begin
|
||||
if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
|
||||
idle <= 1'b0;
|
||||
end else begin
|
||||
case (inst_d1)
|
||||
CMD_TRANSFER: begin
|
||||
if (transfer_active == 1'b0 && wait_for_io == 1'b0)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
CMD_CHIPSELECT: begin
|
||||
if (cs_sleep_counter_compare2)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
CMD_MISC: begin
|
||||
case (cmd_d1[8])
|
||||
MISC_SLEEP: begin
|
||||
if (sleep_counter_compare)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
MISC_SYNC: begin
|
||||
if (sync_ready)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cs <= 'hff;
|
||||
end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
|
||||
cs <= cmd_d1[NUM_OF_CS-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
sync_valid <= 1'b0;
|
||||
end else begin
|
||||
if (exec_sync_cmd == 1'b1) begin
|
||||
sync_valid <= 1'b1;
|
||||
end else if (sync_ready == 1'b1) begin
|
||||
sync_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sync = cmd_d1[7:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0)
|
||||
sdo_data_ready <= 1'b0;
|
||||
else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 && transfer_active == 1'b1)
|
||||
sdo_data_ready <= 1'b1;
|
||||
else if (sdo_data_valid == 1'b1)
|
||||
sdo_data_ready <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0)
|
||||
sdi_data_valid <= 1'b0;
|
||||
else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
|
||||
sdi_data_valid <= 1'b1;
|
||||
else if (sdi_data_ready == 1'b1)
|
||||
sdi_data_valid <= 1'b0;
|
||||
end
|
||||
|
||||
assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
|
||||
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
|
||||
assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
|
||||
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (idle == 1'b1) begin
|
||||
last_transfer <= 1'b0;
|
||||
end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
|
||||
if (transfer_counter == cmd_d1[7:0])
|
||||
last_transfer <= 1'b1;
|
||||
else
|
||||
last_transfer <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
transfer_active <= 1'b0;
|
||||
wait_for_io <= 1'b0;
|
||||
end else begin
|
||||
if (exec_transfer_cmd == 1'b1) begin
|
||||
wait_for_io <= 1'b1;
|
||||
transfer_active <= 1'b0;
|
||||
end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
|
||||
wait_for_io <= 1'b0;
|
||||
if (last_transfer == 1'b0)
|
||||
transfer_active <= 1'b1;
|
||||
else
|
||||
transfer_active <= 1'b0;
|
||||
end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
|
||||
if (last_transfer == 1'b1 || io_ready2 == 1'b0)
|
||||
transfer_active <= 1'b0;
|
||||
if (io_ready2 == 1'b0)
|
||||
wait_for_io <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (transfer_active == 1'b1 || wait_for_io == 1'b1)
|
||||
begin
|
||||
sdo_t_int <= ~sdo_enabled;
|
||||
end else begin
|
||||
sdo_t_int <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Load the SDO parallel data into the SDO shift register. In case of a custom
|
||||
// data width, additional bit shifting must done at load.
|
||||
always @(posedge clk) begin
|
||||
if ((inst_d1 == CMD_TRANSFER) && (!sdo_enabled)) begin
|
||||
data_sdo_shift <= {DATA_WIDTH{SDO_DEFAULT}};
|
||||
end else if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
|
||||
if (first_bit == 1'b1)
|
||||
data_sdo_shift <= sdo_data << left_aligned;
|
||||
else
|
||||
data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
|
||||
end
|
||||
end
|
||||
|
||||
assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1];
|
||||
|
||||
// In case of an interface with high clock rate (SCLK > 50MHz), the latch of
|
||||
// the SDI line can be delayed with 1, 2 or 3 SPI core clock cycle.
|
||||
// Taking the fact that in high SCLK frequencies the pre-scaler most likely will
|
||||
// be set to 0, to reduce the core clock's speed, this delay will mean that SDI will
|
||||
// be latched at one of the next consecutive SCLK edge.
|
||||
|
||||
always @(posedge clk) begin
|
||||
trigger_rx_d <= {trigger_rx_d, trigger_rx};
|
||||
end
|
||||
|
||||
assign trigger_rx_s = trigger_rx_d[SDI_DELAY+1];
|
||||
|
||||
// Load the serial data into SDI shift register(s), then link it to the output
|
||||
// register of the module
|
||||
|
||||
wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);
|
||||
genvar i;
|
||||
generate
|
||||
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
|
||||
|
||||
reg [DATA_WIDTH-1:0] data_sdi_shift;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
data_sdi_shift <= 0;
|
||||
end else begin
|
||||
if (trigger_rx_s == 1'b1) begin
|
||||
data_sdi_shift <= {data_sdi_shift, sdi[i]};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sdi_data[i*DATA_WIDTH+:DATA_WIDTH] = data_sdi_shift;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign last_sdi_bit = (sdi_counter == word_length-1);
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
sdi_counter <= 8'b0;
|
||||
end else begin
|
||||
if (trigger_rx_s == 1'b1) begin
|
||||
sdi_counter <= last_sdi_bit ? 8'b0 : sdi_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (transfer_active == 1'b1) begin
|
||||
sclk_int <= cpol ^ cpha ^ ntx_rx;
|
||||
end else begin
|
||||
sclk_int <= cpol;
|
||||
end
|
||||
end
|
||||
|
||||
// Additional register stage to improve timing
|
||||
always @(posedge clk) begin
|
||||
sclk <= sclk_int;
|
||||
sdo <= sdo_int_s;
|
||||
sdo_t <= sdo_t_int;
|
||||
end
|
||||
|
||||
endmodule
|
||||
+1646
File diff suppressed because it is too large
Load Diff
+842
@@ -0,0 +1,842 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_apis.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Set of Zynq VIP APIs that are used for writing tests.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* API for setting the STOP_ON_ERROR*/
|
||||
task automatic set_stop_on_error;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL);
|
||||
STOP_ON_ERROR = LEVEL;
|
||||
// M_AXI_GP0.master.set_stop_on_error(LEVEL);
|
||||
// M_AXI_GP1.master.set_stop_on_error(LEVEL);
|
||||
// S_AXI_GP0.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_GP1.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP0.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP1.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP2.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP3.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_ACP.slave.set_stop_on_error(LEVEL);
|
||||
M_AXI_GP0.STOP_ON_ERROR = LEVEL;
|
||||
M_AXI_GP1.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_GP0.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_GP1.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP0.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP1.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP2.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP3.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_ACP.STOP_ON_ERROR = LEVEL;
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting the verbosity for channel level info*/
|
||||
task automatic set_channel_level_info;
|
||||
input [1023:0] name;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO, name , LEVEL);
|
||||
case(name)
|
||||
// "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL);
|
||||
// "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL);
|
||||
"ALL" : begin
|
||||
// M_AXI_GP0.master.set_channel_level_info(LEVEL);
|
||||
// M_AXI_GP1.master.set_channel_level_info(LEVEL);
|
||||
// S_AXI_GP0.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_GP1.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP0.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP1.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP2.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP3.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_ACP.slave.set_channel_level_info(LEVEL);
|
||||
end
|
||||
default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting the verbosity for function level info*/
|
||||
task automatic set_function_level_info;
|
||||
input [1023:0] name;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO, name , LEVEL);
|
||||
case(name)
|
||||
// "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL);
|
||||
// "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL);
|
||||
// "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL);
|
||||
"ALL" : begin
|
||||
// M_AXI_GP0.master.set_function_level_info(LEVEL);
|
||||
// M_AXI_GP1.master.set_function_level_info(LEVEL);
|
||||
// S_AXI_GP0.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_GP1.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP0.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP1.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP2.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP3.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_ACP.slave.set_function_level_info(LEVEL);
|
||||
end
|
||||
default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting the Message verbosity */
|
||||
task automatic set_debug_level_info;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO, LEVEL);
|
||||
DEBUG_INFO = LEVEL;
|
||||
M_AXI_GP0.DEBUG_INFO = LEVEL;
|
||||
M_AXI_GP1.DEBUG_INFO = LEVEL;
|
||||
S_AXI_GP0.DEBUG_INFO = LEVEL;
|
||||
S_AXI_GP1.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP0.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP1.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP2.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP3.DEBUG_INFO = LEVEL;
|
||||
S_AXI_ACP.DEBUG_INFO = LEVEL;
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting ARQos Values */
|
||||
task automatic set_arqos;
|
||||
input [1023:0] name;
|
||||
input [axi_qos_width-1:0] value;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO, name , value);
|
||||
case(name)
|
||||
"S_AXI_GP0" : S_AXI_GP0.set_arqos(value);
|
||||
"S_AXI_GP1" : S_AXI_GP1.set_arqos(value);
|
||||
"S_AXI_HP0" : S_AXI_HP0.set_arqos(value);
|
||||
"S_AXI_HP1" : S_AXI_HP1.set_arqos(value);
|
||||
"S_AXI_HP2" : S_AXI_HP2.set_arqos(value);
|
||||
"S_AXI_HP3" : S_AXI_HP3.set_arqos(value);
|
||||
"S_AXI_ACP" : S_AXI_ACP.set_arqos(value);
|
||||
default : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting AWQos Values */
|
||||
task automatic set_awqos;
|
||||
input [1023:0] name;
|
||||
input [axi_qos_width-1:0] value;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO, name , value);
|
||||
case(name)
|
||||
"S_AXI_GP0" : S_AXI_GP0.set_awqos(value);
|
||||
"S_AXI_GP1" : S_AXI_GP1.set_awqos(value);
|
||||
"S_AXI_HP0" : S_AXI_HP0.set_awqos(value);
|
||||
"S_AXI_HP1" : S_AXI_HP1.set_awqos(value);
|
||||
"S_AXI_HP2" : S_AXI_HP2.set_awqos(value);
|
||||
"S_AXI_HP3" : S_AXI_HP3.set_awqos(value);
|
||||
"S_AXI_ACP" : S_AXI_ACP.set_awqos(value);
|
||||
default : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for soft reset control */
|
||||
task automatic fpga_soft_reset;
|
||||
input[data_width-1:0] reset_ctrl;
|
||||
begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO, reset_ctrl);
|
||||
gen_rst.fpga_soft_reset(reset_ctrl);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for por and strb reset control */
|
||||
// task automatic por_srstb_reset;
|
||||
// input por_reset_ctrl;
|
||||
// begin
|
||||
// if(DEBUG_INFO) $display("[%0d] : %0s : POR and STRB Reset called for 0x%0h",$time, DISP_INFO, por_reset_ctrl);
|
||||
// // gen_rst.por_srstb_reset(por_reset_ctrl);
|
||||
// gen_rst.por_srstb_reset(por_reset_ctrl);
|
||||
//
|
||||
// end
|
||||
// endtask
|
||||
|
||||
/* API for pre-loading memories from (DDR/OCM model) */
|
||||
task automatic pre_load_mem_from_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
succ = $fopen(file_name,"r");
|
||||
if(succ == 0) begin
|
||||
$display("[%0d] : %0s : '%0s' doesn't exist. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, file_name);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
else if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem_from_file' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for pre-loading memories (DDR/OCM) */
|
||||
task automatic pre_load_mem;
|
||||
input [1:0] data_type;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for backdoor write to memories (DDR/OCM) */
|
||||
task automatic write_mem;
|
||||
input [max_burst_bits-1 :0] data;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_burst_bytes_width:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
|
||||
else
|
||||
ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes,all_strb_valid);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'write_mem' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_mem' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* read_memory */
|
||||
task automatic read_mem;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_burst_bytes_width :0] no_of_bytes;
|
||||
output[max_burst_bits-1 :0] data;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.read_mem(data,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.read_mem(data,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'read_mem' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_mem' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for backdoor read to memories (DDR/OCM) */
|
||||
task automatic peek_mem_to_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'peek_mem_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'peek_mem_to_file' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to read interrupt status */
|
||||
task automatic read_interrupt;
|
||||
output[irq_width-1:0] irq_status;
|
||||
begin
|
||||
irq_status = IRQ_F2P;
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO, irq_status);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to wait on interrup */
|
||||
task automatic wait_interrupt;
|
||||
input [3:0] irq;
|
||||
output[irq_width-1:0] irq_status;
|
||||
begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO, irq);
|
||||
|
||||
case(irq)
|
||||
0 : wait(IRQ_F2P[0] === 1'b1);
|
||||
1 : wait(IRQ_F2P[1] === 1'b1);
|
||||
2 : wait(IRQ_F2P[2] === 1'b1);
|
||||
3 : wait(IRQ_F2P[3] === 1'b1);
|
||||
4 : wait(IRQ_F2P[4] === 1'b1);
|
||||
5 : wait(IRQ_F2P[5] === 1'b1);
|
||||
6 : wait(IRQ_F2P[6] === 1'b1);
|
||||
7 : wait(IRQ_F2P[7] === 1'b1);
|
||||
8 : wait(IRQ_F2P[8] === 1'b1);
|
||||
9 : wait(IRQ_F2P[9] === 1'b1);
|
||||
10: wait(IRQ_F2P[10] === 1'b1);
|
||||
11: wait(IRQ_F2P[11] === 1'b1);
|
||||
12: wait(IRQ_F2P[12] === 1'b1);
|
||||
13: wait(IRQ_F2P[13] === 1'b1);
|
||||
14: wait(IRQ_F2P[14] === 1'b1);
|
||||
15: wait(IRQ_F2P[15] === 1'b1);
|
||||
default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR);
|
||||
endcase
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO, irq);
|
||||
irq_status = IRQ_F2P;
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to wait for a certain match pattern*/
|
||||
task automatic wait_mem_update;
|
||||
input[addr_width-1:0] address;
|
||||
input[data_width-1:0] data_in;
|
||||
output[data_width-1:0] data_out;
|
||||
reg[data_width-1:0] datao;
|
||||
begin
|
||||
if(mem_update_key) begin
|
||||
mem_update_key = 0;
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : 'wait_mem_update' called for Address(0x%0h) , Match Pattern(0x%0h) \n",$time, DISP_INFO, address, data_in);
|
||||
if(check_addr_aligned(address)) begin
|
||||
ddrc.ddr.wait_mem_update(address, datao);
|
||||
if(datao != data_in)begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \n",$time, DISP_ERR, address, data_in,datao);
|
||||
$stop;
|
||||
end else
|
||||
$display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \n",$time, DISP_INFO, address, data_in);
|
||||
data_out = datao;
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'wait_mem_update' call failed ...\n",$time, DISP_ERR, address);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
mem_update_key = 1;
|
||||
end else
|
||||
$display("[%0d] : %0s : One instance of 'wait_mem_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
/* API to initiate a WRITE transaction on one of the AXI-Master ports*/
|
||||
task automatic write_from_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] wr_size;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
integer succ;
|
||||
begin
|
||||
succ = $fopen(file_name,"r");
|
||||
if(succ == 0) begin
|
||||
$display("[%0d] : %0s : '%0s' doesn't exist. 'write_from_file' call failed ...\n",$time, DISP_ERR, file_name);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
else if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(check_addr_aligned(start_addr)) begin
|
||||
$fclose(succ);
|
||||
// case(start_addr[31:30])
|
||||
if (start_addr[31:30] === 2'b01) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name);
|
||||
M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name);
|
||||
M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
// endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to initiate a READ transaction on one of the AXI-Master ports*/
|
||||
task automatic read_to_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] rd_size;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR , start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(check_addr_aligned(start_addr)) begin
|
||||
// case(start_addr[31:30])
|
||||
if (start_addr[31:30] === 2'b01) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name);
|
||||
M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name);
|
||||
M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
// end
|
||||
// default : $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
// endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/
|
||||
task automatic write_data;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_transfer_bytes_width:0] wr_size;
|
||||
input [(max_transfer_bytes*8)-1:0] w_data;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(wr_size > max_transfer_bytes) begin
|
||||
$display("[%0d] : %0s : Byte Size supported is 128 bytes only. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size);
|
||||
M_AXI_GP0.write_data(start_addr,wr_size,w_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size);
|
||||
M_AXI_GP1.write_data(start_addr,wr_size,w_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/
|
||||
task automatic read_data;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_transfer_bytes_width:0] rd_size;
|
||||
output[(max_transfer_bytes*8)-1:0] rd_data;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range 'read_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(rd_size > max_transfer_bytes) begin
|
||||
$display("[%0d] : %0s : Byte Size supported is 128 bytes only.'read_data' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size);
|
||||
M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size);
|
||||
M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'read_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* Hooks to call to VIP APIs */
|
||||
task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === 2'b01) begin
|
||||
// end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
// end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
|
||||
reg[511:0] rsp; /// string for response
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst_concurrent' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === 2'b01) begin
|
||||
// end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
// end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst_concurrent' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic read_burst;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [axi_len_width-1:0] len;
|
||||
input [axi_size_width-1:0] siz;
|
||||
input [axi_brst_type_width-1:0] burst;
|
||||
input [axi_lock_width-1:0] lck;
|
||||
input [axi_cache_width-1:0] cache;
|
||||
input [axi_prot_width-1:0] prot;
|
||||
output [(axi_mgp_data_width*axi_burst_len)-1:0] data;
|
||||
output [(axi_rsp_width*axi_burst_len)-1:0] response;
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'read_burst' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === 2'b01) begin
|
||||
// end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr);
|
||||
M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
// end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr);
|
||||
M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'read_burst' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic wait_reg_update;
|
||||
input [addr_width-1:0] addr;
|
||||
input [data_width-1:0] data_i;
|
||||
input [data_width-1:0] mask_i;
|
||||
input [int_width-1:0] time_interval;
|
||||
input [int_width-1:0] time_out;
|
||||
output [data_width-1:0] data_o;
|
||||
|
||||
reg upd_done0;
|
||||
reg upd_done1;
|
||||
begin
|
||||
if(!check_master_address(addr)) begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out of range. 'wait_reg_update' call failed ...\n",$time, DISP_ERR, addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(addr[31:30] === 2'b01) begin
|
||||
// end else if(addr[31:30] === GP_M0) begin
|
||||
if(reg_update_key_0) begin
|
||||
reg_update_key_0 = 0;
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i);
|
||||
M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0);
|
||||
if(DEBUG_INFO && upd_done0)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr);
|
||||
reg_update_key_0 = 1;
|
||||
end else
|
||||
$display("[%0d] : M_AXI_GP0 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
|
||||
end else if(addr[31:30] === 2'b10) begin
|
||||
// end else if(addr[31:30] === GP_M1) begin
|
||||
if(reg_update_key_1) begin
|
||||
reg_update_key_1 = 0;
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i);
|
||||
M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1);
|
||||
if(DEBUG_INFO && upd_done1)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr);
|
||||
reg_update_key_1 = 1;
|
||||
end else
|
||||
$display("[%0d] : M_AXI_GP1 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'wait_reg_update' call failed ... \n",$time, DISP_ERR, addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to read register map */
|
||||
task read_register_map;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_regs_width:0] no_of_registers;
|
||||
output[max_burst_bits-1 :0] data;
|
||||
reg [max_regs_width:0] no_of_regs;
|
||||
begin
|
||||
no_of_regs = no_of_registers;
|
||||
if(no_of_registers > 32) begin
|
||||
$display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\n Only 32 registers will be read.",$time, DISP_ERR, start_addr);
|
||||
no_of_regs = 32;
|
||||
end
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
if(decode_address(start_addr) == REG_MEM) begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO, start_addr,no_of_regs );
|
||||
regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, start_addr, data );
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
end else begin
|
||||
data = 0;
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to read single register */
|
||||
task read_register;
|
||||
input [addr_width-1:0] addr;
|
||||
output[data_width-1:0] data;
|
||||
begin
|
||||
if(check_addr_aligned(addr)) begin
|
||||
if(decode_address(addr) == REG_MEM) begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO, addr );
|
||||
regc.regm.get_data(addr >> 2, data);
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, addr, data );
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register' call failed ...",$time, DISP_ERR, addr);
|
||||
end
|
||||
end else begin
|
||||
data = 0;
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register' call failed ...",$time, DISP_ERR, addr);
|
||||
end
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to set the AXI-Slave profile*/
|
||||
task automatic set_slave_profile;
|
||||
input[1023:0] name;
|
||||
input[1:0] latency ;
|
||||
begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO, name);
|
||||
case(name)
|
||||
"S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency);
|
||||
"S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency);
|
||||
"S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency);
|
||||
"S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency);
|
||||
"S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency);
|
||||
"S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency);
|
||||
"S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency);
|
||||
"ALL" : begin
|
||||
S_AXI_GP0.set_latency_type(latency);
|
||||
S_AXI_GP1.set_latency_type(latency);
|
||||
S_AXI_HP0.set_latency_type(latency);
|
||||
S_AXI_HP1.set_latency_type(latency);
|
||||
S_AXI_HP2.set_latency_type(latency);
|
||||
S_AXI_HP3.set_latency_type(latency);
|
||||
S_AXI_ACP.set_latency_type(latency);
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
/*------------------------------ LOCAL APIs ------------------------------------------------ */
|
||||
|
||||
/* local API for address decoding*/
|
||||
function automatic [1:0] decode_address;
|
||||
input [addr_width-1:0] address;
|
||||
begin
|
||||
if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr ))
|
||||
decode_address = OCM_MEM; /// OCM
|
||||
else if(address >= ddr_start_addr && address <= ddr_end_addr)
|
||||
decode_address = DDR_MEM; /// DDR
|
||||
else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr)
|
||||
decode_address = OCM_MEM; /// OCM
|
||||
else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr)
|
||||
decode_address = REG_MEM; /// Register Map
|
||||
else
|
||||
decode_address = INVALID_MEM_TYPE; /// ERROR in Address
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* local API for checking address is 32-bit (4-byte) aligned */
|
||||
function automatic check_addr_aligned;
|
||||
input [addr_width-1:0] address;
|
||||
begin
|
||||
if((address%4) !=0 ) begin //
|
||||
check_addr_aligned = 0; ///not_aligned
|
||||
end else
|
||||
check_addr_aligned = 1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* local API to check address for GP Masters */
|
||||
function check_master_address;
|
||||
input [addr_width-1:0] address;
|
||||
begin
|
||||
if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr)
|
||||
check_master_address = 1'b1;
|
||||
else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr)
|
||||
check_master_address = 1'b1;
|
||||
else
|
||||
check_master_address = 1'b0; /// ERROR in Address
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* Response decode */
|
||||
function automatic [511:0] get_resp;
|
||||
input[axi_rsp_width-1:0] response;
|
||||
begin
|
||||
case(response)
|
||||
2'b00 : get_resp = "OKAY";
|
||||
2'b01 : get_resp = "EXOKAY";
|
||||
2'b10 : get_resp = "SLVERR";
|
||||
2'b11 : get_resp = "DECERR";
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
+94
@@ -0,0 +1,94 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_axi_acp.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Connections for ACP port
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* AXI Slave ACP */
|
||||
processing_system7_vip_v1_0_7_axi_slave_acp #( C_USE_S_AXI_ACP, // enable
|
||||
axi_acp_name, // name
|
||||
axi_acp_data_width, // data width
|
||||
addr_width, /// address width
|
||||
axi_acp_id_width, // ID width
|
||||
C_S_AXI_ACP_BASEADDR, // slave base address
|
||||
C_S_AXI_ACP_HIGHADDR,// slave size
|
||||
axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes
|
||||
axi_slv_excl_support, // Exclusive access support
|
||||
axi_acp_wr_outstanding,
|
||||
axi_acp_rd_outstanding)
|
||||
S_AXI_ACP(.S_RESETN (net_axi_acp_rstn),
|
||||
.S_ACLK (S_AXI_ACP_ACLK),
|
||||
// Write Address Channel
|
||||
.S_AWID (S_AXI_ACP_AWID),
|
||||
.S_AWADDR (S_AXI_ACP_AWADDR),
|
||||
.S_AWLEN (S_AXI_ACP_AWLEN),
|
||||
.S_AWSIZE (S_AXI_ACP_AWSIZE),
|
||||
.S_AWBURST (S_AXI_ACP_AWBURST),
|
||||
.S_AWLOCK (S_AXI_ACP_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_ACP_AWCACHE),
|
||||
.S_AWPROT (S_AXI_ACP_AWPROT),
|
||||
.S_AWVALID (S_AXI_ACP_AWVALID),
|
||||
.S_AWREADY (S_AXI_ACP_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.S_WID (S_AXI_ACP_WID),
|
||||
.S_WDATA (S_AXI_ACP_WDATA),
|
||||
.S_WSTRB (S_AXI_ACP_WSTRB),
|
||||
.S_WLAST (S_AXI_ACP_WLAST),
|
||||
.S_WVALID (S_AXI_ACP_WVALID),
|
||||
.S_WREADY (S_AXI_ACP_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.S_BID (S_AXI_ACP_BID),
|
||||
.S_BRESP (S_AXI_ACP_BRESP),
|
||||
.S_BVALID (S_AXI_ACP_BVALID),
|
||||
.S_BREADY (S_AXI_ACP_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.S_ARID (S_AXI_ACP_ARID),
|
||||
.S_ARADDR (S_AXI_ACP_ARADDR),
|
||||
.S_ARLEN (S_AXI_ACP_ARLEN),
|
||||
.S_ARSIZE (S_AXI_ACP_ARSIZE),
|
||||
.S_ARBURST (S_AXI_ACP_ARBURST),
|
||||
.S_ARLOCK (S_AXI_ACP_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_ACP_ARCACHE),
|
||||
.S_ARPROT (S_AXI_ACP_ARPROT),
|
||||
.S_ARVALID (S_AXI_ACP_ARVALID),
|
||||
.S_ARREADY (S_AXI_ACP_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.S_RID (S_AXI_ACP_RID),
|
||||
.S_RDATA (S_AXI_ACP_RDATA),
|
||||
.S_RRESP (S_AXI_ACP_RRESP),
|
||||
.S_RLAST (S_AXI_ACP_RLAST),
|
||||
.S_RVALID (S_AXI_ACP_RVALID),
|
||||
.S_RREADY (S_AXI_ACP_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_ACP_AWQOS),
|
||||
.S_ARQOS (S_AXI_ACP_ARQOS), // Side band signals
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/
|
||||
.WR_DATA_ACK_DDR (ddr_wr_ack_port0),
|
||||
.WR_DATA_ACK_OCM (ocm_wr_ack_port0),
|
||||
.WR_DATA (net_wr_data_acp),
|
||||
.WR_DATA_STRB (net_wr_strb_acp),
|
||||
.WR_ADDR (net_wr_addr_acp),
|
||||
.WR_BYTES (net_wr_bytes_acp),
|
||||
.WR_DATA_VALID_DDR (ddr_wr_dv_port0),
|
||||
.WR_DATA_VALID_OCM (ocm_wr_dv_port0),
|
||||
.WR_QOS (net_wr_qos_acp),
|
||||
|
||||
.RD_REQ_DDR (ddr_rd_req_port0),
|
||||
.RD_REQ_OCM (ocm_rd_req_port0),
|
||||
.RD_REQ_REG (reg_rd_req_port0),
|
||||
.RD_ADDR (net_rd_addr_acp),
|
||||
.RD_DATA_DDR (ddr_rd_data_port0),
|
||||
.RD_DATA_OCM (ocm_rd_data_port0),
|
||||
.RD_DATA_REG (reg_rd_data_port0),
|
||||
.RD_BYTES (net_rd_bytes_acp),
|
||||
.RD_DATA_VALID_DDR (ddr_rd_dv_port0),
|
||||
.RD_DATA_VALID_OCM (ocm_rd_dv_port0),
|
||||
.RD_DATA_VALID_REG (reg_rd_dv_port0),
|
||||
.RD_QOS (net_rd_qos_acp)
|
||||
|
||||
);
|
||||
+311
@@ -0,0 +1,311 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_axi_gp.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Connections for AXI GP ports
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* IDs for Masters
|
||||
// l2m1 (CPU000)
|
||||
12'b11_000_000_00_00
|
||||
12'b11_010_000_00_00
|
||||
12'b11_011_000_00_00
|
||||
12'b11_100_000_00_00
|
||||
12'b11_101_000_00_00
|
||||
12'b11_110_000_00_00
|
||||
12'b11_111_000_00_00
|
||||
// l2m1 (CPU001)
|
||||
12'b11_000_001_00_00
|
||||
12'b11_010_001_00_00
|
||||
12'b11_011_001_00_00
|
||||
12'b11_100_001_00_00
|
||||
12'b11_101_001_00_00
|
||||
12'b11_110_001_00_00
|
||||
12'b11_111_001_00_00
|
||||
*/
|
||||
|
||||
/* AXI -Master GP0 */
|
||||
processing_system7_vip_v1_0_7_axi_master #(C_USE_M_AXI_GP0, // enable
|
||||
axi_mgp0_name,// name
|
||||
axi_mgp_data_width, /// Data Width
|
||||
addr_width, /// Address width
|
||||
axi_mgp_id_width, //// ID Width
|
||||
axi_mgp_outstanding, //// Outstanding transactions
|
||||
axi_mst_excl_support, // EXCL Access Support
|
||||
axi_mgp_wr_id, //WR_ID
|
||||
axi_mgp_rd_id) //RD_ID
|
||||
M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn),
|
||||
.M_ACLK (M_AXI_GP0_ACLK),
|
||||
// Write Address Channel
|
||||
.M_AWID (M_AXI_GP0_AWID_FULL),
|
||||
.M_AWADDR (M_AXI_GP0_AWADDR),
|
||||
.M_AWLEN (M_AXI_GP0_AWLEN),
|
||||
.M_AWSIZE (M_AXI_GP0_AWSIZE),
|
||||
.M_AWBURST (M_AXI_GP0_AWBURST),
|
||||
.M_AWLOCK (M_AXI_GP0_AWLOCK),
|
||||
.M_AWCACHE (M_AXI_GP0_AWCACHE),
|
||||
.M_AWPROT (M_AXI_GP0_AWPROT),
|
||||
.M_AWVALID (M_AXI_GP0_AWVALID),
|
||||
.M_AWREADY (M_AXI_GP0_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.M_WID (M_AXI_GP0_WID_FULL),
|
||||
.M_WDATA (M_AXI_GP0_WDATA),
|
||||
.M_WSTRB (M_AXI_GP0_WSTRB),
|
||||
.M_WLAST (M_AXI_GP0_WLAST),
|
||||
.M_WVALID (M_AXI_GP0_WVALID),
|
||||
.M_WREADY (M_AXI_GP0_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.M_BID (M_AXI_GP0_BID_FULL),
|
||||
.M_BRESP (M_AXI_GP0_BRESP),
|
||||
.M_BVALID (M_AXI_GP0_BVALID),
|
||||
.M_BREADY (M_AXI_GP0_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.M_ARID (M_AXI_GP0_ARID_FULL),
|
||||
.M_ARADDR (M_AXI_GP0_ARADDR),
|
||||
.M_ARLEN (M_AXI_GP0_ARLEN),
|
||||
.M_ARSIZE (M_AXI_GP0_ARSIZE),
|
||||
.M_ARBURST (M_AXI_GP0_ARBURST),
|
||||
.M_ARLOCK (M_AXI_GP0_ARLOCK),
|
||||
.M_ARCACHE (M_AXI_GP0_ARCACHE),
|
||||
.M_ARPROT (M_AXI_GP0_ARPROT),
|
||||
.M_ARVALID (M_AXI_GP0_ARVALID),
|
||||
.M_ARREADY (M_AXI_GP0_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.M_RID (M_AXI_GP0_RID_FULL),
|
||||
.M_RDATA (M_AXI_GP0_RDATA),
|
||||
.M_RRESP (M_AXI_GP0_RRESP),
|
||||
.M_RLAST (M_AXI_GP0_RLAST),
|
||||
.M_RVALID (M_AXI_GP0_RVALID),
|
||||
.M_RREADY (M_AXI_GP0_RREADY),
|
||||
// Side band signals
|
||||
.M_AWQOS (M_AXI_GP0_AWQOS),
|
||||
.M_ARQOS (M_AXI_GP0_ARQOS)
|
||||
);
|
||||
|
||||
/* AXI Master GP1 */
|
||||
processing_system7_vip_v1_0_7_axi_master #(C_USE_M_AXI_GP1, // enable
|
||||
axi_mgp1_name,// name
|
||||
axi_mgp_data_width, /// Data Width
|
||||
addr_width, /// Address width
|
||||
axi_mgp_id_width, //// ID Width
|
||||
axi_mgp_outstanding, //// Outstanding transactions
|
||||
axi_mst_excl_support, // EXCL Access Support
|
||||
axi_mgp_wr_id, //WR_ID
|
||||
axi_mgp_rd_id) //RD_ID
|
||||
M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn),
|
||||
.M_ACLK (M_AXI_GP1_ACLK),
|
||||
// Write Address Channel
|
||||
.M_AWID (M_AXI_GP1_AWID_FULL),
|
||||
.M_AWADDR (M_AXI_GP1_AWADDR),
|
||||
.M_AWLEN (M_AXI_GP1_AWLEN),
|
||||
.M_AWSIZE (M_AXI_GP1_AWSIZE),
|
||||
.M_AWBURST (M_AXI_GP1_AWBURST),
|
||||
.M_AWLOCK (M_AXI_GP1_AWLOCK),
|
||||
.M_AWCACHE (M_AXI_GP1_AWCACHE),
|
||||
.M_AWPROT (M_AXI_GP1_AWPROT),
|
||||
.M_AWVALID (M_AXI_GP1_AWVALID),
|
||||
.M_AWREADY (M_AXI_GP1_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.M_WID (M_AXI_GP1_WID_FULL),
|
||||
.M_WDATA (M_AXI_GP1_WDATA),
|
||||
.M_WSTRB (M_AXI_GP1_WSTRB),
|
||||
.M_WLAST (M_AXI_GP1_WLAST),
|
||||
.M_WVALID (M_AXI_GP1_WVALID),
|
||||
.M_WREADY (M_AXI_GP1_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.M_BID (M_AXI_GP1_BID_FULL),
|
||||
.M_BRESP (M_AXI_GP1_BRESP),
|
||||
.M_BVALID (M_AXI_GP1_BVALID),
|
||||
.M_BREADY (M_AXI_GP1_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.M_ARID (M_AXI_GP1_ARID_FULL),
|
||||
.M_ARADDR (M_AXI_GP1_ARADDR),
|
||||
.M_ARLEN (M_AXI_GP1_ARLEN),
|
||||
.M_ARSIZE (M_AXI_GP1_ARSIZE),
|
||||
.M_ARBURST (M_AXI_GP1_ARBURST),
|
||||
.M_ARLOCK (M_AXI_GP1_ARLOCK),
|
||||
.M_ARCACHE (M_AXI_GP1_ARCACHE),
|
||||
.M_ARPROT (M_AXI_GP1_ARPROT),
|
||||
.M_ARVALID (M_AXI_GP1_ARVALID),
|
||||
.M_ARREADY (M_AXI_GP1_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.M_RID (M_AXI_GP1_RID_FULL),
|
||||
.M_RDATA (M_AXI_GP1_RDATA),
|
||||
.M_RRESP (M_AXI_GP1_RRESP),
|
||||
.M_RLAST (M_AXI_GP1_RLAST),
|
||||
.M_RVALID (M_AXI_GP1_RVALID),
|
||||
.M_RREADY (M_AXI_GP1_RREADY),
|
||||
// Side band signals
|
||||
.M_AWQOS (M_AXI_GP1_AWQOS),
|
||||
.M_ARQOS (M_AXI_GP1_ARQOS)
|
||||
);
|
||||
|
||||
/* AXI Slave GP0 */
|
||||
processing_system7_vip_v1_0_7_axi_slave #(C_USE_S_AXI_GP0, /// enable
|
||||
axi_sgp0_name, //name
|
||||
axi_sgp_data_width, /// data width
|
||||
addr_width, /// address width
|
||||
axi_sgp_id_width, /// ID width
|
||||
C_S_AXI_GP0_BASEADDR,//// base address
|
||||
C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr)
|
||||
axi_sgp_outstanding, // outstanding transactions
|
||||
axi_slv_excl_support, // exclusive access not supported
|
||||
axi_sgp_wr_outstanding,
|
||||
axi_sgp_rd_outstanding)
|
||||
S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn),
|
||||
.S_ACLK (S_AXI_GP0_ACLK),
|
||||
// Write Address Channel
|
||||
.S_AWID (S_AXI_GP0_AWID),
|
||||
.S_AWADDR (S_AXI_GP0_AWADDR),
|
||||
.S_AWLEN (S_AXI_GP0_AWLEN),
|
||||
.S_AWSIZE (S_AXI_GP0_AWSIZE),
|
||||
.S_AWBURST (S_AXI_GP0_AWBURST),
|
||||
.S_AWLOCK (S_AXI_GP0_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_GP0_AWCACHE),
|
||||
.S_AWPROT (S_AXI_GP0_AWPROT),
|
||||
.S_AWVALID (S_AXI_GP0_AWVALID),
|
||||
.S_AWREADY (S_AXI_GP0_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.S_WID (S_AXI_GP0_WID),
|
||||
.S_WDATA (S_AXI_GP0_WDATA),
|
||||
.S_WSTRB (S_AXI_GP0_WSTRB),
|
||||
.S_WLAST (S_AXI_GP0_WLAST),
|
||||
.S_WVALID (S_AXI_GP0_WVALID),
|
||||
.S_WREADY (S_AXI_GP0_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.S_BID (S_AXI_GP0_BID),
|
||||
.S_BRESP (S_AXI_GP0_BRESP),
|
||||
.S_BVALID (S_AXI_GP0_BVALID),
|
||||
.S_BREADY (S_AXI_GP0_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.S_ARID (S_AXI_GP0_ARID),
|
||||
.S_ARADDR (S_AXI_GP0_ARADDR),
|
||||
.S_ARLEN (S_AXI_GP0_ARLEN),
|
||||
.S_ARSIZE (S_AXI_GP0_ARSIZE),
|
||||
.S_ARBURST (S_AXI_GP0_ARBURST),
|
||||
.S_ARLOCK (S_AXI_GP0_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_GP0_ARCACHE),
|
||||
.S_ARPROT (S_AXI_GP0_ARPROT),
|
||||
.S_ARVALID (S_AXI_GP0_ARVALID),
|
||||
.S_ARREADY (S_AXI_GP0_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.S_RID (S_AXI_GP0_RID),
|
||||
.S_RDATA (S_AXI_GP0_RDATA),
|
||||
.S_RRESP (S_AXI_GP0_RRESP),
|
||||
.S_RLAST (S_AXI_GP0_RLAST),
|
||||
.S_RVALID (S_AXI_GP0_RVALID),
|
||||
.S_RREADY (S_AXI_GP0_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_GP0_AWQOS),
|
||||
.S_ARQOS (S_AXI_GP0_ARQOS),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0),
|
||||
.WR_DATA (net_wr_data_gp0),
|
||||
.WR_DATA_STRB (net_wr_strb_gp0),
|
||||
.WR_ADDR (net_wr_addr_gp0),
|
||||
.WR_BYTES (net_wr_bytes_gp0),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_gp0),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_gp0),
|
||||
.WR_QOS (net_wr_qos_gp0),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_gp0),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_gp0),
|
||||
.RD_REQ_REG (net_rd_req_reg_gp0),
|
||||
.RD_ADDR (net_rd_addr_gp0),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_gp0),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_gp0),
|
||||
.RD_DATA_REG (net_rd_data_reg_gp0),
|
||||
.RD_BYTES (net_rd_bytes_gp0),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0),
|
||||
.RD_DATA_VALID_REG (net_rd_dv_reg_gp0),
|
||||
.RD_QOS (net_rd_qos_gp0)
|
||||
|
||||
);
|
||||
|
||||
/* AXI Slave GP1 */
|
||||
processing_system7_vip_v1_0_7_axi_slave #(C_USE_S_AXI_GP1, /// enable
|
||||
axi_sgp1_name, //name
|
||||
axi_sgp_data_width, /// data width
|
||||
addr_width, /// address width
|
||||
axi_sgp_id_width, /// ID width
|
||||
C_S_AXI_GP1_BASEADDR,//// base address
|
||||
C_S_AXI_GP1_HIGHADDR,/// HIGh_addr
|
||||
axi_sgp_outstanding, // outstanding transactions
|
||||
axi_slv_excl_support, // exclusive access
|
||||
axi_sgp_wr_outstanding,
|
||||
axi_sgp_rd_outstanding)
|
||||
S_AXI_GP1(.S_RESETN (net_axi_gp1_rstn),
|
||||
.S_ACLK (S_AXI_GP1_ACLK),
|
||||
// Write Address Channel
|
||||
.S_AWID (S_AXI_GP1_AWID),
|
||||
.S_AWADDR (S_AXI_GP1_AWADDR),
|
||||
.S_AWLEN (S_AXI_GP1_AWLEN),
|
||||
.S_AWSIZE (S_AXI_GP1_AWSIZE),
|
||||
.S_AWBURST (S_AXI_GP1_AWBURST),
|
||||
.S_AWLOCK (S_AXI_GP1_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_GP1_AWCACHE),
|
||||
.S_AWPROT (S_AXI_GP1_AWPROT),
|
||||
.S_AWVALID (S_AXI_GP1_AWVALID),
|
||||
.S_AWREADY (S_AXI_GP1_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.S_WID (S_AXI_GP1_WID),
|
||||
.S_WDATA (S_AXI_GP1_WDATA),
|
||||
.S_WSTRB (S_AXI_GP1_WSTRB),
|
||||
.S_WLAST (S_AXI_GP1_WLAST),
|
||||
.S_WVALID (S_AXI_GP1_WVALID),
|
||||
.S_WREADY (S_AXI_GP1_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.S_BID (S_AXI_GP1_BID),
|
||||
.S_BRESP (S_AXI_GP1_BRESP),
|
||||
.S_BVALID (S_AXI_GP1_BVALID),
|
||||
.S_BREADY (S_AXI_GP1_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.S_ARID (S_AXI_GP1_ARID),
|
||||
.S_ARADDR (S_AXI_GP1_ARADDR),
|
||||
.S_ARLEN (S_AXI_GP1_ARLEN),
|
||||
.S_ARSIZE (S_AXI_GP1_ARSIZE),
|
||||
.S_ARBURST (S_AXI_GP1_ARBURST),
|
||||
.S_ARLOCK (S_AXI_GP1_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_GP1_ARCACHE),
|
||||
.S_ARPROT (S_AXI_GP1_ARPROT),
|
||||
.S_ARVALID (S_AXI_GP1_ARVALID),
|
||||
.S_ARREADY (S_AXI_GP1_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.S_RID (S_AXI_GP1_RID),
|
||||
.S_RDATA (S_AXI_GP1_RDATA),
|
||||
.S_RRESP (S_AXI_GP1_RRESP),
|
||||
.S_RLAST (S_AXI_GP1_RLAST),
|
||||
.S_RVALID (S_AXI_GP1_RVALID),
|
||||
.S_RREADY (S_AXI_GP1_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_GP1_AWQOS),
|
||||
.S_ARQOS (S_AXI_GP1_ARQOS),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1),
|
||||
.WR_DATA (net_wr_data_gp1),
|
||||
.WR_DATA_STRB (net_wr_strb_gp1),
|
||||
.WR_ADDR (net_wr_addr_gp1),
|
||||
.WR_BYTES (net_wr_bytes_gp1),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_gp1),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_gp1),
|
||||
.WR_QOS (net_wr_qos_gp1),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_gp1),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_gp1),
|
||||
.RD_REQ_REG (net_rd_req_reg_gp1),
|
||||
.RD_ADDR (net_rd_addr_gp1),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_gp1),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_gp1),
|
||||
.RD_DATA_REG (net_rd_data_reg_gp1),
|
||||
.RD_BYTES (net_rd_bytes_gp1),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1),
|
||||
.RD_DATA_VALID_REG (net_rd_dv_reg_gp1),
|
||||
.RD_QOS (net_rd_qos_gp1)
|
||||
|
||||
);
|
||||
+350
@@ -0,0 +1,350 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_axi_hp.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Connections for AXI HP ports
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* AXI Slave HP0 */
|
||||
processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP0, // enable
|
||||
axi_hp0_name, // name
|
||||
C_S_AXI_HP0_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP0_BASEADDR, // slave base address
|
||||
C_S_AXI_HP0_HIGHADDR, // slave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn),
|
||||
.S_ACLK (S_AXI_HP0_ACLK),
|
||||
// Write Address channel
|
||||
.S_AWID (S_AXI_HP0_AWID),
|
||||
.S_AWADDR (S_AXI_HP0_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP0_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP0_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP0_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP0_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP0_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP0_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP0_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP0_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP0_WID),
|
||||
.S_WDATA (S_AXI_HP0_WDATA),
|
||||
.S_WSTRB (S_AXI_HP0_WSTRB),
|
||||
.S_WLAST (S_AXI_HP0_WLAST),
|
||||
.S_WVALID (S_AXI_HP0_WVALID),
|
||||
.S_WREADY (S_AXI_HP0_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP0_BID),
|
||||
.S_BRESP (S_AXI_HP0_BRESP),
|
||||
.S_BVALID (S_AXI_HP0_BVALID),
|
||||
.S_BREADY (S_AXI_HP0_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP0_ARID),
|
||||
.S_ARADDR (S_AXI_HP0_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP0_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP0_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP0_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP0_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP0_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP0_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP0_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP0_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP0_RID),
|
||||
.S_RDATA (S_AXI_HP0_RDATA),
|
||||
.S_RRESP (S_AXI_HP0_RRESP),
|
||||
.S_RLAST (S_AXI_HP0_RLAST),
|
||||
.S_RVALID (S_AXI_HP0_RVALID),
|
||||
.S_RREADY (S_AXI_HP0_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP0_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP0_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP0_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP0_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP0_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP0_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0),
|
||||
.WR_DATA (net_wr_data_hp0),
|
||||
.WR_DATA_STRB (net_wr_strb_hp0),
|
||||
.WR_ADDR (net_wr_addr_hp0),
|
||||
.WR_BYTES (net_wr_bytes_hp0),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp0),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp0),
|
||||
.WR_QOS (net_wr_qos_hp0),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp0),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp0),
|
||||
.RD_ADDR (net_rd_addr_hp0),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp0),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp0),
|
||||
.RD_BYTES (net_rd_bytes_hp0),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0),
|
||||
.RD_QOS (net_rd_qos_hp0)
|
||||
);
|
||||
|
||||
/* AXI Slave HP1 */
|
||||
processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP1, // enable
|
||||
axi_hp1_name, // name
|
||||
C_S_AXI_HP1_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP1_BASEADDR, // slave base address
|
||||
C_S_AXI_HP1_HIGHADDR, // Slave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn),
|
||||
.S_ACLK (S_AXI_HP1_ACLK),
|
||||
// Write Address channel
|
||||
.S_AWID (S_AXI_HP1_AWID),
|
||||
.S_AWADDR (S_AXI_HP1_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP1_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP1_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP1_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP1_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP1_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP1_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP1_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP1_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP1_WID),
|
||||
.S_WDATA (S_AXI_HP1_WDATA),
|
||||
.S_WSTRB (S_AXI_HP1_WSTRB),
|
||||
.S_WLAST (S_AXI_HP1_WLAST),
|
||||
.S_WVALID (S_AXI_HP1_WVALID),
|
||||
.S_WREADY (S_AXI_HP1_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP1_BID),
|
||||
.S_BRESP (S_AXI_HP1_BRESP),
|
||||
.S_BVALID (S_AXI_HP1_BVALID),
|
||||
.S_BREADY (S_AXI_HP1_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP1_ARID),
|
||||
.S_ARADDR (S_AXI_HP1_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP1_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP1_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP1_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP1_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP1_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP1_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP1_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP1_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP1_RID),
|
||||
.S_RDATA (S_AXI_HP1_RDATA),
|
||||
.S_RRESP (S_AXI_HP1_RRESP),
|
||||
.S_RLAST (S_AXI_HP1_RLAST),
|
||||
.S_RVALID (S_AXI_HP1_RVALID),
|
||||
.S_RREADY (S_AXI_HP1_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP1_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP1_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP1_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP1_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP1_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP1_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1),
|
||||
.WR_DATA (net_wr_data_hp1),
|
||||
.WR_DATA_STRB (net_wr_strb_hp1),
|
||||
.WR_ADDR (net_wr_addr_hp1),
|
||||
.WR_BYTES (net_wr_bytes_hp1),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1),
|
||||
.WR_QOS (net_wr_qos_hp1),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp1),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp1),
|
||||
.RD_ADDR (net_rd_addr_hp1),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp1),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp1),
|
||||
.RD_BYTES (net_rd_bytes_hp1),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1),
|
||||
.RD_QOS (net_rd_qos_hp1)
|
||||
|
||||
);
|
||||
|
||||
/* AXI Slave HP2 */
|
||||
processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP2, // enable
|
||||
axi_hp2_name, // name
|
||||
C_S_AXI_HP2_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP2_BASEADDR, // slave base address
|
||||
C_S_AXI_HP2_HIGHADDR, // SLave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn),
|
||||
.S_ACLK (S_AXI_HP2_ACLK),
|
||||
// Write Address channel
|
||||
.S_AWID (S_AXI_HP2_AWID),
|
||||
.S_AWADDR (S_AXI_HP2_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP2_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP2_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP2_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP2_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP2_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP2_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP2_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP2_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP2_WID),
|
||||
.S_WDATA (S_AXI_HP2_WDATA),
|
||||
.S_WSTRB (S_AXI_HP2_WSTRB),
|
||||
.S_WLAST (S_AXI_HP2_WLAST),
|
||||
.S_WVALID (S_AXI_HP2_WVALID),
|
||||
.S_WREADY (S_AXI_HP2_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP2_BID),
|
||||
.S_BRESP (S_AXI_HP2_BRESP),
|
||||
.S_BVALID (S_AXI_HP2_BVALID),
|
||||
.S_BREADY (S_AXI_HP2_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP2_ARID),
|
||||
.S_ARADDR (S_AXI_HP2_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP2_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP2_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP2_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP2_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP2_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP2_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP2_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP2_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP2_RID),
|
||||
.S_RDATA (S_AXI_HP2_RDATA),
|
||||
.S_RRESP (S_AXI_HP2_RRESP),
|
||||
.S_RLAST (S_AXI_HP2_RLAST),
|
||||
.S_RVALID (S_AXI_HP2_RVALID),
|
||||
.S_RREADY (S_AXI_HP2_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP2_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP2_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP2_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP2_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP2_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP2_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2),
|
||||
.WR_DATA (net_wr_data_hp2),
|
||||
.WR_DATA_STRB (net_wr_strb_hp2),
|
||||
.WR_ADDR (net_wr_addr_hp2),
|
||||
.WR_BYTES (net_wr_bytes_hp2),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp2),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp2),
|
||||
.WR_QOS (net_wr_qos_hp2),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp2),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp2),
|
||||
.RD_ADDR (net_rd_addr_hp2),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp2),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp2),
|
||||
.RD_BYTES (net_rd_bytes_hp2),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2),
|
||||
.RD_QOS (net_rd_qos_hp2)
|
||||
|
||||
);
|
||||
|
||||
/* AXI Slave HP3 */
|
||||
processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP3, // enable
|
||||
axi_hp3_name, // name
|
||||
C_S_AXI_HP3_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP3_BASEADDR, // slave base address
|
||||
C_S_AXI_HP3_HIGHADDR, // SLave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn),
|
||||
.S_ACLK (S_AXI_HP3_ACLK),
|
||||
// Write ADDRESS CHANNEL
|
||||
.S_AWID (S_AXI_HP3_AWID),
|
||||
.S_AWADDR (S_AXI_HP3_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP3_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP3_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP3_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP3_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP3_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP3_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP3_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP3_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP3_WID),
|
||||
.S_WDATA (S_AXI_HP3_WDATA),
|
||||
.S_WSTRB (S_AXI_HP3_WSTRB),
|
||||
.S_WLAST (S_AXI_HP3_WLAST),
|
||||
.S_WVALID (S_AXI_HP3_WVALID),
|
||||
.S_WREADY (S_AXI_HP3_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP3_BID),
|
||||
.S_BRESP (S_AXI_HP3_BRESP),
|
||||
.S_BVALID (S_AXI_HP3_BVALID),
|
||||
.S_BREADY (S_AXI_HP3_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP3_ARID),
|
||||
.S_ARADDR (S_AXI_HP3_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP3_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP3_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP3_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP3_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP3_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP3_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP3_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP3_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP3_RID),
|
||||
.S_RDATA (S_AXI_HP3_RDATA),
|
||||
.S_RRESP (S_AXI_HP3_RRESP),
|
||||
.S_RLAST (S_AXI_HP3_RLAST),
|
||||
.S_RVALID (S_AXI_HP3_RVALID),
|
||||
.S_RREADY (S_AXI_HP3_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP3_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP3_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP3_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP3_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP3_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP3_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3),
|
||||
.WR_DATA (net_wr_data_hp3),
|
||||
.WR_DATA_STRB (net_wr_strb_hp3),
|
||||
.WR_ADDR (net_wr_addr_hp3),
|
||||
.WR_BYTES (net_wr_bytes_hp3),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp3),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp3),
|
||||
.WR_QOS (net_wr_qos_hp3),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp3),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp3),
|
||||
.RD_ADDR (net_rd_addr_hp3),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp3),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp3),
|
||||
.RD_BYTES (net_rd_bytes_hp3),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3),
|
||||
.RD_QOS (net_rd_qos_hp3)
|
||||
);
|
||||
+244
@@ -0,0 +1,244 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_local_params.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Parameters used in Zynq VIP
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/* local */
|
||||
parameter m_axi_gp0_baseaddr = 32'h4000_0000;
|
||||
parameter m_axi_gp1_baseaddr = 32'h8000_0000;
|
||||
parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF;
|
||||
parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF;
|
||||
|
||||
parameter addr_width = 32; // maximum address width
|
||||
parameter data_width = 32; // maximum data width.
|
||||
parameter max_chars = 128; // max characters for file name
|
||||
parameter mem_width = data_width/8; /// memory width in bytes
|
||||
parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted
|
||||
parameter int_width = 32; //integre width
|
||||
|
||||
/* for internal read/write APIs used for data transfers */
|
||||
parameter max_burst_len = 16; /// maximum brst length on axi
|
||||
parameter max_data_width = 64; // maximum data width for internal AXI bursts
|
||||
parameter max_burst_bits = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts
|
||||
parameter max_burst_bytes = (max_burst_bits)/8; // maximum data bytes in each transfer
|
||||
parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts
|
||||
|
||||
parameter max_registers = 32;
|
||||
parameter max_regs_width = clogb2(max_registers);
|
||||
|
||||
parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11;
|
||||
|
||||
/* Interrupt bits supported */
|
||||
parameter irq_width = 16;
|
||||
|
||||
/* GP Master0 & Master1 address decode */
|
||||
parameter GP_M0 = 2'b01;
|
||||
parameter GP_M1 = 2'b10;
|
||||
|
||||
parameter ALL_RANDOM= 2'b00;
|
||||
parameter ALL_ZEROS = 2'b01;
|
||||
parameter ALL_ONES = 2'b10;
|
||||
|
||||
parameter ddr_start_addr = 32'h0008_0000;
|
||||
parameter ddr_end_addr = 32'h7FFF_FFFF;
|
||||
|
||||
parameter ocm_start_addr = 32'h0000_0000;
|
||||
parameter ocm_end_addr = 32'h0003_FFFF;
|
||||
parameter high_ocm_start_addr = 32'hFFFC_0000;
|
||||
parameter high_ocm_end_addr = 32'hFFFF_FFFF;
|
||||
parameter ocm_low_addr = 32'hFFFF_0000;
|
||||
|
||||
parameter reg_start_addr = 32'hE000_0000;
|
||||
parameter reg_end_addr = 32'hF8F0_2F80;
|
||||
|
||||
|
||||
/* for Master port APIs and AXI protocol related signal widths*/
|
||||
parameter axi_burst_len = 16;
|
||||
parameter axi_len_width = clogb2(axi_burst_len);
|
||||
parameter axi_size_width = 3;
|
||||
parameter axi_brst_type_width = 2;
|
||||
parameter axi_lock_width = 2;
|
||||
parameter axi_cache_width = 4;
|
||||
parameter axi_prot_width = 3;
|
||||
parameter axi_rsp_width = 2;
|
||||
parameter axi_mgp_data_width = 32;
|
||||
parameter axi_mgp_id_width = 12;
|
||||
parameter axi_mgp_outstanding = 8;
|
||||
parameter axi_mgp_wr_id = 12'hC00;
|
||||
parameter axi_mgp_rd_id = 12'hC0C;
|
||||
parameter axi_mgp0_name = "M_AXI_GP0";
|
||||
parameter axi_mgp1_name = "M_AXI_GP1";
|
||||
parameter axi_qos_width = 4;
|
||||
parameter max_transfer_bytes = 256; // For Master APIs.
|
||||
parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs.
|
||||
|
||||
|
||||
/* for GP slave ports*/
|
||||
parameter axi_sgp_data_width = 32;
|
||||
parameter axi_sgp_id_width = 6;
|
||||
parameter axi_sgp_rd_outstanding = 8;
|
||||
parameter axi_sgp_wr_outstanding = 8;
|
||||
parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding;
|
||||
parameter axi_sgp0_name = "S_AXI_GP0";
|
||||
parameter axi_sgp1_name = "S_AXI_GP1";
|
||||
|
||||
/* for ACP slave ports*/
|
||||
parameter axi_acp_data_width = 64;
|
||||
parameter axi_acp_id_width = 3;
|
||||
parameter axi_acp_rd_outstanding = 7;
|
||||
parameter axi_acp_wr_outstanding = 3;
|
||||
parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding;
|
||||
parameter axi_acp_name = "S_AXI_ACP";
|
||||
|
||||
/* for HP slave ports*/
|
||||
parameter axi_hp_id_width = 6;
|
||||
parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT ..
|
||||
parameter axi_hp0_name = "S_AXI_HP0";
|
||||
parameter axi_hp1_name = "S_AXI_HP1";
|
||||
parameter axi_hp2_name = "S_AXI_HP2";
|
||||
parameter axi_hp3_name = "S_AXI_HP3";
|
||||
|
||||
|
||||
parameter axi_slv_excl_support = 0; // For Slave ports EXCL access is not supported
|
||||
parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported
|
||||
|
||||
/* AXI transfer types */
|
||||
parameter AXI_FIXED = 2'b00;
|
||||
parameter AXI_INCR = 2'b01;
|
||||
parameter AXI_WRAP = 2'b10;
|
||||
|
||||
/* Exclusive Access */
|
||||
parameter AXI_NRML = 2'b00;
|
||||
parameter AXI_EXCL = 2'b01;
|
||||
parameter AXI_LOCK = 2'b10;
|
||||
|
||||
/* AXI Response types */
|
||||
parameter AXI_OK = 2'b00;
|
||||
parameter AXI_EXCL_OK = 2'b01;
|
||||
parameter AXI_SLV_ERR = 2'b10;
|
||||
parameter AXI_DEC_ERR = 2'b11;
|
||||
|
||||
function automatic integer clogb2;
|
||||
input [31:0] value;
|
||||
begin
|
||||
value = value - 1;
|
||||
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
|
||||
value = value >> 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* needed only for AFI modules and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */
|
||||
/* WR FIFO data */
|
||||
// parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
|
||||
// parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
|
||||
// parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1);
|
||||
// parameter wr_bytes_lsb = 0;
|
||||
// parameter wr_bytes_msb = max_burst_bytes_width;
|
||||
// parameter wr_addr_lsb = wr_bytes_msb + 1;
|
||||
// parameter wr_addr_msb = wr_addr_lsb + addr_width-1;
|
||||
// parameter wr_data_lsb = wr_addr_msb + 1;
|
||||
// parameter wr_data_msb = wr_data_lsb + max_burst_bits-1;
|
||||
// parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1;
|
||||
// parameter wr_qos_lsb = wr_data_msb + 1;
|
||||
// `parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1;
|
||||
|
||||
/* WR AFI FIFO data */
|
||||
/* ID - 1071:1066
|
||||
Resp - 1065:1064
|
||||
data - 1063:40
|
||||
address - 39:8
|
||||
valid_bytes - 7:0
|
||||
*/
|
||||
// parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1);
|
||||
// parameter wr_afi_bytes_lsb = 0;
|
||||
// parameter wr_afi_bytes_msb = max_burst_bytes_width;
|
||||
// parameter wr_afi_addr_lsb = wr_afi_bytes_msb + 1;
|
||||
// parameter wr_afi_addr_msb = wr_afi_addr_lsb + addr_width-1;
|
||||
// parameter wr_afi_data_lsb = wr_afi_addr_msb + 1;
|
||||
// parameter wr_afi_rsp_msb = wr_afi_rsp_lsb + axi_rsp_width-1;
|
||||
// parameter wr_afi_id_lsb = wr_afi_rsp_msb + 1;
|
||||
// parameter wr_afi_id_msb = wr_afi_id_lsb + axi_hp_id_width-1;
|
||||
// parameter wr_afi_ln_lsb = wr_afi_id_msb + 1;
|
||||
// parameter wr_afi_ln_msb = wr_afi_ln_lsb + axi_len_width-1;
|
||||
// parameter wr_afi_qos_lsb = wr_afi_ln_msb + 1;
|
||||
// parameter wr_afi_qos_msb = wr_afi_qos_lsb + axi_qos_width-1;
|
||||
|
||||
|
||||
parameter afi_fifo_size = 1024; /// AFI FIFO is stored as 1024-bytes
|
||||
parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes)
|
||||
parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location
|
||||
|
||||
/* for interconnect fifo models */
|
||||
parameter intr_max_outstanding = 8;
|
||||
parameter intr_cnt_width = clogb2(intr_max_outstanding)+1;
|
||||
parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width + axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1);
|
||||
parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ;
|
||||
|
||||
//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
|
||||
parameter rd_afi_bytes_lsb = 0;
|
||||
parameter rd_afi_bytes_msb = max_burst_bytes_width;
|
||||
parameter rd_afi_rsp_lsb = rd_afi_bytes_msb + 1;
|
||||
parameter rd_afi_rsp_msb = rd_afi_rsp_lsb + axi_rsp_width-1;
|
||||
parameter rd_afi_id_lsb = rd_afi_rsp_msb + 1;
|
||||
parameter rd_afi_id_msb = rd_afi_id_lsb + axi_hp_id_width-1;
|
||||
parameter rd_afi_ln_lsb = rd_afi_id_msb + 1;
|
||||
parameter rd_afi_ln_msb = rd_afi_ln_lsb + axi_len_width-1;
|
||||
parameter rd_afi_brst_lsb = rd_afi_ln_msb + 1;
|
||||
parameter rd_afi_brst_msb = rd_afi_brst_lsb + axi_brst_type_width-1;
|
||||
parameter rd_afi_siz_lsb = rd_afi_brst_msb + 1;
|
||||
parameter rd_afi_siz_msb = rd_afi_siz_lsb + axi_size_width-1;
|
||||
parameter rd_afi_addr_lsb = rd_afi_siz_msb + 1;
|
||||
parameter rd_afi_addr_msb = rd_afi_addr_lsb + addr_width-1;
|
||||
parameter rd_afi_data_lsb = rd_afi_addr_msb + 1;
|
||||
parameter rd_afi_data_msb = rd_afi_data_lsb + max_burst_bits-1;
|
||||
|
||||
|
||||
/* Latency types */
|
||||
parameter BEST_CASE = 0;
|
||||
parameter AVG_CASE = 1;
|
||||
parameter WORST_CASE = 2;
|
||||
parameter RANDOM_CASE = 3;
|
||||
|
||||
/* Latency Parameters ACP */
|
||||
parameter acp_wr_min = 21;
|
||||
parameter acp_wr_avg = 16;
|
||||
parameter acp_wr_max = 27;
|
||||
parameter acp_rd_min = 34;
|
||||
parameter acp_rd_avg = 125;
|
||||
parameter acp_rd_max = 130;
|
||||
|
||||
/* Latency Parameters GP */
|
||||
parameter gp_wr_min = 21;
|
||||
parameter gp_wr_avg = 16;
|
||||
parameter gp_wr_max = 46;
|
||||
parameter gp_rd_min = 38;
|
||||
parameter gp_rd_avg = 125;
|
||||
parameter gp_rd_max = 130;
|
||||
|
||||
/* Latency Parameters HP */
|
||||
parameter afi_wr_min = 37;
|
||||
parameter afi_wr_avg = 41;
|
||||
parameter afi_wr_max = 42;
|
||||
parameter afi_rd_min = 41;
|
||||
parameter afi_rd_avg = 221;
|
||||
parameter afi_rd_max = 229;
|
||||
|
||||
/* ID VALID and INVALID */
|
||||
parameter secure_access_enabled = 0;
|
||||
parameter id_invalid = 0;
|
||||
parameter id_valid = 1;
|
||||
|
||||
/* Display */
|
||||
parameter DISP_INFO = "*ZYNQ_VIP_INFO";
|
||||
parameter DISP_WARN = "*ZYNQ_VIP_WARNING";
|
||||
parameter DISP_ERR = "*ZYNQ_VIP_ERROR";
|
||||
parameter DISP_INT_INFO = "ZYNQ_VIP_INT_INFO";
|
||||
|
||||
parameter all_strb_valid = 2048'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
|
||||
|
||||
+2924
File diff suppressed because it is too large
Load Diff
+10519
File diff suppressed because it is too large
Load Diff
+433
@@ -0,0 +1,433 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_unused_ports.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Semantic checks for unused ports.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* CAN */
|
||||
assign CAN0_PHY_TX = 0;
|
||||
assign CAN1_PHY_TX = 0;
|
||||
always @(CAN0_PHY_RX or CAN1_PHY_RX)
|
||||
begin
|
||||
if(CAN0_PHY_RX | CAN1_PHY_RX)
|
||||
$display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* ETHERNET */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign ENET0_GMII_TX_EN = 0;
|
||||
assign ENET0_GMII_TX_ER = 0;
|
||||
assign ENET0_MDIO_MDC = 0;
|
||||
assign ENET0_MDIO_O = 0; /// confirm
|
||||
assign ENET0_MDIO_T = 0;
|
||||
assign ENET0_PTP_DELAY_REQ_RX = 0;
|
||||
assign ENET0_PTP_DELAY_REQ_TX = 0;
|
||||
assign ENET0_PTP_PDELAY_REQ_RX = 0;
|
||||
assign ENET0_PTP_PDELAY_REQ_TX = 0;
|
||||
assign ENET0_PTP_PDELAY_RESP_RX = 0;
|
||||
assign ENET0_PTP_PDELAY_RESP_TX = 0;
|
||||
assign ENET0_PTP_SYNC_FRAME_RX = 0;
|
||||
assign ENET0_PTP_SYNC_FRAME_TX = 0;
|
||||
assign ENET0_SOF_RX = 0;
|
||||
assign ENET0_SOF_TX = 0;
|
||||
assign ENET0_GMII_TXD = 0;
|
||||
always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or
|
||||
ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
|
||||
ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
|
||||
begin
|
||||
if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN |
|
||||
ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
|
||||
ENET0_GMII_TX_CLK | ENET0_MDIO_I )
|
||||
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign ENET1_GMII_TX_EN = 0;
|
||||
assign ENET1_GMII_TX_ER = 0;
|
||||
assign ENET1_MDIO_MDC = 0;
|
||||
assign ENET1_MDIO_O = 0;/// confirm
|
||||
assign ENET1_MDIO_T = 0;
|
||||
assign ENET1_PTP_DELAY_REQ_RX = 0;
|
||||
assign ENET1_PTP_DELAY_REQ_TX = 0;
|
||||
assign ENET1_PTP_PDELAY_REQ_RX = 0;
|
||||
assign ENET1_PTP_PDELAY_REQ_TX = 0;
|
||||
assign ENET1_PTP_PDELAY_RESP_RX = 0;
|
||||
assign ENET1_PTP_PDELAY_RESP_TX = 0;
|
||||
assign ENET1_PTP_SYNC_FRAME_RX = 0;
|
||||
assign ENET1_PTP_SYNC_FRAME_TX = 0;
|
||||
assign ENET1_SOF_RX = 0;
|
||||
assign ENET1_SOF_TX = 0;
|
||||
assign ENET1_GMII_TXD = 0;
|
||||
always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or
|
||||
ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
|
||||
ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
|
||||
begin
|
||||
if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN |
|
||||
ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
|
||||
ENET1_GMII_TX_CLK | ENET1_MDIO_I )
|
||||
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* GPIO */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign GPIO_O = 0;
|
||||
assign GPIO_T = 0;
|
||||
always@(GPIO_I)
|
||||
begin
|
||||
// if(GPIO_I !== 0)
|
||||
// $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* I2C */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign I2C0_SDA_O = 0;
|
||||
assign I2C0_SDA_T = 0;
|
||||
assign I2C0_SCL_O = 0;
|
||||
assign I2C0_SCL_T = 0;
|
||||
assign I2C1_SDA_O = 0;
|
||||
assign I2C1_SDA_T = 0;
|
||||
assign I2C1_SCL_O = 0;
|
||||
assign I2C1_SCL_T = 0;
|
||||
always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
|
||||
begin
|
||||
if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
|
||||
$display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* JTAG */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign PJTAG_TD_T = 0;
|
||||
assign PJTAG_TD_O = 0;
|
||||
always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
|
||||
begin
|
||||
if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
|
||||
$display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* SDIO */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign SDIO0_CLK = 0;
|
||||
assign SDIO0_CMD_O = 0;
|
||||
assign SDIO0_CMD_T = 0;
|
||||
assign SDIO0_DATA_O = 0;
|
||||
assign SDIO0_DATA_T = 0;
|
||||
assign SDIO0_LED = 0;
|
||||
assign SDIO0_BUSPOW = 0;
|
||||
assign SDIO0_BUSVOLT = 0;
|
||||
always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
|
||||
begin
|
||||
if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
|
||||
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign SDIO1_CLK = 0;
|
||||
assign SDIO1_CMD_O = 0;
|
||||
assign SDIO1_CMD_T = 0;
|
||||
assign SDIO1_DATA_O = 0;
|
||||
assign SDIO1_DATA_T = 0;
|
||||
assign SDIO1_LED = 0;
|
||||
assign SDIO1_BUSPOW = 0;
|
||||
assign SDIO1_BUSVOLT = 0;
|
||||
always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
|
||||
begin
|
||||
if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
|
||||
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* SPI */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign SPI0_SCLK_O = 0;
|
||||
assign SPI0_SCLK_T = 0;
|
||||
assign SPI0_MOSI_O = 0;
|
||||
assign SPI0_MOSI_T = 0;
|
||||
assign SPI0_MISO_O = 0;
|
||||
assign SPI0_MISO_T = 0;
|
||||
assign SPI0_SS_O = 0; /// confirm
|
||||
assign SPI0_SS1_O = 0;/// confirm
|
||||
assign SPI0_SS2_O = 0;/// confirm
|
||||
assign SPI0_SS_T = 0;
|
||||
always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
|
||||
begin
|
||||
if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
|
||||
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign SPI1_SCLK_O = 0;
|
||||
assign SPI1_SCLK_T = 0;
|
||||
assign SPI1_MOSI_O = 0;
|
||||
assign SPI1_MOSI_T = 0;
|
||||
assign SPI1_MISO_O = 0;
|
||||
assign SPI1_MISO_T = 0;
|
||||
assign SPI1_SS_O = 0;
|
||||
assign SPI1_SS1_O = 0;
|
||||
assign SPI1_SS2_O = 0;
|
||||
assign SPI1_SS_T = 0;
|
||||
always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
|
||||
begin
|
||||
if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
|
||||
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* UART */
|
||||
/* ------------------------------------------- */
|
||||
/// confirm
|
||||
assign UART0_DTRN = 0;
|
||||
assign UART0_RTSN = 0;
|
||||
assign UART0_TX = 0;
|
||||
always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
|
||||
begin
|
||||
if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
|
||||
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign UART1_DTRN = 0;
|
||||
assign UART1_RTSN = 0;
|
||||
assign UART1_TX = 0;
|
||||
always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
|
||||
begin
|
||||
if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
|
||||
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* TTC */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign TTC0_WAVE0_OUT = 0;
|
||||
assign TTC0_WAVE1_OUT = 0;
|
||||
assign TTC0_WAVE2_OUT = 0;
|
||||
always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
|
||||
begin
|
||||
if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
|
||||
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign TTC1_WAVE0_OUT = 0;
|
||||
assign TTC1_WAVE1_OUT = 0;
|
||||
assign TTC1_WAVE2_OUT = 0;
|
||||
always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
|
||||
begin
|
||||
if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
|
||||
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* WDT */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign WDT_RST_OUT = 0;
|
||||
always@(WDT_CLK_IN)
|
||||
begin
|
||||
if(WDT_CLK_IN)
|
||||
$display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* TRACE */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign TRACE_CTL = 0;
|
||||
assign TRACE_DATA = 0;
|
||||
always@(TRACE_CLK)
|
||||
begin
|
||||
if(TRACE_CLK)
|
||||
$display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* USB */
|
||||
/* ------------------------------------------- */
|
||||
assign USB0_PORT_INDCTL = 0;
|
||||
assign USB0_VBUS_PWRSELECT = 0;
|
||||
always@(USB0_VBUS_PWRFAULT)
|
||||
begin
|
||||
if(USB0_VBUS_PWRFAULT)
|
||||
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign USB1_PORT_INDCTL = 0;
|
||||
assign USB1_VBUS_PWRSELECT = 0;
|
||||
always@(USB1_VBUS_PWRFAULT)
|
||||
begin
|
||||
if(USB1_VBUS_PWRFAULT)
|
||||
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
always@(SRAM_INTIN)
|
||||
begin
|
||||
if(SRAM_INTIN)
|
||||
$display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* DMA */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign DMA0_DATYPE = 0;
|
||||
assign DMA0_DAVALID = 0;
|
||||
assign DMA0_DRREADY = 0;
|
||||
assign DMA0_RSTN = 0;
|
||||
always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
|
||||
begin
|
||||
if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign DMA1_DATYPE = 0;
|
||||
assign DMA1_DAVALID = 0;
|
||||
assign DMA1_DRREADY = 0;
|
||||
assign DMA1_RSTN = 0;
|
||||
always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
|
||||
begin
|
||||
if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign DMA2_DATYPE = 0;
|
||||
assign DMA2_DAVALID = 0;
|
||||
assign DMA2_DRREADY = 0;
|
||||
assign DMA2_RSTN = 0;
|
||||
always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
|
||||
begin
|
||||
if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign DMA3_DATYPE = 0;
|
||||
assign DMA3_DAVALID = 0;
|
||||
assign DMA3_DRREADY = 0;
|
||||
assign DMA3_RSTN = 0;
|
||||
always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
|
||||
begin
|
||||
if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* FTM */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign FTMT_F2P_TRIGACK = 0;
|
||||
assign FTMT_P2F_TRIG = 0;
|
||||
assign FTMT_P2F_DEBUG = 0;
|
||||
always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or
|
||||
FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
|
||||
begin
|
||||
if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
|
||||
$display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* EVENT */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign EVENT_EVENTO = 0;
|
||||
assign EVENT_STANDBYWFE = 0;
|
||||
assign EVENT_STANDBYWFI = 0;
|
||||
always@(EVENT_EVENTI)
|
||||
begin
|
||||
if(EVENT_EVENTI)
|
||||
$display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* MIO */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
always@(MIO)
|
||||
begin
|
||||
// if(MIO !== 0)
|
||||
// $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* FCLK_TRIG */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
|
||||
begin
|
||||
if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
|
||||
$display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* MISC */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
always@(FPGA_IDLE_N)
|
||||
begin
|
||||
if(FPGA_IDLE_N)
|
||||
$display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
always@(DDR_ARB)
|
||||
begin
|
||||
// if(DDR_ARB !== 0)
|
||||
// $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
|
||||
begin
|
||||
if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ)
|
||||
$display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* DDR */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign DDR_WEB = 0;
|
||||
always@(DDR_Clk or DDR_CS_n)
|
||||
begin
|
||||
if(!DDR_CS_n)
|
||||
$display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* IRQ_P2F */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign IRQ_P2F_DMAC_ABORT = 0;
|
||||
assign IRQ_P2F_DMAC0 = 0;
|
||||
assign IRQ_P2F_DMAC1 = 0;
|
||||
assign IRQ_P2F_DMAC2 = 0;
|
||||
assign IRQ_P2F_DMAC3 = 0;
|
||||
assign IRQ_P2F_DMAC4 = 0;
|
||||
assign IRQ_P2F_DMAC5 = 0;
|
||||
assign IRQ_P2F_DMAC6 = 0;
|
||||
assign IRQ_P2F_DMAC7 = 0;
|
||||
assign IRQ_P2F_SMC = 0;
|
||||
assign IRQ_P2F_QSPI = 0;
|
||||
assign IRQ_P2F_CTI = 0;
|
||||
assign IRQ_P2F_GPIO = 0;
|
||||
assign IRQ_P2F_USB0 = 0;
|
||||
assign IRQ_P2F_ENET0 = 0;
|
||||
assign IRQ_P2F_ENET_WAKE0 = 0;
|
||||
assign IRQ_P2F_SDIO0 = 0;
|
||||
assign IRQ_P2F_I2C0 = 0;
|
||||
assign IRQ_P2F_SPI0 = 0;
|
||||
assign IRQ_P2F_UART0 = 0;
|
||||
assign IRQ_P2F_CAN0 = 0;
|
||||
assign IRQ_P2F_USB1 = 0;
|
||||
assign IRQ_P2F_ENET1 = 0;
|
||||
assign IRQ_P2F_ENET_WAKE1 = 0;
|
||||
assign IRQ_P2F_SDIO1 = 0;
|
||||
assign IRQ_P2F_I2C1 = 0;
|
||||
assign IRQ_P2F_SPI1 = 0;
|
||||
assign IRQ_P2F_UART1 = 0;
|
||||
assign IRQ_P2F_CAN1 = 0;
|
||||
+13831
File diff suppressed because it is too large
Load Diff
+409
@@ -0,0 +1,409 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
|
||||
//--
|
||||
//-- This file contains confidential and proprietary information
|
||||
//-- of Xilinx, Inc. and is protected under U.S. and
|
||||
//-- international copyright and other intellectual property
|
||||
//-- laws.
|
||||
//--
|
||||
//-- DISCLAIMER
|
||||
//-- This disclaimer is not a license and does not grant any
|
||||
//-- rights to the materials distributed herewith. Except as
|
||||
//-- otherwise provided in a valid license issued to you by
|
||||
//-- Xilinx, and to the maximum extent permitted by applicable
|
||||
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
//-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
//-- including negligence, or under any other theory of
|
||||
//-- liability) for any loss or damage of any kind or nature
|
||||
//-- related to, arising under or in connection with these
|
||||
//-- materials, including for any direct, or any indirect,
|
||||
//-- special, incidental, or consequential loss or damage
|
||||
//-- (including loss of data, profits, goodwill, or any type of
|
||||
//-- loss or damage suffered as a result of any action brought
|
||||
//-- by a third party) even if such damage or loss was
|
||||
//-- reasonably foreseeable or Xilinx had been advised of the
|
||||
//-- possibility of the same.
|
||||
//--
|
||||
//-- CRITICAL APPLICATIONS
|
||||
//-- Xilinx products are not designed or intended to be fail-
|
||||
//-- safe, or for use in any application requiring fail-safe
|
||||
//-- performance, such as life-support or safety devices or
|
||||
//-- systems, Class III medical devices, nuclear facilities,
|
||||
//-- applications related to the deployment of airbags, or any
|
||||
//-- other applications that could lead to death, personal
|
||||
//-- injury, or severe property or environmental damage
|
||||
//-- (individually and collectively, "Critical
|
||||
//-- Applications"). Customer assumes the sole risk and
|
||||
//-- liability of any use of Xilinx products in Critical
|
||||
//-- Applications, subject only to applicable laws and
|
||||
//-- regulations governing limitations on product liability.
|
||||
//--
|
||||
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
//-- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: ACP Transaction Checker
|
||||
//
|
||||
// Check for optimized ACP transactions and flag if they are broken.
|
||||
//
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// atc
|
||||
// aw_atc
|
||||
// w_atc
|
||||
// b_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
module processing_system7_v5_5_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
// Width of all ADDR signals on SI and MI side of checker.
|
||||
// Range: 32.
|
||||
parameter integer C_AXI_DATA_WIDTH = 64,
|
||||
// Width of all DATA signals on SI and MI side of checker.
|
||||
// Range: 64.
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
// Width of ARUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
// Width of WUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
// Width of RUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1
|
||||
// Width of BUSER signals.
|
||||
// Range: >= 1.
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ACLK,
|
||||
input wire ARESETN,
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
|
||||
input wire [4-1:0] S_AXI_AWLEN,
|
||||
input wire [3-1:0] S_AXI_AWSIZE,
|
||||
input wire [2-1:0] S_AXI_AWBURST,
|
||||
input wire [2-1:0] S_AXI_AWLOCK,
|
||||
input wire [4-1:0] S_AXI_AWCACHE,
|
||||
input wire [3-1:0] S_AXI_AWPROT,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
|
||||
input wire S_AXI_AWVALID,
|
||||
output wire S_AXI_AWREADY,
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
|
||||
input wire S_AXI_WLAST,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
|
||||
input wire S_AXI_WVALID,
|
||||
output wire S_AXI_WREADY,
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
|
||||
output wire [2-1:0] S_AXI_BRESP,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
|
||||
output wire S_AXI_BVALID,
|
||||
input wire S_AXI_BREADY,
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
|
||||
input wire [4-1:0] S_AXI_ARLEN,
|
||||
input wire [3-1:0] S_AXI_ARSIZE,
|
||||
input wire [2-1:0] S_AXI_ARBURST,
|
||||
input wire [2-1:0] S_AXI_ARLOCK,
|
||||
input wire [4-1:0] S_AXI_ARCACHE,
|
||||
input wire [3-1:0] S_AXI_ARPROT,
|
||||
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
|
||||
input wire S_AXI_ARVALID,
|
||||
output wire S_AXI_ARREADY,
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
|
||||
output wire [2-1:0] S_AXI_RRESP,
|
||||
output wire S_AXI_RLAST,
|
||||
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
|
||||
output wire S_AXI_RVALID,
|
||||
input wire S_AXI_RREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
|
||||
output wire [4-1:0] M_AXI_AWLEN,
|
||||
output wire [3-1:0] M_AXI_AWSIZE,
|
||||
output wire [2-1:0] M_AXI_AWBURST,
|
||||
output wire [2-1:0] M_AXI_AWLOCK,
|
||||
output wire [4-1:0] M_AXI_AWCACHE,
|
||||
output wire [3-1:0] M_AXI_AWPROT,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
|
||||
output wire M_AXI_AWVALID,
|
||||
input wire M_AXI_AWREADY,
|
||||
// Master Interface Write Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
|
||||
output wire M_AXI_WLAST,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
|
||||
output wire M_AXI_WVALID,
|
||||
input wire M_AXI_WREADY,
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
|
||||
input wire [2-1:0] M_AXI_BRESP,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
|
||||
input wire M_AXI_BVALID,
|
||||
output wire M_AXI_BREADY,
|
||||
// Master Interface Read Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
|
||||
output wire [4-1:0] M_AXI_ARLEN,
|
||||
output wire [3-1:0] M_AXI_ARSIZE,
|
||||
output wire [2-1:0] M_AXI_ARBURST,
|
||||
output wire [2-1:0] M_AXI_ARLOCK,
|
||||
output wire [4-1:0] M_AXI_ARCACHE,
|
||||
output wire [3-1:0] M_AXI_ARPROT,
|
||||
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
|
||||
output wire M_AXI_ARVALID,
|
||||
input wire M_AXI_ARREADY,
|
||||
// Master Interface Read Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
|
||||
input wire [2-1:0] M_AXI_RRESP,
|
||||
input wire M_AXI_RLAST,
|
||||
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
|
||||
input wire M_AXI_RVALID,
|
||||
output wire M_AXI_RREADY,
|
||||
|
||||
output wire ERROR_TRIGGER,
|
||||
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
localparam C_FIFO_DEPTH_LOG = 4;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Internal reset.
|
||||
reg ARESET;
|
||||
|
||||
// AW->W command queue signals.
|
||||
wire cmd_w_valid;
|
||||
wire cmd_w_check;
|
||||
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
|
||||
wire cmd_w_ready;
|
||||
|
||||
// W->B command queue signals.
|
||||
wire cmd_b_push;
|
||||
wire cmd_b_error;
|
||||
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
|
||||
wire cmd_b_full;
|
||||
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
|
||||
wire cmd_b_ready;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Internal Reset
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
always @ (posedge ACLK) begin
|
||||
ARESET <= !ARESETN;
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Write Channels (AW/W/B)
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Write Address Channel.
|
||||
processing_system7_v5_5_aw_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
|
||||
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
|
||||
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
|
||||
) write_addr_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (Out)
|
||||
.cmd_w_valid (cmd_w_valid),
|
||||
.cmd_w_check (cmd_w_check),
|
||||
.cmd_w_id (cmd_w_id),
|
||||
.cmd_w_ready (cmd_w_ready),
|
||||
.cmd_b_addr (cmd_b_addr),
|
||||
.cmd_b_ready (cmd_b_ready),
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
.S_AXI_AWID (S_AXI_AWID),
|
||||
.S_AXI_AWADDR (S_AXI_AWADDR),
|
||||
.S_AXI_AWLEN (S_AXI_AWLEN),
|
||||
.S_AXI_AWSIZE (S_AXI_AWSIZE),
|
||||
.S_AXI_AWBURST (S_AXI_AWBURST),
|
||||
.S_AXI_AWLOCK (S_AXI_AWLOCK),
|
||||
.S_AXI_AWCACHE (S_AXI_AWCACHE),
|
||||
.S_AXI_AWPROT (S_AXI_AWPROT),
|
||||
.S_AXI_AWUSER (S_AXI_AWUSER),
|
||||
.S_AXI_AWVALID (S_AXI_AWVALID),
|
||||
.S_AXI_AWREADY (S_AXI_AWREADY),
|
||||
|
||||
// Master Interface Write Address Port
|
||||
.M_AXI_AWID (M_AXI_AWID),
|
||||
.M_AXI_AWADDR (M_AXI_AWADDR),
|
||||
.M_AXI_AWLEN (M_AXI_AWLEN),
|
||||
.M_AXI_AWSIZE (M_AXI_AWSIZE),
|
||||
.M_AXI_AWBURST (M_AXI_AWBURST),
|
||||
.M_AXI_AWLOCK (M_AXI_AWLOCK),
|
||||
.M_AXI_AWCACHE (M_AXI_AWCACHE),
|
||||
.M_AXI_AWPROT (M_AXI_AWPROT),
|
||||
.M_AXI_AWUSER (M_AXI_AWUSER),
|
||||
.M_AXI_AWVALID (M_AXI_AWVALID),
|
||||
.M_AXI_AWREADY (M_AXI_AWREADY)
|
||||
);
|
||||
|
||||
// Write Data channel.
|
||||
processing_system7_v5_5_w_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
|
||||
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
|
||||
) write_data_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (In)
|
||||
.cmd_w_valid (cmd_w_valid),
|
||||
.cmd_w_check (cmd_w_check),
|
||||
.cmd_w_id (cmd_w_id),
|
||||
.cmd_w_ready (cmd_w_ready),
|
||||
|
||||
// Command Interface (Out)
|
||||
.cmd_b_push (cmd_b_push),
|
||||
.cmd_b_error (cmd_b_error),
|
||||
.cmd_b_id (cmd_b_id),
|
||||
.cmd_b_full (cmd_b_full),
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
.S_AXI_WID (S_AXI_WID),
|
||||
.S_AXI_WDATA (S_AXI_WDATA),
|
||||
.S_AXI_WSTRB (S_AXI_WSTRB),
|
||||
.S_AXI_WLAST (S_AXI_WLAST),
|
||||
.S_AXI_WUSER (S_AXI_WUSER),
|
||||
.S_AXI_WVALID (S_AXI_WVALID),
|
||||
.S_AXI_WREADY (S_AXI_WREADY),
|
||||
|
||||
// Master Interface Write Data Ports
|
||||
.M_AXI_WID (M_AXI_WID),
|
||||
.M_AXI_WDATA (M_AXI_WDATA),
|
||||
.M_AXI_WSTRB (M_AXI_WSTRB),
|
||||
.M_AXI_WLAST (M_AXI_WLAST),
|
||||
.M_AXI_WUSER (M_AXI_WUSER),
|
||||
.M_AXI_WVALID (M_AXI_WVALID),
|
||||
.M_AXI_WREADY (M_AXI_WREADY)
|
||||
);
|
||||
|
||||
// Write Response channel.
|
||||
processing_system7_v5_5_b_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
|
||||
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
|
||||
) write_response_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (In)
|
||||
.cmd_b_push (cmd_b_push),
|
||||
.cmd_b_error (cmd_b_error),
|
||||
.cmd_b_id (cmd_b_id),
|
||||
.cmd_b_full (cmd_b_full),
|
||||
.cmd_b_addr (cmd_b_addr),
|
||||
.cmd_b_ready (cmd_b_ready),
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
.S_AXI_BID (S_AXI_BID),
|
||||
.S_AXI_BRESP (S_AXI_BRESP),
|
||||
.S_AXI_BUSER (S_AXI_BUSER),
|
||||
.S_AXI_BVALID (S_AXI_BVALID),
|
||||
.S_AXI_BREADY (S_AXI_BREADY),
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
.M_AXI_BID (M_AXI_BID),
|
||||
.M_AXI_BRESP (M_AXI_BRESP),
|
||||
.M_AXI_BUSER (M_AXI_BUSER),
|
||||
.M_AXI_BVALID (M_AXI_BVALID),
|
||||
.M_AXI_BREADY (M_AXI_BREADY),
|
||||
|
||||
// Trigger detection
|
||||
.ERROR_TRIGGER (ERROR_TRIGGER),
|
||||
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
|
||||
);
|
||||
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Read Channels (AR/R)
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Read Address Port
|
||||
assign M_AXI_ARID = S_AXI_ARID;
|
||||
assign M_AXI_ARADDR = S_AXI_ARADDR;
|
||||
assign M_AXI_ARLEN = S_AXI_ARLEN;
|
||||
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
|
||||
assign M_AXI_ARBURST = S_AXI_ARBURST;
|
||||
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
|
||||
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
|
||||
assign M_AXI_ARPROT = S_AXI_ARPROT;
|
||||
assign M_AXI_ARUSER = S_AXI_ARUSER;
|
||||
assign M_AXI_ARVALID = S_AXI_ARVALID;
|
||||
assign S_AXI_ARREADY = M_AXI_ARREADY;
|
||||
|
||||
// Read Data Port
|
||||
assign S_AXI_RID = M_AXI_RID;
|
||||
assign S_AXI_RDATA = M_AXI_RDATA;
|
||||
assign S_AXI_RRESP = M_AXI_RRESP;
|
||||
assign S_AXI_RLAST = M_AXI_RLAST;
|
||||
assign S_AXI_RUSER = M_AXI_RUSER;
|
||||
assign S_AXI_RVALID = M_AXI_RVALID;
|
||||
assign M_AXI_RREADY = S_AXI_RREADY;
|
||||
|
||||
|
||||
endmodule
|
||||
`default_nettype wire
|
||||
+298
@@ -0,0 +1,298 @@
|
||||
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: Address Write Channel for ATC
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// aw_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module processing_system7_v5_5_aw_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
// Width of all ADDR signals on SI and MI side of checker.
|
||||
// Range: 32.
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_FIFO_DEPTH_LOG = 4
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ARESET,
|
||||
input wire ACLK,
|
||||
|
||||
// Command Interface
|
||||
output reg cmd_w_valid,
|
||||
output wire cmd_w_check,
|
||||
output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
|
||||
input wire cmd_w_ready,
|
||||
input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
|
||||
input wire cmd_b_ready,
|
||||
|
||||
// Slave Interface Write Address Port
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
|
||||
input wire [4-1:0] S_AXI_AWLEN,
|
||||
input wire [3-1:0] S_AXI_AWSIZE,
|
||||
input wire [2-1:0] S_AXI_AWBURST,
|
||||
input wire [2-1:0] S_AXI_AWLOCK,
|
||||
input wire [4-1:0] S_AXI_AWCACHE,
|
||||
input wire [3-1:0] S_AXI_AWPROT,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
|
||||
input wire S_AXI_AWVALID,
|
||||
output wire S_AXI_AWREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
|
||||
output wire [4-1:0] M_AXI_AWLEN,
|
||||
output wire [3-1:0] M_AXI_AWSIZE,
|
||||
output wire [2-1:0] M_AXI_AWBURST,
|
||||
output wire [2-1:0] M_AXI_AWLOCK,
|
||||
output wire [4-1:0] M_AXI_AWCACHE,
|
||||
output wire [3-1:0] M_AXI_AWPROT,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
|
||||
output wire M_AXI_AWVALID,
|
||||
input wire M_AXI_AWREADY
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Constants for burst types.
|
||||
localparam [2-1:0] C_FIX_BURST = 2'b00;
|
||||
localparam [2-1:0] C_INCR_BURST = 2'b01;
|
||||
localparam [2-1:0] C_WRAP_BURST = 2'b10;
|
||||
|
||||
// Constants for size.
|
||||
localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011;
|
||||
|
||||
// Constants for length.
|
||||
localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011;
|
||||
|
||||
// Constants for cacheline address.
|
||||
localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0;
|
||||
|
||||
// Command FIFO settings
|
||||
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
|
||||
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Variables for generating parameter controlled instances.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
integer index;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Transaction properties.
|
||||
wire access_is_incr;
|
||||
wire access_is_wrap;
|
||||
wire access_is_coherent;
|
||||
wire access_optimized_size;
|
||||
wire incr_addr_boundary;
|
||||
wire incr_is_optimized;
|
||||
wire wrap_is_optimized;
|
||||
wire access_is_optimized;
|
||||
|
||||
// Command FIFO.
|
||||
wire cmd_w_push;
|
||||
reg cmd_full;
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
|
||||
wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr;
|
||||
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Decode:
|
||||
//
|
||||
// Detect if transaction is of correct typ, size and length to qualify as
|
||||
// an optimized transaction that has to be checked for errors.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Transaction burst type.
|
||||
assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST );
|
||||
assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST );
|
||||
|
||||
// Transaction has to be Coherent.
|
||||
assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) &
|
||||
( S_AXI_AWCACHE[1] == 1'b1 );
|
||||
|
||||
// Transaction cacheline boundary address.
|
||||
assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET );
|
||||
|
||||
// Transaction length & size.
|
||||
assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) &
|
||||
( S_AXI_AWLEN == C_OPTIMIZED_LEN );
|
||||
|
||||
// Transaction is optimized.
|
||||
assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary;
|
||||
assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size;
|
||||
assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized );
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Command FIFO:
|
||||
//
|
||||
// Since supported write interleaving is only 1, it is safe to use only a
|
||||
// simple SRL based FIFO as a command queue.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Determine when transaction infromation is pushed to the FIFO.
|
||||
assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full;
|
||||
|
||||
// SRL FIFO Pointer.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
end else begin
|
||||
if ( cmd_w_push & ~cmd_w_ready ) begin
|
||||
addr_ptr <= addr_ptr + 1;
|
||||
end else if ( ~cmd_w_push & cmd_w_ready ) begin
|
||||
addr_ptr <= addr_ptr - 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Total number of buffered commands.
|
||||
assign all_addr_ptr = addr_ptr + cmd_b_addr + 2;
|
||||
|
||||
// FIFO Flags.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
cmd_full <= 1'b0;
|
||||
cmd_w_valid <= 1'b0;
|
||||
end else begin
|
||||
if ( cmd_w_push & ~cmd_w_ready ) begin
|
||||
cmd_w_valid <= 1'b1;
|
||||
end else if ( ~cmd_w_push & cmd_w_ready ) begin
|
||||
cmd_w_valid <= ( addr_ptr != 0 );
|
||||
end
|
||||
if ( cmd_w_push & ~cmd_b_ready ) begin
|
||||
// Going to full.
|
||||
cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 );
|
||||
end else if ( ~cmd_w_push & cmd_b_ready ) begin
|
||||
// Pop in middle of queue doesn't affect full status.
|
||||
cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 );
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Infere SRL for storage.
|
||||
always @ (posedge ACLK) begin
|
||||
if ( cmd_w_push ) begin
|
||||
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
|
||||
data_srl[index+1] <= data_srl[index];
|
||||
end
|
||||
data_srl[0] <= {access_is_optimized, S_AXI_AWID};
|
||||
end
|
||||
end
|
||||
|
||||
// Get current transaction info.
|
||||
assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr];
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Throttling:
|
||||
//
|
||||
// Stall commands if FIFO is full.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Propagate masked valid.
|
||||
assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full;
|
||||
|
||||
// Return ready with push back.
|
||||
assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Address Write propagation:
|
||||
//
|
||||
// All information is simply forwarded on from the SI- to MI-Side untouched.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// 1:1 mapping.
|
||||
assign M_AXI_AWID = S_AXI_AWID;
|
||||
assign M_AXI_AWADDR = S_AXI_AWADDR;
|
||||
assign M_AXI_AWLEN = S_AXI_AWLEN;
|
||||
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
|
||||
assign M_AXI_AWBURST = S_AXI_AWBURST;
|
||||
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
|
||||
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
|
||||
assign M_AXI_AWPROT = S_AXI_AWPROT;
|
||||
assign M_AXI_AWUSER = S_AXI_AWUSER;
|
||||
|
||||
|
||||
endmodule
|
||||
+413
@@ -0,0 +1,413 @@
|
||||
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: Write Response Channel for ATC
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// b_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module processing_system7_v5_5_b_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_FIFO_DEPTH_LOG = 4
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ARESET,
|
||||
input wire ACLK,
|
||||
|
||||
// Command Interface
|
||||
input wire cmd_b_push,
|
||||
input wire cmd_b_error,
|
||||
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
|
||||
output wire cmd_b_ready,
|
||||
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
|
||||
output reg cmd_b_full,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
|
||||
output reg [2-1:0] S_AXI_BRESP,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
|
||||
output wire S_AXI_BVALID,
|
||||
input wire S_AXI_BREADY,
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
|
||||
input wire [2-1:0] M_AXI_BRESP,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
|
||||
input wire M_AXI_BVALID,
|
||||
output wire M_AXI_BREADY,
|
||||
|
||||
// Trigger detection
|
||||
output reg ERROR_TRIGGER,
|
||||
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Constants for packing levels.
|
||||
localparam [2-1:0] C_RESP_OKAY = 2'b00;
|
||||
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
|
||||
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
|
||||
localparam [2-1:0] C_RESP_DECERR = 2'b11;
|
||||
|
||||
// Command FIFO settings
|
||||
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
|
||||
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Variables for generating parameter controlled instances.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
integer index;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Command Queue.
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
|
||||
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
|
||||
reg cmd_b_valid;
|
||||
wire cmd_b_ready_i;
|
||||
wire inject_error;
|
||||
wire [C_AXI_ID_WIDTH-1:0] current_id;
|
||||
|
||||
// Search command.
|
||||
wire found_match;
|
||||
wire use_match;
|
||||
wire matching_id;
|
||||
|
||||
// Manage valid command.
|
||||
wire write_valid_cmd;
|
||||
reg [C_FIFO_DEPTH-2:0] valid_cmd;
|
||||
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
|
||||
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
|
||||
|
||||
// Pipelined data
|
||||
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
|
||||
reg [2-1:0] M_AXI_BRESP_I;
|
||||
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
|
||||
reg M_AXI_BVALID_I;
|
||||
wire M_AXI_BREADY_I;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Command Queue:
|
||||
//
|
||||
// Keep track of depth of Queue to generate full flag.
|
||||
//
|
||||
// Also generate valid to mark pressence of commands in Queue.
|
||||
//
|
||||
// Maintain Queue and extract data from currently searched entry.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// SRL FIFO Pointer.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
end else begin
|
||||
if ( cmd_b_push & ~cmd_b_ready_i ) begin
|
||||
// Pushing data increase length/addr.
|
||||
addr_ptr <= addr_ptr + 1;
|
||||
end else if ( cmd_b_ready_i ) begin
|
||||
// Collapse addr when data is popped.
|
||||
addr_ptr <= collapsed_addr_ptr;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// FIFO Flags.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
cmd_b_full <= 1'b0;
|
||||
cmd_b_valid <= 1'b0;
|
||||
end else begin
|
||||
if ( cmd_b_push & ~cmd_b_ready_i ) begin
|
||||
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
|
||||
cmd_b_valid <= 1'b1;
|
||||
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
|
||||
cmd_b_full <= 1'b0;
|
||||
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Infere SRL for storage.
|
||||
always @ (posedge ACLK) begin
|
||||
if ( cmd_b_push ) begin
|
||||
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
|
||||
data_srl[index+1] <= data_srl[index];
|
||||
end
|
||||
data_srl[0] <= {cmd_b_error, cmd_b_id};
|
||||
end
|
||||
end
|
||||
|
||||
// Get current transaction info.
|
||||
assign {inject_error, current_id} = data_srl[search_addr_ptr];
|
||||
|
||||
// Assign outputs.
|
||||
assign cmd_b_addr = collapsed_addr_ptr;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Search Command Queue:
|
||||
//
|
||||
// Search for matching valid command in queue.
|
||||
//
|
||||
// A command is found when an valid entry with correct ID is found. The queue
|
||||
// is search from the oldest entry, i.e. from a high value.
|
||||
// When new commands are pushed the search address has to be updated to always
|
||||
// start the search from the oldest available.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Handle search addr.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
end else begin
|
||||
if ( cmd_b_ready_i ) begin
|
||||
// Collapse addr when data is popped.
|
||||
search_addr_ptr <= collapsed_addr_ptr;
|
||||
|
||||
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
|
||||
// Skip non valid command.
|
||||
search_addr_ptr <= search_addr_ptr - 1;
|
||||
|
||||
end else if ( cmd_b_push ) begin
|
||||
search_addr_ptr <= search_addr_ptr + 1;
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Check if searched command is valid and match ID (for existing response on MI side).
|
||||
assign matching_id = ( M_AXI_BID_I == current_id );
|
||||
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
|
||||
assign use_match = found_match & S_AXI_BREADY;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Track Used Commands:
|
||||
//
|
||||
// Actions that affect Valid Command:
|
||||
// * When a new command is pushed
|
||||
// => Shift valid vector one step
|
||||
// * When a command is used
|
||||
// => Clear corresponding valid bit
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Valid command status is updated when a command is used or a new one is pushed.
|
||||
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
|
||||
|
||||
// Update the used command valid bit.
|
||||
always @ *
|
||||
begin
|
||||
updated_valid_cmd = valid_cmd;
|
||||
updated_valid_cmd[search_addr_ptr] = ~use_match;
|
||||
end
|
||||
|
||||
// Shift valid vector when command is pushed.
|
||||
always @ *
|
||||
begin
|
||||
if ( cmd_b_push ) begin
|
||||
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
|
||||
end else begin
|
||||
next_valid_cmd = updated_valid_cmd;
|
||||
end
|
||||
end
|
||||
|
||||
// Valid signals for next cycle.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
|
||||
end else if ( write_valid_cmd ) begin
|
||||
valid_cmd <= next_valid_cmd;
|
||||
end
|
||||
end
|
||||
|
||||
// Detect oldest available command in Queue.
|
||||
always @ *
|
||||
begin
|
||||
// Default to empty.
|
||||
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
|
||||
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
|
||||
if ( next_valid_cmd[index] ) begin
|
||||
collapsed_addr_ptr = index;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Pipe incoming data:
|
||||
//
|
||||
// The B channel is piped to improve timing and avoid impact in search
|
||||
// mechanism due to late arriving signals.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Clock data.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
|
||||
M_AXI_BRESP_I <= 2'b00;
|
||||
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
|
||||
M_AXI_BVALID_I <= 1'b0;
|
||||
end else begin
|
||||
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
|
||||
M_AXI_BVALID_I <= 1'b0;
|
||||
end
|
||||
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
|
||||
M_AXI_BID_I <= M_AXI_BID;
|
||||
M_AXI_BRESP_I <= M_AXI_BRESP;
|
||||
M_AXI_BUSER_I <= M_AXI_BUSER;
|
||||
M_AXI_BVALID_I <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Generate ready to get new transaction.
|
||||
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Inject Error:
|
||||
//
|
||||
// BRESP is modified according to command information.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Inject error in response.
|
||||
always @ *
|
||||
begin
|
||||
if ( inject_error ) begin
|
||||
S_AXI_BRESP = C_RESP_SLVERROR;
|
||||
end else begin
|
||||
S_AXI_BRESP = M_AXI_BRESP_I;
|
||||
end
|
||||
end
|
||||
|
||||
// Handle interrupt generation.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
ERROR_TRIGGER <= 1'b0;
|
||||
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
|
||||
end else begin
|
||||
if ( inject_error & cmd_b_ready_i ) begin
|
||||
ERROR_TRIGGER <= 1'b1;
|
||||
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
|
||||
end else begin
|
||||
ERROR_TRIGGER <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Throttling:
|
||||
//
|
||||
// Response is passed forward when a matching entry has been found in queue.
|
||||
// Both ready and valid are set when the command is completed.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Propagate masked valid.
|
||||
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
|
||||
|
||||
// Return ready with push back.
|
||||
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
|
||||
|
||||
// Command has been handled.
|
||||
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
|
||||
assign cmd_b_ready = cmd_b_ready_i;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Write Response Propagation:
|
||||
//
|
||||
// All information is simply forwarded on from MI- to SI-Side untouched.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// 1:1 mapping.
|
||||
assign S_AXI_BID = M_AXI_BID_I;
|
||||
assign S_AXI_BUSER = M_AXI_BUSER_I;
|
||||
|
||||
|
||||
endmodule
|
||||
+310
@@ -0,0 +1,310 @@
|
||||
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
// Filename: trace_buffer.v
|
||||
// Description: Trace port buffer
|
||||
//-----------------------------------------------------------------------------
|
||||
// Structure: This section shows the hierarchical structure of
|
||||
// pss_wrapper.
|
||||
//
|
||||
// --processing_system7
|
||||
// |
|
||||
// --trace_buffer
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
module processing_system7_v5_5_trace_buffer #
|
||||
(
|
||||
parameter integer FIFO_SIZE = 128,
|
||||
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
|
||||
parameter integer C_DELAY_CLKS = 12
|
||||
)
|
||||
(
|
||||
input wire TRACE_CLK,
|
||||
input wire RST,
|
||||
input wire TRACE_VALID_IN,
|
||||
input wire [3:0] TRACE_ATID_IN,
|
||||
input wire [31:0] TRACE_DATA_IN,
|
||||
output wire TRACE_VALID_OUT,
|
||||
output wire [3:0] TRACE_ATID_OUT,
|
||||
output wire [31:0] TRACE_DATA_OUT
|
||||
);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Architecture section
|
||||
//------------------------------------------------------------
|
||||
|
||||
// function called clogb2 that returns an integer which has the
|
||||
// value of the ceiling of the log base 2.
|
||||
|
||||
function integer clogb2 (input integer bit_depth);
|
||||
integer i;
|
||||
integer temp_log;
|
||||
begin
|
||||
temp_log = 0;
|
||||
for(i=bit_depth; i > 0; i = i>>1)
|
||||
clogb2 = temp_log;
|
||||
temp_log=temp_log+1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam DEPTH = clogb2(FIFO_SIZE-1);
|
||||
|
||||
wire [31:0] reset_zeros;
|
||||
reg [31:0] trace_pedge; // write enable for FIFO
|
||||
reg [31:0] ti;
|
||||
reg [31:0] tom;
|
||||
|
||||
reg [3:0] atid;
|
||||
|
||||
reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
|
||||
|
||||
reg [4:0] dly_ctr;
|
||||
reg [DEPTH-1:0] fifo_wp;
|
||||
reg [DEPTH-1:0] fifo_rp;
|
||||
|
||||
reg fifo_re;
|
||||
wire fifo_empty;
|
||||
wire fifo_full;
|
||||
reg fifo_full_reg;
|
||||
|
||||
assign reset_zeros = 32'h0;
|
||||
|
||||
|
||||
// Pipeline Stage for Traceport ATID ports
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process pedge_ti
|
||||
// rising clock edge
|
||||
if((RST == 1'b1)) begin
|
||||
atid <= reset_zeros;
|
||||
end
|
||||
else begin
|
||||
atid <= TRACE_ATID_IN;
|
||||
end
|
||||
end
|
||||
|
||||
assign TRACE_ATID_OUT = atid;
|
||||
|
||||
/////////////////////////////////////////////
|
||||
// Generate FIFO data based on TRACE_VALID_IN
|
||||
/////////////////////////////////////////////
|
||||
generate
|
||||
if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
|
||||
/////////////////////////////////////////////
|
||||
|
||||
// memory update process
|
||||
// Update memory when positive edge detected and FIFO not full
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
|
||||
trace_fifo[fifo_wp] <= TRACE_DATA_IN;
|
||||
end
|
||||
end
|
||||
|
||||
// fifo write pointer
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process
|
||||
if(RST == 1'b1) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
else if(TRACE_VALID_IN ) begin
|
||||
if(fifo_wp == (FIFO_SIZE - 1)) begin
|
||||
if (fifo_empty) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
end
|
||||
else begin
|
||||
fifo_wp <= fifo_wp + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////
|
||||
// Generate FIFO data based on data edge
|
||||
/////////////////////////////////////////////
|
||||
end else begin : gen_data_edge_detector
|
||||
/////////////////////////////////////////////
|
||||
|
||||
|
||||
// purpose: check for pos edge on any trace input
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process pedge_ti
|
||||
// rising clock edge
|
||||
if((RST == 1'b1)) begin
|
||||
ti <= reset_zeros;
|
||||
trace_pedge <= reset_zeros;
|
||||
end
|
||||
else begin
|
||||
ti <= TRACE_DATA_IN;
|
||||
trace_pedge <= (~ti & TRACE_DATA_IN);
|
||||
//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
|
||||
// posedge only
|
||||
end
|
||||
end
|
||||
|
||||
// memory update process
|
||||
// Update memory when positive edge detected and FIFO not full
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
|
||||
trace_fifo[fifo_wp] <= trace_pedge;
|
||||
end
|
||||
end
|
||||
|
||||
// fifo write pointer
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process
|
||||
if(RST == 1'b1) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
else if(|(trace_pedge) == 1'b1) begin
|
||||
if(fifo_wp == (FIFO_SIZE - 1)) begin
|
||||
if (fifo_empty) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
end
|
||||
else begin
|
||||
fifo_wp <= fifo_wp + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
always @(posedge TRACE_CLK) begin
|
||||
tom <= trace_fifo[fifo_rp] ;
|
||||
end
|
||||
|
||||
|
||||
// // fifo write pointer
|
||||
// always @(posedge TRACE_CLK) begin
|
||||
// // process
|
||||
// if(RST == 1'b1) begin
|
||||
// fifo_wp <= {DEPTH{1'b0}};
|
||||
// end
|
||||
// else if(|(trace_pedge) == 1'b1) begin
|
||||
// if(fifo_wp == (FIFO_SIZE - 1)) begin
|
||||
// fifo_wp <= {DEPTH{1'b0}};
|
||||
// end
|
||||
// else begin
|
||||
// fifo_wp <= fifo_wp + 1;
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
// fifo read pointer update
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(RST == 1'b1) begin
|
||||
fifo_rp <= {DEPTH{1'b0}};
|
||||
fifo_re <= 1'b0;
|
||||
end
|
||||
else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
|
||||
fifo_re <= 1'b1;
|
||||
if(fifo_rp == (FIFO_SIZE - 1)) begin
|
||||
fifo_rp <= {DEPTH{1'b0}};
|
||||
end
|
||||
else begin
|
||||
fifo_rp <= fifo_rp + 1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
fifo_re <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// delay counter update
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(RST == 1'b1) begin
|
||||
dly_ctr <= 5'h0;
|
||||
end
|
||||
else if (fifo_re == 1'b1) begin
|
||||
dly_ctr <= C_DELAY_CLKS-1;
|
||||
end
|
||||
else if(dly_ctr != 5'h0) begin
|
||||
dly_ctr <= dly_ctr - 1;
|
||||
end
|
||||
end
|
||||
|
||||
// fifo empty update
|
||||
assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
|
||||
|
||||
// fifo full update
|
||||
assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
|
||||
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(RST == 1'b1) begin
|
||||
fifo_full_reg <= 1'b0;
|
||||
end
|
||||
else if (fifo_empty) begin
|
||||
fifo_full_reg <= 1'b0;
|
||||
end else begin
|
||||
fifo_full_reg <= fifo_full;
|
||||
end
|
||||
end
|
||||
|
||||
// always @(posedge TRACE_CLK) begin
|
||||
// if(RST == 1'b1) begin
|
||||
// fifo_full_reg <= 1'b0;
|
||||
// end
|
||||
// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
|
||||
// fifo_full_reg <= 1'b1;
|
||||
// end
|
||||
// else begin
|
||||
// fifo_full_reg <= 1'b0;
|
||||
// end
|
||||
// end
|
||||
//
|
||||
assign TRACE_DATA_OUT = tom;
|
||||
|
||||
assign TRACE_VALID_OUT = fifo_re;
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+244
@@ -0,0 +1,244 @@
|
||||
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: Write Channel for ATC
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// w_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module processing_system7_v5_5_w_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_DATA_WIDTH = 64,
|
||||
// Width of all DATA signals on SI and MI side of checker.
|
||||
// Range: 64.
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ARESET,
|
||||
input wire ACLK,
|
||||
|
||||
// Command Interface (In)
|
||||
input wire cmd_w_valid,
|
||||
input wire cmd_w_check,
|
||||
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
|
||||
output wire cmd_w_ready,
|
||||
|
||||
// Command Interface (Out)
|
||||
output wire cmd_b_push,
|
||||
output wire cmd_b_error,
|
||||
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
|
||||
input wire cmd_b_full,
|
||||
|
||||
// Slave Interface Write Port
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
|
||||
input wire S_AXI_WLAST,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
|
||||
input wire S_AXI_WVALID,
|
||||
output wire S_AXI_WREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
|
||||
output wire M_AXI_WLAST,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
|
||||
output wire M_AXI_WVALID,
|
||||
input wire M_AXI_WREADY
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Variables for generating parameter controlled instances.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Detecttion.
|
||||
wire any_strb_deasserted;
|
||||
wire incoming_strb_issue;
|
||||
reg first_word;
|
||||
reg strb_issue;
|
||||
|
||||
// Data flow.
|
||||
wire data_pop;
|
||||
wire cmd_b_push_blocked;
|
||||
reg cmd_b_push_i;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Detect error:
|
||||
//
|
||||
// Detect and accumulate error when a transaction shall be scanned for
|
||||
// potential issues.
|
||||
// Accumulation of error is restarted for each ne transaction.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Check stobe information
|
||||
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
|
||||
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
|
||||
|
||||
// Keep track of first word in a transaction.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
first_word <= 1'b1;
|
||||
end else if ( data_pop ) begin
|
||||
first_word <= S_AXI_WLAST;
|
||||
end
|
||||
end
|
||||
|
||||
// Keep track of error status.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
strb_issue <= 1'b0;
|
||||
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
|
||||
end else if ( data_pop ) begin
|
||||
if ( first_word ) begin
|
||||
strb_issue <= incoming_strb_issue;
|
||||
end else begin
|
||||
strb_issue <= incoming_strb_issue | strb_issue;
|
||||
end
|
||||
cmd_b_id <= cmd_w_id;
|
||||
end
|
||||
end
|
||||
|
||||
assign cmd_b_error = strb_issue;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Control command queue to B:
|
||||
//
|
||||
// Push command to B queue when all data for the transaction has flowed
|
||||
// through.
|
||||
// Delay pipelined command until there is room in the Queue.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Detect when data is popped.
|
||||
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
|
||||
|
||||
// Push command when last word in transfered (pipelined).
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
cmd_b_push_i <= 1'b0;
|
||||
end else begin
|
||||
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
|
||||
end
|
||||
end
|
||||
|
||||
// Detect if pipelined push is blocked.
|
||||
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
|
||||
|
||||
// Assign output.
|
||||
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Throttling:
|
||||
//
|
||||
// Stall commands if FIFO is full or there is no valid command information
|
||||
// from AW.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Propagate masked valid.
|
||||
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
|
||||
|
||||
// Return ready with push back.
|
||||
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
|
||||
|
||||
// End of burst.
|
||||
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Write propagation:
|
||||
//
|
||||
// All information is simply forwarded on from the SI- to MI-Side untouched.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// 1:1 mapping.
|
||||
assign M_AXI_WID = S_AXI_WID;
|
||||
assign M_AXI_WDATA = S_AXI_WDATA;
|
||||
assign M_AXI_WSTRB = S_AXI_WSTRB;
|
||||
assign M_AXI_WLAST = S_AXI_WLAST;
|
||||
assign M_AXI_WUSER = S_AXI_WUSER;
|
||||
|
||||
|
||||
endmodule
|
||||
+2930
File diff suppressed because it is too large
Load Diff
+193178
File diff suppressed because it is too large
Load Diff
+5588
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,79 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
/*
|
||||
* Helper module for synchronizing bit signals from one clock domain to another.
|
||||
* It uses the standard approach of 2 FF in series.
|
||||
* Note, that while the module allows to synchronize multiple bits at once it is
|
||||
* only able to synchronize multi-bit signals where at max one bit changes per
|
||||
* clock cycle (e.g. a gray counter).
|
||||
*/
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module sync_bits #(
|
||||
|
||||
// Number of bits to synchronize
|
||||
parameter NUM_OF_BITS = 1,
|
||||
// Whether input and output clocks are asynchronous, if 0 the synchronizer will
|
||||
// be bypassed and the output signal equals the input signal.
|
||||
parameter ASYNC_CLK = 1)(
|
||||
|
||||
input [NUM_OF_BITS-1:0] in_bits,
|
||||
input out_resetn,
|
||||
input out_clk,
|
||||
output [NUM_OF_BITS-1:0] out_bits);
|
||||
|
||||
generate if (ASYNC_CLK == 1) begin
|
||||
reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
|
||||
reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
|
||||
|
||||
always @(posedge out_clk)
|
||||
begin
|
||||
if (out_resetn == 1'b0) begin
|
||||
cdc_sync_stage1 <= 'b0;
|
||||
cdc_sync_stage2 <= 'b0;
|
||||
end else begin
|
||||
cdc_sync_stage1 <= in_bits;
|
||||
cdc_sync_stage2 <= cdc_sync_stage1;
|
||||
end
|
||||
end
|
||||
|
||||
assign out_bits = cdc_sync_stage2;
|
||||
end else begin
|
||||
assign out_bits = in_bits;
|
||||
end endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,97 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module sync_data #(
|
||||
parameter NUM_OF_BITS = 1,
|
||||
parameter ASYNC_CLK = 1
|
||||
) (
|
||||
input in_clk,
|
||||
input [NUM_OF_BITS-1:0] in_data,
|
||||
input out_clk,
|
||||
output reg [NUM_OF_BITS-1:0] out_data
|
||||
);
|
||||
|
||||
generate
|
||||
if (ASYNC_CLK == 1) begin
|
||||
|
||||
wire out_toggle;
|
||||
wire in_toggle;
|
||||
|
||||
reg out_toggle_d1 = 1'b0;
|
||||
reg in_toggle_d1 = 1'b0;
|
||||
|
||||
reg [NUM_OF_BITS-1:0] cdc_hold;
|
||||
|
||||
sync_bits i_sync_out (
|
||||
.in_bits(in_toggle_d1),
|
||||
.out_clk(out_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(out_toggle)
|
||||
);
|
||||
|
||||
sync_bits i_sync_in (
|
||||
.in_bits(out_toggle_d1),
|
||||
.out_clk(in_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(in_toggle)
|
||||
);
|
||||
|
||||
wire in_load = in_toggle == in_toggle_d1;
|
||||
wire out_load = out_toggle ^ out_toggle_d1;
|
||||
|
||||
always @(posedge in_clk) begin
|
||||
if (in_load == 1'b1) begin
|
||||
cdc_hold <= in_data;
|
||||
in_toggle_d1 <= ~in_toggle_d1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge out_clk) begin
|
||||
if (out_load == 1'b1) begin
|
||||
out_data <= cdc_hold;
|
||||
end
|
||||
out_toggle_d1 <= out_toggle;
|
||||
end
|
||||
|
||||
end else begin
|
||||
always @(*) begin
|
||||
out_data <= in_data;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,120 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module sync_event #(
|
||||
parameter NUM_OF_EVENTS = 1,
|
||||
parameter ASYNC_CLK = 1
|
||||
) (
|
||||
input in_clk,
|
||||
input [NUM_OF_EVENTS-1:0] in_event,
|
||||
input out_clk,
|
||||
output reg [NUM_OF_EVENTS-1:0] out_event
|
||||
);
|
||||
|
||||
generate
|
||||
if (ASYNC_CLK == 1) begin
|
||||
|
||||
wire out_toggle;
|
||||
wire in_toggle;
|
||||
|
||||
reg out_toggle_d1 = 1'b0;
|
||||
reg in_toggle_d1 = 1'b0;
|
||||
|
||||
sync_bits i_sync_out (
|
||||
.in_bits(in_toggle_d1),
|
||||
.out_clk(out_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(out_toggle)
|
||||
);
|
||||
|
||||
sync_bits i_sync_in (
|
||||
.in_bits(out_toggle_d1),
|
||||
.out_clk(in_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(in_toggle)
|
||||
);
|
||||
|
||||
wire in_ready = in_toggle == in_toggle_d1;
|
||||
wire load_out = out_toggle ^ out_toggle_d1;
|
||||
|
||||
reg [NUM_OF_EVENTS-1:0] in_event_sticky = 'h00;
|
||||
wire [NUM_OF_EVENTS-1:0] pending_events = in_event_sticky | in_event;
|
||||
wire [NUM_OF_EVENTS-1:0] out_event_s;
|
||||
|
||||
always @(posedge in_clk) begin
|
||||
if (in_ready == 1'b1) begin
|
||||
in_event_sticky <= {NUM_OF_EVENTS{1'b0}};
|
||||
if (|pending_events == 1'b1) begin
|
||||
in_toggle_d1 <= ~in_toggle_d1;
|
||||
end
|
||||
end else begin
|
||||
in_event_sticky <= pending_events;
|
||||
end
|
||||
end
|
||||
|
||||
if (NUM_OF_EVENTS > 1) begin
|
||||
reg [NUM_OF_EVENTS-1:0] cdc_hold = 'h00;
|
||||
|
||||
always @(posedge in_clk) begin
|
||||
if (in_ready == 1'b1) begin
|
||||
cdc_hold <= pending_events;
|
||||
end
|
||||
end
|
||||
|
||||
assign out_event_s = cdc_hold;
|
||||
end else begin
|
||||
// When there is only one event, we know that it is set.
|
||||
assign out_event_s = 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge out_clk) begin
|
||||
if (load_out == 1'b1) begin
|
||||
out_event <= out_event_s;
|
||||
end else begin
|
||||
out_event <= {NUM_OF_EVENTS{1'b0}};
|
||||
end
|
||||
out_toggle_d1 <= out_toggle;
|
||||
end
|
||||
|
||||
end else begin
|
||||
always @(*) begin
|
||||
out_event <= in_event;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,115 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
/*
|
||||
* Helper module for synchronizing a counter from one clock domain to another
|
||||
* using gray code. To work correctly the counter must not change its value by
|
||||
* more than one in one clock cycle in the source domain. I.e. the value may
|
||||
* change by either -1, 0 or +1.
|
||||
*/
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module sync_gray #(
|
||||
|
||||
// Bit-width of the counter
|
||||
parameter DATA_WIDTH = 1,
|
||||
// Whether the input and output clock are asynchronous, if set to 0 the
|
||||
// synchronizer will be bypassed and out_count will be in_count.
|
||||
parameter ASYNC_CLK = 1)(
|
||||
|
||||
input in_clk,
|
||||
input in_resetn,
|
||||
input [DATA_WIDTH-1:0] in_count,
|
||||
input out_resetn,
|
||||
input out_clk,
|
||||
output [DATA_WIDTH-1:0] out_count);
|
||||
|
||||
generate if (ASYNC_CLK == 1) begin
|
||||
reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
|
||||
reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
|
||||
reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
|
||||
reg [DATA_WIDTH-1:0] out_count_m = 'h0;
|
||||
|
||||
function [DATA_WIDTH-1:0] g2b;
|
||||
input [DATA_WIDTH-1:0] g;
|
||||
reg [DATA_WIDTH-1:0] b;
|
||||
integer i;
|
||||
begin
|
||||
b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
|
||||
for (i = DATA_WIDTH - 2; i >= 0; i = i - 1)
|
||||
b[i] = b[i + 1] ^ g[i];
|
||||
g2b = b;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [DATA_WIDTH-1:0] b2g;
|
||||
input [DATA_WIDTH-1:0] b;
|
||||
reg [DATA_WIDTH-1:0] g;
|
||||
integer i;
|
||||
begin
|
||||
g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
|
||||
for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
|
||||
g[i] = b[i + 1] ^ b[i];
|
||||
b2g = g;
|
||||
end
|
||||
endfunction
|
||||
|
||||
always @(posedge in_clk) begin
|
||||
if (in_resetn == 1'b0) begin
|
||||
cdc_sync_stage0 <= 'h00;
|
||||
end else begin
|
||||
cdc_sync_stage0 <= b2g(in_count);
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge out_clk) begin
|
||||
if (out_resetn == 1'b0) begin
|
||||
cdc_sync_stage1 <= 'h00;
|
||||
cdc_sync_stage2 <= 'h00;
|
||||
out_count_m <= 'h00;
|
||||
end else begin
|
||||
cdc_sync_stage1 <= cdc_sync_stage0;
|
||||
cdc_sync_stage2 <= cdc_sync_stage1;
|
||||
out_count_m <= g2b(cdc_sync_stage2);
|
||||
end
|
||||
end
|
||||
|
||||
assign out_count = out_count_m;
|
||||
end else begin
|
||||
assign out_count = in_count;
|
||||
end endgenerate
|
||||
|
||||
endmodule
|
||||
+152
@@ -0,0 +1,152 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module fifo_address_gray_pipelined #(
|
||||
parameter ADDRESS_WIDTH = 4
|
||||
) (
|
||||
input m_axis_aclk,
|
||||
input m_axis_aresetn,
|
||||
input m_axis_ready,
|
||||
output reg m_axis_valid,
|
||||
output [ADDRESS_WIDTH-1:0] m_axis_raddr,
|
||||
output reg [ADDRESS_WIDTH:0] m_axis_level,
|
||||
|
||||
input s_axis_aclk,
|
||||
input s_axis_aresetn,
|
||||
output reg s_axis_ready,
|
||||
input s_axis_valid,
|
||||
output reg s_axis_empty,
|
||||
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
|
||||
output reg [ADDRESS_WIDTH:0] s_axis_room
|
||||
);
|
||||
|
||||
localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
|
||||
|
||||
reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
|
||||
reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
|
||||
wire [ADDRESS_WIDTH:0] _s_axis_raddr;
|
||||
|
||||
reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
|
||||
reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;
|
||||
wire [ADDRESS_WIDTH:0] _m_axis_waddr;
|
||||
|
||||
assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
|
||||
assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0];
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (s_axis_ready && s_axis_valid)
|
||||
_s_axis_waddr_next <= _s_axis_waddr + 1'b1;
|
||||
else
|
||||
_s_axis_waddr_next <= _s_axis_waddr;
|
||||
end
|
||||
|
||||
always @(posedge s_axis_aclk)
|
||||
begin
|
||||
if (s_axis_aresetn == 1'b0) begin
|
||||
_s_axis_waddr <= 'h00;
|
||||
end else begin
|
||||
_s_axis_waddr <= _s_axis_waddr_next;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (m_axis_ready && m_axis_valid)
|
||||
_m_axis_raddr_next <= _m_axis_raddr + 1'b1;
|
||||
else
|
||||
_m_axis_raddr_next <= _m_axis_raddr;
|
||||
end
|
||||
|
||||
always @(posedge m_axis_aclk)
|
||||
begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
_m_axis_raddr <= 'h00;
|
||||
end else begin
|
||||
_m_axis_raddr <= _m_axis_raddr_next;
|
||||
end
|
||||
end
|
||||
|
||||
sync_gray #(
|
||||
.DATA_WIDTH(ADDRESS_WIDTH + 1)
|
||||
) i_waddr_sync (
|
||||
.in_clk(s_axis_aclk),
|
||||
.in_resetn(s_axis_aresetn),
|
||||
.out_clk(m_axis_aclk),
|
||||
.out_resetn(m_axis_aresetn),
|
||||
.in_count(_s_axis_waddr),
|
||||
.out_count(_m_axis_waddr)
|
||||
);
|
||||
|
||||
sync_gray #(
|
||||
.DATA_WIDTH(ADDRESS_WIDTH + 1)
|
||||
) i_raddr_sync (
|
||||
.in_clk(m_axis_aclk),
|
||||
.in_resetn(m_axis_aresetn),
|
||||
.out_clk(s_axis_aclk),
|
||||
.out_resetn(s_axis_aresetn),
|
||||
.in_count(_m_axis_raddr),
|
||||
.out_count(_s_axis_raddr)
|
||||
);
|
||||
|
||||
always @(posedge s_axis_aclk)
|
||||
begin
|
||||
if (s_axis_aresetn == 1'b0) begin
|
||||
s_axis_ready <= 1'b1;
|
||||
s_axis_empty <= 1'b1;
|
||||
s_axis_room <= MAX_ROOM;
|
||||
end else begin
|
||||
s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] ||
|
||||
_s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]);
|
||||
s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
|
||||
s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + MAX_ROOM;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge m_axis_aclk)
|
||||
begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
m_axis_valid <= 1'b0;
|
||||
m_axis_level <= 'h00;
|
||||
end else begin
|
||||
m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
|
||||
m_axis_level <= _m_axis_waddr - _m_axis_raddr_next;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,109 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module fifo_address_sync #(
|
||||
parameter ADDRESS_WIDTH = 4
|
||||
) (
|
||||
input clk,
|
||||
input resetn,
|
||||
|
||||
input m_axis_ready,
|
||||
output reg m_axis_valid,
|
||||
output reg [ADDRESS_WIDTH-1:0] m_axis_raddr,
|
||||
output [ADDRESS_WIDTH:0] m_axis_level,
|
||||
|
||||
output reg s_axis_ready,
|
||||
input s_axis_valid,
|
||||
output reg s_axis_empty,
|
||||
output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,
|
||||
output [ADDRESS_WIDTH:0] s_axis_room
|
||||
);
|
||||
|
||||
localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
|
||||
|
||||
reg [ADDRESS_WIDTH:0] room = MAX_ROOM;
|
||||
reg [ADDRESS_WIDTH:0] level = 'h00;
|
||||
reg [ADDRESS_WIDTH:0] level_next;
|
||||
|
||||
assign s_axis_room = room;
|
||||
assign m_axis_level = level;
|
||||
|
||||
wire read = m_axis_ready & m_axis_valid;
|
||||
wire write = s_axis_ready & s_axis_valid;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (resetn == 1'b0) begin
|
||||
s_axis_waddr <= 'h00;
|
||||
m_axis_raddr <= 'h00;
|
||||
end else begin
|
||||
if (write)
|
||||
s_axis_waddr <= s_axis_waddr + 1'b1;
|
||||
if (read)
|
||||
m_axis_raddr <= m_axis_raddr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (read & ~write)
|
||||
level_next <= level - 1'b1;
|
||||
else if (~read & write)
|
||||
level_next <= level + 1'b1;
|
||||
else
|
||||
level_next <= level;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (resetn == 1'b0) begin
|
||||
m_axis_valid <= 1'b0;
|
||||
s_axis_ready <= 1'b0;
|
||||
level <= 'h00;
|
||||
room <= MAX_ROOM;
|
||||
s_axis_empty <= 'h00;
|
||||
end else begin
|
||||
level <= level_next;
|
||||
room <= MAX_ROOM - level_next;
|
||||
m_axis_valid <= level_next != 0;
|
||||
s_axis_ready <= level_next != MAX_ROOM;
|
||||
s_axis_empty <= level_next == 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,248 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module util_axis_fifo #(
|
||||
parameter DATA_WIDTH = 64,
|
||||
parameter ASYNC_CLK = 1,
|
||||
parameter ADDRESS_WIDTH = 4,
|
||||
parameter S_AXIS_REGISTERED = 1
|
||||
) (
|
||||
input m_axis_aclk,
|
||||
input m_axis_aresetn,
|
||||
input m_axis_ready,
|
||||
output m_axis_valid,
|
||||
output [DATA_WIDTH-1:0] m_axis_data,
|
||||
output [ADDRESS_WIDTH:0] m_axis_level,
|
||||
|
||||
input s_axis_aclk,
|
||||
input s_axis_aresetn,
|
||||
output s_axis_ready,
|
||||
input s_axis_valid,
|
||||
input [DATA_WIDTH-1:0] s_axis_data,
|
||||
output s_axis_empty,
|
||||
output [ADDRESS_WIDTH:0] s_axis_room
|
||||
);
|
||||
|
||||
generate if (ADDRESS_WIDTH == 0) begin
|
||||
|
||||
reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;
|
||||
reg s_axis_waddr = 1'b0;
|
||||
reg m_axis_raddr = 1'b0;
|
||||
|
||||
wire m_axis_waddr;
|
||||
wire s_axis_raddr;
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(ASYNC_CLK)
|
||||
) i_waddr_sync (
|
||||
.out_clk(m_axis_aclk),
|
||||
.out_resetn(m_axis_aresetn),
|
||||
.in_bits(s_axis_waddr),
|
||||
.out_bits(m_axis_waddr)
|
||||
);
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(ASYNC_CLK)
|
||||
) i_raddr_sync (
|
||||
.out_clk(s_axis_aclk),
|
||||
.out_resetn(s_axis_aresetn),
|
||||
.in_bits(m_axis_raddr),
|
||||
.out_bits(s_axis_raddr)
|
||||
);
|
||||
|
||||
assign m_axis_valid = m_axis_raddr != m_axis_waddr;
|
||||
assign m_axis_level = m_axis_valid;
|
||||
assign s_axis_ready = s_axis_raddr == s_axis_waddr;
|
||||
assign s_axis_empty = s_axis_ready;
|
||||
assign s_axis_room = s_axis_ready;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
|
||||
cdc_sync_fifo_ram <= s_axis_data;
|
||||
end
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_aresetn == 1'b0) begin
|
||||
s_axis_waddr <= 1'b0;
|
||||
end else begin
|
||||
if (s_axis_ready & s_axis_valid) begin
|
||||
s_axis_waddr <= s_axis_waddr + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
m_axis_raddr <= 1'b0;
|
||||
end else begin
|
||||
if (m_axis_valid & m_axis_ready)
|
||||
m_axis_raddr <= m_axis_raddr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign m_axis_data = cdc_sync_fifo_ram;
|
||||
|
||||
end else begin
|
||||
|
||||
reg [DATA_WIDTH-1:0] ram[0:2**ADDRESS_WIDTH-1];
|
||||
|
||||
wire [ADDRESS_WIDTH-1:0] s_axis_waddr;
|
||||
wire [ADDRESS_WIDTH-1:0] m_axis_raddr;
|
||||
wire _m_axis_ready;
|
||||
wire _m_axis_valid;
|
||||
wire [ADDRESS_WIDTH:0] _m_axis_level;
|
||||
|
||||
wire s_mem_write;
|
||||
wire m_mem_read;
|
||||
|
||||
reg valid;
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
valid <= 1'b0;
|
||||
end else begin
|
||||
if (_m_axis_valid)
|
||||
valid <= 1'b1;
|
||||
else if (m_axis_ready)
|
||||
valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign s_mem_write = s_axis_ready & s_axis_valid;
|
||||
assign m_mem_read = (~valid || m_axis_ready) && _m_axis_valid;
|
||||
|
||||
if (ASYNC_CLK == 1) begin
|
||||
|
||||
// The assumption is that in this mode the S_AXIS_REGISTERED is 1
|
||||
|
||||
fifo_address_gray_pipelined #(
|
||||
.ADDRESS_WIDTH(ADDRESS_WIDTH)
|
||||
) i_address_gray (
|
||||
.m_axis_aclk(m_axis_aclk),
|
||||
.m_axis_aresetn(m_axis_aresetn),
|
||||
.m_axis_ready(_m_axis_ready),
|
||||
.m_axis_valid(_m_axis_valid),
|
||||
.m_axis_raddr(m_axis_raddr),
|
||||
.m_axis_level(_m_axis_level),
|
||||
|
||||
.s_axis_aclk(s_axis_aclk),
|
||||
.s_axis_aresetn(s_axis_aresetn),
|
||||
.s_axis_ready(s_axis_ready),
|
||||
.s_axis_valid(s_axis_valid),
|
||||
.s_axis_empty(s_axis_empty),
|
||||
.s_axis_waddr(s_axis_waddr),
|
||||
.s_axis_room(s_axis_room)
|
||||
);
|
||||
|
||||
// When the clocks are asynchronous instantiate a block RAM
|
||||
// regardless of the requested size to make sure we threat the
|
||||
// clock crossing correctly
|
||||
ad_mem #(
|
||||
.DATA_WIDTH (DATA_WIDTH),
|
||||
.ADDRESS_WIDTH (ADDRESS_WIDTH))
|
||||
i_mem (
|
||||
.clka(s_axis_aclk),
|
||||
.wea(s_mem_write),
|
||||
.addra(s_axis_waddr),
|
||||
.dina(s_axis_data),
|
||||
.clkb(m_axis_aclk),
|
||||
.reb(m_mem_read),
|
||||
.addrb(m_axis_raddr),
|
||||
.doutb(m_axis_data)
|
||||
);
|
||||
|
||||
assign _m_axis_ready = ~valid || m_axis_ready;
|
||||
assign m_axis_valid = valid;
|
||||
// the util_axis_fifo is functioning in 'first write fall through' mode,
|
||||
// which means that we need to assure that the value of the level reflects
|
||||
// the actual FIFO level plus the available data, which sits on the bus
|
||||
assign m_axis_level = (m_axis_valid) ? _m_axis_level + 1'b1 : _m_axis_level;
|
||||
|
||||
end else begin
|
||||
|
||||
fifo_address_sync #(
|
||||
.ADDRESS_WIDTH(ADDRESS_WIDTH)
|
||||
) i_address_sync (
|
||||
.clk(m_axis_aclk),
|
||||
.resetn(m_axis_aresetn),
|
||||
.m_axis_ready(_m_axis_ready),
|
||||
.m_axis_valid(_m_axis_valid),
|
||||
.m_axis_raddr(m_axis_raddr),
|
||||
.m_axis_level(m_axis_level),
|
||||
|
||||
.s_axis_ready(s_axis_ready),
|
||||
.s_axis_valid(s_axis_valid),
|
||||
.s_axis_empty(s_axis_empty),
|
||||
.s_axis_waddr(s_axis_waddr),
|
||||
.s_axis_room(s_axis_room)
|
||||
);
|
||||
|
||||
// When the clocks are synchronous use behavioral modeling for the SDP RAM
|
||||
// Let the synthesizer decide what to infer (distributed or block RAM)
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_mem_write)
|
||||
ram[s_axis_waddr] <= s_axis_data;
|
||||
end
|
||||
|
||||
if (S_AXIS_REGISTERED == 1) begin
|
||||
|
||||
reg [DATA_WIDTH-1:0] data;
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_mem_read)
|
||||
data <= ram[m_axis_raddr];
|
||||
end
|
||||
|
||||
assign _m_axis_ready = ~valid || m_axis_ready;
|
||||
assign m_axis_data = data;
|
||||
assign m_axis_valid = valid;
|
||||
|
||||
end else begin
|
||||
|
||||
assign _m_axis_ready = m_axis_ready;
|
||||
assign m_axis_valid = _m_axis_valid;
|
||||
assign m_axis_data = ram[m_axis_raddr];
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
end endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,71 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad_mem #(
|
||||
|
||||
parameter DATA_WIDTH = 16,
|
||||
parameter ADDRESS_WIDTH = 5) (
|
||||
|
||||
input clka,
|
||||
input wea,
|
||||
input [(ADDRESS_WIDTH-1):0] addra,
|
||||
input [(DATA_WIDTH-1):0] dina,
|
||||
|
||||
input clkb,
|
||||
input reb,
|
||||
input [(ADDRESS_WIDTH-1):0] addrb,
|
||||
output reg [(DATA_WIDTH-1):0] doutb);
|
||||
|
||||
(* ram_style = "block" *)
|
||||
reg [(DATA_WIDTH-1):0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
|
||||
|
||||
always @(posedge clka) begin
|
||||
if (wea == 1'b1) begin
|
||||
m_ram[addra] <= dina;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clkb) begin
|
||||
if (reb == 1'b1) begin
|
||||
doutb <= m_ram[addrb];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
+633
@@ -0,0 +1,633 @@
|
||||
// (c) Copyright 2016 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// AXI VIP wrapper
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// axi_vip
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_vip_v1_1_5_top #
|
||||
(
|
||||
parameter C_AXI_PROTOCOL = 0,
|
||||
parameter C_AXI_INTERFACE_MODE = 1, //master, slave and bypass
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_WDATA_WIDTH = 32,
|
||||
parameter integer C_AXI_RDATA_WIDTH = 32,
|
||||
parameter integer C_AXI_WID_WIDTH = 0,
|
||||
parameter integer C_AXI_RID_WIDTH = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_SUPPORTS_NARROW = 1,
|
||||
parameter integer C_AXI_HAS_BURST = 1,
|
||||
parameter integer C_AXI_HAS_LOCK = 1,
|
||||
parameter integer C_AXI_HAS_CACHE = 1,
|
||||
parameter integer C_AXI_HAS_REGION = 1,
|
||||
parameter integer C_AXI_HAS_PROT = 1,
|
||||
parameter integer C_AXI_HAS_QOS = 1,
|
||||
parameter integer C_AXI_HAS_WSTRB = 1,
|
||||
parameter integer C_AXI_HAS_BRESP = 1,
|
||||
parameter integer C_AXI_HAS_RRESP = 1,
|
||||
parameter integer C_AXI_HAS_ARESETN = 1
|
||||
)
|
||||
(
|
||||
//NOTE: C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE
|
||||
//Please refer xgui tcl and coreinfo.yml
|
||||
|
||||
// System Signals
|
||||
input wire aclk,
|
||||
input wire aclken,
|
||||
input wire aresetn,
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_awid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
|
||||
input wire [3-1:0] s_axi_awsize,
|
||||
input wire [2-1:0] s_axi_awburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
|
||||
input wire [4-1:0] s_axi_awcache,
|
||||
input wire [3-1:0] s_axi_awprot,
|
||||
input wire [4-1:0] s_axi_awregion,
|
||||
input wire [4-1:0] s_axi_awqos,
|
||||
input wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
|
||||
input wire s_axi_awvalid,
|
||||
output wire s_axi_awready,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_wid,
|
||||
input wire [C_AXI_WDATA_WIDTH-1:0] s_axi_wdata,
|
||||
input wire [C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb,
|
||||
input wire s_axi_wlast,
|
||||
input wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
|
||||
input wire s_axi_wvalid,
|
||||
output wire s_axi_wready,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_bid,
|
||||
output wire [2-1:0] s_axi_bresp,
|
||||
output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
|
||||
output wire s_axi_bvalid,
|
||||
input wire s_axi_bready,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_arid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
|
||||
input wire [3-1:0] s_axi_arsize,
|
||||
input wire [2-1:0] s_axi_arburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
|
||||
input wire [4-1:0] s_axi_arcache,
|
||||
input wire [3-1:0] s_axi_arprot,
|
||||
input wire [4-1:0] s_axi_arregion,
|
||||
input wire [4-1:0] s_axi_arqos,
|
||||
input wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
|
||||
input wire s_axi_arvalid,
|
||||
output wire s_axi_arready,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_rid,
|
||||
output wire [C_AXI_RDATA_WIDTH-1:0] s_axi_rdata,
|
||||
output wire [2-1:0] s_axi_rresp,
|
||||
output wire s_axi_rlast,
|
||||
output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
|
||||
output wire s_axi_rvalid,
|
||||
input wire s_axi_rready,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_awid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
|
||||
output wire [3-1:0] m_axi_awsize,
|
||||
output wire [2-1:0] m_axi_awburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
|
||||
output wire [4-1:0] m_axi_awcache,
|
||||
output wire [3-1:0] m_axi_awprot,
|
||||
output wire [4-1:0] m_axi_awregion,
|
||||
output wire [4-1:0] m_axi_awqos,
|
||||
output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
|
||||
output wire m_axi_awvalid,
|
||||
input wire m_axi_awready,
|
||||
|
||||
// Master Interface Write Data Ports
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_wid,
|
||||
output wire [C_AXI_WDATA_WIDTH-1:0] m_axi_wdata,
|
||||
output wire [C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb,
|
||||
output wire m_axi_wlast,
|
||||
output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
|
||||
output wire m_axi_wvalid,
|
||||
input wire m_axi_wready,
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_bid,
|
||||
input wire [2-1:0] m_axi_bresp,
|
||||
input wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
|
||||
input wire m_axi_bvalid,
|
||||
output wire m_axi_bready,
|
||||
|
||||
// Master Interface Read Address Port
|
||||
output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_arid,
|
||||
output wire [ C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
|
||||
output wire [3-1:0] m_axi_arsize,
|
||||
output wire [2-1:0] m_axi_arburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
|
||||
output wire [4-1:0] m_axi_arcache,
|
||||
output wire [3-1:0] m_axi_arprot,
|
||||
output wire [4-1:0] m_axi_arregion,
|
||||
output wire [4-1:0] m_axi_arqos,
|
||||
output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
|
||||
output wire m_axi_arvalid,
|
||||
input wire m_axi_arready,
|
||||
|
||||
// Master Interface Read Data Ports
|
||||
input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_rid,
|
||||
input wire [C_AXI_RDATA_WIDTH-1:0] m_axi_rdata,
|
||||
input wire [2-1:0] m_axi_rresp,
|
||||
input wire m_axi_rlast,
|
||||
input wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
|
||||
input wire m_axi_rvalid,
|
||||
output wire m_axi_rready
|
||||
);
|
||||
|
||||
/**********************************************************************************************
|
||||
* NOTE:
|
||||
* C_AXI_INTERFACE_MODE =0 -- MASTER MODE,
|
||||
* C_AXI_INTERFACE_MODE =1 -- PASS-THROUGH MODE
|
||||
* C_AXI_INTERFACE_MODE =2 -- SLAVE MODE
|
||||
* Please refer xgui tcl and coreinfo.yml
|
||||
* User can change PASS_THROUGH VIP to run time master mode or run time slave mode during
|
||||
* the simulation
|
||||
*********************************************************************************************/
|
||||
|
||||
/**********************************************************************************************
|
||||
* Master_mode means that either the dut is statically being configured to be in master mode
|
||||
* or it statically being configured to be pass-through mode and switched to be in master mode
|
||||
* in run time.
|
||||
|
||||
* Slave mode means that either the dut is statically being configured to be in slave mode
|
||||
* or it statically being configured to be pass-through mode and switched to be in slave mode
|
||||
* in run time.
|
||||
|
||||
* Pass-through mode means that either the dut is statically being configured to be in
|
||||
* pass-through mode or it statically being configured to be pass-through mode and switched
|
||||
* to be in master/slave mode and then switch back to be in pass-through mode in run time
|
||||
*********************************************************************************************/
|
||||
|
||||
logic runtime_master =0;
|
||||
logic runtime_slave =0;
|
||||
|
||||
wire run_slave_mode;
|
||||
wire run_master_mode;
|
||||
wire run_passth_mode;
|
||||
wire compile_master_mode;
|
||||
wire compile_slave_mode;
|
||||
wire master_mode;
|
||||
wire slave_mode;
|
||||
|
||||
assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0);
|
||||
assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0;
|
||||
assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0);
|
||||
|
||||
assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode ;
|
||||
assign compile_slave_mode = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode ;
|
||||
|
||||
assign master_mode = compile_master_mode || run_master_mode;
|
||||
assign slave_mode = compile_slave_mode || run_slave_mode;
|
||||
|
||||
// Slave Interface Write Address Ports Internal
|
||||
assign IF.AWID = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.AWADDR = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{1'bz}};
|
||||
assign IF.AWLEN = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
|
||||
assign IF.AWSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{1'bz}};
|
||||
assign IF.AWBURST = slave_mode? s_axi_awburst : {2{1'bz}};
|
||||
assign IF.AWLOCK = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
|
||||
assign IF.AWCACHE = slave_mode? s_axi_awcache : {4{1'bz}};
|
||||
assign IF.AWPROT = slave_mode? s_axi_awprot : {3{1'bz}};
|
||||
assign IF.AWREGION = slave_mode? s_axi_awregion : {4{1'bz}};
|
||||
assign IF.AWQOS = slave_mode? s_axi_awqos : {4{1'bz}};
|
||||
assign IF.AWUSER = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'bz}};
|
||||
assign IF.AWVALID = slave_mode? s_axi_awvalid : {1'bz};
|
||||
assign s_axi_awready = slave_mode? IF.AWREADY : {1'b0};
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
assign IF.WID = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.WDATA = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{1'bz}};
|
||||
assign IF.WSTRB = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}};
|
||||
assign IF.WLAST = slave_mode? s_axi_wlast: {1'bz};
|
||||
assign IF.WUSER = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'bz}};
|
||||
assign IF.WVALID = slave_mode? s_axi_wvalid : {1'bz};
|
||||
assign s_axi_wready = slave_mode? IF.WREADY : {1'b0};
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
assign s_axi_bid = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign s_axi_bresp = slave_mode? IF.BRESP : {2{1'b0}};
|
||||
assign s_axi_buser = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'b0}};
|
||||
assign s_axi_bvalid = slave_mode? IF.BVALID : {1{1'b0}};
|
||||
assign IF.BREADY = slave_mode? s_axi_bready :{1{1'bz}};
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
assign IF.ARID = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
|
||||
assign IF.ARADDR = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{1'bz}} ;
|
||||
assign IF.ARLEN = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
|
||||
assign IF.ARSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{1'bz}};
|
||||
assign IF.ARBURST = slave_mode? s_axi_arburst : {2{1'bz}};
|
||||
assign IF.ARLOCK = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
|
||||
assign IF.ARCACHE = slave_mode? s_axi_arcache : {4{1'bz}};
|
||||
assign IF.ARPROT = slave_mode? s_axi_arprot : {3{1'bz}};
|
||||
assign IF.ARREGION = slave_mode? s_axi_arregion :{4{1'bz}} ;
|
||||
assign IF.ARQOS = slave_mode? s_axi_arqos : {4{1'bz}};
|
||||
assign IF.ARUSER = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'bz}};
|
||||
assign IF.ARVALID = slave_mode? s_axi_arvalid : {1'bz};
|
||||
assign s_axi_arready = slave_mode? IF.ARREADY : {1'b0};
|
||||
|
||||
//Slave Interface Read Data Ports
|
||||
assign s_axi_rid = slave_mode? IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
|
||||
assign s_axi_rdata = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{1'b0}};
|
||||
assign s_axi_rresp = slave_mode? IF.RRESP : {2{1'b0}};
|
||||
assign s_axi_rlast = slave_mode? IF.RLAST : {{1'b0}};
|
||||
assign s_axi_ruser = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'b0}};
|
||||
assign s_axi_rvalid = slave_mode? IF.RVALID : {{1'b0}};
|
||||
assign IF.RREADY = slave_mode? s_axi_rready:{{1'bz}};
|
||||
|
||||
// Master Interface Write Address Port
|
||||
assign m_axi_awid = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign m_axi_awaddr = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{1'b0}};
|
||||
assign m_axi_awlen = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
|
||||
assign m_axi_awsize = master_mode? IF.AWSIZE : {3{1'b0}};
|
||||
assign m_axi_awburst = master_mode? IF.AWBURST : {2{1'b0}};
|
||||
assign m_axi_awlock = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
|
||||
assign m_axi_awcache = master_mode? IF.AWCACHE : {4{1'b0}};
|
||||
assign m_axi_awprot = master_mode? IF.AWPROT : {3{1'b0}};
|
||||
assign m_axi_awregion = master_mode? IF.AWREGION : {4{1'b0}};
|
||||
assign m_axi_awqos = master_mode? IF.AWQOS : {4{1'b0}};
|
||||
assign m_axi_awuser = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'b0}};
|
||||
assign m_axi_awvalid = master_mode? IF.AWVALID :{1'b0};
|
||||
assign IF.AWREADY = master_mode? m_axi_awready :{1'bz};
|
||||
|
||||
// Master Interface Write Data Ports Internal
|
||||
assign m_axi_wid = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign m_axi_wdata = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{1'b0}};
|
||||
assign m_axi_wstrb = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){1'b0}};
|
||||
assign m_axi_wlast = master_mode? IF.WLAST : {1'b0};
|
||||
assign m_axi_wuser = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'b0}};
|
||||
assign m_axi_wvalid = master_mode? IF.WVALID : {1'b0};
|
||||
assign IF.WREADY = master_mode? m_axi_wready : {1'bz};
|
||||
|
||||
// Master Interface Write Response Ports Internal
|
||||
assign IF.BID = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.BRESP = master_mode? m_axi_bresp : {2{1'bz}};
|
||||
assign IF.BUSER = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'bz}};
|
||||
assign IF.BVALID = master_mode? m_axi_bvalid : 1'bz;
|
||||
assign m_axi_bready = master_mode? IF.BREADY : 1'b0;
|
||||
|
||||
// Master Interface Read Address Port Internal
|
||||
assign m_axi_arid = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
|
||||
assign m_axi_araddr = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{1'b0}};
|
||||
assign m_axi_arlen = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
|
||||
assign m_axi_arsize = master_mode? IF.ARSIZE : {3{1'b0}};
|
||||
assign m_axi_arburst = master_mode? IF.ARBURST : {2{1'b0}};
|
||||
assign m_axi_arlock = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
|
||||
assign m_axi_arcache = master_mode?IF.ARCACHE : {4{1'b0}};
|
||||
assign m_axi_arprot = master_mode? IF.ARPROT : {3{1'b0}};
|
||||
assign m_axi_arregion = master_mode? IF.ARREGION : {4{1'b0}};
|
||||
assign m_axi_arqos = master_mode? IF.ARQOS : {4{1'b0}};
|
||||
assign m_axi_aruser = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'b0}};
|
||||
assign m_axi_arvalid = master_mode? IF.ARVALID :{1'b0};
|
||||
assign IF.ARREADY = master_mode? m_axi_arready : {1{1'bz}};
|
||||
|
||||
// Master Interface Read Data Ports Internal
|
||||
assign IF.RID = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
|
||||
assign IF.RDATA = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{1'bz}};
|
||||
assign IF.RRESP = master_mode? m_axi_rresp : {2{1'bz}};
|
||||
assign IF.RLAST = master_mode? m_axi_rlast : {1{1'bz}};
|
||||
assign IF.RUSER = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'bz}};
|
||||
assign IF.RVALID = master_mode? m_axi_rvalid : {1{1'bz}};
|
||||
assign m_axi_rready = master_mode? IF.RREADY : {1{1'b0}};
|
||||
|
||||
axi_vip_if #(
|
||||
.C_AXI_PROTOCOL(C_AXI_PROTOCOL),
|
||||
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ),
|
||||
.C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ),
|
||||
.C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ),
|
||||
.C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ),
|
||||
.C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ),
|
||||
.C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ),
|
||||
.C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ),
|
||||
.C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ),
|
||||
.C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ),
|
||||
.C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ),
|
||||
.C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW),
|
||||
.C_AXI_HAS_BURST(C_AXI_HAS_BURST),
|
||||
.C_AXI_HAS_LOCK(C_AXI_HAS_LOCK),
|
||||
.C_AXI_HAS_CACHE(C_AXI_HAS_CACHE),
|
||||
.C_AXI_HAS_REGION(C_AXI_HAS_REGION),
|
||||
.C_AXI_HAS_PROT(C_AXI_HAS_PROT),
|
||||
.C_AXI_HAS_QOS(C_AXI_HAS_QOS),
|
||||
.C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB),
|
||||
.C_AXI_HAS_BRESP(C_AXI_HAS_BRESP),
|
||||
.C_AXI_HAS_RRESP(C_AXI_HAS_RRESP),
|
||||
.C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN)
|
||||
) IF (
|
||||
.ACLK(aclk),
|
||||
.ARESET_N(aresetn),
|
||||
.ACLKEN(aclken)
|
||||
);
|
||||
|
||||
|
||||
//synthesis translate_off
|
||||
initial begin
|
||||
$display("XilinxAXIVIP: Found at Path: %m");
|
||||
end
|
||||
|
||||
//set IF mode to be in the correct mode according to C_AXI_INTERFACE_MODE,Default is monitor mode
|
||||
generate
|
||||
initial begin
|
||||
if(C_AXI_INTERFACE_MODE ==0) begin
|
||||
IF.set_intf_master;
|
||||
end else if(C_AXI_INTERFACE_MODE ==2) begin
|
||||
IF.set_intf_slave;
|
||||
end else if(C_AXI_INTERFACE_MODE ==1) begin
|
||||
$display("This AXI VIP is in passthrough mode");
|
||||
end else begin
|
||||
$fatal(0,"This AXI VIP's mode is out of range");
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/*
|
||||
Function: set_passthrough_mode
|
||||
Sets AXI VIP passthrough into run time passthrough mode
|
||||
*/
|
||||
function void set_passthrough_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 0;
|
||||
runtime_slave = 0;
|
||||
IF.set_intf_monitor();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_passthrough_mode in the testbench. Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
|
||||
end
|
||||
endfunction: set_passthrough_mode
|
||||
|
||||
/*
|
||||
Function: set_master_mode
|
||||
Sets AXI VIP passthrough into run time master mode
|
||||
*/
|
||||
function void set_master_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 1;
|
||||
runtime_slave = 0;
|
||||
IF.set_intf_master();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_master_mode in the testbench .Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP ");
|
||||
end
|
||||
endfunction : set_master_mode
|
||||
|
||||
/*
|
||||
Function: set_slave_mode
|
||||
Sets AXI VIP passthrough into run time slave mode
|
||||
*/
|
||||
function void set_slave_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 0;
|
||||
runtime_slave = 1;
|
||||
IF.set_intf_slave();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_slave_mode in the testbench.Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
|
||||
end
|
||||
endfunction : set_slave_mode
|
||||
|
||||
/*
|
||||
Function: set_xilinx_slave_ready_check
|
||||
Sets xilinx_slave_ready_check_enable of IF to be 1
|
||||
*/
|
||||
function void set_xilinx_slave_ready_check();
|
||||
IF.xilinx_slave_ready_check_enable = 1;
|
||||
endfunction
|
||||
|
||||
/*
|
||||
Function: clr_xilinx_slave_ready_check
|
||||
Sets xilinx_slave_ready_check_enable of IF to be 0
|
||||
*/
|
||||
function void clr_xilinx_slave_ready_check();
|
||||
IF.xilinx_slave_ready_check_enable = 0;
|
||||
endfunction
|
||||
|
||||
/*
|
||||
Function: set_max_aw_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_aw_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_aw_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_aw_wait_cycles = new_num;
|
||||
endfunction : set_max_aw_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_ar_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_ar_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_ar_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_ar_wait_cycles = new_num;
|
||||
endfunction : set_max_ar_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_r_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_r_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_r_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_r_wait_cycles = new_num;
|
||||
endfunction : set_max_r_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_b_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_b_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_b_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_b_wait_cycles = new_num;
|
||||
endfunction : set_max_b_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_w_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_w_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_w_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_w_wait_cycles = new_num;
|
||||
endfunction : set_max_w_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wlast_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wlast_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wlast_to_awvalid_wait_cycles = new_num;
|
||||
endfunction : set_max_wlast_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_rtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_rtransfers_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_rtransfers_wait_cycles = new_num;
|
||||
endfunction : set_max_rtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wtransfers_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wtransfers_wait_cycles = new_num;
|
||||
endfunction : set_max_wtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wlcmd_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wlcmd_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wlcmd_wait_cycles = new_num;
|
||||
endfunction : set_max_wlcmd_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_aw_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_aw_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_aw_wait_cycles();
|
||||
return(IF.PC.max_aw_wait_cycles);
|
||||
endfunction : get_max_aw_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_ar_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_ar_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_ar_wait_cycles();
|
||||
return(IF.PC.max_ar_wait_cycles);
|
||||
endfunction : get_max_ar_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_r_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_r_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_r_wait_cycles();
|
||||
return(IF.PC.max_r_wait_cycles);
|
||||
endfunction : get_max_r_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_b_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_b_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_b_wait_cycles();
|
||||
return(IF.PC.max_b_wait_cycles);
|
||||
endfunction : get_max_b_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_w_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_w_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_w_wait_cycles();
|
||||
return(IF.PC.max_w_wait_cycles);
|
||||
endfunction :get_max_w_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wlast_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wlast_wait_cycles();
|
||||
return(IF.PC.max_wlast_to_awvalid_wait_cycles);
|
||||
endfunction :get_max_wlast_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_rtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_rtransfers_wait_cycles();
|
||||
return(IF.PC.max_rtransfers_wait_cycles);
|
||||
endfunction :get_max_rtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wtransfers_wait_cycles();
|
||||
return(IF.PC.max_wtransfers_wait_cycles);
|
||||
endfunction :get_max_wtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wlcmd_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wlcmd_wait_cycles();
|
||||
return(IF.PC.max_wlcmd_wait_cycles);
|
||||
endfunction :get_max_wlcmd_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_fatal_to_warnings (not available in VIVADO Simulator)
|
||||
Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 1
|
||||
*/
|
||||
function void set_fatal_to_warnings();
|
||||
IF.PC.fatal_to_warnings = 1;
|
||||
endfunction : set_fatal_to_warnings
|
||||
|
||||
/*
|
||||
Function: clr_fatal_to_warnings (not available in VIVADO Simulator)
|
||||
Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 0
|
||||
*/
|
||||
function void clr_fatal_to_warnings();
|
||||
IF.PC.fatal_to_warnings = 0;
|
||||
endfunction : clr_fatal_to_warnings
|
||||
//synthesis translate_on
|
||||
|
||||
endmodule // axi_vip_v1_1_5_top
|
||||
|
||||
|
||||
+138
@@ -0,0 +1,138 @@
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Generic Functions used by AXI Infrastructure Modules
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
// Global Parameters:
|
||||
//
|
||||
// Functions:
|
||||
//
|
||||
// Tasks:
|
||||
//--------------------------------------------------------------------------
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN Global Parameters
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
localparam G_AXI_AWADDR_INDEX = 0;
|
||||
localparam G_AXI_AWADDR_WIDTH = C_AXI_ADDR_WIDTH;
|
||||
localparam G_AXI_AWPROT_INDEX = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH;
|
||||
localparam G_AXI_AWPROT_WIDTH = 3;
|
||||
localparam G_AXI_AWSIZE_INDEX = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH;
|
||||
localparam G_AXI_AWSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3;
|
||||
localparam G_AXI_AWBURST_INDEX = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH;
|
||||
localparam G_AXI_AWBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2;
|
||||
localparam G_AXI_AWCACHE_INDEX = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH;
|
||||
localparam G_AXI_AWCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||
localparam G_AXI_AWLEN_INDEX = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH;
|
||||
localparam G_AXI_AWLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
|
||||
localparam G_AXI_AWLOCK_INDEX = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH;
|
||||
localparam G_AXI_AWLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
|
||||
localparam G_AXI_AWID_INDEX = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH;
|
||||
localparam G_AXI_AWID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_AWQOS_INDEX = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH;
|
||||
localparam G_AXI_AWQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||
localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH;
|
||||
localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
|
||||
localparam G_AXI_AWUSER_INDEX = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH;
|
||||
localparam G_AXI_AWUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH;
|
||||
localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH;
|
||||
localparam G_AXI_ARADDR_INDEX = 0;
|
||||
localparam G_AXI_ARADDR_WIDTH = C_AXI_ADDR_WIDTH;
|
||||
localparam G_AXI_ARPROT_INDEX = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH;
|
||||
localparam G_AXI_ARPROT_WIDTH = 3;
|
||||
localparam G_AXI_ARSIZE_INDEX = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH;
|
||||
localparam G_AXI_ARSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3;
|
||||
localparam G_AXI_ARBURST_INDEX = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH;
|
||||
localparam G_AXI_ARBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2;
|
||||
localparam G_AXI_ARCACHE_INDEX = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH;
|
||||
localparam G_AXI_ARCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||
localparam G_AXI_ARLEN_INDEX = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH;
|
||||
localparam G_AXI_ARLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
|
||||
localparam G_AXI_ARLOCK_INDEX = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH;
|
||||
localparam G_AXI_ARLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
|
||||
localparam G_AXI_ARID_INDEX = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH;
|
||||
localparam G_AXI_ARID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_ARQOS_INDEX = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH;
|
||||
localparam G_AXI_ARQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||
localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH;
|
||||
localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
|
||||
localparam G_AXI_ARUSER_INDEX = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH;
|
||||
localparam G_AXI_ARUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH;
|
||||
localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH;
|
||||
// Write channel widths
|
||||
localparam G_AXI_WDATA_INDEX = 0;
|
||||
localparam G_AXI_WDATA_WIDTH = C_AXI_DATA_WIDTH;
|
||||
localparam G_AXI_WSTRB_INDEX = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH;
|
||||
localparam G_AXI_WSTRB_WIDTH = C_AXI_DATA_WIDTH / 8;
|
||||
localparam G_AXI_WLAST_INDEX = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH;
|
||||
localparam G_AXI_WLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1;
|
||||
localparam G_AXI_WID_INDEX = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH;
|
||||
localparam G_AXI_WID_WIDTH = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_WUSER_INDEX = G_AXI_WID_INDEX + G_AXI_WID_WIDTH;
|
||||
localparam G_AXI_WUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH;
|
||||
localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH;
|
||||
// Write Response channel Widths
|
||||
localparam G_AXI_BRESP_INDEX = 0;
|
||||
localparam G_AXI_BRESP_WIDTH = 2;
|
||||
localparam G_AXI_BID_INDEX = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH;
|
||||
localparam G_AXI_BID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_BUSER_INDEX = G_AXI_BID_INDEX + G_AXI_BID_WIDTH;
|
||||
localparam G_AXI_BUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH;
|
||||
localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH;
|
||||
// Read channel widths
|
||||
localparam G_AXI_RDATA_INDEX = 0;
|
||||
localparam G_AXI_RDATA_WIDTH = C_AXI_DATA_WIDTH;
|
||||
localparam G_AXI_RRESP_INDEX = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH;
|
||||
localparam G_AXI_RRESP_WIDTH = 2;
|
||||
localparam G_AXI_RLAST_INDEX = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH;
|
||||
localparam G_AXI_RLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1;
|
||||
localparam G_AXI_RID_INDEX = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH;
|
||||
localparam G_AXI_RID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_RUSER_INDEX = G_AXI_RID_INDEX + G_AXI_RID_WIDTH;
|
||||
localparam G_AXI_RUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH;
|
||||
localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH;
|
||||
+670
@@ -0,0 +1,670 @@
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// axis to vector
|
||||
// A generic module to merge all axi signals into one signal called payload.
|
||||
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_axi2vector #
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter integer C_AXI_PROTOCOL = 0,
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_DATA_WIDTH = 32,
|
||||
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
|
||||
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
parameter integer C_AWPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_WPAYLOAD_WIDTH = 73,
|
||||
parameter integer C_BPAYLOAD_WIDTH = 6,
|
||||
parameter integer C_ARPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_RPAYLOAD_WIDTH = 69
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
|
||||
input wire [3-1:0] s_axi_awsize,
|
||||
input wire [2-1:0] s_axi_awburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
|
||||
input wire [4-1:0] s_axi_awcache,
|
||||
input wire [3-1:0] s_axi_awprot,
|
||||
input wire [4-1:0] s_axi_awregion,
|
||||
input wire [4-1:0] s_axi_awqos,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
|
||||
input wire s_axi_wlast,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
|
||||
output wire [2-1:0] s_axi_bresp,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
|
||||
input wire [3-1:0] s_axi_arsize,
|
||||
input wire [2-1:0] s_axi_arburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
|
||||
input wire [4-1:0] s_axi_arcache,
|
||||
input wire [3-1:0] s_axi_arprot,
|
||||
input wire [4-1:0] s_axi_arregion,
|
||||
input wire [4-1:0] s_axi_arqos,
|
||||
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
|
||||
output wire [2-1:0] s_axi_rresp,
|
||||
output wire s_axi_rlast,
|
||||
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
|
||||
|
||||
// payloads
|
||||
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
|
||||
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
|
||||
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
|
||||
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
|
||||
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`include "axi_infrastructure_v1_1_0.vh"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// AXI4, AXI4LITE, AXI3 packing
|
||||
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
|
||||
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
|
||||
|
||||
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
|
||||
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
|
||||
|
||||
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
|
||||
|
||||
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
|
||||
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
|
||||
|
||||
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
|
||||
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
|
||||
|
||||
generate
|
||||
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
|
||||
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
|
||||
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
|
||||
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
|
||||
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
|
||||
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
|
||||
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
|
||||
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
|
||||
|
||||
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
|
||||
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
|
||||
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
|
||||
end
|
||||
else begin : gen_no_axi3_wid_packing
|
||||
end
|
||||
|
||||
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
|
||||
|
||||
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
|
||||
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
|
||||
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
|
||||
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
|
||||
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
|
||||
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
|
||||
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
|
||||
|
||||
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
|
||||
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
|
||||
|
||||
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
|
||||
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
|
||||
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
|
||||
end
|
||||
else begin : gen_no_region_signals
|
||||
end
|
||||
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
|
||||
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
|
||||
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
|
||||
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
|
||||
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
|
||||
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
|
||||
end
|
||||
else begin : gen_no_user_signals
|
||||
assign s_axi_buser = 'b0;
|
||||
assign s_axi_ruser = 'b0;
|
||||
end
|
||||
end
|
||||
else begin : gen_axi4lite_packing
|
||||
assign s_axi_bid = 'b0;
|
||||
assign s_axi_buser = 'b0;
|
||||
|
||||
assign s_axi_rlast = 1'b1;
|
||||
assign s_axi_rid = 'b0;
|
||||
assign s_axi_ruser = 'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
// Description: SRL based FIFO for AXIS/AXI Channels.
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter C_FAMILY = "virtex7",
|
||||
parameter integer C_PAYLOAD_WIDTH = 1,
|
||||
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
input wire aclk, // Clock
|
||||
input wire aresetn, // Reset
|
||||
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
|
||||
input wire s_valid, // Input data valid
|
||||
output reg s_ready, // Input data ready
|
||||
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
|
||||
output reg m_valid, // Output data valid
|
||||
input wire m_ready // Output data ready
|
||||
);
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ceiling logb2
|
||||
function integer f_clogb2 (input integer size);
|
||||
integer s;
|
||||
begin
|
||||
s = size;
|
||||
s = s - 1;
|
||||
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
|
||||
s = s >> 1;
|
||||
end
|
||||
endfunction // clogb2
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
|
||||
wire [4-1:0] fifo_addr;
|
||||
wire push;
|
||||
wire pop ;
|
||||
reg areset_r1;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
always @(posedge aclk) begin
|
||||
areset_r1 <= ~aresetn;
|
||||
end
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
|
||||
end
|
||||
else begin
|
||||
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
|
||||
~push & pop ? fifo_index - 1'b1 :
|
||||
fifo_index;
|
||||
end
|
||||
end
|
||||
|
||||
assign push = s_valid & s_ready;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
s_ready <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
s_ready <= areset_r1 ? 1'b1 :
|
||||
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
|
||||
~push & pop ? 1'b1 :
|
||||
s_ready;
|
||||
end
|
||||
end
|
||||
|
||||
assign pop = m_valid & m_ready;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
m_valid <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
|
||||
push & ~pop ? 1'b1 :
|
||||
m_valid;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
|
||||
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
|
||||
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
|
||||
end
|
||||
else begin : gen_fifo_addr
|
||||
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
|
||||
SRL16E
|
||||
u_srl_fifo(
|
||||
.Q ( m_payload[i] ) ,
|
||||
.A0 ( fifo_addr[0] ) ,
|
||||
.A1 ( fifo_addr[1] ) ,
|
||||
.A2 ( fifo_addr[2] ) ,
|
||||
.A3 ( fifo_addr[3] ) ,
|
||||
.CE ( push ) ,
|
||||
.CLK ( aclk ) ,
|
||||
.D ( s_payload[i] )
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// axi to vector
|
||||
// A generic module to merge all axi signals into one signal called payload.
|
||||
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_vector2axi #
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter integer C_AXI_PROTOCOL = 0,
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_DATA_WIDTH = 32,
|
||||
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
|
||||
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
parameter integer C_AWPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_WPAYLOAD_WIDTH = 73,
|
||||
parameter integer C_BPAYLOAD_WIDTH = 6,
|
||||
parameter integer C_ARPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_RPAYLOAD_WIDTH = 69
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Slave Interface Write Address Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
|
||||
output wire [3-1:0] m_axi_awsize,
|
||||
output wire [2-1:0] m_axi_awburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
|
||||
output wire [4-1:0] m_axi_awcache,
|
||||
output wire [3-1:0] m_axi_awprot,
|
||||
output wire [4-1:0] m_axi_awregion,
|
||||
output wire [4-1:0] m_axi_awqos,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
|
||||
output wire m_axi_wlast,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
|
||||
input wire [2-1:0] m_axi_bresp,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
|
||||
output wire [3-1:0] m_axi_arsize,
|
||||
output wire [2-1:0] m_axi_arburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
|
||||
output wire [4-1:0] m_axi_arcache,
|
||||
output wire [3-1:0] m_axi_arprot,
|
||||
output wire [4-1:0] m_axi_arregion,
|
||||
output wire [4-1:0] m_axi_arqos,
|
||||
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
|
||||
input wire [2-1:0] m_axi_rresp,
|
||||
input wire m_axi_rlast,
|
||||
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
|
||||
|
||||
// payloads
|
||||
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
|
||||
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
|
||||
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
|
||||
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
|
||||
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`include "axi_infrastructure_v1_1_0.vh"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// AXI4, AXI4LITE, AXI3 packing
|
||||
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
|
||||
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
|
||||
|
||||
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
|
||||
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
|
||||
|
||||
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
|
||||
|
||||
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
|
||||
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
|
||||
|
||||
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
|
||||
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
|
||||
|
||||
generate
|
||||
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
|
||||
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
|
||||
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
|
||||
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
|
||||
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
|
||||
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
|
||||
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
|
||||
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
|
||||
|
||||
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
|
||||
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
|
||||
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
|
||||
end
|
||||
else begin : gen_no_axi3_wid_packing
|
||||
assign m_axi_wid = 1'b0;
|
||||
end
|
||||
|
||||
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
|
||||
|
||||
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
|
||||
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
|
||||
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
|
||||
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
|
||||
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
|
||||
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
|
||||
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
|
||||
|
||||
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
|
||||
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
|
||||
|
||||
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
|
||||
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
|
||||
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
|
||||
end
|
||||
else begin : gen_no_region_signals
|
||||
assign m_axi_awregion = 'b0;
|
||||
assign m_axi_arregion = 'b0;
|
||||
end
|
||||
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
|
||||
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
|
||||
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
|
||||
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
|
||||
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
|
||||
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
|
||||
end
|
||||
else begin : gen_no_user_signals
|
||||
assign m_axi_awuser = 'b0;
|
||||
assign m_axi_wuser = 'b0;
|
||||
assign m_axi_aruser = 'b0;
|
||||
end
|
||||
end
|
||||
else begin : gen_axi4lite_packing
|
||||
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
|
||||
assign m_axi_awburst = 'b0;
|
||||
assign m_axi_awcache = 'b0;
|
||||
assign m_axi_awlen = 'b0;
|
||||
assign m_axi_awlock = 'b0;
|
||||
assign m_axi_awid = 'b0;
|
||||
assign m_axi_awqos = 'b0;
|
||||
|
||||
assign m_axi_wlast = 1'b1;
|
||||
assign m_axi_wid = 'b0;
|
||||
|
||||
|
||||
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
|
||||
assign m_axi_arburst = 'b0;
|
||||
assign m_axi_arcache = 'b0;
|
||||
assign m_axi_arlen = 'b0;
|
||||
assign m_axi_arlock = 'b0;
|
||||
assign m_axi_arid = 'b0;
|
||||
assign m_axi_arqos = 'b0;
|
||||
|
||||
assign m_axi_awregion = 'b0;
|
||||
assign m_axi_arregion = 'b0;
|
||||
|
||||
assign m_axi_awuser = 'b0;
|
||||
assign m_axi_wuser = 'b0;
|
||||
assign m_axi_aruser = 'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
+1263
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user