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update dl814_z7 and dl814_cal_coarse

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change frame header of nulling algorithm data in chip-to-chip communication, add several sets of noise data sampled with 814 board
This commit is contained in:
josh
2023-04-05 15:17:14 +08:00
parent d2c22dbeb5
commit 5402f12cf2
122 changed files with 1966442 additions and 24591 deletions
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projects/datalink_814/dl814_z7/project/project_005/project_005.runs/impl_1/system_top.bit
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projects/datalink_814/dl814_z7/project/project_005/project_005.sdk/dl814_null/src/config/app_config.h
+1 -1
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@@ -40,7 +40,7 @@
#define XGPIO_OUTPUT_CH 1
#define XGPIO_INPUT_CH 2
#define C2C_RXBUFF_BASSADDR (XPAR_PS7_RAM_0_S_AXI_BASEADDR + 0x00004000)
#define C2C_RXBUFF_BASSADDR (XPAR_PS7_RAM_0_S_AXI_BASEADDR + 0x00014000)
#define C2C_TXBUFF_BASSADDR (C2C_RXBUFF_BASSADDR + C2C_BUFF_SIZE*C2C_BUFF_NUM)
#define C2C_BUFF_SIZE 1024
#define C2C_BUFF_NUM 16
projects/datalink_814/dl814_z7/project/project_005/project_005.sdk/dl814_null/src/lscript.ld
+1 -1
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@@ -23,7 +23,7 @@ _UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
MEMORY
{
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000
ps7_ddr_0 : ORIGIN = 0x10000000, LENGTH = 0x10000000
ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
projects/datalink_814/dl814_z7/project/project_005/project_005.sdk/dl814_null/src/main.c
+47 -17
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@@ -37,11 +37,12 @@
#include "c2c_bridge/c2c_bridge.h"
#include "common.h"
#include "error.h"
#include "mmu_ctrl.h"
#include "config/app_config.h"
#include "xstatus.h"
/************************** Function Prototypes ******************************/
int SetupInterruptSystem(uint32_t devId, XScuGic* instPtr);
int SetupInterruptSystem(XScuGic* instPtr, uint32_t devId);
// C2C bridge
void C2c_TxIntrHandler(void *Callback);
void C2c_RxIntrHandler(void *Callback);
@@ -66,10 +67,6 @@ typedef struct {
/*********************** Driver Instance Definitions **************************/
static XScuGic intcInst; // General interrupt controller instance
int32_t c2cRxBuffInt32[C2C_BUFF_MAX/sizeof(int32_t)];
int32_t c2cTxBuffInt32[C2C_BUFF_MAX/sizeof(int32_t)];
float_t c2cRxBuffFloat[C2C_BUFF_MAX/sizeof(int32_t)];
float_t c2cTxBuffFloat[C2C_BUFF_MAX/sizeof(int32_t)];
C2C_EXTRA c2cExtraBuff;
XGpio PwdownGpio;
XTime xTimeGlobalTic;
@@ -92,7 +89,7 @@ static double calcTime_us;
* XST_FAILURE if initialization failed.
*
*****************************************************************************/
int SetupInterruptSystem(uint32_t deviceID, XScuGic* instPtr) {
int SetupInterruptSystem(XScuGic* instPtr, uint32_t deviceID) {
XScuGic_Config *configPtr;
int Status;
uint32_t intrState;
@@ -147,8 +144,10 @@ int SetupInterruptSystem(uint32_t deviceID, XScuGic* instPtr) {
}
// Enable interrupts for IRQ_F2P
XScuGic_Enable(instPtr, C2C_TX_INTR_ID);
XScuGic_InterruptMaptoCpu(instPtr, XPAR_CPU_ID, C2C_RX_INTR_ID);
XScuGic_Enable(instPtr, C2C_RX_INTR_ID);
XScuGic_InterruptMaptoCpu(instPtr, XPAR_CPU_ID, C2C_TX_INTR_ID);
XScuGic_Enable(instPtr, C2C_TX_INTR_ID);
/* Initialize the exception table and register the interrupt controller
* handler with the exception table
@@ -205,13 +204,18 @@ void C2c_TxIntrHandler(void *Callback) {
*
*****************************************************************************/
void C2c_RxIntrHandler(void *callBackRef) {
int32_t Status = SUCCESS;
uint32_t c2cRecvLen = 0;
Status = C2c_RecvData(c2cInstPtr, (uint8_t*)c2cRxBuffInt32, &c2cRecvLen);
int32_t Status;
uint32_t c2cRecvLen;
float_t c2cRxBuffFloat[CMPLX_DIM*CHANNEL_NUMBER*CHANNEL_NUMBER];
float_t c2cTxBuffFloat[CMPLX_DIM*CHANNEL_NUMBER*CHANNEL_NUMBER];
int32_t *c2cRxBuffInt32 = (int32_t *)(C2C_RXBUFF_BASSADDR + C2C_PLOAD_OFFSET);
int32_t *c2cTxBuffInt32 = (int32_t *)(C2C_TXBUFF_BASSADDR + C2C_PLOAD_OFFSET);
Status = C2c_RecvIrqHandler(c2cInstPtr);
if(Status != SUCCESS){
DBG_ERROR("C2C data receive error, with error code: %d.\r\n",Status);
}
else{
c2cRecvLen = (IO_In32(c2cInstPtr->lastRxBuff + C2C_DLEN_OFFSET) - C2C_HEADER_LEN);
if (c2cRecvLen == 4*CMPLX_DIM*CHANNEL_NUMBER*CHANNEL_NUMBER)
{
for (int i = 0; i < CMPLX_DIM*CHANNEL_NUMBER*CHANNEL_NUMBER; i++)
@@ -231,7 +235,7 @@ void C2c_RxIntrHandler(void *callBackRef) {
c2cTxBuffInt32[i] = (int32_t)c2cTxBuffFloat[i];
}
Status = C2c_SendData(c2cInstPtr, (uint8_t*) c2cTxBuffInt32, 4*CMPLX_DIM*CHANNEL_NUMBER);
Status = C2c_SendData(c2cInstPtr, (uint8_t*) C2C_TXBUFF_BASSADDR, 4*CMPLX_DIM*CHANNEL_NUMBER);
if (Status != SUCCESS)
{
DBG_ERROR("C2C data send error, with error code: %d.\r\n",Status);
@@ -242,6 +246,14 @@ void C2c_RxIntrHandler(void *callBackRef) {
DBG_ERROR("Autocorrelation data number check failed.\r\n");
}
}
// Start C2C listening.
Status = C2c_RecvData(c2cInstPtr, (uint8_t *)C2C_RXBUFF_BASSADDR, C2C_BUFF_MAX);
if (Status == SUCCESS) {
DBG_INFO("C2c start listening SUCCESS!\r\n");
}
else {
DBG_ERROR("C2c message listening enable FAILED, with error code: %d.\r\n", Status);
}
return;
} // C2cRxIntr_Handler
@@ -333,8 +345,11 @@ arm_status weigh_vec_calc(float32_t * accorMat, float32_t * weightVec)
*
******************************************************************************/
int main(void) {
// Xil_ICacheEnable();
// Xil_DCacheDisable();
Xil_SetTlbAttributes(0x00000000,
MMU_L1_SECT | MMU_L1_DOMAIN(15) | MMU_L1_SHAREABLE
| MMU_L1_GLOBAL | MMU_L1_EXEC | MMU_L1_FULLACS
| 0x00001000); //non-cacheable
int Status = SUCCESS;
// Initialize C2C bridge
@@ -348,7 +363,7 @@ int main(void) {
}
// Initialize GIC.
Status = SetupInterruptSystem(INTC_DEVICE_ID, &intcInst);
Status = SetupInterruptSystem(&intcInst, INTC_DEVICE_ID);
if (Status == SUCCESS) {
DBG_INFO("Intc Init SUCCESS! \r\n");
}
@@ -357,6 +372,24 @@ int main(void) {
return Status;
}
// Start C2C listening.
Status = C2c_RecvData(c2cInstPtr, (uint8_t *)C2C_RXBUFF_BASSADDR, C2C_BUFF_MAX);
if (Status == SUCCESS) {
DBG_INFO("C2c start listening SUCCESS!\r\n");
}
else {
DBG_ERROR("C2c message listening enable FAILED, with error code: %d.\r\n", Status);
return Status;
}
Status = C2c_IrqEnable(c2cInstPtr);
if (Status == SUCCESS) {
DBG_INFO("C2c interrupts enable SUCCESS!\r\n");
}
else {
DBG_ERROR("C2c interrupts enable FAILED, with error code: %d.\r\n", Status);
return Status;
}
while(true){
// main loop
}
@@ -368,9 +401,6 @@ int main(void) {
int main_old(void)
{
Xil_ICacheEnable();
Xil_DCacheDisable();
arm_status status = ARM_MATH_SUCCESS;
float32_t data_snapshot_cov[CHANNEL_NUMBER*CHANNEL_NUMBER*CMPLX_DIM] =
projects/datalink_814/dl814_z7/project/project_005/project_005.sdk/dl814_null/src/mmu_ctrl.h
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@@ -0,0 +1,26 @@
/*
* mmu_ctrl.h
*
* Created on: 2023Äê1ÔÂ7ÈÕ
* Author: Gatsby_Van
*/
#ifndef SRC_MMU_CTRL_H_
#define SRC_MMU_CTRL_H_
#include "xil_mmu.h"
#define MMU_L1_PAGE 0x00000001
#define MMU_L1_SECT 0x00000002
#define MMU_L1_SUPERSECT 0x00040002
#define MMU_L1_DOMAIN(x) ((x & 0x0F) << 4)
#define MMU_L1_SHAREABLE 0x00010000
#define MMU_L1_NON_SHAREABLE 0x00000000
#define MMU_L1_GLOBAL 0x00000000
#define MMU_L1_NON_GLOBAL 0x00020000
#define MMU_L1_EXEC 0x00000000
#define MMU_L1_NON_EXEC 0x00000010
#define MMU_L1_EXEC 0x00000000
#define MMU_L1_NON_EXEC 0x00000010
#define MMU_L1_NONACS 0x00000000
#define MMU_L1_FULLACS 0x00000C00
#endif /* SRC_MMU_CTRL_H_ */
projects/datalink_814/dl814_z7/project/project_005/project_005.sdk/dl814_null_bsp/Makefile
+2 -2
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@@ -23,11 +23,11 @@ $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
@echo "Running Make include in $(subst /make.include,,$@)"
$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -DUSE_AMP=1"
%/make.libs: include
@echo "Running Make libs in $(subst /make.libs,,$@)"
$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -DUSE_AMP=1"
%/make.clean:
$(MAKE) -C $(subst /make.clean,,$@) -s clean
projects/datalink_814/dl814_z7/project/project_005/project_005.sdk/dl814_null_bsp/system.mss
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@@ -15,6 +15,7 @@ BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu_cortexa9
PARAMETER DRIVER_VER = 2.7
PARAMETER HW_INSTANCE = ps7_cortexa9_1
PARAMETER extra_compiler_flags = -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -DUSE_AMP=1
END
projects/datalink_814/dl814_z7/project/project_005/project_005.sdk/phy_bc/src/lscript.ld
+1 -1
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@@ -23,7 +23,7 @@ _UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
MEMORY
{
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0xFF00000
ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
projects/datalink_814/dl814_z7/project/project_005/project_005.sdk/phy_bc/src/main.c
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@@ -407,8 +407,6 @@ void Glink_RxIntrHandler(void *Callback){
*
******************************************************************************/
int main(void) {
// Xil_ICacheEnable();
// Xil_DCacheDisable();
Xil_SetTlbAttributes(0x00000000,
MMU_L1_SECT | MMU_L1_DOMAIN(15) | MMU_L1_SHAREABLE
| MMU_L1_GLOBAL | MMU_L1_EXEC | MMU_L1_FULLACS
projects/datalink_814/dl814_z7/project/project_005/project_005.sdk/system_top.hdf
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