update dl814_z7 and dl814_cal_coarse

change frame header of nulling algorithm data in chip-to-chip communication, add several sets of noise data sampled with 814 board
2023-04-05 15:17:14 +08:00
parent d2c22dbeb5
commit 5402f12cf2
122 changed files with 1966442 additions and 24591 deletions
@@ -3,8 +3,8 @@
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
 // Date        : Mon Apr  3 20:43:37 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-// Command     : write_verilog -force -mode funcsim
+// Command     : write_verilog -force -mode funcsim -rename_top rom_hop_data -prefix
-//               /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_sim_netlist.v
+//               rom_hop_data_ rom_hop_data_sim_netlist.v
 // Design      : rom_hop_data
 // Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
 //               or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -188,7 +188,6 @@ module rom_hop_data
        .web(1'b0));
 endmodule
 (* ORIG_REF_NAME = "bindec" *) 
 module rom_hop_data_bindec
   (ena_array,
    addra);
@@ -209,7 +208,6 @@ module rom_hop_data_bindec
        .O(ena_array));
 endmodule
 (* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) 
 module rom_hop_data_blk_mem_gen_generic_cstr
   (douta,
    clka,
@@ -818,7 +816,6 @@ module rom_hop_data_blk_mem_gen_generic_cstr
        .clka(clka));
 endmodule
 (* ORIG_REF_NAME = "blk_mem_gen_mux" *) 
 module rom_hop_data_blk_mem_gen_mux
   (douta,
    DOADO,
@@ -2959,7 +2956,6 @@ module rom_hop_data_blk_mem_gen_mux
        .R(1'b0));
 endmodule
 (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) 
 module rom_hop_data_blk_mem_gen_prim_width
   (ram_douta,
    clka,
@@ -3685,7 +3681,6 @@ module rom_hop_data_blk_mem_gen_prim_width__parameterized9
        .clka(clka));
 endmodule
 (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) 
 module rom_hop_data_blk_mem_gen_prim_wrapper_init
   (ram_douta,
    clka,
@@ -10110,7 +10105,6 @@ module rom_hop_data_blk_mem_gen_prim_wrapper_init__parameterized9
        .O(addra_13_sn_1));
 endmodule
 (* ORIG_REF_NAME = "blk_mem_gen_top" *) 
 module rom_hop_data_blk_mem_gen_top
   (douta,
    clka,
@@ -10154,7 +10148,7 @@ endmodule
 (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "9600" *) 
 (* C_WRITE_DEPTH_B = "9600" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) 
 (* C_WRITE_WIDTH_A = "96" *) (* C_WRITE_WIDTH_B = "96" *) (* C_XDEVICEFAMILY = "kintex7" *) 
-(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3" *) (* downgradeipidentifiedwarnings = "yes" *) 
+(* downgradeipidentifiedwarnings = "yes" *) 
 module rom_hop_data_blk_mem_gen_v8_4_3
   (clka,
    rsta,
@@ -10540,7 +10534,6 @@ module rom_hop_data_blk_mem_gen_v8_4_3
        .douta(douta));
 endmodule
 (* ORIG_REF_NAME = "blk_mem_gen_v8_4_3_synth" *) 
 module rom_hop_data_blk_mem_gen_v8_4_3_synth
   (douta,
    clka,
@@ -3,8 +3,8 @@
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
 -- Date        : Mon Apr  3 20:43:37 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command     : write_vhdl -force -mode funcsim
+-- Command     : write_vhdl -force -mode funcsim -rename_top rom_hop_data -prefix
--               /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_sim_netlist.vhdl
+--               rom_hop_data_ rom_hop_data_sim_netlist.vhdl
 -- Design      : rom_hop_data
 -- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
 --               synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -19,8 +19,6 @@ entity rom_hop_data_bindec is
    ena_array : out STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of rom_hop_data_bindec : entity is "bindec";
 end rom_hop_data_bindec;
 architecture STRUCTURE of rom_hop_data_bindec is
@@ -101,8 +99,6 @@ entity rom_hop_data_blk_mem_gen_mux is
    \douta[95]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \douta[95]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of rom_hop_data_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
 end rom_hop_data_blk_mem_gen_mux;
 architecture STRUCTURE of rom_hop_data_blk_mem_gen_mux is
@@ -2734,8 +2730,6 @@ entity rom_hop_data_blk_mem_gen_prim_wrapper_init is
    \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of rom_hop_data_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
 end rom_hop_data_blk_mem_gen_prim_wrapper_init;
 architecture STRUCTURE of rom_hop_data_blk_mem_gen_prim_wrapper_init is
@@ -9333,8 +9327,6 @@ entity rom_hop_data_blk_mem_gen_prim_width is
    \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of rom_hop_data_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
 end rom_hop_data_blk_mem_gen_prim_width;
 architecture STRUCTURE of rom_hop_data_blk_mem_gen_prim_width is
@@ -10061,8 +10053,6 @@ entity rom_hop_data_blk_mem_gen_generic_cstr is
    clka : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of rom_hop_data_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
 end rom_hop_data_blk_mem_gen_generic_cstr;
 architecture STRUCTURE of rom_hop_data_blk_mem_gen_generic_cstr is
@@ -11331,8 +11321,6 @@ entity rom_hop_data_blk_mem_gen_top is
    clka : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of rom_hop_data_blk_mem_gen_top : entity is "blk_mem_gen_top";
 end rom_hop_data_blk_mem_gen_top;
 architecture STRUCTURE of rom_hop_data_blk_mem_gen_top is
@@ -11354,8 +11342,6 @@ entity rom_hop_data_blk_mem_gen_v8_4_3_synth is
    clka : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of rom_hop_data_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth";
 end rom_hop_data_blk_mem_gen_v8_4_3_synth;
 architecture STRUCTURE of rom_hop_data_blk_mem_gen_v8_4_3_synth is
@@ -11587,8 +11573,6 @@ entity rom_hop_data_blk_mem_gen_v8_4_3 is
  attribute C_WRITE_WIDTH_B of rom_hop_data_blk_mem_gen_v8_4_3 : entity is 96;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of rom_hop_data_blk_mem_gen_v8_4_3 : entity is "kintex7";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of rom_hop_data_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of rom_hop_data_blk_mem_gen_v8_4_3 : entity is "yes";
 end rom_hop_data_blk_mem_gen_v8_4_3;
@@ -3,8 +3,8 @@
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
 // Date        : Mon Apr  3 20:43:37 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-// Command     : write_verilog -force -mode synth_stub
+// Command     : write_verilog -force -mode synth_stub -rename_top rom_hop_data -prefix
-//               /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.v
+//               rom_hop_data_ rom_hop_data_stub.v
 // Design      : rom_hop_data
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7k410tffg900-2
@@ -3,8 +3,8 @@
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
 -- Date        : Mon Apr  3 20:43:37 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command     : write_vhdl -force -mode synth_stub
+-- Command     : write_vhdl -force -mode synth_stub -rename_top rom_hop_data -prefix
--               /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.vhdl
+--               rom_hop_data_ rom_hop_data_stub.vhdl
 -- Design      : rom_hop_data
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7k410tffg900-2
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
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-# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
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@@ -9,7 +9,7 @@
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+# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
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@@ -4,7 +4,7 @@
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 #             run the exported script and information about the source files.
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+# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
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@@ -9,7 +9,7 @@
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+# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
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@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
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-# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
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@@ -9,7 +9,7 @@
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+# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
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-# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
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@@ -9,7 +9,7 @@
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+# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
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@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
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-# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
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@@ -9,7 +9,7 @@
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+# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
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@@ -4,7 +4,7 @@
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 #             run the exported script and information about the source files.
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-# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
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@@ -9,7 +9,7 @@
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+# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
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@@ -4,7 +4,7 @@
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 #             run the exported script and information about the source files.
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-# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
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@@ -9,7 +9,7 @@
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-# Generated by Vivado on Mon Apr 03 20:42:37 CST 2023
+# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
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@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
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@@ -9,7 +9,7 @@
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 #
-# Generated by Vivado on Mon Apr 03 20:42:37 CST 2023
+# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -0,0 +1,2 @@
 NumberHits:1
 Timestamp: Tue Apr 04 10:48:26 UTC 2023
@@ -1,23 +1,23 @@
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@@ -1,14 +1,14 @@
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@@ -1,3 +1,3 @@
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@@ -3,7 +3,7 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Mon Apr  3 21:10:09 2023">
+<application name="pa" timeStamp="Wed Apr  5 12:53:16 2023">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="dd2c041edc1245f6938f6800e430db6c" type="ProjectID"/>
 <property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -18,38 +18,38 @@ This means code written to parse this file will need to be revisited each subseq
 </item>
 <item name="Java Command Handlers">
 <property name="AddExistingIPHandler" value="3" type="JavaHandler"/>
-<property name="CloseProject" value="3" type="JavaHandler"/>
+<property name="CloseProject" value="4" type="JavaHandler"/>
 <property name="CustomizeCore" value="2" type="JavaHandler"/>
 <property name="EditDelete" value="6" type="JavaHandler"/>
-<property name="ManageCompositeTargets" value="5" type="JavaHandler"/>
+<property name="ManageCompositeTargets" value="7" type="JavaHandler"/>
 <property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
-<property name="OpenIPLocationHandler" value="7" type="JavaHandler"/>
+<property name="OpenIPLocationHandler" value="9" type="JavaHandler"/>
-<property name="OpenPreviousIPHandler" value="10" type="JavaHandler"/>
+<property name="OpenPreviousIPHandler" value="11" type="JavaHandler"/>
 <property name="OpenProject" value="2" type="JavaHandler"/>
-<property name="RecustomizeCore" value="26" type="JavaHandler"/>
+<property name="RecustomizeCore" value="28" type="JavaHandler"/>
 <property name="ReportIPStatus" value="1" type="JavaHandler"/>
 <property name="ShowView" value="5" type="JavaHandler"/>
 </item>
 <item name="Gui Handlers">
-<property name="BaseDialog_CANCEL" value="13" type="GuiHandlerData"/>
+<property name="BaseDialog_CANCEL" value="15" type="GuiHandlerData"/>
-<property name="BaseDialog_OK" value="28" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="30" type="GuiHandlerData"/>
-<property name="CmdMsgDialog_OK" value="2" type="GuiHandlerData"/>
+<property name="CmdMsgDialog_OK" value="3" type="GuiHandlerData"/>
 <property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
 <property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
 <property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="7" type="GuiHandlerData"/>
 <property name="ExpRunMenu_RESET_AND_GENERATE_OUTPUT_PRODUCTS" value="2" type="GuiHandlerData"/>
-<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="19" type="GuiHandlerData"/>
+<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="23" type="GuiHandlerData"/>
-<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="157" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="174" type="GuiHandlerData"/>
-<property name="GettingStartedView_MANAGE_IP" value="9" type="GuiHandlerData"/>
+<property name="GettingStartedView_MANAGE_IP" value="11" type="GuiHandlerData"/>
 <property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
 <property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
-<property name="HACGCCoeFileWidget_BROWSE" value="5" type="GuiHandlerData"/>
+<property name="HACGCCoeFileWidget_BROWSE" value="6" type="GuiHandlerData"/>
 <property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
 <property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
 <property name="MainMenuMgr_EXPORT" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_FILE" value="10" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="12" type="GuiHandlerData"/>
 <property name="MainMenuMgr_IP" value="7" type="GuiHandlerData"/>
-<property name="MainMenuMgr_PROJECT" value="3" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="4" type="GuiHandlerData"/>
 <property name="MainMenuMgr_REPORTS" value="2" type="GuiHandlerData"/>
 <property name="MainMenuMgr_TEXT_EDITOR" value="3" type="GuiHandlerData"/>
 <property name="MainMenuMgr_TOOLS" value="2" type="GuiHandlerData"/>
@@ -61,27 +61,27 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="MsgView_WARNING_MESSAGES" value="1" type="GuiHandlerData"/>
 <property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
 <property name="PACommandNames_ADD_EXISTING_IP" value="3" type="GuiHandlerData"/>
-<property name="PACommandNames_CLOSE_PROJECT" value="3" type="GuiHandlerData"/>
+<property name="PACommandNames_CLOSE_PROJECT" value="4" type="GuiHandlerData"/>
 <property name="PACommandNames_FILESET_WINDOW" value="1" type="GuiHandlerData"/>
-<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
+<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="4" type="GuiHandlerData"/>
-<property name="PACommandNames_OPEN_IP_LOCATION" value="7" type="GuiHandlerData"/>
+<property name="PACommandNames_OPEN_IP_LOCATION" value="9" type="GuiHandlerData"/>
 <property name="PACommandNames_PROPERTIES_WINDOW" value="3" type="GuiHandlerData"/>
 <property name="PACommandNames_REPORT_IP_STATUS" value="1" type="GuiHandlerData"/>
-<property name="PACommandNames_RESET_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_RESET_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
 <property name="ProgressDialog_BACKGROUND" value="5" type="GuiHandlerData"/>
 <property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
 <property name="RemoveSourcesDialog_ALSO_DELETE" value="9" type="GuiHandlerData"/>
 <property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="5" type="GuiHandlerData"/>
-<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="16" type="GuiHandlerData"/>
+<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="18" type="GuiHandlerData"/>
-<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="4" type="GuiHandlerData"/>
+<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="5" type="GuiHandlerData"/>
 <property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="5" type="GuiHandlerData"/>
-<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="10" type="GuiHandlerData"/>
+<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="11" type="GuiHandlerData"/>
 <property name="XPG_CoeFileWidgdet_BROWSE" value="2" type="GuiHandlerData"/>
 </item>
 <item name="Other">
-<property name="GuiMode" value="62" type="GuiMode"/>
+<property name="GuiMode" value="63" type="GuiMode"/>
 <property name="BatchMode" value="0" type="BatchMode"/>
-<property name="TclMode" value="43" type="TclMode"/>
+<property name="TclMode" value="45" type="TclMode"/>
 </item>
 </section>
 </application>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="ad9361_clk_gen_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153566">
  <File Type="RDS-DCP" Name="ad9361_clk_gen.dcp"/>
  <File Type="PA-TCL" Name="ad9361_clk_gen.tcl"/>
  <File Type="RDS-DCP" Name="ad9361_clk_gen.dcp"/>
  <File Type="REPORTS-TCL" Name="ad9361_clk_gen_reports.tcl"/>
  <File Type="RDS-RDS" Name="ad9361_clk_gen.vds"/>
  <File Type="RDS-UTIL" Name="ad9361_clk_gen_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="add_s24_s32_s32_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
  <File Type="RDS-DCP" Name="add_s24_s32_s32.dcp"/>
  <File Type="PA-TCL" Name="add_s24_s32_s32.tcl"/>
  <File Type="RDS-DCP" Name="add_s24_s32_s32.dcp"/>
  <File Type="REPORTS-TCL" Name="add_s24_s32_s32_reports.tcl"/>
  <File Type="RDS-RDS" Name="add_s24_s32_s32.vds"/>
  <File Type="RDS-UTIL" Name="add_s24_s32_s32_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="ant_clk_gen_stg1_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
  <File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
  <File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
  <File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
  <File Type="REPORTS-TCL" Name="ant_clk_gen_stg1_reports.tcl"/>
  <File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
  <File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="ant_clk_gen_stg2_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
  <File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
  <File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
  <File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
  <File Type="REPORTS-TCL" Name="ant_clk_gen_stg2_reports.tcl"/>
  <File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
  <File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="atan2_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
  <File Type="RDS-DCP" Name="atan2_16b.dcp"/>
  <File Type="PA-TCL" Name="atan2_16b.tcl"/>
  <File Type="RDS-DCP" Name="atan2_16b.dcp"/>
  <File Type="REPORTS-TCL" Name="atan2_16b_reports.tcl"/>
  <File Type="RDS-RDS" Name="atan2_16b.vds"/>
  <File Type="RDS-UTIL" Name="atan2_16b_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="cmpy_12x12_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
  <File Type="RDS-DCP" Name="cmpy_12x12.dcp"/>
  <File Type="PA-TCL" Name="cmpy_12x12.tcl"/>
  <File Type="RDS-DCP" Name="cmpy_12x12.dcp"/>
  <File Type="REPORTS-TCL" Name="cmpy_12x12_reports.tcl"/>
  <File Type="RDS-RDS" Name="cmpy_12x12.vds"/>
  <File Type="RDS-UTIL" Name="cmpy_12x12_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="cmpy_16x12_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
  <File Type="RDS-DCP" Name="cmpy_16x12.dcp"/>
  <File Type="PA-TCL" Name="cmpy_16x12.tcl"/>
  <File Type="RDS-DCP" Name="cmpy_16x12.dcp"/>
  <File Type="REPORTS-TCL" Name="cmpy_16x12_reports.tcl"/>
  <File Type="RDS-RDS" Name="cmpy_16x12.vds"/>
  <File Type="RDS-UTIL" Name="cmpy_16x12_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="fifo_accor_cdc_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
  <File Type="RDS-DCP" Name="fifo_accor_cdc.dcp"/>
  <File Type="PA-TCL" Name="fifo_accor_cdc.tcl"/>
  <File Type="RDS-DCP" Name="fifo_accor_cdc.dcp"/>
  <File Type="REPORTS-TCL" Name="fifo_accor_cdc_reports.tcl"/>
  <File Type="RDS-RDS" Name="fifo_accor_cdc.vds"/>
  <File Type="RDS-UTIL" Name="fifo_accor_cdc_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="fifo_weight_cdc_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153568">
  <File Type="RDS-DCP" Name="fifo_weight_cdc.dcp"/>
  <File Type="PA-TCL" Name="fifo_weight_cdc.tcl"/>
  <File Type="RDS-DCP" Name="fifo_weight_cdc.dcp"/>
  <File Type="REPORTS-TCL" Name="fifo_weight_cdc_reports.tcl"/>
  <File Type="RDS-RDS" Name="fifo_weight_cdc.vds"/>
  <File Type="RDS-UTIL" Name="fifo_weight_cdc_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="ila_AntCtrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679400492">
  <File Type="RDS-DCP" Name="ila_AntCtrl.dcp"/>
  <File Type="PA-TCL" Name="ila_AntCtrl.tcl"/>
  <File Type="RDS-DCP" Name="ila_AntCtrl.dcp"/>
  <File Type="REPORTS-TCL" Name="ila_AntCtrl_reports.tcl"/>
  <File Type="RDS-RDS" Name="ila_AntCtrl.vds"/>
  <File Type="RDS-UTIL" Name="ila_AntCtrl_utilization_synth.rpt"/>
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="ila_cal_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1680090743">
  <File Type="REPORTS-TCL" Name="ila_cal_reports.tcl"/>
  <File Type="PA-TCL" Name="ila_cal.tcl"/>
  <File Type="RDS-DCP" Name="ila_cal.dcp"/>
  <File Type="REPORTS-TCL" Name="ila_cal_reports.tcl"/>
  <File Type="RDS-RDS" Name="ila_cal.vds"/>
  <File Type="RDS-UTIL-PB" Name="ila_cal_utilization_synth.pb"/>
  <File Type="RDS-UTIL" Name="ila_cal_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="ila_rfcontrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679400492">
  <File Type="RDS-DCP" Name="ila_rfcontrl.dcp"/>
  <File Type="PA-TCL" Name="ila_rfcontrl.tcl"/>
  <File Type="RDS-DCP" Name="ila_rfcontrl.dcp"/>
  <File Type="REPORTS-TCL" Name="ila_rfcontrl_reports.tcl"/>
  <File Type="RDS-RDS" Name="ila_rfcontrl.vds"/>
  <File Type="RDS-UTIL" Name="ila_rfcontrl_utilization_synth.rpt"/>
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="ila_rx_pre_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1680090770">
  <File Type="REPORTS-TCL" Name="ila_rx_pre_reports.tcl"/>
  <File Type="PA-TCL" Name="ila_rx_pre.tcl"/>
  <File Type="RDS-DCP" Name="ila_rx_pre.dcp"/>
  <File Type="REPORTS-TCL" Name="ila_rx_pre_reports.tcl"/>
  <File Type="RDS-RDS" Name="ila_rx_pre.vds"/>
  <File Type="RDS-UTIL-PB" Name="ila_rx_pre_utilization_synth.pb"/>
  <File Type="RDS-UTIL" Name="ila_rx_pre_utilization_synth.rpt"/>
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="ila_rx_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1680090829">
  <File Type="REPORTS-TCL" Name="ila_rx_reports.tcl"/>
  <File Type="PA-TCL" Name="ila_rx.tcl"/>
  <File Type="RDS-DCP" Name="ila_rx.dcp"/>
  <File Type="REPORTS-TCL" Name="ila_rx_reports.tcl"/>
  <File Type="RDS-RDS" Name="ila_rx.vds"/>
  <File Type="RDS-UTIL-PB" Name="ila_rx_utilization_synth.pb"/>
  <File Type="RDS-UTIL" Name="ila_rx_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="ila_tx_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679400355">
  <File Type="RDS-DCP" Name="ila_tx.dcp"/>
  <File Type="PA-TCL" Name="ila_tx.tcl"/>
  <File Type="RDS-DCP" Name="ila_tx.dcp"/>
  <File Type="REPORTS-TCL" Name="ila_tx_reports.tcl"/>
  <File Type="RDS-RDS" Name="ila_tx.vds"/>
  <File Type="RDS-UTIL" Name="ila_tx_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="ram_hop_data_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153570">
  <File Type="RDS-DCP" Name="ram_hop_data.dcp"/>
  <File Type="PA-TCL" Name="ram_hop_data.tcl"/>
  <File Type="RDS-DCP" Name="ram_hop_data.dcp"/>
  <File Type="REPORTS-TCL" Name="ram_hop_data_reports.tcl"/>
  <File Type="RDS-RDS" Name="ram_hop_data.vds"/>
  <File Type="RDS-UTIL" Name="ram_hop_data_utilization_synth.rpt"/>
@@ -1,5 +0,0 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
    <Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="679484" HostCore="20" HostMemory="65589000">
    </Process>
 </ProcessHandle>
@@ -1,270 +0,0 @@
 //
 //  Vivado(TM)
 //  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
 //  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
 //
 // GLOBAL VARIABLES
 var ISEShell = new ActiveXObject( "WScript.Shell" );
 var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
 var ISERunDir = "";
 var ISELogFile = "runme.log";
 var ISELogFileStr = null;
 var ISELogEcho = true;
 var ISEOldVersionWSH = false;
 // BOOTSTRAP
 ISEInit();
 //
 // ISE FUNCTIONS
 //
 function ISEInit() {
  // 1. RUN DIR setup
  var ISEScrFP = WScript.ScriptFullName;
  var ISEScrN = WScript.ScriptName;
  ISERunDir = 
    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
  // 2. LOG file setup
  ISELogFileStr = ISEOpenFile( ISELogFile );
  // 3. LOG echo?
  var ISEScriptArgs = WScript.Arguments;
  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
    if ( ISEScriptArgs(loopi) == "-quiet" ) {
      ISELogEcho = false;
      break;
    }
  }
  // 4. WSH version check
  var ISEOptimalVersionWSH = 5.6;
  var ISECurrentVersionWSH = WScript.Version;
  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
    ISEStdErr( "" );
    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
 	       ISEOptimalVersionWSH + " or higher. Downloads" );
    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
    ISEStdErr( "" );
    ISEOldVersionWSH = true;
  }
 }
 function ISEStep( ISEProg, ISEArgs ) {
  // CHECK for a STOP FILE
  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
    ISEStdErr( "" );
    ISEStdErr( "*** Halting run - EA reset detected ***" );
    ISEStdErr( "" );
    WScript.Quit( 1 );
  }
  // WRITE STEP HEADER to LOG
  ISEStdOut( "" );
  ISEStdOut( "*** Running " + ISEProg );
  ISEStdOut( "    with args " + ISEArgs );
  ISEStdOut( "" );
  // LAUNCH!
  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
  if ( ISEExitCode != 0 ) {
    WScript.Quit( ISEExitCode );
  }
 }
 function ISEExec( ISEProg, ISEArgs ) {
  var ISEStep = ISEProg;
  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
    ISEProg += ".bat";
  }
  var ISECmdLine = ISEProg + " " + ISEArgs;
  var ISEExitCode = 1;
  if ( ISEOldVersionWSH ) { // WSH 5.1
    // BEGIN file creation
    ISETouchFile( ISEStep, "begin" );
    // LAUNCH!
    ISELogFileStr.Close();
    ISECmdLine = 
      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
    ISELogFileStr = ISEOpenFile( ISELogFile );
  } else {  // WSH 5.6
    // LAUNCH!
    ISEShell.CurrentDirectory = ISERunDir;
    // Redirect STDERR to STDOUT
    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
    var ISEProcess = ISEShell.Exec( ISECmdLine );
    // BEGIN file creation
    var wbemFlagReturnImmediately = 0x10;
    var wbemFlagForwardOnly = 0x20;
    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
    var NOC = 0;
    var NOLP = 0;
    var TPM = 0;
    var cpuInfos = new Enumerator(processor);
    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
        var cpuInfo = cpuInfos.item();
        NOC += cpuInfo.NumberOfCores;
        NOLP += cpuInfo.NumberOfLogicalProcessors;
    }
    var csInfos = new Enumerator(computerSystem);
    for(;!csInfos.atEnd(); csInfos.moveNext()) {
        var csInfo = csInfos.item();
        TPM += csInfo.TotalPhysicalMemory;
    }
    var ISEHOSTCORE = NOLP
    var ISEMEMTOTAL = TPM
    var ISENetwork = WScript.CreateObject( "WScript.Network" );
    var ISEHost = ISENetwork.ComputerName;
    var ISEUser = ISENetwork.UserName;
    var ISEPid = ISEProcess.ProcessID;
    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
 			    "\" Owner=\"" + ISEUser + 
 			    "\" Host=\"" + ISEHost + 
 			    "\" Pid=\"" + ISEPid +
 			    "\" HostCore=\"" + ISEHOSTCORE +
 			    "\" HostMemory=\"" + ISEMEMTOTAL +
 			    "\">" );
    ISEBeginFile.WriteLine( "    </Process>" );
    ISEBeginFile.WriteLine( "</ProcessHandle>" );
    ISEBeginFile.Close();
    var ISEOutStr = ISEProcess.StdOut;
    var ISEErrStr = ISEProcess.StdErr;
    // WAIT for ISEStep to finish
    while ( ISEProcess.Status == 0 ) {
      // dump stdout then stderr - feels a little arbitrary
      while ( !ISEOutStr.AtEndOfStream ) {
        ISEStdOut( ISEOutStr.ReadLine() );
      }  
      WScript.Sleep( 100 );
    }
    ISEExitCode = ISEProcess.ExitCode;
  }
  ISELogFileStr.Close();
  // END/ERROR file creation
  if ( ISEExitCode != 0 ) {    
    ISETouchFile( ISEStep, "error" );
  } else {
    ISETouchFile( ISEStep, "end" );
  }
  return ISEExitCode;
 }
 //
 // UTILITIES
 //
 function ISEStdOut( ISELine ) {
  ISELogFileStr.WriteLine( ISELine );
  if ( ISELogEcho ) {
    WScript.StdOut.WriteLine( ISELine );
  }
 }
 function ISEStdErr( ISELine ) {
  ISELogFileStr.WriteLine( ISELine );
  if ( ISELogEcho ) {
    WScript.StdErr.WriteLine( ISELine );
  }
 }
 function ISETouchFile( ISERoot, ISEStatus ) {
  var ISETFile = 
    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
  ISETFile.Close();
 }
 function ISEOpenFile( ISEFilename ) {
  // This function has been updated to deal with a problem seen in CR #870871.
  // In that case the user runs a script that runs impl_1, and then turns around
  // and runs impl_1 -to_step write_bitstream. That second run takes place in
  // the same directory, which means we may hit some of the same files, and in
  // particular, we will open the runme.log file. Even though this script closes
  // the file (now), we see cases where a subsequent attempt to open the file
  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
  // play? In any case, we try to work around this by first waiting if the file
  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
  // and try to open the file 10 times with a one second delay after each attempt.
  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
  // If there is an unrecognized exception when trying to open the file, we output
  // an error message and write details to an exception.log file.
  var ISEFullPath = ISERunDir + "/" + ISEFilename;
  if (ISEFileSys.FileExists(ISEFullPath)) {
    // File is already there. This could be a problem. Wait in case it is still in use.
    WScript.Sleep(5000);
  }
  var i;
  for (i = 0; i < 10; ++i) {
    try {
      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
    } catch (exception) {
      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
      if (error_code == 52) { // 52 is bad file name or number.
        // Wait a second and try again.
        WScript.Sleep(1000);
        continue;
      } else {
        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
        var exceptionFilePath = ISERunDir + "/exception.log";
        if (!ISEFileSys.FileExists(exceptionFilePath)) {
          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
          exceptionFile.WriteLine("\tException name: " + exception.name);
          exceptionFile.WriteLine("\tException error code: " + error_code);
          exceptionFile.WriteLine("\tException message: " + exception.message);
          exceptionFile.Close();
        }
        throw exception;
      }
    }
  }
  // If we reached this point, we failed to open the file after 10 attempts.
  // We need to error out.
  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
  WScript.Quit(1);
 }
@@ -1,67 +0,0 @@
 #!/bin/sh
 #
 #  Vivado(TM)
 #  ISEWrap.sh: Vivado Runs Script for UNIX
 #  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
 #
 HD_LOG=$1
 shift
 # CHECK for a STOP FILE
 if [ -f .stop.rst ]
 then
 echo ""                                        >> $HD_LOG
 echo "*** Halting run - EA reset detected ***" >> $HD_LOG
 echo ""                                        >> $HD_LOG
 exit 1
 fi
 ISE_STEP=$1
 shift
 # WRITE STEP HEADER to LOG
 echo ""                      >> $HD_LOG
 echo "*** Running $ISE_STEP" >> $HD_LOG
 echo "    with args $@"      >> $HD_LOG
 echo ""                      >> $HD_LOG
 # LAUNCH!
 $ISE_STEP "$@" >> $HD_LOG 2>&1 &
 # BEGIN file creation
 ISE_PID=$!
 if [ X != X$HOSTNAME ]
 then
 ISE_HOST=$HOSTNAME #bash
 else
 ISE_HOST=$HOST     #csh
 fi
 ISE_USER=$USER
 ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
 ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
 ISE_BEGINFILE=.$ISE_STEP.begin.rst
 /bin/touch $ISE_BEGINFILE
 echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
 echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
 echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
 echo "    </Process>"                                                                              >> $ISE_BEGINFILE
 echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
 # WAIT for ISEStep to finish
 wait $ISE_PID
 # END/ERROR file creation
 RETVAL=$?
 if [ $RETVAL -eq 0 ]
 then
    /bin/touch .$ISE_STEP.end.rst
 else
    /bin/touch .$ISE_STEP.error.rst
 fi
 exit $RETVAL
@@ -1,16 +0,0 @@
 # This file is automatically generated.
 # It contains project source information necessary for synthesis and implementation.
 # IP: /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci
 # IP: The module: 'rom_hop_data' is the root of the design. Do not add the DONT_TOUCH constraint.
 # XDC: /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data_ooc.xdc
 # XDC: The top module name and the constraint reference have the same name: 'rom_hop_data'. Do not add the DONT_TOUCH constraint.
 set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
 # IP: /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci
 # IP: The module: 'rom_hop_data' is the root of the design. Do not add the DONT_TOUCH constraint.
 # XDC: /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data_ooc.xdc
 # XDC: The top module name and the constraint reference have the same name: 'rom_hop_data'. Do not add the DONT_TOUCH constraint.
 #dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
@@ -1,64 +0,0 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="rom_hop_data_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1680525756">
  <File Type="VDS-TIMING-PB" Name="rom_hop_data_timing_summary_synth.pb"/>
  <File Type="VDS-TIMINGSUMMARY" Name="rom_hop_data_timing_summary_synth.rpt"/>
  <File Type="RDS-DCP" Name="rom_hop_data.dcp"/>
  <File Type="REPORTS-TCL" Name="rom_hop_data_reports.tcl"/>
  <File Type="PA-TCL" Name="rom_hop_data.tcl"/>
  <File Type="RDS-RDS" Name="rom_hop_data.vds"/>
  <File Type="RDS-PROPCONSTRS" Name="rom_hop_data_drc_synth.rpt"/>
  <File Type="RDS-UTIL" Name="rom_hop_data_utilization_synth.rpt"/>
  <File Type="RDS-UTIL-PB" Name="rom_hop_data_utilization_synth.pb"/>
  <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rom_hop_data">
    <File Path="$PPRDIR/../rx_pre_process/rom_hop_data/rom_hop_data.xci">
      <FileInfo>
        <Attr Name="UsedIn" Val="synthesis"/>
        <Attr Name="UsedIn" Val="implementation"/>
        <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
    </File>
    <File Path="$PPRDIR/../rx_pre_process/rom_hop_data.xcix">
      <FileInfo>
        <Attr Name="UsedIn" Val="synthesis"/>
        <Attr Name="UsedIn" Val="implementation"/>
        <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
    </File>
    <Config>
      <Option Name="TopModule" Val="rom_hop_data"/>
      <Option Name="UseBlackboxStub" Val="1"/>
    </Config>
  </FileSet>
  <FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rom_hop_data">
    <File Path="$PPRDIR/../rx_pre_process/rom_hop_data/rom_hop_data.xci">
      <FileInfo>
        <Attr Name="UsedIn" Val="synthesis"/>
        <Attr Name="UsedIn" Val="implementation"/>
        <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
    </File>
    <File Path="$PPRDIR/../rx_pre_process/rom_hop_data.xcix">
      <FileInfo>
        <Attr Name="UsedIn" Val="synthesis"/>
        <Attr Name="UsedIn" Val="implementation"/>
        <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
    </File>
    <Config>
      <Option Name="TopModule" Val="rom_hop_data"/>
      <Option Name="UseBlackboxStub" Val="1"/>
    </Config>
  </FileSet>
  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
    <Filter Type="Utils"/>
    <Config>
      <Option Name="TopAutoSet" Val="TRUE"/>
    </Config>
  </FileSet>
  <Strategy Version="1" Minor="2">
    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
      <Desc>Vivado Synthesis Defaults</Desc>
    </StratHandle>
    <Step Id="synth_design"/>
  </Strategy>
 </GenRun>
@@ -1,9 +0,0 @@
 #
 # Vivado(TM)
 # htr.txt: a Vivado-generated description of how-to-repeat the
 #          the basic steps of a run.  Note that runme.bat/sh needs
 #          to be invoked for Vivado to track run status.
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 #
 vivado -log rom_hop_data.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_hop_data.tcl
@@ -1,57 +0,0 @@
 version:1
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3236:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3236:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c6164393336315f636c6b5f67656e:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c635f6164647375625f7631325f305f31335c6164645f7332345f7333325f733332:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c616e745f636c6b5f67656e5f73746731:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c616e745f636c6b5f67656e5f73746732:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c6174616e325f313662:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f3132783132:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f3136783132:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00
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 70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c726f746174655f313662:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f7264:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f74657374:636f72655f636f6e7461696e6572:74727565:00:00
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 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3734:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3734:00:00
 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3661346264366134396337643466636438383330333461376438356536303661:506172656e742050412070726f6a656374204944:00
 eof:996904006
@@ -1,156 +0,0 @@
 # 
 # Synthesis run script generated by Vivado
 # 
 set TIME_start [clock seconds] 
 proc create_report { reportName command } {
  set status "."
  append status $reportName ".fail"
  if { [file exists $status] } {
    eval file delete [glob $status]
  }
  send_msg_id runtcl-4 info "Executing : $command"
  set retval [eval catch { $command } msg]
  if { $retval != 0 } {
    set fp [open $status w]
    close $fp
    send_msg_id runtcl-5 warning "$msg"
  }
 }
 set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin
 set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin
 set_param project.vivado.isBlockSynthRun true
 set_msg_config -msgmgr_mode ooc_run
 create_project -in_memory -part xc7k410tffg900-2
 set_param project.singleFileAddWarning.threshold 0
 set_param project.compositeFile.enableAutoGeneration 0
 set_param synth.vivado.isSynthRun true
 set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
 set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
 set_property parent.project_path /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr [current_project]
 set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
 set_property default_lib xil_defaultlib [current_project]
 set_property target_language Verilog [current_project]
 set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
 set_property ip_cache_permissions {read write} [current_project]
 read_ip -quiet /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci
 set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data_ooc.xdc]
 # Mark all dcp files as not used in implementation to prevent them from being
 # stitched into the results of this synthesis run. Any black boxes in the
 # design are intentionally left as such for best results. Dcp files will be
 # stitched into the design at a later time, either when this synthesis run is
 # opened, or when it is stitched into a dependent implementation run.
 foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  set_property used_in_implementation false $dcp
 }
 read_xdc dont_touch.xdc
 set_property used_in_implementation false [get_files dont_touch.xdc]
 set_param ips.enableIPCacheLiteLoad 1
 set cached_ip [config_ip_cache -export -no_bom  -dir /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1 -new_name rom_hop_data -ip [get_ips rom_hop_data]]
 if { $cached_ip eq {} } {
 close [open __synthesis_is_running__ w]
 synth_design -top rom_hop_data -part xc7k410tffg900-2 -mode out_of_context
 #---------------------------------------------------------
 # Generate Checkpoint/Stub/Simulation Files For IP Cache
 #---------------------------------------------------------
 # disable binary constraint mode for IPCache checkpoints
 set_param constraints.enableBinaryConstraints false
 catch {
 write_checkpoint -force -noxdef -rename_prefix rom_hop_data_ rom_hop_data.dcp
 set ipCachedFiles {}
 write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_hop_data_stub.v
 lappend ipCachedFiles rom_hop_data_stub.v
 write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_hop_data_stub.vhdl
 lappend ipCachedFiles rom_hop_data_stub.vhdl
 write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_hop_data_sim_netlist.v
 lappend ipCachedFiles rom_hop_data_sim_netlist.v
 write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_hop_data_sim_netlist.vhdl
 lappend ipCachedFiles rom_hop_data_sim_netlist.vhdl
 set TIME_taken [expr [clock seconds] - $TIME_start]
 config_ip_cache -add -dcp rom_hop_data.dcp -move_files $ipCachedFiles -use_project_ipc  -synth_runtime $TIME_taken  -ip [get_ips rom_hop_data]
 }
 rename_ref -prefix_all rom_hop_data_
 # disable binary constraint mode for synth run checkpoints
 set_param constraints.enableBinaryConstraints false
 write_checkpoint -force -noxdef rom_hop_data.dcp
 create_report "rom_hop_data_synth_1_synth_report_utilization_0" "report_utilization -file rom_hop_data_utilization_synth.rpt -pb rom_hop_data_utilization_synth.pb"
 if { [catch {
  write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.v
 } _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
 }
 if { [catch {
  write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.vhdl
 } _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
 }
 if { [catch {
  write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_sim_netlist.v
 } _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
 }
 if { [catch {
  write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_sim_netlist.vhdl
 } _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
 }
 } else {
 }; # end if cached_ip 
 add_files /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci]
 add_files /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci]
 add_files /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci]
 add_files /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci]
 add_files /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci]
 if {[file isdir /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data]} {
  catch { 
    file copy -force /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_sim_netlist.v /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data
  }
 }
 if {[file isdir /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data]} {
  catch { 
    file copy -force /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data
  }
 }
 if {[file isdir /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data]} {
  catch { 
    file copy -force /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.v /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data
  }
 }
 if {[file isdir /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data]} {
  catch { 
    file copy -force /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.vhdl /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data
  }
 }
 file delete __synthesis_is_running__
 close [open __synthesis_is_complete__ w]
@@ -1,554 +0,0 @@
 #-----------------------------------------------------------
 # Vivado v2019.1.3 (64-bit)
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 # IP Build 2633630 on Wed Sep  4 12:30:14 MDT 2019
 # Start of session at: Mon Apr  3 20:42:37 2023
 # Process ID: 679523
 # Current directory: /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1
 # Command line: vivado -log rom_hop_data.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_hop_data.tcl
 # Log file: /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data.vds
 # Journal file: /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/vivado.jou
 #-----------------------------------------------------------
 source rom_hop_data.tcl -notrace
 Command: synth_design -top rom_hop_data -part xc7k410tffg900-2 -mode out_of_context
 Starting synth_design
 Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
 INFO: [Device 21-403] Loading part xc7k410tffg900-2
 INFO: Launching helper process for spawning children vivado processes
 INFO: Helper process launched with PID 679650 
 ---------------------------------------------------------------------------------
 Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1825.500 ; gain = 153.719 ; free physical = 17079 ; free virtual = 55559
 ---------------------------------------------------------------------------------
 INFO: [Synth 8-638] synthesizing module 'rom_hop_data' [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/synth/rom_hop_data.vhd:67]
 	Parameter C_FAMILY bound to: kintex7 - type: string 
 	Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string 
 	Parameter C_ELABORATION_DIR bound to: ./ - type: string 
 	Parameter C_INTERFACE_TYPE bound to: 0 - type: integer 
 	Parameter C_AXI_TYPE bound to: 1 - type: integer 
 	Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer 
 	Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer 
 	Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer 
 	Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string 
 	Parameter C_HAS_AXI_ID bound to: 0 - type: integer 
 	Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer 
 	Parameter C_MEM_TYPE bound to: 3 - type: integer 
 	Parameter C_BYTE_SIZE bound to: 9 - type: integer 
 	Parameter C_ALGORITHM bound to: 1 - type: integer 
 	Parameter C_PRIM_TYPE bound to: 1 - type: integer 
 	Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer 
 	Parameter C_INIT_FILE_NAME bound to: rom_hop_data.mif - type: string 
 	Parameter C_INIT_FILE bound to: rom_hop_data.mem - type: string 
 	Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer 
 	Parameter C_DEFAULT_DATA bound to: 0 - type: string 
 	Parameter C_HAS_RSTA bound to: 0 - type: integer 
 	Parameter C_RST_PRIORITY_A bound to: CE - type: string 
 	Parameter C_RSTRAM_A bound to: 0 - type: integer 
 	Parameter C_INITA_VAL bound to: 0 - type: string 
 	Parameter C_HAS_ENA bound to: 0 - type: integer 
 	Parameter C_HAS_REGCEA bound to: 0 - type: integer 
 	Parameter C_USE_BYTE_WEA bound to: 0 - type: integer 
 	Parameter C_WEA_WIDTH bound to: 1 - type: integer 
 	Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string 
 	Parameter C_WRITE_WIDTH_A bound to: 96 - type: integer 
 	Parameter C_READ_WIDTH_A bound to: 96 - type: integer 
 	Parameter C_WRITE_DEPTH_A bound to: 9600 - type: integer 
 	Parameter C_READ_DEPTH_A bound to: 9600 - type: integer 
 	Parameter C_ADDRA_WIDTH bound to: 14 - type: integer 
 	Parameter C_HAS_RSTB bound to: 0 - type: integer 
 	Parameter C_RST_PRIORITY_B bound to: CE - type: string 
 	Parameter C_RSTRAM_B bound to: 0 - type: integer 
 	Parameter C_INITB_VAL bound to: 0 - type: string 
 	Parameter C_HAS_ENB bound to: 0 - type: integer 
 	Parameter C_HAS_REGCEB bound to: 0 - type: integer 
 	Parameter C_USE_BYTE_WEB bound to: 0 - type: integer 
 	Parameter C_WEB_WIDTH bound to: 1 - type: integer 
 	Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string 
 	Parameter C_WRITE_WIDTH_B bound to: 96 - type: integer 
 	Parameter C_READ_WIDTH_B bound to: 96 - type: integer 
 	Parameter C_WRITE_DEPTH_B bound to: 9600 - type: integer 
 	Parameter C_READ_DEPTH_B bound to: 9600 - type: integer 
 	Parameter C_ADDRB_WIDTH bound to: 14 - type: integer 
 	Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 0 - type: integer 
 	Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer 
 	Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer 
 	Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer 
 	Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer 
 	Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer 
 	Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer 
 	Parameter C_USE_SOFTECC bound to: 0 - type: integer 
 	Parameter C_USE_ECC bound to: 0 - type: integer 
 	Parameter C_EN_ECC_PIPE bound to: 0 - type: integer 
 	Parameter C_READ_LATENCY_A bound to: 1 - type: integer 
 	Parameter C_READ_LATENCY_B bound to: 1 - type: integer 
 	Parameter C_HAS_INJECTERR bound to: 0 - type: integer 
 	Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string 
 	Parameter C_COMMON_CLK bound to: 0 - type: integer 
 	Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer 
 	Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer 
 	Parameter C_USE_URAM bound to: 0 - type: integer 
 	Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer 
 	Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer 
 	Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer 
 	Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer 
 	Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer 
 	Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer 
 	Parameter C_COUNT_36K_BRAM bound to: 26 - type: string 
 	Parameter C_COUNT_18K_BRAM bound to: 1 - type: string 
 	Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP     :     23.399606 mW - type: string 
 INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_3' declared at '/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_3' [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/synth/rom_hop_data.vhd:230]
 INFO: [Synth 8-256] done synthesizing module 'rom_hop_data' (11#1) [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/synth/rom_hop_data.vhd:67]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port MUX_RST[0]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port MEM_LAT_RST
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port MEM_REG_RST
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port MUX_REGCE[0]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port MEM_REGCE
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port WE
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[13]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[12]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[11]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[10]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[9]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[8]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[7]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[6]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[5]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[4]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[3]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[2]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[1]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[0]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[351]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[350]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[349]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[348]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[347]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[346]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[345]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[344]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[343]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[342]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[341]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[340]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[339]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[338]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[337]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[336]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[335]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[334]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[333]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[332]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[331]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[330]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[329]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[328]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[327]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[326]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[325]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[324]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[323]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[322]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[321]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[320]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[319]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[318]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[317]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[316]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[315]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[314]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[313]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[312]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[311]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[310]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[309]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[308]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[307]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[306]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[305]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[304]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[303]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[302]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[301]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[300]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[299]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[298]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[297]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[296]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[295]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[294]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[293]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[292]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[291]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[290]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[289]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[288]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[287]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[286]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[285]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[284]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[283]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[282]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[281]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[280]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[279]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[278]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[277]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[276]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[275]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[274]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[273]
 WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[272]
 INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
 ---------------------------------------------------------------------------------
 Finished RTL Elaboration : Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2127.750 ; gain = 455.969 ; free physical = 18323 ; free virtual = 56794
 ---------------------------------------------------------------------------------
 Report Check Netlist: 
 +------+------------------+-------+---------+-------+------------------+
 |      |Item              |Errors |Warnings |Status |Description       |
 +------+------------------+-------+---------+-------+------------------+
 |1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
 +------+------------------+-------+---------+-------+------------------+
 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Handling Custom Attributes : Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2130.719 ; gain = 458.938 ; free physical = 18328 ; free virtual = 56799
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2130.719 ; gain = 458.938 ; free physical = 18328 ; free virtual = 56799
 ---------------------------------------------------------------------------------
 INFO: [Netlist 29-17] Analyzing 27 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-570] Preparing netlist for logic optimization
 Processing XDC Constraints
 Initializing timing engine
 Parsing XDC File [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data_ooc.xdc] for cell 'U0'
 Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data_ooc.xdc] for cell 'U0'
 Parsing XDC File [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/dont_touch.xdc]
 Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/dont_touch.xdc]
 Completed Processing XDC Constraints
 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2264.500 ; gain = 0.000 ; free physical = 18228 ; free virtual = 56698
 INFO: [Project 1-111] Unisim Transformation Summary:
 No Unisim elements were transformed.
 Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2264.500 ; gain = 0.000 ; free physical = 18226 ; free virtual = 56697
 ---------------------------------------------------------------------------------
 Finished Constraint Validation : Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18327 ; free virtual = 56798
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Loading Part and Timing Information
 ---------------------------------------------------------------------------------
 Loading part: xc7k410tffg900-2
 ---------------------------------------------------------------------------------
 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18327 ; free virtual = 56798
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Applying 'set_property' XDC Constraints
 ---------------------------------------------------------------------------------
 Applied set_property DONT_TOUCH = true for U0. (constraint file  /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/dont_touch.xdc, line 9).
 ---------------------------------------------------------------------------------
 Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18327 ; free virtual = 56798
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18311 ; free virtual = 56791
 ---------------------------------------------------------------------------------
 Report RTL Partitions: 
 +-+--------------+------------+----------+
 | |RTL Partition |Replication |Instances |
 +-+--------------+------------+----------+
 +-+--------------+------------+----------+
 ---------------------------------------------------------------------------------
 Start RTL Component Statistics 
 ---------------------------------------------------------------------------------
 Detailed RTL Component Info : 
 +---Registers : 
 	                5 Bit    Registers := 2     
 +---Muxes : 
 	   2 Input      1 Bit        Muxes := 64    
 ---------------------------------------------------------------------------------
 Finished RTL Component Statistics 
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start RTL Hierarchical Component Statistics 
 ---------------------------------------------------------------------------------
 Hierarchical RTL Component report 
 Module bindec 
 Detailed RTL Component Info : 
 +---Muxes : 
 	   2 Input      1 Bit        Muxes := 32    
 Module blk_mem_gen_mux 
 Detailed RTL Component Info : 
 +---Registers : 
 	                5 Bit    Registers := 1     
 Module blk_mem_gen_mux__parameterized0 
 Detailed RTL Component Info : 
 +---Registers : 
 	                5 Bit    Registers := 1     
 ---------------------------------------------------------------------------------
 Finished RTL Hierarchical Component Statistics
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Part Resource Summary
 ---------------------------------------------------------------------------------
 Part Resources:
 DSPs: 1540 (col length:140)
 BRAMs: 1590 (col length: RAMB18 140 RAMB36 70)
 ---------------------------------------------------------------------------------
 Finished Part Resource Summary
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Cross Boundary and Area Optimization
 ---------------------------------------------------------------------------------
 Warning: Parallel synthesis criteria is not met 
 ---------------------------------------------------------------------------------
 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18295 ; free virtual = 56780
 ---------------------------------------------------------------------------------
 Report RTL Partitions: 
 +-+--------------+------------+----------+
 | |RTL Partition |Replication |Instances |
 +-+--------------+------------+----------+
 +-+--------------+------------+----------+
 ---------------------------------------------------------------------------------
 Start Applying XDC Timing Constraints
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:46 ; elapsed = 00:00:51 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18141 ; free virtual = 56621
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Timing Optimization
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Timing Optimization : Time (s): cpu = 00:00:46 ; elapsed = 00:00:51 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18139 ; free virtual = 56619
 ---------------------------------------------------------------------------------
 Report RTL Partitions: 
 +-+--------------+------------+----------+
 | |RTL Partition |Replication |Instances |
 +-+--------------+------------+----------+
 +-+--------------+------------+----------+
 ---------------------------------------------------------------------------------
 Start Technology Mapping
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Technology Mapping : Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18135 ; free virtual = 56615
 ---------------------------------------------------------------------------------
 Report RTL Partitions: 
 +-+--------------+------------+----------+
 | |RTL Partition |Replication |Instances |
 +-+--------------+------------+----------+
 +-+--------------+------------+----------+
 ---------------------------------------------------------------------------------
 Start IO Insertion
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Flattening Before IO Insertion
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Flattening Before IO Insertion
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Final Netlist Cleanup
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Final Netlist Cleanup
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished IO Insertion : Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18131 ; free virtual = 56611
 ---------------------------------------------------------------------------------
 Report Check Netlist: 
 +------+------------------+-------+---------+-------+------------------+
 |      |Item              |Errors |Warnings |Status |Description       |
 +------+------------------+-------+---------+-------+------------------+
 |1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
 +------+------------------+-------+---------+-------+------------------+
 ---------------------------------------------------------------------------------
 Start Renaming Generated Instances
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Renaming Generated Instances : Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18131 ; free virtual = 56611
 ---------------------------------------------------------------------------------
 Report RTL Partitions: 
 +-+--------------+------------+----------+
 | |RTL Partition |Replication |Instances |
 +-+--------------+------------+----------+
 +-+--------------+------------+----------+
 ---------------------------------------------------------------------------------
 Start Rebuilding User Hierarchy
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18124 ; free virtual = 56604
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Ports
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Renaming Generated Ports : Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18124 ; free virtual = 56604
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Handling Custom Attributes : Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18124 ; free virtual = 56604
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Nets
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Renaming Generated Nets : Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18124 ; free virtual = 56604
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Writing Synthesis Report
 ---------------------------------------------------------------------------------
 Report BlackBoxes: 
 +-+--------------+----------+
 | |BlackBox name |Instances |
 +-+--------------+----------+
 +-+--------------+----------+
 Report Cell Usage: 
 +------+------------+------+
 |      |Cell        |Count |
 +------+------------+------+
 |1     |LUT2        |     2|
 |2     |LUT3        |    70|
 |3     |LUT4        |     1|
 |4     |LUT5        |     1|
 |5     |LUT6        |    96|
 |6     |MUXF7       |    69|
 |7     |RAMB18E1    |     1|
 |8     |RAMB36E1    |     1|
 |9     |RAMB36E1_1  |     1|
 |10    |RAMB36E1_10 |     1|
 |11    |RAMB36E1_11 |     1|
 |12    |RAMB36E1_12 |     1|
 |13    |RAMB36E1_13 |     1|
 |14    |RAMB36E1_14 |     1|
 |15    |RAMB36E1_15 |     1|
 |16    |RAMB36E1_16 |     1|
 |17    |RAMB36E1_17 |     1|
 |18    |RAMB36E1_18 |     1|
 |19    |RAMB36E1_19 |     1|
 |20    |RAMB36E1_2  |     1|
 |21    |RAMB36E1_20 |     1|
 |22    |RAMB36E1_21 |     1|
 |23    |RAMB36E1_22 |     1|
 |24    |RAMB36E1_23 |     1|
 |25    |RAMB36E1_24 |     1|
 |26    |RAMB36E1_25 |     1|
 |27    |RAMB36E1_3  |     1|
 |28    |RAMB36E1_4  |     1|
 |29    |RAMB36E1_5  |     1|
 |30    |RAMB36E1_6  |     1|
 |31    |RAMB36E1_7  |     1|
 |32    |RAMB36E1_8  |     1|
 |33    |RAMB36E1_9  |     1|
 |34    |FDRE        |     5|
 +------+------------+------+
 Report Instance Areas: 
 +------+---------------------------------------------+-----------------------------------------------+------+
 |      |Instance                                     |Module                                         |Cells |
 +------+---------------------------------------------+-----------------------------------------------+------+
 |1     |top                                          |                                               |   271|
 |2     |  U0                                         |blk_mem_gen_v8_4_3                             |   271|
 |3     |    inst_blk_mem_gen                         |blk_mem_gen_v8_4_3_synth                       |   271|
 |4     |      \gnbram.gnativebmg.native_blk_mem_gen  |blk_mem_gen_top                                |   271|
 |5     |        \valid.cstr                          |blk_mem_gen_generic_cstr                       |   271|
 |6     |          \bindec_a.bindec_inst_a            |bindec                                         |     1|
 |7     |          \has_mux_a.A                       |blk_mem_gen_mux                                |   239|
 |8     |          \ramloop[0].ram.r                  |blk_mem_gen_prim_width                         |     1|
 |9     |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init                  |     1|
 |10    |          \ramloop[10].ram.r                 |blk_mem_gen_prim_width__parameterized9         |     2|
 |11    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized9  |     2|
 |12    |          \ramloop[11].ram.r                 |blk_mem_gen_prim_width__parameterized10        |     1|
 |13    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized10 |     1|
 |14    |          \ramloop[12].ram.r                 |blk_mem_gen_prim_width__parameterized11        |     1|
 |15    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized11 |     1|
 |16    |          \ramloop[13].ram.r                 |blk_mem_gen_prim_width__parameterized12        |     1|
 |17    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized12 |     1|
 |18    |          \ramloop[14].ram.r                 |blk_mem_gen_prim_width__parameterized13        |     1|
 |19    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized13 |     1|
 |20    |          \ramloop[15].ram.r                 |blk_mem_gen_prim_width__parameterized14        |     1|
 |21    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized14 |     1|
 |22    |          \ramloop[16].ram.r                 |blk_mem_gen_prim_width__parameterized15        |     1|
 |23    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized15 |     1|
 |24    |          \ramloop[17].ram.r                 |blk_mem_gen_prim_width__parameterized16        |     1|
 |25    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized16 |     1|
 |26    |          \ramloop[18].ram.r                 |blk_mem_gen_prim_width__parameterized17        |     1|
 |27    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized17 |     1|
 |28    |          \ramloop[19].ram.r                 |blk_mem_gen_prim_width__parameterized18        |     1|
 |29    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized18 |     1|
 |30    |          \ramloop[1].ram.r                  |blk_mem_gen_prim_width__parameterized0         |     1|
 |31    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized0  |     1|
 |32    |          \ramloop[20].ram.r                 |blk_mem_gen_prim_width__parameterized19        |     1|
 |33    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized19 |     1|
 |34    |          \ramloop[21].ram.r                 |blk_mem_gen_prim_width__parameterized20        |     1|
 |35    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized20 |     1|
 |36    |          \ramloop[22].ram.r                 |blk_mem_gen_prim_width__parameterized21        |     1|
 |37    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized21 |     1|
 |38    |          \ramloop[23].ram.r                 |blk_mem_gen_prim_width__parameterized22        |     1|
 |39    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized22 |     1|
 |40    |          \ramloop[24].ram.r                 |blk_mem_gen_prim_width__parameterized23        |     1|
 |41    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized23 |     1|
 |42    |          \ramloop[25].ram.r                 |blk_mem_gen_prim_width__parameterized24        |     1|
 |43    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized24 |     1|
 |44    |          \ramloop[26].ram.r                 |blk_mem_gen_prim_width__parameterized25        |     1|
 |45    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized25 |     1|
 |46    |          \ramloop[2].ram.r                  |blk_mem_gen_prim_width__parameterized1         |     1|
 |47    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized1  |     1|
 |48    |          \ramloop[3].ram.r                  |blk_mem_gen_prim_width__parameterized2         |     1|
 |49    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized2  |     1|
 |50    |          \ramloop[4].ram.r                  |blk_mem_gen_prim_width__parameterized3         |     1|
 |51    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized3  |     1|
 |52    |          \ramloop[5].ram.r                  |blk_mem_gen_prim_width__parameterized4         |     1|
 |53    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized4  |     1|
 |54    |          \ramloop[6].ram.r                  |blk_mem_gen_prim_width__parameterized5         |     1|
 |55    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized5  |     1|
 |56    |          \ramloop[7].ram.r                  |blk_mem_gen_prim_width__parameterized6         |     1|
 |57    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized6  |     1|
 |58    |          \ramloop[8].ram.r                  |blk_mem_gen_prim_width__parameterized7         |     1|
 |59    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized7  |     1|
 |60    |          \ramloop[9].ram.r                  |blk_mem_gen_prim_width__parameterized8         |     1|
 |61    |            \prim_init.ram                   |blk_mem_gen_prim_wrapper_init__parameterized8  |     1|
 +------+---------------------------------------------+-----------------------------------------------+------+
 ---------------------------------------------------------------------------------
 Finished Writing Synthesis Report : Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18124 ; free virtual = 56604
 ---------------------------------------------------------------------------------
 Synthesis finished with 0 errors, 0 critical warnings and 1874 warnings.
 Synthesis Optimization Runtime : Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2264.500 ; gain = 458.938 ; free physical = 18176 ; free virtual = 56656
 Synthesis Optimization Complete : Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2264.500 ; gain = 592.719 ; free physical = 18176 ; free virtual = 56656
 INFO: [Project 1-571] Translating synthesized netlist
 INFO: [Netlist 29-17] Analyzing 96 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-570] Preparing netlist for logic optimization
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2264.500 ; gain = 0.000 ; free physical = 18118 ; free virtual = 56599
 INFO: [Project 1-111] Unisim Transformation Summary:
 No Unisim elements were transformed.
 INFO: [Common 17-83] Releasing license: Synthesis
 17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
 synth_design completed successfully
 synth_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2264.500 ; gain = 869.520 ; free physical = 18238 ; free virtual = 56718
 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2264.500 ; gain = 0.000 ; free physical = 18238 ; free virtual = 56718
 WARNING: [Constraints 18-5210] No constraints selected for write.
 Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
 INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data.dcp' has been generated.
 WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
 INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rom_hop_data, cache-ID = 398372dcfcfb2e33
 INFO: [Coretcl 2-1174] Renamed 60 cell refs.
 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2264.500 ; gain = 0.000 ; free physical = 18239 ; free virtual = 56721
 WARNING: [Constraints 18-5210] No constraints selected for write.
 Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
 INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data.dcp' has been generated.
 INFO: [runtcl-4] Executing : report_utilization -file rom_hop_data_utilization_synth.rpt -pb rom_hop_data_utilization_synth.pb
 INFO: [Common 17-206] Exiting Vivado at Mon Apr  3 20:43:37 2023...
@@ -1,22 +0,0 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
 // Date        : Mon Apr  3 20:43:37 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
 //               /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.v
 // Design      : rom_hop_data
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7k410tffg900-2
 // --------------------------------------------------------------------------------
 // This empty module with port declaration file causes synthesis tools to infer a black box for IP.
 // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
 module rom_hop_data(clka, addra, douta)
 /* synthesis syn_black_box black_box_pad_pin="clka,addra[13:0],douta[95:0]" */;
  input clka;
  input [13:0]addra;
  output [95:0]douta;
 endmodule
@@ -1,32 +0,0 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
 -- Date        : Mon Apr  3 20:43:37 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
 --               /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.vhdl
 -- Design      : rom_hop_data
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7k410tffg900-2
 -- --------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 entity rom_hop_data is
  Port ( 
    clka : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 95 downto 0 )
  );
 end rom_hop_data;
 architecture stub of rom_hop_data is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
 attribute black_box_pad_pin of stub : architecture is "clka,addra[13:0],douta[95:0]";
 attribute x_core_info : string;
 attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
 begin
 end;
@@ -1,183 +0,0 @@
 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
 | Date         : Mon Apr  3 20:43:37 2023
 | Host         : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 | Command      : report_utilization -file rom_hop_data_utilization_synth.rpt -pb rom_hop_data_utilization_synth.pb
 | Design       : rom_hop_data
 | Device       : 7k410tffg900-2
 | Design State : Synthesized
 -------------------------------------------------------------------------------------------------------------------
 Utilization Design Information
 Table of Contents
 -----------------
 1. Slice Logic
 1.1 Summary of Registers by Type
 2. Memory
 3. DSP
 4. IO and GT Specific
 5. Clocking
 6. Specific Feature
 7. Primitives
 8. Black Boxes
 9. Instantiated Netlists
 1. Slice Logic
 --------------
 +-------------------------+------+-------+-----------+-------+
 |        Site Type        | Used | Fixed | Available | Util% |
 +-------------------------+------+-------+-----------+-------+
 | Slice LUTs*             |  170 |     0 |    254200 |  0.07 |
 |   LUT as Logic          |  170 |     0 |    254200 |  0.07 |
 |   LUT as Memory         |    0 |     0 |     90600 |  0.00 |
 | Slice Registers         |    5 |     0 |    508400 | <0.01 |
 |   Register as Flip Flop |    5 |     0 |    508400 | <0.01 |
 |   Register as Latch     |    0 |     0 |    508400 |  0.00 |
 | F7 Muxes                |   69 |     0 |    127100 |  0.05 |
 | F8 Muxes                |    0 |     0 |     63550 |  0.00 |
 +-------------------------+------+-------+-----------+-------+
 * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
 1.1 Summary of Registers by Type
 --------------------------------
 +-------+--------------+-------------+--------------+
 | Total | Clock Enable | Synchronous | Asynchronous |
 +-------+--------------+-------------+--------------+
 | 0     |            _ |           - |            - |
 | 0     |            _ |           - |          Set |
 | 0     |            _ |           - |        Reset |
 | 0     |            _ |         Set |            - |
 | 0     |            _ |       Reset |            - |
 | 0     |          Yes |           - |            - |
 | 0     |          Yes |           - |          Set |
 | 0     |          Yes |           - |        Reset |
 | 0     |          Yes |         Set |            - |
 | 5     |          Yes |       Reset |            - |
 +-------+--------------+-------------+--------------+
 2. Memory
 ---------
 +-------------------+------+-------+-----------+-------+
 |     Site Type     | Used | Fixed | Available | Util% |
 +-------------------+------+-------+-----------+-------+
 | Block RAM Tile    | 26.5 |     0 |       795 |  3.33 |
 |   RAMB36/FIFO*    |   26 |     0 |       795 |  3.27 |
 |     RAMB36E1 only |   26 |       |           |       |
 |   RAMB18          |    1 |     0 |      1590 |  0.06 |
 |     RAMB18E1 only |    1 |       |           |       |
 +-------------------+------+-------+-----------+-------+
 * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
 3. DSP
 ------
 +-----------+------+-------+-----------+-------+
 | Site Type | Used | Fixed | Available | Util% |
 +-----------+------+-------+-----------+-------+
 | DSPs      |    0 |     0 |      1540 |  0.00 |
 +-----------+------+-------+-----------+-------+
 4. IO and GT Specific
 ---------------------
 +-----------------------------+------+-------+-----------+-------+
 |          Site Type          | Used | Fixed | Available | Util% |
 +-----------------------------+------+-------+-----------+-------+
 | Bonded IOB                  |    0 |     0 |       500 |  0.00 |
 | Bonded IPADs                |    0 |     0 |        50 |  0.00 |
 | Bonded OPADs                |    0 |     0 |        32 |  0.00 |
 | PHY_CONTROL                 |    0 |     0 |        10 |  0.00 |
 | PHASER_REF                  |    0 |     0 |        10 |  0.00 |
 | OUT_FIFO                    |    0 |     0 |        40 |  0.00 |
 | IN_FIFO                     |    0 |     0 |        40 |  0.00 |
 | IDELAYCTRL                  |    0 |     0 |        10 |  0.00 |
 | IBUFDS                      |    0 |     0 |       480 |  0.00 |
 | GTXE2_COMMON                |    0 |     0 |         4 |  0.00 |
 | GTXE2_CHANNEL               |    0 |     0 |        16 |  0.00 |
 | PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        40 |  0.00 |
 | PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        40 |  0.00 |
 | IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       500 |  0.00 |
 | ODELAYE2/ODELAYE2_FINEDELAY |    0 |     0 |       150 |  0.00 |
 | IBUFDS_GTE2                 |    0 |     0 |         8 |  0.00 |
 | ILOGIC                      |    0 |     0 |       500 |  0.00 |
 | OLOGIC                      |    0 |     0 |       500 |  0.00 |
 +-----------------------------+------+-------+-----------+-------+
 5. Clocking
 -----------
 +------------+------+-------+-----------+-------+
 |  Site Type | Used | Fixed | Available | Util% |
 +------------+------+-------+-----------+-------+
 | BUFGCTRL   |    0 |     0 |        32 |  0.00 |
 | BUFIO      |    0 |     0 |        40 |  0.00 |
 | MMCME2_ADV |    0 |     0 |        10 |  0.00 |
 | PLLE2_ADV  |    0 |     0 |        10 |  0.00 |
 | BUFMRCE    |    0 |     0 |        20 |  0.00 |
 | BUFHCE     |    0 |     0 |       168 |  0.00 |
 | BUFR       |    0 |     0 |        40 |  0.00 |
 +------------+------+-------+-----------+-------+
 6. Specific Feature
 -------------------
 +-------------+------+-------+-----------+-------+
 |  Site Type  | Used | Fixed | Available | Util% |
 +-------------+------+-------+-----------+-------+
 | BSCANE2     |    0 |     0 |         4 |  0.00 |
 | CAPTUREE2   |    0 |     0 |         1 |  0.00 |
 | DNA_PORT    |    0 |     0 |         1 |  0.00 |
 | EFUSE_USR   |    0 |     0 |         1 |  0.00 |
 | FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
 | ICAPE2      |    0 |     0 |         2 |  0.00 |
 | PCIE_2_1    |    0 |     0 |         1 |  0.00 |
 | STARTUPE2   |    0 |     0 |         1 |  0.00 |
 | XADC        |    0 |     0 |         1 |  0.00 |
 +-------------+------+-------+-----------+-------+
 7. Primitives
 -------------
 +----------+------+---------------------+
 | Ref Name | Used | Functional Category |
 +----------+------+---------------------+
 | LUT6     |   96 |                 LUT |
 | LUT3     |   70 |                 LUT |
 | MUXF7    |   69 |               MuxFx |
 | RAMB36E1 |   26 |        Block Memory |
 | FDRE     |    5 |        Flop & Latch |
 | LUT2     |    2 |                 LUT |
 | RAMB18E1 |    1 |        Block Memory |
 | LUT5     |    1 |                 LUT |
 | LUT4     |    1 |                 LUT |
 +----------+------+---------------------+
 8. Black Boxes
 --------------
 +----------+------+
 | Ref Name | Used |
 +----------+------+
 9. Instantiated Netlists
 ------------------------
 +----------+------+
 | Ref Name | Used |
 +----------+------+
@@ -1,40 +0,0 @@
 //
 // Vivado(TM)
 // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 //
 echo "This script was generated under a different operating system."
 echo "Please update the PATH variable below, before executing this script"
 exit
 var WshShell = new ActiveXObject( "WScript.Shell" );
 var ProcEnv = WshShell.Environment( "Process" );
 var PathVal = ProcEnv("PATH");
 if ( PathVal.length == 0 ) {
  PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;";
 } else {
  PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal;
 }
 ProcEnv("PATH") = PathVal;
 var RDScrFP = WScript.ScriptFullName;
 var RDScrN = WScript.ScriptName;
 var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
 var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
 eval( EAInclude(ISEJScriptLib) );
 ISEStep( "vivado",
         "-log rom_hop_data.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_hop_data.tcl" );
 function EAInclude( EAInclFilename ) {
  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
  var EAIFContents = EAInclFile.ReadAll();
  EAInclFile.Close();
  return EAIFContents;
 }
@@ -1,11 +0,0 @@
@echo off
 rem  Vivado (TM)
 rem  runme.bat: a Vivado-generated Script
 rem  Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 set HD_SDIR=%~dp0
 cd /d "%HD_SDIR%"
 set PATH=%SYSTEMROOT%\system32;%PATH%
 cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
@@ -1,39 +0,0 @@
 #!/bin/sh
 # 
 # Vivado(TM)
 # runme.sh: a Vivado-generated Runs Script for UNIX
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 # 
 if [ -z "$PATH" ]; then
  PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin
 else
  PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH
 fi
 export PATH
 if [ -z "$LD_LIBRARY_PATH" ]; then
  LD_LIBRARY_PATH=
 else
  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
 fi
 export LD_LIBRARY_PATH
 HD_PWD='/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1'
 cd "$HD_PWD"
 HD_LOG=runme.log
 /bin/touch $HD_LOG
 ISEStep="./ISEWrap.sh"
 EAStep()
 {
     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
     if [ $? -ne 0 ]
     then
         exit
     fi
 }
 EAStep vivado -log rom_hop_data.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_hop_data.tcl
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="rotate_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
  <File Type="RDS-DCP" Name="rotate_16b.dcp"/>
  <File Type="PA-TCL" Name="rotate_16b.tcl"/>
  <File Type="RDS-DCP" Name="rotate_16b.dcp"/>
  <File Type="REPORTS-TCL" Name="rotate_16b_reports.tcl"/>
  <File Type="RDS-RDS" Name="rotate_16b.vds"/>
  <File Type="RDS-UTIL" Name="rotate_16b_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="vio_ant_rd_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
  <File Type="RDS-DCP" Name="vio_ant_rd.dcp"/>
  <File Type="PA-TCL" Name="vio_ant_rd.tcl"/>
  <File Type="RDS-DCP" Name="vio_ant_rd.dcp"/>
  <File Type="REPORTS-TCL" Name="vio_ant_rd_reports.tcl"/>
  <File Type="RDS-RDS" Name="vio_ant_rd.vds"/>
  <File Type="RDS-UTIL" Name="vio_ant_rd_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="vio_ant_test_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
  <File Type="RDS-DCP" Name="vio_ant_test.dcp"/>
  <File Type="PA-TCL" Name="vio_ant_test.tcl"/>
  <File Type="RDS-DCP" Name="vio_ant_test.dcp"/>
  <File Type="REPORTS-TCL" Name="vio_ant_test_reports.tcl"/>
  <File Type="RDS-RDS" Name="vio_ant_test.vds"/>
  <File Type="RDS-UTIL" Name="vio_ant_test_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="vio_cal_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
  <File Type="RDS-DCP" Name="vio_cal.dcp"/>
  <File Type="PA-TCL" Name="vio_cal.tcl"/>
  <File Type="RDS-DCP" Name="vio_cal.dcp"/>
  <File Type="REPORTS-TCL" Name="vio_cal_reports.tcl"/>
  <File Type="RDS-RDS" Name="vio_cal.vds"/>
  <File Type="RDS-UTIL" Name="vio_cal_utilization_synth.rpt"/>
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="vio_clk_ld_rd_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
  <File Type="RDS-DCP" Name="vio_clk_ld_rd.dcp"/>
  <File Type="PA-TCL" Name="vio_clk_ld_rd.tcl"/>
  <File Type="RDS-DCP" Name="vio_clk_ld_rd.dcp"/>
  <File Type="REPORTS-TCL" Name="vio_clk_ld_rd_reports.tcl"/>
  <File Type="RDS-RDS" Name="vio_clk_ld_rd.vds"/>
  <File Type="RDS-UTIL" Name="vio_clk_ld_rd_utilization_synth.rpt"/>
--- a/Show More
+++ b/Show More
		`@@ -0,0 +1,2 @@`
							`NumberHits:1`
							`Timestamp: Tue Apr 04 10:48:26 UTC 2023`