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josh
2023-03-18 15:35:53 +08:00
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adi_library/axi_ad7616/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_ad7616
GENERIC_DEPS += ../common/ad_edge_detect.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += axi_ad7616.v
GENERIC_DEPS += axi_ad7616_control.v
GENERIC_DEPS += axi_ad7616_maxis2wrfifo.v
GENERIC_DEPS += axi_ad7616_pif.v
XILINX_DEPS += axi_ad7616_ip.tcl
XILINX_LIB_DEPS += spi_engine/axi_spi_engine
XILINX_LIB_DEPS += spi_engine/spi_engine_execution
XILINX_LIB_DEPS += spi_engine/spi_engine_interconnect
XILINX_LIB_DEPS += spi_engine/spi_engine_offload
include ../scripts/library.mk
adi_library/axi_ad7616/axi_ad7616.cache/wt/project.wpc
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version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:
adi_library/axi_ad7616/axi_ad7616.hw/axi_ad7616.lpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
adi_library/axi_ad7616/axi_ad7616.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616 #(
parameter ID = 0,
parameter IF_TYPE = 1) (
// physical data interface
output rx_sclk,
output rx_cs_n,
output rx_sdo,
input [ 1:0] rx_sdi,
output [15:0] rx_db_o,
input [15:0] rx_db_i,
output rx_db_t,
output rx_rd_n,
output rx_wr_n,
// physical control interface
output rx_cnvst,
input rx_busy,
// AXI Slave Memory Map
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
// Write FIFO interface
output adc_valid,
output [15:0] adc_data,
output adc_sync,
output irq);
localparam NUM_OF_SDI = 2;
localparam SERIAL = 0;
localparam PARALLEL = 1;
localparam NEG_EDGE = 1;
// internal registers
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
// internal signals
wire up_clk;
wire up_rstn;
wire up_rst;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_if_s;
wire up_rack_if_s;
wire [31:0] up_rdata_if_s;
wire up_wack_cntrl_s;
wire up_rack_cntrl_s;
wire [31:0] up_rdata_cntrl_s;
wire trigger_s;
wire rd_req_s;
wire wr_req_s;
wire [15:0] wr_data_s;
wire [15:0] rd_data_s;
wire rd_valid_s;
wire [ 4:0] burst_length_s;
wire m_axis_ready_s;
wire m_axis_valid_s;
wire [15:0] m_axis_data_s;
wire m_axis_xfer_req_s;
// defaults
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign up_rst = ~s_axi_aresetn;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_wack <= up_wack_if_s | up_wack_cntrl_s;
up_rack <= up_rack_if_s | up_rack_cntrl_s;
up_rdata <= up_rdata_if_s | up_rdata_cntrl_s;
end
end
generate if (IF_TYPE == SERIAL) begin
// ground all parallel interface signals
assign rx_db_o = 16'b0;
assign rx_rd_n = 1'b0;
assign rx_wr_n = 1'b0;
// SPI Framework instances and logic
wire spi_resetn_s;
wire s0_cmd_ready_s;
wire s0_cmd_valid_s;
wire [15:0] s0_cmd_data_s;
wire s0_sdo_data_ready_s;
wire s0_sdo_data_valid_s;
wire [ 7:0] s0_sdo_data_s;
wire s0_sdi_data_ready_s;
wire s0_sdi_data_valid_s;
wire [15:0] s0_sdi_data_s;
wire s0_sync_ready_s;
wire s0_sync_valid_s;
wire [ 7:0] s0_sync_s;
wire s1_cmd_ready_s;
wire s1_cmd_valid_s;
wire [15:0] s1_cmd_data_s;
wire s1_sdo_data_ready_s;
wire s1_sdo_data_valid_s;
wire [ 7:0] s1_sdo_data_s;
wire s1_sdi_data_ready_s;
wire s1_sdi_data_valid_s;
wire [15:0] s1_sdi_data_s;
wire s1_sync_ready_s;
wire s1_sync_valid_s;
wire [ 7:0] s1_sync_s;
wire m_cmd_ready_s;
wire m_cmd_valid_s;
wire [15:0] m_cmd_data_s;
wire m_sdo_data_ready_s;
wire m_sdo_data_valid_s;
wire [7:0] m_sdo_data_s;
wire m_sdi_data_ready_s;
wire m_sdi_data_valid_s;
wire [15:0] m_sdi_data_s;
wire m_sync_ready_s;
wire m_sync_valid_s;
wire [ 7:0] m_sync_s;
wire offload0_cmd_wr_en_s;
wire [15:0] offload0_cmd_wr_data_s;
wire offload0_sdo_wr_en_s;
wire [ 7:0] offload0_sdo_wr_data_s;
wire offload0_mem_reset_s;
wire offload0_enable_s;
wire offload0_enabled_s;
axi_spi_engine #(
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI),
.NUM_OFFLOAD(1),
.MM_IF_TYPE(1)
) i_axi_spi_engine (
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_if_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_if_s),
.up_rack (up_rack_if_s),
.irq (irq),
.spi_clk (up_clk),
.spi_resetn (spi_resetn_s),
.cmd_ready (s0_cmd_ready_s),
.cmd_valid (s0_cmd_valid_s),
.cmd_data (s0_cmd_data_s),
.sdo_data_ready (s0_sdo_data_ready_s),
.sdo_data_valid (s0_sdo_data_valid_s),
.sdo_data (s0_sdo_data_s),
.sdi_data_ready (s0_sdi_data_ready_s),
.sdi_data_valid (s0_sdi_data_valid_s),
.sdi_data (s0_sdi_data_s),
.sync_ready (s0_sync_ready_s),
.sync_valid (s0_sync_valid_s),
.sync_data (s0_sync_s),
.offload0_cmd_wr_en (offload0_cmd_wr_en_s),
.offload0_cmd_wr_data (offload0_cmd_wr_data_s),
.offload0_sdo_wr_en (offload0_sdo_wr_en_s),
.offload0_sdo_wr_data (offload0_sdo_wr_data_s),
.offload0_mem_reset (offload0_mem_reset_s),
.offload0_enable (offload0_enable_s),
.offload0_enabled(offload0_enabled_s));
spi_engine_offload #(
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_offload (
.ctrl_clk (up_clk),
.ctrl_cmd_wr_en (offload0_cmd_wr_en_s),
.ctrl_cmd_wr_data (offload0_cmd_wr_data_s),
.ctrl_sdo_wr_en (offload0_sdo_wr_en_s),
.ctrl_sdo_wr_data (offload0_sdo_wr_data_s),
.ctrl_enable (offload0_enable_s),
.ctrl_enabled (offload0_enabled_s),
.ctrl_mem_reset (offload0_mem_reset_s),
.spi_clk (up_clk),
.spi_resetn (spi_resetn_s),
.trigger (trigger_s),
.cmd_valid (s1_cmd_valid_s),
.cmd_ready (s1_cmd_ready_s),
.cmd (s1_cmd_data_s),
.sdo_data_valid (s1_sdo_data_valid_s),
.sdo_data_ready (s1_sdo_data_ready_s),
.sdo_data (s1_sdo_data_s),
.sdi_data_valid (s1_sdi_data_valid_s),
.sdi_data_ready (s1_sdi_data_ready_s),
.sdi_data (s1_sdi_data_s),
.sync_valid (s1_sync_valid_s),
.sync_ready (s1_sync_ready_s),
.sync_data (s1_sync_s),
.offload_sdi_valid (m_axis_valid_s),
.offload_sdi_ready (m_axis_ready_s),
.offload_sdi_data (m_axis_data_s));
spi_engine_interconnect #(
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_interconnect (
.clk (up_clk),
.resetn (spi_resetn_s),
.m_cmd_valid (m_cmd_valid_s),
.m_cmd_ready (m_cmd_ready_s),
.m_cmd_data (m_cmd_data_s),
.m_sdo_valid (m_sdo_data_valid_s),
.m_sdo_ready (m_sdo_data_ready_s),
.m_sdo_data (m_sdo_data_s),
.m_sdi_valid (m_sdi_data_valid_s),
.m_sdi_ready (m_sdi_data_ready_s),
.m_sdi_data (m_sdi_data_s),
.m_sync_valid (m_sync_valid_s),
.m_sync_ready (m_sync_ready_s),
.m_sync (m_sync_s),
.s0_cmd_valid (s0_cmd_valid_s),
.s0_cmd_ready (s0_cmd_ready_s),
.s0_cmd_data (s0_cmd_data_s),
.s0_sdo_valid (s0_sdo_data_valid_s),
.s0_sdo_ready (s0_sdo_data_ready_s),
.s0_sdo_data (s0_sdo_data_s),
.s0_sdi_valid (s0_sdi_data_valid_s),
.s0_sdi_ready (s0_sdi_data_ready_s),
.s0_sdi_data (s0_sdi_data_s),
.s0_sync_valid (s0_sync_valid_s),
.s0_sync_ready (s0_sync_ready_s),
.s0_sync (s0_sync_s),
.s1_cmd_valid (s1_cmd_valid_s),
.s1_cmd_ready (s1_cmd_ready_s),
.s1_cmd_data (s1_cmd_data_s),
.s1_sdo_valid (s1_sdo_data_valid_s),
.s1_sdo_ready (s1_sdo_data_ready_s),
.s1_sdo_data (s1_sdo_data_s),
.s1_sdi_valid (s1_sdi_data_valid_s),
.s1_sdi_ready (s1_sdi_data_ready_s),
.s1_sdi_data (s1_sdi_data_s),
.s1_sync_valid (s1_sync_valid_s),
.s1_sync_ready (s1_sync_ready_s),
.s1_sync (s1_sync_s));
spi_engine_execution #(
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_execution (
.clk (up_clk),
.resetn (spi_resetn_s),
.active (),
.cmd_ready (m_cmd_ready_s),
.cmd_valid (m_cmd_valid_s),
.cmd (m_cmd_data_s),
.sdo_data_valid (m_sdo_data_valid_s),
.sdo_data_ready (m_sdo_data_ready_s),
.sdo_data (m_sdo_data_s),
.sdi_data_ready (m_sdi_data_ready_s),
.sdi_data_valid (m_sdi_data_valid_s),
.sdi_data (m_sdi_data_s),
.sync_ready (m_sync_ready_s),
.sync_valid (m_sync_valid_s),
.sync (m_sync_s),
.sclk (rx_sclk),
.sdo (rx_sdo),
.sdo_t (),
.sdi (rx_sdi),
.cs (rx_cs_n),
.three_wire ());
axi_ad7616_maxis2wrfifo #(
.DATA_WIDTH(16)
) i_maxis2wrfifo (
.clk(up_clk),
.rstn(up_rstn),
.sync_in(trigger_s),
.m_axis_data(m_axis_data_s),
.m_axis_ready(m_axis_ready_s),
.m_axis_valid(m_axis_valid_s),
.fifo_wr_en(adc_valid),
.fifo_wr_data(adc_data),
.fifo_wr_sync(adc_sync),
.fifo_wr_xfer_req(1'b1)
);
end
endgenerate
generate if (IF_TYPE == PARALLEL) begin
assign rx_sclk = 1'h0;
assign rx_sdo = 1'h0;
assign irq = 1'h0;
assign up_wack_if_s = 1'h0;
assign up_rack_if_s = 1'h0;
assign up_rdata_if_s = 1'h0;
axi_ad7616_pif i_ad7616_parallel_interface (
.cs_n (rx_cs_n),
.db_o (rx_db_o),
.db_i (rx_db_i),
.db_t (rx_db_t),
.rd_n (rx_rd_n),
.wr_n (rx_wr_n),
.adc_data (adc_data),
.adc_valid (adc_valid),
.adc_sync (adc_sync),
.end_of_conv (trigger_s),
.burst_length(burst_length_s),
.clk (up_clk),
.rstn (up_rstn),
.rd_req (rd_req_s),
.wr_req (wr_req_s),
.wr_data (wr_data_s),
.rd_data (rd_data_s),
.rd_valid (rd_valid_s)
);
end
endgenerate
axi_ad7616_control #(
.ID(ID),
.IF_TYPE(IF_TYPE)
) i_ad7616_control (
.cnvst (rx_cnvst),
.busy (rx_busy),
.up_burst_length (burst_length_s),
.up_read_data (rd_data_s),
.up_read_valid (rd_valid_s),
.up_write_data (wr_data_s),
.up_read_req (rd_req_s),
.up_write_req (wr_req_s),
.end_of_conv (trigger_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_cntrl_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_cntrl_s),
.up_rack (up_rack_cntrl_s));
// up bus interface
up_axi #(
.AXI_ADDRESS_WIDTH (16)
) i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_ad7616/axi_ad7616.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616/axi_ad7616.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="93a79731539548dc9c23f3a4f29953b7"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../common/ad_edge_detect.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_ad7616_control.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_ad7616_maxis2wrfifo.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_ad7616_pif.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_axi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_ad7616.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_ad7616"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters>
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
</Parameters>
</BootPmcSettings>
</Project>
adi_library/axi_ad7616/axi_ad7616_control.v
+211
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@@ -0,0 +1,211 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616_control #(
parameter ID = 0,
parameter IF_TYPE = 0) (
// control signals
output cnvst,
input busy,
input [15:0] up_read_data,
input up_read_valid,
output reg [15:0] up_write_data,
output up_read_req,
output up_write_req,
output reg [ 4:0] up_burst_length,
output end_of_conv,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack
);
localparam PCORE_VERSION = 'h00001002;
localparam POS_EDGE = 0;
localparam NEG_EDGE = 1;
localparam SERIAL = 0;
localparam PARALLEL = 1;
// internal signals
reg [31:0] up_scratch = 32'b0;
reg up_resetn = 1'b0;
reg up_cnvst_en = 1'b0;
reg [31:0] up_conv_rate = 32'b0;
reg [31:0] cnvst_counter = 32'b0;
reg [ 3:0] pulse_counter = 8'b0;
reg cnvst_buf = 1'b0;
reg cnvst_pulse = 1'b0;
reg [ 2:0] chsel_ff = 3'b0;
wire up_rst;
wire up_rack_s;
wire [31:0] up_read_data_s;
wire up_read_valid_s;
// the up_[read/write]_data interfaces are valid just in parallel mode
assign up_read_valid_s = (IF_TYPE == PARALLEL) ? up_read_valid : 1'b1;
assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : {2{16'hDEAD}};
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 1'h0;
up_scratch <= 32'b0;
up_resetn <= 1'b0;
up_cnvst_en <= 1'b0;
up_conv_rate <= 32'b0;
up_burst_length <= 5'h0;
up_write_data <= 16'h0;
end else begin
up_wack <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h102)) begin
up_scratch <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h110)) begin
up_resetn <= up_wdata[0];
up_cnvst_en <= up_wdata[1];
end
if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h111)) begin
up_conv_rate <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h112)) begin
up_burst_length <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h114)) begin
up_write_data <= up_wdata;
end
end
end
assign up_write_req = (up_waddr[8:0] == 9'h114) ? up_wreq : 1'h0;
// processor read interface
assign up_rack_s = (up_raddr[8:0] == 9'h113) ? up_read_valid_s : up_rreq;
assign up_read_req = (up_raddr[8:0] == 9'h113) ? up_rreq : 1'b0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 1'b0;
up_rdata <= 32'b0;
end else begin
up_rack <= up_rack_s;
if (up_rack_s == 1'b1) begin
case (up_raddr[8:0])
9'h100 : up_rdata <= PCORE_VERSION;
9'h101 : up_rdata <= ID;
9'h102 : up_rdata <= up_scratch;
9'h103 : up_rdata <= IF_TYPE;
9'h110 : up_rdata <= {29'b0, up_cnvst_en, up_resetn};
9'h111 : up_rdata <= up_conv_rate;
9'h112 : up_rdata <= {27'b0, up_burst_length};
9'h113 : up_rdata <= up_read_data_s;
default : up_rdata <= 'h0;
endcase
end
end
end
// instantiations
assign up_rst = ~up_rstn;
ad_edge_detect #(
.EDGE(NEG_EDGE)
) i_ad_edge_detect (
.clk (up_clk),
.rst (up_rst),
.signal_in (busy),
.signal_out (end_of_conv)
);
// convertion start generator
// NOTE: + The minimum convertion cycle is 1 us
// + The rate of the cnvst must be defined in a way,
// to not lose any data. cnvst_rate >= t_conversion + t_aquisition
// See the AD7616 datasheet for more information.
always @(posedge up_clk) begin
if(up_resetn == 1'b0) begin
cnvst_counter <= 32'b0;
end else begin
cnvst_counter <= (cnvst_counter < up_conv_rate) ? cnvst_counter + 1 : 32'b0;
end
end
always @(cnvst_counter, up_conv_rate) begin
cnvst_pulse <= (cnvst_counter == up_conv_rate) ? 1'b1 : 1'b0;
end
always @(posedge up_clk) begin
if(up_resetn == 1'b0) begin
pulse_counter <= 3'b0;
cnvst_buf <= 1'b0;
end else begin
pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 3'b0;
if(cnvst_pulse == 1'b1) begin
cnvst_buf <= 1'b1;
end else if (pulse_counter[2] == 1'b1) begin
cnvst_buf <= 1'b0;
end
end
end
assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
endmodule
adi_library/axi_ad7616/axi_ad7616_ip.log
+1090
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File diff suppressed because it is too large Load Diff
adi_library/axi_ad7616/axi_ad7616_ip.tcl
+27
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@@ -0,0 +1,27 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_ad7616
adi_ip_files axi_ad7616 [list \
"$ad_hdl_dir/library/common/ad_edge_detect.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_ad7616_control.v" \
"axi_ad7616_pif.v" \
"axi_ad7616_maxis2wrfifo.v" \
"axi_ad7616.v" ]
adi_ip_properties axi_ad7616
adi_ip_add_core_dependencies { \
analog.com:user:spi_engine_execution:1.0 \
analog.com:user:axi_spi_engine:1.0 \
analog.com:user:spi_engine_offload:1.0 \
analog.com:user:spi_engine_interconnect:1.0 \
}
set_property DRIVER_VALUE "0" [ipx::get_ports rx_db_i]
ipx::save_core [ipx::current_core]
adi_library/axi_ad7616/axi_ad7616_maxis2wrfifo.v
+83
View File
@@ -0,0 +1,83 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616_maxis2wrfifo #(
parameter DATA_WIDTH = 16) (
input clk,
input rstn,
input sync_in,
// m_axis interface
input [DATA_WIDTH-1:0] m_axis_data,
output reg m_axis_ready,
input m_axis_valid,
output reg m_axis_xfer_req,
// write fifo interface
output reg fifo_wr_en,
output reg [DATA_WIDTH-1:0] fifo_wr_data,
output reg fifo_wr_sync,
input fifo_wr_xfer_req
);
always @(posedge clk) begin
if (rstn == 1'b0) begin
m_axis_ready <= 1'b0;
m_axis_xfer_req <= 1'b0;
fifo_wr_data <= 'b0;
fifo_wr_en <= 1'b0;
fifo_wr_sync <= 1'b0;
end else begin
m_axis_ready <= 1'b1;
m_axis_xfer_req <= fifo_wr_xfer_req;
fifo_wr_data <= m_axis_data;
fifo_wr_en <= m_axis_valid;
if (sync_in == 1'b1) begin
fifo_wr_sync <= 1'b1;
end else if ((m_axis_valid == 1'b1) &&
(fifo_wr_sync == 1'b1)) begin
fifo_wr_sync <= 1'b0;
end
end
end
endmodule
adi_library/axi_ad7616/axi_ad7616_pif.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616_pif #(
parameter UP_ADDRESS_WIDTH = 14) (
// physical interface
output cs_n,
output [15:0] db_o,
input [15:0] db_i,
output db_t,
output rd_n,
output wr_n,
// FIFO interface
output [15:0] adc_data,
output adc_valid,
output reg adc_sync,
// end of convertion
input end_of_conv,
input [ 4:0] burst_length,
// register access
input clk,
input rstn,
input rd_req,
input wr_req,
input [15:0] wr_data,
output reg [15:0] rd_data,
output reg rd_valid);
// state registers
localparam [ 2:0] IDLE = 3'h0,
CS_LOW = 3'h1,
CNTRL0_LOW = 3'h2,
CNTRL0_HIGH = 3'h3,
CNTRL1_LOW = 3'h4,
CNTRL1_HIGH = 3'h5,
CS_HIGH = 3'h6;
// internal registers
reg [ 2:0] transfer_state = 3'h0;
reg [ 2:0] transfer_state_next = 3'h0;
reg [ 1:0] width_counter = 2'h0;
reg [ 4:0] burst_counter = 5'h0;
reg wr_req_d = 1'h0;
reg rd_req_d = 1'h0;
reg rd_conv_d = 1'h0;
reg xfer_req_d = 1'h0;
reg rd_valid_d = 1'h0;
// internal wires
wire start_transfer_s;
wire rd_valid_s;
// FSM state register
always @(posedge clk) begin
if (rstn == 1'b0) begin
transfer_state <= 3'h0;
end else begin
transfer_state <= transfer_state_next;
end
end
// counters to control the RD_N and WR_N lines
assign start_transfer_s = end_of_conv | rd_req | wr_req;
always @(posedge clk) begin
if (rstn == 1'b0) begin
width_counter <= 2'h0;
end else begin
if((transfer_state == CNTRL0_LOW) || (transfer_state == CNTRL0_HIGH) ||
(transfer_state == CNTRL1_LOW) || (transfer_state == CNTRL1_HIGH))
width_counter <= width_counter + 1;
else
width_counter <= 2'h0;
end
end
always @(posedge clk) begin
if (rstn == 1'b0) begin
burst_counter <= 2'h0;
end else begin
if (transfer_state == CS_HIGH)
burst_counter <= burst_counter + 1;
else if (transfer_state == IDLE)
burst_counter <= 5'h0;
end
end
always @(negedge clk) begin
if (transfer_state == IDLE) begin
wr_req_d <= wr_req;
rd_req_d <= rd_req;
rd_conv_d <= end_of_conv;
end
end
// FSM next state logic
always @(*) begin
case (transfer_state)
IDLE : begin
transfer_state_next <= (start_transfer_s == 1'b1) ? CS_LOW : IDLE;
end
CS_LOW : begin
transfer_state_next <= CNTRL0_LOW;
end
CNTRL0_LOW : begin
transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_LOW : CNTRL0_HIGH;
end
CNTRL0_HIGH : begin
transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_HIGH :
((wr_req_d == 1'b1) || (rd_req_d == 1'b1)) ? CS_HIGH : CNTRL1_LOW;
end
CNTRL1_LOW : begin
transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_LOW : CNTRL1_HIGH;
end
CNTRL1_HIGH : begin
transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH;
end
CS_HIGH : begin
transfer_state_next <= (burst_length == burst_counter) ? IDLE : CNTRL0_LOW;
end
default : begin
transfer_state_next <= IDLE;
end
endcase
end
// data valid for the register access and m_axis interface
assign rd_valid_s = (((transfer_state == CNTRL0_HIGH) || (transfer_state == CNTRL1_HIGH)) &&
((rd_req_d == 1'b1) || (rd_conv_d == 1'b1))) ? 1'b1 : 1'b0;
// FSM output logic
assign db_o = wr_data;
always @(posedge clk) begin
rd_data <= (rd_valid_s & ~rd_valid_d) ? db_i : rd_data;
rd_valid_d <= rd_valid_s;
rd_valid <= rd_valid_s & ~rd_valid_d;
end
assign adc_valid = rd_valid;
assign adc_data = rd_data;
assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0;
assign db_t = ~wr_req_d;
assign rd_n = (((transfer_state == CNTRL0_LOW) && ((rd_conv_d == 1'b1) || rd_req_d == 1'b1)) ||
(transfer_state == CNTRL1_LOW)) ? 1'b0 : 1'b1;
assign wr_n = ((transfer_state == CNTRL0_LOW) && (wr_req_d == 1'b1)) ? 1'b0 : 1'b1;
// sync will be asserted at the first valid data right after the convertion start
always @(posedge clk) begin
if (end_of_conv == 1'b1) begin
adc_sync <= 1'b1;
end else if (rd_valid == 1'b1) begin
adc_sync <= 1'b0;
end
end
endmodule
adi_library/axi_ad7616/component.xml
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adi_library/axi_ad7616/vivado.jou
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#-----------------------------------------------------------
# Vivado v2019.1.3 (64-bit)
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
# Start of session at: Thu Dec 9 15:08:05 2021
# Process ID: 3419
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616
# Command line: vivado -mode batch -source axi_ad7616_ip.tcl
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616/vivado.log
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616/vivado.jou
#-----------------------------------------------------------
source axi_ad7616_ip.tcl
adi_library/axi_ad7616/vivado.log
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adi_library/axi_ad7616/xgui/axi_ad7616_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
ipgui::add_param $IPINST -name "IF_TYPE" -parent ${Page_0}
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.IF_TYPE { PARAM_VALUE.IF_TYPE } {
# Procedure called to update IF_TYPE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IF_TYPE { PARAM_VALUE.IF_TYPE } {
# Procedure called to validate IF_TYPE
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.IF_TYPE { MODELPARAM_VALUE.IF_TYPE PARAM_VALUE.IF_TYPE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IF_TYPE}] ${MODELPARAM_VALUE.IF_TYPE}
}