Archived
initial commit
This commit is contained in:
@@ -0,0 +1,32 @@
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||||
####################################################################################
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||||
## Copyright 2018(c) Analog Devices, Inc.
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||||
## Auto-generated, do not modify!
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||||
####################################################################################
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||||
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||||
LIBRARY_NAME := axi_ad9162
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||||
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||||
GENERIC_DEPS += ../common/ad_dds_1.v
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||||
GENERIC_DEPS += ../common/ad_dds_2.v
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||||
GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
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||||
GENERIC_DEPS += ../common/ad_dds_sine.v
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||||
GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
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||||
GENERIC_DEPS += ../common/ad_rst.v
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||||
GENERIC_DEPS += ../common/up_axi.v
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||||
GENERIC_DEPS += ../common/up_clock_mon.v
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||||
GENERIC_DEPS += ../common/up_dac_channel.v
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||||
GENERIC_DEPS += ../common/up_dac_common.v
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||||
GENERIC_DEPS += ../common/up_xfer_cntrl.v
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||||
GENERIC_DEPS += ../common/up_xfer_status.v
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||||
GENERIC_DEPS += axi_ad9162.v
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||||
GENERIC_DEPS += axi_ad9162_channel.v
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||||
GENERIC_DEPS += axi_ad9162_core.v
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||||
GENERIC_DEPS += axi_ad9162_if.v
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||||
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||||
XILINX_DEPS += ../xilinx/common/ad_mul.v
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||||
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
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||||
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
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||||
XILINX_DEPS += axi_ad9162_ip.tcl
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||||
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||||
include ../scripts/library.mk
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@@ -0,0 +1,3 @@
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||||
version:1
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||||
6d6f64655f636f756e7465727c42617463684d6f6465:1
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||||
eof:
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||||
@@ -0,0 +1,6 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
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||||
@@ -0,0 +1,191 @@
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||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
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||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
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||||
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||||
`timescale 1ns / 1ps
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module axi_ad9162 #(
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parameter ID = 0,
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parameter FPGA_TECHNOLOGY = 0,
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||||
parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter DAC_DDS_TYPE = 1,
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||||
parameter DAC_DDS_CORDIC_DW = 16,
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||||
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
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||||
parameter DAC_DATAPATH_DISABLE = 0) (
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||||
|
||||
// jesd interface
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||||
// tx_clk is (line-rate/40)
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||||
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||||
input tx_clk,
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output tx_valid,
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||||
output [255:0] tx_data,
|
||||
input tx_ready,
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||||
|
||||
// dma interface
|
||||
|
||||
output dac_clk,
|
||||
output dac_valid,
|
||||
output dac_enable,
|
||||
input [255:0] dac_ddata,
|
||||
input dac_dunf,
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||||
|
||||
// axi interface
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||||
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||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
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||||
input s_axi_awvalid,
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||||
input [ 15:0] s_axi_awaddr,
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||||
input [ 2:0] s_axi_awprot,
|
||||
output s_axi_awready,
|
||||
input s_axi_wvalid,
|
||||
input [ 31:0] s_axi_wdata,
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||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [ 15:0] s_axi_araddr,
|
||||
input [ 2:0] s_axi_arprot,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
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||||
output [ 31:0] s_axi_rdata,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
input s_axi_rready);
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||||
|
||||
// internal clocks and resets
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||||
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||||
wire dac_rst;
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||||
wire up_clk;
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||||
wire up_rstn;
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||||
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||||
// internal signals
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||||
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||||
wire [255:0] dac_data_s;
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||||
wire up_wreq_s;
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||||
wire [ 13:0] up_waddr_s;
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wire [ 31:0] up_wdata_s;
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||||
wire up_wack_s;
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||||
wire up_rreq_s;
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||||
wire [ 13:0] up_raddr_s;
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||||
wire [ 31:0] up_rdata_s;
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||||
wire up_rack_s;
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||||
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||||
// signal name changes
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||||
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||||
assign up_clk = s_axi_aclk;
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||||
assign up_rstn = s_axi_aresetn;
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||||
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||||
// defaults
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||||
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||||
assign tx_valid = 1'b1;
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||||
|
||||
// device interface
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||||
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||||
axi_ad9162_if i_if (
|
||||
.tx_clk (tx_clk),
|
||||
.tx_data (tx_data),
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||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_data (dac_data_s));
|
||||
|
||||
// core
|
||||
|
||||
axi_ad9162_core #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
|
||||
i_core (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_data (dac_data_s),
|
||||
.dac_valid (dac_valid),
|
||||
.dac_enable (dac_enable),
|
||||
.dac_ddata (dac_ddata),
|
||||
.dac_dunf (dac_dunf),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
// up bus interface
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||||
|
||||
up_axi i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,519 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162/axi_ad9162.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="b27539d14306423b8eea141831d1e472"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
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||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPCachePermission" Val="read"/>
|
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<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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||||
<Option Name="EnableBDX" Val="FALSE"/>
|
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<Option Name="DSAVendor" Val="xilinx"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
|
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="0"/>
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<Option Name="WTModelSimExportSim" Val="0"/>
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<Option Name="WTQuestaExportSim" Val="0"/>
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<Option Name="WTIesExportSim" Val="0"/>
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<Option Name="WTVcsExportSim" Val="0"/>
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<Option Name="WTRivieraExportSim" Val="0"/>
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<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
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||||
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||||
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||||
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||||
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||||
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||||
<FileInfo>
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|
||||
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|
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||||
</FileInfo>
|
||||
</File>
|
||||
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|
||||
<FileInfo>
|
||||
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||||
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|
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||||
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||||
<FileInfo>
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|
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|
||||
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|
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||||
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||||
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|
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|
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|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_ad9162"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_xfer_cntrl_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/ad_rst_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_xfer_status_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_clock_mon_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,577 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module axi_ad9162_channel #(
|
||||
|
||||
parameter CHANNEL_ID = 32'h0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 16,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
|
||||
parameter DATAPATH_DISABLE = 0) (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_clk,
|
||||
input dac_rst,
|
||||
output dac_enable,
|
||||
output [255:0] dac_data,
|
||||
input [255:0] dma_data,
|
||||
|
||||
// processor interface
|
||||
|
||||
input dac_data_sync,
|
||||
input dac_dds_format,
|
||||
|
||||
// bus interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [ 13:0] up_waddr,
|
||||
input [ 31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [ 13:0] up_raddr,
|
||||
output [ 31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [255:0] dac_data_int = 'd0;
|
||||
reg dac_enable_int = 'd0;
|
||||
reg [255:0] dac_data_d = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_00_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_00_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_01_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_01_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_02_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_02_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_03_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_03_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_04_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_04_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_05_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_05_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_06_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_06_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_07_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_07_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_08_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_08_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_09_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_09_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_10_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_10_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_11_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_11_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_12_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_12_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_13_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_13_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_14_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_14_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_15_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_15_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_incr_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_incr_1 = 'd0;
|
||||
reg [255:0] dac_dds_data = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [ 15:0] dac_dds_scale_1_s;
|
||||
wire [ 15:0] dac_dds_init_1_s;
|
||||
wire [ 15:0] dac_dds_incr_1_s;
|
||||
wire [ 15:0] dac_dds_scale_2_s;
|
||||
wire [ 15:0] dac_dds_init_2_s;
|
||||
wire [ 15:0] dac_dds_incr_2_s;
|
||||
wire [ 15:0] dac_pat_data_1_s;
|
||||
wire [ 15:0] dac_pat_data_2_s;
|
||||
wire [ 3:0] dac_data_sel_s;
|
||||
wire [ 1:0] dac_iq_mode_s;
|
||||
wire [255:0] dac_pat_data_s;
|
||||
wire [255:0] dac_dds_data_s;
|
||||
wire [255:0] dac_dds_data_i_s;
|
||||
|
||||
// dac sample mux
|
||||
|
||||
assign dac_data = dac_data_int;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dac_data_int[255:240] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[255:240] : dac_data_d[255:240];
|
||||
dac_data_int[239:224] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[223:208] : dac_data_d[239:224];
|
||||
dac_data_int[223:208] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[239:224] : dac_data_d[223:208];
|
||||
dac_data_int[207:192] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[207:192] : dac_data_d[207:192];
|
||||
dac_data_int[191:176] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[191:176] : dac_data_d[191:176];
|
||||
dac_data_int[175:160] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[159:144] : dac_data_d[175:160];
|
||||
dac_data_int[159:144] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[175:160] : dac_data_d[159:144];
|
||||
dac_data_int[143:128] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[143:128] : dac_data_d[143:128];
|
||||
dac_data_int[127:112] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[127:112] : dac_data_d[127:112];
|
||||
dac_data_int[111: 96] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 95: 80] : dac_data_d[111: 96];
|
||||
dac_data_int[ 95: 80] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[111: 96] : dac_data_d[ 95: 80];
|
||||
dac_data_int[ 79: 64] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 79: 64] : dac_data_d[ 79: 64];
|
||||
dac_data_int[ 63: 48] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 63: 48] : dac_data_d[ 63: 48];
|
||||
dac_data_int[ 47: 32] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 31: 16] : dac_data_d[ 47: 32];
|
||||
dac_data_int[ 31: 16] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 47: 32] : dac_data_d[ 31: 16];
|
||||
dac_data_int[ 15: 0] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 15: 0] : dac_data_d[ 15: 0];
|
||||
end
|
||||
|
||||
// dac pattern data
|
||||
|
||||
genvar n;
|
||||
generate
|
||||
for (n = 0; n < 8; n = n + 1) begin: g_dac_pat_data
|
||||
assign dac_pat_data_s[((32*n)+31):((32*n)+16)] = dac_pat_data_2_s;
|
||||
assign dac_pat_data_s[((32*n)+15):((32*n)+ 0)] = dac_pat_data_1_s;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// dac data select
|
||||
|
||||
assign dac_enable = dac_enable_int;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dac_enable_int <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
|
||||
case (dac_data_sel_s)
|
||||
4'h3: dac_data_d <= 256'd0;
|
||||
4'h2: dac_data_d <= dma_data;
|
||||
4'h1: dac_data_d <= dac_pat_data_s;
|
||||
default: dac_data_d <= dac_dds_data;
|
||||
endcase
|
||||
end
|
||||
|
||||
// dds
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_data_sync == 1'b0) begin
|
||||
dac_dds_phase_00_0 <= dac_dds_phase_00_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_00_1 <= dac_dds_phase_00_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_01_0 <= dac_dds_phase_01_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_01_1 <= dac_dds_phase_01_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_02_0 <= dac_dds_phase_02_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_02_1 <= dac_dds_phase_02_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_03_0 <= dac_dds_phase_03_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_03_1 <= dac_dds_phase_03_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_04_0 <= dac_dds_phase_04_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_04_1 <= dac_dds_phase_04_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_05_0 <= dac_dds_phase_05_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_05_1 <= dac_dds_phase_05_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_06_0 <= dac_dds_phase_06_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_06_1 <= dac_dds_phase_06_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_07_0 <= dac_dds_phase_07_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_07_1 <= dac_dds_phase_07_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_08_0 <= dac_dds_phase_08_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_08_1 <= dac_dds_phase_08_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_09_0 <= dac_dds_phase_09_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_09_1 <= dac_dds_phase_09_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_10_0 <= dac_dds_phase_10_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_10_1 <= dac_dds_phase_10_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_11_0 <= dac_dds_phase_11_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_11_1 <= dac_dds_phase_11_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_12_0 <= dac_dds_phase_12_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_12_1 <= dac_dds_phase_12_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_13_0 <= dac_dds_phase_13_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_13_1 <= dac_dds_phase_13_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_14_0 <= dac_dds_phase_14_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_14_1 <= dac_dds_phase_14_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_15_0 <= dac_dds_phase_15_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_15_1 <= dac_dds_phase_15_1 + dac_dds_incr_1;
|
||||
dac_dds_incr_0 <= dac_dds_incr_0;
|
||||
dac_dds_incr_1 <= dac_dds_incr_1;
|
||||
dac_dds_data <= dac_dds_data_s;
|
||||
end else if (dac_iq_mode_s[0] == 1'b1) begin
|
||||
dac_dds_phase_00_0 <= dac_dds_init_1_s;
|
||||
dac_dds_phase_00_1 <= dac_dds_init_2_s;
|
||||
dac_dds_phase_01_0 <= dac_dds_phase_00_0 + 16'h4000;
|
||||
dac_dds_phase_01_1 <= dac_dds_phase_00_1 + 16'h4000;
|
||||
dac_dds_phase_02_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_02_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_03_0 <= dac_dds_phase_02_0 + 16'h4000;
|
||||
dac_dds_phase_03_1 <= dac_dds_phase_02_1 + 16'h4000;
|
||||
dac_dds_phase_04_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_04_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_05_0 <= dac_dds_phase_04_0 + 16'h4000;
|
||||
dac_dds_phase_05_1 <= dac_dds_phase_04_1 + 16'h4000;
|
||||
dac_dds_phase_06_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_06_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_07_0 <= dac_dds_phase_06_0 + 16'h4000;
|
||||
dac_dds_phase_07_1 <= dac_dds_phase_06_1 + 16'h4000;
|
||||
dac_dds_phase_08_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_08_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_09_0 <= dac_dds_phase_08_0 + 16'h4000;
|
||||
dac_dds_phase_09_1 <= dac_dds_phase_08_1 + 16'h4000;
|
||||
dac_dds_phase_10_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_10_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_11_0 <= dac_dds_phase_10_0 + 16'h4000;
|
||||
dac_dds_phase_11_1 <= dac_dds_phase_10_1 + 16'h4000;
|
||||
dac_dds_phase_12_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_12_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_13_0 <= dac_dds_phase_12_0 + 16'h4000;
|
||||
dac_dds_phase_13_1 <= dac_dds_phase_12_1 + 16'h4000;
|
||||
dac_dds_phase_14_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_14_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_15_0 <= dac_dds_phase_14_0 + 16'h4000;
|
||||
dac_dds_phase_15_1 <= dac_dds_phase_14_1 + 16'h4000;
|
||||
dac_dds_incr_0 <= {dac_dds_incr_1_s[12:0], 3'd0};
|
||||
dac_dds_incr_1 <= {dac_dds_incr_2_s[12:0], 3'd0};
|
||||
dac_dds_data <= 256'd0;
|
||||
end else begin
|
||||
dac_dds_phase_00_0 <= dac_dds_init_1_s;
|
||||
dac_dds_phase_00_1 <= dac_dds_init_2_s;
|
||||
dac_dds_phase_01_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_01_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_02_0 <= dac_dds_phase_01_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_02_1 <= dac_dds_phase_01_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_03_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_03_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_04_0 <= dac_dds_phase_03_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_04_1 <= dac_dds_phase_03_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_05_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_05_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_06_0 <= dac_dds_phase_05_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_06_1 <= dac_dds_phase_05_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_07_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_07_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_08_0 <= dac_dds_phase_07_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_08_1 <= dac_dds_phase_07_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_09_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_09_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_10_0 <= dac_dds_phase_09_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_10_1 <= dac_dds_phase_09_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_11_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_11_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_12_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_12_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_13_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_13_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_14_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_14_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_15_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_15_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s;
|
||||
dac_dds_incr_0 <= {dac_dds_incr_1_s[11:0], 4'd0};
|
||||
dac_dds_incr_1 <= {dac_dds_incr_2_s[11:0], 4'd0};
|
||||
dac_dds_data <= 256'd0;
|
||||
end
|
||||
end
|
||||
|
||||
assign dac_dds_data_s[255:240] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[239:224] : dac_dds_data_i_s[255:240];
|
||||
assign dac_dds_data_s[239:224] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[255:240] : dac_dds_data_i_s[239:224];
|
||||
assign dac_dds_data_s[223:208] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[207:192] : dac_dds_data_i_s[223:208];
|
||||
assign dac_dds_data_s[207:192] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[223:208] : dac_dds_data_i_s[207:192];
|
||||
assign dac_dds_data_s[191:176] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[175:160] : dac_dds_data_i_s[191:176];
|
||||
assign dac_dds_data_s[175:160] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[191:176] : dac_dds_data_i_s[175:160];
|
||||
assign dac_dds_data_s[159:144] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[143:128] : dac_dds_data_i_s[159:144];
|
||||
assign dac_dds_data_s[143:128] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[159:144] : dac_dds_data_i_s[143:128];
|
||||
assign dac_dds_data_s[127:112] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[111: 96] : dac_dds_data_i_s[127:112];
|
||||
assign dac_dds_data_s[111: 96] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[127:112] : dac_dds_data_i_s[111: 96];
|
||||
assign dac_dds_data_s[ 95: 80] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 79: 64] : dac_dds_data_i_s[ 95: 80];
|
||||
assign dac_dds_data_s[ 79: 64] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 95: 80] : dac_dds_data_i_s[ 79: 64];
|
||||
assign dac_dds_data_s[ 63: 48] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 47: 32] : dac_dds_data_i_s[ 63: 48];
|
||||
assign dac_dds_data_s[ 47: 32] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 63: 48] : dac_dds_data_i_s[ 47: 32];
|
||||
assign dac_dds_data_s[ 31: 16] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 15: 0] : dac_dds_data_i_s[ 31: 16];
|
||||
assign dac_dds_data_s[ 15: 0] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 31: 16] : dac_dds_data_i_s[ 15: 0];
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_00 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_00_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_00_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[15:0]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_01 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_01_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_01_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[31:16]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_02 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_02_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_02_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[47:32]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_03 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_03_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_03_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[63:48]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_04 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_04_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_04_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[79:64]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_05 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_05_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_05_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[95:80]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_06 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_06_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_06_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[111:96]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_07 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_07_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_07_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[127:112]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_08 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_08_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_08_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[143:128]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_09 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_09_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_09_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[159:144]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_10 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_10_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_10_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[175:160]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_11 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_11_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_11_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[191:176]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_12 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_12_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_12_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[207:192]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_13 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_13_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_13_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[223:208]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_14 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_14_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_14_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[239:224]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_15 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_15_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_15_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[255:240]));
|
||||
|
||||
// single channel processor
|
||||
|
||||
up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_dds_scale_1 (dac_dds_scale_1_s),
|
||||
.dac_dds_init_1 (dac_dds_init_1_s),
|
||||
.dac_dds_incr_1 (dac_dds_incr_1_s),
|
||||
.dac_dds_scale_2 (dac_dds_scale_2_s),
|
||||
.dac_dds_init_2 (dac_dds_init_2_s),
|
||||
.dac_dds_incr_2 (dac_dds_incr_2_s),
|
||||
.dac_pat_data_1 (dac_pat_data_1_s),
|
||||
.dac_pat_data_2 (dac_pat_data_2_s),
|
||||
.dac_data_sel (dac_data_sel_s),
|
||||
.dac_iq_mode (dac_iq_mode_s),
|
||||
.dac_iqcor_enb (),
|
||||
.dac_iqcor_coeff_1 (),
|
||||
.dac_iqcor_coeff_2 (),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_interpolation_m (),
|
||||
.up_usr_interpolation_n (),
|
||||
.dac_usr_datatype_be (1'b0),
|
||||
.dac_usr_datatype_signed (1'b1),
|
||||
.dac_usr_datatype_shift (8'd0),
|
||||
.dac_usr_datatype_total_bits (8'd16),
|
||||
.dac_usr_datatype_bits (8'd16),
|
||||
.dac_usr_interpolation_m (16'd1),
|
||||
.dac_usr_interpolation_n (16'd1),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,190 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module axi_ad9162_core #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 16,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
|
||||
parameter DATAPATH_DISABLE = 0) (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_clk,
|
||||
output dac_rst,
|
||||
output [255:0] dac_data,
|
||||
|
||||
// dma interface
|
||||
|
||||
output dac_valid,
|
||||
output dac_enable,
|
||||
input [255:0] dac_ddata,
|
||||
input dac_dunf,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [ 13:0] up_waddr,
|
||||
input [ 31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [ 13:0] up_raddr,
|
||||
output reg [ 31:0] up_rdata,
|
||||
output reg up_rack);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire dac_sync_s;
|
||||
wire dac_datafmt_s;
|
||||
wire [ 31:0] up_rdata_0_s;
|
||||
wire up_rack_0_s;
|
||||
wire up_wack_0_s;
|
||||
wire [ 31:0] up_rdata_s;
|
||||
wire up_rack_s;
|
||||
wire up_wack_s;
|
||||
|
||||
// dac valid
|
||||
|
||||
assign dac_valid = 1'b1;
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rdata <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_wack <= 'd0;
|
||||
end else begin
|
||||
up_rdata <= up_rdata_s | up_rdata_0_s;
|
||||
up_rack <= up_rack_s | up_rack_0_s;
|
||||
up_wack <= up_wack_s | up_wack_0_s;
|
||||
end
|
||||
end
|
||||
|
||||
// dac channel
|
||||
|
||||
axi_ad9162_channel #(
|
||||
.CHANNEL_ID (0),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE))
|
||||
i_channel_0 (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_enable (dac_enable),
|
||||
.dac_data (dac_data),
|
||||
.dma_data (dac_ddata),
|
||||
.dac_data_sync (dac_sync_s),
|
||||
.dac_dds_format (dac_datafmt_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_0_s),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_0_s),
|
||||
.up_rack (up_rack_0_s));
|
||||
|
||||
// dac common processor interface
|
||||
|
||||
up_dac_common #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.CONFIG (0),
|
||||
.CLK_EDGE_SEL (1'b0),
|
||||
.COMMON_ID (6'h10),
|
||||
.DRP_DISABLE (0),
|
||||
.USERPORTS_DISABLE (0),
|
||||
.GPIO_DISABLE (0))
|
||||
i_up_dac_common (
|
||||
.mmcm_rst (),
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_sync (dac_sync_s),
|
||||
.dac_frame (),
|
||||
.dac_clksel (),
|
||||
.dac_par_type (),
|
||||
.dac_par_enb (),
|
||||
.dac_r1_mode (),
|
||||
.dac_datafmt (dac_datafmt_s),
|
||||
.dac_datarate (),
|
||||
.dac_status (1'b1),
|
||||
.dac_status_unf (dac_dunf),
|
||||
.dac_clk_ratio (32'd16),
|
||||
.up_dac_ce (),
|
||||
.up_pps_rcounter (32'd0),
|
||||
.up_pps_status (1'd0),
|
||||
.up_pps_irq_mask (),
|
||||
.up_drp_sel (),
|
||||
.up_drp_wr (),
|
||||
.up_drp_addr (),
|
||||
.up_drp_wdata (),
|
||||
.up_drp_rdata (32'd0),
|
||||
.up_drp_ready (1'd0),
|
||||
.up_drp_locked (1'd1),
|
||||
.up_usr_chanmax (),
|
||||
.dac_usr_chanmax (8'd0),
|
||||
.up_dac_gpio_in (32'd0),
|
||||
.up_dac_gpio_out (),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,94 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module axi_ad9162_if (
|
||||
|
||||
// jesd interface
|
||||
// tx_clk is (line-rate/40)
|
||||
|
||||
input tx_clk,
|
||||
output reg [255:0] tx_data,
|
||||
|
||||
// dac interface
|
||||
|
||||
output dac_clk,
|
||||
input dac_rst,
|
||||
input [255:0] dac_data);
|
||||
|
||||
// reorder data for the jesd links
|
||||
|
||||
assign dac_clk = tx_clk;
|
||||
|
||||
always @(posedge tx_clk) begin
|
||||
tx_data[255:248] <= dac_data[247:240];
|
||||
tx_data[247:240] <= dac_data[183:176];
|
||||
tx_data[239:232] <= dac_data[119:112];
|
||||
tx_data[231:224] <= dac_data[ 55: 48];
|
||||
tx_data[223:216] <= dac_data[255:248];
|
||||
tx_data[215:208] <= dac_data[191:184];
|
||||
tx_data[207:200] <= dac_data[127:120];
|
||||
tx_data[199:192] <= dac_data[ 63: 56];
|
||||
tx_data[191:184] <= dac_data[231:224];
|
||||
tx_data[183:176] <= dac_data[167:160];
|
||||
tx_data[175:168] <= dac_data[103: 96];
|
||||
tx_data[167:160] <= dac_data[ 39: 32];
|
||||
tx_data[159:152] <= dac_data[239:232];
|
||||
tx_data[151:144] <= dac_data[175:168];
|
||||
tx_data[143:136] <= dac_data[111:104];
|
||||
tx_data[135:128] <= dac_data[ 47: 40];
|
||||
tx_data[127:120] <= dac_data[215:208];
|
||||
tx_data[119:112] <= dac_data[151:144];
|
||||
tx_data[111:104] <= dac_data[ 87: 80];
|
||||
tx_data[103: 96] <= dac_data[ 23: 16];
|
||||
tx_data[ 95: 88] <= dac_data[223:216];
|
||||
tx_data[ 87: 80] <= dac_data[159:152];
|
||||
tx_data[ 79: 72] <= dac_data[ 95: 88];
|
||||
tx_data[ 71: 64] <= dac_data[ 31: 24];
|
||||
tx_data[ 63: 56] <= dac_data[199:192];
|
||||
tx_data[ 55: 48] <= dac_data[135:128];
|
||||
tx_data[ 47: 40] <= dac_data[ 71: 64];
|
||||
tx_data[ 39: 32] <= dac_data[ 7: 0];
|
||||
tx_data[ 31: 24] <= dac_data[207:200];
|
||||
tx_data[ 23: 16] <= dac_data[143:136];
|
||||
tx_data[ 15: 8] <= dac_data[ 79: 72];
|
||||
tx_data[ 7: 0] <= dac_data[ 15: 8];
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,43 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad9162
|
||||
adi_ip_files axi_ad9162 [list \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_1.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_2.v" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_channel.v" \
|
||||
"axi_ad9162_channel.v" \
|
||||
"axi_ad9162_core.v" \
|
||||
"axi_ad9162_if.v" \
|
||||
"axi_ad9162.v" ]
|
||||
|
||||
adi_ip_properties axi_ad9162
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad9162 "bd/bd.tcl"
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Dec 9 15:09:13 2021
|
||||
# Process ID: 3828
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162
|
||||
# Command line: vivado -mode batch -source axi_ad9162_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_ad9162_ip.tcl
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,148 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to validate DAC_DATAPATH_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_PHASE_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to validate DAC_DDS_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user