Archived
initial commit
This commit is contained in:
@@ -0,0 +1,33 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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||||
####################################################################################
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LIBRARY_NAME := axi_ad9434
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||||
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||||
GENERIC_DEPS += ../common/ad_datafmt.v
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GENERIC_DEPS += ../common/ad_pnmon.v
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||||
GENERIC_DEPS += ../common/ad_rst.v
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||||
GENERIC_DEPS += ../common/up_adc_channel.v
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GENERIC_DEPS += ../common/up_adc_common.v
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||||
GENERIC_DEPS += ../common/up_axi.v
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||||
GENERIC_DEPS += ../common/up_clock_mon.v
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GENERIC_DEPS += ../common/up_delay_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += axi_ad9434.v
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GENERIC_DEPS += axi_ad9434_core.v
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GENERIC_DEPS += axi_ad9434_if.v
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GENERIC_DEPS += axi_ad9434_pnmon.v
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XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v
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XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += ../xilinx/common/ad_serdes_clk.v
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XILINX_DEPS += ../xilinx/common/ad_serdes_in.v
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XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
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XILINX_DEPS += axi_ad9434_constr.xdc
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XILINX_DEPS += axi_ad9434_ip.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
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||||
<labtools version="1" minor="0"/>
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||||
@@ -0,0 +1,236 @@
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// ***************************************************************************
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||||
// ***************************************************************************
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||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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||||
//
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||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
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||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
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||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
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||||
// ***************************************************************************
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||||
// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9434 #(
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parameter ID = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group") (
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// physical interface
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input adc_clk_in_p,
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input adc_clk_in_n,
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input [11:0] adc_data_in_p,
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input [11:0] adc_data_in_n,
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input adc_or_in_p,
|
||||
input adc_or_in_n,
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||||
|
||||
// delay interface
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||||
input delay_clk,
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||||
|
||||
// dma interface
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||||
output adc_clk,
|
||||
output adc_enable,
|
||||
output adc_valid,
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output [63:0] adc_data,
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||||
input adc_dovf,
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||||
|
||||
// axi interface
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||||
input s_axi_aclk,
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||||
input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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||||
output s_axi_awready,
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||||
input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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||||
output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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||||
input s_axi_rready,
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot);
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||||
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||||
// internal clocks & resets
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wire adc_rst;
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wire up_rstn;
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wire mmcm_rst;
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wire up_clk;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_rdata_s;
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wire up_wack_s;
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wire up_rack_s;
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wire [ 1:0] up_status_pn_err_s;
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wire [ 1:0] up_status_pn_oos_s;
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wire [ 1:0] up_status_or_s;
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wire adc_status_s;
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wire [12:0] up_dld_s;
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wire [64:0] up_dwdata_s;
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wire [64:0] up_drdata_s;
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wire delay_clk_s;
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wire delay_rst;
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wire delay_locked_s;
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wire up_drp_sel_s;
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wire up_drp_wr_s;
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wire [11:0] up_drp_addr_s;
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wire [31:0] up_drp_wdata_s;
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wire [31:0] up_drp_rdata_s;
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wire up_drp_ready_s;
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wire up_drp_locked_s;
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||||
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||||
wire [47:0] adc_data_if_s;
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||||
wire adc_or_if_s;
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// clock/reset assignments
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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axi_ad9434_if #(
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||||
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
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.IO_DELAY_GROUP(IO_DELAY_GROUP))
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i_if(
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||||
.adc_clk_in_p(adc_clk_in_p),
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||||
.adc_clk_in_n(adc_clk_in_n),
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||||
.adc_data_in_p(adc_data_in_p),
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||||
.adc_data_in_n(adc_data_in_n),
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||||
.adc_or_in_p(adc_or_in_p),
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||||
.adc_or_in_n(adc_or_in_n),
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||||
.adc_data(adc_data_if_s),
|
||||
.adc_or(adc_or_if_s),
|
||||
.adc_clk(adc_clk),
|
||||
.adc_rst(adc_rst),
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||||
.adc_status(adc_status_s),
|
||||
.up_clk (up_clk),
|
||||
.up_adc_dld (up_dld_s),
|
||||
.up_adc_dwdata (up_dwdata_s),
|
||||
.up_adc_drdata (up_drdata_s),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (delay_locked_s),
|
||||
.mmcm_rst(mmcm_rst),
|
||||
.up_rstn(up_rstn),
|
||||
.up_drp_sel(up_drp_sel_s),
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||||
.up_drp_wr(up_drp_wr_s),
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||||
.up_drp_addr(up_drp_addr_s),
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||||
.up_drp_wdata(up_drp_wdata_s),
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||||
.up_drp_rdata(up_drp_rdata_s),
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.up_drp_ready(up_drp_ready_s),
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.up_drp_locked(up_drp_locked_s));
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// common processor control
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axi_ad9434_core #(
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.ID (ID),
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||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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||||
.FPGA_FAMILY (FPGA_FAMILY),
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||||
.SPEED_GRADE (SPEED_GRADE),
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||||
.DEV_PACKAGE (DEV_PACKAGE)
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||||
) i_core (
|
||||
.adc_clk(adc_clk),
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||||
.adc_data(adc_data_if_s),
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||||
.adc_or(adc_or_if_s),
|
||||
.mmcm_rst (mmcm_rst),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_enable(adc_enable),
|
||||
.adc_status (adc_status_s),
|
||||
.dma_dvalid (adc_valid),
|
||||
.dma_data (adc_data),
|
||||
.dma_dovf (adc_dovf),
|
||||
.up_dld (up_dld_s),
|
||||
.up_dwdata (up_dwdata_s),
|
||||
.up_drdata (up_drdata_s),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (delay_locked_s),
|
||||
.up_drp_sel (up_drp_sel_s),
|
||||
.up_drp_wr (up_drp_wr_s),
|
||||
.up_drp_addr (up_drp_addr_s),
|
||||
.up_drp_wdata (up_drp_wdata_s),
|
||||
.up_drp_rdata (up_drp_rdata_s),
|
||||
.up_drp_ready (up_drp_ready_s),
|
||||
.up_drp_locked (up_drp_locked_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
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||||
|
||||
// up bus interface
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||||
up_axi i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
endmodule
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||||
@@ -0,0 +1,525 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434/axi_ad9434.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="2565cd3432ce41f6afde9063176c1b42"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../common/ad_datafmt.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/ad_mmcm_drp.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/ad_pnmon.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/ad_rst.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/ad_serdes_clk.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/ad_serdes_in.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad9434_core.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad9434_if.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad9434_pnmon.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_adc_channel.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_adc_common.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_clock_mon.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_delay_cntrl.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_xfer_cntrl.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_xfer_status.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad9434.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_ad9434"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_xfer_cntrl_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/ad_rst_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_xfer_status_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_clock_mon_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad9434_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,2 @@
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to \
|
||||
[get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}]
|
||||
@@ -0,0 +1,286 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9434_core #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0) (
|
||||
|
||||
// device interface
|
||||
|
||||
input adc_clk,
|
||||
input [47:0] adc_data,
|
||||
input adc_or,
|
||||
|
||||
// dma interface
|
||||
|
||||
output dma_dvalid,
|
||||
output [63:0] dma_data,
|
||||
input dma_dovf,
|
||||
|
||||
// drp interface
|
||||
|
||||
output up_drp_sel,
|
||||
output up_drp_wr,
|
||||
output [11:0] up_drp_addr,
|
||||
output [31:0] up_drp_wdata,
|
||||
input [31:0] up_drp_rdata,
|
||||
input up_drp_ready,
|
||||
input up_drp_locked,
|
||||
|
||||
// delay interface
|
||||
|
||||
output [12:0] up_dld,
|
||||
output [64:0] up_dwdata,
|
||||
input [64:0] up_drdata,
|
||||
input delay_clk,
|
||||
output delay_rst,
|
||||
input delay_locked,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
output reg up_rack,
|
||||
|
||||
// status and control signals
|
||||
|
||||
output mmcm_rst,
|
||||
output adc_rst,
|
||||
output adc_enable,
|
||||
input adc_status);
|
||||
|
||||
// internal signals
|
||||
wire up_status_pn_err_s;
|
||||
wire up_status_pn_oos_s;
|
||||
wire up_status_or_s;
|
||||
|
||||
wire adc_dfmt_se_s;
|
||||
wire adc_dfmt_type_s;
|
||||
wire adc_dfmt_enable_s;
|
||||
|
||||
wire [ 3:0] adc_pnseq_sel_s;
|
||||
wire adc_pn_err_s;
|
||||
wire adc_pn_oos_s;
|
||||
|
||||
wire up_wack_s[0:2];
|
||||
wire [31:0] up_rdata_s[0:2];
|
||||
wire up_rack_s[0:2];
|
||||
|
||||
// instantiations
|
||||
axi_ad9434_pnmon i_pnmon (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_data (adc_data),
|
||||
.adc_pnseq_sel (adc_pnseq_sel_s),
|
||||
.adc_pn_err (adc_pn_err_s),
|
||||
.adc_pn_oos (adc_pn_oos_s));
|
||||
|
||||
genvar n;
|
||||
generate
|
||||
for (n = 0; n < 4; n = n + 1) begin: g_ad_dfmt
|
||||
ad_datafmt # (
|
||||
.DATA_WIDTH(12))
|
||||
i_datafmt (
|
||||
.clk (adc_clk),
|
||||
.valid (1'b1),
|
||||
.data (adc_data[n*12+11:n*12]),
|
||||
.valid_out (dma_dvalid),
|
||||
.data_out (dma_data[n*16+15:n*16]),
|
||||
.dfmt_enable (adc_dfmt_enable_s),
|
||||
.dfmt_type (adc_dfmt_type_s),
|
||||
.dfmt_se (adc_dfmt_se_s));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rdata <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_wack <= 'd0;
|
||||
end else begin
|
||||
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
|
||||
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
|
||||
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
|
||||
end
|
||||
end
|
||||
|
||||
up_adc_common #(
|
||||
.ID(ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.CONFIG(0),
|
||||
.COMMON_ID(0),
|
||||
.DRP_DISABLE(0),
|
||||
.USERPORTS_DISABLE(1),
|
||||
.GPIO_DISABLE(1),
|
||||
.START_CODE_DISABLE(1))
|
||||
i_adc_common(
|
||||
.mmcm_rst (mmcm_rst),
|
||||
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_r1_mode (),
|
||||
.adc_ddr_edgesel (),
|
||||
.adc_pin_mode (),
|
||||
.adc_status (adc_status),
|
||||
.adc_sync_status (1'd0),
|
||||
.adc_status_ovf (dma_dovf),
|
||||
.adc_clk_ratio (32'd4),
|
||||
.adc_start_code (),
|
||||
.adc_sref_sync (),
|
||||
.adc_sync (),
|
||||
|
||||
.up_pps_rcounter(32'h0),
|
||||
.up_pps_status(1'b0),
|
||||
.up_pps_irq_mask(),
|
||||
|
||||
.up_adc_ce (),
|
||||
.up_status_pn_err (up_status_pn_err_s),
|
||||
.up_status_pn_oos (up_status_pn_oos_s),
|
||||
.up_status_or (up_status_or_s),
|
||||
|
||||
.up_drp_sel (up_drp_sel),
|
||||
.up_drp_wr (up_drp_wr),
|
||||
.up_drp_addr (up_drp_addr),
|
||||
.up_drp_wdata (up_drp_wdata),
|
||||
.up_drp_rdata (up_drp_rdata),
|
||||
.up_drp_ready (up_drp_ready),
|
||||
.up_drp_locked (up_drp_locked),
|
||||
|
||||
.up_usr_chanmax_out (),
|
||||
.up_usr_chanmax_in (8'd0),
|
||||
.up_adc_gpio_in (32'd0),
|
||||
.up_adc_gpio_out (),
|
||||
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[0]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[0]),
|
||||
.up_rack (up_rack_s[0]));
|
||||
|
||||
up_adc_channel #(
|
||||
.CHANNEL_ID(0),
|
||||
.USERPORTS_DISABLE(1),
|
||||
.DATAFORMAT_DISABLE(0),
|
||||
.DCFILTER_DISABLE(1),
|
||||
.IQCORRECTION_DISABLE(1))
|
||||
i_adc_channel(
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_enable (adc_enable),
|
||||
.adc_iqcor_enb (),
|
||||
.adc_dcfilt_enb (),
|
||||
.adc_dfmt_se (adc_dfmt_se_s),
|
||||
.adc_dfmt_type (adc_dfmt_type_s),
|
||||
.adc_dfmt_enable (adc_dfmt_enable_s),
|
||||
.adc_dcfilt_offset (),
|
||||
.adc_dcfilt_coeff (),
|
||||
.adc_iqcor_coeff_1 (),
|
||||
.adc_iqcor_coeff_2 (),
|
||||
.adc_pnseq_sel (adc_pnseq_sel_s),
|
||||
.adc_data_sel (),
|
||||
.adc_pn_err (adc_pn_err_s),
|
||||
.adc_pn_oos (adc_pn_oos_s),
|
||||
.adc_or (adc_or),
|
||||
.up_adc_pn_err (up_status_pn_err_s),
|
||||
.up_adc_pn_oos (up_status_pn_oos_s),
|
||||
.up_adc_or (up_status_or_s),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_decimation_m (),
|
||||
.up_usr_decimation_n (),
|
||||
.adc_usr_datatype_be (1'b0),
|
||||
.adc_usr_datatype_signed (1'b1),
|
||||
.adc_usr_datatype_shift (8'd0),
|
||||
.adc_usr_datatype_total_bits (8'd16),
|
||||
.adc_usr_datatype_bits (8'd16),
|
||||
.adc_usr_decimation_m (16'd1),
|
||||
.adc_usr_decimation_n (16'd1),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[1]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[1]),
|
||||
.up_rack (up_rack_s[1]));
|
||||
|
||||
// adc delay control
|
||||
|
||||
up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (delay_locked),
|
||||
.up_dld (up_dld),
|
||||
.up_dwdata (up_dwdata),
|
||||
.up_drdata (up_drdata),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[2]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[2]),
|
||||
.up_rack (up_rack_s[2]));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,211 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9434_if #(
|
||||
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
|
||||
|
||||
// device interface
|
||||
input adc_clk_in_p,
|
||||
input adc_clk_in_n,
|
||||
input [11:0] adc_data_in_p,
|
||||
input [11:0] adc_data_in_n,
|
||||
input adc_or_in_p,
|
||||
input adc_or_in_n,
|
||||
|
||||
// interface outputs
|
||||
output [47:0] adc_data,
|
||||
output adc_or,
|
||||
|
||||
// internl reset and clocks
|
||||
output adc_clk,
|
||||
input adc_rst,
|
||||
output reg adc_status,
|
||||
|
||||
// delay interface (for IDELAY macros)
|
||||
input up_clk,
|
||||
input [12:0] up_adc_dld,
|
||||
input [64:0] up_adc_dwdata,
|
||||
output [64:0] up_adc_drdata,
|
||||
input delay_clk,
|
||||
input delay_rst,
|
||||
output delay_locked,
|
||||
|
||||
// mmcm reset
|
||||
input mmcm_rst,
|
||||
|
||||
// drp interface for MMCM_OR_BUFR_N
|
||||
input up_rstn,
|
||||
input up_drp_sel,
|
||||
input up_drp_wr,
|
||||
input [11:0] up_drp_addr,
|
||||
input [31:0] up_drp_wdata,
|
||||
output [31:0] up_drp_rdata,
|
||||
output up_drp_ready,
|
||||
output up_drp_locked);
|
||||
|
||||
|
||||
localparam SDR = 0;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg adc_status_m1 = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [3:0] adc_or_s;
|
||||
|
||||
wire adc_clk_in;
|
||||
wire adc_div_clk;
|
||||
|
||||
genvar l_inst;
|
||||
|
||||
// output assignment for adc clock (1:4 of the sampling clock)
|
||||
assign adc_clk = adc_div_clk;
|
||||
|
||||
// data interface
|
||||
ad_serdes_in #(
|
||||
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
|
||||
.IODELAY_CTRL(0),
|
||||
.IODELAY_GROUP(IO_DELAY_GROUP),
|
||||
.DDR_OR_SDR_N(SDR),
|
||||
.DATA_WIDTH(12),
|
||||
.SERDES_FACTOR(4))
|
||||
i_adc_data (
|
||||
.rst(adc_rst),
|
||||
.clk(adc_clk_in),
|
||||
.div_clk(adc_div_clk),
|
||||
.loaden(1'b0),
|
||||
.phase(8'b0),
|
||||
.locked(1'b0),
|
||||
.data_s0(adc_data[47:36]),
|
||||
.data_s1(adc_data[35:24]),
|
||||
.data_s2(adc_data[23:12]),
|
||||
.data_s3(adc_data[11: 0]),
|
||||
.data_s4(),
|
||||
.data_s5(),
|
||||
.data_s6(),
|
||||
.data_s7(),
|
||||
.data_in_p(adc_data_in_p),
|
||||
.data_in_n(adc_data_in_n),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_adc_dld[11:0]),
|
||||
.up_dwdata (up_adc_dwdata[59:0]),
|
||||
.up_drdata (up_adc_drdata[59:0]),
|
||||
.delay_clk(delay_clk),
|
||||
.delay_rst(delay_rst),
|
||||
.delay_locked());
|
||||
|
||||
// over-range interface
|
||||
ad_serdes_in #(
|
||||
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
|
||||
.IODELAY_CTRL(1),
|
||||
.IODELAY_GROUP(IO_DELAY_GROUP),
|
||||
.DDR_OR_SDR_N(SDR),
|
||||
.DATA_WIDTH(1),
|
||||
.SERDES_FACTOR(4))
|
||||
i_adc_or (
|
||||
.rst(adc_rst),
|
||||
.clk(adc_clk_in),
|
||||
.div_clk(adc_div_clk),
|
||||
.loaden(1'b0),
|
||||
.phase(8'b0),
|
||||
.locked(1'b0),
|
||||
.data_s0(adc_or_s[3]),
|
||||
.data_s1(adc_or_s[2]),
|
||||
.data_s2(adc_or_s[1]),
|
||||
.data_s3(adc_or_s[0]),
|
||||
.data_s4(),
|
||||
.data_s5(),
|
||||
.data_s6(),
|
||||
.data_s7(),
|
||||
.data_in_p(adc_or_in_p),
|
||||
.data_in_n(adc_or_in_n),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_adc_dld[12]),
|
||||
.up_dwdata (up_adc_dwdata[64:60]),
|
||||
.up_drdata (up_adc_drdata[64:60]),
|
||||
.delay_clk(delay_clk),
|
||||
.delay_rst(delay_rst),
|
||||
.delay_locked(delay_locked));
|
||||
|
||||
// clock input buffers and MMCM_OR_BUFR_N
|
||||
ad_serdes_clk #(
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.CLKIN_DS_OR_SE_N (1),
|
||||
.MMCM_OR_BUFR_N (1),
|
||||
.MMCM_CLKIN_PERIOD (2),
|
||||
.MMCM_VCO_DIV (6),
|
||||
.MMCM_VCO_MUL (12),
|
||||
.MMCM_CLK0_DIV (2),
|
||||
.MMCM_CLK1_DIV (8),
|
||||
.SERDES_FACTOR(4))
|
||||
i_serdes_clk (
|
||||
.rst (mmcm_rst),
|
||||
.clk_in_p (adc_clk_in_p),
|
||||
.clk_in_n (adc_clk_in_n),
|
||||
.clk (adc_clk_in),
|
||||
.div_clk (adc_div_clk),
|
||||
.out_clk (),
|
||||
.loaden (),
|
||||
.phase (),
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn),
|
||||
.up_drp_sel (up_drp_sel),
|
||||
.up_drp_wr (up_drp_wr),
|
||||
.up_drp_addr (up_drp_addr),
|
||||
.up_drp_wdata (up_drp_wdata),
|
||||
.up_drp_rdata (up_drp_rdata),
|
||||
.up_drp_ready (up_drp_ready),
|
||||
.up_drp_locked (up_drp_locked));
|
||||
|
||||
// adc over range
|
||||
assign adc_or = adc_or_s[0] | adc_or_s[1] | adc_or_s[2] | adc_or_s[3];
|
||||
|
||||
// adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up
|
||||
always @(posedge adc_div_clk) begin
|
||||
if(adc_rst == 1'b1) begin
|
||||
adc_status_m1 <= 1'b0;
|
||||
adc_status <= 1'b0;
|
||||
end else begin
|
||||
adc_status_m1 <= up_drp_locked & delay_locked;
|
||||
adc_status <= adc_status_m1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,45 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad9434
|
||||
adi_ip_files axi_ad9434 [list \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \
|
||||
"$ad_hdl_dir/library/common/ad_datafmt.v" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
"$ad_hdl_dir/library/common/ad_pnmon.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"axi_ad9434_if.v" \
|
||||
"axi_ad9434_pnmon.v" \
|
||||
"axi_ad9434_core.v" \
|
||||
"axi_ad9434_constr.xdc" \
|
||||
"axi_ad9434.v" ]
|
||||
|
||||
adi_ip_properties axi_ad9434
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad9434 "bd/bd.tcl"
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,192 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module axi_ad9434_pnmon (
|
||||
|
||||
// adc interface
|
||||
input adc_clk,
|
||||
input [47:0] adc_data,
|
||||
|
||||
// pn interface
|
||||
input [ 3:0] adc_pnseq_sel,
|
||||
output adc_pn_err,
|
||||
output adc_pn_oos);
|
||||
|
||||
// internal registers
|
||||
reg [47:0] adc_pn_data_pn = 'd0;
|
||||
|
||||
// internal signals
|
||||
wire [47:0] adc_pn_data_pn_s;
|
||||
|
||||
wire [47:0] adc_data_inv_s;
|
||||
|
||||
// prbs pn9 function
|
||||
function [47:0] pn9;
|
||||
input [47:0] din;
|
||||
reg [47:0] dout;
|
||||
begin
|
||||
dout[47] = din[8] ^ din[4];
|
||||
dout[46] = din[7] ^ din[3];
|
||||
dout[45] = din[6] ^ din[2];
|
||||
dout[44] = din[5] ^ din[1];
|
||||
dout[43] = din[4] ^ din[0];
|
||||
dout[42] = din[3] ^ din[8] ^ din[4];
|
||||
dout[41] = din[2] ^ din[7] ^ din[3];
|
||||
dout[40] = din[1] ^ din[6] ^ din[2];
|
||||
dout[39] = din[0] ^ din[5] ^ din[1];
|
||||
dout[38] = din[8] ^ din[0];
|
||||
dout[37] = din[7] ^ din[8] ^ din[4];
|
||||
dout[36] = din[6] ^ din[7] ^ din[3];
|
||||
dout[35] = din[5] ^ din[6] ^ din[2];
|
||||
dout[34] = din[4] ^ din[5] ^ din[1];
|
||||
dout[33] = din[3] ^ din[4] ^ din[0];
|
||||
dout[32] = din[2] ^ din[3] ^ din[8] ^ din[4];
|
||||
dout[31] = din[1] ^ din[2] ^ din[7] ^ din[3];
|
||||
dout[30] = din[0] ^ din[1] ^ din[6] ^ din[2];
|
||||
dout[29] = din[8] ^ din[0] ^ din[4] ^ din[5] ^ din[1];
|
||||
dout[28] = din[7] ^ din[8] ^ din[3] ^ din[0];
|
||||
dout[27] = din[6] ^ din[7] ^ din[2] ^ din[8] ^ din[4];
|
||||
dout[26] = din[5] ^ din[6] ^ din[1] ^ din[7] ^ din[3];
|
||||
dout[25] = din[4] ^ din[5] ^ din[0] ^ din[6] ^ din[2];
|
||||
dout[24] = din[3] ^ din[8] ^ din[5] ^ din[1];
|
||||
dout[23] = din[2] ^ din[4] ^ din[7] ^ din[0];
|
||||
dout[22] = din[1] ^ din[3] ^ din[6] ^ din[8] ^ din[4];
|
||||
dout[21] = din[0] ^ din[2] ^ din[5] ^ din[7] ^ din[3];
|
||||
dout[20] = din[8] ^ din[1] ^ din[6] ^ din[2];
|
||||
dout[19] = din[7] ^ din[0] ^ din[5] ^ din[1];
|
||||
dout[18] = din[6] ^ din[8] ^ din[0];
|
||||
dout[17] = din[5] ^ din[7] ^ din[8] ^ din[4];
|
||||
dout[16] = din[4] ^ din[6] ^ din[7] ^ din[3];
|
||||
dout[15] = din[3] ^ din[5] ^ din[6] ^ din[2];
|
||||
dout[14] = din[2] ^ din[4] ^ din[5] ^ din[1];
|
||||
dout[13] = din[1] ^ din[3] ^ din[4] ^ din[0];
|
||||
dout[12] = din[0] ^ din[2] ^ din[3] ^ din[8] ^ din[4];
|
||||
dout[11] = din[8] ^ din[1] ^ din[2] ^ din[4] ^ din[7] ^ din[3];
|
||||
dout[10] = din[7] ^ din[0] ^ din[1] ^ din[3] ^ din[6] ^ din[2];
|
||||
dout[9] = din[6] ^ din[8] ^ din[0] ^ din[2] ^ din[4] ^ din[5] ^ din[1];
|
||||
dout[8] = din[5] ^ din[7] ^ din[8] ^ din[1] ^ din[3] ^ din[0];
|
||||
dout[7] = din[6] ^ din[7] ^ din[0] ^ din[2] ^ din[8];
|
||||
dout[6] = din[5] ^ din[6] ^ din[8] ^ din[1] ^ din[4] ^ din[7];
|
||||
dout[5] = din[4] ^ din[5] ^ din[7] ^ din[0] ^ din[3] ^ din[6];
|
||||
dout[4] = din[3] ^ din[6] ^ din[8] ^ din[2] ^ din[5];
|
||||
dout[3] = din[2] ^ din[4] ^ din[5] ^ din[7] ^ din[1];
|
||||
dout[2] = din[1] ^ din[4] ^ din[3] ^ din[6] ^ din[0];
|
||||
dout[1] = din[0] ^ din[3] ^ din[2] ^ din[5] ^ din[8] ^ din[4];
|
||||
dout[0] = din[8] ^ din[2] ^ din[1] ^ din[7] ^ din[3];
|
||||
pn9 = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// prbs pn23 function
|
||||
function [47:0] pn23;
|
||||
input [47:0] din;
|
||||
reg [47:0] dout;
|
||||
begin
|
||||
dout[47] = din[22] ^ din[17];
|
||||
dout[46] = din[21] ^ din[16];
|
||||
dout[45] = din[20] ^ din[15];
|
||||
dout[44] = din[19] ^ din[14];
|
||||
dout[43] = din[18] ^ din[13];
|
||||
dout[42] = din[17] ^ din[12];
|
||||
dout[41] = din[16] ^ din[11];
|
||||
dout[40] = din[15] ^ din[10];
|
||||
dout[39] = din[14] ^ din[9];
|
||||
dout[38] = din[13] ^ din[8];
|
||||
dout[37] = din[12] ^ din[7];
|
||||
dout[36] = din[11] ^ din[6];
|
||||
dout[35] = din[10] ^ din[5];
|
||||
dout[34] = din[9] ^ din[4];
|
||||
dout[33] = din[8] ^ din[3];
|
||||
dout[32] = din[7] ^ din[2];
|
||||
dout[31] = din[6] ^ din[1];
|
||||
dout[30] = din[5] ^ din[0];
|
||||
dout[29] = din[4] ^ din[22] ^ din[17];
|
||||
dout[28] = din[3] ^ din[21] ^ din[16];
|
||||
dout[27] = din[2] ^ din[20] ^ din[15];
|
||||
dout[26] = din[1] ^ din[19] ^ din[14];
|
||||
dout[25] = din[0] ^ din[18] ^ din[13];
|
||||
dout[24] = din[22] ^ din[12];
|
||||
dout[23] = din[21] ^ din[11];
|
||||
dout[22] = din[20] ^ din[10];
|
||||
dout[21] = din[19] ^ din[9];
|
||||
dout[20] = din[18] ^ din[8];
|
||||
dout[19] = din[17] ^ din[7];
|
||||
dout[18] = din[16] ^ din[6];
|
||||
dout[17] = din[15] ^ din[5];
|
||||
dout[16] = din[14] ^ din[4];
|
||||
dout[15] = din[13] ^ din[3];
|
||||
dout[14] = din[12] ^ din[2];
|
||||
dout[13] = din[11] ^ din[1];
|
||||
dout[12] = din[10] ^ din[0];
|
||||
dout[11] = din[9] ^ din[22] ^ din[17];
|
||||
dout[10] = din[8] ^ din[21] ^ din[16];
|
||||
dout[9] = din[7] ^ din[20] ^ din[15];
|
||||
dout[8] = din[6] ^ din[19] ^ din[14];
|
||||
dout[7] = din[5] ^ din[18] ^ din[13];
|
||||
dout[6] = din[4] ^ din[17] ^ din[12];
|
||||
dout[5] = din[3] ^ din[16] ^ din[11];
|
||||
dout[4] = din[2] ^ din[15] ^ din[10];
|
||||
dout[3] = din[1] ^ din[14] ^ din[9];
|
||||
dout[2] = din[0] ^ din[13] ^ din[8];
|
||||
dout[1] = din[22] ^ din[12] ^ din[17] ^ din[7];
|
||||
dout[0] = din[21] ^ din[11] ^ din[16] ^ din[6];
|
||||
pn23 = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// pn sequence selection
|
||||
assign adc_data_inv_s = {adc_data[11:0], adc_data[23:12], adc_data[35:24], adc_data[47:36]};
|
||||
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_data_inv_s : adc_pn_data_pn;
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if(adc_pnseq_sel == 4'b0) begin
|
||||
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
|
||||
end else begin
|
||||
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
|
||||
end
|
||||
end
|
||||
|
||||
// pn oos & pn err
|
||||
ad_pnmon #(.DATA_WIDTH(48)) i_pnmon (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_valid_in (1'b1),
|
||||
.adc_data_in (adc_data_inv_s),
|
||||
.adc_data_pn (adc_pn_data_pn),
|
||||
.adc_pn_oos (adc_pn_oos),
|
||||
.adc_pn_err (adc_pn_err));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Dec 9 15:10:20 2021
|
||||
# Process ID: 4188
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434
|
||||
# Command line: vivado -mode batch -source axi_ad9434_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9434/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_ad9434_ip.tcl
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,103 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
|
||||
# Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
|
||||
# Procedure called to validate IO_DELAY_GROUP
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user