josh/vivado-202304
Archived
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

initial commit

Browse Source
This commit is contained in:
josh
2023-03-18 15:35:53 +08:00
commit 5965eba577
3222 changed files with 4025781 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
adi_library/axi_ad9625/Makefile
+30
View File
@@ -0,0 +1,30 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_ad9625
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_mem.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9625.v
GENERIC_DEPS += axi_ad9625_channel.v
GENERIC_DEPS += axi_ad9625_if.v
GENERIC_DEPS += axi_ad9625_pnmon.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9625_ip.tcl
include ../scripts/library.mk
adi_library/axi_ad9625/axi_ad9625.cache/wt/project.wpc
+3
View File
@@ -0,0 +1,3 @@
version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:
adi_library/axi_ad9625/axi_ad9625.hw/axi_ad9625.lpr
+6
View File
@@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
adi_library/axi_ad9625/axi_ad9625.v
+276
View File
@@ -0,0 +1,276 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9625 #(
parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DELAY_REFCLK_FREQUENCY = 200) (
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk,
input [ 3:0] rx_sof,
input rx_valid,
input [255:0] rx_data,
output rx_ready,
// dma interface
output adc_clk,
output adc_rst,
output adc_valid,
output adc_enable,
output [255:0] adc_data,
input adc_dovf,
output [ 15:0] adc_sref,
input [ 3:0] adc_raddr_in,
output [ 3:0] adc_raddr_out,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 15:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 15:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [ 31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal registers
reg [ 31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire up_rstn;
wire up_clk;
wire [191:0] adc_data_s;
wire adc_or_s;
wire adc_status_s;
wire adc_sref_sync_s;
wire up_adc_pn_err_s;
wire up_adc_pn_oos_s;
wire up_adc_or_s;
wire [ 31:0] up_rdata_s[0:1];
wire up_rack_s[0:1];
wire up_wack_s[0:1];
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// defaults
assign rx_ready = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_rack <= up_rack_s[0] | up_rack_s[1] ;
up_wack <= up_wack_s[0] | up_wack_s[1] ;
end
end
// main (device interface)
assign adc_valid = 1'b1;
axi_ad9625_if #(
.ID (ID))
i_if (
.rx_clk (rx_clk),
.rx_sof (rx_sof),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_status (adc_status_s),
.adc_sref (adc_sref),
.adc_sref_sync (adc_sref_sync_s),
.adc_raddr_in (adc_raddr_in),
.adc_raddr_out (adc_raddr_out));
// channel
axi_ad9625_channel i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_dfmt_data (adc_data),
.adc_enable (adc_enable),
.up_adc_pn_err (up_adc_pn_err_s),
.up_adc_pn_oos (up_adc_pn_oos_s),
.up_adc_or (up_adc_or_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// common processor control
up_adc_common #(
.ID(ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG(0),
.COMMON_ID(6'h0),
.DRP_DISABLE(1),
.USERPORTS_DISABLE(1),
.GPIO_DISABLE(1),
.START_CODE_DISABLE(1))
i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_clk_ratio (32'd16),
.adc_start_code (),
.adc_sync (),
.adc_sref_sync (adc_sref_sync_s),
.up_pps_rcounter(32'h0),
.up_pps_status(1'b0),
.up_pps_irq_mask(),
.up_adc_ce (),
.up_status_pn_err (up_adc_pn_err_s),
.up_status_pn_oos (up_adc_pn_oos_s),
.up_status_or (up_adc_or_s),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd1),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_ad9625/axi_ad9625.xpr
+505
View File
@@ -0,0 +1,505 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625/axi_ad9625.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="7ba3491e6d014c15a101b294937f389f"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../common/ad_datafmt.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/ad_mem.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/ad_pnmon.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/ad_rst.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/ad_xcvr_rx_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_ad9625_channel.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_ad9625_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_ad9625_pnmon.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_adc_channel.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_adc_common.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_axi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_clock_mon.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_xfer_cntrl.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_xfer_status.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_ad9625.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<File Path="$PPRDIR/bd/bd.tcl">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_ad9625"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../xilinx/common/up_xfer_cntrl_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../xilinx/common/ad_rst_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../xilinx/common/up_xfer_status_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../xilinx/common/up_clock_mon_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters>
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
</Parameters>
</BootPmcSettings>
</Project>
adi_library/axi_ad9625/axi_ad9625_channel.v
+158
View File
@@ -0,0 +1,158 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9625_channel (
// adc interface
input adc_clk,
input adc_rst,
input [191:0] adc_data,
input adc_or,
// channel interface
output [255:0] adc_dfmt_data,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output [ 31:0] up_rdata,
output up_rack);
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire adc_dfmt_enable_s;
wire adc_dfmt_type_s;
wire adc_dfmt_se_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
axi_ad9625_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
genvar n;
generate
for (n = 0; n < 16; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(12)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*12+11:n*12]),
.valid_out (),
.data_out (adc_dfmt_data[n*16+15:n*16]),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
up_adc_channel #(
.COMMON_ID(6'h1),
.CHANNEL_ID(0),
.USERPORTS_DISABLE(1),
.DATAFORMAT_DISABLE(0),
.DCFILTER_DISABLE(1),
.IQCORRECTION_DISABLE(1))
i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_ad9625/axi_ad9625_if.v
+238
View File
@@ -0,0 +1,238 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9625_if #(
parameter ID = 0) (
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk,
input [ 3:0] rx_sof,
input [255:0] rx_data,
// adc data output
output adc_clk,
input adc_rst,
output [191:0] adc_data,
output adc_or,
output adc_status,
output [ 15:0] adc_sref,
input adc_sref_sync,
input [ 3:0] adc_raddr_in,
output [ 3:0] adc_raddr_out);
// internal registers
reg [191:0] adc_data_int = 'd0;
reg adc_status_int = 'd0;
reg [ 15:0] adc_sref_int = 'd0;
reg [191:0] adc_data_cur = 'd0;
reg [191:0] adc_data_prv = 'd0;
reg [ 3:0] adc_waddr = 'd0;
reg [191:0] adc_wdata = 'd0;
reg [ 3:0] adc_raddr = 'd0;
// internal signals
wire [191:0] adc_rdata_s;
wire [ 3:0] adc_raddr_s;
wire [ 15:0] adc_sref_s;
wire [191:0] adc_data_s;
wire [ 15:0] adc_data_s15_s;
wire [ 15:0] adc_data_s14_s;
wire [ 15:0] adc_data_s13_s;
wire [ 15:0] adc_data_s12_s;
wire [ 15:0] adc_data_s11_s;
wire [ 15:0] adc_data_s10_s;
wire [ 15:0] adc_data_s09_s;
wire [ 15:0] adc_data_s08_s;
wire [ 15:0] adc_data_s07_s;
wire [ 15:0] adc_data_s06_s;
wire [ 15:0] adc_data_s05_s;
wire [ 15:0] adc_data_s04_s;
wire [ 15:0] adc_data_s03_s;
wire [ 15:0] adc_data_s02_s;
wire [ 15:0] adc_data_s01_s;
wire [ 15:0] adc_data_s00_s;
wire [ 31:0] rx_data0_s;
wire [ 31:0] rx_data1_s;
wire [ 31:0] rx_data2_s;
wire [ 31:0] rx_data3_s;
wire [ 31:0] rx_data4_s;
wire [ 31:0] rx_data5_s;
wire [ 31:0] rx_data6_s;
wire [ 31:0] rx_data7_s;
wire [255:0] rx_data_s;
// nothing much to do on clock & over-range
assign adc_clk = rx_clk;
assign adc_or = 1'b0;
// synchronization mode, multiple instances
assign adc_data = adc_data_int;
assign adc_status = adc_status_int;
assign adc_sref = adc_sref_int;
assign adc_raddr_out = adc_raddr;
assign adc_raddr_s = (ID == 0) ? adc_raddr : adc_raddr_in;
always @(posedge rx_clk) begin
if (adc_sref_sync == 1'b1) begin
adc_data_int <= adc_rdata_s;
end else begin
adc_data_int <= adc_data_s;
end
if (adc_sref_s != 16'd0) begin
adc_sref_int <= adc_sref_s;
end
adc_data_cur <= adc_data_s;
adc_data_prv <= adc_data_cur;
if (adc_sref_s == 16'd0) begin
adc_waddr <= adc_waddr + 1'b1;
adc_raddr <= adc_raddr + 1'b1;
end else begin
adc_waddr <= 4'h0;
adc_raddr <= 4'h8;
end
case (adc_sref_int)
16'h8000: adc_wdata <= {adc_data_cur[179:0], adc_data_prv[191:180]};
16'h4000: adc_wdata <= {adc_data_cur[167:0], adc_data_prv[191:168]};
16'h2000: adc_wdata <= {adc_data_cur[155:0], adc_data_prv[191:156]};
16'h1000: adc_wdata <= {adc_data_cur[143:0], adc_data_prv[191:144]};
16'h0800: adc_wdata <= {adc_data_cur[131:0], adc_data_prv[191:132]};
16'h0400: adc_wdata <= {adc_data_cur[119:0], adc_data_prv[191:120]};
16'h0200: adc_wdata <= {adc_data_cur[107:0], adc_data_prv[191:108]};
16'h0100: adc_wdata <= {adc_data_cur[ 95:0], adc_data_prv[191: 96]};
16'h0080: adc_wdata <= {adc_data_cur[ 83:0], adc_data_prv[191: 84]};
16'h0040: adc_wdata <= {adc_data_cur[ 71:0], adc_data_prv[191: 72]};
16'h0020: adc_wdata <= {adc_data_cur[ 59:0], adc_data_prv[191: 60]};
16'h0010: adc_wdata <= {adc_data_cur[ 47:0], adc_data_prv[191: 48]};
16'h0008: adc_wdata <= {adc_data_cur[ 35:0], adc_data_prv[191: 36]};
16'h0004: adc_wdata <= {adc_data_cur[ 23:0], adc_data_prv[191: 24]};
16'h0002: adc_wdata <= {adc_data_cur[ 11:0], adc_data_prv[191: 12]};
default: adc_wdata <= adc_data_prv;
endcase
end
// samples only
assign adc_sref_s = {adc_data_s15_s[14], adc_data_s14_s[14],
adc_data_s13_s[14], adc_data_s12_s[14], adc_data_s11_s[14],
adc_data_s10_s[14], adc_data_s09_s[14], adc_data_s08_s[14],
adc_data_s07_s[14], adc_data_s06_s[14], adc_data_s05_s[14],
adc_data_s04_s[14], adc_data_s03_s[14], adc_data_s02_s[14],
adc_data_s01_s[14], adc_data_s00_s[14]};
assign adc_data_s = {adc_data_s15_s[11:0], adc_data_s14_s[11:0],
adc_data_s13_s[11:0], adc_data_s12_s[11:0], adc_data_s11_s[11:0],
adc_data_s10_s[11:0], adc_data_s09_s[11:0], adc_data_s08_s[11:0],
adc_data_s07_s[11:0], adc_data_s06_s[11:0], adc_data_s05_s[11:0],
adc_data_s04_s[11:0], adc_data_s03_s[11:0], adc_data_s02_s[11:0],
adc_data_s01_s[11:0], adc_data_s00_s[11:0]};
// data is received across multiple lanes (reconstruct samples)
assign adc_data_s15_s = {rx_data7_s[27:24], rx_data6_s[31:24], rx_data7_s[31:28]};
assign adc_data_s14_s = {rx_data5_s[27:24], rx_data4_s[31:24], rx_data5_s[31:28]};
assign adc_data_s13_s = {rx_data3_s[27:24], rx_data2_s[31:24], rx_data3_s[31:28]};
assign adc_data_s12_s = {rx_data1_s[27:24], rx_data0_s[31:24], rx_data1_s[31:28]};
assign adc_data_s11_s = {rx_data7_s[19:16], rx_data6_s[23:16], rx_data7_s[23:20]};
assign adc_data_s10_s = {rx_data5_s[19:16], rx_data4_s[23:16], rx_data5_s[23:20]};
assign adc_data_s09_s = {rx_data3_s[19:16], rx_data2_s[23:16], rx_data3_s[23:20]};
assign adc_data_s08_s = {rx_data1_s[19:16], rx_data0_s[23:16], rx_data1_s[23:20]};
assign adc_data_s07_s = {rx_data7_s[11: 8], rx_data6_s[15: 8], rx_data7_s[15:12]};
assign adc_data_s06_s = {rx_data5_s[11: 8], rx_data4_s[15: 8], rx_data5_s[15:12]};
assign adc_data_s05_s = {rx_data3_s[11: 8], rx_data2_s[15: 8], rx_data3_s[15:12]};
assign adc_data_s04_s = {rx_data1_s[11: 8], rx_data0_s[15: 8], rx_data1_s[15:12]};
assign adc_data_s03_s = {rx_data7_s[ 3: 0], rx_data6_s[ 7: 0], rx_data7_s[ 7: 4]};
assign adc_data_s02_s = {rx_data5_s[ 3: 0], rx_data4_s[ 7: 0], rx_data5_s[ 7: 4]};
assign adc_data_s01_s = {rx_data3_s[ 3: 0], rx_data2_s[ 7: 0], rx_data3_s[ 7: 4]};
assign adc_data_s00_s = {rx_data1_s[ 3: 0], rx_data0_s[ 7: 0], rx_data1_s[ 7: 4]};
assign rx_data0_s = rx_data_s[ 31: 0];
assign rx_data1_s = rx_data_s[ 63: 32];
assign rx_data2_s = rx_data_s[ 95: 64];
assign rx_data3_s = rx_data_s[127: 96];
assign rx_data4_s = rx_data_s[159:128];
assign rx_data5_s = rx_data_s[191:160];
assign rx_data6_s = rx_data_s[223:192];
assign rx_data7_s = rx_data_s[255:224];
// status
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status_int <= 1'b0;
end else begin
adc_status_int <= 1'b1;
end
end
// alignment fifo
ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(192)) i_mem (
.clka (rx_clk),
.wea (1'b1),
.addra (adc_waddr),
.dina (adc_wdata),
.clkb (rx_clk),
.reb (1'b1),
.addrb (adc_raddr_s),
.doutb (adc_rdata_s));
// frame-alignment
genvar n;
generate
for (n = 0; n < 8; n = n + 1) begin: g_xcvr_if
ad_xcvr_rx_if i_xcvr_if (
.rx_clk (rx_clk),
.rx_ip_sof (rx_sof),
.rx_ip_data (rx_data[((n*32)+31):(n*32)]),
.rx_sof (),
.rx_data (rx_data_s[((n*32)+31):(n*32)]));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_ad9625/axi_ad9625_ip.log
+2058
View File
File diff suppressed because it is too large Load Diff
adi_library/axi_ad9625/axi_ad9625_ip.tcl
+46
View File
@@ -0,0 +1,46 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_ad9625
adi_ip_files axi_ad9625 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_mem.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"axi_ad9625_pnmon.v" \
"axi_ad9625_channel.v" \
"axi_ad9625_if.v" \
"axi_ad9625.v" ]
adi_ip_properties axi_ad9625
adi_init_bd_tcl
adi_ip_bd axi_ad9625 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/axi_ad9625/axi_ad9625_pnmon.v
+509
View File
@@ -0,0 +1,509 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9625_pnmon (
// adc interface
input adc_clk,
input [191:0] adc_data,
// pn out of sync and error
output adc_pn_oos,
output adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel);
// internal registers
reg [191:0] adc_pn_data_in = 'd0;
reg [191:0] adc_pn_data_pn = 'd0;
// internal signals
wire [191:0] adc_pn_data_pn_s;
// PN23 function
function [191:0] pn23;
input [191:0] din;
reg [191:0] dout;
begin
dout[191] = din[22] ^ din[17];
dout[190] = din[21] ^ din[16];
dout[189] = din[20] ^ din[15];
dout[188] = din[19] ^ din[14];
dout[187] = din[18] ^ din[13];
dout[186] = din[17] ^ din[12];
dout[185] = din[16] ^ din[11];
dout[184] = din[15] ^ din[10];
dout[183] = din[14] ^ din[ 9];
dout[182] = din[13] ^ din[ 8];
dout[181] = din[12] ^ din[ 7];
dout[180] = din[11] ^ din[ 6];
dout[179] = din[10] ^ din[ 5];
dout[178] = din[ 9] ^ din[ 4];
dout[177] = din[ 8] ^ din[ 3];
dout[176] = din[ 7] ^ din[ 2];
dout[175] = din[ 6] ^ din[ 1];
dout[174] = din[ 5] ^ din[ 0];
dout[173] = din[ 4] ^ din[22] ^ din[17];
dout[172] = din[ 3] ^ din[21] ^ din[16];
dout[171] = din[ 2] ^ din[20] ^ din[15];
dout[170] = din[ 1] ^ din[19] ^ din[14];
dout[169] = din[ 0] ^ din[18] ^ din[13];
dout[168] = din[22] ^ din[12];
dout[167] = din[21] ^ din[11];
dout[166] = din[20] ^ din[10];
dout[165] = din[19] ^ din[ 9];
dout[164] = din[18] ^ din[ 8];
dout[163] = din[17] ^ din[ 7];
dout[162] = din[16] ^ din[ 6];
dout[161] = din[15] ^ din[ 5];
dout[160] = din[14] ^ din[ 4];
dout[159] = din[13] ^ din[ 3];
dout[158] = din[12] ^ din[ 2];
dout[157] = din[11] ^ din[ 1];
dout[156] = din[10] ^ din[ 0];
dout[155] = din[ 9] ^ din[22] ^ din[17];
dout[154] = din[ 8] ^ din[21] ^ din[16];
dout[153] = din[ 7] ^ din[20] ^ din[15];
dout[152] = din[ 6] ^ din[19] ^ din[14];
dout[151] = din[ 5] ^ din[18] ^ din[13];
dout[150] = din[ 4] ^ din[17] ^ din[12];
dout[149] = din[ 3] ^ din[16] ^ din[11];
dout[148] = din[ 2] ^ din[15] ^ din[10];
dout[147] = din[ 1] ^ din[14] ^ din[ 9];
dout[146] = din[ 0] ^ din[13] ^ din[ 8];
dout[145] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[144] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
dout[143] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
dout[142] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
dout[141] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
dout[140] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
dout[139] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
dout[138] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
dout[137] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[17];
dout[136] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[16];
dout[135] = din[12] ^ din[ 2] ^ din[ 7] ^ din[20] ^ din[15];
dout[134] = din[11] ^ din[ 1] ^ din[ 6] ^ din[19] ^ din[14];
dout[133] = din[10] ^ din[ 0] ^ din[ 5] ^ din[18] ^ din[13];
dout[132] = din[ 9] ^ din[22] ^ din[ 4] ^ din[12];
dout[131] = din[ 8] ^ din[21] ^ din[ 3] ^ din[11];
dout[130] = din[ 7] ^ din[20] ^ din[ 2] ^ din[10];
dout[129] = din[ 6] ^ din[19] ^ din[ 1] ^ din[ 9];
dout[128] = din[ 5] ^ din[18] ^ din[ 0] ^ din[ 8];
dout[127] = din[ 4] ^ din[22] ^ din[ 7];
dout[126] = din[ 3] ^ din[21] ^ din[ 6];
dout[125] = din[ 2] ^ din[20] ^ din[ 5];
dout[124] = din[ 1] ^ din[19] ^ din[ 4];
dout[123] = din[ 0] ^ din[18] ^ din[ 3];
dout[122] = din[22] ^ din[ 2];
dout[121] = din[21] ^ din[ 1];
dout[120] = din[20] ^ din[ 0];
dout[119] = din[19] ^ din[22] ^ din[17];
dout[118] = din[18] ^ din[21] ^ din[16];
dout[117] = din[17] ^ din[20] ^ din[15];
dout[116] = din[16] ^ din[19] ^ din[14];
dout[115] = din[15] ^ din[18] ^ din[13];
dout[114] = din[14] ^ din[17] ^ din[12];
dout[113] = din[13] ^ din[16] ^ din[11];
dout[112] = din[12] ^ din[15] ^ din[10];
dout[111] = din[11] ^ din[14] ^ din[ 9];
dout[110] = din[10] ^ din[13] ^ din[ 8];
dout[109] = din[ 9] ^ din[12] ^ din[ 7];
dout[108] = din[ 8] ^ din[11] ^ din[ 6];
dout[107] = din[ 7] ^ din[10] ^ din[ 5];
dout[106] = din[ 6] ^ din[ 9] ^ din[ 4];
dout[105] = din[ 5] ^ din[ 8] ^ din[ 3];
dout[104] = din[ 4] ^ din[ 7] ^ din[ 2];
dout[103] = din[ 3] ^ din[ 6] ^ din[ 1];
dout[102] = din[ 2] ^ din[ 5] ^ din[ 0];
dout[101] = din[ 1] ^ din[ 4] ^ din[22] ^ din[17];
dout[100] = din[ 0] ^ din[ 3] ^ din[21] ^ din[16];
dout[ 99] = din[22] ^ din[ 2] ^ din[17] ^ din[20] ^ din[15];
dout[ 98] = din[21] ^ din[ 1] ^ din[16] ^ din[19] ^ din[14];
dout[ 97] = din[20] ^ din[ 0] ^ din[15] ^ din[18] ^ din[13];
dout[ 96] = din[19] ^ din[22] ^ din[14] ^ din[12];
dout[ 95] = din[18] ^ din[21] ^ din[13] ^ din[11];
dout[ 94] = din[17] ^ din[20] ^ din[12] ^ din[10];
dout[ 93] = din[16] ^ din[19] ^ din[11] ^ din[ 9];
dout[ 92] = din[15] ^ din[18] ^ din[10] ^ din[ 8];
dout[ 91] = din[14] ^ din[17] ^ din[ 9] ^ din[ 7];
dout[ 90] = din[13] ^ din[16] ^ din[ 8] ^ din[ 6];
dout[ 89] = din[12] ^ din[15] ^ din[ 7] ^ din[ 5];
dout[ 88] = din[11] ^ din[14] ^ din[ 6] ^ din[ 4];
dout[ 87] = din[10] ^ din[13] ^ din[ 5] ^ din[ 3];
dout[ 86] = din[ 9] ^ din[12] ^ din[ 4] ^ din[ 2];
dout[ 85] = din[ 8] ^ din[11] ^ din[ 3] ^ din[ 1];
dout[ 84] = din[ 7] ^ din[10] ^ din[ 2] ^ din[ 0];
dout[ 83] = din[ 6] ^ din[ 9] ^ din[ 1] ^ din[22] ^ din[17];
dout[ 82] = din[ 5] ^ din[ 8] ^ din[ 0] ^ din[21] ^ din[16];
dout[ 81] = din[ 4] ^ din[ 7] ^ din[22] ^ din[17] ^ din[20] ^ din[15];
dout[ 80] = din[ 3] ^ din[ 6] ^ din[21] ^ din[16] ^ din[19] ^ din[14];
dout[ 79] = din[ 2] ^ din[ 5] ^ din[20] ^ din[15] ^ din[18] ^ din[13];
dout[ 78] = din[ 1] ^ din[ 4] ^ din[17] ^ din[19] ^ din[14] ^ din[12];
dout[ 77] = din[ 0] ^ din[ 3] ^ din[16] ^ din[18] ^ din[13] ^ din[11];
dout[ 76] = din[22] ^ din[ 2] ^ din[15] ^ din[12] ^ din[10];
dout[ 75] = din[21] ^ din[ 1] ^ din[14] ^ din[11] ^ din[ 9];
dout[ 74] = din[20] ^ din[ 0] ^ din[13] ^ din[10] ^ din[ 8];
dout[ 73] = din[19] ^ din[22] ^ din[12] ^ din[17] ^ din[ 9] ^ din[ 7];
dout[ 72] = din[18] ^ din[21] ^ din[11] ^ din[16] ^ din[ 8] ^ din[ 6];
dout[ 71] = din[17] ^ din[20] ^ din[10] ^ din[15] ^ din[ 7] ^ din[ 5];
dout[ 70] = din[16] ^ din[19] ^ din[ 9] ^ din[14] ^ din[ 6] ^ din[ 4];
dout[ 69] = din[15] ^ din[18] ^ din[ 8] ^ din[13] ^ din[ 5] ^ din[ 3];
dout[ 68] = din[14] ^ din[17] ^ din[ 7] ^ din[12] ^ din[ 4] ^ din[ 2];
dout[ 67] = din[13] ^ din[16] ^ din[ 6] ^ din[11] ^ din[ 3] ^ din[ 1];
dout[ 66] = din[12] ^ din[15] ^ din[ 5] ^ din[10] ^ din[ 2] ^ din[ 0];
dout[ 65] = din[11] ^ din[14] ^ din[ 4] ^ din[ 9] ^ din[ 1] ^ din[22] ^ din[17];
dout[ 64] = din[10] ^ din[13] ^ din[ 3] ^ din[ 8] ^ din[ 0] ^ din[21] ^ din[16];
dout[ 63] = din[ 9] ^ din[12] ^ din[ 2] ^ din[ 7] ^ din[22] ^ din[17] ^ din[20] ^ din[15];
dout[ 62] = din[ 8] ^ din[11] ^ din[ 1] ^ din[ 6] ^ din[21] ^ din[16] ^ din[19] ^ din[14];
dout[ 61] = din[ 7] ^ din[10] ^ din[ 0] ^ din[ 5] ^ din[20] ^ din[15] ^ din[18] ^ din[13];
dout[ 60] = din[ 6] ^ din[ 9] ^ din[22] ^ din[ 4] ^ din[19] ^ din[14] ^ din[12];
dout[ 59] = din[ 5] ^ din[ 8] ^ din[21] ^ din[ 3] ^ din[18] ^ din[13] ^ din[11];
dout[ 58] = din[ 4] ^ din[ 7] ^ din[17] ^ din[20] ^ din[ 2] ^ din[12] ^ din[10];
dout[ 57] = din[ 3] ^ din[ 6] ^ din[16] ^ din[19] ^ din[ 1] ^ din[11] ^ din[ 9];
dout[ 56] = din[ 2] ^ din[ 5] ^ din[15] ^ din[18] ^ din[ 0] ^ din[10] ^ din[ 8];
dout[ 55] = din[ 1] ^ din[ 4] ^ din[14] ^ din[22] ^ din[ 9] ^ din[ 7];
dout[ 54] = din[ 0] ^ din[ 3] ^ din[13] ^ din[21] ^ din[ 8] ^ din[ 6];
dout[ 53] = din[22] ^ din[ 2] ^ din[12] ^ din[17] ^ din[20] ^ din[ 7] ^ din[ 5];
dout[ 52] = din[21] ^ din[ 1] ^ din[11] ^ din[16] ^ din[19] ^ din[ 6] ^ din[ 4];
dout[ 51] = din[20] ^ din[ 0] ^ din[10] ^ din[15] ^ din[18] ^ din[ 5] ^ din[ 3];
dout[ 50] = din[19] ^ din[22] ^ din[ 9] ^ din[14] ^ din[ 4] ^ din[ 2];
dout[ 49] = din[18] ^ din[21] ^ din[ 8] ^ din[13] ^ din[ 3] ^ din[ 1];
dout[ 48] = din[17] ^ din[20] ^ din[ 7] ^ din[12] ^ din[ 2] ^ din[ 0];
dout[ 47] = din[16] ^ din[19] ^ din[ 6] ^ din[11] ^ din[ 1] ^ din[22] ^ din[17];
dout[ 46] = din[15] ^ din[18] ^ din[ 5] ^ din[10] ^ din[ 0] ^ din[21] ^ din[16];
dout[ 45] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[20] ^ din[15];
dout[ 44] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[19] ^ din[14];
dout[ 43] = din[12] ^ din[ 2] ^ din[ 7] ^ din[20] ^ din[18] ^ din[13];
dout[ 42] = din[11] ^ din[ 1] ^ din[17] ^ din[ 6] ^ din[19] ^ din[12];
dout[ 41] = din[10] ^ din[ 0] ^ din[16] ^ din[ 5] ^ din[18] ^ din[11];
dout[ 40] = din[ 9] ^ din[22] ^ din[15] ^ din[ 4] ^ din[10];
dout[ 39] = din[ 8] ^ din[21] ^ din[14] ^ din[ 3] ^ din[ 9];
dout[ 38] = din[ 7] ^ din[20] ^ din[13] ^ din[ 2] ^ din[ 8];
dout[ 37] = din[ 6] ^ din[19] ^ din[12] ^ din[ 1] ^ din[ 7];
dout[ 36] = din[ 5] ^ din[18] ^ din[11] ^ din[ 0] ^ din[ 6];
dout[ 35] = din[ 4] ^ din[10] ^ din[22] ^ din[ 5];
dout[ 34] = din[ 3] ^ din[ 9] ^ din[21] ^ din[ 4];
dout[ 33] = din[ 2] ^ din[ 8] ^ din[20] ^ din[ 3];
dout[ 32] = din[ 1] ^ din[ 7] ^ din[19] ^ din[ 2];
dout[ 31] = din[ 0] ^ din[ 6] ^ din[18] ^ din[ 1];
dout[ 30] = din[22] ^ din[ 5] ^ din[ 0];
dout[ 29] = din[21] ^ din[ 4] ^ din[22] ^ din[17];
dout[ 28] = din[20] ^ din[ 3] ^ din[21] ^ din[16];
dout[ 27] = din[19] ^ din[ 2] ^ din[20] ^ din[15];
dout[ 26] = din[18] ^ din[ 1] ^ din[19] ^ din[14];
dout[ 25] = din[17] ^ din[ 0] ^ din[18] ^ din[13];
dout[ 24] = din[16] ^ din[22] ^ din[12];
dout[ 23] = din[15] ^ din[21] ^ din[11];
dout[ 22] = din[14] ^ din[20] ^ din[10];
dout[ 21] = din[13] ^ din[19] ^ din[ 9];
dout[ 20] = din[12] ^ din[18] ^ din[ 8];
dout[ 19] = din[11] ^ din[17] ^ din[ 7];
dout[ 18] = din[10] ^ din[16] ^ din[ 6];
dout[ 17] = din[ 9] ^ din[15] ^ din[ 5];
dout[ 16] = din[ 8] ^ din[14] ^ din[ 4];
dout[ 15] = din[ 7] ^ din[13] ^ din[ 3];
dout[ 14] = din[ 6] ^ din[12] ^ din[ 2];
dout[ 13] = din[ 5] ^ din[11] ^ din[ 1];
dout[ 12] = din[ 4] ^ din[10] ^ din[ 0];
dout[ 11] = din[ 3] ^ din[ 9] ^ din[22] ^ din[17];
dout[ 10] = din[ 2] ^ din[ 8] ^ din[21] ^ din[16];
dout[ 9] = din[ 1] ^ din[ 7] ^ din[20] ^ din[15];
dout[ 8] = din[ 0] ^ din[ 6] ^ din[19] ^ din[14];
dout[ 7] = din[22] ^ din[ 5] ^ din[17] ^ din[18] ^ din[13];
dout[ 6] = din[21] ^ din[ 4] ^ din[17] ^ din[16] ^ din[12];
dout[ 5] = din[20] ^ din[ 3] ^ din[16] ^ din[15] ^ din[11];
dout[ 4] = din[19] ^ din[ 2] ^ din[15] ^ din[14] ^ din[10];
dout[ 3] = din[18] ^ din[ 1] ^ din[14] ^ din[13] ^ din[ 9];
dout[ 2] = din[17] ^ din[ 0] ^ din[13] ^ din[12] ^ din[ 8];
dout[ 1] = din[16] ^ din[22] ^ din[12] ^ din[11] ^ din[17] ^ din[ 7];
dout[ 0] = din[15] ^ din[21] ^ din[11] ^ din[10] ^ din[16] ^ din[ 6];
pn23 = dout;
end
endfunction
// PN9 function
function [191:0] pn9;
input [191:0] din;
reg [191:0] dout;
begin
dout[191] = din[ 8] ^ din[ 4];
dout[190] = din[ 7] ^ din[ 3];
dout[189] = din[ 6] ^ din[ 2];
dout[188] = din[ 5] ^ din[ 1];
dout[187] = din[ 4] ^ din[ 0];
dout[186] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[185] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[184] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[183] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[182] = din[ 8] ^ din[ 0];
dout[181] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[180] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[179] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[178] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[177] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[176] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[175] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[174] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[173] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[172] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[171] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[170] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[169] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[168] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[167] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[166] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[165] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[164] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[163] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[162] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[161] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[160] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
dout[159] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2];
dout[158] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[157] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0];
dout[156] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[155] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3];
dout[154] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[153] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[152] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0];
dout[151] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8];
dout[150] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7];
dout[149] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6];
dout[148] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5];
dout[147] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1];
dout[146] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0];
dout[145] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4];
dout[144] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[143] = din[ 7] ^ din[ 1] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[142] = din[ 6] ^ din[ 0] ^ din[ 8] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[141] = din[ 5] ^ din[ 8] ^ din[ 7] ^ din[ 3] ^ din[ 0];
dout[140] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8];
dout[139] = din[ 6] ^ din[ 5] ^ din[ 1] ^ din[ 7];
dout[138] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6];
dout[137] = din[ 3] ^ din[ 8] ^ din[ 5];
dout[136] = din[ 2] ^ din[ 4] ^ din[ 7];
dout[135] = din[ 1] ^ din[ 3] ^ din[ 6];
dout[134] = din[ 0] ^ din[ 2] ^ din[ 5];
dout[133] = din[ 8] ^ din[ 1];
dout[132] = din[ 7] ^ din[ 0];
dout[131] = din[ 6] ^ din[ 8] ^ din[ 4];
dout[130] = din[ 5] ^ din[ 7] ^ din[ 3];
dout[129] = din[ 4] ^ din[ 6] ^ din[ 2];
dout[128] = din[ 3] ^ din[ 5] ^ din[ 1];
dout[127] = din[ 2] ^ din[ 4] ^ din[ 0];
dout[126] = din[ 1] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[125] = din[ 0] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[124] = din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 6] ^ din[ 2];
dout[123] = din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[122] = din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 0];
dout[121] = din[ 5] ^ din[ 7] ^ din[ 1] ^ din[ 8] ^ din[ 4];
dout[120] = din[ 4] ^ din[ 6] ^ din[ 0] ^ din[ 7] ^ din[ 3];
dout[119] = din[ 3] ^ din[ 5] ^ din[ 8] ^ din[ 4] ^ din[ 6] ^ din[ 2];
dout[118] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[117] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 0];
dout[116] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 8] ^ din[ 4];
dout[115] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 0] ^ din[ 7] ^ din[ 3];
dout[114] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 8] ^ din[ 4] ^ din[ 6] ^ din[ 2];
dout[113] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[112] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 0];
dout[111] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 8];
dout[110] = din[ 5] ^ din[ 4] ^ din[ 6] ^ din[ 1] ^ din[ 0] ^ din[ 7];
dout[109] = din[ 3] ^ din[ 5] ^ din[ 0] ^ din[ 8] ^ din[ 6];
dout[108] = din[ 2] ^ din[ 8] ^ din[ 7] ^ din[ 5];
dout[107] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[ 6];
dout[106] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5];
dout[105] = din[ 8] ^ din[ 2] ^ din[ 5];
dout[104] = din[ 4] ^ din[ 7] ^ din[ 1];
dout[103] = din[ 3] ^ din[ 6] ^ din[ 0];
dout[102] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4];
dout[101] = din[ 4] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[100] = din[ 3] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 99] = din[ 2] ^ din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 1];
dout[ 98] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[ 3] ^ din[ 0];
dout[ 97] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[ 96] = din[ 8] ^ din[ 2] ^ din[ 5] ^ din[ 4] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 95] = din[ 4] ^ din[ 7] ^ din[ 1] ^ din[ 3] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 94] = din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 2] ^ din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 1];
dout[ 93] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 1] ^ din[ 7] ^ din[ 3] ^ din[ 0];
dout[ 92] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 8];
dout[ 91] = din[ 0] ^ din[ 6] ^ din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 1] ^ din[ 7];
dout[ 90] = din[ 8] ^ din[ 5] ^ din[ 7] ^ din[ 3] ^ din[ 0] ^ din[ 6];
dout[ 89] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8] ^ din[ 5];
dout[ 88] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1] ^ din[ 7];
dout[ 87] = din[ 5] ^ din[ 4] ^ din[ 3] ^ din[ 0] ^ din[ 6];
dout[ 86] = din[ 3] ^ din[ 2] ^ din[ 8] ^ din[ 5];
dout[ 85] = din[ 2] ^ din[ 4] ^ din[ 1] ^ din[ 7];
dout[ 84] = din[ 1] ^ din[ 3] ^ din[ 0] ^ din[ 6];
dout[ 83] = din[ 0] ^ din[ 2] ^ din[ 8] ^ din[ 4] ^ din[ 5];
dout[ 82] = din[ 8] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 81] = din[ 7] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 80] = din[ 6] ^ din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 1];
dout[ 79] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 3] ^ din[ 0];
dout[ 78] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 8];
dout[ 77] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 7];
dout[ 76] = din[ 4] ^ din[ 1] ^ din[ 0] ^ din[ 6];
dout[ 75] = din[ 3] ^ din[ 0] ^ din[ 8] ^ din[ 5] ^ din[ 4];
dout[ 74] = din[ 2] ^ din[ 8] ^ din[ 7] ^ din[ 3];
dout[ 73] = din[ 1] ^ din[ 7] ^ din[ 6] ^ din[ 2];
dout[ 72] = din[ 0] ^ din[ 6] ^ din[ 5] ^ din[ 1];
dout[ 71] = din[ 8] ^ din[ 5] ^ din[ 0];
dout[ 70] = din[ 7] ^ din[ 8];
dout[ 69] = din[ 6] ^ din[ 7];
dout[ 68] = din[ 5] ^ din[ 6];
dout[ 67] = din[ 4] ^ din[ 5];
dout[ 66] = din[ 3] ^ din[ 4];
dout[ 65] = din[ 2] ^ din[ 3];
dout[ 64] = din[ 1] ^ din[ 2];
dout[ 63] = din[ 0] ^ din[ 1];
dout[ 62] = din[ 8] ^ din[ 0] ^ din[ 4];
dout[ 61] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 4];
dout[ 60] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 3];
dout[ 59] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 2];
dout[ 58] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 1];
dout[ 57] = din[ 3] ^ din[ 8] ^ din[ 0];
dout[ 56] = din[ 2] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[ 55] = din[ 1] ^ din[ 6] ^ din[ 7] ^ din[ 3];
dout[ 54] = din[ 0] ^ din[ 5] ^ din[ 6] ^ din[ 2];
dout[ 53] = din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 52] = din[ 7] ^ din[ 4] ^ din[ 0];
dout[ 51] = din[ 6] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[ 50] = din[ 5] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[ 49] = din[ 4] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 48] = din[ 3] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 47] = din[ 2] ^ din[ 8] ^ din[ 0];
dout[ 46] = din[ 1] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[ 45] = din[ 0] ^ din[ 6] ^ din[ 7] ^ din[ 3];
dout[ 44] = din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 6] ^ din[ 2];
dout[ 43] = din[ 7] ^ din[ 4] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[ 42] = din[ 6] ^ din[ 3] ^ din[ 4] ^ din[ 2] ^ din[ 0];
dout[ 41] = din[ 5] ^ din[ 2] ^ din[ 3] ^ din[ 1] ^ din[ 8] ^ din[ 4];
dout[ 40] = din[ 4] ^ din[ 1] ^ din[ 2] ^ din[ 0] ^ din[ 7] ^ din[ 3];
dout[ 39] = din[ 3] ^ din[ 0] ^ din[ 1] ^ din[ 8] ^ din[ 4] ^ din[ 6] ^ din[ 2];
dout[ 38] = din[ 2] ^ din[ 8] ^ din[ 0] ^ din[ 7] ^ din[ 4] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[ 37] = din[ 1] ^ din[ 7] ^ din[ 8] ^ din[ 6] ^ din[ 3] ^ din[ 2] ^ din[ 0];
dout[ 36] = din[ 0] ^ din[ 6] ^ din[ 7] ^ din[ 5] ^ din[ 2] ^ din[ 1] ^ din[ 8] ^ din[ 4];
dout[ 35] = din[ 8] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 0] ^ din[ 7] ^ din[ 3];
dout[ 34] = din[ 7] ^ din[ 5] ^ din[ 0] ^ din[ 8] ^ din[ 6] ^ din[ 2];
dout[ 33] = din[ 6] ^ din[ 8] ^ din[ 7] ^ din[ 5] ^ din[ 1];
dout[ 32] = din[ 5] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 0];
dout[ 31] = din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 8];
dout[ 30] = din[ 4] ^ din[ 2] ^ din[ 5] ^ din[ 7];
dout[ 29] = din[ 4] ^ din[ 3] ^ din[ 1] ^ din[ 6];
dout[ 28] = din[ 3] ^ din[ 2] ^ din[ 0] ^ din[ 5];
dout[ 27] = din[ 2] ^ din[ 1] ^ din[ 8];
dout[ 26] = din[ 1] ^ din[ 0] ^ din[ 7];
dout[ 25] = din[ 0] ^ din[ 8] ^ din[ 6] ^ din[ 4];
dout[ 24] = din[ 8] ^ din[ 7] ^ din[ 5] ^ din[ 4] ^ din[ 3];
dout[ 23] = din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 3] ^ din[ 2];
dout[ 22] = din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 2] ^ din[ 1];
dout[ 21] = din[ 4] ^ din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 0];
dout[ 20] = din[ 3] ^ din[ 1] ^ din[ 0] ^ din[ 8];
dout[ 19] = din[ 2] ^ din[ 0] ^ din[ 8] ^ din[ 7] ^ din[ 4];
dout[ 18] = din[ 1] ^ din[ 8] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 3];
dout[ 17] = din[ 0] ^ din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 2];
dout[ 16] = din[ 8] ^ din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
dout[ 15] = din[ 7] ^ din[ 5] ^ din[ 4] ^ din[ 1] ^ din[ 0];
dout[ 14] = din[ 6] ^ din[ 3] ^ din[ 0] ^ din[ 8];
dout[ 13] = din[ 5] ^ din[ 2] ^ din[ 8] ^ din[ 4] ^ din[ 7];
dout[ 12] = din[ 4] ^ din[ 1] ^ din[ 7] ^ din[ 3] ^ din[ 6];
dout[ 11] = din[ 3] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5];
dout[ 10] = din[ 2] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 9] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 8] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 7] = din[ 8] ^ din[ 2] ^ din[ 5] ^ din[ 4] ^ din[ 7] ^ din[ 3];
dout[ 6] = din[ 7] ^ din[ 4] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[ 5] = din[ 6] ^ din[ 3] ^ din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 1];
dout[ 4] = din[ 5] ^ din[ 2] ^ din[ 8] ^ din[ 1] ^ din[ 0];
dout[ 3] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 8];
dout[ 2] = din[ 0] ^ din[ 6] ^ din[ 8] ^ din[ 4] ^ din[ 7];
dout[ 1] = din[ 8] ^ din[ 5] ^ din[ 7] ^ din[ 4] ^ din[ 3] ^ din[ 6];
dout[ 0] = din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 3] ^ din[ 2] ^ din[ 5];
pn9 = dout;
end
endfunction
// pn sequence select
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
adc_pn_data_in <= { ~adc_data[ 11], adc_data[ 10: 0],
~adc_data[ 23], adc_data[ 22: 12],
~adc_data[ 35], adc_data[ 34: 24],
~adc_data[ 47], adc_data[ 46: 36],
~adc_data[ 59], adc_data[ 58: 48],
~adc_data[ 71], adc_data[ 70: 60],
~adc_data[ 83], adc_data[ 82: 72],
~adc_data[ 95], adc_data[ 94: 84],
~adc_data[107], adc_data[106: 96],
~adc_data[119], adc_data[118:108],
~adc_data[131], adc_data[130:120],
~adc_data[143], adc_data[142:132],
~adc_data[155], adc_data[154:144],
~adc_data[167], adc_data[166:156],
~adc_data[179], adc_data[178:168],
~adc_data[191], adc_data[190:180]};
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
// pn oos & pn error
ad_pnmon #(.DATA_WIDTH(192)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_ad9625/bd/bd.tcl
+47
View File
@@ -0,0 +1,47 @@
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
DEV_PACKAGE \
SPEED_GRADE \
FPGA_FAMILY \
FPGA_TECHNOLOGY"
adi_auto_assign_device_spec $cellpath
}
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
proc adi_auto_assign_device_spec {cellpath} {
set ip [get_bd_cells $cellpath]
set ip_param_list [list_property $ip]
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
set parent_dir "../"
for {set x 1} {$x<=4} {incr x} {
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
if { [file exists $linkname] } {
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
break
}
append parent_dir "../"
}
# Find predefindes auto assignable parameters
foreach i $auto_set_param_list {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
# Find predefindes auto assignable/overwritable parameters
foreach i $auto_set_param_list_overwritable {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
}
adi_library/axi_ad9625/component.xml
+1245
View File
File diff suppressed because it is too large Load Diff
adi_library/axi_ad9625/temporary_case_dependencies.mk
+2
View File
@@ -0,0 +1,2 @@
CLEAN_TARGET += bd
CLEAN_TARGET += temporary_case_dependencies.mk
adi_library/axi_ad9625/vivado.jou
+12
View File
@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Vivado v2019.1.3 (64-bit)
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
# Start of session at: Thu Dec 9 15:10:54 2021
# Process ID: 4379
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625
# Command line: vivado -mode batch -source axi_ad9625_ip.tcl
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625/vivado.log
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9625/vivado.jou
#-----------------------------------------------------------
source axi_ad9625_ip.tcl
adi_library/axi_ad9625/vivado.log
+2063
View File
File diff suppressed because it is too large Load Diff
adi_library/axi_ad9625/xgui/axi_ad9625_v1_0.tcl
+103
View File
@@ -0,0 +1,103 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQUENCY" -parent ${Page_0}
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
#Adding Group
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
}
proc update_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
# Procedure called to update DELAY_REFCLK_FREQUENCY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
# Procedure called to validate DELAY_REFCLK_FREQUENCY
return true
}
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to validate DEV_PACKAGE
return true
}
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to validate FPGA_FAMILY
return true
}
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to validate FPGA_TECHNOLOGY
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to validate SPEED_GRADE
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
}
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
}
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
}
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
}
proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY { MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY}
}