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josh
2023-03-18 15:35:53 +08:00
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adi_library/axi_adc_trigger/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_adc_trigger
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += axi_adc_trigger.v
GENERIC_DEPS += axi_adc_trigger_reg.v
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += axi_adc_trigger_constr.xdc
XILINX_DEPS += axi_adc_trigger_ip.tcl
include ../scripts/library.mk
adi_library/axi_adc_trigger/axi_adc_trigger.cache/wt/project.wpc
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version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:
adi_library/axi_adc_trigger/axi_adc_trigger.hw/axi_adc_trigger.lpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
adi_library/axi_adc_trigger/axi_adc_trigger.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adc_trigger #(
// parameters
parameter SIGN_BITS = 2,
parameter OUT_PIN_HOLD_N = 100000) (
// interface
input clk,
input reset,
input trigger_in,
input [ 1:0] trigger_i,
output reg [ 1:0] trigger_o,
output [ 1:0] trigger_t,
input [15:0] data_a,
input [15:0] data_b,
input data_valid_a,
input data_valid_b,
output reg [15:0] data_a_trig,
output reg [15:0] data_b_trig,
output reg data_valid_a_trig,
output reg data_valid_b_trig,
output trigger_out,
output trigger_out_la,
output [31:0] fifo_depth,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 6:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 6:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
localparam DW = 15 - SIGN_BITS;
// internal signals
wire up_clk;
wire up_rstn;
wire [ 4:0] up_waddr;
wire [31:0] up_wdata;
wire up_wack;
wire up_wreq;
wire up_rack;
wire [31:0] up_rdata;
wire up_rreq;
wire [ 4:0] up_raddr;
wire [ 7:0] io_selection;
wire [ 1:0] low_level;
wire [ 1:0] high_level;
wire [ 1:0] any_edge;
wire [ 1:0] rise_edge;
wire [ 1:0] fall_edge;
wire [15:0] limit_a;
wire [ 1:0] function_a;
wire [31:0] hysteresis_a;
wire [ 3:0] trigger_l_mix_a;
wire [15:0] limit_b;
wire [ 1:0] function_b;
wire [31:0] hysteresis_b;
wire [ 3:0] trigger_l_mix_b;
wire [16:0] trigger_out_control;
wire [31:0] trigger_delay;
wire [31:0] trigger_holdoff;
wire [19:0] trigger_out_hold_pins;
wire signed [DW:0] data_a_cmp;
wire signed [DW:0] data_b_cmp;
wire signed [DW:0] limit_a_cmp;
wire signed [DW:0] limit_b_cmp;
wire comp_low_a_s; // signal is over the limit
wire comp_low_b_s; // signal is over the limit
wire trigger_a_fall_edge;
wire trigger_a_rise_edge;
wire trigger_b_fall_edge;
wire trigger_b_rise_edge;
wire trigger_a_any_edge;
wire trigger_b_any_edge;
wire trigger_out_delayed;
wire [ 1:0] trigger_up_o_s;
wire trigger_out_holdoff;
wire holdoff_cnt_en;
wire streaming;
wire trigger_out_s;
wire embedded_trigger;
wire external_trigger;
reg trigger_a_d1; // synchronization flip flop
reg trigger_a_d2; // synchronization flip flop
reg trigger_a_d3;
reg trigger_b_d1; // synchronization flip flop
reg trigger_b_d2; // synchronization flip flop
reg trigger_b_d3;
reg comp_high_a; // signal is over the limit
reg old_comp_high_a; // t + 1 version of comp_high_a
reg hyst_high_limit_pass_a; // valid hysteresis range on passthrough high trigger limit
reg hyst_low_limit_pass_a; // valid hysteresis range on passthrough low trigger limit
reg signed [DW:0] hyst_a_high_limit;
reg signed [DW:0] hyst_a_low_limit;
reg comp_high_b; // signal is over the limit
reg old_comp_high_b; // t + 1 version of comp_high_b
reg hyst_high_limit_pass_b; // valid hysteresis range on passthrough high trigger limit
reg hyst_low_limit_pass_b; // valid hysteresis range on passthrough low trigger limit
reg signed [DW:0] hyst_b_high_limit;
reg signed [DW:0] hyst_b_low_limit;
reg passthrough_high_a; // trigger when rising through the limit
reg passthrough_low_a; // trigger when fallingh thorugh the limit
reg passthrough_high_b; // trigger when rising through the limit
reg passthrough_low_b; // trigger when fallingh thorugh the limit
reg trigger_pin_a;
reg trigger_pin_b;
reg [ 1:0] trigger_o_m = 1'd0;
reg trig_o_hold_0 = 1'b0;
reg trig_o_hold_1 = 1'b0;
reg [19:0] trig_o_hold_cnt_0 = 20'd0;
reg [19:0] trig_o_hold_cnt_1 = 20'd0;
reg trigger_adc_a;
reg trigger_adc_b;
reg trigger_a;
reg trigger_b;
reg trigger_out_mixed;
reg up_triggered;
reg up_triggered_d1;
reg up_triggered_d2;
reg up_triggered_set;
reg up_triggered_reset;
reg up_triggered_reset_d1;
reg up_triggered_reset_d2;
reg [31:0] trigger_delay_counter = 32'h0;
reg [31:0] trigger_holdoff_counter = 32'h0;
reg triggered;
reg trigger_out_m1;
reg trigger_out_m2;
reg streaming_on;
reg trigger_out_hold;
reg trigger_out_ack;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign trigger_t = io_selection[1:0];
assign trigger_a_fall_edge = (trigger_a_d2 == 1'b0 && trigger_a_d3 == 1'b1) ? 1'b1: 1'b0;
assign trigger_a_rise_edge = (trigger_a_d2 == 1'b1 && trigger_a_d3 == 1'b0) ? 1'b1: 1'b0;
assign trigger_a_any_edge = trigger_a_rise_edge | trigger_a_fall_edge;
assign trigger_b_fall_edge = (trigger_b_d2 == 1'b0 && trigger_b_d3 == 1'b1) ? 1'b1: 1'b0;
assign trigger_b_rise_edge = (trigger_b_d2 == 1'b1 && trigger_b_d3 == 1'b0) ? 1'b1: 1'b0;
assign trigger_b_any_edge = trigger_b_rise_edge | trigger_b_fall_edge;
assign data_a_cmp = data_a[DW:0];
assign data_b_cmp = data_b[DW:0];
assign limit_a_cmp = limit_a[DW:0];
assign limit_b_cmp = limit_b[DW:0];
always @(*) begin
case(io_selection[4:2])
3'h0: trigger_o_m[0] = trigger_up_o_s[0];
3'h1: trigger_o_m[0] = trigger_i[0];
3'h2: trigger_o_m[0] = trigger_i[1];
3'h3: trigger_o_m[0] = trigger_out_mixed;
3'h4: trigger_o_m[0] = trigger_in;
default: trigger_o_m[0] = trigger_up_o_s[0];
endcase
case(io_selection[7:5])
3'h0: trigger_o_m[1] = trigger_up_o_s[1];
3'h1: trigger_o_m[1] = trigger_i[1];
3'h2: trigger_o_m[1] = trigger_i[0];
3'h3: trigger_o_m[1] = trigger_out_mixed;
3'h4: trigger_o_m[1] = trigger_in;
default: trigger_o_m[1] = trigger_up_o_s[1];
endcase
end
// External trigger output hold 100000 clock cycles(1ms) on polarity change.
// All trigger signals that are to be outputted on the external trigger after a
// trigger out is acknowledged by the hold counter will be disregarded for 1ms.
// This was done to avoid noise created by high frequency switches on long
// wires.
always @(posedge clk) begin
// trigger_o[0] hold start
if (trig_o_hold_cnt_0 != 20'd0) begin
trig_o_hold_cnt_0 <= trig_o_hold_cnt_0 - 20'd1;
end else if (trig_o_hold_0 != trigger_o_m[0]) begin
trig_o_hold_cnt_0 <= trigger_out_hold_pins;
trig_o_hold_0 <= trigger_o_m[0];
end
// trigger_o[1] hold start
if (trig_o_hold_cnt_1 != 20'd0) begin
trig_o_hold_cnt_1 <= trig_o_hold_cnt_1 - 20'd1;
end else if (trig_o_hold_1 != trigger_o_m[1]) begin
trig_o_hold_cnt_1 <= trigger_out_hold_pins;
trig_o_hold_1 <= trigger_o_m[1];
end
// hold
trigger_o[0] <= (trig_o_hold_cnt_0 == 'd0) ? trigger_o_m[0] : trig_o_hold_0;
trigger_o[1] <= (trig_o_hold_cnt_1 == 'd0) ? trigger_o_m[1] : trig_o_hold_1;
end
// 1. keep data in sync with the trigger. The trigger bypasses the variable
// fifo. The data goes through and it is delayed with 4 clock cycles)
// 2. For non max sample rate of the ADC, the trigger signal that originates
// from an external source is stored until the valid acknowledges the trigger.
always @(posedge clk) begin
if (reset == 1'b1) begin
trigger_out_m1 <= 1'b0;
trigger_out_m2 <= 1'b0;
trigger_out_ack <= 1'b0;
trigger_out_hold <= 1'b0;
end else begin
if (data_out_valid == 1'b1) begin
trigger_out_m1 <= trigger_out_s | trigger_out_hold;
trigger_out_m2 <= trigger_out_m1;
trigger_out_ack <= trigger_out_hold;
end
if (~trigger_out_m1 & trigger_out_s & ~data_out_valid) begin
trigger_out_hold <= 1'b1;
end
if (trigger_out_ack) begin
trigger_out_hold <= 1'b0;
end
end
end
assign data_out_valid = data_valid_a | data_valid_b;
assign trigger_out_la = trigger_out_mixed;
assign trigger_out = trigger_out_m2;
always @(posedge clk) begin
if (data_out_valid) begin
data_a_trig <= (embedded_trigger == 1'h0) ? {data_a[14],data_a[14:0]} : {trigger_out_s,data_a[14:0]};
data_b_trig <= (embedded_trigger == 1'h0) ? {data_b[14],data_b[14:0]} : {trigger_out_s,data_b[14:0]};
end
data_valid_a_trig <= data_valid_a;
data_valid_b_trig <= data_valid_b;
end
assign embedded_trigger = trigger_out_control[16];
assign trigger_out_s = (trigger_delay == 32'h0) ? (trigger_out_holdoff | streaming_on) :
(trigger_out_delayed | streaming_on);
assign trigger_out_delayed = (trigger_delay_counter == 32'h0) ? 1 : 0;
// delay out trigger
always @(posedge clk) begin
if (trigger_delay == 0) begin
trigger_delay_counter <= 32'h0;
end else begin
if (data_valid_a == 1'b1) begin
triggered <= trigger_out_holdoff | triggered;
if (trigger_delay_counter == 0) begin
trigger_delay_counter <= trigger_delay;
triggered <= 1'b0;
end else begin
if(triggered == 1'b1 || trigger_out_holdoff == 1'b1) begin
trigger_delay_counter <= trigger_delay_counter - 1;
end
end
end
end
end
always @(posedge clk) begin
if (trigger_delay == 0) begin
if (streaming == 1'b1 && data_valid_a == 1'b1 && trigger_out_holdoff == 1'b1) begin
streaming_on <= 1'b1;
end else if (streaming == 1'b0) begin
streaming_on <= 1'b0;
end
end else begin
if (streaming == 1'b1 && data_valid_a == 1'b1 && trigger_out_delayed == 1'b1) begin
streaming_on <= 1'b1;
end else if (streaming == 1'b0) begin
streaming_on <= 1'b0;
end
end
end
// hold off trigger
assign trigger_out_holdoff = (trigger_holdoff_counter != 0) ? 0 : trigger_out_mixed;
always @(posedge clk) begin
if (reset == 1'b1) begin
trigger_holdoff_counter <= 0;
end else begin
if (trigger_holdoff_counter != 0) begin
trigger_holdoff_counter <= trigger_holdoff_counter - 1'b1;
end else if (trigger_out_holdoff == 1'b1) begin
trigger_holdoff_counter <= trigger_holdoff;
end else begin
trigger_holdoff_counter <= trigger_holdoff_counter;
end
end
end
always @(posedge clk) begin
if (data_valid_a == 1'b1 && trigger_out_holdoff == 1'b1) begin
up_triggered_set <= 1'b1;
end else if (up_triggered_reset == 1'b1) begin
up_triggered_set <= 1'b0;
end
up_triggered_reset_d1 <= up_triggered;
up_triggered_reset_d2 <= up_triggered_reset_d1;
up_triggered_reset <= up_triggered_reset_d2;
end
always @(posedge up_clk) begin
up_triggered_d1 <= up_triggered_set;
up_triggered_d2 <= up_triggered_d1;
up_triggered <= up_triggered_d2;
end
always @(*) begin
case(trigger_l_mix_a)
4'h0: trigger_a = 1'b1;
4'h1: trigger_a = trigger_pin_a;
4'h2: trigger_a = trigger_adc_a;
4'h4: trigger_a = trigger_pin_a | trigger_adc_a ;
4'h5: trigger_a = trigger_pin_a & trigger_adc_a ;
4'h6: trigger_a = trigger_pin_a ^ trigger_adc_a ;
4'h7: trigger_a = !(trigger_pin_a | trigger_adc_a) ;
4'h8: trigger_a = !(trigger_pin_a & trigger_adc_a) ;
4'h9: trigger_a = !(trigger_pin_a ^ trigger_adc_a) ;
default: trigger_a = 1'b1;
endcase
end
always @(*) begin
case(trigger_l_mix_b)
4'h0: trigger_b = 1'b1;
4'h1: trigger_b = trigger_pin_b;
4'h2: trigger_b = trigger_adc_b;
4'h4: trigger_b = trigger_pin_b | trigger_adc_b ;
4'h5: trigger_b = trigger_pin_b & trigger_adc_b ;
4'h6: trigger_b = trigger_pin_b ^ trigger_adc_b ;
4'h7: trigger_b = !(trigger_pin_b | trigger_adc_b) ;
4'h8: trigger_b = !(trigger_pin_b & trigger_adc_b) ;
4'h9: trigger_b = !(trigger_pin_b ^ trigger_adc_b) ;
default: trigger_b = 1'b1;
endcase
end
always @(*) begin
case(function_a)
2'h0: trigger_adc_a = comp_low_a_s;
2'h1: trigger_adc_a = comp_high_a;
2'h2: trigger_adc_a = passthrough_high_a;
2'h3: trigger_adc_a = passthrough_low_a;
default: trigger_adc_a = comp_low_a_s;
endcase
end
always @(*) begin
case(function_b)
2'h0: trigger_adc_b = comp_low_b_s;
2'h1: trigger_adc_b = comp_high_b;
2'h2: trigger_adc_b = passthrough_high_b;
2'h3: trigger_adc_b = passthrough_low_b;
default: trigger_adc_b = comp_low_b_s;
endcase
end
always @(posedge clk) begin
trigger_a_d1 <= trigger_i[0];
trigger_a_d2 <= trigger_a_d1;
trigger_a_d3 <= trigger_a_d2;
trigger_b_d1 <= trigger_i[1];
trigger_b_d2 <= trigger_b_d1;
trigger_b_d3 <= trigger_b_d2;
end
always @(*) begin
trigger_pin_a = ((!trigger_a_d3 & low_level[0]) |
(trigger_a_d3 & high_level[0]) |
(trigger_a_fall_edge & fall_edge[0]) |
(trigger_a_rise_edge & rise_edge[0]) |
(trigger_a_any_edge & any_edge[0]));
end
always @(*) begin
trigger_pin_b = ((!trigger_b_d3 & low_level[1]) |
(trigger_b_d3 & high_level[1]) |
(trigger_b_fall_edge & fall_edge[1]) |
(trigger_b_rise_edge & rise_edge[1]) |
(trigger_b_any_edge & any_edge[1]));
end
always @(*) begin
case(trigger_out_control[3:0])
4'h0: trigger_out_mixed = trigger_a;
4'h1: trigger_out_mixed = trigger_b;
4'h2: trigger_out_mixed = trigger_a | trigger_b;
4'h3: trigger_out_mixed = trigger_a & trigger_b;
4'h4: trigger_out_mixed = trigger_a ^ trigger_b;
4'h5: trigger_out_mixed = trigger_in;
4'h6: trigger_out_mixed = trigger_a | trigger_in;
4'h7: trigger_out_mixed = trigger_b | trigger_in;
4'h8: trigger_out_mixed = trigger_a | trigger_b | trigger_in;
4'hf: trigger_out_mixed = 1'b0; // trigger disable
default: trigger_out_mixed = 1'b0;
endcase
end
always @(posedge clk) begin
if (reset == 1'b1) begin
comp_high_a <= 1'b0;
old_comp_high_a <= 1'b0;
passthrough_high_a <= 1'b0;
passthrough_low_a <= 1'b0;
hyst_a_high_limit <= {DW{1'b0}};
hyst_a_low_limit <= {DW{1'b0}};
hyst_high_limit_pass_a <= 1'b0;
hyst_low_limit_pass_a <= 1'b0;
end else begin
if (data_valid_a == 1'b1) begin
hyst_a_high_limit <= limit_a_cmp + hysteresis_a[DW:0];
hyst_a_low_limit <= limit_a_cmp - hysteresis_a[DW:0];
if (data_a_cmp >= limit_a_cmp) begin
comp_high_a <= 1'b1;
end else begin
comp_high_a <= 1'b0;
end
if (data_a_cmp > hyst_a_high_limit) begin
hyst_low_limit_pass_a <= 1'b1;
end else begin
hyst_low_limit_pass_a <= (passthrough_low_a) ? 1'b0 : hyst_low_limit_pass_a;
end
if (data_a_cmp < hyst_a_low_limit) begin
hyst_high_limit_pass_a <= 1'b1;
end else begin
hyst_high_limit_pass_a <= passthrough_high_a ? 1'b0 : hyst_high_limit_pass_a;
end
old_comp_high_a <= comp_high_a;
passthrough_high_a <= !old_comp_high_a & comp_high_a & hyst_high_limit_pass_a;
passthrough_low_a <= old_comp_high_a & !comp_high_a & hyst_low_limit_pass_a;
end
end
end
assign comp_low_a_s = !comp_high_a;
always @(posedge clk) begin
if (reset == 1'b1) begin
comp_high_b <= 1'b0;
old_comp_high_b <= 1'b0;
passthrough_high_b <= 1'b0;
passthrough_low_b <= 1'b0;
hyst_b_high_limit <= {DW{1'b0}};
hyst_b_low_limit <= {DW{1'b0}};
hyst_high_limit_pass_b <= 1'b0;
hyst_low_limit_pass_b <= 1'b0;
end else begin
if (data_valid_b == 1'b1) begin
hyst_b_high_limit <= limit_b_cmp + hysteresis_b[DW:0];
hyst_b_low_limit <= limit_b_cmp - hysteresis_b[DW:0];
if (data_b_cmp >= limit_b_cmp) begin
comp_high_b <= 1'b1;
end else begin
comp_high_b <= 1'b0;
end
if (data_b_cmp > hyst_b_high_limit) begin
hyst_low_limit_pass_b <= 1'b1;
end else begin
hyst_low_limit_pass_b <= (passthrough_low_b) ? 1'b0 : hyst_low_limit_pass_b;
end
if (data_b_cmp < hyst_b_low_limit) begin
hyst_high_limit_pass_b <= 1'b1;
end else begin
hyst_high_limit_pass_b <= passthrough_high_b ? 1'b0 : hyst_high_limit_pass_b;
end
old_comp_high_b <= comp_high_b;
passthrough_high_b <= !old_comp_high_b & comp_high_b & hyst_high_limit_pass_b;
passthrough_low_b <= old_comp_high_b & !comp_high_b & hyst_low_limit_pass_b;
end
end
end
assign comp_low_b_s = !comp_high_b;
axi_adc_trigger_reg adc_trigger_registers (
.clk(clk),
.io_selection(io_selection),
.trigger_o(trigger_up_o_s),
.triggered(up_triggered),
.low_level(low_level),
.high_level(high_level),
.any_edge(any_edge),
.rise_edge(rise_edge),
.fall_edge(fall_edge),
.limit_a(limit_a),
.function_a(function_a),
.hysteresis_a(hysteresis_a),
.trigger_l_mix_a(trigger_l_mix_a),
.limit_b(limit_b),
.function_b(function_b),
.hysteresis_b(hysteresis_b),
.trigger_l_mix_b(trigger_l_mix_b),
.trigger_out_control(trigger_out_control),
.trigger_delay(trigger_delay),
.trigger_holdoff (trigger_holdoff),
.trigger_out_hold_pins (trigger_out_hold_pins),
.fifo_depth(fifo_depth),
.streaming(streaming),
// bus interface
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack));
up_axi #(
.AXI_ADDRESS_WIDTH(7)
) i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_adc_trigger/axi_adc_trigger.xpr
+409
View File
@@ -0,0 +1,409 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters>
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
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<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
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<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
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<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
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</Project>
adi_library/axi_adc_trigger/axi_adc_trigger_constr.xdc
+11
View File
@@ -0,0 +1,11 @@
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_a_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_b_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_reset_d*}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_a_d1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_b_d1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}]
adi_library/axi_adc_trigger/axi_adc_trigger_ip.log
+1036
View File
File diff suppressed because it is too large Load Diff
adi_library/axi_adc_trigger/axi_adc_trigger_ip.tcl
+21
View File
@@ -0,0 +1,21 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_adc_trigger
adi_ip_files axi_adc_trigger [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"axi_adc_trigger_constr.xdc" \
"axi_adc_trigger_reg.v" \
"axi_adc_trigger.v" ]
adi_ip_properties axi_adc_trigger
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/axi_adc_trigger/axi_adc_trigger_reg.v
+288
View File
@@ -0,0 +1,288 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adc_trigger_reg (
input clk,
output [ 7:0] io_selection,
output [ 1:0] trigger_o,
input triggered,
output [ 1:0] low_level,
output [ 1:0] high_level,
output [ 1:0] any_edge,
output [ 1:0] rise_edge,
output [ 1:0] fall_edge,
output [15:0] limit_a,
output [ 1:0] function_a,
output [31:0] hysteresis_a,
output [ 3:0] trigger_l_mix_a,
output [15:0] limit_b,
output [ 1:0] function_b,
output [31:0] hysteresis_b,
output [ 3:0] trigger_l_mix_b,
output [16:0] trigger_out_control,
output [31:0] fifo_depth,
output [31:0] trigger_delay,
output [31:0] trigger_holdoff,
output [19:0] trigger_out_hold_pins,
output streaming,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 4:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 4:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
localparam DEFAULT_OUT_HOLD = 100000; // 1ms
// internal signals
wire [ 9:0] config_trigger_i;
// internal registers
reg [31:0] up_version = 32'h00030000;
reg [31:0] up_scratch = 32'h0;
reg [ 7:0] up_io_selection = 8'h0;
reg [ 1:0] up_trigger_o = 2'h0;
reg [ 9:0] up_config_trigger_i = 10'h0;
reg [15:0] up_limit_a = 16'h0;
reg [ 1:0] up_function_a = 2'h0;
reg [31:0] up_hysteresis_a = 32'h0;
reg [ 3:0] up_trigger_l_mix_a = 4'h0;
reg [15:0] up_limit_b = 16'h0;
reg [ 1:0] up_function_b = 2'h0;
reg [31:0] up_hysteresis_b = 32'h0;
reg [ 3:0] up_trigger_l_mix_b = 4'h0;
reg [16:0] up_trigger_out_control = 17'h0;
reg [31:0] up_fifo_depth = 32'h0;
reg [31:0] up_trigger_delay = 32'h0;
reg [31:0] up_trigger_holdoff = 32'h0;
reg [19:0] up_trigger_out_hold_pins = DEFAULT_OUT_HOLD;
reg up_triggered = 1'h0;
reg up_streaming = 1'h0;
assign low_level = config_trigger_i[1:0];
assign high_level = config_trigger_i[3:2];
assign any_edge = config_trigger_i[5:4];
assign rise_edge = config_trigger_i[7:6];
assign fall_edge = config_trigger_i[9:8];
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_trigger_o <= 'd0;
up_io_selection <= 'd1;
up_config_trigger_i <= 'd0;
up_limit_a <= 'd0;
up_function_a <= 'd0;
up_hysteresis_a <= 'd0;
up_limit_b <= 'd0;
up_function_b <= 'd0;
up_hysteresis_b <= 'd0;
up_fifo_depth <= 'd0;
up_trigger_delay <= 'd0;
up_trigger_l_mix_a <= 'd0;
up_trigger_l_mix_b <= 'd0;
up_trigger_out_control <= 'd0;
up_triggered <= 1'd0;
up_streaming <= 1'd0;
up_trigger_holdoff <= 32'h0;
up_trigger_out_hold_pins <= DEFAULT_OUT_HOLD;
end else begin
up_wack <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
up_scratch <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h2)) begin
up_trigger_o <= up_wdata[1:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h3)) begin
up_io_selection <= up_wdata[7:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h4)) begin
up_config_trigger_i <= up_wdata[9:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h5)) begin
up_limit_a <= up_wdata[15:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h6)) begin
up_function_a <= up_wdata[1:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h7)) begin
up_hysteresis_a <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h8)) begin
up_trigger_l_mix_a <= up_wdata[3:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h9)) begin
up_limit_b <= up_wdata[15:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'ha)) begin
up_function_b <= up_wdata[1:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hb)) begin
up_hysteresis_b <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hc)) begin
up_trigger_l_mix_b <= up_wdata[3:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hd)) begin
up_trigger_out_control <= up_wdata[16:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'he)) begin
up_fifo_depth <= up_wdata;
end
if (triggered == 1'b1) begin
up_triggered <= 1'b1;
end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hf)) begin
up_triggered <= up_triggered & ~up_wdata[0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
up_trigger_delay <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
up_streaming <= up_wdata[0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
up_trigger_holdoff <= up_wdata[31:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
up_trigger_out_hold_pins <= up_wdata[19:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq;
if (up_rreq == 1'b1) begin
case (up_raddr[4:0])
5'h0: up_rdata <= up_version;
5'h1: up_rdata <= up_scratch;
5'h2: up_rdata <= {30'h0,up_trigger_o};
5'h3: up_rdata <= {24'h0,up_io_selection};
5'h4: up_rdata <= {22'h0,up_config_trigger_i};
5'h5: up_rdata <= {16'h0,up_limit_a};
5'h6: up_rdata <= {30'h0,up_function_a};
5'h7: up_rdata <= up_hysteresis_a;
5'h8: up_rdata <= {28'h0,up_trigger_l_mix_a};
5'h9: up_rdata <= {16'h0,up_limit_b};
5'ha: up_rdata <= {30'h0,up_function_b};
5'hb: up_rdata <= up_hysteresis_b;
5'hc: up_rdata <= {28'h0,up_trigger_l_mix_b};
5'hd: up_rdata <= {15'h0,up_trigger_out_control};
5'he: up_rdata <= up_fifo_depth;
5'hf: up_rdata <= {31'h0,up_triggered};
5'h10: up_rdata <= up_trigger_delay;
5'h11: up_rdata <= {31'h0,up_streaming};
5'h12: up_rdata <= up_trigger_holdoff;
5'h13: up_rdata <= {12'h0,up_trigger_out_hold_pins};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
up_xfer_cntrl #(.DATA_WIDTH(262)) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_streaming, // 1
up_trigger_o, // 2
up_io_selection, // 8
up_config_trigger_i, // 10
up_limit_a, // 16
up_function_a, // 2
up_hysteresis_a, // 32
up_trigger_l_mix_a, // 4
up_limit_b, // 16
up_function_b, // 2
up_hysteresis_b, // 32
up_trigger_l_mix_b, // 4
up_trigger_out_control, // 17
up_fifo_depth, // 32
up_trigger_holdoff, // 32
up_trigger_out_hold_pins, // 20
up_trigger_delay}), // 32
.up_xfer_done (),
.d_rst (1'b0),
.d_clk (clk),
.d_data_cntrl ({ streaming, // 1
trigger_o, // 2
io_selection, // 8
config_trigger_i, // 10
limit_a, // 16
function_a, // 2
hysteresis_a, // 32
trigger_l_mix_a, // 4
limit_b, // 16
function_b, // 2
hysteresis_b, // 32
trigger_l_mix_b, // 4
trigger_out_control, // 17
fifo_depth, // 32
trigger_holdoff, // 32
trigger_out_hold_pins, // 20
trigger_delay})); // 32
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_adc_trigger/component.xml
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adi_library/axi_adc_trigger/vivado.jou
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#-----------------------------------------------------------
# Vivado v2019.1.3 (64-bit)
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
# Start of session at: Thu Dec 9 15:12:55 2021
# Process ID: 5029
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger
# Command line: vivado -mode batch -source axi_adc_trigger_ip.tcl
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger/vivado.log
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_adc_trigger/vivado.jou
#-----------------------------------------------------------
source axi_adc_trigger_ip.tcl
adi_library/axi_adc_trigger/vivado.log
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adi_library/axi_adc_trigger/xgui/axi_adc_trigger_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "OUT_PIN_HOLD_N" -parent ${Page_0}
ipgui::add_param $IPINST -name "SIGN_BITS" -parent ${Page_0}
}
proc update_PARAM_VALUE.OUT_PIN_HOLD_N { PARAM_VALUE.OUT_PIN_HOLD_N } {
# Procedure called to update OUT_PIN_HOLD_N when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.OUT_PIN_HOLD_N { PARAM_VALUE.OUT_PIN_HOLD_N } {
# Procedure called to validate OUT_PIN_HOLD_N
return true
}
proc update_PARAM_VALUE.SIGN_BITS { PARAM_VALUE.SIGN_BITS } {
# Procedure called to update SIGN_BITS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SIGN_BITS { PARAM_VALUE.SIGN_BITS } {
# Procedure called to validate SIGN_BITS
return true
}
proc update_MODELPARAM_VALUE.SIGN_BITS { MODELPARAM_VALUE.SIGN_BITS PARAM_VALUE.SIGN_BITS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SIGN_BITS}] ${MODELPARAM_VALUE.SIGN_BITS}
}
proc update_MODELPARAM_VALUE.OUT_PIN_HOLD_N { MODELPARAM_VALUE.OUT_PIN_HOLD_N PARAM_VALUE.OUT_PIN_HOLD_N } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.OUT_PIN_HOLD_N}] ${MODELPARAM_VALUE.OUT_PIN_HOLD_N}
}