Archived
initial commit
This commit is contained in:
@@ -0,0 +1,17 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_clkgen
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GENERIC_DEPS += ../common/ad_rst.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_clkgen.v
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GENERIC_DEPS += axi_clkgen.v
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XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v
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XILINX_DEPS += axi_clkgen_ip.tcl
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XILINX_DEPS += bd/bd.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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||||
<!-- -->
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||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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||||
|
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,224 @@
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// ***************************************************************************
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||||
// ***************************************************************************
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||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
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||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
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||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
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||||
//
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||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
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||||
//
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||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
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||||
// of this repository (LICENSE_GPL2), and also online at:
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||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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||||
// OR
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||||
//
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||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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||||
// This will allow to generate bit files and not release the source code,
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||||
// as long as it attaches to an ADI device.
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||||
//
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// ***************************************************************************
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||||
// ***************************************************************************
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// software programmable clock generator (still needs a reference input!)
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`timescale 1ns/100ps
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module axi_clkgen #(
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parameter ID = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter FPGA_VOLTAGE = 0,
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parameter CLKSEL_EN = 0,
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parameter real CLKIN_PERIOD = 5.000,
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parameter real CLKIN2_PERIOD = 5.000,
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parameter integer VCO_DIV = 11,
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parameter real VCO_MUL = 49.000,
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parameter real CLK0_DIV = 6.000,
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parameter real CLK0_PHASE = 0.000,
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parameter integer CLK1_DIV = 6,
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parameter real CLK1_PHASE = 0.000) (
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// clocks
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input clk,
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input clk2,
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output clk_0,
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output clk_1,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready,
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot);
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// reset and clocks
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wire mmcm_rst;
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wire clk_sel_s;
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wire up_clk_sel_s;
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire up_drp_sel_s;
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wire up_drp_wr_s;
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wire [11:0] up_drp_addr_s;
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wire [15:0] up_drp_wdata_s;
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wire [15:0] up_drp_rdata_s;
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wire up_drp_ready_s;
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wire up_drp_locked_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_s;
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wire up_rack_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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||||
.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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||||
.up_axi_bresp (s_axi_bresp),
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||||
.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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||||
.up_axi_araddr (s_axi_araddr),
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||||
.up_axi_arready (s_axi_arready),
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||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
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||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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||||
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// processor interface
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||||
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||||
up_clkgen #(
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||||
.ID(ID),
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||||
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
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.FPGA_FAMILY(FPGA_FAMILY),
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||||
.SPEED_GRADE(SPEED_GRADE),
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||||
.DEV_PACKAGE(DEV_PACKAGE),
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||||
.FPGA_VOLTAGE(FPGA_VOLTAGE)
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) i_up_clkgen (
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||||
.mmcm_rst (mmcm_rst),
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.clk_sel (up_clk_sel_s),
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||||
.up_drp_sel (up_drp_sel_s),
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||||
.up_drp_wr (up_drp_wr_s),
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||||
.up_drp_addr (up_drp_addr_s),
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||||
.up_drp_wdata (up_drp_wdata_s),
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||||
.up_drp_rdata (up_drp_rdata_s),
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||||
.up_drp_ready (up_drp_ready_s),
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||||
.up_drp_locked (up_drp_locked_s),
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.up_rstn (up_rstn),
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||||
.up_clk (up_clk),
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||||
.up_wreq (up_wreq_s),
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||||
.up_waddr (up_waddr_s),
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||||
.up_wdata (up_wdata_s),
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||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
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||||
.up_raddr (up_raddr_s),
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||||
.up_rdata (up_rdata_s),
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||||
.up_rack (up_rack_s));
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// If CLKSEL_EN is not active, the clk0 port of the MMCM is used, this
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// should be used when the MMCM has only one active clock source
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generate if (CLKSEL_EN == 1) begin
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assign clk_sel_s = up_clk_sel_s;
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end else begin
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assign clk_sel_s = 1'b1;
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end
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endgenerate
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||||
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||||
// mmcm instantiations
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ad_mmcm_drp #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.MMCM_CLKIN_PERIOD (CLKIN_PERIOD),
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||||
.MMCM_CLKIN2_PERIOD (CLKIN2_PERIOD),
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||||
.MMCM_VCO_DIV (VCO_DIV),
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||||
.MMCM_VCO_MUL (VCO_MUL),
|
||||
.MMCM_CLK0_DIV (CLK0_DIV),
|
||||
.MMCM_CLK0_PHASE (CLK0_PHASE),
|
||||
.MMCM_CLK1_DIV (CLK1_DIV),
|
||||
.MMCM_CLK1_PHASE (CLK1_PHASE))
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||||
i_mmcm_drp (
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||||
.clk (clk),
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||||
.clk2 (clk2),
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||||
.clk_sel(clk_sel_s),
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||||
.mmcm_rst (mmcm_rst),
|
||||
.mmcm_clk_0 (clk_0),
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||||
.mmcm_clk_1 (clk_1),
|
||||
.mmcm_clk_2 (),
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn),
|
||||
.up_drp_sel (up_drp_sel_s),
|
||||
.up_drp_wr (up_drp_wr_s),
|
||||
.up_drp_addr (up_drp_addr_s),
|
||||
.up_drp_wdata (up_drp_wdata_s),
|
||||
.up_drp_rdata (up_drp_rdata_s),
|
||||
.up_drp_ready (up_drp_ready_s),
|
||||
.up_drp_locked (up_drp_locked_s));
|
||||
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||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,418 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen/axi_clkgen.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="fa53a625cb934711a66c5f8d7de408cd"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../xilinx/common/ad_mmcm_drp.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/ad_rst.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_clkgen.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_clkgen.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../scripts/adi_xilinx_device_info_enc.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_clkgen"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,751 @@
|
||||
|
||||
****** Vivado v2019.1.3 (64-bit)
|
||||
**** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
**** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source axi_clkgen_ip.tcl
|
||||
# source ../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create axi_clkgen
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files axi_clkgen [list \
|
||||
# "$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
# "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
|
||||
# "$ad_hdl_dir/library/common/up_axi.v" \
|
||||
# "$ad_hdl_dir/library/common/up_clkgen.v" \
|
||||
# "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
|
||||
# "bd/bd.tcl" \
|
||||
# "axi_clkgen.v" ]
|
||||
# adi_ip_properties axi_clkgen
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clkgen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clkgen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Synthesis'.
|
||||
Resolution: Remove the file from the specified file group.
|
||||
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Synthesis'.
|
||||
Resolution: Remove the file from the specified file group.
|
||||
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Simulation'.
|
||||
Resolution: Remove the file from the specified file group.
|
||||
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Simulation'.
|
||||
Resolution: Remove the file from the specified file group.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
# adi_ip_bd axi_clkgen "bd/bd.tcl"
|
||||
# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_0' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_1' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# set cc [ipx::current_core]
|
||||
# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
# set param [ipx::add_user_parameter ENABLE_CLKIN2 $cc]
|
||||
# set_property -dict {value_resolve_type user value_format bool value false} $param
|
||||
# set param [ipgui::add_param -name {ENABLE_CLKIN2} -component $cc -parent $page0]
|
||||
# set_property -dict [list \
|
||||
# display_name {Enable secondary clock input} \
|
||||
# widget {checkBox} \
|
||||
# ] $param
|
||||
# set param [ipx::add_user_parameter ENABLE_CLKOUT1 $cc]
|
||||
# set_property -dict {value_resolve_type user value_format bool value false} $param
|
||||
# set param [ipgui::add_param -name {ENABLE_CLKOUT1} -component $cc -parent $page0]
|
||||
# set_property -dict [list \
|
||||
# display_name {Enable secondary clock output} \
|
||||
# widget {checkBox} \
|
||||
# ] $param
|
||||
# adi_add_auto_fpga_spec_params
|
||||
# ipx::create_xgui_files [ipx::current_core]
|
||||
# set_property enablement_tcl_expr {$ENABLE_CLKIN2} [ipx::get_user_parameters CLKIN2_PERIOD -of_objects $cc]
|
||||
# set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_DIV -of_objects $cc]
|
||||
# set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_PHASE -of_objects $cc]
|
||||
# adi_set_ports_dependency clk2 ENABLE_CLKIN2 0
|
||||
# adi_set_ports_dependency clk_1 ENABLE_CLKOUT1
|
||||
# ipx::create_xgui_files $cc
|
||||
# ipx::save_core $cc
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:22:17 2021...
|
||||
@@ -0,0 +1,56 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_clkgen
|
||||
adi_ip_files axi_clkgen [list \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_clkgen.v" \
|
||||
"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
|
||||
"bd/bd.tcl" \
|
||||
"axi_clkgen.v" ]
|
||||
|
||||
adi_ip_properties axi_clkgen
|
||||
adi_ip_bd axi_clkgen "bd/bd.tcl"
|
||||
|
||||
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
set cc [ipx::current_core]
|
||||
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
|
||||
set param [ipx::add_user_parameter ENABLE_CLKIN2 $cc]
|
||||
set_property -dict {value_resolve_type user value_format bool value false} $param
|
||||
|
||||
set param [ipgui::add_param -name {ENABLE_CLKIN2} -component $cc -parent $page0]
|
||||
set_property -dict [list \
|
||||
display_name {Enable secondary clock input} \
|
||||
widget {checkBox} \
|
||||
] $param
|
||||
|
||||
set param [ipx::add_user_parameter ENABLE_CLKOUT1 $cc]
|
||||
set_property -dict {value_resolve_type user value_format bool value false} $param
|
||||
|
||||
set param [ipgui::add_param -name {ENABLE_CLKOUT1} -component $cc -parent $page0]
|
||||
set_property -dict [list \
|
||||
display_name {Enable secondary clock output} \
|
||||
widget {checkBox} \
|
||||
] $param
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
set_property enablement_tcl_expr {$ENABLE_CLKIN2} [ipx::get_user_parameters CLKIN2_PERIOD -of_objects $cc]
|
||||
set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_DIV -of_objects $cc]
|
||||
set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_PHASE -of_objects $cc]
|
||||
|
||||
adi_set_ports_dependency clk2 ENABLE_CLKIN2 0
|
||||
adi_set_ports_dependency clk_1 ENABLE_CLKOUT1
|
||||
|
||||
ipx::create_xgui_files $cc
|
||||
ipx::save_core $cc
|
||||
@@ -0,0 +1,154 @@
|
||||
## ***************************************************************************
|
||||
## ***************************************************************************
|
||||
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
##
|
||||
## In this HDL repository, there are many different and unique modules, consisting
|
||||
## of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
## developed independently, and may be accompanied by separate and unique license
|
||||
## terms.
|
||||
##
|
||||
## The user should read each of these license terms, and understand the
|
||||
## freedoms and responsibilities that he or she has by using this source/core.
|
||||
##
|
||||
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
## A PARTICULAR PURPOSE.
|
||||
##
|
||||
## Redistribution and use of source or resulting binaries, with or without modification
|
||||
## of this file, are permitted under one of the following two license terms:
|
||||
##
|
||||
## 1. The GNU General Public License version 2 as published by the
|
||||
## Free Software Foundation, which can be found in the top level directory
|
||||
## of this repository (LICENSE_GPL2), and also online at:
|
||||
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
##
|
||||
## OR
|
||||
##
|
||||
## 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
## of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
## This will allow to generate bit files and not release the source code,
|
||||
## as long as it attaches to an ADI device.
|
||||
##
|
||||
## ***************************************************************************
|
||||
## ***************************************************************************
|
||||
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_override $ip \
|
||||
"CLKIN_PERIOD \
|
||||
CLKIN2_PERIOD \
|
||||
FPGA_VOLTAGE"
|
||||
|
||||
bd::mark_propagate_only $ip \
|
||||
"FPGA_TECHNOLOGY \
|
||||
FPGA_FAMILY \
|
||||
SPEED_GRADE \
|
||||
DEV_PACKAGE \
|
||||
FPGA_VOLTAGE"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
proc axi_clkgen_get_infer_period {ip param clk_name} {
|
||||
set param_src [get_property "CONFIG.$param.VALUE_SRC" $ip]
|
||||
if {[string equal $param_src "USER"]} {
|
||||
return;
|
||||
}
|
||||
|
||||
set clk [get_bd_pins "$ip/$clk_name"]
|
||||
set clk_freq [get_property CONFIG.FREQ_HZ $clk]
|
||||
|
||||
if {$clk_freq != {}} {
|
||||
set clk_period [expr 1000000000.0 / $clk_freq]
|
||||
set_property "CONFIG.$param" [format "%.6f" $clk_period] $ip
|
||||
}
|
||||
}
|
||||
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc propagate {cellpath otherinfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
set vco_mul [get_property CONFIG.VCO_MUL $ip]
|
||||
set vco_div [get_property CONFIG.VCO_DIV $ip]
|
||||
set clk0_div [get_property CONFIG.CLK0_DIV $ip]
|
||||
set clk1_div [get_property CONFIG.CLK1_DIV $ip]
|
||||
|
||||
if {$vco_mul == {} || $vco_mul < 1} {
|
||||
set vco_mul 1
|
||||
}
|
||||
if {$vco_div == {} || $vco_div < 1} {
|
||||
set vco_div 1
|
||||
}
|
||||
if {$clk0_div == {} || $clk0_div < 1} {
|
||||
set clk0_div 1
|
||||
}
|
||||
if {$clk1_div == {} || $clk0_div < 1} {
|
||||
set clk1_div 1
|
||||
}
|
||||
|
||||
set clk [get_bd_pins "$ip/clk"]
|
||||
set clk_freq [get_property CONFIG.FREQ_HZ $clk]
|
||||
if {[get_property "CONFIG.ENABLE_CLKIN2" $ip] == "true"} {
|
||||
set clk2 [get_bd_pins "$ip/clk"]
|
||||
set clk2_freq [get_property CONFIG.FREQ_HZ $clk2]
|
||||
# Use the larger of the two
|
||||
if {$clk_freq == {} || $clk2_freq > $clk_freq} {
|
||||
set clk_freq $clk2_freq
|
||||
}
|
||||
}
|
||||
|
||||
if {$clk_freq != {}} {
|
||||
set clk0_out [get_bd_pins "$ip/clk_0"]
|
||||
set clk0_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk0_div)]
|
||||
set_property CONFIG.FREQ_HZ $clk0_out_freq $clk0_out
|
||||
|
||||
if {[get_property "CONFIG.ENABLE_CLKOUT1" $ip] == "true"} {
|
||||
set clk1_out [get_bd_pins "$ip/clk_1"]
|
||||
set clk1_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk1_div)]
|
||||
set_property CONFIG.FREQ_HZ $clk1_out_freq $clk1_out
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc post_propagate {cellpath otherinfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
axi_clkgen_get_infer_period $ip CLKIN_PERIOD clk
|
||||
if {[get_property "CONFIG.ENABLE_CLKIN2" $ip] == "true"} {
|
||||
axi_clkgen_get_infer_period $ip CLKIN2_PERIOD clk2
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,4 @@
|
||||
# This file is automatically written. Do not modify.
|
||||
proc gen_USERPARAMETER_CLKIN2_PERIOD_ENABLEMENT {ENABLE_CLKIN2 } {expr $ENABLE_CLKIN2}
|
||||
proc gen_USERPARAMETER_CLK1_DIV_ENABLEMENT {ENABLE_CLKOUT1 } {expr $ENABLE_CLKOUT1}
|
||||
proc gen_USERPARAMETER_CLK1_PHASE_ENABLEMENT {ENABLE_CLKOUT1 } {expr $ENABLE_CLKOUT1}
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Dec 8 10:22:07 2021
|
||||
# Process ID: 66374
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen
|
||||
# Command line: vivado -mode batch -source axi_clkgen_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_clkgen_ip.tcl
|
||||
@@ -0,0 +1,756 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Dec 8 10:22:07 2021
|
||||
# Process ID: 66374
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen
|
||||
# Command line: vivado -mode batch -source axi_clkgen_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_clkgen_ip.tcl
|
||||
# source ../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create axi_clkgen
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files axi_clkgen [list \
|
||||
# "$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
# "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
|
||||
# "$ad_hdl_dir/library/common/up_axi.v" \
|
||||
# "$ad_hdl_dir/library/common/up_clkgen.v" \
|
||||
# "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
|
||||
# "bd/bd.tcl" \
|
||||
# "axi_clkgen.v" ]
|
||||
# adi_ip_properties axi_clkgen
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clkgen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clkgen.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Synthesis'.
|
||||
Resolution: Remove the file from the specified file group.
|
||||
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Synthesis'.
|
||||
Resolution: Remove the file from the specified file group.
|
||||
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Simulation'.
|
||||
Resolution: Remove the file from the specified file group.
|
||||
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Simulation'.
|
||||
Resolution: Remove the file from the specified file group.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
# adi_ip_bd axi_clkgen "bd/bd.tcl"
|
||||
# ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_0' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_1' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# set cc [ipx::current_core]
|
||||
# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
# set param [ipx::add_user_parameter ENABLE_CLKIN2 $cc]
|
||||
# set_property -dict {value_resolve_type user value_format bool value false} $param
|
||||
# set param [ipgui::add_param -name {ENABLE_CLKIN2} -component $cc -parent $page0]
|
||||
# set_property -dict [list \
|
||||
# display_name {Enable secondary clock input} \
|
||||
# widget {checkBox} \
|
||||
# ] $param
|
||||
# set param [ipx::add_user_parameter ENABLE_CLKOUT1 $cc]
|
||||
# set_property -dict {value_resolve_type user value_format bool value false} $param
|
||||
# set param [ipgui::add_param -name {ENABLE_CLKOUT1} -component $cc -parent $page0]
|
||||
# set_property -dict [list \
|
||||
# display_name {Enable secondary clock output} \
|
||||
# widget {checkBox} \
|
||||
# ] $param
|
||||
# adi_add_auto_fpga_spec_params
|
||||
# ipx::create_xgui_files [ipx::current_core]
|
||||
# set_property enablement_tcl_expr {$ENABLE_CLKIN2} [ipx::get_user_parameters CLKIN2_PERIOD -of_objects $cc]
|
||||
# set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_DIV -of_objects $cc]
|
||||
# set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_PHASE -of_objects $cc]
|
||||
# adi_set_ports_dependency clk2 ENABLE_CLKIN2 0
|
||||
# adi_set_ports_dependency clk_1 ENABLE_CLKOUT1
|
||||
# ipx::create_xgui_files $cc
|
||||
# ipx::save_core $cc
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:22:17 2021...
|
||||
@@ -0,0 +1,289 @@
|
||||
|
||||
# Loading additional proc with user specified bodies to compute parameter values.
|
||||
source [file join [file dirname [file dirname [info script]]] gui/axi_clkgen_v1_0.gtcl]
|
||||
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "CLK0_DIV" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CLK0_PHASE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CLK1_DIV" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CLK1_PHASE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CLKIN2_PERIOD" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CLKIN_PERIOD" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CLKSEL_EN" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "VCO_DIV" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "VCO_MUL" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ENABLE_CLKIN2" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ENABLE_CLKOUT1" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_VOLTAGE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLK1_DIV { PARAM_VALUE.CLK1_DIV PARAM_VALUE.ENABLE_CLKOUT1 } {
|
||||
# Procedure called to update CLK1_DIV when any of the dependent parameters in the arguments change
|
||||
|
||||
set CLK1_DIV ${PARAM_VALUE.CLK1_DIV}
|
||||
set ENABLE_CLKOUT1 ${PARAM_VALUE.ENABLE_CLKOUT1}
|
||||
set values(ENABLE_CLKOUT1) [get_property value $ENABLE_CLKOUT1]
|
||||
if { [gen_USERPARAMETER_CLK1_DIV_ENABLEMENT $values(ENABLE_CLKOUT1)] } {
|
||||
set_property enabled true $CLK1_DIV
|
||||
} else {
|
||||
set_property enabled false $CLK1_DIV
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLK1_DIV { PARAM_VALUE.CLK1_DIV } {
|
||||
# Procedure called to validate CLK1_DIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLK1_PHASE { PARAM_VALUE.CLK1_PHASE PARAM_VALUE.ENABLE_CLKOUT1 } {
|
||||
# Procedure called to update CLK1_PHASE when any of the dependent parameters in the arguments change
|
||||
|
||||
set CLK1_PHASE ${PARAM_VALUE.CLK1_PHASE}
|
||||
set ENABLE_CLKOUT1 ${PARAM_VALUE.ENABLE_CLKOUT1}
|
||||
set values(ENABLE_CLKOUT1) [get_property value $ENABLE_CLKOUT1]
|
||||
if { [gen_USERPARAMETER_CLK1_PHASE_ENABLEMENT $values(ENABLE_CLKOUT1)] } {
|
||||
set_property enabled true $CLK1_PHASE
|
||||
} else {
|
||||
set_property enabled false $CLK1_PHASE
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLK1_PHASE { PARAM_VALUE.CLK1_PHASE } {
|
||||
# Procedure called to validate CLK1_PHASE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLKIN2_PERIOD { PARAM_VALUE.CLKIN2_PERIOD PARAM_VALUE.ENABLE_CLKIN2 } {
|
||||
# Procedure called to update CLKIN2_PERIOD when any of the dependent parameters in the arguments change
|
||||
|
||||
set CLKIN2_PERIOD ${PARAM_VALUE.CLKIN2_PERIOD}
|
||||
set ENABLE_CLKIN2 ${PARAM_VALUE.ENABLE_CLKIN2}
|
||||
set values(ENABLE_CLKIN2) [get_property value $ENABLE_CLKIN2]
|
||||
if { [gen_USERPARAMETER_CLKIN2_PERIOD_ENABLEMENT $values(ENABLE_CLKIN2)] } {
|
||||
set_property enabled true $CLKIN2_PERIOD
|
||||
} else {
|
||||
set_property enabled false $CLKIN2_PERIOD
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLKIN2_PERIOD { PARAM_VALUE.CLKIN2_PERIOD } {
|
||||
# Procedure called to validate CLKIN2_PERIOD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLK0_DIV { PARAM_VALUE.CLK0_DIV } {
|
||||
# Procedure called to update CLK0_DIV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLK0_DIV { PARAM_VALUE.CLK0_DIV } {
|
||||
# Procedure called to validate CLK0_DIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLK0_PHASE { PARAM_VALUE.CLK0_PHASE } {
|
||||
# Procedure called to update CLK0_PHASE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLK0_PHASE { PARAM_VALUE.CLK0_PHASE } {
|
||||
# Procedure called to validate CLK0_PHASE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLKIN_PERIOD { PARAM_VALUE.CLKIN_PERIOD } {
|
||||
# Procedure called to update CLKIN_PERIOD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLKIN_PERIOD { PARAM_VALUE.CLKIN_PERIOD } {
|
||||
# Procedure called to validate CLKIN_PERIOD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLKSEL_EN { PARAM_VALUE.CLKSEL_EN } {
|
||||
# Procedure called to update CLKSEL_EN when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLKSEL_EN { PARAM_VALUE.CLKSEL_EN } {
|
||||
# Procedure called to validate CLKSEL_EN
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ENABLE_CLKIN2 { PARAM_VALUE.ENABLE_CLKIN2 } {
|
||||
# Procedure called to update ENABLE_CLKIN2 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ENABLE_CLKIN2 { PARAM_VALUE.ENABLE_CLKIN2 } {
|
||||
# Procedure called to validate ENABLE_CLKIN2
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ENABLE_CLKOUT1 { PARAM_VALUE.ENABLE_CLKOUT1 } {
|
||||
# Procedure called to update ENABLE_CLKOUT1 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ENABLE_CLKOUT1 { PARAM_VALUE.ENABLE_CLKOUT1 } {
|
||||
# Procedure called to validate ENABLE_CLKOUT1
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_VOLTAGE { PARAM_VALUE.FPGA_VOLTAGE } {
|
||||
# Procedure called to update FPGA_VOLTAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_VOLTAGE { PARAM_VALUE.FPGA_VOLTAGE } {
|
||||
# Procedure called to validate FPGA_VOLTAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.VCO_DIV { PARAM_VALUE.VCO_DIV } {
|
||||
# Procedure called to update VCO_DIV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.VCO_DIV { PARAM_VALUE.VCO_DIV } {
|
||||
# Procedure called to validate VCO_DIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.VCO_MUL { PARAM_VALUE.VCO_MUL } {
|
||||
# Procedure called to update VCO_MUL when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.VCO_MUL { PARAM_VALUE.VCO_MUL } {
|
||||
# Procedure called to validate VCO_MUL
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_VOLTAGE { MODELPARAM_VALUE.FPGA_VOLTAGE PARAM_VALUE.FPGA_VOLTAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_VOLTAGE}] ${MODELPARAM_VALUE.FPGA_VOLTAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLKSEL_EN { MODELPARAM_VALUE.CLKSEL_EN PARAM_VALUE.CLKSEL_EN } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLKSEL_EN}] ${MODELPARAM_VALUE.CLKSEL_EN}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLKIN_PERIOD { MODELPARAM_VALUE.CLKIN_PERIOD PARAM_VALUE.CLKIN_PERIOD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLKIN_PERIOD}] ${MODELPARAM_VALUE.CLKIN_PERIOD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLKIN2_PERIOD { MODELPARAM_VALUE.CLKIN2_PERIOD PARAM_VALUE.CLKIN2_PERIOD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLKIN2_PERIOD}] ${MODELPARAM_VALUE.CLKIN2_PERIOD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.VCO_DIV { MODELPARAM_VALUE.VCO_DIV PARAM_VALUE.VCO_DIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.VCO_DIV}] ${MODELPARAM_VALUE.VCO_DIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.VCO_MUL { MODELPARAM_VALUE.VCO_MUL PARAM_VALUE.VCO_MUL } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.VCO_MUL}] ${MODELPARAM_VALUE.VCO_MUL}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLK0_DIV { MODELPARAM_VALUE.CLK0_DIV PARAM_VALUE.CLK0_DIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLK0_DIV}] ${MODELPARAM_VALUE.CLK0_DIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLK0_PHASE { MODELPARAM_VALUE.CLK0_PHASE PARAM_VALUE.CLK0_PHASE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLK0_PHASE}] ${MODELPARAM_VALUE.CLK0_PHASE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLK1_DIV { MODELPARAM_VALUE.CLK1_DIV PARAM_VALUE.CLK1_DIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLK1_DIV}] ${MODELPARAM_VALUE.CLK1_DIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLK1_PHASE { MODELPARAM_VALUE.CLK1_PHASE PARAM_VALUE.CLK1_PHASE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLK1_PHASE}] ${MODELPARAM_VALUE.CLK1_PHASE}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user