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## ***************************************************************************
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## ***************************************************************************
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## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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##
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## In this HDL repository, there are many different and unique modules, consisting
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## of various HDL (Verilog or VHDL) components. The individual modules are
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## developed independently, and may be accompanied by separate and unique license
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## terms.
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##
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## The user should read each of these license terms, and understand the
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## freedoms and responsibilities that he or she has by using this source/core.
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##
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## This core is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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## A PARTICULAR PURPOSE.
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##
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## Redistribution and use of source or resulting binaries, with or without modification
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## of this file, are permitted under one of the following two license terms:
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##
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## 1. The GNU General Public License version 2 as published by the
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## Free Software Foundation, which can be found in the top level directory
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## of this repository (LICENSE_GPL2), and also online at:
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## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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##
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## OR
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##
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## 2. An ADI specific BSD license, which can be found in the top level directory
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## of this repository (LICENSE_ADIBSD), and also on-line at:
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## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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## This will allow to generate bit files and not release the source code,
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## as long as it attaches to an ADI device.
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##
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## ***************************************************************************
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## ***************************************************************************
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proc init {cellpath otherInfo} {
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set ip [get_bd_cells $cellpath]
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bd::mark_propagate_override $ip \
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"CLKIN_PERIOD \
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CLKIN2_PERIOD \
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FPGA_VOLTAGE"
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bd::mark_propagate_only $ip \
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"FPGA_TECHNOLOGY \
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FPGA_FAMILY \
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SPEED_GRADE \
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DEV_PACKAGE \
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FPGA_VOLTAGE"
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adi_auto_assign_device_spec $cellpath
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}
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proc axi_clkgen_get_infer_period {ip param clk_name} {
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set param_src [get_property "CONFIG.$param.VALUE_SRC" $ip]
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if {[string equal $param_src "USER"]} {
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return;
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}
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set clk [get_bd_pins "$ip/$clk_name"]
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set clk_freq [get_property CONFIG.FREQ_HZ $clk]
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if {$clk_freq != {}} {
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set clk_period [expr 1000000000.0 / $clk_freq]
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set_property "CONFIG.$param" [format "%.6f" $clk_period] $ip
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}
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}
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proc adi_auto_assign_device_spec {cellpath} {
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set ip [get_bd_cells $cellpath]
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set ip_param_list [list_property $ip]
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set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
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set parent_dir "../"
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for {set x 1} {$x<=4} {incr x} {
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set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
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if { [file exists $linkname] } {
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source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
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break
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}
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append parent_dir "../"
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}
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# Find predefindes auto assignable parameters
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foreach i $auto_set_param_list {
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if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
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set val [adi_device_spec $cellpath $i]
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set_property CONFIG.$i $val $ip
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}
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}
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# Find predefindes auto assignable/overwritable parameters
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foreach i $auto_set_param_list_overwritable {
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if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
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set val [adi_device_spec $cellpath $i]
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set_property CONFIG.$i $val $ip
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}
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}
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}
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proc propagate {cellpath otherinfo} {
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set ip [get_bd_cells $cellpath]
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set vco_mul [get_property CONFIG.VCO_MUL $ip]
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set vco_div [get_property CONFIG.VCO_DIV $ip]
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set clk0_div [get_property CONFIG.CLK0_DIV $ip]
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set clk1_div [get_property CONFIG.CLK1_DIV $ip]
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if {$vco_mul == {} || $vco_mul < 1} {
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set vco_mul 1
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}
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if {$vco_div == {} || $vco_div < 1} {
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set vco_div 1
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}
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if {$clk0_div == {} || $clk0_div < 1} {
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set clk0_div 1
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}
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if {$clk1_div == {} || $clk0_div < 1} {
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set clk1_div 1
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}
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set clk [get_bd_pins "$ip/clk"]
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set clk_freq [get_property CONFIG.FREQ_HZ $clk]
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if {[get_property "CONFIG.ENABLE_CLKIN2" $ip] == "true"} {
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set clk2 [get_bd_pins "$ip/clk"]
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set clk2_freq [get_property CONFIG.FREQ_HZ $clk2]
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# Use the larger of the two
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if {$clk_freq == {} || $clk2_freq > $clk_freq} {
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set clk_freq $clk2_freq
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}
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}
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if {$clk_freq != {}} {
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set clk0_out [get_bd_pins "$ip/clk_0"]
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set clk0_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk0_div)]
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set_property CONFIG.FREQ_HZ $clk0_out_freq $clk0_out
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if {[get_property "CONFIG.ENABLE_CLKOUT1" $ip] == "true"} {
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set clk1_out [get_bd_pins "$ip/clk_1"]
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set clk1_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk1_div)]
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set_property CONFIG.FREQ_HZ $clk1_out_freq $clk1_out
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}
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}
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}
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proc post_propagate {cellpath otherinfo} {
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set ip [get_bd_cells $cellpath]
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axi_clkgen_get_infer_period $ip CLKIN_PERIOD clk
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if {[get_property "CONFIG.ENABLE_CLKIN2" $ip] == "true"} {
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axi_clkgen_get_infer_period $ip CLKIN2_PERIOD clk2
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}
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}
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