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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_2d_transfer #(
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parameter DMA_AXI_ADDR_WIDTH = 32,
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parameter DMA_LENGTH_WIDTH = 24,
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parameter BYTES_PER_BURST_WIDTH = 7,
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parameter BYTES_PER_BEAT_WIDTH_SRC = 3,
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parameter BYTES_PER_BEAT_WIDTH_DEST = 3)(
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input req_aclk,
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input req_aresetn,
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input req_valid,
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output reg req_ready,
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input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
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input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
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input [DMA_LENGTH_WIDTH-1:0] req_x_length,
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input [DMA_LENGTH_WIDTH-1:0] req_y_length,
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input [DMA_LENGTH_WIDTH-1:0] req_dest_stride,
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input [DMA_LENGTH_WIDTH-1:0] req_src_stride,
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input req_sync_transfer_start,
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input req_last,
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output reg req_eot,
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output reg [BYTES_PER_BURST_WIDTH-1:0] req_measured_burst_length,
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output reg req_response_partial,
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output reg req_response_valid,
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input req_response_ready,
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input out_abort_req,
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output reg out_req_valid,
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input out_req_ready,
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output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
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output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
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output [DMA_LENGTH_WIDTH-1:0] out_req_length,
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output reg out_req_sync_transfer_start,
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output out_req_last,
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input out_eot,
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input [BYTES_PER_BURST_WIDTH-1:0] out_measured_burst_length,
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input out_response_partial,
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input out_response_valid,
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output reg out_response_ready = 1'b1
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);
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reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dest_address = 'h00;
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reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] src_address = 'h00;
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reg [DMA_LENGTH_WIDTH-1:0] x_length = 'h00;
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reg [DMA_LENGTH_WIDTH-1:0] y_length = 'h00;
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reg [DMA_LENGTH_WIDTH-1:0] dest_stride = 'h0;
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reg [DMA_LENGTH_WIDTH-1:0] src_stride = 'h00;
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reg gen_last = 'h0;
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reg [1:0] req_id = 'h00;
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reg [1:0] eot_id = 'h00;
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reg [3:0] last_req = 'h00;
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wire out_last;
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assign out_req_dest_address = dest_address;
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assign out_req_src_address = src_address;
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assign out_req_length = x_length;
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assign out_last = y_length == 'h00;
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always @(posedge req_aclk) begin
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if (req_aresetn == 1'b0) begin
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req_id <= 2'b0;
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eot_id <= 2'b0;
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req_eot <= 1'b0;
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end else begin
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if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
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req_id <= req_id + 1'b1;
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end
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if (out_eot == 1'b1 && out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
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eot_id <= eot_id + 1'b1;
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req_eot <= last_req[eot_id];
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end else begin
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req_eot <= 1'b0;
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end
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end
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end
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always @(posedge req_aclk) begin
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if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
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last_req[req_id] <= out_last;
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end
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end
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always @(posedge req_aclk) begin
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if (out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
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req_measured_burst_length <= out_measured_burst_length;
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req_response_partial <= out_response_partial;
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end
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end
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always @(posedge req_aclk) begin
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if (out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
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req_response_valid <= 1'b1;
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end else if (req_response_ready == 1'b1) begin
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req_response_valid <= 1'b0;
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end
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end
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always @(posedge req_aclk) begin
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if (req_aresetn == 1'b0) begin
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out_response_ready <= 1'b1;
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end else if (out_response_ready == 1'b1) begin
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out_response_ready <= ~out_response_valid;
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end else if (req_response_ready == 1'b1) begin
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out_response_ready <= 1'b1;
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end
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end
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always @(posedge req_aclk) begin
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if (req_ready == 1'b1 && req_valid == 1'b1) begin
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dest_address <= req_dest_address;
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src_address <= req_src_address;
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x_length <= req_x_length;
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y_length <= req_y_length;
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dest_stride <= req_dest_stride;
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src_stride <= req_src_stride;
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out_req_sync_transfer_start <= req_sync_transfer_start;
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gen_last <= req_last;
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end else if (out_abort_req == 1'b1) begin
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y_length <= 0;
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end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
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dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
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src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
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y_length <= y_length - 1'b1;
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out_req_sync_transfer_start <= 1'b0;
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end
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end
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always @(posedge req_aclk) begin
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if (req_aresetn == 1'b0) begin
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req_ready <= 1'b1;
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out_req_valid <= 1'b0;
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end else begin
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if (req_ready == 1'b1 && req_valid == 1'b1) begin
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req_ready <= 1'b0;
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out_req_valid <= 1'b1;
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end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1 &&
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out_last == 1'b1) begin
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out_req_valid <= 1'b0;
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req_ready <= 1'b1;
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end
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end
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end
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assign out_req_last = out_last & gen_last;
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endmodule
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