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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_hdmi_rx #(
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parameter ID = 0,
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parameter IO_INTERFACE = 1) (
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// hdmi interface
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input hdmi_rx_clk,
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input [15:0] hdmi_rx_data,
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// dma interface
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output hdmi_clk,
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output hdmi_dma_sof,
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output hdmi_dma_de,
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output [63:0] hdmi_dma_data,
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input hdmi_dma_ovf,
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input hdmi_dma_unf,
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// processor interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot);
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// internal signals
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_s;
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wire up_rack_s;
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wire hdmi_edge_sel_s;
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wire hdmi_bgr_s;
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wire hdmi_packed_s;
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wire hdmi_csc_bypass_s;
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wire [15:0] hdmi_vs_count_s;
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wire [15:0] hdmi_hs_count_s;
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wire hdmi_tpm_oos_s;
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wire hdmi_vs_oos_s;
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wire hdmi_hs_oos_s;
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wire hdmi_vs_mismatch_s;
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wire hdmi_hs_mismatch_s;
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wire [15:0] hdmi_vs_s;
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wire [15:0] hdmi_hs_s;
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wire hdmi_rst;
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wire [15:0] hdmi_data;
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// signal name changes
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assign hdmi_clk = hdmi_rx_clk;
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assign hdmi_data = hdmi_rx_data;
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assign up_rstn = s_axi_aresetn;
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assign up_clk = s_axi_aclk;
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// axi interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// processor interface
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up_hdmi_rx i_up (
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.hdmi_clk (hdmi_clk),
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.hdmi_rst (hdmi_rst),
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.hdmi_edge_sel (hdmi_edge_sel_s),
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.hdmi_bgr (hdmi_bgr_s),
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.hdmi_packed (hdmi_packed_s),
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.hdmi_csc_bypass (hdmi_csc_bypass_s),
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.hdmi_vs_count (hdmi_vs_count_s),
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.hdmi_hs_count (hdmi_hs_count_s),
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.hdmi_dma_ovf (hdmi_dma_ovf),
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.hdmi_dma_unf (hdmi_dma_unf),
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.hdmi_tpm_oos (hdmi_tpm_oos_s),
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.hdmi_vs_oos (hdmi_vs_oos_s),
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.hdmi_hs_oos (hdmi_hs_oos_s),
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.hdmi_vs_mismatch (hdmi_vs_mismatch_s),
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.hdmi_hs_mismatch (hdmi_hs_mismatch_s),
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.hdmi_vs (hdmi_vs_s),
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.hdmi_hs (hdmi_hs_s),
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.hdmi_clk_ratio (32'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// hdmi interface
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axi_hdmi_rx_core i_rx_core (
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.hdmi_clk (hdmi_clk),
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.hdmi_rst (hdmi_rst),
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.hdmi_data (hdmi_data),
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.hdmi_edge_sel (hdmi_edge_sel_s),
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.hdmi_bgr (hdmi_bgr_s),
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.hdmi_packed (hdmi_packed_s),
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.hdmi_csc_bypass (hdmi_csc_bypass_s),
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.hdmi_vs_count (hdmi_vs_count_s),
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.hdmi_hs_count (hdmi_hs_count_s),
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.hdmi_tpm_oos (hdmi_tpm_oos_s),
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.hdmi_vs_oos (hdmi_vs_oos_s),
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.hdmi_hs_oos (hdmi_hs_oos_s),
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.hdmi_vs_mismatch (hdmi_vs_mismatch_s),
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.hdmi_hs_mismatch (hdmi_hs_mismatch_s),
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.hdmi_vs (hdmi_vs_s),
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.hdmi_hs (hdmi_hs_s),
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.hdmi_dma_sof (hdmi_dma_sof),
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.hdmi_dma_de (hdmi_dma_de),
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.hdmi_dma_data (hdmi_dma_data));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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